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| author | Peter Hinch <peter@hinch.me.uk> | 2016-01-11 06:48:35 +0000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2016-01-13 21:53:26 +0000 |
| commit | c13b2f2d0040cdf38ea3178717480d07f02c5245 (patch) | |
| tree | a6d17950ffc505f19f565f7f0b8313dc2246cc60 /docs/reference/asm_thumb2_misc.rst | |
| parent | 22d85ec5be77e7ee6b703221d51113f7f21a995b (diff) | |
docs: Several minor changes: network, pyb, ADCAll and inline asm.
Diffstat (limited to 'docs/reference/asm_thumb2_misc.rst')
| -rw-r--r-- | docs/reference/asm_thumb2_misc.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/reference/asm_thumb2_misc.rst b/docs/reference/asm_thumb2_misc.rst index eb96f4877..ca3f878cc 100644 --- a/docs/reference/asm_thumb2_misc.rst +++ b/docs/reference/asm_thumb2_misc.rst @@ -5,6 +5,9 @@ Miscellaneous instructions * wfi() Suspend execution in a low power state until an interrupt occurs. * cpsid(flags) set the Priority Mask Register - disable interrupts. * cpsie(flags) clear the Priority Mask Register - enable interrupts. +* mrs(Rd, special_reg) ``Rd = special_reg`` copy a special register to a general register. The special register + may be IPSR (Interrupt Status Register) or BASEPRI (Base Priority Register). The IPSR provides a means of determining + the exception number of an interrupt being processed. It contains zero if no interrupt is being processed. Currently the ``cpsie()`` and ``cpsid()`` functions are partially implemented. They require but ignore the flags argument and serve as a means of enabling and disabling interrupts. |