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| author | Dan Halbert <halbert@halwitz.org> | 2018-10-03 13:31:48 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-03 13:31:48 -0400 |
| commit | 6049776b2665c2bc7d490a0630cf514a13aecf99 (patch) | |
| tree | e0a25a07a459a1b84610c4362fc5072a43b89da4 /locale/circuitpython.pot | |
| parent | a47eaa521b39f90667da17a4ec7a1c256dec2ab5 (diff) | |
| parent | 86ae707b0871f3b5f7766bfcd920635b337a6b29 (diff) | |
Merge branch 'master' into nrf52_uart_io
Diffstat (limited to 'locale/circuitpython.pot')
| -rw-r--r-- | locale/circuitpython.pot | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index ca8d55dcb..232ad7c46 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -2007,19 +2007,19 @@ msgstr "" msgid "Buffer must be at least length 1" msgstr "" -#: shared-bindings/bitbangio/SPI.c:151 shared-bindings/busio/SPI.c:168 +#: shared-bindings/bitbangio/SPI.c:151 shared-bindings/busio/SPI.c:175 msgid "Invalid polarity" msgstr "" -#: shared-bindings/bitbangio/SPI.c:155 shared-bindings/busio/SPI.c:172 +#: shared-bindings/bitbangio/SPI.c:155 shared-bindings/busio/SPI.c:179 msgid "Invalid phase" msgstr "" -#: shared-bindings/bitbangio/SPI.c:159 shared-bindings/busio/SPI.c:176 +#: shared-bindings/bitbangio/SPI.c:159 shared-bindings/busio/SPI.c:183 msgid "Invalid number of bits" msgstr "" -#: shared-bindings/bitbangio/SPI.c:284 shared-bindings/busio/SPI.c:341 +#: shared-bindings/bitbangio/SPI.c:284 shared-bindings/busio/SPI.c:348 msgid "buffer slices must be of equal length" msgstr "" |