Merge pull request #4446 from tannewt/rp2040_flash

Switch RP2040 flash settings to nvm.toml

29 files changed, 396 insertions, 56 deletions

diff --git a/ports/raspberrypi/Makefile b/ports/raspberrypi/Makefile
index 2c1a13a8b..30648ba8e 100644
--- a/ports/raspberrypi/Makefile
+++ b/ports/raspberrypi/Makefile
@@ -106,7 +106,7 @@ INC += -I. \
        -I$(BUILD)
 
 # Pico specific configuration
-CFLAGS += -DPICO_ON_DEVICE=1 -DPICO_NO_BINARY_INFO=0 -DPICO_TIME_DEFAULT_ALARM_POOL_DISABLED=1 -DPICO_DIVIDER_CALL_IDIV0=0 -DPICO_DIVIDER_CALL_LDIV0=0 -DPICO_DIVIDER_HARDWARE=1 -DPICO_DOUBLE_ROM=1 -DPICO_FLOAT_ROM=1 -DPICO_MULTICORE=1 -DPICO_BITS_IN_RAM=0 -DPICO_DIVIDER_IN_RAM=0 -DPICO_DOUBLE_PROPAGATE_NANS=0 -DPICO_DOUBLE_IN_RAM=0 -DPICO_MEM_IN_RAM=0 -DPICO_FLOAT_IN_RAM=0 -DPICO_FLOAT_PROPAGATE_NANS=1 -DPICO_NO_FLASH=0 -DPICO_COPY_TO_RAM=0 -DPICO_DISABLE_SHARED_IRQ_HANDLERS=0 -DPICO_NO_BI_BOOTSEL_VIA_DOUBLE_RESET=0
+CFLAGS += -DRASPBERRYPI -DPICO_ON_DEVICE=1 -DPICO_NO_BINARY_INFO=0 -DPICO_TIME_DEFAULT_ALARM_POOL_DISABLED=1 -DPICO_DIVIDER_CALL_IDIV0=0 -DPICO_DIVIDER_CALL_LDIV0=0 -DPICO_DIVIDER_HARDWARE=1 -DPICO_DOUBLE_ROM=1 -DPICO_FLOAT_ROM=1 -DPICO_MULTICORE=1 -DPICO_BITS_IN_RAM=0 -DPICO_DIVIDER_IN_RAM=0 -DPICO_DOUBLE_PROPAGATE_NANS=0 -DPICO_DOUBLE_IN_RAM=0 -DPICO_MEM_IN_RAM=0 -DPICO_FLOAT_IN_RAM=0 -DPICO_FLOAT_PROPAGATE_NANS=1 -DPICO_NO_FLASH=0 -DPICO_COPY_TO_RAM=0 -DPICO_DISABLE_SHARED_IRQ_HANDLERS=0 -DPICO_NO_BI_BOOTSEL_VIA_DOUBLE_RESET=0
 OPTIMIZATION_FLAGS ?= -O3
 # TinyUSB defines
 CFLAGS += -DTUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX=1 -DCFG_TUSB_MCU=OPT_MCU_RP2040 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024
@@ -169,7 +169,7 @@ SRC_SDK := \
 	src/rp2_common/hardware_irq/irq.c \
 	src/rp2_common/hardware_pio/pio.c \
 	src/rp2_common/hardware_pll/pll.c \
-  src/rp2_common/hardware_rtc/rtc.c \
+	src/rp2_common/hardware_rtc/rtc.c \
 	src/rp2_common/hardware_spi/spi.c \
 	src/rp2_common/hardware_sync/sync.c \
 	src/rp2_common/hardware_timer/timer.c \
@@ -233,7 +233,6 @@ SRC_SHARED_MODULE_EXPANDED = $(addprefix shared-bindings/, $(SRC_SHARED_MODULE))
 SRC_COMMON_HAL_SHARED_MODULE_EXPANDED = $(sort $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED))
 
 SRC_S = supervisor/$(CHIP_FAMILY)_cpu.s
-BOOT2_S_UPPER ?= sdk/src/rp2_common/boot_stage2/boot2_generic_03h.S
 BOOT2_S_CFLAGS ?= -DPICO_FLASH_SPI_CLKDIV=4
 SRC_S_UPPER = sdk/src/rp2_common/hardware_divider/divider.S \
               sdk/src/rp2_common/hardware_irq/irq_handler_chain.S \
@@ -270,9 +269,15 @@ $(BUILD)/boot2.bin: $(BUILD)/boot2.elf
 	$(STEPECHO) "OBJCOPY $<"
 	$(Q)$(OBJCOPY) -O binary $< $@
 
-$(BUILD)/boot2.elf: $(BOOT2_S_UPPER) | $(BUILD)/
+
+$(BUILD)/stage2.c: stage2.c.jinja gen_stage2.py | $(BUILD)/
+	$(STEPECHO) "GEN $<"
+	$(Q)$(PYTHON3) gen_stage2.py $< $@ $(EXTERNAL_FLASH_DEVICES)
+
+$(BUILD)/boot2.elf: $(BUILD)/stage2.c
 	$(STEPECHO) "BOOT $<"
-	$(Q)$(CC) $(CFLAGS) $(BOOT2_S_CFLAGS) -Isdk/src/rp2_common/boot_stage2/asminclude --specs=nosys.specs -nostartfiles -Wl,-T,sdk/src/rp2_common/boot_stage2/boot_stage2.ld -o $@ $<
+	$(Q)$(CC) $(CFLAGS) $(BOOT2_S_CFLAGS) -Os -ggdb3 -I. -fPIC --specs=nosys.specs -nostartfiles -Wl,-T,boot_stage2.ld  -Wl,-Map=$@.map -o $@ $<
+	$(Q)$(SIZE) $@
 
 SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
 
@@ -285,7 +290,7 @@ $(BUILD)/firmware.elf: $(OBJ) link.ld
 
 $(BUILD)/firmware.bin: $(BUILD)/firmware.elf
 	$(STEPECHO) "Create $@"
-	$(Q)$(OBJCOPY) -O binary $^ $@
+	$(Q)$(OBJCOPY) -O binary -R .dtcm_bss $^ $@
 
 $(BUILD)/firmware.uf2: $(BUILD)/firmware.bin
 	$(STEPECHO) "Create $@"
diff --git a/ports/raspberrypi/boards/adafruit_feather_rp2040/mpconfigboard.h b/ports/raspberrypi/boards/adafruit_feather_rp2040/mpconfigboard.h
index a594e6a55..fba7dc3b1 100644
--- a/ports/raspberrypi/boards/adafruit_feather_rp2040/mpconfigboard.h
+++ b/ports/raspberrypi/boards/adafruit_feather_rp2040/mpconfigboard.h
@@ -12,6 +12,3 @@
 
 #define DEFAULT_UART_BUS_RX (&pin_GPIO1)
 #define DEFAULT_UART_BUS_TX (&pin_GPIO0)
-
-// Flash chip is GD25Q64 connected over QSPI
-#define TOTAL_FLASH_SIZE (8 * 1024 * 1024)
diff --git a/ports/raspberrypi/boards/adafruit_feather_rp2040/mpconfigboard.mk b/ports/raspberrypi/boards/adafruit_feather_rp2040/mpconfigboard.mk
index f4106b94a..84c4adabb 100644
--- a/ports/raspberrypi/boards/adafruit_feather_rp2040/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/adafruit_feather_rp2040/mpconfigboard.mk
@@ -6,4 +6,4 @@ USB_MANUFACTURER = "Adafruit"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "GD25Q64C"
diff --git a/ports/raspberrypi/boards/adafruit_itsybitsy_rp2040/mpconfigboard.h b/ports/raspberrypi/boards/adafruit_itsybitsy_rp2040/mpconfigboard.h
index 8e36eb198..dad4e2eae 100644
--- a/ports/raspberrypi/boards/adafruit_itsybitsy_rp2040/mpconfigboard.h
+++ b/ports/raspberrypi/boards/adafruit_itsybitsy_rp2040/mpconfigboard.h
@@ -12,6 +12,3 @@
 
 #define DEFAULT_UART_BUS_RX (&pin_GPIO1)
 #define DEFAULT_UART_BUS_TX (&pin_GPIO0)
-
-// Flash chip is W25Q64 connected over QSPI
-#define TOTAL_FLASH_SIZE (8 * 1024 * 1024)
diff --git a/ports/raspberrypi/boards/adafruit_itsybitsy_rp2040/mpconfigboard.mk b/ports/raspberrypi/boards/adafruit_itsybitsy_rp2040/mpconfigboard.mk
index 9d1d15141..965acff27 100644
--- a/ports/raspberrypi/boards/adafruit_itsybitsy_rp2040/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/adafruit_itsybitsy_rp2040/mpconfigboard.mk
@@ -6,4 +6,4 @@ USB_MANUFACTURER = "Adafruit"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "W25Q64JVxQ"
diff --git a/ports/raspberrypi/boards/qtpy_rp2040/board.c b/ports/raspberrypi/boards/adafruit_qtpy_rp2040/board.c
index 332145ab8..332145ab8 100644
--- a/ports/raspberrypi/boards/qtpy_rp2040/board.c
+++ b/ports/raspberrypi/boards/adafruit_qtpy_rp2040/board.c
diff --git a/ports/raspberrypi/boards/qtpy_rp2040/mpconfigboard.h b/ports/raspberrypi/boards/adafruit_qtpy_rp2040/mpconfigboard.h
index 0ba490e81..6b84afb64 100644
--- a/ports/raspberrypi/boards/qtpy_rp2040/mpconfigboard.h
+++ b/ports/raspberrypi/boards/adafruit_qtpy_rp2040/mpconfigboard.h
@@ -12,6 +12,3 @@
 
 #define DEFAULT_UART_BUS_RX (&pin_GPIO5)
 #define DEFAULT_UART_BUS_TX (&pin_GPIO20)
-
-// Flash chip is GD25Q64 connected over QSPI
-#define TOTAL_FLASH_SIZE (8 * 1024 * 1024)
diff --git a/ports/raspberrypi/boards/qtpy_rp2040/mpconfigboard.mk b/ports/raspberrypi/boards/adafruit_qtpy_rp2040/mpconfigboard.mk
index 5e454e312..8258f8783 100644
--- a/ports/raspberrypi/boards/qtpy_rp2040/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/adafruit_qtpy_rp2040/mpconfigboard.mk
@@ -6,4 +6,4 @@ USB_MANUFACTURER = "Adafruit"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "W25Q64JVxQ"
diff --git a/ports/raspberrypi/boards/qtpy_rp2040/pins.c b/ports/raspberrypi/boards/adafruit_qtpy_rp2040/pins.c
index 150aa374e..150aa374e 100644
--- a/ports/raspberrypi/boards/qtpy_rp2040/pins.c
+++ b/ports/raspberrypi/boards/adafruit_qtpy_rp2040/pins.c
diff --git a/ports/raspberrypi/boards/pimoroni_keybow2040/mpconfigboard.h b/ports/raspberrypi/boards/pimoroni_keybow2040/mpconfigboard.h
index 234be27c2..ecc127db6 100644
--- a/ports/raspberrypi/boards/pimoroni_keybow2040/mpconfigboard.h
+++ b/ports/raspberrypi/boards/pimoroni_keybow2040/mpconfigboard.h
@@ -28,8 +28,6 @@
 #define DEFAULT_UART_BUS_RX (&pin_GPIO1)
 #define DEFAULT_UART_BUS_TX (&pin_GPIO0)
 
-#define TOTAL_FLASH_SIZE (2 * 1024 * 1024)
-
 // These pins are unconnected
 #define IGNORE_PIN_GPIO2    1
 #define IGNORE_PIN_GPIO22   1
diff --git a/ports/raspberrypi/boards/pimoroni_keybow2040/mpconfigboard.mk b/ports/raspberrypi/boards/pimoroni_keybow2040/mpconfigboard.mk
index cf7429431..ad343c4e0 100644
--- a/ports/raspberrypi/boards/pimoroni_keybow2040/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/pimoroni_keybow2040/mpconfigboard.mk
@@ -6,6 +6,6 @@ USB_MANUFACTURER = "Pimoroni"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "W25Q16JVxQ"
 
 CIRCUITPY__EVE = 1
diff --git a/ports/raspberrypi/boards/pimoroni_picosystem/mpconfigboard.h b/ports/raspberrypi/boards/pimoroni_picosystem/mpconfigboard.h
index a1395f17d..8a61d6a76 100644
--- a/ports/raspberrypi/boards/pimoroni_picosystem/mpconfigboard.h
+++ b/ports/raspberrypi/boards/pimoroni_picosystem/mpconfigboard.h
@@ -38,8 +38,6 @@
 #define DEFAULT_UART_BUS_RX (&pin_GPIO1)
 #define DEFAULT_UART_BUS_TX (&pin_GPIO0)
 
-#define TOTAL_FLASH_SIZE (16 * 1024 * 1024)
-
 // These pins are unconnected
 #define IGNORE_PIN_GPIO3    1
 #define IGNORE_PIN_GPIO10   1
diff --git a/ports/raspberrypi/boards/pimoroni_picosystem/mpconfigboard.mk b/ports/raspberrypi/boards/pimoroni_picosystem/mpconfigboard.mk
index c9d22549b..f00fb64cc 100644
--- a/ports/raspberrypi/boards/pimoroni_picosystem/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/pimoroni_picosystem/mpconfigboard.mk
@@ -6,6 +6,6 @@ USB_MANUFACTURER = "Pimoroni"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "W25Q128JVxQ"
 
 CIRCUITPY__EVE = 1
diff --git a/ports/raspberrypi/boards/pimoroni_tiny2040/mpconfigboard.h b/ports/raspberrypi/boards/pimoroni_tiny2040/mpconfigboard.h
index 965dd0e04..8f188959c 100644
--- a/ports/raspberrypi/boards/pimoroni_tiny2040/mpconfigboard.h
+++ b/ports/raspberrypi/boards/pimoroni_tiny2040/mpconfigboard.h
@@ -7,8 +7,6 @@
 
 #define MICROPY_HW_USER_SW (&pin_GPIO23)
 
-#define TOTAL_FLASH_SIZE (8 * 1024 * 1024)
-
 // These pins are unconnected
 #define IGNORE_PIN_GPIO8    1
 #define IGNORE_PIN_GPIO9    1
diff --git a/ports/raspberrypi/boards/pimoroni_tiny2040/mpconfigboard.mk b/ports/raspberrypi/boards/pimoroni_tiny2040/mpconfigboard.mk
index 75fe36a29..748778223 100644
--- a/ports/raspberrypi/boards/pimoroni_tiny2040/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/pimoroni_tiny2040/mpconfigboard.mk
@@ -6,6 +6,6 @@ USB_MANUFACTURER = "Pimoroni"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "W25Q64JVxQ"
 
 CIRCUITPY__EVE = 1
diff --git a/ports/raspberrypi/boards/raspberry_pi_pico/mpconfigboard.h b/ports/raspberrypi/boards/raspberry_pi_pico/mpconfigboard.h
index a506fec49..efb2fc340 100644
--- a/ports/raspberrypi/boards/raspberry_pi_pico/mpconfigboard.h
+++ b/ports/raspberrypi/boards/raspberry_pi_pico/mpconfigboard.h
@@ -1,18 +1,2 @@
-// LEDs
-// #define MICROPY_HW_LED_STATUS   (&pin_PA17)
-
 #define MICROPY_HW_BOARD_NAME "Raspberry Pi Pico"
 #define MICROPY_HW_MCU_NAME "rp2040"
-
-// #define DEFAULT_I2C_BUS_SCL (&pin_PA23)
-// #define DEFAULT_I2C_BUS_SDA (&pin_PA22)
-
-// #define DEFAULT_SPI_BUS_SCK (&pin_PB11)
-// #define DEFAULT_SPI_BUS_MOSI (&pin_PB10)
-// #define DEFAULT_SPI_BUS_MISO (&pin_PA12)
-
-// #define DEFAULT_UART_BUS_RX (&pin_PA11)
-// #define DEFAULT_UART_BUS_TX (&pin_PA10)
-
-// Flash chip is W25Q16JVUXIQ connected over QSPI
-#define TOTAL_FLASH_SIZE (2 * 1024 * 1024)
diff --git a/ports/raspberrypi/boards/raspberry_pi_pico/mpconfigboard.mk b/ports/raspberrypi/boards/raspberry_pi_pico/mpconfigboard.mk
index 8d6ca5330..608ca280d 100644
--- a/ports/raspberrypi/boards/raspberry_pi_pico/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/raspberry_pi_pico/mpconfigboard.mk
@@ -6,8 +6,6 @@ USB_MANUFACTURER = "Raspberry Pi"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "W25Q16JVxQ"
 
 CIRCUITPY__EVE = 1
-
-BOOT2_S_UPPER = sdk/src/rp2_common/boot_stage2/boot2_w25q080.S
diff --git a/ports/raspberrypi/boards/sparkfun_pro_micro_rp2040/mpconfigboard.h b/ports/raspberrypi/boards/sparkfun_pro_micro_rp2040/mpconfigboard.h
index 8ceab9caa..eb807097b 100644
--- a/ports/raspberrypi/boards/sparkfun_pro_micro_rp2040/mpconfigboard.h
+++ b/ports/raspberrypi/boards/sparkfun_pro_micro_rp2040/mpconfigboard.h
@@ -12,6 +12,3 @@
 
 #define DEFAULT_UART_BUS_RX (&pin_GPIO1)
 #define DEFAULT_UART_BUS_TX (&pin_GPIO0)
-
-// Flash chip is GD25Q128 connected over QSPI
-#define TOTAL_FLASH_SIZE (16 * 1024 * 1024)
diff --git a/ports/raspberrypi/boards/sparkfun_pro_micro_rp2040/mpconfigboard.mk b/ports/raspberrypi/boards/sparkfun_pro_micro_rp2040/mpconfigboard.mk
index 6f758cd8f..d02d14267 100644
--- a/ports/raspberrypi/boards/sparkfun_pro_micro_rp2040/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/sparkfun_pro_micro_rp2040/mpconfigboard.mk
@@ -6,4 +6,4 @@ USB_MANUFACTURER = "SparkFun"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "W25Q128JVxM"
diff --git a/ports/raspberrypi/boards/sparkfun_thing_plus_rp2040/mpconfigboard.h b/ports/raspberrypi/boards/sparkfun_thing_plus_rp2040/mpconfigboard.h
index 564e41a65..6c307ec89 100644
--- a/ports/raspberrypi/boards/sparkfun_thing_plus_rp2040/mpconfigboard.h
+++ b/ports/raspberrypi/boards/sparkfun_thing_plus_rp2040/mpconfigboard.h
@@ -12,6 +12,3 @@
 
 #define DEFAULT_UART_BUS_RX (&pin_GPIO1)
 #define DEFAULT_UART_BUS_TX (&pin_GPIO0)
-
-// Flash chip is GD25Q128 connected over QSPI
-#define TOTAL_FLASH_SIZE (16 * 1024 * 1024)
diff --git a/ports/raspberrypi/boards/sparkfun_thing_plus_rp2040/mpconfigboard.mk b/ports/raspberrypi/boards/sparkfun_thing_plus_rp2040/mpconfigboard.mk
index f7369ab37..101adbfa4 100644
--- a/ports/raspberrypi/boards/sparkfun_thing_plus_rp2040/mpconfigboard.mk
+++ b/ports/raspberrypi/boards/sparkfun_thing_plus_rp2040/mpconfigboard.mk
@@ -6,4 +6,4 @@ USB_MANUFACTURER = "SparkFun"
 CHIP_VARIANT = RP2040
 CHIP_FAMILY = rp2
 
-INTERNAL_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICES = "W25Q128JVxM"
diff --git a/ports/raspberrypi/boot_stage2.ld b/ports/raspberrypi/boot_stage2.ld
new file mode 100644
index 000000000..c29429062
--- /dev/null
+++ b/ports/raspberrypi/boot_stage2.ld
@@ -0,0 +1,13 @@
+MEMORY {
+    /* We are loaded to the top 256 bytes of SRAM, which is above the bootrom
+       stack. Note 4 bytes occupied by checksum. */
+    SRAM(rx) : ORIGIN = 0x20041f00, LENGTH = 252
+}
+
+SECTIONS {
+    . = ORIGIN(SRAM);
+    .text : {
+        *(.entry.*)
+        *(.text.*)
+    } >SRAM
+}
diff --git a/ports/raspberrypi/gen_stage2.py b/ports/raspberrypi/gen_stage2.py
new file mode 100644
index 000000000..4a6790518
--- /dev/null
+++ b/ports/raspberrypi/gen_stage2.py
@@ -0,0 +1,82 @@
+import sys
+import cascadetoml
+import pathlib
+import typer
+from jinja2 import Template
+
+
+def main(input_template: pathlib.Path, output_path: pathlib.Path, skus: str = typer.Argument("")):
+    if "," in skus:
+        skus = skus.split(",")
+    else:
+        skus = [skus]
+    skus = ['sku="{}"'.format(f.strip()) for f in skus]
+    flashes = cascadetoml.filter_toml(pathlib.Path("../../data/nvm.toml"), skus)
+
+    if len(skus) == 0:
+        print("Set EXTERNAL_FLASH_DEVICES in mpconfigboard.mk with all possible flash skus")
+        raise typer.Exit(code=1)
+
+    def all_have(nvms, key):
+        for nvm in nvms:
+            if not nvm.get(key, False):
+                return False
+        return True
+
+    def all_match(nvms, key, default=None):
+        shared_value = nvms[0].get(key, default)
+        for nvm in nvms:
+            this_value = nvm.get(key, default)
+            if this_value != shared_value:
+                print(
+                    "{}.{} = {} does not match {}".format(
+                        nvm["sku"], key, this_value, shared_value
+                    )
+                )
+                return None
+        return shared_value
+
+    quad_enable_status_byte = all_match(flashes["nvm"], "quad_enable_status_byte", None)
+    quad_enable_bit_mask = all_match(flashes["nvm"], "quad_enable_bit_mask")
+    continuous_status_write = all_have(flashes["nvm"], "01_continuous_status_write")
+    split_status_write = all_have(flashes["nvm"], "write_status_register_split")
+    e7_quad_word_read = all_have(flashes["nvm"], "e7_quad_word_read")
+
+    quad_ok = quad_enable_status_byte is not None and quad_enable_bit_mask is not None
+
+    max_clock_speed_mhz = min((x.get("max_clock_speed_mhz", 1000) for x in flashes["nvm"]))
+
+    # Check that we have a consistent way to set quad enable.
+    if continuous_status_write is None and split_status_write is None:
+        print("quad not ok", continuous_status_write, split_status_write)
+        quad_ok = False
+
+    clock_divider = 4
+
+    read_command = 0x03
+    wait_cycles = 0
+    if quad_ok:
+        if e7_quad_word_read:
+            read_command = 0xE7
+            wait_cycles = 2
+        else:
+            read_command = 0xEB
+            wait_cycles = 4
+
+    flash_settings = {
+        "quad_ok": quad_ok,
+        "quad_enable_status_byte": quad_enable_status_byte,
+        "quad_enable_bit_mask": quad_enable_bit_mask,
+        "split_status_write": split_status_write,
+        "clock_divider": clock_divider,
+        "read_command": read_command,
+        "wait_cycles": wait_cycles,
+    }
+
+    template = Template(input_template.read_text())
+
+    output_path.write_text(template.render(flash_settings))
+
+
+if __name__ == "__main__":
+    typer.run(main)
diff --git a/ports/raspberrypi/link.ld b/ports/raspberrypi/link.ld
index 653408d4e..62b1bd04b 100644
--- a/ports/raspberrypi/link.ld
+++ b/ports/raspberrypi/link.ld
@@ -174,6 +174,40 @@ SECTIONS
         __data_end__ = .;
     } > RAM AT> FLASH_FIRMWARE
 
+    .itcm :
+    {
+        . = ALIGN(4);
+        *(.itcm.*)
+
+        . = ALIGN(4);
+    } > RAM AT> FLASH_FIRMWARE
+    _ld_itcm_destination = ADDR(.itcm);
+    _ld_itcm_flash_copy = LOADADDR(.itcm);
+    _ld_itcm_size = SIZEOF(.itcm);
+
+    .dtcm_data :
+    {
+        . = ALIGN(4);
+
+        *(.dtcm_data.*)
+
+        . = ALIGN(4);
+    } > RAM AT> FLASH_FIRMWARE
+    _ld_dtcm_data_destination = ADDR(.dtcm_data);
+    _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data);
+    _ld_dtcm_data_size = SIZEOF(.dtcm_data);
+
+    .dtcm_bss :
+    {
+        . = ALIGN(4);
+
+        *(.dtcm_bss.*)
+
+        . = ALIGN(4);
+    } > RAM AT> RAM
+    _ld_dtcm_bss_start = ADDR(.dtcm_bss);
+    _ld_dtcm_bss_size = SIZEOF(.dtcm_bss);
+
     .uninitialized_data (COPY): {
         . = ALIGN(4);
         *(.uninitialized_data*)
diff --git a/ports/raspberrypi/mpconfigport.mk b/ports/raspberrypi/mpconfigport.mk
index bcfe3efd1..395948a51 100644
--- a/ports/raspberrypi/mpconfigport.mk
+++ b/ports/raspberrypi/mpconfigport.mk
@@ -55,3 +55,5 @@ USB_SERIAL_NUMBER_LENGTH = 16
 
 # Number of USB endpoint pairs.
 USB_NUM_EP = 8
+
+INTERNAL_FLASH_FILESYSTEM = 1
diff --git a/ports/raspberrypi/sdk b/ports/raspberrypi/sdk
-Subproject fc10a97c386f65c1a44c68684fe52a56aaf50df
+Subproject 9323b67fce48119b0080854d48abc6b1425e327
diff --git a/ports/raspberrypi/stage2.c.jinja b/ports/raspberrypi/stage2.c.jinja
new file mode 100644
index 000000000..13de7bff9
--- /dev/null
+++ b/ports/raspberrypi/stage2.c.jinja
@@ -0,0 +1,196 @@
+#include "sdk/src/rp2040/hardware_structs/include/hardware/structs/ssi.h"
+#include "sdk/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h"
+#include "sdk/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h"
+#include "sdk/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h"
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence.
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0xa0
+
+// Define interface width: single/dual/quad IO
+{% if quad_ok %}
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+#define TRANSACTION_TYPE SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+#define INSTRUCTION_LENGTH SSI_SPI_CTRLR0_INST_L_VALUE_NONE
+#define READ_INSTRUCTION MODE_CONTINUOUS_READ
+#define ADDR_L 8 // 6 for address, 2 for mode
+{% else %}
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_STD
+#define TRANSACTION_TYPE SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A
+#define INSTRUCTION_LENGTH SSI_SPI_CTRLR0_INST_L_VALUE_8B
+#define READ_INSTRUCTION (0x{{ '%02x' % read_command }})
+#define ADDR_L 6 // * 4 = 24
+{% endif %}
+
+#define CMD_READ_STATUS1 0x05
+#define CMD_READ_STATUS2 0x35
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_WRITE_STATUS1 0x01
+#define CMD_WRITE_STATUS2 0x31
+
+#define SREG_DATA 0x02
+
+static uint32_t wait_and_read(uint8_t);
+static uint8_t read_flash_sreg(uint8_t status_command);
+
+// This function is use by the bootloader to enable the XIP flash. It is also
+// used by the SDK to reinit XIP after doing non-read flash interactions such as
+// writing or erasing. This code must compile down to position independent
+// assembly because we don't know where in RAM it'll be when run.
+
+// This must be the first defined function so that it is placed at the start of
+// memory where the bootloader jumps to!
+void __attribute__((section(".entry._stage2_boot"), used)) _stage2_boot(void) {
+    uint32_t lr;
+    asm ("MOV %0, LR\n" : "=r" (lr) );
+
+    // Set aggressive pad configuration for QSPI
+    // - SCLK 8mA drive, no slew limiting
+    // - SDx disable input Schmitt to reduce delay
+
+    // SCLK
+    pads_qspi_hw->io[0] = PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB |
+                          PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS;
+
+    // Data lines
+    uint32_t data_settings = pads_qspi_hw->io[1];
+    data_settings &= ~PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS;
+    pads_qspi_hw->io[2] = data_settings;
+    {% if quad_ok %}
+    pads_qspi_hw->io[1] = data_settings;
+    pads_qspi_hw->io[3] = data_settings;
+    pads_qspi_hw->io[4] = data_settings;
+    {% endif %}
+
+    // Disable the SSI so we can change the settings.
+    ssi_hw->ssienr = 0;
+
+    // QSPI config
+    ssi_hw->baudr = {{ clock_divider }}; // 125 mhz / clock divider
+
+    // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
+    // if the flash launches data on SCLK posedge, we capture it at the time that
+    // the next SCLK posedge is launched. This is shortly before that posedge
+    // arrives at the flash, so data hold time should be ok. For
+    // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
+    ssi_hw->rx_sample_dly = 1;
+
+    // Set a temporary mode for doing simple commands.
+    ssi_hw->ctrlr0 = (7 << SSI_CTRLR0_DFS_32_LSB) | // 8 bits per data frame
+                     (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB);
+
+    ssi_hw->ssienr = 0x1;
+
+    {% if quad_ok %}
+    // Program status register.
+    // Enable SSI and select slave 0
+    {% if quad_enable_status_byte == 1 %}
+    uint8_t result = read_flash_sreg(CMD_READ_STATUS1);
+    {% elif quad_enable_status_byte == 2 %}
+    uint8_t result = read_flash_sreg(CMD_READ_STATUS2);
+    {% endif %}
+    if (result != {{ quad_enable_bit_mask }}) {
+        ssi_hw->dr0 = (uint8_t) CMD_WRITE_ENABLE;
+        wait_and_read(1);
+
+        {% if split_status_write %}
+        {% if quad_enable_status_byte == 1 %}
+        ssi_hw->dr0 = (uint8_t) CMD_WRITE_STATUS1;
+        {% elif quad_enable_status_byte == 2 %}
+        ssi_hw->dr0 = (uint8_t) CMD_WRITE_STATUS2;
+        {% endif %}
+        ssi_hw->dr0 = {{ quad_enable_bit_mask }};
+        wait_and_read(2);
+        {% else %}
+        ssi_hw->dr0 = (uint8_t) CMD_WRITE_STATUS1;
+        {% if quad_enable_status_byte == 2 %}
+        ssi_hw->dr0 = 0x0;
+        {% endif %}
+        ssi_hw->dr0 = {{ quad_enable_bit_mask }};
+        wait_and_read({{ quad_enable_status_byte + 1 }});
+        {% endif %}
+        // Wait for the write to complete.
+        while ((read_flash_sreg(CMD_READ_STATUS1) & 0x1) != 0) {}
+    }
+    {% endif %}
+
+    // Disable SSI again so that it can be reconfigured
+    ssi_hw->ssienr = 0;
+
+    // Do a single read to get us in continuous mode.
+
+    // Final SSI ctrlr0 settings. We only change the SPI specific settings later.
+    ssi_hw->ctrlr0 = (FRAME_FORMAT << SSI_CTRLR0_SPI_FRF_LSB) | // Quad I/O mode
+                     (31 << SSI_CTRLR0_DFS_32_LSB)  |       // 32 data bits
+                     (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ << SSI_CTRLR0_TMOD_LSB);    // Send INST/ADDR, Receive Data
+
+    ssi_hw->ctrlr1 = 0; // Single 32b read
+
+    {% if quad_ok %}
+    ssi_hw->spi_ctrlr0 = (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | // Address + mode bits
+                         // Hi-Z dummy clocks following address + mode
+                         ({{ wait_cycles }} << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |
+                         // 8-bit instruction
+                         (SSI_SPI_CTRLR0_INST_L_VALUE_8B << SSI_SPI_CTRLR0_INST_L_LSB) |
+                         // Send Command in serial mode then address in Quad I/O mode
+                         (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A << SSI_SPI_CTRLR0_TRANS_TYPE_LSB);
+
+    // Re-enable the SSI
+    ssi_hw->ssienr = 1;
+
+    // Do a single read to get us in continuous mode.
+    ssi_hw->dr0 = 0x{{ '%02x' % read_command }};
+    ssi_hw->dr0 = MODE_CONTINUOUS_READ;
+    wait_and_read(2);
+
+    // Disable the SSI to switch to no-command mode (because we're setup for continuous.)
+    ssi_hw->ssienr = 0;
+    {% endif %}
+
+    // Final SPI ctrlr0 settings.
+    ssi_hw->spi_ctrlr0 = (READ_INSTRUCTION << SSI_SPI_CTRLR0_XIP_CMD_LSB) | // Mode bits to keep flash in continuous read mode
+                         (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |    // Total number of address + mode bits
+                         ({{ wait_cycles }} << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    // Hi-Z dummy clocks following address + mode
+                         (INSTRUCTION_LENGTH << SSI_SPI_CTRLR0_INST_L_LSB) | // Do not send a command, instead send XIP_CMD as mode bits after address
+                         (TRANSACTION_TYPE << SSI_SPI_CTRLR0_TRANS_TYPE_LSB); // Send Address in Quad I/O mode (and Command but that is zero bits long)
+
+    // Re-enable the SSI
+    ssi_hw->ssienr = 1;
+
+    // If lr is 0, then we came from the bootloader.
+    if (lr == 0) {
+        uint32_t* vector_table = (uint32_t*) (XIP_BASE + 0x100);
+        // Switch the vector table to immediately after the stage 2 area.
+        *((uint32_t *) (PPB_BASE + M0PLUS_VTOR_OFFSET)) = (uint32_t) vector_table;
+        // Set the top of the stack according to the vector table.
+        asm volatile ("MSR msp, %0" : : "r" (vector_table[0]) : );
+        // The reset handler is the second entry in the vector table
+        asm volatile ("bx %0" : : "r" (vector_table[1]) : );
+        // Doesn't return. It jumps to the reset handler instead.
+    }
+    // Otherwise we return.
+}
+
+static uint32_t wait_and_read(uint8_t count) {
+    while ((ssi_hw->sr & SSI_SR_TFE_BITS) == 0) {}
+    while ((ssi_hw->sr & SSI_SR_BUSY_BITS) != 0) {}
+    uint32_t result = 0;
+    while (count > 0) {
+        result = ssi_hw->dr0;
+        count--;
+    }
+    return result;
+}
+
+static uint8_t read_flash_sreg(uint8_t status_command) {
+    ssi_hw->dr0 = status_command;
+    ssi_hw->dr0 = status_command;
+
+    return wait_and_read(2);
+}
diff --git a/ports/raspberrypi/supervisor/internal_flash.c b/ports/raspberrypi/supervisor/internal_flash.c
index 81f26967e..51068e184 100644
--- a/ports/raspberrypi/supervisor/internal_flash.c
+++ b/ports/raspberrypi/supervisor/internal_flash.c
@@ -51,17 +51,32 @@
 #define NO_CACHE 0xffffffff
 STATIC uint8_t _cache[SECTOR_SIZE];
 STATIC uint32_t _cache_lba = NO_CACHE;
+STATIC uint32_t _flash_size = 0;
 
 void supervisor_flash_init(void) {
     bi_decl_if_func_used(bi_block_device(
         BINARY_INFO_MAKE_TAG('C', 'P'),
         "CircuitPython",
         RESERVED_FLASH,
-        TOTAL_FLASH_SIZE - RESERVED_FLASH,
+        (1 * 1024 * 1024), // This is a minimum. We can't set it dynamically.
         NULL,
         BINARY_INFO_BLOCK_DEV_FLAG_READ |
         BINARY_INFO_BLOCK_DEV_FLAG_WRITE |
         BINARY_INFO_BLOCK_DEV_FLAG_PT_UNKNOWN));
+
+    // Read the RDID register to get the flash capacity.
+    uint8_t cmd[] = {0x9f, 0, 0, 0};
+    uint8_t data[4];
+    flash_do_cmd(cmd, data, 4);
+    uint8_t power_of_two = 21;
+    // Flash must be at least 2MB (1 << 21) because we use the first 1MB for the
+    // CircuitPython core. We validate the range because Adesto Tech flash chips
+    // don't return the correct value. So, we default to 2MB which will work for
+    // larger chips, it just won't use all of the space.
+    if (data[3] >= 21 && data[3] < 30) {
+        power_of_two = data[3];
+    }
+    _flash_size = 1 << power_of_two;
 }
 
 uint32_t supervisor_flash_get_block_size(void) {
@@ -69,7 +84,7 @@ uint32_t supervisor_flash_get_block_size(void) {
 }
 
 uint32_t supervisor_flash_get_block_count(void) {
-    return (TOTAL_FLASH_SIZE - RESERVED_FLASH) / FILESYSTEM_BLOCK_SIZE;
+    return (_flash_size - RESERVED_FLASH) / FILESYSTEM_BLOCK_SIZE;
 }
 
 void port_internal_flash_flush(void) {
diff --git a/ports/raspberrypi/supervisor/port.c b/ports/raspberrypi/supervisor/port.c
index cf4c05f81..9b3e140a8 100644
--- a/ports/raspberrypi/supervisor/port.c
+++ b/ports/raspberrypi/supervisor/port.c
@@ -74,10 +74,42 @@ STATIC void _binary_info(void) {
     // TODO: Add build attribute for debug builds. Needs newer CircuitPython with CIRCUITPY_DEBUG.
 }
 
+extern uint32_t _ld_dtcm_bss_start;
+extern uint32_t _ld_dtcm_bss_size;
+extern uint32_t _ld_dtcm_data_destination;
+extern uint32_t _ld_dtcm_data_size;
+extern uint32_t _ld_dtcm_data_flash_copy;
+extern uint32_t _ld_itcm_destination;
+extern uint32_t _ld_itcm_size;
+extern uint32_t _ld_itcm_flash_copy;
+
 safe_mode_t port_init(void) {
     _binary_info();
     // Set brown out.
 
+    // Copy all of the "tightly coupled memory" code and data to run from RAM.
+    // This lets us use the 16k cache for dynamically used data and code.
+    // We must do this before we try and call any of its code or load the data.
+    for (uint32_t i = 0; i < ((size_t)&_ld_itcm_size) / 4; i++) {
+        (&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i];
+        // Now zero it out to evict the line from the XIP cache. Without this,
+        // it'll stay in the XIP cache anyway.
+        (&_ld_itcm_flash_copy)[i] = 0x0;
+    }
+
+    // Copy all of the data to run from DTCM.
+    for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_data_size) / 4; i++) {
+        (&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i];
+        // Now zero it out to evict the line from the XIP cache. Without this,
+        // it'll stay in the XIP cache anyway.
+        (&_ld_dtcm_data_flash_copy)[i] = 0x0;
+    }
+
+    // Clear DTCM bss.
+    for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_bss_size) / 4; i++) {
+        (&_ld_dtcm_bss_start)[i] = 0;
+    }
+
     // Reset everything into a known state before board_init.
     reset_port();