diff options
| author | DavePutz <dwputz@gmail.com> | 2020-06-08 10:42:45 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-08 10:42:45 -0500 |
| commit | ef87cc3ed389700f7d32d8a74b2e8499863f1a74 (patch) | |
| tree | 1bcae9dd5dac92169db4435421aa1a4510a449ce /ports | |
| parent | 1f40f9e04ff9be0eb82f56014bde5749be604ad9 (diff) | |
| parent | 004d6441842981994d20027ab7e3248339524bec (diff) | |
Merge pull request #6 from adafruit/master
updating from adafruit
Diffstat (limited to 'ports')
276 files changed, 3106 insertions, 1544 deletions
diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile index 8a5c3309f..d0ab65e6b 100644 --- a/ports/atmel-samd/Makefile +++ b/ports/atmel-samd/Makefile @@ -134,7 +134,7 @@ else endif endif -CFLAGS += $(INC) -Wall -Werror -std=gnu11 -nostdlib $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) +CFLAGS += $(INC) -Wall -Werror -std=gnu11 -nostdlib -fshort-enums $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) ifeq ($(CHIP_FAMILY), samd21) CFLAGS += \ @@ -157,7 +157,7 @@ endif -LDFLAGS = $(CFLAGS) -nostartfiles -fshort-enums -Wl,-nostdlib -Wl,-T,$(GENERATED_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs +LDFLAGS = $(CFLAGS) -nostartfiles -Wl,-nostdlib -Wl,-T,$(GENERATED_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs LIBS := -lgcc -lc # Use toolchain libm if we're not using our own. diff --git a/ports/atmel-samd/boards/8086_commander/pins.c b/ports/atmel-samd/boards/8086_commander/pins.c index 3eea4009e..728da3f6b 100644 --- a/ports/atmel-samd/boards/8086_commander/pins.c +++ b/ports/atmel-samd/boards/8086_commander/pins.c @@ -2,7 +2,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { - // Serial + // Serial { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA11) }, // RX { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA11) }, { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA10) }, // TX diff --git a/ports/atmel-samd/boards/aloriumtech_evo_m51/board.c b/ports/atmel-samd/boards/aloriumtech_evo_m51/board.c index b418d0f1b..1e9ab029e 100644 --- a/ports/atmel-samd/boards/aloriumtech_evo_m51/board.c +++ b/ports/atmel-samd/boards/aloriumtech_evo_m51/board.c @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -// Updated to support Alorium Technology Evo M51 +// Updated to support Alorium Technology Evo M51 // Author: Bryan Craker // Date: 2020-05-20 diff --git a/ports/atmel-samd/boards/capablerobot_usbhub/pins.c b/ports/atmel-samd/boards/capablerobot_usbhub/pins.c index b1966930c..f7ad82c57 100644 --- a/ports/atmel-samd/boards/capablerobot_usbhub/pins.c +++ b/ports/atmel-samd/boards/capablerobot_usbhub/pins.c @@ -4,7 +4,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_ANMB), MP_ROM_PTR(&pin_PA02) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ANVLIM), MP_ROM_PTR(&pin_PA04) }, { MP_OBJ_NEW_QSTR(MP_QSTR_AN5V), MP_ROM_PTR(&pin_PA05) }, - + { MP_OBJ_NEW_QSTR(MP_QSTR_MBPWM), MP_ROM_PTR(&pin_PA14) }, { MP_OBJ_NEW_QSTR(MP_QSTR_MBINT), MP_ROM_PTR(&pin_PA15) }, { MP_OBJ_NEW_QSTR(MP_QSTR_MBCS), MP_ROM_PTR(&pin_PA18) }, diff --git a/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.h b/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.h index 592160b84..321436c6b 100755 --- a/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.h +++ b/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.h @@ -32,4 +32,4 @@ // USB is always used internally so skip the pin objects for it. #define IGNORE_PIN_PA24 1 -#define IGNORE_PIN_PA25 1
\ No newline at end of file +#define IGNORE_PIN_PA25 1 diff --git a/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk b/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk index 19e5dd2ab..a71728e2d 100755 --- a/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk +++ b/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk @@ -15,4 +15,3 @@ CIRCUITPY_BITBANGIO = 0 CIRCUITPY_FREQUENCYIO = 0 CIRCUITPY_I2CSLAVE = 0 CIRCUITPY_VECTORIO = 0 - diff --git a/ports/atmel-samd/boards/datum_distance/pins.c b/ports/atmel-samd/boards/datum_distance/pins.c index b29a859b6..8e4f1101e 100644 --- a/ports/atmel-samd/boards/datum_distance/pins.c +++ b/ports/atmel-samd/boards/datum_distance/pins.c @@ -14,7 +14,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA20) }, { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) }, - { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, diff --git a/ports/atmel-samd/boards/datum_imu/pins.c b/ports/atmel-samd/boards/datum_imu/pins.c index 237b5774e..eabd2567e 100644 --- a/ports/atmel-samd/boards/datum_imu/pins.c +++ b/ports/atmel-samd/boards/datum_imu/pins.c @@ -16,7 +16,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA20) }, { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) }, - { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, diff --git a/ports/atmel-samd/boards/datum_light/pins.c b/ports/atmel-samd/boards/datum_light/pins.c index b29a859b6..8e4f1101e 100644 --- a/ports/atmel-samd/boards/datum_light/pins.c +++ b/ports/atmel-samd/boards/datum_light/pins.c @@ -14,7 +14,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA20) }, { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) }, - { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, diff --git a/ports/atmel-samd/boards/datum_weather/pins.c b/ports/atmel-samd/boards/datum_weather/pins.c index b29a859b6..8e4f1101e 100644 --- a/ports/atmel-samd/boards/datum_weather/pins.c +++ b/ports/atmel-samd/boards/datum_weather/pins.c @@ -14,7 +14,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA20) }, { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) }, - { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, diff --git a/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.mk b/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.mk index 93f6b1c90..e45b5aae3 100644 --- a/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.mk +++ b/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.mk @@ -9,5 +9,6 @@ CHIP_FAMILY = samd21 INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = NONE CIRCUITPY_FULL_BUILD = 0 +CIRCUITPY_RTC = 0 SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/escornabot_makech/pins.c b/ports/atmel-samd/boards/escornabot_makech/pins.c index d43d254e7..fefee1919 100644 --- a/ports/atmel-samd/boards/escornabot_makech/pins.c +++ b/ports/atmel-samd/boards/escornabot_makech/pins.c @@ -9,11 +9,11 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { // Buttons { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA03) }, - - + + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA00) }, { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA01) }, - + // Motors { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA22) }, { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA11) }, @@ -23,10 +23,10 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA18) }, { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA17) }, - + // Buzzer { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA16) }, - + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA09) }, { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA13) }, @@ -34,7 +34,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { //UART { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA01) }, { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA00) }, - + // I2C { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA09) }, diff --git a/ports/atmel-samd/boards/feather_m4_express/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m4_express/mpconfigboard.mk index 7cb53bd13..4946788d3 100644 --- a/ports/atmel-samd/boards/feather_m4_express/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_m4_express/mpconfigboard.mk @@ -12,4 +12,3 @@ EXTERNAL_FLASH_DEVICES = GD25Q16C LONGINT_IMPL = MPZ CIRCUITPY_VECTORIO = 1 - diff --git a/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk b/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk index 3aa7c5721..e9d94638a 100755 --- a/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk @@ -18,4 +18,3 @@ CIRCUITPY_AUDIOIO = 0 # Too much flash for Korean translations CIRCUITPY_VECTORIO = 0 - diff --git a/ports/atmel-samd/boards/fluff_m0/board.c b/ports/atmel-samd/boards/fluff_m0/board.c new file mode 100644 index 000000000..c8e20206a --- /dev/null +++ b/ports/atmel-samd/boards/fluff_m0/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" + +void board_init(void) +{ +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/atmel-samd/boards/fluff_m0/mpconfigboard.h b/ports/atmel-samd/boards/fluff_m0/mpconfigboard.h new file mode 100644 index 000000000..0782c980d --- /dev/null +++ b/ports/atmel-samd/boards/fluff_m0/mpconfigboard.h @@ -0,0 +1,20 @@ +#define MICROPY_HW_BOARD_NAME "Fluff M0" +#define MICROPY_HW_MCU_NAME "samd21e18" + +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) + +#define DEFAULT_I2C_BUS_SCL (&pin_PA23) +#define DEFAULT_I2C_BUS_SDA (&pin_PA22) + +#define DEFAULT_SPI_BUS_SCK (&pin_PA30) +#define DEFAULT_SPI_BUS_MOSI (&pin_PA00) +#define DEFAULT_SPI_BUS_MISO (&pin_PA31) + +#define DEFAULT_UART_BUS_RX (&pin_PA11) +#define DEFAULT_UART_BUS_TX (&pin_PA10) + +// USB is always used internally so skip the pin objects for it. +#define IGNORE_PIN_PA24 1 +#define IGNORE_PIN_PA25 1 diff --git a/ports/atmel-samd/boards/fluff_m0/mpconfigboard.mk b/ports/atmel-samd/boards/fluff_m0/mpconfigboard.mk new file mode 100644 index 000000000..8efc1b575 --- /dev/null +++ b/ports/atmel-samd/boards/fluff_m0/mpconfigboard.mk @@ -0,0 +1,18 @@ +USB_VID = 0x239A +USB_PID = 0x80B0 +USB_PRODUCT = "Fluff M0" +USB_MANUFACTURER = "Radomir Dopieralski" + +CHIP_VARIANT = SAMD21E18A +CHIP_FAMILY = samd21 + +INTERNAL_FLASH_FILESYSTEM = 1 +LONGINT_IMPL = NONE +CIRCUITPY_FULL_BUILD = 0 + +SUPEROPT_GC = 0 + +CFLAGS_BOARD = --param max-inline-insns-auto=15 +ifeq ($(TRANSLATION), zh_Latn_pinyin) +CFLAGS_INLINE_LIMIT = 35 +endif diff --git a/ports/atmel-samd/boards/fluff_m0/pins.c b/ports/atmel-samd/boards/fluff_m0/pins.c new file mode 100644 index 000000000..d80d46b89 --- /dev/null +++ b/ports/atmel-samd/boards/fluff_m0/pins.c @@ -0,0 +1,38 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_PA03) }, + + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA07) }, + + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA31) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA30) }, + + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA10) }, + + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) }, + + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) }, + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/hallowing_m4_express/pins.c b/ports/atmel-samd/boards/hallowing_m4_express/pins.c index 9365ea3ca..388a85d56 100644 --- a/ports/atmel-samd/boards/hallowing_m4_express/pins.c +++ b/ports/atmel-samd/boards/hallowing_m4_express/pins.c @@ -40,7 +40,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA20) }, { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA21) }, { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA23) }, - + { MP_ROM_QSTR(MP_QSTR_TFT_BACKLIGHT), MP_ROM_PTR(&pin_PB14) }, { MP_ROM_QSTR(MP_QSTR_TFT_CS), MP_ROM_PTR(&pin_PA27) }, { MP_ROM_QSTR(MP_QSTR_TFT_DC), MP_ROM_PTR(&pin_PB31) }, diff --git a/ports/atmel-samd/boards/kicksat-sprite/board.c b/ports/atmel-samd/boards/kicksat-sprite/board.c index fc53f3967..75cdfbc82 100644 --- a/ports/atmel-samd/boards/kicksat-sprite/board.c +++ b/ports/atmel-samd/boards/kicksat-sprite/board.c @@ -38,4 +38,4 @@ bool board_requests_safe_mode(void) { } void reset_board(void) { -}
\ No newline at end of file +} diff --git a/ports/atmel-samd/boards/kicksat-sprite/pins.c b/ports/atmel-samd/boards/kicksat-sprite/pins.c index 03af22ff2..87d894c58 100644 --- a/ports/atmel-samd/boards/kicksat-sprite/pins.c +++ b/ports/atmel-samd/boards/kicksat-sprite/pins.c @@ -22,7 +22,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_DAC0), MP_ROM_PTR(&pin_PA02) }, - + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB09) }, { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB08) }, { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA16) }, @@ -30,9 +30,9 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PB03) }, - + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, }; -MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
\ No newline at end of file +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/meowmeow/mpconfigboard.mk b/ports/atmel-samd/boards/meowmeow/mpconfigboard.mk index bd0afb60e..175501313 100644 --- a/ports/atmel-samd/boards/meowmeow/mpconfigboard.mk +++ b/ports/atmel-samd/boards/meowmeow/mpconfigboard.mk @@ -9,5 +9,8 @@ CHIP_FAMILY = samd21 INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = NONE CIRCUITPY_FULL_BUILD = 0 +CIRCUITPY_ROTARYIO = 0 +CIRCUITPY_COUNTIO = 0 +CIRCUITPY_RTC = 0 SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/monster_m4sk/mpconfigboard.h b/ports/atmel-samd/boards/monster_m4sk/mpconfigboard.h index 4bd01706d..ed8f15856 100644 --- a/ports/atmel-samd/boards/monster_m4sk/mpconfigboard.h +++ b/ports/atmel-samd/boards/monster_m4sk/mpconfigboard.h @@ -23,6 +23,3 @@ // Enable the use of 2 displays #define CIRCUITPY_DISPLAY_LIMIT (2) - - - diff --git a/ports/atmel-samd/boards/ndgarage_ndbit6/mpconfigboard.h b/ports/atmel-samd/boards/ndgarage_ndbit6/mpconfigboard.h index 869f207a1..51be8d7c0 100644 --- a/ports/atmel-samd/boards/ndgarage_ndbit6/mpconfigboard.h +++ b/ports/atmel-samd/boards/ndgarage_ndbit6/mpconfigboard.h @@ -29,4 +29,3 @@ // USB is always used. #define IGNORE_PIN_PA24 1 #define IGNORE_PIN_PA25 1 - diff --git a/ports/atmel-samd/boards/ndgarage_ndbit6/mpconfigboard.mk b/ports/atmel-samd/boards/ndgarage_ndbit6/mpconfigboard.mk index 5e5f0ff5f..09804bc4e 100644 --- a/ports/atmel-samd/boards/ndgarage_ndbit6/mpconfigboard.mk +++ b/ports/atmel-samd/boards/ndgarage_ndbit6/mpconfigboard.mk @@ -12,4 +12,3 @@ LONGINT_IMPL = NONE CIRCUITPY_FULL_BUILD = 0 SUPEROPT_GC = 0 - diff --git a/ports/atmel-samd/boards/ndgarage_ndbit6/pins.c b/ports/atmel-samd/boards/ndgarage_ndbit6/pins.c index 6d1fc53b6..2ea563007 100644 --- a/ports/atmel-samd/boards/ndgarage_ndbit6/pins.c +++ b/ports/atmel-samd/boards/ndgarage_ndbit6/pins.c @@ -23,7 +23,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA04) }, { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA05) }, - + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA09) }, diff --git a/ports/atmel-samd/boards/pycubed/board.c b/ports/atmel-samd/boards/pycubed/board.c index 31b081209..9d29d2a66 100644 --- a/ports/atmel-samd/boards/pycubed/board.c +++ b/ports/atmel-samd/boards/pycubed/board.c @@ -58,4 +58,4 @@ void reset_board(void) { common_hal_nvm_bytearray_get_bytes(&bootcnt,0,1,&value_out); ++value_out; common_hal_nvm_bytearray_set_bytes(&bootcnt,0,&value_out,1); -}
\ No newline at end of file +} diff --git a/ports/atmel-samd/boards/pycubed/mpconfigboard.h b/ports/atmel-samd/boards/pycubed/mpconfigboard.h index 8d046c75b..fc16e22b5 100644 --- a/ports/atmel-samd/boards/pycubed/mpconfigboard.h +++ b/ports/atmel-samd/boards/pycubed/mpconfigboard.h @@ -17,7 +17,7 @@ #define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000 - CIRCUITPY_INTERNAL_NVM_SIZE) -// External flash W25Q80DV +// External flash W25Q80DV #define EXTERNAL_FLASH_QSPI_DUAL #define BOARD_HAS_CRYSTAL 1 diff --git a/ports/atmel-samd/boards/pycubed/pins.c b/ports/atmel-samd/boards/pycubed/pins.c index 4c97f58a8..e494fb54b 100644 --- a/ports/atmel-samd/boards/pycubed/pins.c +++ b/ports/atmel-samd/boards/pycubed/pins.c @@ -40,16 +40,16 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_EN_GPS), MP_ROM_PTR(&pin_PB01) }, { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB02) }, { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB03) }, - + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB12) }, { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB13) }, { MP_ROM_QSTR(MP_QSTR_WDT_WDI), MP_ROM_PTR(&pin_PA23) }, { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA21) }, - + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, - + }; -MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
\ No newline at end of file +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/pycubed_mram/board.c b/ports/atmel-samd/boards/pycubed_mram/board.c index 31b081209..9d29d2a66 100644 --- a/ports/atmel-samd/boards/pycubed_mram/board.c +++ b/ports/atmel-samd/boards/pycubed_mram/board.c @@ -58,4 +58,4 @@ void reset_board(void) { common_hal_nvm_bytearray_get_bytes(&bootcnt,0,1,&value_out); ++value_out; common_hal_nvm_bytearray_set_bytes(&bootcnt,0,&value_out,1); -}
\ No newline at end of file +} diff --git a/ports/atmel-samd/boards/pygamer/pins.c b/ports/atmel-samd/boards/pygamer/pins.c index 7e6eff43f..107d780a8 100644 --- a/ports/atmel-samd/boards/pygamer/pins.c +++ b/ports/atmel-samd/boards/pygamer/pins.c @@ -44,7 +44,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB23) }, // SDCS, dup of D4 - { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CS), MP_ROM_PTR(&pin_PA14) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CS), MP_ROM_PTR(&pin_PA14) }, // Special named pins { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA15) }, diff --git a/ports/atmel-samd/boards/pygamer_advance/pins.c b/ports/atmel-samd/boards/pygamer_advance/pins.c index 9c2284db1..653a1bb2e 100644 --- a/ports/atmel-samd/boards/pygamer_advance/pins.c +++ b/ports/atmel-samd/boards/pygamer_advance/pins.c @@ -44,7 +44,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB23) }, // SDCS, dup of D4 - { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CS), MP_ROM_PTR(&pin_PA14) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SD_CS), MP_ROM_PTR(&pin_PA14) }, // Special named pins { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA15) }, diff --git a/ports/atmel-samd/boards/pyruler/mpconfigboard.mk b/ports/atmel-samd/boards/pyruler/mpconfigboard.mk index 475d8b634..885f58e4e 100644 --- a/ports/atmel-samd/boards/pyruler/mpconfigboard.mk +++ b/ports/atmel-samd/boards/pyruler/mpconfigboard.mk @@ -10,6 +10,7 @@ INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = NONE CIRCUITPY_FULL_BUILD = 0 CIRCUITPY_COUNTIO = 0 +CIRCUITPY_RTC = 0 SUPEROPT_GC = 0 CFLAGS_BOARD = --param max-inline-insns-auto=15 diff --git a/ports/atmel-samd/boards/robohatmm1_m4/pins.c b/ports/atmel-samd/boards/robohatmm1_m4/pins.c index 4fc290fb0..74dcfd651 100644 --- a/ports/atmel-samd/boards/robohatmm1_m4/pins.c +++ b/ports/atmel-samd/boards/robohatmm1_m4/pins.c @@ -83,7 +83,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_SWCLK), MP_ROM_PTR(&pin_PA30) }, { MP_ROM_QSTR(MP_QSTR_PI_GP24), MP_ROM_PTR(&pin_PA31) }, { MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA31) }, - + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, //{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, diff --git a/ports/atmel-samd/boards/sam32/board.c b/ports/atmel-samd/boards/sam32/board.c index 7a23d3007..e03260144 100644 --- a/ports/atmel-samd/boards/sam32/board.c +++ b/ports/atmel-samd/boards/sam32/board.c @@ -49,4 +49,4 @@ void reset_board(void) { common_hal_digitalio_digitalinout_switch_to_output(&neopixel, false, DRIVE_MODE_PUSH_PULL); common_hal_neopixel_write(&neopixel, zeroes, 96); common_hal_digitalio_digitalinout_deinit(&neopixel); -}
\ No newline at end of file +} diff --git a/ports/atmel-samd/boards/sam32/mpconfigboard.mk b/ports/atmel-samd/boards/sam32/mpconfigboard.mk index 118744935..1dc686ef8 100644 --- a/ports/atmel-samd/boards/sam32/mpconfigboard.mk +++ b/ports/atmel-samd/boards/sam32/mpconfigboard.mk @@ -14,4 +14,4 @@ CIRCUITPY_AUDIOBUSIO = 0 CIRCUITPY_USTACK = 1 FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_BusDevice -FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel
\ No newline at end of file +FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel diff --git a/ports/atmel-samd/boards/sam32/pins.c b/ports/atmel-samd/boards/sam32/pins.c index f0a5b2b62..463615960 100644 --- a/ports/atmel-samd/boards/sam32/pins.c +++ b/ports/atmel-samd/boards/sam32/pins.c @@ -42,12 +42,12 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_TDI), MP_ROM_PTR(&pin_PB02) }, { MP_ROM_QSTR(MP_QSTR_TMS), MP_ROM_PTR(&pin_PB03) }, { MP_ROM_QSTR(MP_QSTR_ESP_CS),MP_ROM_PTR(&pin_PB15) }, - + { MP_ROM_QSTR(MP_QSTR_TX1), MP_ROM_PTR(&pin_PA12) }, { MP_ROM_QSTR(MP_QSTR_RX1), MP_ROM_PTR(&pin_PA13) }, { MP_ROM_QSTR(MP_QSTR_TX2), MP_ROM_PTR(&pin_PB16) }, { MP_ROM_QSTR(MP_QSTR_RX2), MP_ROM_PTR(&pin_PB17) }, - + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA08) }, { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA09) }, @@ -56,11 +56,11 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA27) }, { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA15) }, - + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, { MP_ROM_QSTR(MP_QSTR_BATTERY), MP_ROM_PTR(&pin_PA06) }, - + }; -MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
\ No newline at end of file +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/serpente/pins.c b/ports/atmel-samd/boards/serpente/pins.c index 0bf686656..7b7b14799 100644 --- a/ports/atmel-samd/boards/serpente/pins.c +++ b/ports/atmel-samd/boards/serpente/pins.c @@ -37,4 +37,3 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); - diff --git a/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/pins.c b/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/pins.c index f9d755d93..9562dc3b8 100644 --- a/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/pins.c +++ b/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/pins.c @@ -21,14 +21,14 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA10) }, { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PA22) }, { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PA23) }, - + // External SPI { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA05) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, - // UART + // UART { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA22) }, { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA23) }, { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, diff --git a/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/pins.c b/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/pins.c index f9d755d93..9562dc3b8 100644 --- a/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/pins.c +++ b/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/pins.c @@ -21,14 +21,14 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA10) }, { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PA22) }, { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PA23) }, - + // External SPI { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA05) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, - // UART + // UART { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA22) }, { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA23) }, { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, diff --git a/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk b/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk index e56517b5c..46f727131 100644 --- a/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk +++ b/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk @@ -13,6 +13,7 @@ LONGINT_IMPL = MPZ CIRCUITPY_BITBANGIO = 0 CIRCUITPY_COUNTIO = 0 +CIRCUITPY_RTC = 0 CIRCUITPY_FREQUENCYIO = 0 CIRCUITPY_I2CSLAVE = 0 diff --git a/ports/atmel-samd/common-hal/countio/Counter.c b/ports/atmel-samd/common-hal/countio/Counter.c index db5b325b8..d2e3fae63 100644 --- a/ports/atmel-samd/common-hal/countio/Counter.c +++ b/ports/atmel-samd/common-hal/countio/Counter.c @@ -25,20 +25,20 @@ void common_hal_countio_counter_construct(countio_counter_obj_t* self, // These default settings apply when the EIC isn't yet enabled. self->eic_channel_a = pin_a->extint_channel; - + self->pin_a = pin_a->number; - + gpio_set_pin_function(self->pin_a, GPIO_PIN_FUNCTION_A); gpio_set_pin_pull_mode(self->pin_a, GPIO_PULL_UP); set_eic_channel_data(self->eic_channel_a, (void*) self); self->count = 0; - + claim_pin(pin_a); - - + + set_eic_handler(self->eic_channel_a, EIC_HANDLER_COUNTER); turn_on_eic_channel(self->eic_channel_a, EIC_CONFIG_SENSE0_FALL_Val); @@ -77,7 +77,7 @@ void common_hal_countio_counter_reset(countio_counter_obj_t* self){ void counter_interrupt_handler(uint8_t channel) { countio_counter_obj_t* self = get_eic_channel_data(channel); - + self->count += 1; - + } diff --git a/ports/atmel-samd/common-hal/digitalio/DigitalInOut.c b/ports/atmel-samd/common-hal/digitalio/DigitalInOut.c index 68d3da806..e37769c15 100644 --- a/ports/atmel-samd/common-hal/digitalio/DigitalInOut.c +++ b/ports/atmel-samd/common-hal/digitalio/DigitalInOut.c @@ -73,7 +73,7 @@ void common_hal_digitalio_digitalinout_switch_to_input( common_hal_digitalio_digitalinout_set_pull(self, pull); } -void common_hal_digitalio_digitalinout_switch_to_output( +digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( digitalio_digitalinout_obj_t* self, bool value, digitalio_drive_mode_t drive_mode) { const uint8_t pin = self->pin->number; @@ -86,6 +86,7 @@ void common_hal_digitalio_digitalinout_switch_to_output( // Direction is set in set_value. We don't need to do it here. common_hal_digitalio_digitalinout_set_value(self, value); + return DIGITALINOUT_OK; } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( @@ -128,7 +129,7 @@ bool common_hal_digitalio_digitalinout_get_value( } } -void common_hal_digitalio_digitalinout_set_drive_mode( +digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( digitalio_digitalinout_obj_t* self, digitalio_drive_mode_t drive_mode) { bool value = common_hal_digitalio_digitalinout_get_value(self); @@ -138,6 +139,7 @@ void common_hal_digitalio_digitalinout_set_drive_mode( if (value) { common_hal_digitalio_digitalinout_set_value(self, value); } + return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( diff --git a/ports/atmel-samd/common-hal/neopixel_write/__init__.c b/ports/atmel-samd/common-hal/neopixel_write/__init__.c index 175527025..5c79f72a4 100644 --- a/ports/atmel-samd/common-hal/neopixel_write/__init__.c +++ b/ports/atmel-samd/common-hal/neopixel_write/__init__.c @@ -150,4 +150,3 @@ void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout, mp_hal_enable_all_interrupts(); } - diff --git a/ports/atmel-samd/common-hal/pulseio/PWMOut.c b/ports/atmel-samd/common-hal/pulseio/PWMOut.c index 1da0da844..b627dadc5 100644 --- a/ports/atmel-samd/common-hal/pulseio/PWMOut.c +++ b/ports/atmel-samd/common-hal/pulseio/PWMOut.c @@ -181,7 +181,7 @@ pwmout_result_t common_hal_pulseio_pwmout_construct(pulseio_pwmout_obj_t* self, mux_position = j; // Claim channel. tcc_channels[timer->index] |= (1 << tcc_channel(timer)); - + tcc_refcount[timer->index]++; } } } diff --git a/ports/atmel-samd/common-hal/supervisor/__init__.c b/ports/atmel-samd/common-hal/supervisor/__init__.c index ac88556b4..6dca35fb5 100755 --- a/ports/atmel-samd/common-hal/supervisor/__init__.c +++ b/ports/atmel-samd/common-hal/supervisor/__init__.c @@ -37,4 +37,4 @@ const super_runtime_obj_t common_hal_supervisor_runtime_obj = { .base = { .type = &supervisor_runtime_type, }, -};
\ No newline at end of file +}; diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index eadd3e8f5..2b3e9826f 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -69,6 +69,7 @@ #include "samd/events.h" #include "samd/external_interrupts.h" #include "samd/dma.h" +#include "shared-bindings/microcontroller/__init__.h" #include "shared-bindings/rtc/__init__.h" #include "reset.h" @@ -496,7 +497,12 @@ void port_sleep_until_interrupt(void) { (void) __get_FPSCR(); } #endif - __WFI(); + common_hal_mcu_disable_interrupts(); + if (!tud_task_event_ready()) { + __DSB(); + __WFI(); + } + common_hal_mcu_enable_interrupts(); } /** diff --git a/ports/cxd56/boards/spresense/mpconfigboard.h b/ports/cxd56/boards/spresense/mpconfigboard.h index c53f6b418..adfcbacb9 100644 --- a/ports/cxd56/boards/spresense/mpconfigboard.h +++ b/ports/cxd56/boards/spresense/mpconfigboard.h @@ -38,4 +38,3 @@ #define DEFAULT_UART_BUS_TX (&pin_UART2_TXD) #define MICROPY_PY_REVERSE_SPECIAL_METHODS (1) - diff --git a/ports/cxd56/common-hal/busio/I2C.c b/ports/cxd56/common-hal/busio/I2C.c index c163c183a..127b6e75c 100644 --- a/ports/cxd56/common-hal/busio/I2C.c +++ b/ports/cxd56/common-hal/busio/I2C.c @@ -79,7 +79,7 @@ bool common_hal_busio_i2c_try_lock(busio_i2c_obj_t *self) { bool common_hal_busio_i2c_has_lock(busio_i2c_obj_t *self) { return self->has_lock; } - + void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) { self->has_lock = false; } diff --git a/ports/cxd56/common-hal/busio/SPI.c b/ports/cxd56/common-hal/busio/SPI.c index 9a41011f2..718a8ff16 100644 --- a/ports/cxd56/common-hal/busio/SPI.c +++ b/ports/cxd56/common-hal/busio/SPI.c @@ -31,7 +31,7 @@ #include "shared-bindings/busio/SPI.h" -void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t *clock, +void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, const mcu_pin_obj_t *miso) { int port = -1; diff --git a/ports/cxd56/common-hal/digitalio/DigitalInOut.c b/ports/cxd56/common-hal/digitalio/DigitalInOut.c index c9af12e44..37b695567 100644 --- a/ports/cxd56/common-hal/digitalio/DigitalInOut.c +++ b/ports/cxd56/common-hal/digitalio/DigitalInOut.c @@ -70,7 +70,7 @@ void common_hal_digitalio_digitalinout_switch_to_input(digitalio_digitalinout_ob board_gpio_config(self->pin->number, 0, true, true, pull); } -void common_hal_digitalio_digitalinout_switch_to_output(digitalio_digitalinout_obj_t *self, bool value, digitalio_drive_mode_t drive_mode) { +digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output(digitalio_digitalinout_obj_t *self, bool value, digitalio_drive_mode_t drive_mode) { self->input = false; self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN; board_gpio_write(self->pin->number, -1); @@ -80,6 +80,7 @@ void common_hal_digitalio_digitalinout_switch_to_output(digitalio_digitalinout_o board_gpio_write(self->pin->number, 0); } common_hal_digitalio_digitalinout_set_value(self, value); + return DIGITALINOUT_OK; } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction(digitalio_digitalinout_obj_t *self) { @@ -104,7 +105,7 @@ bool common_hal_digitalio_digitalinout_get_value(digitalio_digitalinout_obj_t *s return board_gpio_read(self->pin->number); } -void common_hal_digitalio_digitalinout_set_drive_mode(digitalio_digitalinout_obj_t *self, digitalio_drive_mode_t drive_mode) { +digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode(digitalio_digitalinout_obj_t *self, digitalio_drive_mode_t drive_mode) { if (drive_mode == DRIVE_MODE_PUSH_PULL) { board_gpio_write(self->pin->number, -1); board_gpio_config(self->pin->number, 0, false, true, PIN_FLOAT); @@ -115,6 +116,7 @@ void common_hal_digitalio_digitalinout_set_drive_mode(digitalio_digitalinout_obj board_gpio_write(self->pin->number, 0); self->open_drain = true; } + return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode(digitalio_digitalinout_obj_t *self) { diff --git a/ports/cxd56/common-hal/pulseio/PulseOut.c b/ports/cxd56/common-hal/pulseio/PulseOut.c index 5e1d5a2ed..21b4c77e5 100644 --- a/ports/cxd56/common-hal/pulseio/PulseOut.c +++ b/ports/cxd56/common-hal/pulseio/PulseOut.c @@ -63,7 +63,7 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self, if (pulse_fd < 0) { pulse_fd = open("/dev/timer0", O_RDONLY); } - + if (pulse_fd < 0) { mp_raise_RuntimeError(translate("All timers in use")); } diff --git a/ports/cxd56/mkspk/.gitignore b/ports/cxd56/mkspk/.gitignore index e9a6ab18f..4c3d12e3a 100644 --- a/ports/cxd56/mkspk/.gitignore +++ b/ports/cxd56/mkspk/.gitignore @@ -1,3 +1,2 @@ /mkspk /mkspk.exe - diff --git a/ports/cxd56/supervisor/port.c b/ports/cxd56/supervisor/port.c index 9ec9dbfdf..a40d31faf 100644 --- a/ports/cxd56/supervisor/port.c +++ b/ports/cxd56/supervisor/port.c @@ -29,6 +29,8 @@ #include <sys/boardctl.h> #include <sys/time.h> +#include <cxd56_rtc.h> + #include "sched/sched.h" #include "boards/board.h" @@ -45,7 +47,8 @@ safe_mode_t port_init(void) { boardctl(BOARDIOC_INIT, 0); - board_init(); + // Wait until RTC is available + while (g_rtc_enabled == false); if (board_requests_safe_mode()) { return USER_SAFE_MODE; @@ -121,14 +124,10 @@ void board_timerhook(void) } uint64_t port_get_raw_ticks(uint8_t* subticks) { - struct timeval tv; - gettimeofday(&tv, NULL); - long computed_subticks = tv.tv_usec * 1024 * 32 / 1000000; - if (subticks != NULL) { - *subticks = computed_subticks % 32; - } + uint64_t count = cxd56_rtc_count(); + *subticks = count % 32; - return tv.tv_sec * 1024 + computed_subticks / 32; + return count / 32; } // Enable 1/1024 second tick. @@ -147,4 +146,3 @@ void port_interrupt_after_ticks(uint32_t ticks) { void port_sleep_until_interrupt(void) { // TODO: Implement sleep. } - diff --git a/ports/esp32s2/Makefile b/ports/esp32s2/Makefile index be4b2f00f..5ad5c2f1d 100644 --- a/ports/esp32s2/Makefile +++ b/ports/esp32s2/Makefile @@ -31,6 +31,9 @@ else endif endif +# If the flash PORT is not given, use the default /dev/tty.SLAB_USBtoUART. +PORT ?= /dev/tty.SLAB_USBtoUART + # If the build directory is not given, make it reflect the board name. BUILD ?= build-$(BOARD) @@ -107,7 +110,7 @@ endif CFLAGS += $(INC) -Werror -Wall -mlongcalls -std=gnu11 -Wl,--gc-sections $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) -LDFLAGS = $(CFLAGS) -fshort-enums -Wl,-nostdlib -Wl,-Map=$@.map -Wl,-cref +LDFLAGS = $(CFLAGS) -Wl,-nostdlib -Wl,-Map=$@.map -Wl,-cref LDFLAGS += -L$(BUILD)/esp-idf/esp-idf/esp32s2 \ -Tesp32s2_out.ld \ -L$(BUILD)/esp-idf/esp-idf/esp32s2/ld \ @@ -149,6 +152,7 @@ SRC_C += \ mphalport.c \ boards/$(BOARD)/board.c \ boards/$(BOARD)/pins.c \ + modules/$(CIRCUITPY_MODULE).c \ lib/libc/string0.c \ lib/mp-readline/readline.c \ lib/oofatfs/ff.c \ @@ -270,7 +274,7 @@ $(BUILD)/firmware.bin: $(BUILD)/esp-idf/partition_table/partition-table.bin $(BU $(Q)$(PYTHON) ../../tools/join_bins.py $@ 0x1000 $(BUILD)/esp-idf/bootloader/bootloader.bin 0x8000 $(BUILD)/esp-idf/partition_table/partition-table.bin 0x10000 $(BUILD)/circuitpython-firmware.bin flash: $(BUILD)/firmware.bin - esptool.py --chip esp32s2 -p /dev/tty.SLAB_USBtoUART -b 460800 --before=default_reset --after=hard_reset write_flash $(FLASH_FLAGS) 0x0000 $^ + esptool.py --chip esp32s2 -p $(PORT) -b 460800 --before=default_reset --after=hard_reset write_flash $(FLASH_FLAGS) 0x0000 $^ include $(TOP)/py/mkrules.mk diff --git a/ports/esp32s2/boards/espressif_saola_1_wroom/board.c b/ports/esp32s2/boards/espressif_saola_1_wroom/board.c index a3a351f27..b7b2c4ef5 100644 --- a/ports/esp32s2/boards/espressif_saola_1_wroom/board.c +++ b/ports/esp32s2/boards/espressif_saola_1_wroom/board.c @@ -26,8 +26,16 @@ #include "boards/board.h" #include "mpconfigboard.h" +#include "shared-bindings/microcontroller/Pin.h" void board_init(void) { + // USB + never_reset_pin(&pin_GPIO19); + never_reset_pin(&pin_GPIO20); + + // Debug UART + never_reset_pin(&pin_GPIO43); + never_reset_pin(&pin_GPIO44); } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.mk b/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.mk index aa82588a5..cd2735615 100644 --- a/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.mk +++ b/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.mk @@ -18,3 +18,5 @@ CIRCUITPY_MICROCONTROLLER = 0 CIRCUITPY_ESP_FLASH_MODE=dio CIRCUITPY_ESP_FLASH_FREQ=40m CIRCUITPY_ESP_FLASH_SIZE=4MB + +CIRCUITPY_MODULE=wroom diff --git a/ports/esp32s2/boards/espressif_saola_1_wrover/board.c b/ports/esp32s2/boards/espressif_saola_1_wrover/board.c index a3a351f27..b7b2c4ef5 100644 --- a/ports/esp32s2/boards/espressif_saola_1_wrover/board.c +++ b/ports/esp32s2/boards/espressif_saola_1_wrover/board.c @@ -26,8 +26,16 @@ #include "boards/board.h" #include "mpconfigboard.h" +#include "shared-bindings/microcontroller/Pin.h" void board_init(void) { + // USB + never_reset_pin(&pin_GPIO19); + never_reset_pin(&pin_GPIO20); + + // Debug UART + never_reset_pin(&pin_GPIO43); + never_reset_pin(&pin_GPIO44); } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.mk b/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.mk index ff7e6228a..0b847de94 100644 --- a/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.mk +++ b/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.mk @@ -18,3 +18,5 @@ CIRCUITPY_MICROCONTROLLER = 0 CIRCUITPY_ESP_FLASH_MODE=dio CIRCUITPY_ESP_FLASH_FREQ=40m CIRCUITPY_ESP_FLASH_SIZE=4MB + +CIRCUITPY_MODULE=wrover diff --git a/ports/esp32s2/common-hal/digitalio/DigitalInOut.c b/ports/esp32s2/common-hal/digitalio/DigitalInOut.c index 349da6bf4..7745a9c0a 100644 --- a/ports/esp32s2/common-hal/digitalio/DigitalInOut.c +++ b/ports/esp32s2/common-hal/digitalio/DigitalInOut.c @@ -30,24 +30,18 @@ #include "driver/gpio.h" - -#include "esp_log.h" - -static const char* TAG = "CircuitPython digitalio"; +#include "esp-idf/components/soc/include/hal/gpio_hal.h" void common_hal_digitalio_digitalinout_never_reset( digitalio_digitalinout_obj_t *self) { - (void)self; + never_reset_pin_number(self->pin->number); } digitalinout_result_t common_hal_digitalio_digitalinout_construct( digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { - - // claim_pin(pin); + claim_pin(pin); self->pin = pin; - ESP_EARLY_LOGW(TAG, "construct %d", pin->number); - return DIGITALINOUT_OK; } @@ -60,78 +54,86 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self return; } - // reset_pin_number(0, self->pin->number); + reset_pin_number(self->pin->number); self->pin = mp_const_none; } void common_hal_digitalio_digitalinout_switch_to_input( digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { - gpio_config_t config = { - .pin_bit_mask = 1 << self->pin->number, - .mode = GPIO_MODE_INPUT - }; - if (pull == PULL_UP) { - config.pull_up_en = GPIO_PULLUP_ENABLE; - } else if (pull == PULL_DOWN) { - config.pull_down_en = GPIO_PULLDOWN_ENABLE; - } - - gpio_config(&config); + common_hal_digitalio_digitalinout_set_pull(self, pull); + gpio_set_direction(self->pin->number, GPIO_MODE_DEF_INPUT); } -void common_hal_digitalio_digitalinout_switch_to_output( +digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( digitalio_digitalinout_obj_t *self, bool value, digitalio_drive_mode_t drive_mode) { - gpio_config_t config = { - .pin_bit_mask = 1ULL << self->pin->number, - .mode = GPIO_MODE_OUTPUT - }; - if (drive_mode == DRIVE_MODE_OPEN_DRAIN) { - config.mode = GPIO_MODE_OUTPUT_OD; - } gpio_set_level(self->pin->number, value); - gpio_config(&config); + return common_hal_digitalio_digitalinout_set_drive_mode(self, drive_mode); } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( digitalio_digitalinout_obj_t *self) { - + uint32_t iomux = READ_PERI_REG(GPIO_PIN_MUX_REG[self->pin->number]); + if ((iomux & FUN_IE) != 0) { + return DIRECTION_INPUT; + } return DIRECTION_OUTPUT; } void common_hal_digitalio_digitalinout_set_value( digitalio_digitalinout_obj_t *self, bool value) { - ESP_EARLY_LOGW(TAG, "set %d %d", self->pin->number, value); gpio_set_level(self->pin->number, value); } bool common_hal_digitalio_digitalinout_get_value( digitalio_digitalinout_obj_t *self) { - return true; + return gpio_get_level(self->pin->number) == 1; } -void common_hal_digitalio_digitalinout_set_drive_mode( +digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( digitalio_digitalinout_obj_t *self, digitalio_drive_mode_t drive_mode) { - (void)self; - (void)drive_mode; + gpio_num_t number = self->pin->number; + gpio_mode_t mode; + if (drive_mode == DRIVE_MODE_OPEN_DRAIN) { + mode = GPIO_MODE_DEF_OD; + } else { + mode = GPIO_MODE_DEF_OUTPUT; + } + esp_err_t result = gpio_set_direction(number, mode); + if (result != ESP_OK) { + return DIGITALINOUT_INPUT_ONLY; + } + return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( digitalio_digitalinout_obj_t *self) { - // if (common_hal_digitalio_digitalinout_get_direction(self) == DIRECTION_OUTPUT) - // return DRIVE_MODE_PUSH_PULL; - // else - return DRIVE_MODE_OPEN_DRAIN; + if (GPIO_HAL_GET_HW(GPIO_PORT_0)->pin[self->pin->number].pad_driver == 1) { + return DRIVE_MODE_OPEN_DRAIN; + } + return DRIVE_MODE_PUSH_PULL; } void common_hal_digitalio_digitalinout_set_pull( digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { - (void)self; - (void)pull; + gpio_num_t number = self->pin->number; + gpio_pullup_dis(number); + gpio_pulldown_dis(number); + if (pull == PULL_UP) { + gpio_pullup_en(number); + } else if (pull == PULL_DOWN) { + gpio_pulldown_en(number); + } } digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( digitalio_digitalinout_obj_t *self) { + gpio_num_t gpio_num = self->pin->number; + if (REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU) == 1) { + return PULL_UP; + } else if (REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD) == 1) { + return PULL_DOWN; + } return PULL_NONE; } diff --git a/ports/esp32s2/common-hal/microcontroller/Pin.c b/ports/esp32s2/common-hal/microcontroller/Pin.c index e142191fd..4c39eea16 100644 --- a/ports/esp32s2/common-hal/microcontroller/Pin.c +++ b/ports/esp32s2/common-hal/microcontroller/Pin.c @@ -29,18 +29,51 @@ #include "py/mphal.h" +#include "esp-idf/components/driver/include/driver/gpio.h" +#include "esp-idf/components/soc/include/hal/gpio_hal.h" + +STATIC uint32_t never_reset_pins[2]; +STATIC uint32_t in_use[2]; + +void never_reset_pin_number(gpio_num_t pin_number) { + never_reset_pins[pin_number / 32] |= 1 << pin_number % 32; +} + +void never_reset_pin(const mcu_pin_obj_t* pin) { + never_reset_pin_number(pin->number); +} + // Mark pin as free and return it to a quiescent state. -void reset_pin_number(uint8_t pin_port, uint8_t pin_number) { +void reset_pin_number(gpio_num_t pin_number) { + never_reset_pins[pin_number / 32] &= ~(1 << pin_number % 32); + in_use[pin_number / 32] &= ~(1 << pin_number % 32); } +void reset_all_pins(void) { + for (uint8_t i = 0; i < GPIO_PIN_COUNT; i++) { + uint32_t iomux_address = GPIO_PIN_MUX_REG[i]; + if (iomux_address == 0 || + (never_reset_pins[i / 32] & (1 << i % 32)) != 0) { + continue; + } + gpio_set_direction(i, GPIO_MODE_DEF_INPUT); + gpio_pullup_dis(i); + gpio_pulldown_dis(i); + } + in_use[0] = 0; + in_use[1] = 0; +} void claim_pin(const mcu_pin_obj_t* pin) { + in_use[pin->number / 32] |= (1 << pin->number % 32); } -bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number) { - return true; +bool pin_number_is_free(gpio_num_t pin_number) { + uint8_t offset = pin_number / 32; + uint8_t mask = 1 << pin_number % 32; + return (never_reset_pins[offset] & mask) == 0 && (in_use[offset] & mask) == 0; } bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { - return pin_number_is_free(0, pin->number); + return pin_number_is_free(pin->number); } diff --git a/ports/esp32s2/common-hal/microcontroller/Pin.h b/ports/esp32s2/common-hal/microcontroller/Pin.h index ab5574422..6f47b1ed3 100644 --- a/ports/esp32s2/common-hal/microcontroller/Pin.h +++ b/ports/esp32s2/common-hal/microcontroller/Pin.h @@ -34,11 +34,10 @@ void reset_all_pins(void); // reset_pin_number takes the pin number instead of the pointer so that objects don't // need to store a full pointer. -void reset_pin_number(uint8_t pin_port, uint8_t pin_number); +void reset_pin_number(gpio_num_t pin_number); void claim_pin(const mcu_pin_obj_t* pin); -bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number); -void never_reset_pin_number(uint8_t pin_port, uint8_t pin_number); -// GPIO_TypeDef * pin_port(uint8_t pin_port); -uint16_t pin_mask(uint8_t pin_number); +bool pin_number_is_free(gpio_num_t pin_number); +void never_reset_pin_number(gpio_num_t pin_number); +void never_reset_pin(const mcu_pin_obj_t* pin); #endif // MICROPY_INCLUDED_ESP32S2_COMMON_HAL_MICROCONTROLLER_PIN_H diff --git a/ports/esp32s2/common-hal/microcontroller/__init__.c b/ports/esp32s2/common-hal/microcontroller/__init__.c index a36d0c440..6b2e18673 100644 --- a/ports/esp32s2/common-hal/microcontroller/__init__.c +++ b/ports/esp32s2/common-hal/microcontroller/__init__.c @@ -39,24 +39,31 @@ #include "supervisor/filesystem.h" #include "supervisor/shared/safe_mode.h" +#include "freertos/FreeRTOS.h" + void common_hal_mcu_delay_us(uint32_t delay) { } volatile uint32_t nesting_count = 0; +static portMUX_TYPE cp_mutex = portMUX_INITIALIZER_UNLOCKED; void common_hal_mcu_disable_interrupts(void) { + if (nesting_count == 0) { + portENTER_CRITICAL(&cp_mutex); + } nesting_count++; } void common_hal_mcu_enable_interrupts(void) { if (nesting_count == 0) { - + // Maybe log here because it's very bad. } nesting_count--; if (nesting_count > 0) { return; } + portEXIT_CRITICAL(&cp_mutex); } void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) { diff --git a/ports/esp32s2/common-hal/supervisor/Runtime.c b/ports/esp32s2/common-hal/supervisor/Runtime.c index feab6987d..ea663f897 100644 --- a/ports/esp32s2/common-hal/supervisor/Runtime.c +++ b/ports/esp32s2/common-hal/supervisor/Runtime.c @@ -35,4 +35,3 @@ bool common_hal_get_serial_connected(void) { bool common_hal_get_serial_bytes_available(void) { return (bool) serial_bytes_available(); } - diff --git a/ports/esp32s2/common-hal/supervisor/__init__.c b/ports/esp32s2/common-hal/supervisor/__init__.c index ac88556b4..6dca35fb5 100644 --- a/ports/esp32s2/common-hal/supervisor/__init__.c +++ b/ports/esp32s2/common-hal/supervisor/__init__.c @@ -37,4 +37,4 @@ const super_runtime_obj_t common_hal_supervisor_runtime_obj = { .base = { .type = &supervisor_runtime_type, }, -};
\ No newline at end of file +}; diff --git a/ports/esp32s2/esp-idf b/ports/esp32s2/esp-idf -Subproject 0daf6e0e41f95d22d193d08941a00df9525bc40 +Subproject 7aae7f034bab68d2dd6aaa763924c91eb697d87 diff --git a/ports/esp32s2/modules/module.h b/ports/esp32s2/modules/module.h new file mode 100644 index 000000000..6c40e30e0 --- /dev/null +++ b/ports/esp32s2/modules/module.h @@ -0,0 +1,35 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +#ifndef MICROPY_INCLUDED_ESP32S2_MODULES_MODULE_H +#define MICROPY_INCLUDED_ESP32S2_MODULES_MODULE_H + +#include "shared-bindings/microcontroller/Pin.h" + +void never_reset_module_internal_pins(void); + +#endif // MICROPY_INCLUDED_ESP32S2_MODULES_MODULE_H diff --git a/ports/esp32s2/modules/none.c b/ports/esp32s2/modules/none.c new file mode 100644 index 000000000..9b5433bd9 --- /dev/null +++ b/ports/esp32s2/modules/none.c @@ -0,0 +1,28 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +void never_reset_module_internal_pins(void) { +} diff --git a/ports/esp32s2/modules/wroom.c b/ports/esp32s2/modules/wroom.c new file mode 100644 index 000000000..16c586118 --- /dev/null +++ b/ports/esp32s2/modules/wroom.c @@ -0,0 +1,37 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "modules/module.h" + +void never_reset_module_internal_pins(void) { + // SPI Flash + never_reset_pin(&pin_GPIO27); + never_reset_pin(&pin_GPIO28); + never_reset_pin(&pin_GPIO29); + never_reset_pin(&pin_GPIO30); + never_reset_pin(&pin_GPIO31); + never_reset_pin(&pin_GPIO32); +} diff --git a/ports/esp32s2/modules/wrover.c b/ports/esp32s2/modules/wrover.c new file mode 100644 index 000000000..d589a8fd4 --- /dev/null +++ b/ports/esp32s2/modules/wrover.c @@ -0,0 +1,38 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "modules/module.h" + +void never_reset_module_internal_pins(void) { + // SPI Flash and RAM + never_reset_pin(&pin_GPIO26); + never_reset_pin(&pin_GPIO27); + never_reset_pin(&pin_GPIO28); + never_reset_pin(&pin_GPIO29); + never_reset_pin(&pin_GPIO30); + never_reset_pin(&pin_GPIO31); + never_reset_pin(&pin_GPIO32); +} diff --git a/ports/esp32s2/mpconfigport.h b/ports/esp32s2/mpconfigport.h index c307d4791..d340bb480 100644 --- a/ports/esp32s2/mpconfigport.h +++ b/ports/esp32s2/mpconfigport.h @@ -32,6 +32,7 @@ #define MICROPY_NLR_THUMB (0) #define MICROPY_PY_UJSON (0) +#define MICROPY_USE_INTERNAL_PRINTF (0) #include "py/circuitpy_mpconfig.h" diff --git a/ports/esp32s2/mpconfigport.mk b/ports/esp32s2/mpconfigport.mk index 6d66d9057..c9df81db0 100644 --- a/ports/esp32s2/mpconfigport.mk +++ b/ports/esp32s2/mpconfigport.mk @@ -33,3 +33,5 @@ CIRCUITPY_TOUCHIO = 0 # Enable USB support CIRCUITPY_USB_HID = 1 CIRCUITPY_USB_MIDI = 1 + +CIRCUITPY_MODULE ?= none diff --git a/ports/esp32s2/mphalport.c b/ports/esp32s2/mphalport.c index 772b61c9e..da5258b0e 100644 --- a/ports/esp32s2/mphalport.c +++ b/ports/esp32s2/mphalport.c @@ -37,6 +37,24 @@ void mp_hal_delay_us(mp_uint_t delay) { mp_hal_delay_ms(delay / 1000); } -mp_uint_t cpu_get_regs_and_sp(mp_uint_t *regs) { +// This is provided by the esp-idf/components/xtensa/esp32s2/libhal.a binary +// blob. +extern void xthal_window_spill(void); + +mp_uint_t cpu_get_regs_and_sp(mp_uint_t *regs, uint8_t reg_count) { + // xtensa has more registers than an instruction can address. The 16 that + // can be addressed are called the "window". When a function is called or + // returns the window rotates. This allows for more efficient function calls + // because ram doesn't need to be used. It's only used if the window wraps + // around onto itself. At that point values are "spilled" to empty spots in + // the stack that were set aside. When the window rotates back around (on + // function return), the values are restored into the register from ram. + + // So, in order to read the values in the stack scan we must make sure all + // of the register values we care about have been spilled to RAM. Luckily, + // there is a HAL call to do it. There is a bit of a race condition here + // because the register value could change after it's been restored but that + // is unlikely to happen with a heap pointer while we do a GC. + xthal_window_spill(); return (mp_uint_t) __builtin_frame_address(0); } diff --git a/ports/esp32s2/peripherals/pins.h b/ports/esp32s2/peripherals/pins.h index 1a74b0367..07d0b908e 100644 --- a/ports/esp32s2/peripherals/pins.h +++ b/ports/esp32s2/peripherals/pins.h @@ -33,10 +33,12 @@ #include <stdint.h> #include "esp32s2_peripherals_config.h" +#include "esp-idf/config/sdkconfig.h" +#include "esp-idf/components/soc/include/hal/gpio_types.h" typedef struct { PIN_PREFIX_FIELDS - uint8_t number; + gpio_num_t number; } mcu_pin_obj_t; extern const mcu_pin_obj_t pin_GPIO0; diff --git a/ports/esp32s2/sdkconfig.defaults b/ports/esp32s2/sdkconfig.defaults index f7deb53fb..958e1852e 100644 --- a/ports/esp32s2/sdkconfig.defaults +++ b/ports/esp32s2/sdkconfig.defaults @@ -259,7 +259,7 @@ CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 CONFIG_ESP_ERR_TO_NAME_LOOKUP=y CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 -CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192 CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 CONFIG_ESP_CONSOLE_UART_DEFAULT=y diff --git a/ports/esp32s2/supervisor/internal_flash.c b/ports/esp32s2/supervisor/internal_flash.c index aab7e587a..a8d3fa485 100644 --- a/ports/esp32s2/supervisor/internal_flash.c +++ b/ports/esp32s2/supervisor/internal_flash.c @@ -100,18 +100,20 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 _cache_lba = sector_offset; } for (uint8_t b = block_offset; b < blocks_per_sector; b++) { + // Stop copying after the last block. + if (block >= num_blocks) { + break; + } memcpy(_cache + b * FILESYSTEM_BLOCK_SIZE, src + block * FILESYSTEM_BLOCK_SIZE, FILESYSTEM_BLOCK_SIZE); block++; } result = esp_partition_erase_range(_partition, sector_offset, SECTOR_SIZE); - ESP_EARLY_LOGW(TAG, "erase %d", result); result = esp_partition_write(_partition, sector_offset, _cache, SECTOR_SIZE); - ESP_EARLY_LOGW(TAG, "write %d", result); } return 0; // success @@ -119,4 +121,3 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 void supervisor_flash_release_cache(void) { } - diff --git a/ports/esp32s2/supervisor/port.c b/ports/esp32s2/supervisor/port.c index 4389bb6a8..4c42f11af 100644 --- a/ports/esp32s2/supervisor/port.c +++ b/ports/esp32s2/supervisor/port.c @@ -29,10 +29,12 @@ #include <sys/time.h> #include "supervisor/port.h" #include "boards/board.h" +#include "modules/module.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" +#include "common-hal/microcontroller/Pin.h" #include "supervisor/memory.h" #include "supervisor/shared/tick.h" @@ -56,12 +58,14 @@ safe_mode_t port_init(void) { if (result != ESP_OK) { ESP_EARLY_LOGE(TAG, "Unable to create tick timer."); } + never_reset_module_internal_pins(); ESP_EARLY_LOGW(TAG, "port init done"); return NO_SAFE_MODE; } void reset_port(void) { + reset_all_pins(); } void reset_to_bootloader(void) { @@ -148,6 +152,9 @@ void port_sleep_until_interrupt(void) { // FreeRTOS delay here maybe. // Light sleep shuts down BLE and wifi. // esp_light_sleep_start() + if (sleep_time_duration == 0) { + return; + } vTaskDelayUntil(&sleep_time_set, sleep_time_duration); } diff --git a/ports/esp32s2/supervisor/usb.c b/ports/esp32s2/supervisor/usb.c index 7c508485e..39eb8204f 100644 --- a/ports/esp32s2/supervisor/usb.c +++ b/ports/esp32s2/supervisor/usb.c @@ -29,6 +29,11 @@ #include "lib/utils/interrupt_char.h" #include "lib/mp-readline/readline.h" +#include "esp-idf/components/soc/soc/esp32s2/include/soc/usb_periph.h" +#include "esp-idf/components/driver/include/driver/periph_ctrl.h" +#include "esp-idf/components/driver/include/driver/gpio.h" +#include "esp-idf/components/esp_rom/include/esp32s2/rom/gpio.h" + #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -64,17 +69,22 @@ void usb_device_task(void* param) } void init_usb_hardware(void) { + periph_module_reset(PERIPH_USB_MODULE); + periph_module_enable(PERIPH_USB_MODULE); usb_hal_context_t hal = { .use_external_phy = false // use built-in PHY }; usb_hal_init(&hal); + // Initialize the pin drive strength. + gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3); + gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); + (void) xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, - configMAX_PRIORITIES-1, + 5, usb_device_stack, &usb_device_taskdef); } - diff --git a/ports/esp32s2/tools/decode_backtrace.py b/ports/esp32s2/tools/decode_backtrace.py new file mode 100644 index 000000000..3f078895a --- /dev/null +++ b/ports/esp32s2/tools/decode_backtrace.py @@ -0,0 +1,23 @@ +"""Simple script that translates "Backtrace:" lines from the ESP output to files + and line numbers. + + Run with: python3 tools/decode_backtrace.py <board> + + Enter the backtrace line at the "? " prompt. CTRL-C to exit the script. + """ + +import subprocess +import sys + +board = sys.argv[1] +print(board) + +while True: + addresses = input("? ") + if addresses.startswith("Backtrace:"): + addresses = addresses[len("Backtrace:"):] + addresses = addresses.strip().split() + addresses = [address.split(":")[0] for address in addresses] + print('got', addresses) + subprocess.run(["xtensa-esp32s2-elf-addr2line", + "-e", "build-{}/firmware.elf".format(board)] + addresses) diff --git a/ports/litex/Makefile b/ports/litex/Makefile index 596eaf2bb..d75a4da28 100644 --- a/ports/litex/Makefile +++ b/ports/litex/Makefile @@ -83,14 +83,14 @@ else ### CFLAGS += -flto endif -CFLAGS += $(INC) -Werror -Wall -std=gnu11 -nostdlib $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) +CFLAGS += $(INC) -Werror -Wall -std=gnu11 -nostdlib -fshort-enums $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) # TODO: check this CFLAGS += -D__START=main -DFOMU LD_FILE := boards/$(BOARD)/$(BOARD)-spi.ld -LDFLAGS = $(CFLAGS) -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs -Wl,-melf32lriscv +LDFLAGS = $(CFLAGS) -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs -Wl,-melf32lriscv LIBS := -lgcc -lc diff --git a/ports/litex/common-hal/digitalio/DigitalInOut.c b/ports/litex/common-hal/digitalio/DigitalInOut.c index 574d0de56..26f79f16d 100644 --- a/ports/litex/common-hal/digitalio/DigitalInOut.c +++ b/ports/litex/common-hal/digitalio/DigitalInOut.c @@ -64,12 +64,13 @@ void common_hal_digitalio_digitalinout_switch_to_input( touch_oe_write(touch_oe_read() & ~(1 << self->pin->number)); } -void common_hal_digitalio_digitalinout_switch_to_output( +digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( digitalio_digitalinout_obj_t *self, bool value, digitalio_drive_mode_t drive_mode) { (void)drive_mode; common_hal_digitalio_digitalinout_set_value(self, value); touch_oe_write(touch_oe_read() | (1 << self->pin->number)); + return DIGITALINOUT_OK; } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( @@ -92,11 +93,12 @@ bool common_hal_digitalio_digitalinout_get_value( return !!(touch_i_read() & (1 << self->pin->number)); } -void common_hal_digitalio_digitalinout_set_drive_mode( +digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( digitalio_digitalinout_obj_t *self, digitalio_drive_mode_t drive_mode) { (void)self; (void)drive_mode; + return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( diff --git a/ports/litex/common-hal/supervisor/Runtime.c b/ports/litex/common-hal/supervisor/Runtime.c index feab6987d..ea663f897 100644 --- a/ports/litex/common-hal/supervisor/Runtime.c +++ b/ports/litex/common-hal/supervisor/Runtime.c @@ -35,4 +35,3 @@ bool common_hal_get_serial_connected(void) { bool common_hal_get_serial_bytes_available(void) { return (bool) serial_bytes_available(); } - diff --git a/ports/litex/common-hal/supervisor/__init__.c b/ports/litex/common-hal/supervisor/__init__.c index ac88556b4..6dca35fb5 100644 --- a/ports/litex/common-hal/supervisor/__init__.c +++ b/ports/litex/common-hal/supervisor/__init__.c @@ -37,4 +37,4 @@ const super_runtime_obj_t common_hal_supervisor_runtime_obj = { .base = { .type = &supervisor_runtime_type, }, -};
\ No newline at end of file +}; diff --git a/ports/litex/hw/common.h b/ports/litex/hw/common.h index 6a97ca2e9..b902bc4f2 100644 --- a/ports/litex/hw/common.h +++ b/ports/litex/hw/common.h @@ -30,4 +30,4 @@ static inline uint32_t csr_readl(uint32_t addr) { return *(volatile uint32_t *)addr; } -#endif /* _HW_COMMON_H_ */
\ No newline at end of file +#endif /* _HW_COMMON_H_ */ diff --git a/ports/litex/irq.h b/ports/litex/irq.h index a82218907..dc96c228d 100644 --- a/ports/litex/irq.h +++ b/ports/litex/irq.h @@ -68,4 +68,4 @@ static inline unsigned int irq_pending(void) } #endif -#endif /* __IRQ_H */
\ No newline at end of file +#endif /* __IRQ_H */ diff --git a/ports/litex/supervisor/internal_flash.c b/ports/litex/supervisor/internal_flash.c index 2dbf46b3a..cf777a8ac 100644 --- a/ports/litex/supervisor/internal_flash.c +++ b/ports/litex/supervisor/internal_flash.c @@ -348,4 +348,3 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 void supervisor_flash_release_cache(void) { } - diff --git a/ports/litex/supervisor/port.c b/ports/litex/supervisor/port.c index 4721d82fa..3125072e6 100644 --- a/ports/litex/supervisor/port.c +++ b/ports/litex/supervisor/port.c @@ -68,7 +68,6 @@ safe_mode_t port_init(void) { irq_setmask(0); irq_setie(1); tick_init(); - board_init(); return NO_SAFE_MODE; } diff --git a/ports/mimxrt10xx/Makefile b/ports/mimxrt10xx/Makefile index 922978ac2..78cab0188 100644 --- a/ports/mimxrt10xx/Makefile +++ b/ports/mimxrt10xx/Makefile @@ -90,7 +90,7 @@ else #CFLAGS += -flto -flto-partition=none endif -CFLAGS += $(INC) -ggdb -Wall -Wno-cast-align -std=gnu11 -nostdlib $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) +CFLAGS += $(INC) -ggdb -Wall -Wno-cast-align -std=gnu11 -nostdlib -fshort-enums $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) # TODO: add these when -Werror is applied # Disable some warnings, as do most ports. NXP SDK causes undef, tinyusb causes cast-align @@ -112,7 +112,7 @@ LD_FILES = $(wildcard boards/$(BOARD)/*.ld) $(addprefix linking/, flash/$(FLASH) LD_SCRIPT_FLAG := -Wl,-T, -LDFLAGS = $(CFLAGS) -nostartfiles -fshort-enums -Wl,-nostdlib $(addprefix $(LD_SCRIPT_FLAG), $(LD_FILES)) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs +LDFLAGS = $(CFLAGS) -nostartfiles -Wl,-nostdlib $(addprefix $(LD_SCRIPT_FLAG), $(LD_FILES)) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs LIBS := -lgcc -lc -lnosys -lm # Use toolchain libm if we're not using our own. diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board.c b/ports/mimxrt10xx/boards/imxrt1010_evk/board.c index b94e6055e..ba3498581 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board.c @@ -33,7 +33,6 @@ void board_init(void) { // SWD Pins common_hal_never_reset_pin(&pin_GPIO_AD_13); //SWDIO common_hal_never_reset_pin(&pin_GPIO_AD_12); //SWCLK - common_hal_never_reset_pin(&pin_GPIO_AD_09); //SWO // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); common_hal_never_reset_pin(&pin_GPIO_SD_11); diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h b/ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h index 128e33111..77d458d75 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h @@ -7,6 +7,10 @@ #define BOARD_FLASH_SIZE (16 * 1024 * 1024) +#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_AD_06) +#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_AD_04) +#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_AD_03) + #define DEFAULT_I2C_BUS_SCL (&pin_GPIO_02) #define DEFAULT_I2C_BUS_SDA (&pin_GPIO_01) diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/pins.c b/ports/mimxrt10xx/boards/imxrt1010_evk/pins.c index a5a598760..a0221a2ad 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/pins.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/pins.c @@ -4,9 +4,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_09) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) }, { MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_10) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) }, { MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_05) }, { MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_06) }, { MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_08) }, @@ -20,9 +18,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_AD_03) }, { MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_AD_06) }, { MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_01) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_01) }, { MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_02) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_02) }, { MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_07) }, { MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_09) }, @@ -31,6 +27,16 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_01) }, { MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO_AD_04) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO_AD_03) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO_AD_06) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_11) }, { MP_OBJ_NEW_QSTR(MP_QSTR_USER_SW), MP_ROM_PTR(&pin_GPIO_SD_05) }, diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board.c b/ports/mimxrt10xx/boards/imxrt1020_evk/board.c index aaa7b382c..d5166b356 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board.c @@ -33,7 +33,6 @@ void board_init(void) { // SWD Pins common_hal_never_reset_pin(&pin_GPIO_AD_B0_00);//SWDIO common_hal_never_reset_pin(&pin_GPIO_AD_B0_01);//SWCLK - common_hal_never_reset_pin(&pin_GPIO_AD_B0_04);//SWO // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_06); diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c index 80a57f17b..43ffe0dd1 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c @@ -45,7 +45,7 @@ const flexspi_nor_config_t qspiflash_config = { #ifdef BOARD_USING_SECONDARY_QSPI_PINMUX .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromInternally, #else - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, #endif .csHoldTime = 1u, .csSetupTime = 2u, diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/board.c b/ports/mimxrt10xx/boards/imxrt1060_evk/board.c index c3895473e..25bc4e8c9 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board.c @@ -33,7 +33,6 @@ void board_init(void) { // SWD Pins common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);//SWDIO common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);//SWCLK - common_hal_never_reset_pin(&pin_GPIO_AD_B0_10);//SWO // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_00); diff --git a/ports/mimxrt10xx/boards/teensy40/board.c b/ports/mimxrt10xx/boards/teensy40/board.c index a16e90103..09f0bf3f2 100644 --- a/ports/mimxrt10xx/boards/teensy40/board.c +++ b/ports/mimxrt10xx/boards/teensy40/board.c @@ -30,11 +30,6 @@ #include "shared-bindings/microcontroller/Pin.h" void board_init(void) { - // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);//SWCLK - common_hal_never_reset_pin(&pin_GPIO_AD_B0_10);//SWO - // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_06); common_hal_never_reset_pin(&pin_GPIO_SD_B1_07); @@ -43,9 +38,18 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO_SD_B1_10); common_hal_never_reset_pin(&pin_GPIO_SD_B1_11); - // USB Pins - common_hal_never_reset_pin(&pin_GPIO_AD_B0_01); - common_hal_never_reset_pin(&pin_GPIO_AD_B0_03); + // FLEX flash 2 + common_hal_never_reset_pin(&pin_GPIO_AD_B0_04); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_06); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_07); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_08); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_09); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_10); + common_hal_never_reset_pin(&pin_GPIO_EMC_01); + common_hal_never_reset_pin(&pin_GPIO_B0_13); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_11); + // Data strobe needs protection despite being grounded + common_hal_never_reset_pin(&pin_GPIO_SD_B1_05); } bool board_requests_safe_mode(void) { diff --git a/ports/mimxrt10xx/boards/teensy41/board.c b/ports/mimxrt10xx/boards/teensy41/board.c index 52dd498b3..09f0bf3f2 100644 --- a/ports/mimxrt10xx/boards/teensy41/board.c +++ b/ports/mimxrt10xx/boards/teensy41/board.c @@ -27,8 +27,29 @@ #include "boards/board.h" #include "mpconfigboard.h" +#include "shared-bindings/microcontroller/Pin.h" void board_init(void) { + // FLEX flash + common_hal_never_reset_pin(&pin_GPIO_SD_B1_06); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_07); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_08); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_09); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_10); + common_hal_never_reset_pin(&pin_GPIO_SD_B1_11); + + // FLEX flash 2 + common_hal_never_reset_pin(&pin_GPIO_AD_B0_04); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_06); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_07); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_08); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_09); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_10); + common_hal_never_reset_pin(&pin_GPIO_EMC_01); + common_hal_never_reset_pin(&pin_GPIO_B0_13); + common_hal_never_reset_pin(&pin_GPIO_AD_B0_11); + // Data strobe needs protection despite being grounded + common_hal_never_reset_pin(&pin_GPIO_SD_B1_05); } bool board_requests_safe_mode(void) { diff --git a/ports/mimxrt10xx/common-hal/busio/I2C.c b/ports/mimxrt10xx/common-hal/busio/I2C.c index 0bb7dcc6c..aaa2549a8 100644 --- a/ports/mimxrt10xx/common-hal/busio/I2C.c +++ b/ports/mimxrt10xx/common-hal/busio/I2C.c @@ -27,15 +27,32 @@ #include <stdio.h> +#include "shared-bindings/microcontroller/Pin.h" +#include "shared-bindings/microcontroller/__init__.h" #include "shared-bindings/busio/I2C.h" #include "py/mperrno.h" #include "py/runtime.h" #include "periph.h" #include "fsl_lpi2c.h" +#include "fsl_gpio.h" #define I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (1+CLOCK_GetDiv(kCLOCK_Lpi2cDiv))) - +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5 5U + +//arrays use 0 based numbering: I2C1 is stored at index 0 +#define MAX_I2C 4 +STATIC bool reserved_i2c[MAX_I2C]; +STATIC bool never_reset_i2c[MAX_I2C]; + +void i2c_reset(void) { + for(uint i = 0; i < MP_ARRAY_SIZE(mcu_i2c_banks); i++) { + if (!never_reset_i2c[i]) { + reserved_i2c[i] = false; + LPI2C_MasterDeinit(mcu_i2c_banks[i]); + } + } +} static void config_periph_pin(const mcu_periph_obj_t *periph) { IOMUXC_SetPinMux( @@ -56,11 +73,49 @@ static void config_periph_pin(const mcu_periph_obj_t *periph) { | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } +static void i2c_check_pin_config(const mcu_pin_obj_t *pin, uint32_t pull) +{ + IOMUXC_SetPinConfig(0, 0, 0, 0, pin->cfg_reg, + IOMUXC_SW_PAD_CTL_PAD_HYS(1) + | IOMUXC_SW_PAD_CTL_PAD_PUS(0) // Pulldown + | IOMUXC_SW_PAD_CTL_PAD_PUE(pull) // 0=nopull (keeper), 1=pull + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(0) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(1) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); +} + void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) { - const uint32_t sda_count = sizeof(mcu_i2c_sda_list) / sizeof(mcu_periph_obj_t); - const uint32_t scl_count = sizeof(mcu_i2c_scl_list) / sizeof(mcu_periph_obj_t); + #if CIRCUITPY_REQUIRE_I2C_PULLUPS + // Test that the pins are in a high state. (Hopefully indicating they are pulled up.) + IOMUXC_SetPinMux(sda->mux_reg, IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5, 0, 0, 0, 0); + IOMUXC_SetPinMux(scl->mux_reg, IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5, 0, 0, 0, 0); + i2c_check_pin_config(sda, 1); + i2c_check_pin_config(scl, 1); + const gpio_pin_config_t check_config = { kGPIO_DigitalInput, 0, kGPIO_NoIntmode }; + GPIO_PinInit(sda->gpio, sda->number, &check_config); + GPIO_PinInit(scl->gpio, scl->number, &check_config); + + common_hal_mcu_delay_us(10); + + i2c_check_pin_config(sda, 0); + i2c_check_pin_config(scl, 0); + + // We must pull up within 3us to achieve 400khz. + common_hal_mcu_delay_us(3); + + if( !GPIO_PinRead(sda->gpio, sda->number) || !GPIO_PinRead(scl->gpio, scl->number)) { + common_hal_reset_pin(sda); + common_hal_reset_pin(scl); + mp_raise_RuntimeError(translate("SDA or SCL needs a pull up")); + } + #endif + + const uint32_t sda_count = MP_ARRAY_SIZE(mcu_i2c_sda_list); + const uint32_t scl_count = MP_ARRAY_SIZE(mcu_i2c_scl_list); for (uint32_t i = 0; i < sda_count; ++i) { if (mcu_i2c_sda_list[i].pin != sda) @@ -73,21 +128,21 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, if (mcu_i2c_scl_list[j].bank_idx != mcu_i2c_sda_list[i].bank_idx) continue; - self->sda_pin = &mcu_i2c_sda_list[i]; - self->scl_pin = &mcu_i2c_scl_list[j]; + self->sda = &mcu_i2c_sda_list[i]; + self->scl = &mcu_i2c_scl_list[j]; break; } } - if(self->sda_pin == NULL || self->scl_pin == NULL) { - mp_raise_RuntimeError(translate("Invalid I2C pin selection")); + if(self->sda == NULL || self->scl == NULL) { + mp_raise_ValueError(translate("Invalid pins")); } else { - self->i2c = mcu_i2c_banks[self->sda_pin->bank_idx - 1]; + self->i2c = mcu_i2c_banks[self->sda->bank_idx - 1]; } - config_periph_pin(self->sda_pin); - config_periph_pin(self->scl_pin); + config_periph_pin(self->sda); + config_periph_pin(self->scl); lpi2c_master_config_t config = { 0 }; LPI2C_MasterGetDefaultConfig(&config); @@ -96,34 +151,35 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, LPI2C_MasterInit(self->i2c, &config, I2C_CLOCK_FREQ); -#if CIRCUITPY_REQUIRE_I2C_PULLUPS -// if (!gpio_get_pin_level(sda->number) || !gpio_get_pin_level(scl->number)) { -// reset_pin_number(sda->number); -// reset_pin_number(scl->number); -// mp_raise_RuntimeError(translate("SDA or SCL needs a pull up")); -// } -#endif + claim_pin(self->sda->pin); + claim_pin(self->scl->pin); +} + +void common_hal_busio_i2c_never_reset(busio_i2c_obj_t *self) { + never_reset_i2c[self->sda->bank_idx - 1] = true; - claim_pin(self->sda_pin->pin); - claim_pin(self->scl_pin->pin); + common_hal_never_reset_pin(self->sda->pin); + common_hal_never_reset_pin(self->scl->pin); } bool common_hal_busio_i2c_deinited(busio_i2c_obj_t *self) { - return self->sda_pin == NULL; + return self->sda == NULL; } void common_hal_busio_i2c_deinit(busio_i2c_obj_t *self) { if (common_hal_busio_i2c_deinited(self)) { return; } + reserved_i2c[self->sda->bank_idx - 1] = false; + never_reset_i2c[self->sda->bank_idx - 1] = false; LPI2C_MasterDeinit(self->i2c); -// reset_pin_number(self->sda_pin); -// reset_pin_number(self->scl_pin); + common_hal_reset_pin(self->sda->pin); + common_hal_reset_pin(self->scl->pin); - self->sda_pin = NULL; - self->scl_pin = NULL; + self->sda = NULL; + self->scl = NULL; } bool common_hal_busio_i2c_probe(busio_i2c_obj_t *self, uint8_t addr) { @@ -183,10 +239,3 @@ uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, return MP_EIO; } - -void common_hal_busio_i2c_never_reset(busio_i2c_obj_t *self) { -// never_reset_sercom(self->i2c_desc.device.hw); -// -// never_reset_pin_number(self->scl_pin); -// never_reset_pin_number(self->sda_pin); -} diff --git a/ports/mimxrt10xx/common-hal/busio/I2C.h b/ports/mimxrt10xx/common-hal/busio/I2C.h index 924e10811..789f01a5f 100644 --- a/ports/mimxrt10xx/common-hal/busio/I2C.h +++ b/ports/mimxrt10xx/common-hal/busio/I2C.h @@ -37,8 +37,8 @@ typedef struct { mp_obj_base_t base; LPI2C_Type *i2c; bool has_lock; - const mcu_periph_obj_t *scl_pin; - const mcu_periph_obj_t *sda_pin; + const mcu_periph_obj_t *scl; + const mcu_periph_obj_t *sda; } busio_i2c_obj_t; #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_BUSIO_I2C_H diff --git a/ports/mimxrt10xx/common-hal/busio/SPI.c b/ports/mimxrt10xx/common-hal/busio/SPI.c index 15c320140..c51aef4da 100644 --- a/ports/mimxrt10xx/common-hal/busio/SPI.c +++ b/ports/mimxrt10xx/common-hal/busio/SPI.c @@ -25,6 +25,8 @@ * THE SOFTWARE. */ +#include "shared-bindings/microcontroller/Pin.h" +#include "shared-bindings/microcontroller/__init__.h" #include "shared-bindings/busio/SPI.h" #include "py/mperrno.h" #include "py/runtime.h" @@ -34,6 +36,8 @@ #include <stdio.h> +#define LPSPI_MASTER_CLK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1)) + //arrays use 0 based numbering: SPI1 is stored at index 0 #define MAX_SPI 4 STATIC bool reserved_spi[MAX_SPI]; @@ -58,11 +62,12 @@ STATIC void config_periph_pin(const mcu_periph_obj_t *periph) { | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } -#define LPSPI_MASTER_CLK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1)) - void spi_reset(void) { - for (int i = 0; i < MAX_SPI; i++) { - reserved_spi[i] = false; + for (uint i = 0; i < MP_ARRAY_SIZE(mcu_spi_banks); i++) { + if (!never_reset_spi[i]) { + reserved_spi[i] = false; + LPSPI_Deinit(mcu_spi_banks[i]); + } } } @@ -82,7 +87,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, //if both MOSI and MISO exist, loop search normally if ((mosi != NULL) && (miso != NULL)) { for (uint j = 0; j < mosi_count; j++) { - if ((mcu_spi_mosi_list[i].pin != mosi) + if ((mcu_spi_mosi_list[i].pin != mosi) || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)){ continue; } @@ -91,10 +96,10 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, || (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[k].bank_idx)) { continue; } - //keep looking if the SPI is taken, edge case + // if SPI is taken, break (pins never have >1 periph) if (reserved_spi[mcu_spi_sck_list[i].bank_idx - 1]) { spi_taken = true; - continue; + break; } //store pins if not self->clock = &mcu_spi_sck_list[i]; @@ -102,11 +107,11 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, self->miso = &mcu_spi_miso_list[k]; break; } - if (self->clock != NULL) { + if (self->clock != NULL || spi_taken) { break; // Multi-level break to pick lowest peripheral } } - if (self->clock != NULL) { + if (self->clock != NULL || spi_taken) { break; } // if just MISO, reduce search @@ -118,14 +123,13 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, } if (reserved_spi[mcu_spi_sck_list[i].bank_idx - 1]) { spi_taken = true; - continue; + break; } self->clock = &mcu_spi_sck_list[i]; - self->mosi = NULL; self->miso = &mcu_spi_miso_list[j]; break; } - if (self->clock != NULL) { + if (self->clock != NULL || spi_taken) { break; } // if just MOSI, reduce search @@ -137,14 +141,13 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, } if (reserved_spi[mcu_spi_sck_list[i].bank_idx - 1]) { spi_taken = true; - continue; + break; } self->clock = &mcu_spi_sck_list[i]; self->mosi = &mcu_spi_mosi_list[j]; - self->miso = NULL; break; } - if (self->clock != NULL) { + if (self->clock != NULL || spi_taken) { break; } } else { @@ -159,7 +162,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, if (spi_taken) { mp_raise_ValueError(translate("Hardware busy, try alternative pins")); } else { - mp_raise_ValueError(translate("Invalid SPI pin selection")); + mp_raise_ValueError(translate("Invalid pins")); } } @@ -194,7 +197,14 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, } void common_hal_busio_spi_never_reset(busio_spi_obj_t *self) { - // TODO + never_reset_spi[self->clock->bank_idx - 1] = true; + common_hal_never_reset_pin(self->clock->pin); + if (self->mosi != NULL) { + common_hal_never_reset_pin(self->mosi->pin); + } + if (self->miso != NULL) { + common_hal_never_reset_pin(self->miso->pin); + } } bool common_hal_busio_spi_deinited(busio_spi_obj_t *self) { @@ -205,8 +215,20 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { if (common_hal_busio_spi_deinited(self)) { return; } + LPSPI_Deinit(self->spi); + reserved_spi[self->clock->bank_idx - 1] = false; + never_reset_spi[self->clock->bank_idx - 1] = false; + common_hal_reset_pin(self->clock->pin); + if (self->mosi != NULL) { + common_hal_reset_pin(self->mosi->pin); + } + if (self->miso != NULL) { + common_hal_reset_pin(self->miso->pin); + } self->clock = NULL; + self->mosi = NULL; + self->miso = NULL; } bool common_hal_busio_spi_configure(busio_spi_obj_t *self, diff --git a/ports/mimxrt10xx/common-hal/busio/UART.c b/ports/mimxrt10xx/common-hal/busio/UART.c index fbb45eeea..5ef347e59 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.c +++ b/ports/mimxrt10xx/common-hal/busio/UART.c @@ -25,6 +25,7 @@ * THE SOFTWARE. */ +#include "shared-bindings/microcontroller/Pin.h" #include "shared-bindings/microcontroller/__init__.h" #include "shared-bindings/busio/UART.h" @@ -39,7 +40,9 @@ #include "fsl_lpuart.h" -// TODO +//arrays use 0 based numbering: UART1 is stored at index 0 +#define MAX_UART 8 +STATIC bool reserved_uart[MAX_UART]; #define UART_CLOCK_FREQ (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U) @@ -71,6 +74,13 @@ void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t st } } +void uart_reset(void) { + for(uint i = 0; i < MP_ARRAY_SIZE(mcu_uart_banks); i++) { + reserved_uart[i] = false; + LPUART_Deinit(mcu_uart_banks[i]); + } +} + void common_hal_busio_uart_construct(busio_uart_obj_t *self, const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx, const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts, @@ -79,109 +89,159 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer, bool sigint_enabled) { - // TODO: Allow none rx or tx - - bool have_tx = tx != NULL; - bool have_rx = rx != NULL; - if (!have_tx && !have_rx) { - mp_raise_ValueError(translate("tx and rx cannot both be None")); - } - self->baudrate = baudrate; self->character_bits = bits; self->timeout_ms = timeout * 1000; - const uint32_t rx_count = sizeof(mcu_uart_rx_list) / sizeof(mcu_periph_obj_t); - const uint32_t tx_count = sizeof(mcu_uart_tx_list) / sizeof(mcu_periph_obj_t); + // We are transmitting one direction if one pin is NULL and the other isn't. + bool is_onedirection = (rx != NULL) != (tx != NULL); + bool uart_taken = false; - for (uint32_t i = 0; i < rx_count; ++i) { - if (mcu_uart_rx_list[i].pin != rx) - continue; + const uint32_t rx_count = MP_ARRAY_SIZE(mcu_uart_rx_list); + const uint32_t tx_count = MP_ARRAY_SIZE(mcu_uart_tx_list); - for (uint32_t j = 0; j < tx_count; ++j) { - if (mcu_uart_tx_list[j].pin != tx) + // RX loop handles rx only, or both rx and tx + if (rx != NULL) { + for (uint32_t i = 0; i < rx_count; ++i) { + if (mcu_uart_rx_list[i].pin != rx) { continue; - - if (mcu_uart_tx_list[j].bank_idx != mcu_uart_rx_list[i].bank_idx) + } + // If TX is on, keep looking, else stop + if (tx != NULL) { + for (uint32_t j = 0; j < tx_count; ++j) { + if (mcu_uart_tx_list[j].pin != tx || + mcu_uart_tx_list[j].bank_idx != mcu_uart_rx_list[i].bank_idx) { + continue; + } + // If UART is taken, break (pins never have >1 periph) + if (reserved_uart[mcu_uart_rx_list[i].bank_idx - 1]) { + uart_taken = true; + break; + } + self->rx = &mcu_uart_rx_list[i]; + self->tx = &mcu_uart_tx_list[j]; + break; + } + if (self->tx != NULL || uart_taken) { + break; + } + } else { + if (reserved_uart[mcu_uart_rx_list[i].bank_idx - 1]) { + uart_taken = true; + break; + } + self->rx = &mcu_uart_rx_list[i]; + } + } + } else if (tx != NULL) { + // TX only case + for (uint32_t i = 0; i < tx_count; ++i) { + if (mcu_uart_tx_list[i].pin != tx) { continue; - - self->rx_pin = &mcu_uart_rx_list[i]; - self->tx_pin = &mcu_uart_tx_list[j]; - + } + if (reserved_uart[mcu_uart_tx_list[i].bank_idx - 1]) { + uart_taken = true; + break; + } + self->tx = &mcu_uart_tx_list[i]; break; } + } else { + mp_raise_ValueError(translate("Supply at least one UART pin")); + } + + if (uart_taken) { + mp_raise_ValueError(translate("Hardware in use, try alternative pins")); + } + + if(self->rx == NULL && self->tx == NULL) { + mp_raise_ValueError(translate("Invalid pins")); } - if(self->rx_pin == NULL || self->tx_pin == NULL) { - mp_raise_RuntimeError(translate("Invalid UART pin selection")); + if (is_onedirection && ((rts != NULL) || (cts != NULL))) { + mp_raise_ValueError(translate("Both RX and TX required for flow control")); } // Filter for sane settings for RS485 if (rs485_dir != NULL) { - if ((rts != NULL) || (cts != NULL)) { - mp_raise_ValueError(translate("Cannot specify RTS or CTS in RS485 mode")); - } - // For IMXRT the RTS pin is used for RS485 direction - rts = rs485_dir; + if ((rts != NULL) || (cts != NULL)) { + mp_raise_ValueError(translate("Cannot specify RTS or CTS in RS485 mode")); + } + // For IMXRT the RTS pin is used for RS485 direction + rts = rs485_dir; } else { - if (rs485_invert) { - mp_raise_ValueError(translate("RS485 inversion specified when not in RS485 mode")); - } + if (rs485_invert) { + mp_raise_ValueError(translate("RS485 inversion specified when not in RS485 mode")); + } } // Now check for RTS/CTS (or overloaded RS485 direction) pin(s) - const uint32_t rts_count = sizeof(mcu_uart_rts_list) / sizeof(mcu_periph_obj_t); - const uint32_t cts_count = sizeof(mcu_uart_cts_list) / sizeof(mcu_periph_obj_t); + const uint32_t rts_count = MP_ARRAY_SIZE(mcu_uart_rts_list); + const uint32_t cts_count = MP_ARRAY_SIZE(mcu_uart_cts_list); if (rts != NULL) { - for (uint32_t i=0; i < rts_count; ++i) { - if (mcu_uart_rts_list[i].bank_idx == self->rx_pin->bank_idx) { - if (mcu_uart_rts_list[i].pin == rts) { - self->rts_pin = &mcu_uart_rts_list[i]; - break; - } + for (uint32_t i=0; i < rts_count; ++i) { + if (mcu_uart_rts_list[i].bank_idx == self->rx->bank_idx) { + if (mcu_uart_rts_list[i].pin == rts) { + self->rts = &mcu_uart_rts_list[i]; + break; + } + } + } + if (self->rts == NULL){ + mp_raise_ValueError(translate("Selected RTS pin not valid")); } - } - if (self->rts_pin == NULL) - mp_raise_ValueError(translate("Selected RTS pin not valid")); } if (cts != NULL) { - for (uint32_t i=0; i < cts_count; ++i) { - if (mcu_uart_cts_list[i].bank_idx == self->rx_pin->bank_idx) { - if (mcu_uart_cts_list[i].pin == cts) { - self->cts_pin = &mcu_uart_cts_list[i]; - break; - } + for (uint32_t i=0; i < cts_count; ++i) { + if (mcu_uart_cts_list[i].bank_idx == self->rx->bank_idx) { + if (mcu_uart_cts_list[i].pin == cts) { + self->cts = &mcu_uart_cts_list[i]; + break; + } + } + } + if (self->cts == NULL){ + mp_raise_ValueError(translate("Selected CTS pin not valid")); } - } - if (self->cts_pin == NULL) - mp_raise_ValueError(translate("Selected CTS pin not valid")); } - self->uart = mcu_uart_banks[self->tx_pin->bank_idx - 1]; + if (self->rx) { + self->uart = mcu_uart_banks[self->rx->bank_idx - 1]; + } else { + self->uart = mcu_uart_banks[self->tx->bank_idx - 1]; + } - config_periph_pin(self->rx_pin); - config_periph_pin(self->tx_pin); - if (self->rts_pin) - config_periph_pin(self->rts_pin); - if (self->cts_pin) - config_periph_pin(self->cts_pin); + if (self->rx) { + config_periph_pin(self->rx); + } + if (self->tx) { + config_periph_pin(self->tx); + } + if (self->rts) { + config_periph_pin(self->rts); + } + if (self->cts) { + config_periph_pin(self->cts); + } lpuart_config_t config = { 0 }; LPUART_GetDefaultConfig(&config); config.dataBitsCount = self->character_bits == 8 ? kLPUART_EightDataBits : kLPUART_SevenDataBits; config.baudRate_Bps = self->baudrate; - config.enableTx = self->tx_pin != NULL; - config.enableRx = self->rx_pin != NULL; - config.enableRxRTS = self->rts_pin != NULL; - config.enableTxCTS = self->cts_pin != NULL; - if (self->rts_pin != NULL) - claim_pin(self->rts_pin->pin); - if (self->cts_pin != NULL) - claim_pin(self->cts_pin->pin); + config.enableTx = self->tx != NULL; + config.enableRx = self->rx != NULL; + config.enableRxRTS = self->rts != NULL; + config.enableTxCTS = self->cts != NULL; + if (self->rts != NULL) { + claim_pin(self->rts->pin); + } + if (self->cts != NULL) { + claim_pin(self->cts->pin); + } LPUART_Init(self->uart, &config, UART_CLOCK_FREQ); @@ -189,16 +249,18 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, // ..unfortunately this isn't done by the driver library uint32_t modir = (self->uart->MODIR) & ~(LPUART_MODIR_TXRTSPOL_MASK | LPUART_MODIR_TXRTSE_MASK); if (rs485_dir != NULL) { - modir |= LPUART_MODIR_TXRTSE_MASK; - if (rs485_invert) - modir |= LPUART_MODIR_TXRTSPOL_MASK; + modir |= LPUART_MODIR_TXRTSE_MASK; + if (rs485_invert) { + modir |= LPUART_MODIR_TXRTSPOL_MASK; + } } self->uart->MODIR = modir; - if (self->tx_pin != NULL) - claim_pin(self->tx_pin->pin); + if (self->tx != NULL) { + claim_pin(self->tx->pin); + } - if (self->rx_pin != NULL) { + if (self->rx != NULL) { // The LPUART ring buffer wastes one byte to distinguish between full and empty. self->ringbuf = gc_alloc(receiver_buffer_size + 1, false, true /*long-lived*/); @@ -212,33 +274,41 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, // the capacity is one less than the size. LPUART_TransferStartRingBuffer(self->uart, &self->handle, self->ringbuf, receiver_buffer_size + 1); - claim_pin(self->rx_pin->pin); + claim_pin(self->rx->pin); } } bool common_hal_busio_uart_deinited(busio_uart_obj_t *self) { - return self->rx_pin == NULL && self->tx_pin == NULL; + return self->rx == NULL && self->tx == NULL; } void common_hal_busio_uart_deinit(busio_uart_obj_t *self) { if (common_hal_busio_uart_deinited(self)) { return; } + if (self->rx) { + reserved_uart[self->rx->bank_idx - 1] = false; + } else { + reserved_uart[self->tx->bank_idx - 1] = false; + } LPUART_Deinit(self->uart); - gc_free(self->ringbuf); -// reset_pin_number(self->rx_pin); -// reset_pin_number(self->tx_pin); + if (self->rx) { + common_hal_reset_pin(self->rx->pin); + } + if (self->tx) { + common_hal_reset_pin(self->tx->pin); + } - self->rx_pin = NULL; - self->tx_pin = NULL; + self->rx = NULL; + self->tx = NULL; } // Read characters. size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t len, int *errcode) { - if (self->rx_pin == NULL) { + if (self->rx == NULL) { mp_raise_ValueError(translate("No RX pin")); } @@ -284,7 +354,7 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t // Write characters. size_t common_hal_busio_uart_write(busio_uart_obj_t *self, const uint8_t *data, size_t len, int *errcode) { - if (self->tx_pin == NULL) { + if (self->tx == NULL) { mp_raise_ValueError(translate("No TX pin")); } @@ -320,7 +390,7 @@ void common_hal_busio_uart_clear_rx_buffer(busio_uart_obj_t *self) { } bool common_hal_busio_uart_ready_to_tx(busio_uart_obj_t *self) { - if (self->tx_pin == NULL) { + if (self->tx == NULL) { return false; } diff --git a/ports/mimxrt10xx/common-hal/busio/UART.h b/ports/mimxrt10xx/common-hal/busio/UART.h index 3a326eb3a..94a5fb02c 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.h +++ b/ports/mimxrt10xx/common-hal/busio/UART.h @@ -45,10 +45,10 @@ typedef struct { uint32_t baudrate; uint8_t character_bits; uint32_t timeout_ms; - const mcu_periph_obj_t *rx_pin; - const mcu_periph_obj_t *tx_pin; - const mcu_periph_obj_t *cts_pin; - const mcu_periph_obj_t *rts_pin; + const mcu_periph_obj_t *rx; + const mcu_periph_obj_t *tx; + const mcu_periph_obj_t *cts; + const mcu_periph_obj_t *rts; } busio_uart_obj_t; #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_BUSIO_UART_H diff --git a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c index 4931599d4..e4eda9f4f 100644 --- a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c +++ b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c @@ -97,7 +97,7 @@ void common_hal_digitalio_digitalinout_switch_to_input( common_hal_digitalio_digitalinout_set_pull(self, pull); } -void common_hal_digitalio_digitalinout_switch_to_output( +digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( digitalio_digitalinout_obj_t* self, bool value, digitalio_drive_mode_t drive_mode) { self->output = true; @@ -108,6 +108,7 @@ void common_hal_digitalio_digitalinout_switch_to_output( const gpio_pin_config_t config = { kGPIO_DigitalOutput, value, kGPIO_NoIntmode }; GPIO_PinInit(self->pin->gpio, self->pin->number, &config); + return DIGITALINOUT_OK; } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( @@ -125,7 +126,7 @@ bool common_hal_digitalio_digitalinout_get_value( return GPIO_PinRead(self->pin->gpio, self->pin->number); } -void common_hal_digitalio_digitalinout_set_drive_mode( +digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( digitalio_digitalinout_obj_t* self, digitalio_drive_mode_t drive_mode) { bool value = common_hal_digitalio_digitalinout_get_value(self); @@ -138,6 +139,7 @@ void common_hal_digitalio_digitalinout_set_drive_mode( if (value) { common_hal_digitalio_digitalinout_set_value(self, value); } + return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Pin.c b/ports/mimxrt10xx/common-hal/microcontroller/Pin.c index e75df6e60..a005924e2 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Pin.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/Pin.c @@ -5,6 +5,7 @@ * * Copyright (c) 2016 Scott Shawcroft for Adafruit Industries * Copyright (c) 2019 Artur Pacholec + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -40,8 +41,8 @@ STATIC bool claimed_pins[IOMUXC_SW_PAD_CTL_PAD_COUNT]; STATIC bool never_reset_pins[IOMUXC_SW_PAD_CTL_PAD_COUNT]; // There are two numbering systems used here: -// IOMUXC index, used for iterating through pins and accessing reset information, -// and GPIO port and number, used to store claimed and reset tagging. The two number +// IOMUXC index, used for iterating through pins and accessing reset information, +// and GPIO port and number, used to store claimed and reset tagging. The two number // systems are not related and one cannot determine the other without a pin object void reset_all_pins(void) { for (uint8_t i = 0; i < IOMUXC_SW_PAD_CTL_PAD_COUNT; i++) { @@ -63,8 +64,8 @@ void reset_all_pins(void) { #endif } -// Since i.MX pins need extra register and reset information to reset properly, -// resetting pins by number alone has been removed. +// Since i.MX pins need extra register and reset information to reset properly, +// resetting pins by number alone has been removed. void common_hal_reset_pin(const mcu_pin_obj_t* pin) { never_reset_pins[pin->mux_idx] = false; claimed_pins[pin->mux_idx] = false; diff --git a/ports/mimxrt10xx/common-hal/supervisor/__init__.c b/ports/mimxrt10xx/common-hal/supervisor/__init__.c index ac88556b4..6dca35fb5 100755 --- a/ports/mimxrt10xx/common-hal/supervisor/__init__.c +++ b/ports/mimxrt10xx/common-hal/supervisor/__init__.c @@ -37,4 +37,4 @@ const super_runtime_obj_t common_hal_supervisor_runtime_obj = { .base = { .type = &supervisor_runtime_type, }, -};
\ No newline at end of file +}; diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c index 2fed6dfc6..a994e154d 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c @@ -29,7 +29,7 @@ #include "py/mphal.h" #include "mimxrt10xx/periph.h" -LPI2C_Type *mcu_i2c_banks[] = { LPI2C1, LPI2C2 }; +LPI2C_Type *mcu_i2c_banks[2] = { LPI2C1, LPI2C2 }; const mcu_periph_obj_t mcu_i2c_sda_list[8] = { PERIPH_PIN(1, 0, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 0, &pin_GPIO_AD_13), @@ -55,7 +55,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[8] = { PERIPH_PIN(2, 3, kIOMUXC_LPI2C2_SCL_SELECT_INPUT, 3, &pin_GPIO_10), }; -LPSPI_Type *mcu_spi_banks[] = { LPSPI1, LPSPI2 }; +LPSPI_Type *mcu_spi_banks[2] = { LPSPI1, LPSPI2 }; const mcu_periph_obj_t mcu_spi_sck_list[4] = { PERIPH_PIN(1, 0, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_06), @@ -81,7 +81,7 @@ const mcu_periph_obj_t mcu_spi_miso_list[4] = { PERIPH_PIN(2, 1, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 1, &pin_GPIO_SD_09), }; -LPUART_Type *mcu_uart_banks[] = { LPUART1, LPUART2, LPUART3, LPUART4 }; +LPUART_Type *mcu_uart_banks[4] = { LPUART1, LPUART2, LPUART3, LPUART4 }; const mcu_periph_obj_t mcu_uart_rx_list[9] = { PERIPH_PIN(1, 2, kIOMUXC_LPUART1_RXD_SELECT_INPUT, 0, &pin_GPIO_SD_11), @@ -115,7 +115,7 @@ const mcu_periph_obj_t mcu_uart_tx_list[9] = { const mcu_periph_obj_t mcu_uart_rts_list[4] = { PERIPH_PIN(1, 6, 0, 0, &pin_GPIO_07), - + PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_07), PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_13), diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h index d6d489537..3bc86f33a 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h @@ -27,13 +27,19 @@ #ifndef MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1011_PERIPH_H #define MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1011_PERIPH_H +LPI2C_Type *mcu_i2c_banks[2]; + extern const mcu_periph_obj_t mcu_i2c_sda_list[8]; extern const mcu_periph_obj_t mcu_i2c_scl_list[8]; +LPSPI_Type *mcu_spi_banks[2]; + extern const mcu_periph_obj_t mcu_spi_sck_list[4]; extern const mcu_periph_obj_t mcu_spi_mosi_list[4]; extern const mcu_periph_obj_t mcu_spi_miso_list[4]; +LPUART_Type *mcu_uart_banks[4]; + extern const mcu_periph_obj_t mcu_uart_rx_list[9]; extern const mcu_periph_obj_t mcu_uart_tx_list[9]; extern const mcu_periph_obj_t mcu_uart_rts_list[4]; diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c index 60f301668..3d043a14e 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c @@ -30,7 +30,7 @@ #include "py/mphal.h" #include "mimxrt10xx/periph.h" -LPI2C_Type *mcu_i2c_banks[] = { LPI2C1, LPI2C2, LPI2C3, LPI2C4 }; +LPI2C_Type *mcu_i2c_banks[4] = { LPI2C1, LPI2C2, LPI2C3, LPI2C4 }; const mcu_periph_obj_t mcu_i2c_sda_list[8] = { PERIPH_PIN(1, 6, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 0, &pin_GPIO_EMC_03), @@ -60,7 +60,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[8] = { PERIPH_PIN(4, 3, kIOMUXC_LPI2C4_SCL_SELECT_INPUT, 1, &pin_GPIO_SD_B1_02), }; -LPSPI_Type *mcu_spi_banks[] = { LPSPI1, LPSPI2, LPSPI3, LPSPI4 }; +LPSPI_Type *mcu_spi_banks[4] = { LPSPI1, LPSPI2, LPSPI3, LPSPI4 }; const mcu_periph_obj_t mcu_spi_sck_list[8] = { PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 0, &pin_GPIO_SD_B0_02), @@ -104,7 +104,7 @@ const mcu_periph_obj_t mcu_spi_miso_list[8] = { PERIPH_PIN(4, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 1, &pin_GPIO_EMC_35), }; -LPUART_Type *mcu_uart_banks[] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }; +LPUART_Type *mcu_uart_banks[8] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }; const mcu_periph_obj_t mcu_uart_rx_list[16] = { PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_07), @@ -160,7 +160,7 @@ const mcu_periph_obj_t mcu_uart_tx_list[16] = { const mcu_periph_obj_t mcu_uart_rts_list[10] = { PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_09), - + PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_EMC_21), PERIPH_PIN(2, 2, 0, 1, &pin_GPIO_AD_B1_07), diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.h index ba88ef4c6..814bc5f6c 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.h +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.h @@ -28,13 +28,19 @@ #ifndef MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PERIPH_H #define MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PERIPH_H +LPI2C_Type *mcu_i2c_banks[4]; + extern const mcu_periph_obj_t mcu_i2c_sda_list[8]; extern const mcu_periph_obj_t mcu_i2c_scl_list[8]; +LPSPI_Type *mcu_spi_banks[4]; + extern const mcu_periph_obj_t mcu_spi_sck_list[8]; extern const mcu_periph_obj_t mcu_spi_mosi_list[8]; extern const mcu_periph_obj_t mcu_spi_miso_list[8]; +LPUART_Type *mcu_uart_banks[8]; + extern const mcu_periph_obj_t mcu_uart_rx_list[16]; extern const mcu_periph_obj_t mcu_uart_tx_list[16]; extern const mcu_periph_obj_t mcu_uart_rts_list[10]; diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c index 9a1a4ab65..fd1e4ddb8 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c @@ -29,7 +29,7 @@ #include "py/mphal.h" #include "mimxrt10xx/periph.h" -LPI2C_Type *mcu_i2c_banks[] = { LPI2C1, LPI2C2, LPI2C3, LPI2C4 }; +LPI2C_Type *mcu_i2c_banks[4] = { LPI2C1, LPI2C2, LPI2C3, LPI2C4 }; const mcu_periph_obj_t mcu_i2c_sda_list[9] = { PERIPH_PIN(1, 2, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 0, &pin_GPIO_SD_B1_05), @@ -61,7 +61,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[9] = { PERIPH_PIN(4, 0, kIOMUXC_LPI2C4_SCL_SELECT_INPUT, 1, &pin_GPIO_AD_B0_12), }; -LPSPI_Type *mcu_spi_banks[] = { LPSPI1, LPSPI2, LPSPI3, LPSPI4 }; +LPSPI_Type *mcu_spi_banks[4] = { LPSPI1, LPSPI2, LPSPI3, LPSPI4 }; const mcu_periph_obj_t mcu_spi_sck_list[8] = { PERIPH_PIN(1, 3, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 0, &pin_GPIO_EMC_27), @@ -105,7 +105,7 @@ const mcu_periph_obj_t mcu_spi_miso_list[8] = { PERIPH_PIN(4, 1, kIOMUXC_LPSPI4_SDI_SELECT_INPUT, 1, &pin_GPIO_B1_05), }; -LPUART_Type *mcu_uart_banks[] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }; +LPUART_Type *mcu_uart_banks[8] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }; const mcu_periph_obj_t mcu_uart_rx_list[18] = { PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_13), @@ -165,7 +165,7 @@ const mcu_periph_obj_t mcu_uart_tx_list[18] = { const mcu_periph_obj_t mcu_uart_rts_list[9] = { PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_15), - + PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_01), PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_05), @@ -188,7 +188,7 @@ const mcu_periph_obj_t mcu_uart_cts_list[9] = { PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_00), PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 0, &pin_GPIO_EMC_15), - PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 1, &pin_GPIO_AD_B1_04), + PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 1, &pin_GPIO_AD_B1_04), PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_17), diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h index 45b92f247..35ac4fc9b 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h @@ -27,13 +27,19 @@ #ifndef MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1011_PERIPH_H #define MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1011_PERIPH_H +LPI2C_Type *mcu_i2c_banks[4]; + extern const mcu_periph_obj_t mcu_i2c_sda_list[9]; extern const mcu_periph_obj_t mcu_i2c_scl_list[9]; +LPSPI_Type *mcu_spi_banks[4]; + extern const mcu_periph_obj_t mcu_spi_sck_list[8]; extern const mcu_periph_obj_t mcu_spi_mosi_list[8]; extern const mcu_periph_obj_t mcu_spi_miso_list[8]; +LPUART_Type *mcu_uart_banks[8]; + extern const mcu_periph_obj_t mcu_uart_rx_list[18]; extern const mcu_periph_obj_t mcu_uart_tx_list[18]; extern const mcu_periph_obj_t mcu_uart_rts_list[9]; diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c index 9f25225bb..ce098ea2b 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c @@ -141,15 +141,15 @@ const mcu_pin_obj_t pin_GPIO_SD_B0_02 = PIN(GPIO3, 14, GPIO_SD_B0_02, NO_ADC, 0, const mcu_pin_obj_t pin_GPIO_SD_B0_03 = PIN(GPIO3, 15, GPIO_SD_B0_03, NO_ADC, 0, 0x00000005, 0x000010B0); const mcu_pin_obj_t pin_GPIO_SD_B0_04 = PIN(GPIO3, 16, GPIO_SD_B0_04, NO_ADC, 0, 0x00000005, 0x000010B0); const mcu_pin_obj_t pin_GPIO_SD_B0_05 = PIN(GPIO3, 17, GPIO_SD_B0_05, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_00 = PIN(GPIO3, 0, GPIO_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_01 = PIN(GPIO3, 1, GPIO_B1_01, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_02 = PIN(GPIO3, 2, GPIO_B1_02, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_03 = PIN(GPIO3, 3, GPIO_B1_03, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_04 = PIN(GPIO3, 4, GPIO_B1_04, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_05 = PIN(GPIO3, 5, GPIO_B1_05, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_06 = PIN(GPIO3, 6, GPIO_B1_06, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_07 = PIN(GPIO3, 7, GPIO_B1_07, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_08 = PIN(GPIO3, 8, GPIO_B1_08, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_09 = PIN(GPIO3, 9, GPIO_B1_09, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_10 = PIN(GPIO3, 10, GPIO_B1_10, NO_ADC, 0, 0x00000005, 0x000010B0); -const mcu_pin_obj_t pin_GPIO_SD_B1_11 = PIN(GPIO3, 11, GPIO_B1_11, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_00 = PIN(GPIO3, 0, GPIO_SD_B1_00, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_01 = PIN(GPIO3, 1, GPIO_SD_B1_01, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_02 = PIN(GPIO3, 2, GPIO_SD_B1_02, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_03 = PIN(GPIO3, 3, GPIO_SD_B1_03, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_04 = PIN(GPIO3, 4, GPIO_SD_B1_04, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_05 = PIN(GPIO3, 5, GPIO_SD_B1_05, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_06 = PIN(GPIO3, 6, GPIO_SD_B1_06, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_07 = PIN(GPIO3, 7, GPIO_SD_B1_07, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_08 = PIN(GPIO3, 8, GPIO_SD_B1_08, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_09 = PIN(GPIO3, 9, GPIO_SD_B1_09, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_10 = PIN(GPIO3, 10, GPIO_SD_B1_10, NO_ADC, 0, 0x00000005, 0x000010B0); +const mcu_pin_obj_t pin_GPIO_SD_B1_11 = PIN(GPIO3, 11, GPIO_SD_B1_11, NO_ADC, 0, 0x00000005, 0x000010B0); diff --git a/ports/mimxrt10xx/supervisor/internal_flash.c b/ports/mimxrt10xx/supervisor/internal_flash.c index 4f52748ed..9abd15e60 100644 --- a/ports/mimxrt10xx/supervisor/internal_flash.c +++ b/ports/mimxrt10xx/supervisor/internal_flash.c @@ -254,4 +254,3 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 void supervisor_flash_release_cache(void) { } - diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c index b6ae00293..ed5824732 100644 --- a/ports/mimxrt10xx/supervisor/port.c +++ b/ports/mimxrt10xx/supervisor/port.c @@ -257,8 +257,8 @@ safe_mode_t port_init(void) { // enabled. It won't occur very often so it'll be low overhead. NVIC_EnableIRQ(SNVS_HP_WRAPPER_IRQn); - // Reset everything into a known state before board_init. - reset_port(); + // Note that `reset_port` CANNOT GO HERE, unlike other ports, because `board_init` hasn't been + // run yet, which uses `never_reset` to protect critical pins from being reset by `reset_port`. if (board_requests_safe_mode()) { return USER_SAFE_MODE; diff --git a/ports/mimxrt10xx/supervisor/serial.c b/ports/mimxrt10xx/supervisor/serial.c index 22c979cf9..01656a819 100644 --- a/ports/mimxrt10xx/supervisor/serial.c +++ b/ports/mimxrt10xx/supervisor/serial.c @@ -90,4 +90,3 @@ void serial_write_substring(const char *text, uint32_t len) { LPUART_WriteBlocking(uart_instance, (uint8_t*)text, len); } - diff --git a/ports/nrf/Makefile b/ports/nrf/Makefile index 8a7b1104b..5b81fa9a7 100755 --- a/ports/nrf/Makefile +++ b/ports/nrf/Makefile @@ -93,7 +93,7 @@ else endif -CFLAGS += $(INC) -Wall -Werror -std=gnu11 -nostdlib $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) +CFLAGS += $(INC) -Wall -Werror -std=gnu11 -nostdlib -fshort-enums $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) # Undo some warnings. # nrfx uses undefined preprocessor variables quite casually, so we can't do warning checks for these. @@ -114,7 +114,7 @@ CFLAGS += \ # TODO: check this CFLAGS += -D__START=main -LDFLAGS = $(CFLAGS) -nostartfiles -fshort-enums -Wl,-nostdlib -Wl,-T,$(GENERATED_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs +LDFLAGS = $(CFLAGS) -nostartfiles -Wl,-nostdlib -Wl,-T,$(GENERATED_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs LIBS := -lgcc -lc LDFLAGS += -mthumb -mcpu=cortex-m4 @@ -136,6 +136,7 @@ SRC_NRFX = $(addprefix nrfx/,\ drivers/src/nrfx_gpiote.c \ drivers/src/nrfx_rtc.c \ drivers/src/nrfx_nvmc.c \ + drivers/src/nrfx_wdt.c \ ) ifdef EXTERNAL_FLASH_DEVICES diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/doc/ble_api.dox b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/doc/ble_api.dox index a444c5e4e..ecabf96aa 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/doc/ble_api.dox +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/doc/ble_api.dox @@ -968,11 +968,11 @@ * |||; * SD<-ADVERTISERS [label = "Scannable Advertisement (ADV_SCAN_IND)", textcolor="#000080", linecolor="#000080"]; * SD->ADVERTISERS [label = "Scan Request (SCAN_REQ)", textcolor="#000080", linecolor="#000080"]; - * SD<-ADVERTISERS [label = "Scan Response (SCAN_RSP)", textcolor="#000080", linecolor="#000080"]; + * SD<-ADVERTISERS [label = "Scan Response (SCAN_RSP)", textcolor="#000080", linecolor="#000080"]; * APP<<=SD [label = "BLE_GAP_EVT_ADV_REPORT {bdaddr, rssi, data}"]; - * ...; - * APP<<=SD [label = "BLE_GAP_EVT_TIMEOUT {BLE_GAP_TIMEOUT_SRC_SCAN}"]; - * |||; + * ...; + * APP<<=SD [label = "BLE_GAP_EVT_TIMEOUT {BLE_GAP_TIMEOUT_SRC_SCAN}"]; + * |||; * @endmsc * @defgroup BLE_GAP_SCAN_MSC_AE Scanning for advertisers performing legacy and extended advertising * @msc @@ -1011,7 +1011,7 @@ * APP<<=SD [label = "BLE_GAP_EVT_ADV_REPORT {type : {extended_pdu = 1, scannable = 1, scan_response = 1}, data}"]; * APP=>SD [label = "sd_ble_gap_scan_start(params = NULL, adv_report_buffer)"]; * APP<<SD [label = "NRF_SUCCESS"]; - * SD<-ADVERTISERS [label = "Legacy Scannable Advertisement (ADV_SCAN_IND) with adv_data ", textcolor="#000080", linecolor="#000080"]; + * SD<-ADVERTISERS [label = "Legacy Scannable Advertisement (ADV_SCAN_IND) with adv_data ", textcolor="#000080", linecolor="#000080"]; * SD->ADVERTISERS [label = "Legacy Scan Request (SCAN_REQ)", textcolor="#000080", linecolor="#000080"]; * APP<<=SD [label = "BLE_GAP_EVT_ADV_REPORT {type : {extended_pdu = 0, scannable = 1, scan_response = 0}, adv_data}"]; * APP=>SD [label = "sd_ble_gap_scan_start(params = NULL, adv_report_buffer)"]; @@ -1030,8 +1030,8 @@ * --- [label = " Variant #2 Reporting incomplete advertising reports"]; * |||; * APP=>SD [label = "sd_ble_gap_scan_start(params : {extended = 1, report_incomplete_evts = 1}, adv_report_buffer)"]; - * APP<<SD [label = "NRF_SUCCESS"]; - * |||; + * APP<<SD [label = "NRF_SUCCESS"]; + * |||; * SD<-ADVERTISERS [label = "Advertisement (ADV_*_IND)", textcolor="#000080", linecolor="#000080"]; * APP<<=SD [label = "BLE_GAP_EVT_ADV_REPORT {type : status = BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, aux_pointer}"]; * |||; @@ -1052,7 +1052,7 @@ * @defgroup BLE_GAP_CENTRAL_CONN_MSC Central Connection Establishment and Termination * @{ * @defgroup BLE_GAP_CENTRAL_CONN_MSC_LEGACY Connecting to legacy advertisers - + * @msc * hscale = "1.5"; * APP,SD,PERIPHERAL; @@ -1114,9 +1114,9 @@ * SD rbox SD [label = "Connection timeout reached"]; * |||; * APP<<=SD [label = "BLE_GAP_EVT_TIMEOUT {BLE_GAP_TIMEOUT_SRC_CONN}"]; - * @endmsc + * @endmsc * @} - + * * @defgroup BLE_GAP_CENTRAL_CPU_MSC Central Connection Parameter Update * @msc @@ -1868,7 +1868,7 @@ * APP=>SD [label = "sd_ble_gap_privacy_set(params: {mode: DEVICE_PRIVACY, private_addr_type: RESOLVABLE } "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {{peer_addr1, peer_irk1}}, pp_local_irks: {local_irk1}) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -3894,4 +3894,3 @@ * @} * @} */ - diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble.h index da1a06bbc..e2abcd7ad 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble.h @@ -521,7 +521,7 @@ SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_v /**@brief Remove a Vendor Specific base UUID. - * + * * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows * the application to reuse memory allocated for Vendor Specific base UUIDs. * diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gap.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gap.h index a130d7b51..6750e742f 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gap.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gap.h @@ -1664,7 +1664,7 @@ SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr * * @retval ::NRF_SUCCESS Address successfully retrieved. * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. - * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. * @retval ::NRF_ERROR_INVALID_STATE The advertising set is currently not advertising. */ SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr)); diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/doc/ble_api.dox b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/doc/ble_api.dox index 6cdfc8870..ceebf55a7 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/doc/ble_api.dox +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/doc/ble_api.dox @@ -968,11 +968,11 @@ * |||; * SD<-ADVERTISERS [label = "Scannable Advertisement (ADV_SCAN_IND)", textcolor="#000080", linecolor="#000080"]; * SD->ADVERTISERS [label = "Scan Request (SCAN_REQ)", textcolor="#000080", linecolor="#000080"]; - * SD<-ADVERTISERS [label = "Scan Response (SCAN_RSP)", textcolor="#000080", linecolor="#000080"]; + * SD<-ADVERTISERS [label = "Scan Response (SCAN_RSP)", textcolor="#000080", linecolor="#000080"]; * APP<<=SD [label = "BLE_GAP_EVT_ADV_REPORT {bdaddr, rssi, data}"]; - * ...; - * APP<<=SD [label = "BLE_GAP_EVT_TIMEOUT {BLE_GAP_TIMEOUT_SRC_SCAN}"]; - * |||; + * ...; + * APP<<=SD [label = "BLE_GAP_EVT_TIMEOUT {BLE_GAP_TIMEOUT_SRC_SCAN}"]; + * |||; * @endmsc * @defgroup BLE_GAP_SCAN_MSC_AE Scanning for advertisers performing legacy and extended advertising * @msc @@ -1011,7 +1011,7 @@ * APP<<=SD [label = "BLE_GAP_EVT_ADV_REPORT {type : {extended_pdu = 1, scannable = 1, scan_response = 1}, data}"]; * APP=>SD [label = "sd_ble_gap_scan_start(params = NULL, adv_report_buffer)"]; * APP<<SD [label = "NRF_SUCCESS"]; - * SD<-ADVERTISERS [label = "Legacy Scannable Advertisement (ADV_SCAN_IND) with adv_data ", textcolor="#000080", linecolor="#000080"]; + * SD<-ADVERTISERS [label = "Legacy Scannable Advertisement (ADV_SCAN_IND) with adv_data ", textcolor="#000080", linecolor="#000080"]; * SD->ADVERTISERS [label = "Legacy Scan Request (SCAN_REQ)", textcolor="#000080", linecolor="#000080"]; * APP<<=SD [label = "BLE_GAP_EVT_ADV_REPORT {type : {extended_pdu = 0, scannable = 1, scan_response = 0}, adv_data}"]; * APP=>SD [label = "sd_ble_gap_scan_start(params = NULL, adv_report_buffer)"]; @@ -1030,8 +1030,8 @@ * --- [label = " Variant #2 Reporting incomplete advertising reports"]; * |||; * APP=>SD [label = "sd_ble_gap_scan_start(params : {extended = 1, report_incomplete_evts = 1}, adv_report_buffer)"]; - * APP<<SD [label = "NRF_SUCCESS"]; - * |||; + * APP<<SD [label = "NRF_SUCCESS"]; + * |||; * SD<-ADVERTISERS [label = "Advertisement (ADV_*_IND)", textcolor="#000080", linecolor="#000080"]; * APP<<=SD [label = "BLE_GAP_EVT_ADV_REPORT {type : status = BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, aux_pointer}"]; * |||; @@ -1052,7 +1052,7 @@ * @defgroup BLE_GAP_CENTRAL_CONN_MSC Central Connection Establishment and Termination * @{ * @defgroup BLE_GAP_CENTRAL_CONN_MSC_LEGACY Connecting to legacy advertisers - + * @msc * hscale = "1.5"; * APP,SD,PERIPHERAL; @@ -1114,9 +1114,9 @@ * SD rbox SD [label = "Connection timeout reached"]; * |||; * APP<<=SD [label = "BLE_GAP_EVT_TIMEOUT {BLE_GAP_TIMEOUT_SRC_CONN}"]; - * @endmsc + * @endmsc * @} - + * * @defgroup BLE_GAP_CENTRAL_CPU_MSC Central Connection Parameter Update * @msc @@ -1868,7 +1868,7 @@ * APP=>SD [label = "sd_ble_gap_privacy_set(params: {mode: DEVICE_PRIVACY, private_addr_type: RESOLVABLE } "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {peer_addr1, peer_irk1}, pp_local_irks: {local_irk1}) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -1970,7 +1970,7 @@ * hscale = "1.5"; * APP,SD,ADVERTISERS; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {peer_addr1, peer_irk1}, pp_local_irks: NULL) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -2022,7 +2022,7 @@ * |||; * --- [label = " Variant #4 Scan directed advertisers and resolve initiator address using local IRK in device identity list"]; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {peer_addr1, peer_irk1}, pp_local_irks: local_irk1) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -2054,7 +2054,7 @@ * |||; * --- [label = " Variant #1 Advertise directed to private peer"]; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {peer_addr1, peer_irk1}, pp_local_irks: NULL) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -2070,7 +2070,7 @@ * |||; * --- [label = " Variant #2 Private directed advertising to private peer using device IRK"]; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {peer_addr1, peer_irk1}, pp_local_irks: NULL) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -2089,7 +2089,7 @@ * |||; * --- [label = " Variant #3 Private directed advertising to private peer using local IRK in device identity list"]; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {peer_addr1, peer_irk1}, pp_local_irks: {local_irk1}) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -2132,7 +2132,7 @@ * hscale = "1.5"; * APP,SD,CENTRAL; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {peer_addr1, peer_irk1}, pp_local_irks: NULL) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -2157,7 +2157,7 @@ * hscale = "1.5"; * APP,SD,PERIPHERAL; * |||; - + * APP=>SD [label = "sd_ble_gap_device_identities_set(pp_id_keys: {peer_addr1, peer_irk1}, pp_local_irks: NULL) "]; * APP<<SD [label = "NRF_SUCCESS"]; * |||; @@ -2346,7 +2346,7 @@ * APP<<SD [label = "NRF_SUCCESS"]; * SD:>PEER [label = "LL Length Request (LL_LENGTH_REQ) {tx=251, rx=251}", textcolor="#000080", linecolor="#000080"]; * SD<:PEER [label = "LL Length Response (LL_LENGTH_RSP) {tx=251, rx=251}", textcolor="#000080", linecolor="#000080"]; - + * APP<<=SD [label = "BLE_GAP_EVT_DATA_LENGTH_UPDATE {.effective_params={.max_tx_octets=251, .max_rx_octets=251, .max_tx_time_us=2120, .max_rx_time_us=2120}}"]; * |||; * ...; @@ -3927,4 +3927,3 @@ * @} * @} */ - diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble.h index 39944854c..d17ac9a59 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble.h @@ -89,7 +89,7 @@ enum BLE_COMMON_SVCS */ enum BLE_COMMON_EVTS { - BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. See @ref ble_evt_user_mem_request_t + BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. See @ref ble_evt_user_mem_request_t \n Reply with @ref sd_ble_user_mem_reply. */ BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1, /**< User Memory release. See @ref ble_evt_user_mem_release_t */ }; @@ -389,10 +389,10 @@ typedef union * application RAM region (APP_RAM_BASE). On return, this will * contain the minimum start address of the application RAM region * required by the SoftDevice for this configuration. - * @warning After this call, the SoftDevice may generate several events. The list of events provided - * below require the application to initiate a SoftDevice API call. The corresponding API call - * is referenced in the event documentation. - * If the application fails to do so, the BLE connection may timeout, or the SoftDevice may stop + * @warning After this call, the SoftDevice may generate several events. The list of events provided + * below require the application to initiate a SoftDevice API call. The corresponding API call + * is referenced in the event documentation. + * If the application fails to do so, the BLE connection may timeout, or the SoftDevice may stop * communicating with the peer device. * - @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST * - @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST @@ -537,7 +537,7 @@ SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_v /**@brief Remove a Vendor Specific base UUID. - * + * * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows * the application to reuse memory allocated for Vendor Specific base UUIDs. * diff --git a/ports/nrf/boards/common.template.ld b/ports/nrf/boards/common.template.ld index 9a7df69a4..5982b8ba0 100644 --- a/ports/nrf/boards/common.template.ld +++ b/ports/nrf/boards/common.template.ld @@ -70,20 +70,6 @@ SECTIONS _etext = .; /* define a global symbol at end of code */ } >FLASH_FIRMWARE - /* - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } >FLASH_FIRMWARE - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH_FIRMWARE - */ - /* used by the startup to initialize data */ _sidata = .; @@ -147,6 +133,14 @@ SECTIONS . = ALIGN(4); } >RAM + /* Remove exception unwinding information, since Circuit Python + does not support this GCC feature. */ + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx*) + } + /* Remove information from the standard libraries */ /* /DISCARD/ : diff --git a/ports/nrf/boards/electronut_labs_papyr/README.md b/ports/nrf/boards/electronut_labs_papyr/README.md index fda390193..7e5c43cc8 100644 --- a/ports/nrf/boards/electronut_labs_papyr/README.md +++ b/ports/nrf/boards/electronut_labs_papyr/README.md @@ -4,7 +4,7 @@ The `Electronut Labs Papyr` board is based on the `nRF52840` SoC from Nordic Semiconductors. It has an e-ink display on it, along with a CR2477 battery holder. -Papyr can be programmed with the [`Adafruit nRF52 bootloader`](https://github.com/adafruit/Adafruit_nRF52_Bootloader) to +Papyr can be programmed with the [`Adafruit nRF52 bootloader`](https://github.com/adafruit/Adafruit_nRF52_Bootloader) to Schematic, datasheet default pin mapping etc. can be found over [here](https://docs.electronut.in/papyr/). The default pin mapping can be found in the board directory. diff --git a/ports/nrf/boards/hiibot_bluefi/board.c b/ports/nrf/boards/hiibot_bluefi/board.c new file mode 100644 index 000000000..6b53cab13 --- /dev/null +++ b/ports/nrf/boards/hiibot_bluefi/board.c @@ -0,0 +1,103 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "mpconfigboard.h" + +#include "shared-bindings/busio/SPI.h" +#include "shared-bindings/displayio/FourWire.h" +#include "shared-module/displayio/__init__.h" +#include "shared-module/displayio/mipi_constants.h" + +displayio_fourwire_obj_t board_display_obj; + +#define DELAY 0x80 + +uint8_t display_init_sequence[] = { + 0x01, 0 | DELAY, 150, // SWRESET + 0x11, 0 | DELAY, 255, // SLPOUT + 0x36, 1, 0b10100000, // _MADCTL for rotation 0 + 0x3a, 1, 0x55, // COLMOD - 16bit color + 0x21, 0 | DELAY, 10, // _INVON + 0x13, 0 | DELAY, 10, // _NORON + 0x29, 0 | DELAY, 255, // _DISPON +}; + +void board_init(void) { + busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + common_hal_busio_spi_construct(spi, &pin_P0_07, &pin_P1_08, NULL); // SCK, MOSI, MISO + common_hal_busio_spi_never_reset(spi); + + displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + bus->base.type = &displayio_fourwire_type; + common_hal_displayio_fourwire_construct(bus, + spi, + &pin_P0_27, // TFT_DC Command or data + &pin_P0_05, // TFT_CS Chip select + NULL, // no TFT_RST Reset + //&pin_P1_14, // TFT_RST Reset + 60000000, // Baudrate + 0, // Polarity + 0); // Phase + + displayio_display_obj_t* display = &displays[0].display; + display->base.type = &displayio_display_type; + common_hal_displayio_display_construct(display, + bus, + 240, // Width (after rotation) + 240, // Height (after rotation) + 80, // column start + 0, // row start + 180, // rotation + 16, // Color depth + false, // Grayscale + false, // Pixels in a byte share a row. Only used for depth < 8 + 1, // bytes per cell. Only valid for depths < 8 + false, // reverse_pixels_in_byte. Only valid for depths < 8 + true, // reverse_pixels_in_word + MIPI_COMMAND_SET_COLUMN_ADDRESS, // Set column command + MIPI_COMMAND_SET_PAGE_ADDRESS, // Set row command + MIPI_COMMAND_WRITE_MEMORY_START, // Write memory command + 0x37, // set vertical scroll command + display_init_sequence, + sizeof(display_init_sequence), + &pin_P1_13, // backlight pin + NO_BRIGHTNESS_COMMAND, + 1.0f, // brightness (ignored) + true, // auto_brightness + false, // single_byte_bounds + false, // data_as_commands + true, // auto_refresh + 60, // native_frames_per_second + true); // backlight_on_high +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/nrf/boards/hiibot_bluefi/mpconfigboard.h b/ports/nrf/boards/hiibot_bluefi/mpconfigboard.h new file mode 100644 index 000000000..4b7a884cf --- /dev/null +++ b/ports/nrf/boards/hiibot_bluefi/mpconfigboard.h @@ -0,0 +1,64 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Glenn Ruben Bakke + * Copyright (c) 2018 Dan Halbert for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "nrfx/hal/nrf_gpio.h" + +#define MICROPY_HW_BOARD_NAME "HiiBot BlueFi" +#define MICROPY_HW_MCU_NAME "nRF52840" + +#define MICROPY_HW_NEOPIXEL (&pin_P1_10) // P18 / D18 + +#define MICROPY_HW_LED_STATUS (&pin_P1_12) // P17 / D17 + +#if QSPI_FLASH_FILESYSTEM +#define MICROPY_QSPI_DATA0 NRF_GPIO_PIN_MAP(1, 1) +#define MICROPY_QSPI_DATA1 NRF_GPIO_PIN_MAP(1, 4) +#define MICROPY_QSPI_DATA2 NRF_GPIO_PIN_MAP(1, 6) +#define MICROPY_QSPI_DATA3 NRF_GPIO_PIN_MAP(1, 5) +#define MICROPY_QSPI_SCK NRF_GPIO_PIN_MAP(1, 3) +#define MICROPY_QSPI_CS NRF_GPIO_PIN_MAP(1, 2) +#endif + +#if SPI_FLASH_FILESYSTEM +#define SPI_FLASH_MOSI_PIN &pin_P1_01 +#define SPI_FLASH_MISO_PIN &pin_P1_04 +#define SPI_FLASH_SCK_PIN &pin_P1_03 +#define SPI_FLASH_CS_PIN &pin_P1_02 +#endif + +// No 32kHz crystal. THere's a 32MHz crystal in the nRF module. +#define BOARD_HAS_32KHZ_XTAL (0) + +#define DEFAULT_I2C_BUS_SCL (&pin_P0_00) +#define DEFAULT_I2C_BUS_SDA (&pin_P0_31) + +#define DEFAULT_SPI_BUS_SCK (&pin_P0_06) +#define DEFAULT_SPI_BUS_MOSI (&pin_P0_26) +#define DEFAULT_SPI_BUS_MISO (&pin_P0_04) + +#define DEFAULT_UART_BUS_RX (&pin_P0_28) +#define DEFAULT_UART_BUS_TX (&pin_P0_02) diff --git a/ports/nrf/boards/hiibot_bluefi/mpconfigboard.mk b/ports/nrf/boards/hiibot_bluefi/mpconfigboard.mk new file mode 100644 index 000000000..e43639a89 --- /dev/null +++ b/ports/nrf/boards/hiibot_bluefi/mpconfigboard.mk @@ -0,0 +1,17 @@ +USB_VID = 0x239A +USB_PID = 0x80B2 +USB_PRODUCT = "HiiBot BlueFi" +USB_MANUFACTURER = "HiiBot" + +MCU_CHIP = nrf52840 + +QSPI_FLASH_FILESYSTEM = 1 +EXTERNAL_FLASH_DEVICE_COUNT = 1 +EXTERNAL_FLASH_DEVICES = "W25Q16JV_IQ" + +# Allocate two, not just one I2C peripheral for Bluefi, so that we have both +# on-board and off-board I2C available. +# When SPIM3 becomes available we'll be able to have two I2C and two SPI peripherals. +# We use a CFLAGS define here because there are include order issues +# if we try to include "mpconfigport.h" into nrfx_config.h . +CFLAGS += -DCIRCUITPY_NRF_NUM_I2C=2 diff --git a/ports/nrf/boards/hiibot_bluefi/pins.c b/ports/nrf/boards/hiibot_bluefi/pins.c new file mode 100644 index 000000000..340ea948c --- /dev/null +++ b/ports/nrf/boards/hiibot_bluefi/pins.c @@ -0,0 +1,180 @@ +#include "shared-bindings/board/__init__.h" + +#include "boards/board.h" +#include "shared-module/displayio/__init__.h" + +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR_P0), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_P0_28) }, + + { MP_ROM_QSTR(MP_QSTR_P1), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_P0_02) }, + + { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_P0_29) }, + + { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_P0_30) }, + + { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_P0_03) }, + + { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P1_07) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_P1_07) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON_A), MP_ROM_PTR(&pin_P1_07) }, + + { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_08) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_P0_08) }, + + { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_25) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_P0_25) }, + + { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_23) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_P0_23) }, + + { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_21) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_P0_21) }, + + { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_P0_19) }, + + { MP_ROM_QSTR(MP_QSTR_P11), MP_ROM_PTR(&pin_P1_09) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_P1_09) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON_B), MP_ROM_PTR(&pin_P1_09) }, + + { MP_ROM_QSTR(MP_QSTR_P12), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_P0_16) }, + + { MP_ROM_QSTR(MP_QSTR_P13), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P0_06) }, + + { MP_ROM_QSTR(MP_QSTR_P14), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_P0_04) }, + + { MP_ROM_QSTR(MP_QSTR_P15), MP_ROM_PTR(&pin_P0_26) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_P0_26) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_P0_26) }, + + { MP_ROM_QSTR(MP_QSTR_P16), MP_ROM_PTR(&pin_P0_01) }, + { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_P0_01) }, + + { MP_ROM_QSTR(MP_QSTR_P17), MP_ROM_PTR(&pin_P1_12) }, + { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_P1_12) }, + { MP_ROM_QSTR(MP_QSTR_REDLED), MP_ROM_PTR(&pin_P1_12) }, + + { MP_ROM_QSTR(MP_QSTR_P18), MP_ROM_PTR(&pin_P1_10) }, + { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_P1_10) }, + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_P1_10) }, + + { MP_ROM_QSTR(MP_QSTR_P19), MP_ROM_PTR(&pin_P0_00) }, + { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_P0_00) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_P0_00) }, + + { MP_ROM_QSTR(MP_QSTR_P20), MP_ROM_PTR(&pin_P0_31) }, + { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_P0_31) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_P0_31) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_P0_31) }, + + { MP_ROM_QSTR(MP_QSTR_P21), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_MICROPHONE_CLOCK), MP_ROM_PTR(&pin_P0_09) }, + + { MP_ROM_QSTR(MP_QSTR_P22), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_MICROPHONE_DATA), MP_ROM_PTR(&pin_P0_10) }, + + { MP_ROM_QSTR(MP_QSTR_P23), MP_ROM_PTR(&pin_P0_07) }, + { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_P0_07) }, + { MP_ROM_QSTR(MP_QSTR_TFT_SCK), MP_ROM_PTR(&pin_P0_07) }, + + { MP_ROM_QSTR(MP_QSTR_P24), MP_ROM_PTR(&pin_P1_08) }, + { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_P1_08) }, + { MP_ROM_QSTR(MP_QSTR_TFT_MOSI), MP_ROM_PTR(&pin_P1_08) }, + + { MP_ROM_QSTR(MP_QSTR_P25), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_TFT_CS), MP_ROM_PTR(&pin_P0_05) }, + + { MP_ROM_QSTR(MP_QSTR_P26), MP_ROM_PTR(&pin_P0_27) }, + { MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_P0_27) }, + { MP_ROM_QSTR(MP_QSTR_TFT_DC), MP_ROM_PTR(&pin_P0_27) }, + + { MP_ROM_QSTR(MP_QSTR_P27), MP_ROM_PTR(&pin_P1_14) }, + { MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_P1_14) }, + { MP_ROM_QSTR(MP_QSTR_TFT_RESET), MP_ROM_PTR(&pin_P1_14) }, + { MP_ROM_QSTR(MP_QSTR_TFT_BACKLIGHT), MP_ROM_PTR(&pin_P1_14) }, + + // P28~P33/D28~D33 connecte into QSPI FlashROM (W25Q16JV_IQ) + + { MP_ROM_QSTR(MP_QSTR_P34), MP_ROM_PTR(&pin_P0_22) }, + { MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_P0_22) }, + { MP_ROM_QSTR(MP_QSTR_WIFI_SCK), MP_ROM_PTR(&pin_P0_22) }, + + { MP_ROM_QSTR(MP_QSTR_P35), MP_ROM_PTR(&pin_P0_17) }, + { MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_P0_17) }, + { MP_ROM_QSTR(MP_QSTR_WIFI_MISO), MP_ROM_PTR(&pin_P0_17) }, + + { MP_ROM_QSTR(MP_QSTR_P36), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_WIFI_MOSI), MP_ROM_PTR(&pin_P0_20) }, + + { MP_ROM_QSTR(MP_QSTR_P37), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_WIFI_BUSY), MP_ROM_PTR(&pin_P0_15) }, + + { MP_ROM_QSTR(MP_QSTR_P38), MP_ROM_PTR(&pin_P0_24) }, + { MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_P0_24) }, + { MP_ROM_QSTR(MP_QSTR_WIFI_CS), MP_ROM_PTR(&pin_P0_24) }, + + { MP_ROM_QSTR(MP_QSTR_P39), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_WIFI_RESET), MP_ROM_PTR(&pin_P1_00) }, + + { MP_ROM_QSTR(MP_QSTR_P40), MP_ROM_PTR(&pin_P0_13) }, + { MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_P0_13) }, + { MP_ROM_QSTR(MP_QSTR_WIFI_PWR), MP_ROM_PTR(&pin_P0_13) }, + + { MP_ROM_QSTR(MP_QSTR_P41), MP_ROM_PTR(&pin_P0_11) }, + { MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_P0_11) }, + { MP_ROM_QSTR(MP_QSTR_SENSORS_SCL), MP_ROM_PTR(&pin_P0_11) }, + + { MP_ROM_QSTR(MP_QSTR_P42), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_SENSORS_SDA), MP_ROM_PTR(&pin_P0_12) }, + + { MP_ROM_QSTR(MP_QSTR_P43), MP_ROM_PTR(&pin_P0_14) }, + { MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_P0_14) }, + { MP_ROM_QSTR(MP_QSTR_IMU_IRQ), MP_ROM_PTR(&pin_P0_14) }, + { MP_ROM_QSTR(MP_QSTR_ACCELEROMETER_INTERRUPT), MP_ROM_PTR(&pin_P0_14) }, + + { MP_ROM_QSTR(MP_QSTR_P44), MP_ROM_PTR(&pin_P1_14) }, + { MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_P1_14) }, + { MP_ROM_QSTR(MP_QSTR_WHITELED), MP_ROM_PTR(&pin_P1_14) }, + + { MP_ROM_QSTR(MP_QSTR_P45), MP_ROM_PTR(&pin_P1_11) }, + { MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_P1_11) }, + { MP_ROM_QSTR(MP_QSTR_SPEAKER_ENABLE), MP_ROM_PTR(&pin_P1_11) }, + + { MP_ROM_QSTR(MP_QSTR_P46), MP_ROM_PTR(&pin_P1_15) }, + { MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_P1_15) }, + { MP_ROM_QSTR(MP_QSTR_SPEAKER), MP_ROM_PTR(&pin_P1_15) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO), MP_ROM_PTR(&pin_P1_15) }, + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, + + { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].display)} +}; + +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/nrf/boards/particle_argon/mpconfigboard.mk b/ports/nrf/boards/particle_argon/mpconfigboard.mk index a0edfda95..2ca08b982 100644 --- a/ports/nrf/boards/particle_argon/mpconfigboard.mk +++ b/ports/nrf/boards/particle_argon/mpconfigboard.mk @@ -11,4 +11,4 @@ EXTERNAL_FLASH_DEVICES = "MX25L3233F" # Support for the Ethernet FeatherWing CIRCUITPY_NETWORK = 1 -MICROPY_PY_WIZNET5K = 5500
\ No newline at end of file +MICROPY_PY_WIZNET5K = 5500 diff --git a/ports/nrf/boards/particle_boron/mpconfigboard.mk b/ports/nrf/boards/particle_boron/mpconfigboard.mk index ccb2d63a1..f03f43a7b 100644 --- a/ports/nrf/boards/particle_boron/mpconfigboard.mk +++ b/ports/nrf/boards/particle_boron/mpconfigboard.mk @@ -11,4 +11,4 @@ EXTERNAL_FLASH_DEVICES = "MX25L3233F" # Support for the Ethernet FeatherWing CIRCUITPY_NETWORK = 1 -MICROPY_PY_WIZNET5K = 5500
\ No newline at end of file +MICROPY_PY_WIZNET5K = 5500 diff --git a/ports/nrf/boards/particle_xenon/mpconfigboard.mk b/ports/nrf/boards/particle_xenon/mpconfigboard.mk index 3970b1d05..44309bbca 100644 --- a/ports/nrf/boards/particle_xenon/mpconfigboard.mk +++ b/ports/nrf/boards/particle_xenon/mpconfigboard.mk @@ -11,4 +11,4 @@ EXTERNAL_FLASH_DEVICES = "MX25L3233F" # Support for the Ethernet FeatherWing CIRCUITPY_NETWORK = 1 -MICROPY_PY_WIZNET5K = 5500
\ No newline at end of file +MICROPY_PY_WIZNET5K = 5500 diff --git a/ports/nrf/boards/pca10100/mpconfigboard.mk b/ports/nrf/boards/pca10100/mpconfigboard.mk index 1206c8fe5..715b65e63 100644 --- a/ports/nrf/boards/pca10100/mpconfigboard.mk +++ b/ports/nrf/boards/pca10100/mpconfigboard.mk @@ -8,9 +8,13 @@ MCU_CHIP = nrf52833 INTERNAL_FLASH_FILESYSTEM = 1 CIRCUITPY_AUDIOMP3 = 0 +CIRCUITPY_BITBANGIO = 0 CIRCUITPY_BUSIO = 1 +CIRCUITPY_COUNTIO = 0 CIRCUITPY_DISPLAYIO = 0 CIRCUITPY_FRAMEBUFFERIO = 0 +CIRCUITPY_FREQUENCYIO = 0 +CIRCUITPY_I2CSLAVE = 0 CIRCUITPY_NEOPIXEL_WRITE = 0 CIRCUITPY_NVM = 0 CIRCUITPY_PIXELBUF = 0 @@ -20,6 +24,8 @@ CIRCUITPY_RTC = 1 CIRCUITPY_TOUCHIO = 0 CIRCUITPY_ULAB = 0 +SUPEROPT_GC = 0 + # These defines must be overridden before mpconfigboard.h is included, which is # why they are passed on the command line. CFLAGS += -DSPIM3_BUFFER_SIZE=0 -DSOFTDEVICE_RAM_SIZE='(32*1024)' diff --git a/ports/nrf/boards/simmel/mpconfigboard.h b/ports/nrf/boards/simmel/mpconfigboard.h index bcffb40ea..28c4ee7d9 100644 --- a/ports/nrf/boards/simmel/mpconfigboard.h +++ b/ports/nrf/boards/simmel/mpconfigboard.h @@ -40,7 +40,7 @@ #endif #define CIRCUITPY_INTERNAL_NVM_SIZE 0 -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (80*1024) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (76*1024) #define BOOTLOADER_SIZE (0x4000) // 12 kiB #define CIRCUITPY_BLE_CONFIG_SIZE (12*1024) diff --git a/ports/nrf/boards/simmel/mpconfigboard.mk b/ports/nrf/boards/simmel/mpconfigboard.mk index 36a6fadda..2bca2492f 100644 --- a/ports/nrf/boards/simmel/mpconfigboard.mk +++ b/ports/nrf/boards/simmel/mpconfigboard.mk @@ -24,6 +24,7 @@ CIRCUITPY_ROTARYIO = 0 CIRCUITPY_RTC = 1 CIRCUITPY_TOUCHIO = 0 CIRCUITPY_ULAB = 0 +CIRCUITPY_WATCHDOG = 1 # Enable micropython.native #CIRCUITPY_ENABLE_MPY_NATIVE = 1 diff --git a/ports/nrf/boards/sparkfun_nrf52840_mini/README.md b/ports/nrf/boards/sparkfun_nrf52840_mini/README.md index f80f1c27c..396e169a1 100644 --- a/ports/nrf/boards/sparkfun_nrf52840_mini/README.md +++ b/ports/nrf/boards/sparkfun_nrf52840_mini/README.md @@ -45,4 +45,4 @@ The nRF52840 Mini hardware layout is open source: * [Schematic](https://cdn.sparkfun.com/assets/learn_tutorials/8/2/0/nrf52840-breakout-mdbt50q-v10.pdf) * [Eagle Files](https://cdn.sparkfun.com/assets/learn_tutorials/8/2/0/nrf52840-breakout-mdbt50q-v10.zip) -* [Hookup Guide](https://learn.sparkfun.com/tutorials/sparkfun-pro-nrf52840-mini-hookup-guide)
\ No newline at end of file +* [Hookup Guide](https://learn.sparkfun.com/tutorials/sparkfun-pro-nrf52840-mini-hookup-guide) diff --git a/ports/nrf/common-hal/audiobusio/I2SOut.c b/ports/nrf/common-hal/audiobusio/I2SOut.c index 2fa28afac..34eecf8d5 100644 --- a/ports/nrf/common-hal/audiobusio/I2SOut.c +++ b/ports/nrf/common-hal/audiobusio/I2SOut.c @@ -31,6 +31,7 @@ #include "common-hal/audiobusio/I2SOut.h" #include "shared-bindings/audiobusio/I2SOut.h" #include "shared-module/audiocore/__init__.h" +#include "supervisor/shared/tick.h" #include "py/obj.h" #include "py/runtime.h" @@ -158,7 +159,7 @@ static void i2s_buffer_fill(audiobusio_i2sout_obj_t* self) { // Find the last frame of real audio data and replicate its samples until // you have 32 bits worth, which is the fundamental unit of nRF I2S DMA - if(buffer != buffer_start) { + if (buffer != buffer_start) { if (self->bytes_per_sample == 1 && self->channel_count == 1) { // For 8-bit mono, 4 copies of the final sample are required self->hold_value = 0x01010101 * *(uint8_t*)(buffer-1); @@ -211,6 +212,8 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, NRF_I2S->CONFIG.ALIGN = I2S_CONFIG_ALIGN_ALIGN_Left; NRF_I2S->CONFIG.FORMAT = left_justified ? I2S_CONFIG_FORMAT_FORMAT_Aligned : I2S_CONFIG_FORMAT_FORMAT_I2S; + + supervisor_enable_tick(); } bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t* self) { @@ -230,6 +233,7 @@ void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { reset_pin_number(self->data_pin_number); self->data_pin_number = 0xff; instance = NULL; + supervisor_disable_tick(); } void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, @@ -340,5 +344,8 @@ void i2s_reset(void) { NRF_I2S->PSEL.LRCK = 0xFFFFFFFF; NRF_I2S->PSEL.SDOUT = 0xFFFFFFFF; NRF_I2S->PSEL.SDIN = 0xFFFFFFFF; + if (instance) { + supervisor_disable_tick(); + } instance = NULL; } diff --git a/ports/nrf/common-hal/audiopwmio/PWMAudioOut.c b/ports/nrf/common-hal/audiopwmio/PWMAudioOut.c index 89966b7da..7fec766fb 100644 --- a/ports/nrf/common-hal/audiopwmio/PWMAudioOut.c +++ b/ports/nrf/common-hal/audiopwmio/PWMAudioOut.c @@ -36,6 +36,7 @@ #include "shared-bindings/audiopwmio/PWMAudioOut.h" #include "shared-bindings/microcontroller/__init__.h" #include "shared-bindings/microcontroller/Pin.h" +#include "supervisor/shared/tick.h" #include "supervisor/shared/translate.h" // TODO: This should be the same size as PWMOut.c:pwms[], but there's no trivial way to accomplish that @@ -67,6 +68,7 @@ STATIC void activate_audiopwmout_obj(audiopwmio_pwmaudioout_obj_t *self) { for (size_t i=0; i < MP_ARRAY_SIZE(active_audio); i++) { if (!active_audio[i]) { active_audio[i] = self; + supervisor_enable_tick(); break; } } @@ -77,12 +79,16 @@ STATIC void deactivate_audiopwmout_obj(audiopwmio_pwmaudioout_obj_t *self) { for (size_t i=0; i < MP_ARRAY_SIZE(active_audio); i++) { if (active_audio[i] == self) { active_audio[i] = NULL; + supervisor_disable_tick(); } } } void audiopwmout_reset() { for (size_t i=0; i < MP_ARRAY_SIZE(active_audio); i++) { + if (active_audio[i]) { + supervisor_disable_tick(); + } active_audio[i] = NULL; } } diff --git a/ports/nrf/common-hal/digitalio/DigitalInOut.c b/ports/nrf/common-hal/digitalio/DigitalInOut.c index c5a7a7dfb..2a72151b7 100644 --- a/ports/nrf/common-hal/digitalio/DigitalInOut.c +++ b/ports/nrf/common-hal/digitalio/DigitalInOut.c @@ -65,12 +65,13 @@ void common_hal_digitalio_digitalinout_switch_to_input( common_hal_digitalio_digitalinout_set_pull(self, pull); } -void common_hal_digitalio_digitalinout_switch_to_output( +digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( digitalio_digitalinout_obj_t *self, bool value, digitalio_drive_mode_t drive_mode) { common_hal_digitalio_digitalinout_set_drive_mode(self, drive_mode); common_hal_digitalio_digitalinout_set_value(self, value); + return DIGITALINOUT_OK; } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( @@ -92,7 +93,7 @@ bool common_hal_digitalio_digitalinout_get_value( : nrf_gpio_pin_out_read(self->pin->number); } -void common_hal_digitalio_digitalinout_set_drive_mode( +digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( digitalio_digitalinout_obj_t *self, digitalio_drive_mode_t drive_mode) { nrf_gpio_cfg(self->pin->number, @@ -101,6 +102,7 @@ void common_hal_digitalio_digitalinout_set_drive_mode( NRF_GPIO_PIN_NOPULL, drive_mode == DRIVE_MODE_OPEN_DRAIN ? NRF_GPIO_PIN_H0D1 : NRF_GPIO_PIN_H0H1, NRF_GPIO_PIN_NOSENSE); + return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( diff --git a/ports/nrf/common-hal/microcontroller/__init__.c b/ports/nrf/common-hal/microcontroller/__init__.c index 90d97f868..f5caf68ef 100644 --- a/ports/nrf/common-hal/microcontroller/__init__.c +++ b/ports/nrf/common-hal/microcontroller/__init__.c @@ -94,7 +94,7 @@ void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) { void common_hal_mcu_reset(void) { filesystem_flush(); - NVIC_SystemReset(); + reset_cpu(); } // The singleton microcontroller.Processor object, bound to microcontroller.cpu @@ -106,7 +106,6 @@ const mcu_processor_obj_t common_hal_mcu_processor_obj = { }; #if CIRCUITPY_INTERNAL_NVM_SIZE > 0 - // The singleton nvm.ByteArray object. const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .base = { @@ -117,6 +116,17 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { }; #endif +#if CIRCUITPY_WATCHDOG +// The singleton watchdog.WatchDogTimer object. +watchdog_watchdogtimer_obj_t common_hal_mcu_watchdogtimer_obj = { + .base = { + .type = &watchdog_watchdogtimer_type, + }, + .timeout = 0.0f, + .mode = WATCHDOGMODE_NONE, +}; +#endif + STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_P0_00), MP_ROM_PTR(&pin_P0_00) }, { MP_ROM_QSTR(MP_QSTR_P0_01), MP_ROM_PTR(&pin_P0_01) }, diff --git a/ports/nrf/common-hal/neopixel_write/__init__.h b/ports/nrf/common-hal/neopixel_write/__init__.h index b8dce85ad..9366235af 100644 --- a/ports/nrf/common-hal/neopixel_write/__init__.h +++ b/ports/nrf/common-hal/neopixel_write/__init__.h @@ -29,4 +29,4 @@ void neopixel_write_reset(void); -#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_NEOPIXEL_WRITE_INIT_H
\ No newline at end of file +#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_NEOPIXEL_WRITE_INIT_H diff --git a/ports/nrf/common-hal/rotaryio/IncrementalEncoder.c b/ports/nrf/common-hal/rotaryio/IncrementalEncoder.c index a0cfd48d5..28f563da6 100644 --- a/ports/nrf/common-hal/rotaryio/IncrementalEncoder.c +++ b/ports/nrf/common-hal/rotaryio/IncrementalEncoder.c @@ -49,9 +49,9 @@ static void _intr_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { self->state = new_state; - // logic from the atmel-samd port: provides some damping and scales movement - // down by 4:1. - if (self->quarter >= 4) { + // logic from the atmel-samd port: provides some damping and scales movement + // down by 4:1. + if (self->quarter >= 4) { self->position++; self->quarter = 0; } else if (self->quarter <= -4) { diff --git a/ports/nrf/common-hal/rtc/RTC.c b/ports/nrf/common-hal/rtc/RTC.c index 06345f589..93ba007c8 100644 --- a/ports/nrf/common-hal/rtc/RTC.c +++ b/ports/nrf/common-hal/rtc/RTC.c @@ -79,4 +79,3 @@ int common_hal_rtc_get_calibration(void) { void common_hal_rtc_set_calibration(int calibration) { mp_raise_NotImplementedError(translate("RTC calibration is not supported on this board")); } - diff --git a/ports/nrf/common-hal/supervisor/Runtime.c b/ports/nrf/common-hal/supervisor/Runtime.c index feab6987d..ea663f897 100755 --- a/ports/nrf/common-hal/supervisor/Runtime.c +++ b/ports/nrf/common-hal/supervisor/Runtime.c @@ -35,4 +35,3 @@ bool common_hal_get_serial_connected(void) { bool common_hal_get_serial_bytes_available(void) { return (bool) serial_bytes_available(); } - diff --git a/ports/nrf/common-hal/supervisor/__init__.c b/ports/nrf/common-hal/supervisor/__init__.c index ac88556b4..6dca35fb5 100755 --- a/ports/nrf/common-hal/supervisor/__init__.c +++ b/ports/nrf/common-hal/supervisor/__init__.c @@ -37,4 +37,4 @@ const super_runtime_obj_t common_hal_supervisor_runtime_obj = { .base = { .type = &supervisor_runtime_type, }, -};
\ No newline at end of file +}; diff --git a/ports/nrf/common-hal/watchdog/WatchDogMode.c b/ports/nrf/common-hal/watchdog/WatchDogMode.c new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/ports/nrf/common-hal/watchdog/WatchDogMode.c diff --git a/ports/nrf/common-hal/watchdog/WatchDogTimer.c b/ports/nrf/common-hal/watchdog/WatchDogTimer.c new file mode 100644 index 000000000..bec0ac473 --- /dev/null +++ b/ports/nrf/common-hal/watchdog/WatchDogTimer.c @@ -0,0 +1,189 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Nick Moore for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +#include <math.h> +#include <string.h> + +#include "py/obj.h" +#include "py/objproperty.h" +#include "py/runtime.h" + +#include "common-hal/watchdog/WatchDogTimer.h" + +#include "shared-bindings/microcontroller/__init__.h" +#include "shared-bindings/watchdog/__init__.h" +#include "shared-bindings/watchdog/WatchDogTimer.h" + +#include "supervisor/port.h" + +#include "nrf/timers.h" +#include "nrf_wdt.h" +#include "nrfx_wdt.h" +#include "nrfx_timer.h" + +STATIC uint8_t timer_refcount = 0; +STATIC nrfx_timer_t *timer = NULL; +STATIC nrfx_wdt_t wdt = NRFX_WDT_INSTANCE(0); +STATIC nrfx_wdt_channel_id wdt_channel_id; + +STATIC void watchdogtimer_timer_event_handler(nrf_timer_event_t event_type, void *p_context) { + watchdog_watchdogtimer_obj_t *self = MP_OBJ_TO_PTR(p_context); + if (event_type != NRF_TIMER_EVENT_COMPARE0) { + // Spurious event. + return; + } + + // If the timer hits without being cleared, pause the timer and raise an exception. + nrfx_timer_pause(timer); + self->mode = WATCHDOGMODE_NONE; + mp_obj_exception_clear_traceback(MP_OBJ_FROM_PTR(&mp_watchdog_timeout_exception)); + MP_STATE_VM(mp_pending_exception) = &mp_watchdog_timeout_exception; +#if MICROPY_ENABLE_SCHEDULER + if (MP_STATE_VM(sched_state) == MP_SCHED_IDLE) { + MP_STATE_VM(sched_state) = MP_SCHED_PENDING; + } +#endif +} + +static void timer_free(void) { + timer_refcount--; + if (timer_refcount == 0) { + nrf_peripherals_free_timer(timer); + timer = NULL; + } +} + +// This function is called if the timer expires. The system will reboot +// in 1/16384 of a second. Issue a reboot ourselves so we can do any +// cleanup necessary. +STATIC void watchdogtimer_watchdog_event_handler(void) { + reset_cpu(); +} + +void common_hal_watchdog_feed(watchdog_watchdogtimer_obj_t *self) { + if (self->mode == WATCHDOGMODE_RESET) { + nrfx_wdt_feed(&wdt); + } else if (self->mode == WATCHDOGMODE_RAISE) { + nrfx_timer_clear(timer); + } +} + +void common_hal_watchdog_deinit(watchdog_watchdogtimer_obj_t *self) { + if (timer) { + timer_free(); + } + self->mode = WATCHDOGMODE_NONE; +} + +void watchdog_reset(void) { + common_hal_watchdog_deinit(&common_hal_mcu_watchdogtimer_obj); +} + +mp_float_t common_hal_watchdog_get_timeout(watchdog_watchdogtimer_obj_t *self) { + return self->timeout; +} + +void common_hal_watchdog_set_timeout(watchdog_watchdogtimer_obj_t *self, mp_float_t timeout) { + if (self->mode == WATCHDOGMODE_RAISE) { + // If the WatchDogTimer is already running in "RAISE" mode, reset the timer + // with the new value. + uint64_t ticks = timeout * 31250ULL; + if (ticks > UINT32_MAX) { + mp_raise_ValueError(translate("timeout duration exceeded the maximum supported value")); + } + nrfx_timer_clear(timer); + nrfx_timer_compare(timer, NRF_TIMER_CC_CHANNEL0, ticks, true); + } + + self->timeout = timeout; +} + +watchdog_watchdogmode_t common_hal_watchdog_get_mode(watchdog_watchdogtimer_obj_t *self) { + return self->mode; +} + +void common_hal_watchdog_set_mode(watchdog_watchdogtimer_obj_t *self, watchdog_watchdogmode_t new_mode) { + watchdog_watchdogmode_t current_mode = self->mode; + + if (new_mode == WATCHDOGMODE_RAISE) { + if (timer_refcount == 0) { + timer = nrf_peripherals_allocate_timer_or_throw(); + } + timer_refcount++; + + nrfx_timer_config_t timer_config = { + .frequency = NRF_TIMER_FREQ_31250Hz, + .mode = NRF_TIMER_MODE_TIMER, + .bit_width = NRF_TIMER_BIT_WIDTH_32, + .interrupt_priority = NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY, + .p_context = self, + }; + + nrfx_timer_init(timer, &timer_config, &watchdogtimer_timer_event_handler); + + uint64_t ticks = nrfx_timer_ms_to_ticks(timer, self->timeout * 1000); + if (ticks > UINT32_MAX) { + mp_raise_ValueError(translate("timeout duration exceeded the maximum supported value")); + } + + // true enables interrupt. + nrfx_timer_clear(timer); + nrfx_timer_compare(timer, NRF_TIMER_CC_CHANNEL0, ticks, true); + nrfx_timer_resume(timer); + + } else if (new_mode == WATCHDOGMODE_RESET) { + uint64_t ticks = self->timeout * 1000.0f; + if (ticks > UINT32_MAX) { + mp_raise_ValueError(translate("timeout duration exceeded the maximum supported value")); + } + + nrfx_wdt_config_t config = { + .reload_value = ticks, // in units of ms + .behaviour = NRF_WDT_BEHAVIOUR_RUN_SLEEP, + NRFX_WDT_IRQ_CONFIG + }; + + nrfx_err_t err_code; + err_code = nrfx_wdt_init(&wdt, &config, watchdogtimer_watchdog_event_handler); + if (err_code != NRFX_SUCCESS) { + mp_raise_OSError(1); + } + err_code = nrfx_wdt_channel_alloc(&wdt, &wdt_channel_id); + if (err_code != NRFX_SUCCESS) { + mp_raise_OSError(1); + } + nrfx_wdt_enable(&wdt); + nrfx_wdt_feed(&wdt); + } + + // If we just switched away from RAISE, disable the timmer. + if (current_mode == WATCHDOGMODE_RAISE && new_mode != WATCHDOGMODE_RAISE) { + timer_free(); + } + + self->mode = new_mode; +} diff --git a/ports/nrf/common-hal/watchdog/WatchDogTimer.h b/ports/nrf/common-hal/watchdog/WatchDogTimer.h new file mode 100644 index 000000000..8d6df934e --- /dev/null +++ b/ports/nrf/common-hal/watchdog/WatchDogTimer.h @@ -0,0 +1,44 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Noralf Trønnes + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_NRF_COMMON_HAL_WATCHDOG_WATCHDOGTIMER_H +#define MICROPY_INCLUDED_NRF_COMMON_HAL_WATCHDOG_WATCHDOGTIMER_H + +#include "py/obj.h" +#include "shared-bindings/watchdog/WatchDogMode.h" +#include "shared-bindings/watchdog/WatchDogTimer.h" + +struct _watchdog_watchdogtimer_obj_t { + mp_obj_base_t base; + mp_float_t timeout; + watchdog_watchdogmode_t mode; +}; + +// This needs to be called in order to disable the watchdog if it's set to +// "RAISE". If set to "RESET", then the watchdog cannot be reset. +void watchdog_reset(void); + +#endif // MICROPY_INCLUDED_NRF_COMMON_HAL_WATCHDOG_WATCHDOGTIMER_H diff --git a/ports/nrf/common-hal/watchdog/__init__.c b/ports/nrf/common-hal/watchdog/__init__.c new file mode 100644 index 000000000..79875d127 --- /dev/null +++ b/ports/nrf/common-hal/watchdog/__init__.c @@ -0,0 +1,25 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Nick Moore for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ diff --git a/ports/nrf/common-hal/watchdog/__init__.h b/ports/nrf/common-hal/watchdog/__init__.h new file mode 100644 index 000000000..de19bdae4 --- /dev/null +++ b/ports/nrf/common-hal/watchdog/__init__.h @@ -0,0 +1,30 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Noralf Trønnes + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_NRF_COMMON_HAL_WATCHDOG___INIT___H +#define MICROPY_INCLUDED_NRF_COMMON_HAL_WATCHDOG___INIT___H + +#endif // MICROPY_INCLUDED_NRF_COMMON_HAL_WATCHDOG___INIT___H diff --git a/ports/nrf/examples/ubluepy_eddystone.py b/ports/nrf/examples/ubluepy_eddystone.py index baf25ba4b..426a4aa55 100644 --- a/ports/nrf/examples/ubluepy_eddystone.py +++ b/ports/nrf/examples/ubluepy_eddystone.py @@ -53,6 +53,6 @@ def generate_eddystone_adv_packet(url): return packet def start(): - adv_packet = generate_eddystone_adv_packet("micropython") + adv_packet = generate_eddystone_adv_packet("micropython") p = Peripheral() - p.advertise(data=adv_packet, connectable=False)
\ No newline at end of file + p.advertise(data=adv_packet, connectable=False) diff --git a/ports/nrf/examples/ubluepy_scan.py b/ports/nrf/examples/ubluepy_scan.py index ab11661cc..c0a7d05a3 100644 --- a/ports/nrf/examples/ubluepy_scan.py +++ b/ports/nrf/examples/ubluepy_scan.py @@ -19,7 +19,7 @@ def get_device_names(scan_entries): def find_device_by_name(name): s = Scanner() scan_res = s.scan(100) - + device_names = get_device_names(scan_res) for dev in device_names: if name == dev[1]: @@ -30,9 +30,9 @@ def find_device_by_name(name): # ... print("address:", res.addr()) # ... print("address type:", res.addr_type()) # ... print("rssi:", res.rssi()) -# ... -# ... -# ... +# ... +# ... +# ... # address: c2:73:61:89:24:45 # address type: 1 # rssi: -26 diff --git a/ports/nrf/examples/ubluepy_temp.py b/ports/nrf/examples/ubluepy_temp.py index e5c157dbb..118407af5 100644 --- a/ports/nrf/examples/ubluepy_temp.py +++ b/ports/nrf/examples/ubluepy_temp.py @@ -31,7 +31,7 @@ def event_handler(id, handle, data): global periph global serv_env_sense global notif_enabled - + if id == constants.EVT_GAP_CONNECTED: # indicated 'connected' LED(1).on() @@ -50,7 +50,7 @@ def event_handler(id, handle, data): notif_enabled = True # start low power timer rtc.start() - else: + else: notif_enabled = False # stop low power timer rtc.stop() @@ -68,7 +68,7 @@ def send_temp(timer_id): # start off with LED(1) off LED(1).off() -# use RTC1 as RTC0 is used by bluetooth stack +# use RTC1 as RTC0 is used by bluetooth stack # set up RTC callback every 5 second rtc = RTC(1, period=5, mode=RTC.PERIODIC, callback=send_temp) @@ -76,7 +76,7 @@ notif_enabled = False uuid_env_sense = UUID("0x181A") # Environmental Sensing service uuid_temp = UUID("0x2A6E") # Temperature characteristic - + serv_env_sense = Service(uuid_env_sense) temp_props = Characteristic.PROP_NOTIFY | Characteristic.PROP_READ @@ -89,4 +89,3 @@ periph = Peripheral() periph.addService(serv_env_sense) periph.setConnectionHandler(event_handler) periph.advertise(device_name="micr_temp", services=[serv_env_sense]) - diff --git a/ports/nrf/gccollect.c b/ports/nrf/gccollect.c index b7aa57a55..3661daa53 100644 --- a/ports/nrf/gccollect.c +++ b/ports/nrf/gccollect.c @@ -43,7 +43,7 @@ void gc_collect(void) { gc_collect_start(); mp_uint_t sp = get_msp(); // Get stack pointer - + // trace the stack, including the registers (since they live on the stack in this function) gc_collect_root((void**)sp, ((uint32_t)&_ram_end - sp) / sizeof(uint32_t)); diff --git a/ports/nrf/mpconfigport.mk b/ports/nrf/mpconfigport.mk index a9ad11bd4..dda9b2436 100644 --- a/ports/nrf/mpconfigport.mk +++ b/ports/nrf/mpconfigport.mk @@ -37,6 +37,7 @@ CIRCUITPY_RGBMATRIX ?= 1 CIRCUITPY_FRAMEBUFFERIO ?= 1 CIRCUITPY_COUNTIO = 0 +CIRCUITPY_WATCHDOG ?= 1 # nRF52840-specific @@ -45,6 +46,9 @@ MCU_SERIES = m4 MCU_VARIANT = nrf52 MCU_SUB_VARIANT = nrf52840 +# Fits on nrf52840 but space is tight on nrf52833. +CIRCUITPY_AESIO ?= 1 + SD ?= s140 SOFTDEV_VERSION ?= 6.1.0 diff --git a/ports/nrf/nrfx_config.h b/ports/nrf/nrfx_config.h index 7a7f2e6d6..b528a6032 100644 --- a/ports/nrf/nrfx_config.h +++ b/ports/nrf/nrfx_config.h @@ -122,4 +122,11 @@ // NVM controller #define NRFX_NVMC_ENABLED 1 +// Watchdog timer +#define NRFX_WDT_ENABLED 1 +#define NRFX_WDT0_ENABLED 1 +// This IRQ indicates the system will reboot shortly, so give +// it a high priority. +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 2 + #endif // NRFX_CONFIG_H__ diff --git a/ports/nrf/nrfx_glue.h b/ports/nrf/nrfx_glue.h index 345de3870..9f91b72a1 100644 --- a/ports/nrf/nrfx_glue.h +++ b/ports/nrf/nrfx_glue.h @@ -180,17 +180,17 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) return (NVIC_GetPendingIRQ(irq_number) == 1); } -//#include <nordic_common.h> -//#include <app_util_platform.h> +void common_hal_mcu_disable_interrupts(void); +void common_hal_mcu_enable_interrupts(void); /** * @brief Macro for entering into a critical section. */ -#define NRFX_CRITICAL_SECTION_ENTER() CRITICAL_REGION_ENTER() +#define NRFX_CRITICAL_SECTION_ENTER() common_hal_mcu_disable_interrupts() /** * @brief Macro for exiting from a critical section. */ -#define NRFX_CRITICAL_SECTION_EXIT() CRITICAL_REGION_EXIT() +#define NRFX_CRITICAL_SECTION_EXIT() common_hal_mcu_enable_interrupts() //------------------------------------------------------------------------------ diff --git a/ports/nrf/peripherals/nrf/nvm.c b/ports/nrf/peripherals/nrf/nvm.c index 63b168f14..dc50e2eef 100644 --- a/ports/nrf/peripherals/nrf/nvm.c +++ b/ports/nrf/peripherals/nrf/nvm.c @@ -40,6 +40,8 @@ STATIC bool sd_is_enabled(void) { uint8_t sd_en = 0; + if (__get_PRIMASK()) + return false; (void) sd_softdevice_is_enabled(&sd_en); return sd_en; } diff --git a/ports/nrf/supervisor/port.c b/ports/nrf/supervisor/port.c index ea09115f7..aee2d63e1 100644 --- a/ports/nrf/supervisor/port.c +++ b/ports/nrf/supervisor/port.c @@ -50,9 +50,13 @@ #include "common-hal/pulseio/PulseIn.h" #include "common-hal/rtc/RTC.h" #include "common-hal/neopixel_write/__init__.h" +#include "common-hal/watchdog/WatchDogTimer.h" +#include "shared-bindings/microcontroller/__init__.h" #include "shared-bindings/rtc/__init__.h" +#include "lib/tinyusb/src/device/usbd.h" + #ifdef CIRCUITPY_AUDIOBUSIO #include "common-hal/audiobusio/I2SOut.h" #endif @@ -74,13 +78,19 @@ const nrfx_rtc_config_t rtc_config = { .interrupt_priority = 6 }; -static volatile uint64_t overflowed_ticks = 0; +#define OVERFLOW_CHECK_PREFIX 0x2cad564f +#define OVERFLOW_CHECK_SUFFIX 0x11343ef7 +static volatile struct { + uint32_t prefix; + uint64_t overflowed_ticks; + uint32_t suffix; +} overflow_tracker __attribute__((section(".uninitialized"))); void rtc_handler(nrfx_rtc_int_type_t int_type) { if (int_type == NRFX_RTC_INT_OVERFLOW) { // Our RTC is 24 bits and we're clocking it at 32.768khz which is 32 (2 ** 5) subticks per // tick. - overflowed_ticks += (1L<< (24 - 5)); + overflow_tracker.overflowed_ticks += (1L<< (24 - 5)); } else if (int_type == NRFX_RTC_INT_TICK && nrfx_rtc_counter_get(&rtc_instance) % 32 == 0) { // Do things common to all ports when the tick occurs supervisor_tick(); @@ -97,6 +107,17 @@ void tick_init(void) { nrfx_rtc_init(&rtc_instance, &rtc_config, rtc_handler); nrfx_rtc_enable(&rtc_instance); nrfx_rtc_overflow_enable(&rtc_instance, true); + + // If the check prefix and suffix aren't correct, then the structure + // in memory isn't correct and the clock will be wildly wrong. Initialize + // the prefix and suffix so that we know the value is correct, and reset + // the time to 0. + if (overflow_tracker.prefix != OVERFLOW_CHECK_PREFIX || + overflow_tracker.suffix != OVERFLOW_CHECK_SUFFIX) { + overflow_tracker.prefix = OVERFLOW_CHECK_PREFIX; + overflow_tracker.suffix = OVERFLOW_CHECK_SUFFIX; + overflow_tracker.overflowed_ticks = 0; + } } safe_mode_t port_init(void) { @@ -128,6 +149,21 @@ safe_mode_t port_init(void) { analogin_init(); #endif + // If the board was reset by the WatchDogTimer, we may + // need to boot into safe mode. Reset the RESETREAS bit + // for the WatchDogTimer so we don't encounter this the + // next time we reboot. + if (NRF_POWER->RESETREAS & POWER_RESETREAS_DOG_Msk) { + NRF_POWER->RESETREAS = POWER_RESETREAS_DOG_Msk; + uint32_t usb_reg = NRF_POWER->USBREGSTATUS; + + // If USB is connected, then the user might be editing `code.py`, + // in which case we should reboot into Safe Mode. + if (usb_reg & POWER_USBREGSTATUS_VBUSDETECT_Msk) { + return WATCHDOG_RESET; + } + } + return NO_SAFE_MODE; } @@ -171,6 +207,10 @@ void reset_port(void) { bleio_reset(); #endif +#if CIRCUITPY_WATCHDOG + watchdog_reset(); +#endif + reset_all_pins(); } @@ -182,6 +222,10 @@ void reset_to_bootloader(void) { } void reset_cpu(void) { + // We're getting ready to reset, so save the counter off. + // This counter will get reset to zero during the reboot. + uint32_t ticks = nrfx_rtc_counter_get(&rtc_instance); + overflow_tracker.overflowed_ticks += ticks / 32; NVIC_SystemReset(); } @@ -225,7 +269,7 @@ uint64_t port_get_raw_ticks(uint8_t* subticks) { if (subticks != NULL) { *subticks = (rtc % 32); } - return overflowed_ticks + rtc / 32; + return overflow_tracker.overflowed_ticks + rtc / 32; } // Enable 1/1024 second tick. @@ -264,7 +308,17 @@ void port_sleep_until_interrupt(void) { sd_app_evt_wait(); } else { // Call wait for interrupt ourselves if the SD isn't enabled. - __WFI(); + // Note that `wfi` should be called with interrupts disabled, + // to ensure that the queue is properly drained. The `wfi` + // instruction will returned as long as an interrupt is + // available, even though the actual handler won't fire until + // we re-enable interrupts. + common_hal_mcu_disable_interrupts(); + if (!tud_task_event_ready()) { + __DSB(); + __WFI(); + } + common_hal_mcu_enable_interrupts(); } } diff --git a/ports/stm/.gitignore b/ports/stm/.gitignore index 3080ece14..5d645392c 100644 --- a/ports/stm/.gitignore +++ b/ports/stm/.gitignore @@ -6,4 +6,4 @@ build-*/ ##################### ref/ -.gdb_history
\ No newline at end of file +.gdb_history diff --git a/ports/stm/Makefile b/ports/stm/Makefile index b667990bd..a7b519ffc 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -94,7 +94,7 @@ endif # MCU Series is defined by the HAL package and doesn't need to be specified here C_DEFS = -D$(MCU_PACKAGE) -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -D$(MCU_VARIANT) -CFLAGS += $(INC) -Werror -Wall -std=gnu11 $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) -nostdlib -nostartfiles +CFLAGS += $(INC) -Werror -Wall -std=gnu11 -fshort-enums $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) -nostdlib -nostartfiles # Undo some warnings. # STM32 HAL uses undefined preprocessor variables, shadowed variables, casts that change alignment reqs @@ -136,7 +136,7 @@ ifndef BOOTLOADER_OFFSET BOOTLOADER_OFFSET := 0x8000000 endif -LDFLAGS = $(CFLAGS) -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-T,$(LD_COMMON) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs +LDFLAGS = $(CFLAGS) -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-T,$(LD_COMMON) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs LIBS := -lgcc -lc # Use toolchain libm if we're not using our own. @@ -207,11 +207,11 @@ SRC_C += \ mphalport.c \ boards/$(BOARD)/board.c \ boards/$(BOARD)/pins.c \ + peripherals/stm32$(MCU_SERIES_LOWER)/clocks.c \ peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/pins.c \ - peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/clocks.c \ peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/gpio.c \ peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/periph.c \ - packages/$(MCU_PACKAGE).c\ + packages/$(MCU_PACKAGE).c \ lib/libc/string0.c \ lib/mp-readline/readline.c \ lib/oofatfs/ff.c \ diff --git a/ports/stm/README.md b/ports/stm/README.md index 95e9bd13f..5df9cedee 100644 --- a/ports/stm/README.md +++ b/ports/stm/README.md @@ -1,6 +1,6 @@ # Circuitpython on STM32 # -This port brings the ST Microelectronics STM32 series of MCUs to Circuitpython. STM32 chips have a wide range of capability, from <$1 low power STM32F0s to dual-core STM32H7s running at 400+ MHz. Currently, only the F4, F7, and H7 families are supported, powered by the ARM Cortex M4 and M7 processors. +This port brings the ST Microelectronics STM32 series of MCUs to Circuitpython. STM32 chips have a wide range of capability, from <$1 low power STM32F0s to dual-core STM32H7s running at 400+ MHz. Currently, only the F4, F7, and H7 families are supported, powered by the ARM Cortex M4 and M7 processors. Refer to the ST Microelectronics website for more information on features sorted by family and individual chip lines: [st.com/en/microcontrollers-microprocessors/stm32-high-performance-mcus.html](https://www.st.com/en/microcontrollers-microprocessors/stm32-high-performance-mcus.html) @@ -13,10 +13,10 @@ STM32 SoCs vary product-by-product in clock speed, peripheral capability, pin as - **packages/** contains package-specific pin bindings (LQFP100, BGA216, etc) - **peripherals/** contains peripheral setup files and peripheral mapping information, sorted by family and sub-variant. Most files in this directory can be generated with the python scripts in **tools/**. - **st-driver/** submodule for ST HAL and LL files generated via CubeMX. Shared with TinyUSB. -- **supervisor/** contains port-specific implementations of internal flash, serial and USB, as well as the **port.c** file, which initializes the port at startup. -- **tools/** python scripts for generating peripheral and pin mapping files in **peripherals/** and **board/**. +- **supervisor/** contains port-specific implementations of internal flash, serial and USB, as well as the **port.c** file, which initializes the port at startup. +- **tools/** python scripts for generating peripheral and pin mapping files in **peripherals/** and **board/**. -At the root level, refer to **mpconfigboard.h** and **mpconfigport.mk** for port specific settings and a list of enabled modules. +At the root level, refer to **mpconfigboard.h** and **mpconfigport.mk** for port specific settings and a list of enabled modules. ## Build instructions ## @@ -36,9 +36,9 @@ You may also build with certain flags available in the makefile, depending on yo ## USB connection ## -Connect your development board of choice to the host PC via the USB cable. Note that for most ST development boards such as the Nucleo and Discovery series, you must use a secondary OTG USB connector to access circuitpython, as the primary USB connector will be connected to a built-in ST-Link debugger rather than the chip itself. +Connect your development board of choice to the host PC via the USB cable. Note that for most ST development boards such as the Nucleo and Discovery series, you must use a secondary OTG USB connector to access circuitpython, as the primary USB connector will be connected to a built-in ST-Link debugger rather than the chip itself. -In many cases, this ST-Link USB connector will **still need to be connected to power** for the chip to turn on - refer to your specific product manual for details. +In many cases, this ST-Link USB connector will **still need to be connected to power** for the chip to turn on - refer to your specific product manual for details. ## Flash the bootloader ## @@ -52,7 +52,7 @@ Windows users will need to install [stm32cubeprog](https://www.st.com/en/develop ## Flashing the circuitpython image with DFU-Util ## -Ensure the board is in dfu mode by following the steps in the previous section. Then run: +Ensure the board is in dfu mode by following the steps in the previous section. Then run: $ make BOARD=feather_stm32F405_express flash @@ -62,10 +62,10 @@ Alternatively, you can navigate to the build directory and run the raw `dfu-util ## Accessing the board ## -Connecting the board to the PC via the USB cable will allow code to be uploaded to the `CIRCUITPY` volume. +Connecting the board to the PC via the USB cable will allow code to be uploaded to the `CIRCUITPY` volume. -Circuitpython exposes a CDC virtual serial connection for REPL access and debugging. Connecting to it from OSX will look something like this: +Circuitpython exposes a CDC virtual serial connection for REPL access and debugging. Connecting to it from OSX will look something like this: screen /dev/tty.usbmodem14111201 115200 -You may also use a program like [mu](https://codewith.mu/) to assist with REPL access. +You may also use a program like [mu](https://codewith.mu/) to assist with REPL access. diff --git a/ports/stm/boards/STM32F401xe_boot.ld b/ports/stm/boards/STM32F401xe_boot.ld index 37827c330..4f3e6ea70 100644 --- a/ports/stm/boards/STM32F401xe_boot.ld +++ b/ports/stm/boards/STM32F401xe_boot.ld @@ -1,5 +1,5 @@ /* - GNU linker script for STM32F401 with bootloader (such as the Meowbit). No internal fs. + GNU linker script for STM32F401 with bootloader (such as the Meowbit). No internal fs. */ /* Specify the memory areas */ @@ -23,4 +23,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32F405_boot.ld b/ports/stm/boards/STM32F405_boot.ld index 5768d1a01..0b0e1a5f3 100644 --- a/ports/stm/boards/STM32F405_boot.ld +++ b/ports/stm/boards/STM32F405_boot.ld @@ -24,4 +24,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32F405_default.ld b/ports/stm/boards/STM32F405_default.ld index 4c11fd7cf..39255ff7a 100644 --- a/ports/stm/boards/STM32F405_default.ld +++ b/ports/stm/boards/STM32F405_default.ld @@ -24,4 +24,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32F405_fs.ld b/ports/stm/boards/STM32F405_fs.ld index e6c66127f..d6de1a08b 100644 --- a/ports/stm/boards/STM32F405_fs.ld +++ b/ports/stm/boards/STM32F405_fs.ld @@ -25,4 +25,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32F407_fs.ld b/ports/stm/boards/STM32F407_fs.ld index f06c19d99..293ac6ff5 100644 --- a/ports/stm/boards/STM32F407_fs.ld +++ b/ports/stm/boards/STM32F407_fs.ld @@ -25,4 +25,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32F411_fs.ld b/ports/stm/boards/STM32F411_fs.ld index 1b45f235f..69b98cf82 100644 --- a/ports/stm/boards/STM32F411_fs.ld +++ b/ports/stm/boards/STM32F411_fs.ld @@ -24,4 +24,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32F412_fs.ld b/ports/stm/boards/STM32F412_fs.ld index 8837bd87d..d3ad291a2 100644 --- a/ports/stm/boards/STM32F412_fs.ld +++ b/ports/stm/boards/STM32F412_fs.ld @@ -24,4 +24,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32F746xG_fs.ld b/ports/stm/boards/STM32F746xG_fs.ld index be10a1429..6c9ea4de3 100644 --- a/ports/stm/boards/STM32F746xG_fs.ld +++ b/ports/stm/boards/STM32F746xG_fs.ld @@ -49,4 +49,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32F767_fs.ld b/ports/stm/boards/STM32F767_fs.ld index 25322b0b6..2feb42225 100644 --- a/ports/stm/boards/STM32F767_fs.ld +++ b/ports/stm/boards/STM32F767_fs.ld @@ -24,4 +24,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/STM32H743_fs.ld b/ports/stm/boards/STM32H743_fs.ld index b6c3d5b62..ca69f0d8d 100644 --- a/ports/stm/boards/STM32H743_fs.ld +++ b/ports/stm/boards/STM32H743_fs.ld @@ -36,4 +36,3 @@ _estack = ORIGIN(DTCM) + LENGTH(DTCM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - diff --git a/ports/stm/boards/common_default.ld b/ports/stm/boards/common_default.ld index ade3571a5..0c7efd01d 100644 --- a/ports/stm/boards/common_default.ld +++ b/ports/stm/boards/common_default.ld @@ -1,4 +1,4 @@ -/* Memory layout for default case. +/* Memory layout for default case. FLASH_ISR .isr_vector FLASH_FIRMWARE .text @@ -96,4 +96,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - diff --git a/ports/stm/boards/common_nvm.ld b/ports/stm/boards/common_nvm.ld index f948b94e1..91e453bfd 100644 --- a/ports/stm/boards/common_nvm.ld +++ b/ports/stm/boards/common_nvm.ld @@ -106,4 +106,3 @@ SECTIONS .ARM.attributes 0 : { *(.ARM.attributes) } } - diff --git a/ports/stm/boards/common_tcm.ld b/ports/stm/boards/common_tcm.ld index 1a41853fe..9e677862d 100644 --- a/ports/stm/boards/common_tcm.ld +++ b/ports/stm/boards/common_tcm.ld @@ -133,7 +133,7 @@ SECTIONS . += _ld_default_stack_size; } > DTCM _ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM); - + .ARM.attributes 0 : { *(.ARM.attributes) } } diff --git a/ports/stm/boards/espruino_pico/README.md b/ports/stm/boards/espruino_pico/README.md index 9f0321c47..86df1ad32 100644 --- a/ports/stm/boards/espruino_pico/README.md +++ b/ports/stm/boards/espruino_pico/README.md @@ -6,10 +6,10 @@ The Espruino Pico is normally updated via a bootloader activated by the Espruino - Install ST's DFU utility on Windows, or dfu-util for Mac or Linux - **Mac**: install with Homebrew: `brew install dfu-util` - **Linux**: install with apt-get: `sudo apt-get install dfu-util` - - **Windows**: download [ST's application](https://www.st.com/en/development-tools/stsw-stm32080.html) or install the Linux subsystem for Windows 10 and follow the linux instructions. + - **Windows**: download [ST's application](https://www.st.com/en/development-tools/stsw-stm32080.html) or install the Linux subsystem for Windows 10 and follow the linux instructions. - Hold down the Pico's button while plugging it into USB (when overwriting Espruino's default firmware) - - Navigate to the same directory as your firmware.bin file for Circuitpython and run the following command: `sudo dfu-util -a 0 -s 0x08000000 -D firmware.bin` or use the ST utility on Windows. - - Restart the board. + - Navigate to the same directory as your firmware.bin file for Circuitpython and run the following command: `sudo dfu-util -a 0 -s 0x08000000 -D firmware.bin` or use the ST utility on Windows. + - Restart the board. -To reinstall Espruino, follow the same steps with the latest Espruino Pico binary from espruino.com/binaries. This will reinstall the usual Espruino bootloader. You must un-short the BOOT0/BTN jumper to re-use the original Espruino Bootloader again. If you used a Pencil mark then you may need to use cleaning fluid and a small brush to totally clear out the graphite.
\ No newline at end of file +To reinstall Espruino, follow the same steps with the latest Espruino Pico binary from espruino.com/binaries. This will reinstall the usual Espruino bootloader. You must un-short the BOOT0/BTN jumper to re-use the original Espruino Bootloader again. If you used a Pencil mark then you may need to use cleaning fluid and a small brush to totally clear out the graphite. diff --git a/ports/stm/boards/espruino_pico/mpconfigboard.h b/ports/stm/boards/espruino_pico/mpconfigboard.h index 890b1b88e..fe4ed6ca2 100644 --- a/ports/stm/boards/espruino_pico/mpconfigboard.h +++ b/ports/stm/boards/espruino_pico/mpconfigboard.h @@ -35,6 +35,6 @@ #define AUTORESET_DELAY_MS (500) #define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000) -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) - diff --git a/ports/stm/boards/espruino_wifi/README.MD b/ports/stm/boards/espruino_wifi/README.MD index 8c2cd3be2..cc78811f1 100644 --- a/ports/stm/boards/espruino_wifi/README.MD +++ b/ports/stm/boards/espruino_wifi/README.MD @@ -6,10 +6,10 @@ The Espruino Wifi is normally updated via a bootloader activated by the Espruino - Install ST's DFU utility on Windows, or dfu-util for Mac or Linux - **Mac**: install with Homebrew: `brew install dfu-util` - **Linux**: install with apt-get: `sudo apt-get install dfu-util` - - **Windows**: download [ST's application](https://www.st.com/en/development-tools/stsw-stm32080.html) or install the Linux subsystem for Windows 10 and follow the linux instructions. + - **Windows**: download [ST's application](https://www.st.com/en/development-tools/stsw-stm32080.html) or install the Linux subsystem for Windows 10 and follow the linux instructions. - Hold down the Wifi's button while plugging it into USB (when overwriting Espruino's default firmware) - - Navigate to the same directory as your firmware.bin file for Circuitpython and run the following command: `sudo dfu-util -a 0 -s 0x08000000 -D firmware.bin` or use the ST utility on Windows. - - Restart the board. + - Navigate to the same directory as your firmware.bin file for Circuitpython and run the following command: `sudo dfu-util -a 0 -s 0x08000000 -D firmware.bin` or use the ST utility on Windows. + - Restart the board. -To reinstall Espruino, follow the same steps with the latest Espruino Wifi binary from espruino.com/binaries. This will reinstall the usual Espruino bootloader. You must un-short the BOOT0/BTN jumper to re-use the original Espruino Bootloader again. If you used a Pencil mark then you may need to use cleaning fluid and a small brush to totally clear out the graphite.
\ No newline at end of file +To reinstall Espruino, follow the same steps with the latest Espruino Wifi binary from espruino.com/binaries. This will reinstall the usual Espruino bootloader. You must un-short the BOOT0/BTN jumper to re-use the original Espruino Bootloader again. If you used a Pencil mark then you may need to use cleaning fluid and a small brush to totally clear out the graphite. diff --git a/ports/stm/boards/espruino_wifi/mpconfigboard.h b/ports/stm/boards/espruino_wifi/mpconfigboard.h index 80aae3ad4..b7f38f69b 100644 --- a/ports/stm/boards/espruino_wifi/mpconfigboard.h +++ b/ports/stm/boards/espruino_wifi/mpconfigboard.h @@ -32,6 +32,7 @@ #define FLASH_SIZE (0x80000) //512K #define FLASH_PAGE_SIZE (0x4000) //16K -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) #define BOARD_OVERWRITE_SWD (1) diff --git a/ports/stm/boards/espruino_wifi/mpconfigboard.mk b/ports/stm/boards/espruino_wifi/mpconfigboard.mk index 70d0ea2bd..ee82095ff 100644 --- a/ports/stm/boards/espruino_wifi/mpconfigboard.mk +++ b/ports/stm/boards/espruino_wifi/mpconfigboard.mk @@ -10,6 +10,5 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F411xE MCU_PACKAGE = UFQFPN48 -LD_COMMON = boards/common_default.ld +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F411_fs.ld - diff --git a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h index 8f8e24566..0d49748c8 100644 --- a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h +++ b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h @@ -34,8 +34,8 @@ #define MICROPY_HW_NEOPIXEL (&pin_PC00) -#define BOARD_OSC_DIV (12) -#define HSE_VALUE ((uint32_t)12000000U) +#define HSE_VALUE ((uint32_t)12000000U) +#define LSE_VALUE ((uint32_t)32768) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) // On-board flash diff --git a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk index 85ed18f4f..d98bd29ec 100644 --- a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk +++ b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk @@ -12,8 +12,7 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F405xx MCU_PACKAGE = LQFP64 -LD_COMMON = boards/common_default.ld -LD_DEFAULT = boards/STM32F405_default.ld +LD_COMMON = boards/common_default.ld +LD_DEFAULT = boards/STM32F405_default.ld LD_BOOT = boards/STM32F405_boot.ld # UF2 boot option UF2_OFFSET = 0x8010000 - diff --git a/ports/stm/boards/meowbit_v121/mpconfigboard.h b/ports/stm/boards/meowbit_v121/mpconfigboard.h index 268a66015..106f25b15 100644 --- a/ports/stm/boards/meowbit_v121/mpconfigboard.h +++ b/ports/stm/boards/meowbit_v121/mpconfigboard.h @@ -35,10 +35,9 @@ #define AUTORESET_DELAY_MS 500 #define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000) -#define BOARD_OSC_DIV (12) +#define HSE_VALUE ((uint32_t)12000000U) +#define LSE_VALUE ((uint32_t)32000U) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) -#define HSE_VALUE ((uint32_t)12000000U) -#define LSE_VALUE ((uint32_t)32000U) #define BOARD_NO_VBUS_SENSE (1) #define BOARD_VTOR_DEFER (1) //Leave VTOR relocation to bootloader diff --git a/ports/stm/boards/meowbit_v121/mpconfigboard.mk b/ports/stm/boards/meowbit_v121/mpconfigboard.mk index cd8d3b548..cf60c89c2 100644 --- a/ports/stm/boards/meowbit_v121/mpconfigboard.mk +++ b/ports/stm/boards/meowbit_v121/mpconfigboard.mk @@ -15,7 +15,6 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F401xE MCU_PACKAGE = LQFP64 -LD_COMMON = boards/common_default.ld -LD_FILE = boards/STM32F401xe_boot.ld +LD_COMMON = boards/common_default.ld +LD_FILE = boards/STM32F401xe_boot.ld # LD_FILE = boards/STM32F401xe_fs.ld # use for internal flash - diff --git a/ports/stm/boards/nucleo_f746zg/mpconfigboard.h b/ports/stm/boards/nucleo_f746zg/mpconfigboard.h index b1abd140f..c1f0d59b2 100644 --- a/ports/stm/boards/nucleo_f746zg/mpconfigboard.h +++ b/ports/stm/boards/nucleo_f746zg/mpconfigboard.h @@ -33,7 +33,10 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) #define DEBUG_UART_TX (&pin_PD08) #define DEBUG_UART_RX (&pin_PD09) diff --git a/ports/stm/boards/nucleo_f746zg/mpconfigboard.mk b/ports/stm/boards/nucleo_f746zg/mpconfigboard.mk index 8a793d570..f23f642e7 100644 --- a/ports/stm/boards/nucleo_f746zg/mpconfigboard.mk +++ b/ports/stm/boards/nucleo_f746zg/mpconfigboard.mk @@ -10,5 +10,5 @@ MCU_SERIES = F7 MCU_VARIANT = STM32F746xx MCU_PACKAGE = LQFP144 -LD_COMMON = boards/common_default.ld +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F746xG_fs.ld diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h index 314c96cb5..21e0ef0ba 100644 --- a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h +++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h @@ -32,5 +32,7 @@ #define FLASH_SIZE (0x200000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) -#define BOARD_HAS_LOW_SPEED_CRYSTAL (0) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk b/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk index c8c2a3d2b..4e5e1bc7c 100644 --- a/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk +++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk @@ -10,6 +10,5 @@ MCU_SERIES = F7 MCU_VARIANT = STM32F767xx MCU_PACKAGE = LQFP144 -LD_COMMON = boards/common_default.ld +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F767_fs.ld - diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h index 8909cc5be..1ae7f81a4 100644 --- a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h +++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h @@ -31,5 +31,7 @@ #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) -#define BOARD_HAS_LOW_SPEED_CRYSTAL (0) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk index 01ace06a2..ea99a1e10 100644 --- a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk +++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk @@ -10,6 +10,5 @@ MCU_SERIES = H7 MCU_VARIANT = STM32H743xx MCU_PACKAGE = LQFP144 -LD_COMMON = boards/common_tcm.ld +LD_COMMON = boards/common_tcm.ld LD_FILE = boards/STM32H743_fs.ld - diff --git a/ports/stm/boards/openmv_h7/mpconfigboard.h b/ports/stm/boards/openmv_h7/mpconfigboard.h index 9a049ed2c..cf9d6e7d1 100644 --- a/ports/stm/boards/openmv_h7/mpconfigboard.h +++ b/ports/stm/boards/openmv_h7/mpconfigboard.h @@ -31,7 +31,5 @@ #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (12) -#define HSE_VALUE ((uint32_t)12000000) +#define HSE_VALUE ((uint32_t)12000000) #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) - diff --git a/ports/stm/boards/openmv_h7/mpconfigboard.mk b/ports/stm/boards/openmv_h7/mpconfigboard.mk index 242dac52c..4ff0f18d5 100644 --- a/ports/stm/boards/openmv_h7/mpconfigboard.mk +++ b/ports/stm/boards/openmv_h7/mpconfigboard.mk @@ -10,6 +10,5 @@ MCU_SERIES = H7 MCU_VARIANT = STM32H743xx MCU_PACKAGE = LQFP100_x7 -LD_COMMON = boards/common_tcm.ld +LD_COMMON = boards/common_tcm.ld LD_FILE = boards/STM32H743_fs.ld - diff --git a/ports/stm/boards/openmv_h7/openmv.csv b/ports/stm/boards/openmv_h7/openmv.csv index 9045e1ea2..f9d4ebc40 100644 --- a/ports/stm/boards/openmv_h7/openmv.csv +++ b/ports/stm/boards/openmv_h7/openmv.csv @@ -23,4 +23,4 @@ I2C4_SDA,PD13 SPI2_NSS,PB12 SPI2_SCK,PB13 SPI2_MISO,PB14 -SPI2_MOSI,PB15
\ No newline at end of file +SPI2_MOSI,PB15 diff --git a/ports/stm/boards/pyb_nano_v2/mpconfigboard.h b/ports/stm/boards/pyb_nano_v2/mpconfigboard.h index 721a91def..7c1ab31e3 100644 --- a/ports/stm/boards/pyb_nano_v2/mpconfigboard.h +++ b/ports/stm/boards/pyb_nano_v2/mpconfigboard.h @@ -32,7 +32,8 @@ #define FLASH_SIZE (0x80000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) // On-board flash diff --git a/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk b/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk index 0a06852fb..08a266816 100644 --- a/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk +++ b/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk @@ -12,6 +12,5 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F411xE MCU_PACKAGE = UFQFPN48 -LD_COMMON = boards/common_default.ld +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F411_fs.ld - diff --git a/ports/stm/boards/pyboard_v11/mpconfigboard.h b/ports/stm/boards/pyboard_v11/mpconfigboard.h index 77fab2c69..50a90c52b 100644 --- a/ports/stm/boards/pyboard_v11/mpconfigboard.h +++ b/ports/stm/boards/pyboard_v11/mpconfigboard.h @@ -32,10 +32,9 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (12) +#define HSE_VALUE ((uint32_t)12000000) +#define LSE_VALUE ((uint32_t)32000U) #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) -#define HSE_VALUE ((uint32_t)12000000U) -#define LSE_VALUE ((uint32_t)32000U) #define DEFAULT_I2C_BUS_SCL (&pin_PB06) #define DEFAULT_I2C_BUS_SDA (&pin_PB07) diff --git a/ports/stm/boards/pyboard_v11/mpconfigboard.mk b/ports/stm/boards/pyboard_v11/mpconfigboard.mk index 9d8b0f3f2..c0c0f5f6c 100644 --- a/ports/stm/boards/pyboard_v11/mpconfigboard.mk +++ b/ports/stm/boards/pyboard_v11/mpconfigboard.mk @@ -10,6 +10,5 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F405xx MCU_PACKAGE = LQFP64 -LD_COMMON = boards/common_default.ld +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F405_fs.ld - diff --git a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h index a21060a84..83a8bded3 100644 --- a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h +++ b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h @@ -32,11 +32,9 @@ #define FLASH_SIZE (0x80000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (25) +#define HSE_VALUE ((uint32_t)25000000) #define BOARD_NO_VBUS_SENSE (1) - #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) -#define HSE_VALUE ((uint32_t)25000000U) // On-board flash // #define SPI_FLASH_MOSI_PIN (&pin_PA07) diff --git a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk index 62887c028..0054232e1 100644 --- a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk +++ b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk @@ -15,6 +15,5 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F411xE MCU_PACKAGE = UFQFPN48 -LD_COMMON = boards/common_default.ld +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F411_fs.ld - diff --git a/ports/stm/boards/stm32f411ce_blackpill/pins.c b/ports/stm/boards/stm32f411ce_blackpill/pins.c index aa9736fc4..2f8aab6e8 100644 --- a/ports/stm/boards/stm32f411ce_blackpill/pins.c +++ b/ports/stm/boards/stm32f411ce_blackpill/pins.c @@ -33,7 +33,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, { MP_ROM_QSTR(MP_QSTR_C15), MP_ROM_PTR(&pin_PC15) }, { MP_ROM_QSTR(MP_QSTR_C14), MP_ROM_PTR(&pin_PC14) }, - { MP_ROM_QSTR(MP_QSTR_C13), MP_ROM_PTR(&pin_PC13) }, - { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_C13), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PC13) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h index 3956a365c..0be43f4fb 100644 --- a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h @@ -32,8 +32,8 @@ #define FLASH_SIZE (0x80000) //512K #define FLASH_PAGE_SIZE (0x4000) //16K -#define BOARD_OSC_DIV (8) - +#define HSE_VALUE ((uint32_t)8000000) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) // The schematic has a 32k crystal that isn't fitted. Uncommented the line below if you add it. diff --git a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk index 761602acd..ca2f10ba3 100644 --- a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk @@ -12,4 +12,3 @@ MCU_PACKAGE = LQFP100_f4 LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F411_fs.ld - diff --git a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h index 112d2a83c..6b9ab6467 100644 --- a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h @@ -32,9 +32,11 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) - +#define HSE_VALUE ((uint32_t)8000000) +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal #define BOARD_HAS_LOW_SPEED_CRYSTAL (1) +#define CPY_CLK_USB_USES_AUDIOPLL (1) #define DEFAULT_I2C_BUS_SCL (&pin_PB10) #define DEFAULT_I2C_BUS_SDA (&pin_PB09) diff --git a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk index 09e7bda85..04d2a9b0d 100644 --- a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk @@ -17,5 +17,3 @@ MCU_PACKAGE = LQFP144 LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F412_fs.ld - - diff --git a/ports/stm/boards/stm32f4_discovery/mpconfigboard.h b/ports/stm/boards/stm32f4_discovery/mpconfigboard.h index 28a370afd..44ee07378 100644 --- a/ports/stm/boards/stm32f4_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f4_discovery/mpconfigboard.h @@ -32,6 +32,6 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (8) - -#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) +#define HSE_VALUE ((uint32_t)8000000) +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (0) diff --git a/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk index 57a65f75a..09652d9ad 100644 --- a/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk @@ -12,4 +12,3 @@ MCU_PACKAGE = LQFP100_f4 LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F407_fs.ld - diff --git a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h index 28784f6ab..1fa69182a 100644 --- a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h @@ -34,10 +34,15 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_OSC_DIV (25) -#define HSE_VALUE ((uint32_t)25000000) -#define BOARD_OSC_PLLN (400) -#define BOARD_OSC_PLLQ (9) +// Lower frequency to allow external RAM use +#define HSE_VALUE ((uint32_t)25000000) +#define LSE_VALUE ((uint32_t)32768) +#define CPY_CLK_PLLN (400) +#define CPY_CLK_PLLQ (9) +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_6) +#define CPY_CLK_USB_USES_AUDIOPLL (1) + +#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) -#define BOARD_FLASH_LATENCY FLASH_LATENCY_6 #define BOARD_NO_VBUS_SENSE 1 diff --git a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.mk index 0b4ccc760..ff8456df6 100644 --- a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.mk @@ -10,5 +10,5 @@ MCU_SERIES = F7 MCU_VARIANT = STM32F746xx MCU_PACKAGE = TFBGA216 -LD_COMMON = boards/common_default.ld +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F746xG_fs.ld diff --git a/ports/stm/boards/system_stm32f4xx.c b/ports/stm/boards/system_stm32f4xx.c index caa4f9caf..d8c745dbb 100644 --- a/ports/stm/boards/system_stm32f4xx.c +++ b/ports/stm/boards/system_stm32f4xx.c @@ -1,6 +1,6 @@ /* * Taken from ST Cube library and modified. See below for original header. - * + * * Modifications copyright (c) 2019 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -28,16 +28,16 @@ * @author MCD Application Team * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * - * This file provides two functions and one global variable to be called from + * This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and + * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. @@ -79,8 +79,8 @@ /** @addtogroup stm32f4xx_system * @{ - */ - + */ + /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ @@ -89,7 +89,7 @@ #include "stm32f4xx.h" #include "py/mpconfig.h" -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -121,7 +121,7 @@ /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ STM32F412Zx || STM32F412Vx */ - + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* #define DATA_IN_ExtSDRAM */ @@ -131,7 +131,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ @@ -153,7 +153,7 @@ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. @@ -170,7 +170,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; */ #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); + static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /** @@ -183,7 +183,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory + * Initialize the FPU setting, vector table location and External memory * configuration. * @param None * @retval None @@ -214,7 +214,7 @@ void SystemInit(void) RCC->CIR = 0x00000000; #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); + SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /* Configure the Vector Table location add offset address ------------------*/ @@ -232,41 +232,41 @@ void SystemInit(void) * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value * depends on the application requirements), user has to ensure that HSE_VALUE * is same as the real frequency of the crystal used. Otherwise, this function * may have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. - * + * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - + /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; @@ -282,10 +282,10 @@ void SystemCoreClockUpdate(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - + if (pllsource != 0) { /* HSE used as PLL clock source */ @@ -334,79 +334,79 @@ void SystemInit_ExtMemCtl(void) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; - + /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -414,50 +414,50 @@ void SystemInit_ExtMemCtl(void) tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); FMC_Bank5_6->SDCR[0] = 0x000019E4; - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ FMC_Bank5_6->SDCMR = 0x00000073; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ FMC_Bank5_6->SDCMR = 0x00046014; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) @@ -465,7 +465,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001091; @@ -473,7 +473,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ - (void)(tmp); + (void)(tmp); } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) @@ -499,13 +499,13 @@ void SystemInit_ExtMemCtl(void) clock */ RCC->AHB1ENR |= 0x0000007D; #else - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001F8; -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + #if defined(STM32F446xx) /* Connect PAx pins to FMC Alternate function */ GPIOA->AFR[0] |= 0xC0000000; @@ -535,78 +535,78 @@ void SystemInit_ExtMemCtl(void) /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ + /* Configure PDx pins speed to 50 MHz */ GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ + /* Configure PEx pins speed to 50 MHz */ GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) + || defined(STM32F469xx) || defined(STM32F479xx) /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -616,65 +616,65 @@ void SystemInit_ExtMemCtl(void) /* Configure and enable SDRAM bank1 */ #if defined(STM32F446xx) FMC_Bank5_6->SDCR[0] = 0x00001954; -#else +#else FMC_Bank5_6->SDCR[0] = 0x000019E4; #endif /* STM32F446xx */ - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x000000F3; -#else +#else FMC_Bank5_6->SDCMR = 0x00000073; #endif /* STM32F446xx */ timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x00044014; -#else +#else FMC_Bank5_6->SDCMR = 0x00046014; #endif /* STM32F446xx */ timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; #if defined(STM32F446xx) FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); -#else +#else FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); #endif /* STM32F446xx */ - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #endif /* DATA_IN_ExtSDRAM */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ @@ -689,55 +689,55 @@ void SystemInit_ExtMemCtl(void) RCC->AHB1ENR |= 0x00000078; /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0x00CCCCCC; GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ + /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0x00CCCCCC; GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00085AAA; - /* Configure PGx pins speed to 100 MHz */ + /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000CAFFF; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /*-- FMC/FSMC Configuration --------------------------------------------------*/ /* Enable the FMC/FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -749,7 +749,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); @@ -770,8 +770,8 @@ void SystemInit_ExtMemCtl(void) #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ - (void)(tmp); + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); } #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ /** diff --git a/ports/stm/boards/system_stm32f7xx.c b/ports/stm/boards/system_stm32f7xx.c index 184fefb36..4aebc3d35 100644 --- a/ports/stm/boards/system_stm32f7xx.c +++ b/ports/stm/boards/system_stm32f7xx.c @@ -4,16 +4,16 @@ * @author MCD Application Team * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * - * This file provides two functions and one global variable to be called from + * This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and + * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f7xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. @@ -39,15 +39,15 @@ /** @addtogroup stm32f7xx_system * @{ - */ - + */ + /** @addtogroup STM32F7xx_System_Private_Includes * @{ */ #include "stm32f7xx.h" -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -76,7 +76,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ @@ -99,7 +99,7 @@ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. @@ -126,7 +126,7 @@ /** * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the + * Initialize the Embedded Flash Interface, the PLL and update the * SystemFrequency variable. * @param None * @retval None @@ -154,41 +154,41 @@ void SystemInit(void) * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. - * + * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - + /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; @@ -204,10 +204,10 @@ void SystemCoreClockUpdate(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - + if (pllsource != 0) { /* HSE used as PLL clock source */ @@ -216,7 +216,7 @@ void SystemCoreClockUpdate(void) else { /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; @@ -240,8 +240,8 @@ void SystemCoreClockUpdate(void) /** * @} */ - + /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/boards/system_stm32h7xx.c b/ports/stm/boards/system_stm32h7xx.c index 2132f26a0..bbb0f821f 100644 --- a/ports/stm/boards/system_stm32h7xx.c +++ b/ports/stm/boards/system_stm32h7xx.c @@ -1,6 +1,6 @@ /* * Taken from ST Cube library and modified. See below for original header. - * + * * Modifications copyright (c) 2020 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h index 7102b1242..394fbfd84 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.h +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -40,12 +40,11 @@ #define FLASH_PAGE_SIZE (0x4000) #define BOARD_FLASH_SIZE (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000) -#define BOARD_OSC_DIV (24) +#define HSE_VALUE ((uint32_t)24000000U) #define BOARD_OVERWRITE_SWD (1) #define BOARD_NO_VBUS_SENSE (1) #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) -#define HSE_VALUE ((uint32_t)24000000U) // Status LEDs #define MICROPY_HW_LED_STATUS (&pin_PA02) diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c index 559d9658e..eed54eb3c 100644 --- a/ports/stm/boards/thunderpack/pins.c +++ b/ports/stm/boards/thunderpack/pins.c @@ -10,7 +10,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PA6), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_PA7), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_PA8), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA9), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA9), MP_ROM_PTR(&pin_PA09) }, { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, diff --git a/ports/stm/common-hal/busio/I2C.c b/ports/stm/common-hal/busio/I2C.c index e3c59e7e0..48c4c1933 100644 --- a/ports/stm/common-hal/busio/I2C.c +++ b/ports/stm/common-hal/busio/I2C.c @@ -122,7 +122,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, #if (CPY_STM32H7 || CPY_STM32F7) self->handle.Init.Timing = 0x40604E73; //Taken from STCube examples #else - self->handle.Init.ClockSpeed = 100000; + self->handle.Init.ClockSpeed = frequency; self->handle.Init.DutyCycle = I2C_DUTYCYCLE_2; #endif diff --git a/ports/stm/common-hal/busio/SPI.c b/ports/stm/common-hal/busio/SPI.c index d3310efe0..65eeb8ebc 100644 --- a/ports/stm/common-hal/busio/SPI.c +++ b/ports/stm/common-hal/busio/SPI.c @@ -269,18 +269,14 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, } void common_hal_busio_spi_never_reset(busio_spi_obj_t *self) { - for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_spi_banks); i++) { - if (mcu_spi_banks[i] == self->handle.Instance) { - never_reset_spi[i] = true; - never_reset_pin_number(self->sck->pin->port, self->sck->pin->number); - if (self->mosi != NULL) { - never_reset_pin_number(self->mosi->pin->port, self->mosi->pin->number); - } - if (self->miso != NULL) { - never_reset_pin_number(self->miso->pin->port, self->miso->pin->number); - } - break; - } + + never_reset_spi[self->sck->periph_index - 1] = true; + never_reset_pin_number(self->sck->pin->port, self->sck->pin->number); + if (self->mosi != NULL) { + never_reset_pin_number(self->mosi->pin->port, self->mosi->pin->number); + } + if (self->miso != NULL) { + never_reset_pin_number(self->miso->pin->port, self->miso->pin->number); } } diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c index c83479126..86a932290 100644 --- a/ports/stm/common-hal/busio/UART.c +++ b/ports/stm/common-hal/busio/UART.c @@ -259,7 +259,7 @@ void common_hal_busio_uart_never_reset(busio_uart_obj_t *self) { } bool common_hal_busio_uart_deinited(busio_uart_obj_t *self) { - return self->tx->pin == NULL; + return (self->tx->pin == NULL && self->rx->pin == NULL); } void common_hal_busio_uart_deinit(busio_uart_obj_t *self) { @@ -272,10 +272,15 @@ void common_hal_busio_uart_deinit(busio_uart_obj_t *self) { } } - reset_pin_number(self->tx->pin->port,self->tx->pin->number); - reset_pin_number(self->rx->pin->port,self->rx->pin->number); - self->tx = NULL; - self->rx = NULL; + if (self->tx) { + reset_pin_number(self->tx->pin->port,self->tx->pin->number); + self->tx = NULL; + } + if (self->rx) { + reset_pin_number(self->rx->pin->port,self->rx->pin->number); + self->rx = NULL; + } + ringbuf_free(&self->ringbuf); } diff --git a/ports/stm/common-hal/digitalio/DigitalInOut.c b/ports/stm/common-hal/digitalio/DigitalInOut.c index 647a46e90..1354e1a32 100644 --- a/ports/stm/common-hal/digitalio/DigitalInOut.c +++ b/ports/stm/common-hal/digitalio/DigitalInOut.c @@ -29,7 +29,7 @@ #include "py/runtime.h" #include "supervisor/shared/translate.h" -// The HAL is sparse on obtaining register information, so we use the LLs here. +// The HAL is sparse on obtaining register information, so we use the LLs here. #if (CPY_STM32H7) #include "stm32h7xx_ll_gpio.h" #elif (CPY_STM32F7) @@ -85,12 +85,13 @@ void common_hal_digitalio_digitalinout_switch_to_input( common_hal_digitalio_digitalinout_set_pull(self, pull); } -void common_hal_digitalio_digitalinout_switch_to_output( +digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( digitalio_digitalinout_obj_t *self, bool value, digitalio_drive_mode_t drive_mode) { common_hal_digitalio_digitalinout_set_drive_mode(self, drive_mode); common_hal_digitalio_digitalinout_set_value(self, value); + return DIGITALINOUT_OK; } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( @@ -112,7 +113,7 @@ bool common_hal_digitalio_digitalinout_get_value( : LL_GPIO_IsOutputPinSet(pin_port(self->pin->port), pin_mask(self->pin->number)); } -void common_hal_digitalio_digitalinout_set_drive_mode( +digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( digitalio_digitalinout_obj_t *self, digitalio_drive_mode_t drive_mode) { GPIO_InitTypeDef GPIO_InitStruct = {0}; @@ -122,6 +123,7 @@ void common_hal_digitalio_digitalinout_set_drive_mode( GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; HAL_GPIO_Init(pin_port(self->pin->port), &GPIO_InitStruct); + return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( diff --git a/ports/stm/common-hal/nvm/ByteArray.c b/ports/stm/common-hal/nvm/ByteArray.c index 1aaf54653..462d3aa9d 100644 --- a/ports/stm/common-hal/nvm/ByteArray.c +++ b/ports/stm/common-hal/nvm/ByteArray.c @@ -60,7 +60,7 @@ bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, return false; } } - + // Finish up HAL_FLASH_Lock(); return true; diff --git a/ports/stm/common-hal/os/__init__.c b/ports/stm/common-hal/os/__init__.c index eef58bfe2..84deb8175 100644 --- a/ports/stm/common-hal/os/__init__.c +++ b/ports/stm/common-hal/os/__init__.c @@ -92,4 +92,4 @@ bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { #else return false; #endif -}
\ No newline at end of file +} diff --git a/ports/stm/common-hal/supervisor/Runtime.c b/ports/stm/common-hal/supervisor/Runtime.c index feab6987d..ea663f897 100755 --- a/ports/stm/common-hal/supervisor/Runtime.c +++ b/ports/stm/common-hal/supervisor/Runtime.c @@ -35,4 +35,3 @@ bool common_hal_get_serial_connected(void) { bool common_hal_get_serial_bytes_available(void) { return (bool) serial_bytes_available(); } - diff --git a/ports/stm/common-hal/supervisor/__init__.c b/ports/stm/common-hal/supervisor/__init__.c index ac88556b4..6dca35fb5 100755 --- a/ports/stm/common-hal/supervisor/__init__.c +++ b/ports/stm/common-hal/supervisor/__init__.c @@ -37,4 +37,4 @@ const super_runtime_obj_t common_hal_supervisor_runtime_obj = { .base = { .type = &supervisor_runtime_type, }, -};
\ No newline at end of file +}; diff --git a/ports/stm/packages/LQFP100_f4.c b/ports/stm/packages/LQFP100_f4.c index 5bc0a5158..9136b9495 100644 --- a/ports/stm/packages/LQFP100_f4.c +++ b/ports/stm/packages/LQFP100_f4.c @@ -114,4 +114,4 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // VDD --------------------------------------------*/ }; -MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
\ No newline at end of file +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/LQFP100_x7.c b/ports/stm/packages/LQFP100_x7.c index 23d89a826..4d3d5f45a 100644 --- a/ports/stm/packages/LQFP100_x7.c +++ b/ports/stm/packages/LQFP100_x7.c @@ -112,4 +112,4 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // VDD --------------------------------------------*/ }; -MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
\ No newline at end of file +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/LQFP144.c b/ports/stm/packages/LQFP144.c index 36683bb64..5e0d743d7 100644 --- a/ports/stm/packages/LQFP144.c +++ b/ports/stm/packages/LQFP144.c @@ -154,6 +154,6 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, // PDR_ON -----------------------------------------*/ // VDD --------------------------------------------*/ - + }; -MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
\ No newline at end of file +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/LQFP64.c b/ports/stm/packages/LQFP64.c index e6a492bc3..52ca27cd9 100644 --- a/ports/stm/packages/LQFP64.c +++ b/ports/stm/packages/LQFP64.c @@ -76,6 +76,6 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, // VSS --------------------------------------------*/ // VDD --------------------------------------------*/ - + }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/UFQFPN48.c b/ports/stm/packages/UFQFPN48.c index ae4bcf6cd..5304482ec 100644 --- a/ports/stm/packages/UFQFPN48.c +++ b/ports/stm/packages/UFQFPN48.c @@ -58,6 +58,6 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, // VSS --------------------------------------------*/ // VDD --------------------------------------------*/ - + }; -MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
\ No newline at end of file +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index 316dbbec5..34089c849 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -51,8 +51,8 @@ typedef struct { // Timer Peripheral typedef struct { - uint8_t tim_index:4; - uint8_t altfn_index:4; + uint8_t tim_index:4; + uint8_t altfn_index:4; uint8_t channel_index:4; const mcu_pin_obj_t * pin; } mcu_tim_pin_obj_t; diff --git a/ports/stm/peripherals/pins.h b/ports/stm/peripherals/pins.h index 8f06d012e..358313f56 100644 --- a/ports/stm/peripherals/pins.h +++ b/ports/stm/peripherals/pins.h @@ -39,7 +39,7 @@ typedef struct { mp_obj_base_t base; uint8_t port:4; uint8_t number:4; - uint8_t adc_unit:3; + uint8_t adc_unit:3; uint8_t adc_channel:5; } mcu_pin_obj_t; @@ -50,8 +50,8 @@ typedef struct { #define ADC_3 4 //STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin, -//but all 3 ADCs will share the same input number per pin. -//F4 family has 3 ADC max, 24 channels max. +//but all 3 ADCs will share the same input number per pin. +//F4 family has 3 ADC max, 24 channels max. #define ADC_INPUT(mask, number) \ .adc_unit = mask, \ .adc_channel = number, @@ -63,7 +63,7 @@ typedef struct { extern const mp_obj_type_t mcu_pin_type; // STM32 can have up to 9 ports, each restricted to 16 pins -// We split the pin/port evenly, in contrast to nrf. +// We split the pin/port evenly, in contrast to nrf. #define PIN(p_port, p_number, p_adc) \ { \ { &mcu_pin_type }, \ diff --git a/ports/stm/peripherals/stm32f4/clocks.c b/ports/stm/peripherals/stm32f4/clocks.c new file mode 100644 index 000000000..7a16812b3 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/clocks.c @@ -0,0 +1,120 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" +#include "supervisor/shared/safe_mode.h" +#include <stdbool.h> + +// F4 Series +#ifdef STM32F401xE +#include "stm32f4/stm32f401xe/clocks.h" +#endif +#ifdef STM32F411xE +#include "stm32f4/stm32f411xe/clocks.h" +#endif +#ifdef STM32F412Zx +#include "stm32f4/stm32f412zx/clocks.h" +#endif +#ifdef STM32F405xx +#include "stm32f4/stm32f405xx/clocks.h" +#endif +#ifdef STM32F407xx +#include "stm32f4/stm32f407xx/clocks.h" +#endif + +void stm32_peripherals_clocks_init(void) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + bool lse_failure = false; + + // Set voltage scaling in accordance with system clock speed + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); + + // Set up primary PLL and HSE clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + #else + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + #endif + RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; + RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; + RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; + #if (CPY_CLK_USB_USES_AUDIOPLL) + RCC_OscInitStruct.PLL.PLLR = 2; // Unused but required by HAL + #endif + + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // Failure likely means a LSE issue - attempt to swap to LSI, and set to crash + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // No HSE means no USB, so just fail forever + while(1); + } + lse_failure = true; + } + + // Configure bus clock sources and divisors + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; + RCC_ClkInitStruct.APB1CLKDivider = CPY_CLK_APB1DIV; + RCC_ClkInitStruct.APB2CLKDivider = CPY_CLK_APB2DIV; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, CPY_CLK_FLASH_LATENCY); + + // Set up non-bus peripherals + // TODO: I2S settings go here + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + #else + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + #endif + #if (CPY_CLK_USB_USES_AUDIOPLL) + // Not supported by all lines. Should always result in 48M. + PeriphClkInitStruct.PLLI2S.PLLI2SM = HSE_VALUE/1000000; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_CK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ; + #endif + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + if (lse_failure) { + reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT? + } +} diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c deleted file mode 100644 index 194992e81..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c +++ /dev/null @@ -1,62 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h new file mode 100644 index 000000000..d157d944a --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h @@ -0,0 +1,63 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F401 +// Line Type: Access Line +// Speed: 84MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE2) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (336) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV4) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (7) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_2) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c b/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c index 514bcc506..d10fcbb6f 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c @@ -42,4 +42,3 @@ void stm32_peripherals_gpio_init(void) { never_reset_pin_number(0,13); //PA13 SWDIO never_reset_pin_number(0,14); //PA14 SWCLK } - diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h index 334a14db5..ae416bda1 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h @@ -54,4 +54,4 @@ extern const mcu_periph_obj_t mcu_uart_rx_list[6]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H
\ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c index eea2a1a1b..ed89f0de6 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c @@ -120,4 +120,4 @@ const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC); -const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC);
\ No newline at end of file +const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c deleted file mode 100644 index f4c583068..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c +++ /dev/null @@ -1,64 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - // APB1 must always be on so that we can talk to the RTC for timing. - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - // TODO: Only turn on APB2 when it is needed to save power. - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h new file mode 100644 index 000000000..87faec035 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h @@ -0,0 +1,63 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F405 +// Line Type: Foundation Line +// Speed: 168MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (336) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (7) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_5) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c index a5f4eae78..03fba6289 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c @@ -48,12 +48,10 @@ void stm32_peripherals_gpio_init(void) { // never_reset_pin_number(1,4); //PB4 JTRST // Port H is not included in GPIO port array - // never_reset_pin_number(5,0); //PH0 JTDO + // never_reset_pin_number(5,0); //PH0 JTDO // never_reset_pin_number(5,1); //PH1 JTRST } void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { } - - diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h index 98b4fab9c..df67a99d7 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h @@ -54,4 +54,4 @@ extern const mcu_periph_obj_t mcu_uart_rx_list[12]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H
\ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c index 0f669f1c6..4282741a8 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c @@ -38,17 +38,17 @@ const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT -const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF03 = PIN(5, 3, ADC_INPUT(ADC_3,9)); // 144 only -const mcu_pin_obj_t pin_PF04 = PIN(5, 4, ADC_INPUT(ADC_3,14)); // 144 only -const mcu_pin_obj_t pin_PF05 = PIN(5, 5, ADC_INPUT(ADC_3,15)); // 144 only -const mcu_pin_obj_t pin_PF06 = PIN(5, 6, ADC_INPUT(ADC_3,4)); // 144 only -const mcu_pin_obj_t pin_PF07 = PIN(5, 7, ADC_INPUT(ADC_3,5)); // 144 only -const mcu_pin_obj_t pin_PF08 = PIN(5, 8, ADC_INPUT(ADC_3,6)); // 144 only -const mcu_pin_obj_t pin_PF09 = PIN(5, 9, ADC_INPUT(ADC_3,7)); // 144 only -const mcu_pin_obj_t pin_PF10 = PIN(5, 10, ADC_INPUT(ADC_3,8)); // 144 only +const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF03 = PIN(5, 3, ADC_INPUT(ADC_3,9)); // 144 only +const mcu_pin_obj_t pin_PF04 = PIN(5, 4, ADC_INPUT(ADC_3,14)); // 144 only +const mcu_pin_obj_t pin_PF05 = PIN(5, 5, ADC_INPUT(ADC_3,15)); // 144 only +const mcu_pin_obj_t pin_PF06 = PIN(5, 6, ADC_INPUT(ADC_3,4)); // 144 only +const mcu_pin_obj_t pin_PF07 = PIN(5, 7, ADC_INPUT(ADC_3,5)); // 144 only +const mcu_pin_obj_t pin_PF08 = PIN(5, 8, ADC_INPUT(ADC_3,6)); // 144 only +const mcu_pin_obj_t pin_PF09 = PIN(5, 9, ADC_INPUT(ADC_3,7)); // 144 only +const mcu_pin_obj_t pin_PF10 = PIN(5, 10, ADC_INPUT(ADC_3,8)); // 144 only const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_123,10)); const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_123,11)); @@ -71,14 +71,14 @@ const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_12,8)); const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_12,9)); const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); //BOOT1 -const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); @@ -91,7 +91,7 @@ const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC); const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC); const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); -const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); +const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.h b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.h index b3e5e3344..e722b6e5a 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.h @@ -38,17 +38,17 @@ extern const mcu_pin_obj_t pin_PC13; extern const mcu_pin_obj_t pin_PC14; //pg 51 extern const mcu_pin_obj_t pin_PC15; -extern const mcu_pin_obj_t pin_PF00; // 144 only -extern const mcu_pin_obj_t pin_PF01; // 144 only -extern const mcu_pin_obj_t pin_PF02; // 144 only -extern const mcu_pin_obj_t pin_PF03; // 144 only -extern const mcu_pin_obj_t pin_PF04; // 144 only -extern const mcu_pin_obj_t pin_PF05; // 144 only -extern const mcu_pin_obj_t pin_PF06; // 144 only -extern const mcu_pin_obj_t pin_PF07; // 144 only -extern const mcu_pin_obj_t pin_PF08; // 144 only -extern const mcu_pin_obj_t pin_PF09; // 144 only -extern const mcu_pin_obj_t pin_PF10; // 144 only +extern const mcu_pin_obj_t pin_PF00; // 144 only +extern const mcu_pin_obj_t pin_PF01; // 144 only +extern const mcu_pin_obj_t pin_PF02; // 144 only +extern const mcu_pin_obj_t pin_PF03; // 144 only +extern const mcu_pin_obj_t pin_PF04; // 144 only +extern const mcu_pin_obj_t pin_PF05; // 144 only +extern const mcu_pin_obj_t pin_PF06; // 144 only +extern const mcu_pin_obj_t pin_PF07; // 144 only +extern const mcu_pin_obj_t pin_PF08; // 144 only +extern const mcu_pin_obj_t pin_PF09; // 144 only +extern const mcu_pin_obj_t pin_PF10; // 144 only //pg 52 extern const mcu_pin_obj_t pin_PC00; extern const mcu_pin_obj_t pin_PC01; @@ -69,13 +69,13 @@ extern const mcu_pin_obj_t pin_PC05; extern const mcu_pin_obj_t pin_PB00; extern const mcu_pin_obj_t pin_PB01; extern const mcu_pin_obj_t pin_PB02; -extern const mcu_pin_obj_t pin_PF11; // 144 only -extern const mcu_pin_obj_t pin_PF12; // 144 only -extern const mcu_pin_obj_t pin_PF13; // 144 only -extern const mcu_pin_obj_t pin_PF14; // 144 only -extern const mcu_pin_obj_t pin_PF15; // 144 only -extern const mcu_pin_obj_t pin_PG00; // 144 only -extern const mcu_pin_obj_t pin_PG01; // 144 only +extern const mcu_pin_obj_t pin_PF11; // 144 only +extern const mcu_pin_obj_t pin_PF12; // 144 only +extern const mcu_pin_obj_t pin_PF13; // 144 only +extern const mcu_pin_obj_t pin_PF14; // 144 only +extern const mcu_pin_obj_t pin_PF15; // 144 only +extern const mcu_pin_obj_t pin_PG00; // 144 only +extern const mcu_pin_obj_t pin_PG01; // 144 only //pg 55 extern const mcu_pin_obj_t pin_PE07; extern const mcu_pin_obj_t pin_PE08; diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c deleted file mode 100644 index a545aaec5..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c +++ /dev/null @@ -1,62 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h new file mode 100644 index 000000000..5894b4ae8 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h @@ -0,0 +1,63 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F407 +// Line Type: Foundation Line +// Speed: 168MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (336) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (7) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_5) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c index a5f4eae78..03fba6289 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c @@ -48,12 +48,10 @@ void stm32_peripherals_gpio_init(void) { // never_reset_pin_number(1,4); //PB4 JTRST // Port H is not included in GPIO port array - // never_reset_pin_number(5,0); //PH0 JTDO + // never_reset_pin_number(5,0); //PH0 JTDO // never_reset_pin_number(5,1); //PH1 JTRST } void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { } - - diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h index 15cbfb16d..55c00ee93 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h @@ -54,4 +54,4 @@ extern const mcu_periph_obj_t mcu_uart_rx_list[12]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H
\ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c index 0f669f1c6..4282741a8 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c @@ -38,17 +38,17 @@ const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT -const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF03 = PIN(5, 3, ADC_INPUT(ADC_3,9)); // 144 only -const mcu_pin_obj_t pin_PF04 = PIN(5, 4, ADC_INPUT(ADC_3,14)); // 144 only -const mcu_pin_obj_t pin_PF05 = PIN(5, 5, ADC_INPUT(ADC_3,15)); // 144 only -const mcu_pin_obj_t pin_PF06 = PIN(5, 6, ADC_INPUT(ADC_3,4)); // 144 only -const mcu_pin_obj_t pin_PF07 = PIN(5, 7, ADC_INPUT(ADC_3,5)); // 144 only -const mcu_pin_obj_t pin_PF08 = PIN(5, 8, ADC_INPUT(ADC_3,6)); // 144 only -const mcu_pin_obj_t pin_PF09 = PIN(5, 9, ADC_INPUT(ADC_3,7)); // 144 only -const mcu_pin_obj_t pin_PF10 = PIN(5, 10, ADC_INPUT(ADC_3,8)); // 144 only +const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF03 = PIN(5, 3, ADC_INPUT(ADC_3,9)); // 144 only +const mcu_pin_obj_t pin_PF04 = PIN(5, 4, ADC_INPUT(ADC_3,14)); // 144 only +const mcu_pin_obj_t pin_PF05 = PIN(5, 5, ADC_INPUT(ADC_3,15)); // 144 only +const mcu_pin_obj_t pin_PF06 = PIN(5, 6, ADC_INPUT(ADC_3,4)); // 144 only +const mcu_pin_obj_t pin_PF07 = PIN(5, 7, ADC_INPUT(ADC_3,5)); // 144 only +const mcu_pin_obj_t pin_PF08 = PIN(5, 8, ADC_INPUT(ADC_3,6)); // 144 only +const mcu_pin_obj_t pin_PF09 = PIN(5, 9, ADC_INPUT(ADC_3,7)); // 144 only +const mcu_pin_obj_t pin_PF10 = PIN(5, 10, ADC_INPUT(ADC_3,8)); // 144 only const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_123,10)); const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_123,11)); @@ -71,14 +71,14 @@ const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_12,8)); const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_12,9)); const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); //BOOT1 -const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); @@ -91,7 +91,7 @@ const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC); const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC); const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); -const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); +const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.h b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.h index 109dcb922..a247fe631 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.h @@ -38,17 +38,17 @@ extern const mcu_pin_obj_t pin_PC13; extern const mcu_pin_obj_t pin_PC14; //pg 51 extern const mcu_pin_obj_t pin_PC15; -extern const mcu_pin_obj_t pin_PF00; // 144 only -extern const mcu_pin_obj_t pin_PF01; // 144 only -extern const mcu_pin_obj_t pin_PF02; // 144 only -extern const mcu_pin_obj_t pin_PF03; // 144 only -extern const mcu_pin_obj_t pin_PF04; // 144 only -extern const mcu_pin_obj_t pin_PF05; // 144 only -extern const mcu_pin_obj_t pin_PF06; // 144 only -extern const mcu_pin_obj_t pin_PF07; // 144 only -extern const mcu_pin_obj_t pin_PF08; // 144 only -extern const mcu_pin_obj_t pin_PF09; // 144 only -extern const mcu_pin_obj_t pin_PF10; // 144 only +extern const mcu_pin_obj_t pin_PF00; // 144 only +extern const mcu_pin_obj_t pin_PF01; // 144 only +extern const mcu_pin_obj_t pin_PF02; // 144 only +extern const mcu_pin_obj_t pin_PF03; // 144 only +extern const mcu_pin_obj_t pin_PF04; // 144 only +extern const mcu_pin_obj_t pin_PF05; // 144 only +extern const mcu_pin_obj_t pin_PF06; // 144 only +extern const mcu_pin_obj_t pin_PF07; // 144 only +extern const mcu_pin_obj_t pin_PF08; // 144 only +extern const mcu_pin_obj_t pin_PF09; // 144 only +extern const mcu_pin_obj_t pin_PF10; // 144 only //pg 52 extern const mcu_pin_obj_t pin_PC00; extern const mcu_pin_obj_t pin_PC01; @@ -69,13 +69,13 @@ extern const mcu_pin_obj_t pin_PC05; extern const mcu_pin_obj_t pin_PB00; extern const mcu_pin_obj_t pin_PB01; extern const mcu_pin_obj_t pin_PB02; -extern const mcu_pin_obj_t pin_PF11; // 144 only -extern const mcu_pin_obj_t pin_PF12; // 144 only -extern const mcu_pin_obj_t pin_PF13; // 144 only -extern const mcu_pin_obj_t pin_PF14; // 144 only -extern const mcu_pin_obj_t pin_PF15; // 144 only -extern const mcu_pin_obj_t pin_PG00; // 144 only -extern const mcu_pin_obj_t pin_PG01; // 144 only +extern const mcu_pin_obj_t pin_PF11; // 144 only +extern const mcu_pin_obj_t pin_PF12; // 144 only +extern const mcu_pin_obj_t pin_PF13; // 144 only +extern const mcu_pin_obj_t pin_PF14; // 144 only +extern const mcu_pin_obj_t pin_PF15; // 144 only +extern const mcu_pin_obj_t pin_PG00; // 144 only +extern const mcu_pin_obj_t pin_PG01; // 144 only //pg 55 extern const mcu_pin_obj_t pin_PE07; extern const mcu_pin_obj_t pin_PE08; diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c deleted file mode 100644 index 194992e81..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c +++ /dev/null @@ -1,62 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h new file mode 100644 index 000000000..a2fb7bd54 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h @@ -0,0 +1,67 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F411 +// Line Type: Access Line +// Speed: 96MHz + +// Note - the actual maximum frequency is 100MHz, but this requires divisors +// which are incompatible with USB, and there is no additional PLL such as on +// the F412. + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (192) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (4) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_3) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c b/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c index 9aabffa9f..08c6b55cd 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c @@ -56,5 +56,3 @@ void stm32_peripherals_gpio_init(void) { //LEDs are inverted on F411 DISCO void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { } - - diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h index 2c5e5dd56..14a73d12f 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h @@ -54,4 +54,4 @@ extern const mcu_periph_obj_t mcu_uart_rx_list[7]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H
\ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c index eea2a1a1b..ed89f0de6 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c @@ -120,4 +120,4 @@ const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC); -const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC);
\ No newline at end of file +const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c deleted file mode 100644 index 6c4cb5b32..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c +++ /dev/null @@ -1,75 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f4xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the - * device is clocked below the maximum system frequency, to update the - * voltage scaling value regarding system frequency refer to product - * datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 200; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - RCC_OscInitStruct.PLL.PLLR = 2; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLLSAI output as USB clock source */ - PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; - PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - * clocks dividers */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | - RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h new file mode 100644 index 000000000..e1355c8f3 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h @@ -0,0 +1,66 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f4xx_hal.h" + +// Chip: STM32F412 +// Line Type: Access Line +// Speed: 200MHz (MAX) + +// Note - uses the I2S PLL for SUSB to enable full 100MHz operation, since USB +// can't get the right divisors from 100MHz PLL settings. + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (200) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (7) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_3) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (1) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index 3ec1b5b79..5ca4667a4 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -49,6 +49,6 @@ void stm32_peripherals_gpio_init(void) { //never_reset_pin_number(1,4); //PB4 JTRST // Port H is not included in GPIO port array - // never_reset_pin_number(5,0); //PH0 JTDO + // never_reset_pin_number(5,0); //PH0 JTDO // never_reset_pin_number(5,1); //PH1 JTRST } diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h index f668ace75..f6b001a4e 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h @@ -55,4 +55,4 @@ extern const mcu_periph_obj_t mcu_uart_rx_list[12]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H
\ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c index ef3ce6d0e..c1b624f4d 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c @@ -38,17 +38,17 @@ const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT -const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); // 144 only const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10)); const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11)); @@ -71,14 +71,14 @@ const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_1,8)); const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_1,9)); const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); -const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h index 5cf99345c..8914530d2 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h @@ -37,17 +37,17 @@ extern const mcu_pin_obj_t pin_PC13; extern const mcu_pin_obj_t pin_PC14; //pg 51 extern const mcu_pin_obj_t pin_PC15; -extern const mcu_pin_obj_t pin_PF00; // 144 only -extern const mcu_pin_obj_t pin_PF01; // 144 only -extern const mcu_pin_obj_t pin_PF02; // 144 only -extern const mcu_pin_obj_t pin_PF03; // 144 only -extern const mcu_pin_obj_t pin_PF04; // 144 only -extern const mcu_pin_obj_t pin_PF05; // 144 only -extern const mcu_pin_obj_t pin_PF06; // 144 only -extern const mcu_pin_obj_t pin_PF07; // 144 only -extern const mcu_pin_obj_t pin_PF08; // 144 only -extern const mcu_pin_obj_t pin_PF09; // 144 only -extern const mcu_pin_obj_t pin_PF10; // 144 only +extern const mcu_pin_obj_t pin_PF00; // 144 only +extern const mcu_pin_obj_t pin_PF01; // 144 only +extern const mcu_pin_obj_t pin_PF02; // 144 only +extern const mcu_pin_obj_t pin_PF03; // 144 only +extern const mcu_pin_obj_t pin_PF04; // 144 only +extern const mcu_pin_obj_t pin_PF05; // 144 only +extern const mcu_pin_obj_t pin_PF06; // 144 only +extern const mcu_pin_obj_t pin_PF07; // 144 only +extern const mcu_pin_obj_t pin_PF08; // 144 only +extern const mcu_pin_obj_t pin_PF09; // 144 only +extern const mcu_pin_obj_t pin_PF10; // 144 only //pg 52 extern const mcu_pin_obj_t pin_PC00; extern const mcu_pin_obj_t pin_PC01; @@ -68,13 +68,13 @@ extern const mcu_pin_obj_t pin_PC05; extern const mcu_pin_obj_t pin_PB00; extern const mcu_pin_obj_t pin_PB01; extern const mcu_pin_obj_t pin_PB02; -extern const mcu_pin_obj_t pin_PF11; // 144 only -extern const mcu_pin_obj_t pin_PF12; // 144 only -extern const mcu_pin_obj_t pin_PF13; // 144 only -extern const mcu_pin_obj_t pin_PF14; // 144 only -extern const mcu_pin_obj_t pin_PF15; // 144 only -extern const mcu_pin_obj_t pin_PG00; // 144 only -extern const mcu_pin_obj_t pin_PG01; // 144 only +extern const mcu_pin_obj_t pin_PF11; // 144 only +extern const mcu_pin_obj_t pin_PF12; // 144 only +extern const mcu_pin_obj_t pin_PF13; // 144 only +extern const mcu_pin_obj_t pin_PF14; // 144 only +extern const mcu_pin_obj_t pin_PF15; // 144 only +extern const mcu_pin_obj_t pin_PG00; // 144 only +extern const mcu_pin_obj_t pin_PG01; // 144 only //pg 55 extern const mcu_pin_obj_t pin_PE07; extern const mcu_pin_obj_t pin_PE08; diff --git a/ports/stm/peripherals/stm32f7/clocks.c b/ports/stm/peripherals/stm32f7/clocks.c new file mode 100644 index 000000000..93016f682 --- /dev/null +++ b/ports/stm/peripherals/stm32f7/clocks.c @@ -0,0 +1,118 @@ + /* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f7xx_hal.h" +#include "supervisor/shared/safe_mode.h" +#include <stdbool.h> + +// F7 Series +#ifdef STM32F746xx +#include "stm32f7/stm32f746xx/clocks.h" +#endif +#ifdef STM32F767xx +#include "stm32f7/stm32f767xx/clocks.h" +#endif + +void stm32_peripherals_clocks_init(void) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + bool lse_failure = false; + + // Configure LSE Drive + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + // Set voltage scaling in accordance with system clock speed + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); + + // Set up primary PLL and HSE clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + #else + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + #endif + RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; + RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; + RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; + + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // Failure likely means a LSE issue - attempt to swap to LSI, and set to crash + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // No HSE means no USB, so just fail forever + while(1); + } + lse_failure = true; + } + + /* Activate the OverDrive to reach the 216 MHz Frequency */ + HAL_PWREx_EnableOverDrive(); + + // Configure bus clock sources and divisors + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; + RCC_ClkInitStruct.APB1CLKDivider = CPY_CLK_APB1DIV; + RCC_ClkInitStruct.APB2CLKDivider = CPY_CLK_APB2DIV; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, CPY_CLK_FLASH_LATENCY); + + // Set up non-bus peripherals + // TODO: I2S settings go here + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + #else + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + #endif + #if (CPY_CLK_USB_USES_AUDIOPLL) + // Should always result in 48M. + PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; + PeriphClkInitStruct.PLLSAI.PLLSAIR = 2; + PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; + PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4; + PeriphClkInitStruct.PLLSAIDivQ = 1; + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; + PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_CK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP; + #endif + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + if (lse_failure) { + reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT? + } +} diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c b/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c deleted file mode 100644 index 2afa2e377..000000000 --- a/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c +++ /dev/null @@ -1,96 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Lucian Copeland for Adafruit Industries - * Copyright (c) 2020 Mark Olsson <mark@markolsson.se> - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include STM32_HAL_H - -#ifndef BOARD_OSC_DIV -#define BOARD_OSC_DIV (8) -#endif -#ifndef BOARD_OSC_PLLN -#define BOARD_OSC_PLLN (432) -#endif -#ifndef BOARD_OSC_PLLQ -#define BOARD_OSC_PLLQ (9) -#endif -#ifndef BOARD_FLASH_LATENCY -#define BOARD_FLASH_LATENCY FLASH_LATENCY_7 -#endif -#ifndef BOARD_OSC_HSESTATE -#define BOARD_OSC_HSESTATE RCC_HSE_BYPASS -#endif - -void stm32_peripherals_clocks_init(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = BOARD_OSC_HSESTATE; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = BOARD_OSC_PLLN; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = BOARD_OSC_PLLQ; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Activate the OverDrive to reach the 216 MHz Frequency */ - HAL_PWREx_EnableOverDrive(); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, BOARD_FLASH_LATENCY); - - #ifdef STM32F746G_DISCO - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; - PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; - PeriphClkInitStruct.PLLSAI.PLLSAIR = 2; - PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; - PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4; - PeriphClkInitStruct.PLLSAIDivQ = 1; - PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - #endif -} diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.h b/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.h new file mode 100644 index 000000000..eb4462514 --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.h @@ -0,0 +1,63 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f7xx_hal.h" + +// Chip: STM32F746 +// Line Type: Advanced Line +// Speed: 216MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (432) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (9) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_7) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c b/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c index cee4b4f45..ca64428eb 100644 --- a/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c +++ b/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c @@ -50,4 +50,3 @@ void stm32_peripherals_gpio_init(void) { never_reset_pin_number(7,0); //PH0 OSC_IN never_reset_pin_number(7,1); //PH1 OSC_OUT } - diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c b/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c index 895ad5ec0..ae940c1a0 100644 --- a/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c +++ b/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c @@ -28,7 +28,7 @@ #include "py/mphal.h" #include "peripherals/pins.h" -// Todo: some pins do have ADCs, but the module isn't set up yet. +// Todo: some pins do have ADCs, but the module isn't set up yet. const mcu_pin_obj_t pin_PA00 = PIN(0, 0, NO_ADC); const mcu_pin_obj_t pin_PA01 = PIN(0, 1, NO_ADC); diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c deleted file mode 100644 index 18b202df5..000000000 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c +++ /dev/null @@ -1,66 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32f7xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 432; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 9; - RCC_OscInitStruct.PLL.PLLR = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Activate the OverDrive to reach the 216 MHz Frequency */ - HAL_PWREx_EnableOverDrive(); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); - -} diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.h b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.h new file mode 100644 index 000000000..187a024ad --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.h @@ -0,0 +1,63 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32f7xx_hal.h" + +// Chip: STM32F767 +// Line Type: Advanced Line +// Speed: 216MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (432) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (9) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV4) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_7) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c b/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c index d51ff53c1..1189948c7 100644 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c @@ -44,5 +44,3 @@ void stm32_peripherals_gpio_init(void) { never_reset_pin_number(0,13); //PA13 SWDIO never_reset_pin_number(0,14); //PA14 SWCLK } - - diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h index 98aa5782a..438964c3e 100644 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h @@ -54,4 +54,4 @@ TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H
\ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c index 870545f99..5c9daea98 100644 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c @@ -28,7 +28,7 @@ #include "py/mphal.h" #include "peripherals/pins.h" -// Todo: some pins do have ADCs, but the module isn't set up yet. +// Todo: some pins do have ADCs, but the module isn't set up yet. const mcu_pin_obj_t pin_PA00 = PIN(0, 0, NO_ADC); const mcu_pin_obj_t pin_PA01 = PIN(0, 1, NO_ADC); diff --git a/ports/stm/peripherals/stm32h7/clocks.c b/ports/stm/peripherals/stm32h7/clocks.c new file mode 100644 index 000000000..0e4e79f9f --- /dev/null +++ b/ports/stm/peripherals/stm32h7/clocks.c @@ -0,0 +1,123 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32h7xx_hal.h" +#include "supervisor/shared/safe_mode.h" +#include <stdbool.h> + +// H7 Series +#ifdef STM32H743xx +#include "stm32h7/stm32h743xx/clocks.h" +#endif + +void stm32_peripherals_clocks_init(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + bool lse_failure = false; + + // Set voltage scaling in accordance with system clock speed + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Configure LSE Drive + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + // Set up primary PLL and HSE clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + #else + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + #endif + #if (CPY_CLK_USB_USES_AUDIOPLL) // Not actually audio PLL in this case, swap macro? + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + #endif + RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/2000000; + RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; + RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; + RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // Failure likely means a LSE issue - attempt to swap to LSI, and set to crash + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + // No HSE means no USB, so just fail forever + while(1); + } + lse_failure = true; + } + + // Configure bus clock sources and divisors + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; + RCC_ClkInitStruct.APB1CLKDivider = CPY_CLK_APB1DIV; + RCC_ClkInitStruct.APB2CLKDivider = CPY_CLK_APB2DIV; + RCC_ClkInitStruct.APB3CLKDivider = CPY_CLK_APB3DIV; + RCC_ClkInitStruct.APB4CLKDivider = CPY_CLK_APB4DIV; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, CPY_CLK_FLASH_LATENCY); + + // Set up non-bus peripherals + // TODO: I2S settings go here + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART3 + |RCC_PERIPHCLK_USB; + #if (BOARD_HAS_LOW_SPEED_CRYSTAL) + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + #else + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + #endif + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + #if (CPY_CLK_USB_USES_AUDIOPLL) // Not actually audio PLL in this case, swap macro? + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + #else + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; + #endif + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + // Enable USB Voltage detector + HAL_PWREx_EnableUSBVoltageDetector(); + + if (lse_failure) { + reset_into_safe_mode(HARD_CRASH); //TODO: make safe mode category CLOCK_FAULT? + } +} diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c deleted file mode 100644 index 8ede6080e..000000000 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c +++ /dev/null @@ -1,83 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "stm32h7xx_hal.h" - -void stm32_peripherals_clocks_init(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The PWR block is always enabled on the H7 series- there is no clock - enable. For now, use the default VOS3 scale mode (lowest) and limit clock - frequencies to avoid potential current draw problems from bus - power when using the max clock speeds throughout the chip. */ - - /* Enable HSE Oscillator and activate PLL1 with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.CSIState = RCC_CSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 7; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; - RCC_OscInitStruct.PLL.PLLFRACN = 0; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \ - RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \ - RCC_CLOCKTYPE_D3PCLK1); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; - - /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are - device-dependent- 120 MHz for this board according to Figure 2 of - the datasheet. Dividing by half will be safe for now. */ - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - - /* 4 wait states required for 168MHz and VOS3. */ - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); - - /* Like on F4, on H7, USB's actual peripheral clock and bus clock are - separate. However, the main system PLL (PLL1) doesn't have a direct - connection to the USB peripheral clock to generate 48 MHz, so we do this - dance. This will connect PLL1's Q output to the USB peripheral clock. */ - RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; - - RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; - HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); - -} diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h new file mode 100644 index 000000000..ad241b7ef --- /dev/null +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h @@ -0,0 +1,70 @@ + +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "stm32h7xx_hal.h" + +// Chip: STM32H743 +// Line Type: Single-Core +// Speed: 480MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE0) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (480) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (2) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (20) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_HCLK_DIV2) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_APB1_DIV2) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_APB2_DIV2) +#endif +#ifndef CPY_CLK_APB3DIV +#define CPY_CLK_APB3DIV (RCC_APB3_DIV2) +#endif +#ifndef CPY_CLK_APB4DIV +#define CPY_CLK_APB4DIV (RCC_APB4_DIV2) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_4) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif +#ifndef BOARD_HSE_SOURCE +#define BOARD_HSE_SOURCE (RCC_HSE_ON) +#endif diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c b/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c index d51ff53c1..1189948c7 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c @@ -44,5 +44,3 @@ void stm32_peripherals_gpio_init(void) { never_reset_pin_number(0,13); //PA13 SWDIO never_reset_pin_number(0,14); //PA14 SWCLK } - - diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h index 4b852413b..9aa2f7366 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h @@ -52,4 +52,4 @@ const mcu_periph_obj_t mcu_uart_rx_list[26]; #define TIM_PIN_ARRAY_LEN 58 TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H
\ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c index 491fe6938..7484781c2 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c @@ -28,7 +28,7 @@ #include "py/mphal.h" #include "peripherals/pins.h" -// Todo: some pins do have ADCs, but the module isn't set up yet. +// Todo: some pins do have ADCs, but the module isn't set up yet. const mcu_pin_obj_t pin_PA00 = PIN(0, 0, NO_ADC); const mcu_pin_obj_t pin_PA01 = PIN(0, 1, NO_ADC); diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 060eadecb..d37a54f60 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -321,4 +321,3 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, void supervisor_flash_release_cache(void) { } - diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index 9b62fa2eb..25504ddec 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -147,9 +147,10 @@ __attribute__((used, naked)) void Reset_Handler(void) { __enable_irq(); main(); } - #endif //end H7 specific code +// Low power clock variables +static volatile uint32_t systick_ms; static RTC_HandleTypeDef _hrtc; #if BOARD_HAS_LOW_SPEED_CRYSTAL @@ -159,7 +160,7 @@ static uint32_t rtc_clock_frequency = LSI_VALUE; #endif safe_mode_t port_init(void) { - HAL_Init(); + HAL_Init(); // Turns on SysTick __HAL_RCC_SYSCFG_CLK_ENABLE(); #if (CPY_STM32F4) @@ -169,64 +170,7 @@ safe_mode_t port_init(void) { stm32_peripherals_clocks_init(); stm32_peripherals_gpio_init(); - HAL_PWR_EnableBkUpAccess(); - - // TODO: move all of this to clocks.c - #if BOARD_HAS_LOW_SPEED_CRYSTAL - uint32_t tickstart = HAL_GetTick(); - - // H7/F7 untested with LSE, so autofail them until above move is done - #if (CPY_STM32F4) - bool lse_setupsuccess = true; - #else - bool lse_setupsuccess = false; - #endif - - // Update LSE configuration in Backup Domain control register - // Requires to enable write access to Backup Domain of necessary - // TODO: should be using the HAL OSC initializer, otherwise we'll need - // preprocessor defines for every register to account for F7/H7 - #if (CPY_STM32F4) - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - // Enable write access to Backup domain - SET_BIT(PWR->CR, PWR_CR_DBP); - // Wait for Backup domain Write protection disable - tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - lse_setupsuccess = false; - } - } - } - #endif - - __HAL_RCC_LSE_CONFIG(RCC_LSE_ON); - tickstart = HAL_GetTick(); - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if((HAL_GetTick() - tickstart ) > LSE_STARTUP_TIMEOUT) - { - lse_setupsuccess = false; - __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - __HAL_RCC_LSI_ENABLE(); - rtc_clock_frequency = LSI_VALUE; - break; - } - } - - if (lse_setupsuccess) { - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - } else { - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - } - - #else - __HAL_RCC_LSI_ENABLE(); - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - #endif - + // RTC oscillator selection is handled in peripherals/<family>/<line>/clocks.c __HAL_RCC_RTC_ENABLE(); _hrtc.Instance = RTC; _hrtc.Init.HourFormat = RTC_HOURFORMAT_24; @@ -237,16 +181,40 @@ safe_mode_t port_init(void) { _hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; HAL_RTC_Init(&_hrtc); - HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + // Turn off SysTick + SysTick->CTRL = 0; + return NO_SAFE_MODE; } +void HAL_Delay(uint32_t delay_ms) { + if (SysTick->CTRL != 0) { + // SysTick is on, so use it + uint32_t tickstart = systick_ms; + while (systick_ms - tickstart < delay_ms) { + } + } else { + mp_hal_delay_ms(delay_ms); + } +} + +uint32_t HAL_GetTick() { + if (SysTick->CTRL != 0) { + return systick_ms; + } else { + uint8_t subticks; + uint32_t result = (uint32_t)port_get_raw_ticks(&subticks); + return result; + } +} + + void SysTick_Handler(void) { + systick_ms += 1; // Read the CTRL register to clear the SysTick interrupt. SysTick->CTRL; - HAL_IncTick(); } void reset_port(void) { @@ -453,4 +421,3 @@ void _init(void) { } - diff --git a/ports/stm/supervisor/serial.c b/ports/stm/supervisor/serial.c index ce1366000..3a058ed2e 100644 --- a/ports/stm/supervisor/serial.c +++ b/ports/stm/supervisor/serial.c @@ -72,4 +72,3 @@ void serial_write_substring(const char *text, uint32_t len) { } HAL_UART_Transmit(&huart2, (uint8_t*)text, len, 5000); } - diff --git a/ports/stm/tools/examples/nucleo_h743.csv b/ports/stm/tools/examples/nucleo_h743.csv index 2481415b3..d3647ca42 100644 --- a/ports/stm/tools/examples/nucleo_h743.csv +++ b/ports/stm/tools/examples/nucleo_h743.csv @@ -127,4 +127,4 @@ ETH_RMII_RXD0,PC4 ETH_RMII_RXD1,PC5 ETH_RMII_TX_EN,PG11 ETH_RMII_TXD0,PG13 -ETH_RMII_TXD1,PB13
\ No newline at end of file +ETH_RMII_TXD1,PB13 diff --git a/ports/stm/tools/parse_af_csv.py b/ports/stm/tools/parse_af_csv.py index b257a450c..4e9725260 100644 --- a/ports/stm/tools/parse_af_csv.py +++ b/ports/stm/tools/parse_af_csv.py @@ -28,8 +28,8 @@ import sys # Use: parse_af_csf.py Filename.csv -pins-only # Designed for use with .csv files from Micropython, or in identical format # created via Datasheet peripheral tables with a Sheets program. -# -# See examples/stm32f405.csv for example formatting. +# +# See examples/stm32f405.csv for example formatting. # Most peripherals (SPI, I2C) output 3 values: # peripheral index, alt function, pin string @@ -52,7 +52,7 @@ def evaluate_tim(inper, inlist, altfn, pin): if inper[:3] == "TIM" and inper[5:7] == "CH" and inper[-1:] != 'N': inlist.append([inper[3:4],altfn,inper[-1:],pin]) - + # Open target file with open(sys.argv[1]) as csv_file: csv_reader = csv.reader(csv_file, delimiter=',') @@ -107,7 +107,7 @@ with open(sys.argv[1]) as csv_file: print(" PERIPH(" + row[0] + ", " + str(row[1]) + ", &pin_" + row[2] + "),") print("};") - # Timer special case: + # Timer special case: print("const mcu_tim_pin_obj_t mcu_tim_pin_list[" + str(len(outlist[-1])) + "] = {") for row in outlist[-1]: print(" TIM(" + row[0] + ", " + str(row[1]) + ", " + str(row[2]) + ", &pin_" + row[3] + "),") diff --git a/ports/stm/tools/parse_pins_csv.py b/ports/stm/tools/parse_pins_csv.py index b69b4791b..4ab3fc25c 100644 --- a/ports/stm/tools/parse_pins_csv.py +++ b/ports/stm/tools/parse_pins_csv.py @@ -25,12 +25,12 @@ import csv import sys -# Use: parse_pins_csv.py Filename.csv +# Use: parse_pins_csv.py Filename.csv # Designed for use with .csv files from Micropython, or in identical format # created via Datasheet peripheral tables with a Sheets program. -# -# See examples/nucleo_h743.csv for example formatting. - +# +# See examples/nucleo_h743.csv for example formatting. + # Open target file with open(sys.argv[1]) as csv_file: csv_reader = csv.reader(csv_file, delimiter=',') |