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authorScott Shawcroft <scott@adafruit.com>2020-05-12 11:56:33 -0700
committerGitHub <noreply@github.com>2020-05-12 11:56:33 -0700
commitf7303e6bd0e3fbfb8c781bab024f4f689268b0b6 (patch)
tree418b21bdf8d40cfd3ab31cb7a1633397216ede28 /supervisor/shared/external_flash/external_flash.c
parenta1091bbfbbb1b35c2e685fa874cc2caf7020740b (diff)
parente6df8e0989478d61e9c62033cf59b77afa3210e6 (diff)
Merge pull request #2754 from maholli/non-standard-nvm
Add non-standard nvm to QSPI for external flash support
Diffstat (limited to 'supervisor/shared/external_flash/external_flash.c')
-rw-r--r--supervisor/shared/external_flash/external_flash.c86
1 files changed, 56 insertions, 30 deletions
diff --git a/supervisor/shared/external_flash/external_flash.c b/supervisor/shared/external_flash/external_flash.c
index bfc434664..5bde7fd48 100644
--- a/supervisor/shared/external_flash/external_flash.c
+++ b/supervisor/shared/external_flash/external_flash.c
@@ -27,7 +27,6 @@
#include <stdint.h>
#include <string.h>
-
#include "supervisor/flash.h"
#include "supervisor/spi_flash_api.h"
#include "supervisor/shared/external_flash/common_commands.h"
@@ -58,9 +57,13 @@ static supervisor_allocation* supervisor_cache = NULL;
// Wait until both the write enable and write in progress bits have cleared.
static bool wait_for_flash_ready(void) {
- uint8_t read_status_response[1] = {0x00};
bool ok = true;
// Both the write enable and write in progress bits should be low.
+ if (flash_device->no_ready_bit){
+ // For NVM without a ready bit in status register
+ return ok;
+ }
+ uint8_t read_status_response[1] = {0x00};
do {
ok = spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1);
} while (ok && (read_status_response[0] & 0x3) != 0);
@@ -92,15 +95,18 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len
}
// Don't bother writing if the data is all 1s. Thats equivalent to the flash
// state after an erase.
- bool all_ones = true;
- for (uint16_t i = 0; i < data_length; i++) {
- if (data[i] != 0xff) {
- all_ones = false;
- break;
+ if (!flash_device->no_erase_cmd){
+ // Only do this if the device has an erase command
+ bool all_ones = true;
+ for (uint16_t i = 0; i < data_length; i++) {
+ if (data[i] != 0xff) {
+ all_ones = false;
+ break;
+ }
+ }
+ if (all_ones) {
+ return true;
}
- }
- if (all_ones) {
- return true;
}
for (uint32_t bytes_written = 0;
@@ -121,6 +127,10 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len
static bool page_erased(uint32_t sector_address) {
// Check the first few bytes to catch the common case where there is data
// without using a bunch of memory.
+ if (flash_device->no_erase_cmd){
+ // skip this if device doesn't have an erase command.
+ return true;
+ }
uint8_t short_buffer[4];
if (read_flash(sector_address, short_buffer, 4)) {
for (uint16_t i = 0; i < 4; i++) {
@@ -151,10 +161,16 @@ static bool page_erased(uint32_t sector_address) {
static bool erase_sector(uint32_t sector_address) {
// Before we erase the sector we need to wait for any writes to finish and
// and then enable the write again.
+ if (flash_device->no_erase_cmd){
+ // skip this if device doesn't have an erase command.
+ return true;
+ }
if (!wait_for_flash_ready() || !write_enable()) {
return false;
}
-
+ if (flash_device->no_erase_cmd) {
+ return true;
+ }
spi_flash_sector_command(CMD_SECTOR_ERASE, sector_address);
return true;
}
@@ -192,25 +208,33 @@ void supervisor_flash_init(void) {
spi_flash_init();
+#ifdef EXTERNAL_FLASH_NO_JEDEC
+ // For NVM that don't have JEDEC response
+ spi_flash_command(CMD_WAKE);
+ for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
+ const external_flash_device* possible_device = &possible_devices[i];
+ flash_device = possible_device;
+ break;
+ }
+#else
// The response will be 0xff if the flash needs more time to start up.
uint8_t jedec_id_response[3] = {0xff, 0xff, 0xff};
while (jedec_id_response[0] == 0xff) {
spi_flash_read_command(CMD_READ_JEDEC_ID, jedec_id_response, 3);
}
-
- for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
- const external_flash_device* possible_device = &possible_devices[i];
- if (jedec_id_response[0] == possible_device->manufacturer_id &&
- jedec_id_response[1] == possible_device->memory_type &&
- jedec_id_response[2] == possible_device->capacity) {
- flash_device = possible_device;
- break;
+ for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
+ const external_flash_device* possible_device = &possible_devices[i];
+ if (jedec_id_response[0] == possible_device->manufacturer_id &&
+ jedec_id_response[1] == possible_device->memory_type &&
+ jedec_id_response[2] == possible_device->capacity) {
+ flash_device = possible_device;
+ break;
+ }
+ }
+#endif
+ if (flash_device == NULL) {
+ return;
}
- }
-
- if (flash_device == NULL) {
- return;
- }
// We don't know what state the flash is in so wait for any remaining writes and then reset.
uint8_t read_status_response[1] = {0x00};
@@ -219,14 +243,16 @@ void supervisor_flash_init(void) {
spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1);
} while ((read_status_response[0] & 0x1) != 0);
if (!flash_device->single_status_byte) {
- // The suspended write/erase bit should be low.
- do {
- spi_flash_read_command(CMD_READ_STATUS2, read_status_response, 1);
- } while ((read_status_response[0] & 0x80) != 0);
+ // The suspended write/erase bit should be low.
+ do {
+ spi_flash_read_command(CMD_READ_STATUS2, read_status_response, 1);
+ } while ((read_status_response[0] & 0x80) != 0);
}
- spi_flash_command(CMD_ENABLE_RESET);
- spi_flash_command(CMD_RESET);
+ if (!(flash_device->no_reset_cmd)){
+ spi_flash_command(CMD_ENABLE_RESET);
+ spi_flash_command(CMD_RESET);
+ }
// Wait 30us for the reset
common_hal_mcu_delay_us(30);