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authorDiego Elio Pettenò <flameeyes@flameeyes.com>2020-05-30 10:44:13 +0100
committerDiego Elio Pettenò <flameeyes@flameeyes.com>2020-06-03 10:56:35 +0100
commitdd5d7c86d22807c021dd1711eb7dd3daebc5cfcf (patch)
treedde417af2cae8cb1797582d6489eab9cb9caeddf /tests/wipy/uart.py
parent60df6170cc5d0e495fde9613c05c55b64189b425 (diff)
Fix up end of file and trailing whitespace.
This can be enforced by pre-commit, but correct it separately to make it easier to review.
Diffstat (limited to 'tests/wipy/uart.py')
-rw-r--r--tests/wipy/uart.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/wipy/uart.py b/tests/wipy/uart.py
index 8e794015d..d8b405f77 100644
--- a/tests/wipy/uart.py
+++ b/tests/wipy/uart.py
@@ -1,5 +1,5 @@
'''
-UART test for the CC3200 based boards.
+UART test for the CC3200 based boards.
UART0 and UART1 must be connected together for this test to pass.
'''
@@ -58,7 +58,7 @@ print(uart0.read() == None)
uart0.write(b'123')
buf = bytearray(3)
-print(uart1.readinto(buf, 1) == 1)
+print(uart1.readinto(buf, 1) == 1)
print(buf)
print(uart1.readinto(buf) == 2)
print(buf)
@@ -145,7 +145,7 @@ except Exception:
try:
UART(2, 9600)
except Exception:
- print('Exception')
+ print('Exception')
for uart_id in uart_id_range:
uart = UART(uart_id, 1000000)