diff options
6 files changed, 11 insertions, 3 deletions
diff --git a/ports/stm32f4/boards/feather_stm32f405_express/mpconfigboard.h b/ports/stm32f4/boards/feather_stm32f405_express/mpconfigboard.h index ad9bba7b0..3ea469383 100644 --- a/ports/stm32f4/boards/feather_stm32f405_express/mpconfigboard.h +++ b/ports/stm32f4/boards/feather_stm32f405_express/mpconfigboard.h @@ -34,6 +34,8 @@ #define MICROPY_HW_NEOPIXEL (&pin_PC00) +#define BOARD_OSC_DIV 12 + // On-board flash #define SPI_FLASH_MOSI_PIN (&pin_PB05) #define SPI_FLASH_MISO_PIN (&pin_PB04) diff --git a/ports/stm32f4/boards/pyboard_v11/mpconfigboard.h b/ports/stm32f4/boards/pyboard_v11/mpconfigboard.h index 7093442d0..2da2c6da9 100644 --- a/ports/stm32f4/boards/pyboard_v11/mpconfigboard.h +++ b/ports/stm32f4/boards/pyboard_v11/mpconfigboard.h @@ -32,6 +32,7 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) +#define BOARD_OSC_DIV 12 #define DEFAULT_I2C_BUS_SCL (&pin_PB06) #define DEFAULT_I2C_BUS_SDA (&pin_PB07) diff --git a/ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.h b/ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.h index 3ab9a5585..b6d28cb12 100644 --- a/ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.h +++ b/ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.h @@ -32,5 +32,7 @@ #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x4000) +#define BOARD_OSC_DIV 8 + #define DEFAULT_I2C_BUS_SCL (&pin_PB10) #define DEFAULT_I2C_BUS_SDA (&pin_PB09) diff --git a/ports/stm32f4/peripherals/stm32f4/stm32f401xe/clocks.c b/ports/stm32f4/peripherals/stm32f4/stm32f401xe/clocks.c index 53af29b3b..53810af26 100644 --- a/ports/stm32f4/peripherals/stm32f4/stm32f401xe/clocks.c +++ b/ports/stm32f4/peripherals/stm32f4/stm32f401xe/clocks.c @@ -25,6 +25,7 @@ * THE SOFTWARE. */ #include "stm32f4xx_hal.h" +#include "py/mpconfig.h" void stm32f4_peripherals_clocks_init(void) { //System clock init @@ -44,7 +45,7 @@ void stm32f4_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; RCC_OscInitStruct.PLL.PLLN = 336; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; RCC_OscInitStruct.PLL.PLLQ = 7; diff --git a/ports/stm32f4/peripherals/stm32f4/stm32f405xx/clocks.c b/ports/stm32f4/peripherals/stm32f4/stm32f405xx/clocks.c index c259f54fa..2afca64e8 100644 --- a/ports/stm32f4/peripherals/stm32f4/stm32f405xx/clocks.c +++ b/ports/stm32f4/peripherals/stm32f4/stm32f405xx/clocks.c @@ -25,6 +25,7 @@ * THE SOFTWARE. */ #include "stm32f4xx_hal.h" +#include "py/mpconfig.h" void stm32f4_peripherals_clocks_init(void) { //TODO: All parameters must be moved to board level, due to relationship with HSE Osc. @@ -46,7 +47,7 @@ void stm32f4_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; RCC_OscInitStruct.PLL.PLLN = 336; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 7; diff --git a/ports/stm32f4/peripherals/stm32f4/stm32f412zx/clocks.c b/ports/stm32f4/peripherals/stm32f4/stm32f412zx/clocks.c index 107056550..b208f9dfb 100644 --- a/ports/stm32f4/peripherals/stm32f4/stm32f412zx/clocks.c +++ b/ports/stm32f4/peripherals/stm32f4/stm32f412zx/clocks.c @@ -25,6 +25,7 @@ * THE SOFTWARE. */ #include "stm32f4xx_hal.h" +#include "py/mpconfig.h" void stm32f4_peripherals_clocks_init(void) { //System clock init @@ -46,7 +47,7 @@ void stm32f4_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; RCC_OscInitStruct.PLL.PLLN = 200; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 7; |