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-rw-r--r--ports/stm/boards/STM32F401xd_fs.ld2
-rw-r--r--ports/stm/boards/STM32F401xe_boot.ld2
-rw-r--r--ports/stm/boards/STM32F401xe_fs.ld2
-rw-r--r--ports/stm/boards/STM32F405_boot.ld2
-rw-r--r--ports/stm/boards/STM32F405_default.ld2
-rw-r--r--ports/stm/boards/STM32F405_fs.ld2
-rw-r--r--ports/stm/boards/STM32F407_fs.ld2
-rw-r--r--ports/stm/boards/STM32F411_fs.ld2
-rw-r--r--ports/stm/boards/STM32F411_nvm.ld2
-rw-r--r--ports/stm/boards/STM32F412_fs.ld2
-rw-r--r--ports/stm/boards/STM32F746xG_fs.ld2
-rw-r--r--ports/stm/boards/STM32F767_fs.ld2
-rw-r--r--ports/stm/boards/STM32H743_fs.ld2
-rw-r--r--ports/stm/supervisor/port.c74
14 files changed, 73 insertions, 27 deletions
diff --git a/ports/stm/boards/STM32F401xd_fs.ld b/ports/stm/boards/STM32F401xd_fs.ld
index 3086c2c6b..69bae46cb 100644
--- a/ports/stm/boards/STM32F401xd_fs.ld
+++ b/ports/stm/boards/STM32F401xd_fs.ld
@@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F401xe_boot.ld b/ports/stm/boards/STM32F401xe_boot.ld
index 040947694..37827c330 100644
--- a/ports/stm/boards/STM32F401xe_boot.ld
+++ b/ports/stm/boards/STM32F401xe_boot.ld
@@ -12,7 +12,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F401xe_fs.ld b/ports/stm/boards/STM32F401xe_fs.ld
index b55bc4bb4..20247930c 100644
--- a/ports/stm/boards/STM32F401xe_fs.ld
+++ b/ports/stm/boards/STM32F401xe_fs.ld
@@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F405_boot.ld b/ports/stm/boards/STM32F405_boot.ld
index 906f56e0d..5768d1a01 100644
--- a/ports/stm/boards/STM32F405_boot.ld
+++ b/ports/stm/boards/STM32F405_boot.ld
@@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define the top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F405_default.ld b/ports/stm/boards/STM32F405_default.ld
index 0aafdbcac..4c11fd7cf 100644
--- a/ports/stm/boards/STM32F405_default.ld
+++ b/ports/stm/boards/STM32F405_default.ld
@@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F405_fs.ld b/ports/stm/boards/STM32F405_fs.ld
index bff312660..e6c66127f 100644
--- a/ports/stm/boards/STM32F405_fs.ld
+++ b/ports/stm/boards/STM32F405_fs.ld
@@ -14,7 +14,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F407_fs.ld b/ports/stm/boards/STM32F407_fs.ld
index 5330b4116..f06c19d99 100644
--- a/ports/stm/boards/STM32F407_fs.ld
+++ b/ports/stm/boards/STM32F407_fs.ld
@@ -14,7 +14,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F411_fs.ld b/ports/stm/boards/STM32F411_fs.ld
index 82c7aea06..1b45f235f 100644
--- a/ports/stm/boards/STM32F411_fs.ld
+++ b/ports/stm/boards/STM32F411_fs.ld
@@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F411_nvm.ld b/ports/stm/boards/STM32F411_nvm.ld
index 897b99631..5ac3e52a6 100644
--- a/ports/stm/boards/STM32F411_nvm.ld
+++ b/ports/stm/boards/STM32F411_nvm.ld
@@ -14,7 +14,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define the top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F412_fs.ld b/ports/stm/boards/STM32F412_fs.ld
index afd51c6b1..8837bd87d 100644
--- a/ports/stm/boards/STM32F412_fs.ld
+++ b/ports/stm/boards/STM32F412_fs.ld
@@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F746xG_fs.ld b/ports/stm/boards/STM32F746xG_fs.ld
index f1bd3d5dc..be10a1429 100644
--- a/ports/stm/boards/STM32F746xG_fs.ld
+++ b/ports/stm/boards/STM32F746xG_fs.ld
@@ -38,7 +38,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32F767_fs.ld b/ports/stm/boards/STM32F767_fs.ld
index 40e67829b..25322b0b6 100644
--- a/ports/stm/boards/STM32F767_fs.ld
+++ b/ports/stm/boards/STM32F767_fs.ld
@@ -13,7 +13,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
diff --git a/ports/stm/boards/STM32H743_fs.ld b/ports/stm/boards/STM32H743_fs.ld
index 686f93ea3..b6c3d5b62 100644
--- a/ports/stm/boards/STM32H743_fs.ld
+++ b/ports/stm/boards/STM32H743_fs.ld
@@ -22,7 +22,7 @@ MEMORY
}
/* produce a link error if there is not this amount of RAM for these sections */
-_minimum_stack_size = 2K;
+_minimum_stack_size = 24K; /*TODO: this can probably be bigger, but how big?*/
_minimum_heap_size = 16K;
/* brainless copy paste for stack code. Results in ambiguous hard crash */
diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c
index 779348c02..23ba7d874 100644
--- a/ports/stm/supervisor/port.c
+++ b/ports/stm/supervisor/port.c
@@ -49,7 +49,7 @@
#include STM32_HAL_H
//only enable the Reset Handler overwrite for the H7 for now
-#if defined(STM32H7)
+#if (CPY_STM32H7)
// Device memories must be accessed in order.
#define DEVICE 2
@@ -153,16 +153,16 @@ __attribute__((used, naked)) void Reset_Handler(void) {
static RTC_HandleTypeDef _hrtc;
#if BOARD_HAS_LOW_SPEED_CRYSTAL
-#define RTC_CLOCK_FREQUENCY LSE_VALUE
+static uint32_t rtc_clock_frequency = LSE_VALUE;
#else
-#define RTC_CLOCK_FREQUENCY LSI_VALUE
+static uint32_t rtc_clock_frequency = LSI_VALUE;
#endif
safe_mode_t port_init(void) {
HAL_Init();
__HAL_RCC_SYSCFG_CLK_ENABLE();
- #if defined(STM32F4)
+ #if (CPY_STM32F4)
__HAL_RCC_PWR_CLK_ENABLE();
#endif
@@ -170,24 +170,70 @@ safe_mode_t port_init(void) {
stm32_peripherals_gpio_init();
HAL_PWR_EnableBkUpAccess();
+
+ // TODO: move all of this to clocks.c
#if BOARD_HAS_LOW_SPEED_CRYSTAL
- __HAL_RCC_LSE_CONFIG(RCC_LSE_ON);
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {}
+ uint32_t tickstart = HAL_GetTick();
+
+ // H7/F7 untested with LSE, so autofail them until above move is done
+ #if (CPY_STM32F4)
+ bool lse_setupsuccess = true;
#else
- __HAL_RCC_LSI_ENABLE();
+ bool lse_setupsuccess = false;
#endif
- #if BOARD_HAS_LOW_SPEED_CRYSTAL
- __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+
+ // Update LSE configuration in Backup Domain control register
+ // Requires to enable write access to Backup Domain of necessary
+ // TODO: should be using the HAL OSC initializer, otherwise we'll need
+ // preprocessor defines for every register to account for F7/H7
+ #if (CPY_STM32F4)
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ // Enable write access to Backup domain
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+ // Wait for Backup domain Write protection disable
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ lse_setupsuccess = false;
+ }
+ }
+ }
+ #endif
+
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_ON);
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {
+ if((HAL_GetTick() - tickstart ) > LSE_STARTUP_TIMEOUT)
+ {
+ lse_setupsuccess = false;
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+ __HAL_RCC_LSI_ENABLE();
+ rtc_clock_frequency = LSI_VALUE;
+ break;
+ }
+ }
+
+ if (lse_setupsuccess) {
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+ } else {
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+ }
+
#else
+ __HAL_RCC_LSI_ENABLE();
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
#endif
+
__HAL_RCC_RTC_ENABLE();
_hrtc.Instance = RTC;
_hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
- // Divide async as little as possible so that we have RTC_CLOCK_FREQUENCY count in subseconds.
+ // Divide async as little as possible so that we have rtc_clock_frequency count in subseconds.
// This ensures our timing > 1 second is correct.
_hrtc.Init.AsynchPrediv = 0x0;
- _hrtc.Init.SynchPrediv = RTC_CLOCK_FREQUENCY - 1;
+ _hrtc.Init.SynchPrediv = rtc_clock_frequency - 1;
_hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
HAL_RTC_Init(&_hrtc);
@@ -293,7 +339,7 @@ volatile uint32_t cached_date = 0;
volatile uint32_t seconds_to_minute = 0;
volatile uint32_t cached_hours_minutes = 0;
uint64_t port_get_raw_ticks(uint8_t* subticks) {
- uint32_t subseconds = RTC_CLOCK_FREQUENCY - (uint32_t)(RTC->SSR);
+ uint32_t subseconds = rtc_clock_frequency - (uint32_t)(RTC->SSR);
uint32_t time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
uint32_t date = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
if (date != cached_date) {
@@ -341,7 +387,7 @@ void RTC_Alarm_IRQHandler(void) {
// Enable 1/1024 second tick.
void port_enable_tick(void) {
- HAL_RTCEx_SetWakeUpTimer_IT(&_hrtc, RTC_CLOCK_FREQUENCY / 1024 / 2, RTC_WAKEUPCLOCK_RTCCLK_DIV2);
+ HAL_RTCEx_SetWakeUpTimer_IT(&_hrtc, rtc_clock_frequency / 1024 / 2, RTC_WAKEUPCLOCK_RTCCLK_DIV2);
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 1, 0U);
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
}
@@ -372,7 +418,7 @@ void port_interrupt_after_ticks(uint32_t ticks) {
alarm.AlarmMask = RTC_ALARMMASK_ALL;
}
- alarm.AlarmTime.SubSeconds = RTC_CLOCK_FREQUENCY -
+ alarm.AlarmTime.SubSeconds = rtc_clock_frequency -
((raw_ticks % 1024) * 32);
alarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
alarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_SET;
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-08 08:42:20 +0000