diff options
Diffstat (limited to 'supervisor/shared/external_flash/devices.h')
| -rw-r--r-- | supervisor/shared/external_flash/devices.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/supervisor/shared/external_flash/devices.h b/supervisor/shared/external_flash/devices.h index 57c52e2ea..f99fad4e7 100644 --- a/supervisor/shared/external_flash/devices.h +++ b/supervisor/shared/external_flash/devices.h @@ -64,6 +64,15 @@ typedef struct { // True when the status register is a single byte. This implies the Quad Enable bit is in the // first byte and the Read Status Register 2 command (0x35) is unsupported. bool single_status_byte: 1; + + // Does not support using a ready bit within the status register + bool no_ready_bit: 1; + + // Does not support the erase command (0x20) + bool no_erase_cmd: 1; + + // Device does not have a reset command + bool no_reset_cmd: 1; } external_flash_device; // Settings for the Adesto Tech AT25DF081A 1MiB SPI flash. It's on the SAMD21 @@ -426,6 +435,27 @@ typedef struct { .single_status_byte = false, \ } +// Settings for the Everspin MR20H40 / MR25H40 magnetic non-volatile RAM +// Datasheet: https://www.everspin.com/supportdocs/MR25H40CDFR +#define MR2xH40 {\ + .total_size = (1 << 22), /* 4 MiB */ \ + .start_up_time_us = 10000, \ + .manufacturer_id = 0xef, /*no JDEC*/ \ + .memory_type = 0x40, /*no JDEC*/ \ + .capacity = 0x14, /*no JDEC*/ \ + .max_clock_speed_mhz = 10, \ + .quad_enable_bit_mask = 0x00, \ + .has_sector_protection = false, \ + .supports_fast_read = false, \ + .supports_qspi = false, \ + .supports_qspi_writes = false, \ + .write_status_register_split = false, \ + .single_status_byte = true, \ + .no_ready_bit = true, \ + .no_erase_cmd = true, \ + .no_reset_cmd = true, \ +} + // Settings for the Macronix MX25L1606 2MiB SPI flash. // Datasheet: #define MX25L1606 {\ |