From 67d8f108bb94bd734e218f13201fb31d64a66dd4 Mon Sep 17 00:00:00 2001
From: Jeff Epler <jepler@gmail.com>
Date: Fri, 18 Sep 2020 10:56:52 -0500
Subject: Add CAN to SAM E51 clock config

---
 .../asf4_conf/same51/peripheral_clk_config.h       | 82 ++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h
index 59fe8730e..51173f6d3 100644
--- a/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h
+++ b/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h
@@ -1165,6 +1165,88 @@
 #define CONF_SDHC1_SLOW_FREQUENCY 12000000
 #endif
 
+// <h> CAN Clock Settings
+// <y> CAN Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CAN.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_CAN0_SRC
+#define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CAN FREQUENCY
+ * \brief CAN's Clock frequency
+ */
+#ifndef CONF_CAN0_FREQUENCY
+#define CONF_CAN0_FREQUENCY 120000000
+#endif
+
+// <h> CAN Clock Settings
+// <y> CAN Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CAN.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_CAN1_SRC
+#define CONF_GCLK_CAN1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CAN FREQUENCY
+ * \brief CAN's Clock frequency
+ */
+#ifndef CONF_CAN1_FREQUENCY
+#define CONF_CAN1_FREQUENCY 120000000
+#endif
+
 // <<< end of configuration section >>>
 
 #endif // PERIPHERAL_CLK_CONFIG_H
-- 
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