From 8a93a81a2628a644b8bcc656b96881b6de35fa98 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Sun, 15 Mar 2020 22:31:36 -0700
Subject: Chip specific code.

---
 ports/stm/supervisor/usb.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'ports/stm/supervisor/usb.c')

diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 358c2de5b..86a51d750 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -59,13 +59,13 @@ STATIC void init_usb_vbus_sense(void) {
 }
 
 void init_usb_hardware(void) {
-    //TODO: if future chips overload this with options, move to peripherals management. 
+    //TODO: if future chips overload this with options, move to peripherals management.
 
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     /**USB_OTG_FS GPIO Configuration
     PA10     ------> USB_OTG_FS_ID
     PA11     ------> USB_OTG_FS_DM
-    PA12     ------> USB_OTG_FS_DP 
+    PA12     ------> USB_OTG_FS_DP
     */
     __HAL_RCC_GPIOA_CLK_ENABLE();
 
@@ -80,11 +80,13 @@ void init_usb_hardware(void) {
     never_reset_pin_number(0, 12);
 
     /* Configure VBUS Pin */
+#if (BOARD_NO_VBUS_SENSE)
     GPIO_InitStruct.Pin = GPIO_PIN_9;
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
     never_reset_pin_number(0, 9);
+#endif
 
     /* This for ID line debug */
     GPIO_InitStruct.Pin = GPIO_PIN_10;
@@ -103,7 +105,7 @@ void init_usb_hardware(void) {
     HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
     never_reset_pin_number(0, 8);
 #endif
-    
+
     /* Peripheral clock enable */
     __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-- 
cgit v1.2.3


From 07549b7fd955cb1368a58d12e82e005865305f26 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Tue, 17 Mar 2020 00:27:04 -0700
Subject: Bring back trimmed spaces.

---
 ports/stm/peripherals/stm32f4/periph.h           |  40 +--
 ports/stm/peripherals/stm32f4/pins.h             |  10 +-
 ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c |   3 +-
 ports/stm/supervisor/usb.c                       |   8 +-
 ports/stm/system_stm32f4xx.c                     | 304 +++++++++++------------
 5 files changed, 182 insertions(+), 183 deletions(-)

(limited to 'ports/stm/supervisor/usb.c')

diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h
index 663df4bed..1dfa7ac45 100644
--- a/ports/stm/peripherals/stm32f4/periph.h
+++ b/ports/stm/peripherals/stm32f4/periph.h
@@ -33,9 +33,9 @@
 #include "stm32f4xx_hal.h"
 #include "stm32f4/pins.h"
 
-// I2C
+// I2C 
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them.
+// find a compelling reason to store more unique data in them. 
 
 typedef struct {
     uint8_t i2c_index:4; // Index of the I2C unit (1 to 3)
@@ -44,8 +44,8 @@ typedef struct {
 } mcu_i2c_sda_obj_t;
 
 typedef struct {
-    uint8_t i2c_index:4;
-    uint8_t altfn_index:4;
+    uint8_t i2c_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_i2c_scl_obj_t;
 
@@ -64,9 +64,9 @@ typedef struct {
     .pin = scl_pin, \
 }
 
-// SPI
+// SPI 
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them.
+// find a compelling reason to store more unique data in them. 
 
 typedef struct {
     uint8_t spi_index:4; //Up to 6 SPI units
@@ -75,20 +75,20 @@ typedef struct {
 } mcu_spi_sck_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4;
-    uint8_t altfn_index:4;
+    uint8_t spi_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_spi_mosi_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4;
-    uint8_t altfn_index:4;
+    uint8_t spi_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_spi_miso_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4;
-    uint8_t altfn_index:4;
+    uint8_t spi_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_spi_nss_obj_t;
 
@@ -101,17 +101,17 @@ typedef struct {
 
 // UART
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them.
+// find a compelling reason to store more unique data in them. 
 
 typedef struct {
-    uint8_t uart_index:4;
-    uint8_t altfn_index:4;
+    uint8_t uart_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_uart_tx_obj_t;
 
 typedef struct {
-    uint8_t uart_index:4;
-    uint8_t altfn_index:4;
+    uint8_t uart_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_uart_rx_obj_t;
 
@@ -124,8 +124,8 @@ typedef struct {
 
 //Timers
 typedef struct {
-    uint8_t tim_index:4;
-    uint8_t altfn_index:4;
+    uint8_t tim_index:4; 
+    uint8_t altfn_index:4; 
     uint8_t channel_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_tim_pin_obj_t;
@@ -184,4 +184,4 @@ typedef struct {
 #include "stm32f407xx/periph.h"
 #endif
 
-#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
+#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
\ No newline at end of file
diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h
index 7e8baf89d..ce2980969 100644
--- a/ports/stm/peripherals/stm32f4/pins.h
+++ b/ports/stm/peripherals/stm32f4/pins.h
@@ -40,7 +40,7 @@ typedef struct {
     mp_obj_base_t base;
     uint8_t port:4;
     uint8_t number:4;
-    uint8_t adc_unit:3;
+    uint8_t adc_unit:3; 
     uint8_t adc_channel:5;
 } mcu_pin_obj_t;
 
@@ -51,8 +51,8 @@ typedef struct {
 #define ADC_3   4
 
 //STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin,
-//but all 3 ADCs will share the same input number per pin.
-//F4 family has 3 ADC max, 24 channels max.
+//but all 3 ADCs will share the same input number per pin. 
+//F4 family has 3 ADC max, 24 channels max. 
 #define ADC_INPUT(mask, number) \
     .adc_unit = mask, \
     .adc_channel = number,
@@ -64,7 +64,7 @@ typedef struct {
 extern const mp_obj_type_t mcu_pin_type;
 
 // STM32 can have up to 9 ports, each restricted to 16 pins
-// We split the pin/port evenly, in contrast to nrf.
+// We split the pin/port evenly, in contrast to nrf. 
 #define PIN(p_port, p_number, p_adc)       \
 { \
     { &mcu_pin_type }, \
@@ -96,4 +96,4 @@ extern const mp_obj_type_t mcu_pin_type;
 #include "stm32f407xx/pins.h"
 #endif
 
-#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
+#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
\ No newline at end of file
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
index fde10be3c..68a75f463 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
@@ -220,7 +220,7 @@ void stm32f4_peripherals_gpio_init(void) {
     //never_reset_pin_number(1,4); //PB4 JTRST
 
     // Port H is not included in GPIO port array
-    // never_reset_pin_number(5,0); //PH0 JTDO
+    // never_reset_pin_number(5,0); //PH0 JTDO   
     // never_reset_pin_number(5,1); //PH1 JTRST
 }
 
@@ -240,4 +240,3 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
 	}
 }
 
-
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 86a51d750..b2c417b11 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -59,13 +59,13 @@ STATIC void init_usb_vbus_sense(void) {
 }
 
 void init_usb_hardware(void) {
-    //TODO: if future chips overload this with options, move to peripherals management.
+    //TODO: if future chips overload this with options, move to peripherals management. 
 
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     /**USB_OTG_FS GPIO Configuration
     PA10     ------> USB_OTG_FS_ID
     PA11     ------> USB_OTG_FS_DM
-    PA12     ------> USB_OTG_FS_DP
+    PA12     ------> USB_OTG_FS_DP 
     */
     __HAL_RCC_GPIOA_CLK_ENABLE();
 
@@ -105,10 +105,10 @@ void init_usb_hardware(void) {
     HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
     never_reset_pin_number(0, 8);
 #endif
-
+    
     /* Peripheral clock enable */
     __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
     init_usb_vbus_sense();
-}
+}
\ No newline at end of file
diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/system_stm32f4xx.c
index dd9ab1acd..23a133647 100644
--- a/ports/stm/system_stm32f4xx.c
+++ b/ports/stm/system_stm32f4xx.c
@@ -1,6 +1,6 @@
 /*
  * Taken from ST Cube library and modified.  See below for original header.
- *
+ * 
  * Modifications copyright (c) 2019 Lucian Copeland for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -28,16 +28,16 @@
   * @author  MCD Application Team
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
-  *   This file provides two functions and one global variable to be called from
+  *   This file provides two functions and one global variable to be called from 
   *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
+  *      - SystemInit(): This function is called at startup just after reset and 
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32f4xx.s" file.
   *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
+  *                                  by the user application to setup the SysTick 
   *                                  timer or configure other parameters.
-  *
+  *                                     
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
@@ -79,8 +79,8 @@
 
 /** @addtogroup stm32f4xx_system
   * @{
-  */
-
+  */  
+  
 /** @addtogroup STM32F4xx_System_Private_Includes
   * @{
   */
@@ -89,7 +89,7 @@
 #include "stm32f4xx.h"
 #include "py/mpconfig.h"
 
-#if !defined  (HSE_VALUE)
+#if !defined  (HSE_VALUE) 
   #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -121,8 +121,8 @@
  || defined(STM32F412Cx)
 /* #define DATA_IN_ExtSRAM */
 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
-          STM32F412Zx || STM32F412Vx || STM32F412Zx*/
-
+          STM32F412Zx || STM32F412Vx || STM32F412Cx */
+ 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /* #define DATA_IN_ExtSDRAM */
@@ -132,7 +132,7 @@
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
                                    This value must be a multiple of 0x200. */
 /******************************************************************************/
 
@@ -154,7 +154,7 @@
   /* This variable is updated in three ways:
       1) by calling CMSIS function SystemCoreClockUpdate()
       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
          Note: If you use this function to configure the system clock; then there
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
@@ -171,7 +171,7 @@ const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
   */
 
 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void);
+  static void SystemInit_ExtMemCtl(void); 
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
 /**
@@ -184,7 +184,7 @@ const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 
 /**
   * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and External memory
+  *         Initialize the FPU setting, vector table location and External memory 
   *         configuration.
   * @param  None
   * @retval None
@@ -215,7 +215,7 @@ void SystemInit(void)
   RCC->CIR = 0x00000000;
 
 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl();
+  SystemInit_ExtMemCtl(); 
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
   /* Configure the Vector Table location add offset address ------------------*/
@@ -233,41 +233,41 @@ void SystemInit(void)
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
   *         be used by the user application to setup the SysTick timer or configure
   *         other parameters.
-  *
+  *           
   * @note   Each time the core clock (HCLK) changes, this function must be called
   *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
   *           constant and the selected clock source:
-  *
+  *             
   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
+  *                                              
   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
+  *         
   *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
   *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
+  *             in voltage and temperature.   
+  *    
   *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
   *              depends on the application requirements), user has to ensure that HSE_VALUE
   *              is same as the real frequency of the crystal used. Otherwise, this function
   *              may have wrong result.
-  *
+  *                
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
-  *
+  *     
   * @param  None
   * @retval None
   */
 void SystemCoreClockUpdate(void)
 {
   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
+  
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
 
@@ -283,10 +283,10 @@ void SystemCoreClockUpdate(void)
 
       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
          SYSCLK = PLL_VCO / PLL_P
-         */
+         */    
       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
+      
       if (pllsource != 0)
       {
         /* HSE used as PLL clock source */
@@ -335,79 +335,79 @@ void SystemInit_ExtMemCtl(void)
 
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
+  
   /* Connect PDx pins to FMC Alternate function */
   GPIOD->AFR[0]  = 0x00CCC0CC;
   GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */
+  /* Configure PDx pins in Alternate function mode */  
   GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */
+  /* Configure PDx pins speed to 100 MHz */  
   GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */
+  /* Configure PDx pins Output type to push-pull */  
   GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
+  /* No pull-up, pull-down for PDx pins */ 
   GPIOD->PUPDR   = 0x00000000;
 
   /* Connect PEx pins to FMC Alternate function */
   GPIOE->AFR[0]  = 0xC00CC0CC;
   GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
+  /* Configure PEx pins in Alternate function mode */ 
   GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */
+  /* Configure PEx pins speed to 100 MHz */ 
   GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */
+  /* Configure PEx pins Output type to push-pull */  
   GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
+  /* No pull-up, pull-down for PEx pins */ 
   GPIOE->PUPDR   = 0x00000000;
-
+  
   /* Connect PFx pins to FMC Alternate function */
   GPIOF->AFR[0]  = 0xCCCCCCCC;
   GPIOF->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PFx pins in Alternate function mode */
+  /* Configure PFx pins in Alternate function mode */   
   GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */
+  /* Configure PFx pins speed to 50 MHz */ 
   GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */
+  /* Configure PFx pins Output type to push-pull */  
   GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
+  /* No pull-up, pull-down for PFx pins */ 
   GPIOF->PUPDR   = 0x00000000;
 
   /* Connect PGx pins to FMC Alternate function */
   GPIOG->AFR[0]  = 0xCCCCCCCC;
   GPIOG->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PGx pins in Alternate function mode */
+  /* Configure PGx pins in Alternate function mode */ 
   GPIOG->MODER   = 0xAAAAAAAA;
-  /* Configure PGx pins speed to 50 MHz */
+  /* Configure PGx pins speed to 50 MHz */ 
   GPIOG->OSPEEDR = 0xAAAAAAAA;
-  /* Configure PGx pins Output type to push-pull */
+  /* Configure PGx pins Output type to push-pull */  
   GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
+  /* No pull-up, pull-down for PGx pins */ 
   GPIOG->PUPDR   = 0x00000000;
-
+  
   /* Connect PHx pins to FMC Alternate function */
   GPIOH->AFR[0]  = 0x00C0CC00;
   GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */
+  /* Configure PHx pins in Alternate function mode */ 
   GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */
+  /* Configure PHx pins speed to 50 MHz */ 
   GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */
+  /* Configure PHx pins Output type to push-pull */  
   GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */
+  /* No pull-up, pull-down for PHx pins */ 
   GPIOH->PUPDR   = 0x00000000;
-
+  
   /* Connect PIx pins to FMC Alternate function */
   GPIOI->AFR[0]  = 0xCCCCCCCC;
   GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */
+  /* Configure PIx pins in Alternate function mode */ 
   GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */
+  /* Configure PIx pins speed to 50 MHz */ 
   GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */
+  /* Configure PIx pins Output type to push-pull */  
   GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */
+  /* No pull-up, pull-down for PIx pins */ 
   GPIOI->PUPDR   = 0x00000000;
-
+  
 /*-- FMC Configuration -------------------------------------------------------*/
   /* Enable the FMC interface clock */
   RCC->AHB3ENR |= 0x00000001;
@@ -415,50 +415,50 @@ void SystemInit_ExtMemCtl(void)
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
 
   FMC_Bank5_6->SDCR[0] = 0x000019E4;
-  FMC_Bank5_6->SDTR[0] = 0x01115351;
-
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
   /* SDRAM initialization sequence */
   /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011;
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
 
   /* Delay */
   for (index = 0; index<1000; index++);
-
+  
   /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;
+  FMC_Bank5_6->SDCMR = 0x00000012;           
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
-
+  
   /* Auto refresh command */
   FMC_Bank5_6->SDCMR = 0x00000073;
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
-
+ 
   /* MRD register program */
   FMC_Bank5_6->SDCMR = 0x00046014;
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
   /* Set refresh count */
   tmpreg = FMC_Bank5_6->SDRTR;
   FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-
+  
   /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0];
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
   FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
@@ -466,7 +466,7 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[2]  = 0x00001011;
   FMC_Bank1->BTCR[3]  = 0x00000201;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
 #if defined(STM32F469xx) || defined(STM32F479xx)
   /* Configure and enable Bank1_SRAM2 */
   FMC_Bank1->BTCR[2]  = 0x00001091;
@@ -474,7 +474,7 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
 
-  (void)(tmp);
+  (void)(tmp); 
 }
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
@@ -500,13 +500,13 @@ void SystemInit_ExtMemCtl(void)
       clock */
   RCC->AHB1ENR |= 0x0000007D;
 #else
-  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
       clock */
   RCC->AHB1ENR |= 0x000001F8;
-#endif /* STM32F446xx */
+#endif /* STM32F446xx */  
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
+  
 #if defined(STM32F446xx)
   /* Connect PAx pins to FMC Alternate function */
   GPIOA->AFR[0]  |= 0xC0000000;
@@ -536,78 +536,78 @@ void SystemInit_ExtMemCtl(void)
   /* Connect PDx pins to FMC Alternate function */
   GPIOD->AFR[0]  = 0x000000CC;
   GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */
+  /* Configure PDx pins in Alternate function mode */  
   GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */
+  /* Configure PDx pins speed to 50 MHz */  
   GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */
+  /* Configure PDx pins Output type to push-pull */  
   GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
+  /* No pull-up, pull-down for PDx pins */ 
   GPIOD->PUPDR   = 0x00000000;
 
   /* Connect PEx pins to FMC Alternate function */
   GPIOE->AFR[0]  = 0xC00000CC;
   GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
+  /* Configure PEx pins in Alternate function mode */ 
   GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */
+  /* Configure PEx pins speed to 50 MHz */ 
   GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */
+  /* Configure PEx pins Output type to push-pull */  
   GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
+  /* No pull-up, pull-down for PEx pins */ 
   GPIOE->PUPDR   = 0x00000000;
 
   /* Connect PFx pins to FMC Alternate function */
   GPIOF->AFR[0]  = 0xCCCCCCCC;
   GPIOF->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PFx pins in Alternate function mode */
+  /* Configure PFx pins in Alternate function mode */   
   GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */
+  /* Configure PFx pins speed to 50 MHz */ 
   GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */
+  /* Configure PFx pins Output type to push-pull */  
   GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
+  /* No pull-up, pull-down for PFx pins */ 
   GPIOF->PUPDR   = 0x00000000;
 
   /* Connect PGx pins to FMC Alternate function */
   GPIOG->AFR[0]  = 0xCCCCCCCC;
   GPIOG->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PGx pins in Alternate function mode */
+  /* Configure PGx pins in Alternate function mode */ 
   GPIOG->MODER   = 0xAAAAAAAA;
-  /* Configure PGx pins speed to 50 MHz */
+  /* Configure PGx pins speed to 50 MHz */ 
   GPIOG->OSPEEDR = 0xAAAAAAAA;
-  /* Configure PGx pins Output type to push-pull */
+  /* Configure PGx pins Output type to push-pull */  
   GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
+  /* No pull-up, pull-down for PGx pins */ 
   GPIOG->PUPDR   = 0x00000000;
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx)  
   /* Connect PHx pins to FMC Alternate function */
   GPIOH->AFR[0]  = 0x00C0CC00;
   GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */
+  /* Configure PHx pins in Alternate function mode */ 
   GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */
+  /* Configure PHx pins speed to 50 MHz */ 
   GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */
+  /* Configure PHx pins Output type to push-pull */  
   GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */
+  /* No pull-up, pull-down for PHx pins */ 
   GPIOH->PUPDR   = 0x00000000;
-
+  
   /* Connect PIx pins to FMC Alternate function */
   GPIOI->AFR[0]  = 0xCCCCCCCC;
   GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */
+  /* Configure PIx pins in Alternate function mode */ 
   GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */
+  /* Configure PIx pins speed to 50 MHz */ 
   GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */
+  /* Configure PIx pins Output type to push-pull */  
   GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */
+  /* No pull-up, pull-down for PIx pins */ 
   GPIOI->PUPDR   = 0x00000000;
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
+  
 /*-- FMC Configuration -------------------------------------------------------*/
   /* Enable the FMC interface clock */
   RCC->AHB3ENR |= 0x00000001;
@@ -617,65 +617,65 @@ void SystemInit_ExtMemCtl(void)
   /* Configure and enable SDRAM bank1 */
 #if defined(STM32F446xx)
   FMC_Bank5_6->SDCR[0] = 0x00001954;
-#else
+#else  
   FMC_Bank5_6->SDCR[0] = 0x000019E4;
 #endif /* STM32F446xx */
-  FMC_Bank5_6->SDTR[0] = 0x01115351;
-
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
   /* SDRAM initialization sequence */
   /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011;
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
 
   /* Delay */
   for (index = 0; index<1000; index++);
-
+  
   /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;
+  FMC_Bank5_6->SDCMR = 0x00000012;           
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
-
+  
   /* Auto refresh command */
 #if defined(STM32F446xx)
   FMC_Bank5_6->SDCMR = 0x000000F3;
-#else
+#else  
   FMC_Bank5_6->SDCMR = 0x00000073;
 #endif /* STM32F446xx */
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
-
+ 
   /* MRD register program */
 #if defined(STM32F446xx)
   FMC_Bank5_6->SDCMR = 0x00044014;
-#else
+#else  
   FMC_Bank5_6->SDCMR = 0x00046014;
 #endif /* STM32F446xx */
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
   /* Set refresh count */
   tmpreg = FMC_Bank5_6->SDRTR;
 #if defined(STM32F446xx)
   FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
-#else
+#else    
   FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
 #endif /* STM32F446xx */
-
+  
   /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0];
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
   FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
 #endif /* DATA_IN_ExtSDRAM */
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
@@ -691,55 +691,55 @@ void SystemInit_ExtMemCtl(void)
   RCC->AHB1ENR   |= 0x00000078;
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
-
+  
   /* Connect PDx pins to FMC Alternate function */
   GPIOD->AFR[0]  = 0x00CCC0CC;
   GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */
+  /* Configure PDx pins in Alternate function mode */  
   GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */
+  /* Configure PDx pins speed to 100 MHz */  
   GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */
+  /* Configure PDx pins Output type to push-pull */  
   GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
+  /* No pull-up, pull-down for PDx pins */ 
   GPIOD->PUPDR   = 0x00000000;
 
   /* Connect PEx pins to FMC Alternate function */
   GPIOE->AFR[0]  = 0xC00CC0CC;
   GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
+  /* Configure PEx pins in Alternate function mode */ 
   GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */
+  /* Configure PEx pins speed to 100 MHz */ 
   GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */
+  /* Configure PEx pins Output type to push-pull */  
   GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
+  /* No pull-up, pull-down for PEx pins */ 
   GPIOE->PUPDR   = 0x00000000;
 
   /* Connect PFx pins to FMC Alternate function */
   GPIOF->AFR[0]  = 0x00CCCCCC;
   GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */
+  /* Configure PFx pins in Alternate function mode */   
   GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */
+  /* Configure PFx pins speed to 100 MHz */ 
   GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */
+  /* Configure PFx pins Output type to push-pull */  
   GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
+  /* No pull-up, pull-down for PFx pins */ 
   GPIOF->PUPDR   = 0x00000000;
 
   /* Connect PGx pins to FMC Alternate function */
   GPIOG->AFR[0]  = 0x00CCCCCC;
   GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */
+  /* Configure PGx pins in Alternate function mode */ 
   GPIOG->MODER   = 0x00085AAA;
-  /* Configure PGx pins speed to 100 MHz */
+  /* Configure PGx pins speed to 100 MHz */ 
   GPIOG->OSPEEDR = 0x000CAFFF;
-  /* Configure PGx pins Output type to push-pull */
+  /* Configure PGx pins Output type to push-pull */  
   GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
+  /* No pull-up, pull-down for PGx pins */ 
   GPIOG->PUPDR   = 0x00000000;
-
+  
 /*-- FMC/FSMC Configuration --------------------------------------------------*/
   /* Enable the FMC/FSMC interface clock */
   RCC->AHB3ENR         |= 0x00000001;
@@ -751,7 +751,7 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[2]  = 0x00001011;
   FMC_Bank1->BTCR[3]  = 0x00000201;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
 #if defined(STM32F469xx) || defined(STM32F479xx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
@@ -768,12 +768,12 @@ void SystemInit_ExtMemCtl(void)
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || defined(STM32F412Cx) */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */
-  (void)(tmp);
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || defined(STM32F412Cx)  */ 
+  (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
 /**
@@ -787,4 +787,4 @@ void SystemInit_ExtMemCtl(void)
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
-- 
cgit v1.2.3


From 24d1fd2bf1325ea6ede4a73cc6e8251d486f42a4 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Tue, 17 Mar 2020 00:48:19 -0700
Subject: PR Cleanup.

---
 lib/lwip                                         | 1 +
 lib/mbedtls                                      | 1 +
 lib/mynewt-nimble                                | 1 +
 lib/stm32lib                                     | 1 +
 ports/stm/boards/thunderpack/mpconfigboard.h     | 2 +-
 ports/stm/peripherals/stm32f4/periph.h           | 2 +-
 ports/stm/peripherals/stm32f4/pins.h             | 2 +-
 ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 1 -
 ports/stm/supervisor/usb.c                       | 2 +-
 ports/stm/system_stm32f4xx.c                     | 2 +-
 10 files changed, 9 insertions(+), 6 deletions(-)
 create mode 160000 lib/lwip
 create mode 160000 lib/mbedtls
 create mode 160000 lib/mynewt-nimble
 create mode 160000 lib/stm32lib

(limited to 'ports/stm/supervisor/usb.c')

diff --git a/lib/lwip b/lib/lwip
new file mode 160000
index 000000000..159e31b68
--- /dev/null
+++ b/lib/lwip
@@ -0,0 +1 @@
+Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10
diff --git a/lib/mbedtls b/lib/mbedtls
new file mode 160000
index 000000000..3f8d78411
--- /dev/null
+++ b/lib/mbedtls
@@ -0,0 +1 @@
+Subproject commit 3f8d78411a26e833db18d9fbde0e2f0baeda87f0
diff --git a/lib/mynewt-nimble b/lib/mynewt-nimble
new file mode 160000
index 000000000..223714cb1
--- /dev/null
+++ b/lib/mynewt-nimble
@@ -0,0 +1 @@
+Subproject commit 223714cb16c255cfa701929c0de6d7579bfd2cdd
diff --git a/lib/stm32lib b/lib/stm32lib
new file mode 160000
index 000000000..668d7a9e5
--- /dev/null
+++ b/lib/stm32lib
@@ -0,0 +1 @@
+Subproject commit 668d7a9e54aea98f8fe8a858eac1d3daa80fa824
diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h
index 18977c131..c9602d412 100644
--- a/ports/stm/boards/thunderpack/mpconfigboard.h
+++ b/ports/stm/boards/thunderpack/mpconfigboard.h
@@ -40,4 +40,4 @@
 #define MICROPY_HW_LED_STATUS (&pin_PA03)
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PB06)
-#define DEFAULT_I2C_BUS_SDA (&pin_PB07)
\ No newline at end of file
+#define DEFAULT_I2C_BUS_SDA (&pin_PB07)
diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h
index 1dfa7ac45..5ac8b4061 100644
--- a/ports/stm/peripherals/stm32f4/periph.h
+++ b/ports/stm/peripherals/stm32f4/periph.h
@@ -184,4 +184,4 @@ typedef struct {
 #include "stm32f407xx/periph.h"
 #endif
 
-#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
\ No newline at end of file
+#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h
index ce2980969..53040995d 100644
--- a/ports/stm/peripherals/stm32f4/pins.h
+++ b/ports/stm/peripherals/stm32f4/pins.h
@@ -96,4 +96,4 @@ extern const mp_obj_type_t mcu_pin_type;
 #include "stm32f407xx/pins.h"
 #endif
 
-#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
\ No newline at end of file
+#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
index 68a75f463..2eb296723 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
@@ -239,4 +239,3 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
 		default: break;
 	}
 }
-
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index b2c417b11..0c5e70dd8 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -111,4 +111,4 @@ void init_usb_hardware(void) {
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
     init_usb_vbus_sense();
-}
\ No newline at end of file
+}
diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/system_stm32f4xx.c
index 5fb2946e8..caa4f9caf 100644
--- a/ports/stm/system_stm32f4xx.c
+++ b/ports/stm/system_stm32f4xx.c
@@ -785,4 +785,4 @@ void SystemInit_ExtMemCtl(void)
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-- 
cgit v1.2.3


From 679314a22ed78ede26b7d01646e4fd82aeb30b68 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Wed, 18 Mar 2020 00:35:20 -0700
Subject: Fix disable VBUS sensing.

---
 ports/stm/supervisor/usb.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'ports/stm/supervisor/usb.c')

diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 0c5e70dd8..6cb9feb4b 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -41,7 +41,12 @@ STATIC void init_usb_vbus_sense(void) {
 #if (BOARD_NO_VBUS_SENSE)
     // Disable VBUS sensing
     #ifdef USB_OTG_GCCFG_VBDEN
+        // Deactivate VBUS Sensing B
         USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+        // B-peripheral session valid override enable
+        USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+        USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
     #else
         USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
         USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-- 
cgit v1.2.3


From 29ce7567098dd6b5b093b1bd5a3e0ff553c91801 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Sun, 22 Mar 2020 18:41:19 -0700
Subject: PR feedback.

---
 ports/stm/boards/thunderpack/pins.c | 8 ++++----
 ports/stm/supervisor/usb.c          | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'ports/stm/supervisor/usb.c')

diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c
index 830e99dae..04394993e 100644
--- a/ports/stm/boards/thunderpack/pins.c
+++ b/ports/stm/boards/thunderpack/pins.c
@@ -10,10 +10,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) },
     { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) },
     { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) },
-    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) },  //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, //USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, 
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) },
     { MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_PA13) },
     { MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_PA14) },
 
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 6cb9feb4b..93b5ae769 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -85,7 +85,7 @@ void init_usb_hardware(void) {
     never_reset_pin_number(0, 12);
 
     /* Configure VBUS Pin */
-#if (BOARD_NO_VBUS_SENSE)
+#if (BOARD_NO_VBUS_SENSE == 0)
     GPIO_InitStruct.Pin = GPIO_PIN_9;
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
-- 
cgit v1.2.3


From 8ed4deee9d49b477a1a11cea52248122caaef3d5 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Mon, 23 Mar 2020 23:06:55 -0700
Subject: Rename pins

---
 ports/stm/boards/thunderpack/pins.c | 35 ++++++++++++++++-------------------
 ports/stm/supervisor/usb.c          |  2 +-
 2 files changed, 17 insertions(+), 20 deletions(-)

(limited to 'ports/stm/supervisor/usb.c')

diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c
index 04394993e..559d9658e 100644
--- a/ports/stm/boards/thunderpack/pins.c
+++ b/ports/stm/boards/thunderpack/pins.c
@@ -1,26 +1,23 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
-    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
-    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
-    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
-    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
-    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
-    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) },
-    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) },
-    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) },
-    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, 
-    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) },
-    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) },
-    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) },
-    { MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_PA13) },
-    { MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA2), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PA3), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_PA4), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA5), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA6), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA7), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PA8), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PA9), MP_ROM_PTR(&pin_PA09) }, 
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
 
-    { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) },
-    { MP_ROM_QSTR(MP_QSTR_B5), MP_ROM_PTR(&pin_PB05) },
-    { MP_ROM_QSTR(MP_QSTR_B6), MP_ROM_PTR(&pin_PB06) },
-    { MP_ROM_QSTR(MP_QSTR_B7), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_PB5), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB6), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB7), MP_ROM_PTR(&pin_PB07) },
 
     { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PA00) },
     { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PA01) },
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 93b5ae769..8bfdcde40 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -85,7 +85,7 @@ void init_usb_hardware(void) {
     never_reset_pin_number(0, 12);
 
     /* Configure VBUS Pin */
-#if (BOARD_NO_VBUS_SENSE == 0)
+#if  !(BOARD_NO_VBUS_SENSE)
     GPIO_InitStruct.Pin = GPIO_PIN_9;
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
-- 
cgit v1.2.3