From f884c2b9b68baba4031f7cc95aa04d01fed218bf Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Sun, 15 Mar 2020 19:34:41 -0700
Subject: Incremental update

---
 ports/stm/supervisor/internal_flash.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'ports/stm/supervisor')

diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h
index 9f16a799d..92d1baddc 100644
--- a/ports/stm/supervisor/internal_flash.h
+++ b/ports/stm/supervisor/internal_flash.h
@@ -42,7 +42,7 @@
 #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
 #endif
 
-#ifdef STM32F412Zx
+#if (defined(STM32F412Zx) || defined(STM32F412Cx))
 #define STM32_FLASH_SIZE 0x100000 //1MB
 #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
 #endif
-- 
cgit v1.2.3


From 8a93a81a2628a644b8bcc656b96881b6de35fa98 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Sun, 15 Mar 2020 22:31:36 -0700
Subject: Chip specific code.

---
 ports/stm/common-hal/busio/UART.c                  |   4 +
 ports/stm/peripherals/stm32f4/periph.h             |  45 +++++---
 .../stm32f4/stm32f412cx_thunderpack/periph.c       | 128 ++++++++++++++++++++-
 .../stm32f4/stm32f412cx_thunderpack/pins.c         |  36 +++---
 .../stm32f4/stm32f412cx_thunderpack/pins.h         |  36 +++---
 ports/stm/supervisor/usb.c                         |   8 +-
 6 files changed, 193 insertions(+), 64 deletions(-)

(limited to 'ports/stm/supervisor')

diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c
index 0b434fd02..20648bf3d 100644
--- a/ports/stm/common-hal/busio/UART.c
+++ b/ports/stm/common-hal/busio/UART.c
@@ -443,9 +443,11 @@ STATIC void uart_clock_enable(uint16_t mask) {
     #endif
     #ifdef USART3
     if (mask & (1 << 2)) {
+        #ifndef STM32F412Cx
         __HAL_RCC_USART3_FORCE_RESET();
         __HAL_RCC_USART3_RELEASE_RESET();
         __HAL_RCC_USART3_CLK_ENABLE();
+        #endif
     }
     #endif
     #ifdef UART4
@@ -516,9 +518,11 @@ STATIC void uart_clock_disable(uint16_t mask) {
     #endif
     #ifdef USART3
     if (mask & (1 << 2)) {
+        #ifndef STM32F412Cx
         __HAL_RCC_USART3_FORCE_RESET();
         __HAL_RCC_USART3_RELEASE_RESET();
         __HAL_RCC_USART3_CLK_DISABLE();
+        #endif
     }
     #endif
     #ifdef UART4
diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h
index d311afe4a..663df4bed 100644
--- a/ports/stm/peripherals/stm32f4/periph.h
+++ b/ports/stm/peripherals/stm32f4/periph.h
@@ -33,9 +33,9 @@
 #include "stm32f4xx_hal.h"
 #include "stm32f4/pins.h"
 
-// I2C 
+// I2C
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them. 
+// find a compelling reason to store more unique data in them.
 
 typedef struct {
     uint8_t i2c_index:4; // Index of the I2C unit (1 to 3)
@@ -44,8 +44,8 @@ typedef struct {
 } mcu_i2c_sda_obj_t;
 
 typedef struct {
-    uint8_t i2c_index:4; 
-    uint8_t altfn_index:4; 
+    uint8_t i2c_index:4;
+    uint8_t altfn_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_i2c_scl_obj_t;
 
@@ -64,9 +64,9 @@ typedef struct {
     .pin = scl_pin, \
 }
 
-// SPI 
+// SPI
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them. 
+// find a compelling reason to store more unique data in them.
 
 typedef struct {
     uint8_t spi_index:4; //Up to 6 SPI units
@@ -75,20 +75,20 @@ typedef struct {
 } mcu_spi_sck_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4; 
-    uint8_t altfn_index:4; 
+    uint8_t spi_index:4;
+    uint8_t altfn_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_spi_mosi_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4; 
-    uint8_t altfn_index:4; 
+    uint8_t spi_index:4;
+    uint8_t altfn_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_spi_miso_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4; 
-    uint8_t altfn_index:4; 
+    uint8_t spi_index:4;
+    uint8_t altfn_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_spi_nss_obj_t;
 
@@ -101,17 +101,17 @@ typedef struct {
 
 // UART
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them. 
+// find a compelling reason to store more unique data in them.
 
 typedef struct {
-    uint8_t uart_index:4; 
-    uint8_t altfn_index:4; 
+    uint8_t uart_index:4;
+    uint8_t altfn_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_uart_tx_obj_t;
 
 typedef struct {
-    uint8_t uart_index:4; 
-    uint8_t altfn_index:4; 
+    uint8_t uart_index:4;
+    uint8_t altfn_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_uart_rx_obj_t;
 
@@ -124,8 +124,8 @@ typedef struct {
 
 //Timers
 typedef struct {
-    uint8_t tim_index:4; 
-    uint8_t altfn_index:4; 
+    uint8_t tim_index:4;
+    uint8_t altfn_index:4;
     uint8_t channel_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_tim_pin_obj_t;
@@ -154,6 +154,13 @@ typedef struct {
 #include "stm32f411xe/periph.h"
 #endif
 
+#ifdef BOARD_THUNDERPACK_STM32F412
+#define HAS_DAC 0
+#define HAS_TRNG 1
+#define HAS_BASIC_TIM 1
+#include "stm32f412cx_thunderpack/periph.h"
+#endif
+
 #ifdef STM32F412Zx
 #define HAS_DAC 0
 #define HAS_TRNG 1
diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c
index aa9d7abf5..f5effa80e 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c
@@ -31,56 +31,133 @@
 
 // I2C
 
-I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, NULL, NULL};
+I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3};
 
 const mcu_i2c_sda_obj_t mcu_i2c_sda_list[8] = {
     I2C_SDA(1, 4, &pin_PB07),
+    I2C_SDA(1, 4, &pin_PB09),
+    I2C_SDA(2, 4, &pin_PB11), //not on LQFP100
+    I2C_SDA(2, 9, &pin_PB09),
+    I2C_SDA(2, 9, &pin_PB03),
+    I2C_SDA(3, 4, &pin_PC09),
+    I2C_SDA(3, 9, &pin_PB04),
+    I2C_SDA(3, 9, &pin_PB08)
 };
 
 const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = {
     I2C_SCL(1, 4, &pin_PB06),
+    I2C_SCL(1, 4, &pin_PB08),
+    I2C_SCL(2, 4, &pin_PB10),
+    I2C_SCL(3, 4, &pin_PA08)
 };
 
 // SPI
 
-SPI_TypeDef * mcu_spi_banks[5] = {SPI1, NULL, NULL, NULL, NULL};
+SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5};
 
 const mcu_spi_sck_obj_t mcu_spi_sck_list[15] = {
     SPI(1, 5, &pin_PA05),
+    SPI(1, 5, &pin_PB03),
+    SPI(2, 5, &pin_PB10),
+    SPI(2, 5, &pin_PB13),
+    SPI(2, 5, &pin_PC07),
+    SPI(2, 5, &pin_PD03),
+    SPI(3, 6, &pin_PB03),
+    SPI(3, 7, &pin_PB12),
+    SPI(3, 6, &pin_PC10),
+    SPI(4, 6, &pin_PB13),
+    SPI(4, 5, &pin_PE02),
+    SPI(4, 5, &pin_PE12),
+    SPI(5, 6, &pin_PB00),
+    SPI(5, 6, &pin_PE02),
+    SPI(5, 6, &pin_PE12)
 };
 
 const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14] = {
     SPI(1, 5, &pin_PA07),
     SPI(1, 5, &pin_PB05),
+    SPI(2, 5, &pin_PB15),
+    SPI(2, 5, &pin_PC03),
+    SPI(3, 6, &pin_PB05),
+    SPI(3, 6, &pin_PC12),
+    SPI(3, 5, &pin_PD06),
+    SPI(4, 5, &pin_PA01),
+    SPI(4, 5, &pin_PE06),
+    SPI(4, 5, &pin_PE14),
+    SPI(5, 6, &pin_PA10),
+    SPI(5, 6, &pin_PB08),
+    SPI(5, 6, &pin_PE06),
+    SPI(5, 6, &pin_PE14)
 };
 
 const mcu_spi_miso_obj_t mcu_spi_miso_list[12] = {
     SPI(1, 5, &pin_PA06),
+    SPI(1, 5, &pin_PB04),
+    SPI(2, 5, &pin_PB14),
+    SPI(2, 5, &pin_PC02),
+    SPI(3, 6, &pin_PB04),
+    SPI(3, 6, &pin_PC11),
+    SPI(4, 6, &pin_PA11),
+    SPI(4, 5, &pin_PE05),
+    SPI(4, 5, &pin_PE13),
+    SPI(5, 6, &pin_PA12),
+    SPI(5, 6, &pin_PE05),
+    SPI(5, 6, &pin_PE13)
 };
 
 const mcu_spi_nss_obj_t mcu_spi_nss_list[12] = {
     SPI(1, 5, &pin_PA04),
+    SPI(1, 5, &pin_PA15),
+    SPI(2, 5, &pin_PB09),
+    SPI(2, 5, &pin_PB12),
+    SPI(3, 6, &pin_PA04),
+    SPI(3, 6, &pin_PA15),
+    SPI(4, 6, &pin_PB12),
+    SPI(4, 5, &pin_PE04),
+    SPI(4, 5, &pin_PE11),
+    SPI(5, 6, &pin_PB01),
+    SPI(5, 6, &pin_PE04),
+    SPI(5, 6, &pin_PE11)
 };
 
 //UART
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, NULL, NULL, NULL, NULL, NULL};
-bool mcu_uart_has_usart[MAX_UART] = {true, false, false, false, false, false};
+USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, NULL, NULL, USART6};
+bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true};
 
 const mcu_uart_tx_obj_t mcu_uart_tx_list[11] = {
+    UART(2, 7, &pin_PA02),
     UART(1, 7, &pin_PA09),
+    UART(1, 7, &pin_PA15),
+    UART(6, 8, &pin_PA11),
     UART(1, 7, &pin_PB06),
+    UART(3, 7, &pin_PB10),
+    UART(6, 8, &pin_PC06),
+    UART(3, 7, &pin_PC10),
+    UART(2, 7, &pin_PD05),
+    UART(3, 7, &pin_PD08),
+    UART(6, 8, &pin_PG14),
 };
 
 const mcu_uart_rx_obj_t mcu_uart_rx_list[12] = {
+    UART(2, 7, &pin_PA03),
     UART(1, 7, &pin_PA10),
+    UART(6, 8, &pin_PA12),
+    UART(1, 7, &pin_PB03),
     UART(1, 7, &pin_PB07),
+    UART(3, 7, &pin_PB11),
+    UART(3, 7, &pin_PC05),
+    UART(6, 8, &pin_PC07),
+    UART(3, 7, &pin_PC11),
+    UART(2, 7, &pin_PD06),
+    UART(3, 7, &pin_PD09),
+    UART(6, 8, &pin_PG09),
 };
 
 //Timers
 //TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, NULL,
-                                    NULL, NULL, TIM13, TIM14};
+TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
+                                    TIM11, TIM12, TIM13, TIM14};
 
 const mcu_tim_pin_obj_t mcu_tim_pin_list[60] = {
     TIM(2,1,1,&pin_PA00),
@@ -101,7 +178,46 @@ const mcu_tim_pin_obj_t mcu_tim_pin_list[60] = {
     TIM(1,1,2,&pin_PA09),
     TIM(1,1,3,&pin_PA10),
     TIM(1,1,4,&pin_PA11),
+    TIM(2,1,1,&pin_PA15),
+    TIM(3,2,3,&pin_PB00),
+    TIM(3,2,4,&pin_PB01),
+    TIM(2,1,2,&pin_PB03),
+    TIM(3,2,1,&pin_PB04),
     TIM(3,2,2,&pin_PB05),
     TIM(4,2,1,&pin_PB06),
     TIM(4,2,2,&pin_PB07),
+    TIM(4,2,3,&pin_PB08),
+    TIM(10,2,1,&pin_PB08),
+    TIM(4,2,4,&pin_PB09),
+    TIM(11,2,1,&pin_PB09),
+    TIM(2,1,3,&pin_PB10),
+    TIM(2,1,4,&pin_PB11),
+    TIM(12,9,1,&pin_PB14),
+    TIM(12,9,2,&pin_PB15),
+    TIM(3,2,1,&pin_PC06),
+    TIM(3,2,2,&pin_PC07),
+    TIM(3,2,3,&pin_PC08),
+    TIM(3,2,4,&pin_PC09),
+    TIM(8,3,1,&pin_PC06),
+    TIM(8,3,2,&pin_PC07),
+    TIM(8,3,3,&pin_PC08),
+    TIM(8,3,4,&pin_PC09),
+    TIM(4,2,1,&pin_PD12),
+    TIM(4,2,2,&pin_PD13),
+    TIM(4,2,3,&pin_PD14),
+    TIM(4,2,4,&pin_PD15),
+    TIM(9,3,1,&pin_PE05),
+    TIM(9,3,2,&pin_PE06),
+    TIM(1,1,1,&pin_PE09),
+    TIM(1,1,2,&pin_PE11),
+    TIM(1,1,3,&pin_PE13),
+    TIM(1,1,4,&pin_PE14),
+    TIM(10,3,1,&pin_PF06),
+    TIM(11,3,1,&pin_PF07),
+    TIM(13,9,1,&pin_PF08),
+    TIM(14,9,1,&pin_PF09),
+    TIM(5,2,1,&pin_PF03),
+    TIM(5,2,2,&pin_PF04),
+    TIM(5,2,3,&pin_PF05),
+    TIM(5,2,4,&pin_PF10),
 };
diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c
index c56de5a29..fddab5ef1 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c
@@ -38,17 +38,17 @@ const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp
 const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN
 const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT
 
-const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); // 144 only 
+const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); // 144 only
 
 const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10));
 const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11));
@@ -71,14 +71,14 @@ const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_1,8));
 const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_1,9));
 const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC);
 
-const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only 
-const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only 
-const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only 
-const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only 
-const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only 
+const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only
+const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only
+const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only
+const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only
+const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only
 
-const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC);   // 144 only 
-const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC);   // 144 only 
+const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC);   // 144 only
+const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC);   // 144 only
 
 const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC);
 const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC);
diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h
index 180f5c316..07c22d528 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h
+++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h
@@ -38,17 +38,17 @@ extern const mcu_pin_obj_t pin_PC13;
 extern const mcu_pin_obj_t pin_PC14;
 //pg 51
 extern const mcu_pin_obj_t pin_PC15;
-extern const mcu_pin_obj_t pin_PF00;  // 144 only 
-extern const mcu_pin_obj_t pin_PF01;  // 144 only 
-extern const mcu_pin_obj_t pin_PF02;  // 144 only 
-extern const mcu_pin_obj_t pin_PF03;  // 144 only 
-extern const mcu_pin_obj_t pin_PF04;  // 144 only 
-extern const mcu_pin_obj_t pin_PF05;  // 144 only 
-extern const mcu_pin_obj_t pin_PF06;  // 144 only 
-extern const mcu_pin_obj_t pin_PF07;  // 144 only 
-extern const mcu_pin_obj_t pin_PF08;  // 144 only 
-extern const mcu_pin_obj_t pin_PF09;  // 144 only 
-extern const mcu_pin_obj_t pin_PF10; // 144 only 
+extern const mcu_pin_obj_t pin_PF00;  // 144 only
+extern const mcu_pin_obj_t pin_PF01;  // 144 only
+extern const mcu_pin_obj_t pin_PF02;  // 144 only
+extern const mcu_pin_obj_t pin_PF03;  // 144 only
+extern const mcu_pin_obj_t pin_PF04;  // 144 only
+extern const mcu_pin_obj_t pin_PF05;  // 144 only
+extern const mcu_pin_obj_t pin_PF06;  // 144 only
+extern const mcu_pin_obj_t pin_PF07;  // 144 only
+extern const mcu_pin_obj_t pin_PF08;  // 144 only
+extern const mcu_pin_obj_t pin_PF09;  // 144 only
+extern const mcu_pin_obj_t pin_PF10; // 144 only
 //pg 52
 extern const mcu_pin_obj_t pin_PC00;
 extern const mcu_pin_obj_t pin_PC01;
@@ -69,13 +69,13 @@ extern const mcu_pin_obj_t pin_PC05;
 extern const mcu_pin_obj_t pin_PB00;
 extern const mcu_pin_obj_t pin_PB01;
 extern const mcu_pin_obj_t pin_PB02;
-extern const mcu_pin_obj_t pin_PF11; // 144 only 
-extern const mcu_pin_obj_t pin_PF12; // 144 only 
-extern const mcu_pin_obj_t pin_PF13; // 144 only 
-extern const mcu_pin_obj_t pin_PF14; // 144 only 
-extern const mcu_pin_obj_t pin_PF15; // 144 only 
-extern const mcu_pin_obj_t pin_PG00;  // 144 only 
-extern const mcu_pin_obj_t pin_PG01;  // 144 only 
+extern const mcu_pin_obj_t pin_PF11; // 144 only
+extern const mcu_pin_obj_t pin_PF12; // 144 only
+extern const mcu_pin_obj_t pin_PF13; // 144 only
+extern const mcu_pin_obj_t pin_PF14; // 144 only
+extern const mcu_pin_obj_t pin_PF15; // 144 only
+extern const mcu_pin_obj_t pin_PG00;  // 144 only
+extern const mcu_pin_obj_t pin_PG01;  // 144 only
 //pg 55
 extern const mcu_pin_obj_t pin_PE07;
 extern const mcu_pin_obj_t pin_PE08;
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 358c2de5b..86a51d750 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -59,13 +59,13 @@ STATIC void init_usb_vbus_sense(void) {
 }
 
 void init_usb_hardware(void) {
-    //TODO: if future chips overload this with options, move to peripherals management. 
+    //TODO: if future chips overload this with options, move to peripherals management.
 
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     /**USB_OTG_FS GPIO Configuration
     PA10     ------> USB_OTG_FS_ID
     PA11     ------> USB_OTG_FS_DM
-    PA12     ------> USB_OTG_FS_DP 
+    PA12     ------> USB_OTG_FS_DP
     */
     __HAL_RCC_GPIOA_CLK_ENABLE();
 
@@ -80,11 +80,13 @@ void init_usb_hardware(void) {
     never_reset_pin_number(0, 12);
 
     /* Configure VBUS Pin */
+#if (BOARD_NO_VBUS_SENSE)
     GPIO_InitStruct.Pin = GPIO_PIN_9;
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
     never_reset_pin_number(0, 9);
+#endif
 
     /* This for ID line debug */
     GPIO_InitStruct.Pin = GPIO_PIN_10;
@@ -103,7 +105,7 @@ void init_usb_hardware(void) {
     HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
     never_reset_pin_number(0, 8);
 #endif
-    
+
     /* Peripheral clock enable */
     __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-- 
cgit v1.2.3


From 07549b7fd955cb1368a58d12e82e005865305f26 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Tue, 17 Mar 2020 00:27:04 -0700
Subject: Bring back trimmed spaces.

---
 ports/stm/peripherals/stm32f4/periph.h           |  40 +--
 ports/stm/peripherals/stm32f4/pins.h             |  10 +-
 ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c |   3 +-
 ports/stm/supervisor/usb.c                       |   8 +-
 ports/stm/system_stm32f4xx.c                     | 304 +++++++++++------------
 5 files changed, 182 insertions(+), 183 deletions(-)

(limited to 'ports/stm/supervisor')

diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h
index 663df4bed..1dfa7ac45 100644
--- a/ports/stm/peripherals/stm32f4/periph.h
+++ b/ports/stm/peripherals/stm32f4/periph.h
@@ -33,9 +33,9 @@
 #include "stm32f4xx_hal.h"
 #include "stm32f4/pins.h"
 
-// I2C
+// I2C 
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them.
+// find a compelling reason to store more unique data in them. 
 
 typedef struct {
     uint8_t i2c_index:4; // Index of the I2C unit (1 to 3)
@@ -44,8 +44,8 @@ typedef struct {
 } mcu_i2c_sda_obj_t;
 
 typedef struct {
-    uint8_t i2c_index:4;
-    uint8_t altfn_index:4;
+    uint8_t i2c_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_i2c_scl_obj_t;
 
@@ -64,9 +64,9 @@ typedef struct {
     .pin = scl_pin, \
 }
 
-// SPI
+// SPI 
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them.
+// find a compelling reason to store more unique data in them. 
 
 typedef struct {
     uint8_t spi_index:4; //Up to 6 SPI units
@@ -75,20 +75,20 @@ typedef struct {
 } mcu_spi_sck_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4;
-    uint8_t altfn_index:4;
+    uint8_t spi_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_spi_mosi_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4;
-    uint8_t altfn_index:4;
+    uint8_t spi_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_spi_miso_obj_t;
 
 typedef struct {
-    uint8_t spi_index:4;
-    uint8_t altfn_index:4;
+    uint8_t spi_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_spi_nss_obj_t;
 
@@ -101,17 +101,17 @@ typedef struct {
 
 // UART
 // TODO: these objects should be condensed into a single 'periph_pin' unless we
-// find a compelling reason to store more unique data in them.
+// find a compelling reason to store more unique data in them. 
 
 typedef struct {
-    uint8_t uart_index:4;
-    uint8_t altfn_index:4;
+    uint8_t uart_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_uart_tx_obj_t;
 
 typedef struct {
-    uint8_t uart_index:4;
-    uint8_t altfn_index:4;
+    uint8_t uart_index:4; 
+    uint8_t altfn_index:4; 
     const mcu_pin_obj_t * pin;
 } mcu_uart_rx_obj_t;
 
@@ -124,8 +124,8 @@ typedef struct {
 
 //Timers
 typedef struct {
-    uint8_t tim_index:4;
-    uint8_t altfn_index:4;
+    uint8_t tim_index:4; 
+    uint8_t altfn_index:4; 
     uint8_t channel_index:4;
     const mcu_pin_obj_t * pin;
 } mcu_tim_pin_obj_t;
@@ -184,4 +184,4 @@ typedef struct {
 #include "stm32f407xx/periph.h"
 #endif
 
-#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
+#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
\ No newline at end of file
diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h
index 7e8baf89d..ce2980969 100644
--- a/ports/stm/peripherals/stm32f4/pins.h
+++ b/ports/stm/peripherals/stm32f4/pins.h
@@ -40,7 +40,7 @@ typedef struct {
     mp_obj_base_t base;
     uint8_t port:4;
     uint8_t number:4;
-    uint8_t adc_unit:3;
+    uint8_t adc_unit:3; 
     uint8_t adc_channel:5;
 } mcu_pin_obj_t;
 
@@ -51,8 +51,8 @@ typedef struct {
 #define ADC_3   4
 
 //STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin,
-//but all 3 ADCs will share the same input number per pin.
-//F4 family has 3 ADC max, 24 channels max.
+//but all 3 ADCs will share the same input number per pin. 
+//F4 family has 3 ADC max, 24 channels max. 
 #define ADC_INPUT(mask, number) \
     .adc_unit = mask, \
     .adc_channel = number,
@@ -64,7 +64,7 @@ typedef struct {
 extern const mp_obj_type_t mcu_pin_type;
 
 // STM32 can have up to 9 ports, each restricted to 16 pins
-// We split the pin/port evenly, in contrast to nrf.
+// We split the pin/port evenly, in contrast to nrf. 
 #define PIN(p_port, p_number, p_adc)       \
 { \
     { &mcu_pin_type }, \
@@ -96,4 +96,4 @@ extern const mp_obj_type_t mcu_pin_type;
 #include "stm32f407xx/pins.h"
 #endif
 
-#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
+#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
\ No newline at end of file
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
index fde10be3c..68a75f463 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
@@ -220,7 +220,7 @@ void stm32f4_peripherals_gpio_init(void) {
     //never_reset_pin_number(1,4); //PB4 JTRST
 
     // Port H is not included in GPIO port array
-    // never_reset_pin_number(5,0); //PH0 JTDO
+    // never_reset_pin_number(5,0); //PH0 JTDO   
     // never_reset_pin_number(5,1); //PH1 JTRST
 }
 
@@ -240,4 +240,3 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
 	}
 }
 
-
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 86a51d750..b2c417b11 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -59,13 +59,13 @@ STATIC void init_usb_vbus_sense(void) {
 }
 
 void init_usb_hardware(void) {
-    //TODO: if future chips overload this with options, move to peripherals management.
+    //TODO: if future chips overload this with options, move to peripherals management. 
 
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     /**USB_OTG_FS GPIO Configuration
     PA10     ------> USB_OTG_FS_ID
     PA11     ------> USB_OTG_FS_DM
-    PA12     ------> USB_OTG_FS_DP
+    PA12     ------> USB_OTG_FS_DP 
     */
     __HAL_RCC_GPIOA_CLK_ENABLE();
 
@@ -105,10 +105,10 @@ void init_usb_hardware(void) {
     HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
     never_reset_pin_number(0, 8);
 #endif
-
+    
     /* Peripheral clock enable */
     __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
     init_usb_vbus_sense();
-}
+}
\ No newline at end of file
diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/system_stm32f4xx.c
index dd9ab1acd..23a133647 100644
--- a/ports/stm/system_stm32f4xx.c
+++ b/ports/stm/system_stm32f4xx.c
@@ -1,6 +1,6 @@
 /*
  * Taken from ST Cube library and modified.  See below for original header.
- *
+ * 
  * Modifications copyright (c) 2019 Lucian Copeland for Adafruit Industries
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -28,16 +28,16 @@
   * @author  MCD Application Team
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
-  *   This file provides two functions and one global variable to be called from
+  *   This file provides two functions and one global variable to be called from 
   *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
+  *      - SystemInit(): This function is called at startup just after reset and 
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32f4xx.s" file.
   *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
+  *                                  by the user application to setup the SysTick 
   *                                  timer or configure other parameters.
-  *
+  *                                     
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
@@ -79,8 +79,8 @@
 
 /** @addtogroup stm32f4xx_system
   * @{
-  */
-
+  */  
+  
 /** @addtogroup STM32F4xx_System_Private_Includes
   * @{
   */
@@ -89,7 +89,7 @@
 #include "stm32f4xx.h"
 #include "py/mpconfig.h"
 
-#if !defined  (HSE_VALUE)
+#if !defined  (HSE_VALUE) 
   #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -121,8 +121,8 @@
  || defined(STM32F412Cx)
 /* #define DATA_IN_ExtSRAM */
 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
-          STM32F412Zx || STM32F412Vx || STM32F412Zx*/
-
+          STM32F412Zx || STM32F412Vx || STM32F412Cx */
+ 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /* #define DATA_IN_ExtSDRAM */
@@ -132,7 +132,7 @@
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
                                    This value must be a multiple of 0x200. */
 /******************************************************************************/
 
@@ -154,7 +154,7 @@
   /* This variable is updated in three ways:
       1) by calling CMSIS function SystemCoreClockUpdate()
       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
          Note: If you use this function to configure the system clock; then there
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
@@ -171,7 +171,7 @@ const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
   */
 
 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void);
+  static void SystemInit_ExtMemCtl(void); 
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
 /**
@@ -184,7 +184,7 @@ const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 
 /**
   * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and External memory
+  *         Initialize the FPU setting, vector table location and External memory 
   *         configuration.
   * @param  None
   * @retval None
@@ -215,7 +215,7 @@ void SystemInit(void)
   RCC->CIR = 0x00000000;
 
 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl();
+  SystemInit_ExtMemCtl(); 
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
   /* Configure the Vector Table location add offset address ------------------*/
@@ -233,41 +233,41 @@ void SystemInit(void)
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
   *         be used by the user application to setup the SysTick timer or configure
   *         other parameters.
-  *
+  *           
   * @note   Each time the core clock (HCLK) changes, this function must be called
   *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
   *           constant and the selected clock source:
-  *
+  *             
   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
+  *                                              
   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
+  *         
   *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
   *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
+  *             in voltage and temperature.   
+  *    
   *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
   *              depends on the application requirements), user has to ensure that HSE_VALUE
   *              is same as the real frequency of the crystal used. Otherwise, this function
   *              may have wrong result.
-  *
+  *                
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
-  *
+  *     
   * @param  None
   * @retval None
   */
 void SystemCoreClockUpdate(void)
 {
   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
+  
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
 
@@ -283,10 +283,10 @@ void SystemCoreClockUpdate(void)
 
       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
          SYSCLK = PLL_VCO / PLL_P
-         */
+         */    
       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
+      
       if (pllsource != 0)
       {
         /* HSE used as PLL clock source */
@@ -335,79 +335,79 @@ void SystemInit_ExtMemCtl(void)
 
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
+  
   /* Connect PDx pins to FMC Alternate function */
   GPIOD->AFR[0]  = 0x00CCC0CC;
   GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */
+  /* Configure PDx pins in Alternate function mode */  
   GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */
+  /* Configure PDx pins speed to 100 MHz */  
   GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */
+  /* Configure PDx pins Output type to push-pull */  
   GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
+  /* No pull-up, pull-down for PDx pins */ 
   GPIOD->PUPDR   = 0x00000000;
 
   /* Connect PEx pins to FMC Alternate function */
   GPIOE->AFR[0]  = 0xC00CC0CC;
   GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
+  /* Configure PEx pins in Alternate function mode */ 
   GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */
+  /* Configure PEx pins speed to 100 MHz */ 
   GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */
+  /* Configure PEx pins Output type to push-pull */  
   GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
+  /* No pull-up, pull-down for PEx pins */ 
   GPIOE->PUPDR   = 0x00000000;
-
+  
   /* Connect PFx pins to FMC Alternate function */
   GPIOF->AFR[0]  = 0xCCCCCCCC;
   GPIOF->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PFx pins in Alternate function mode */
+  /* Configure PFx pins in Alternate function mode */   
   GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */
+  /* Configure PFx pins speed to 50 MHz */ 
   GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */
+  /* Configure PFx pins Output type to push-pull */  
   GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
+  /* No pull-up, pull-down for PFx pins */ 
   GPIOF->PUPDR   = 0x00000000;
 
   /* Connect PGx pins to FMC Alternate function */
   GPIOG->AFR[0]  = 0xCCCCCCCC;
   GPIOG->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PGx pins in Alternate function mode */
+  /* Configure PGx pins in Alternate function mode */ 
   GPIOG->MODER   = 0xAAAAAAAA;
-  /* Configure PGx pins speed to 50 MHz */
+  /* Configure PGx pins speed to 50 MHz */ 
   GPIOG->OSPEEDR = 0xAAAAAAAA;
-  /* Configure PGx pins Output type to push-pull */
+  /* Configure PGx pins Output type to push-pull */  
   GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
+  /* No pull-up, pull-down for PGx pins */ 
   GPIOG->PUPDR   = 0x00000000;
-
+  
   /* Connect PHx pins to FMC Alternate function */
   GPIOH->AFR[0]  = 0x00C0CC00;
   GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */
+  /* Configure PHx pins in Alternate function mode */ 
   GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */
+  /* Configure PHx pins speed to 50 MHz */ 
   GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */
+  /* Configure PHx pins Output type to push-pull */  
   GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */
+  /* No pull-up, pull-down for PHx pins */ 
   GPIOH->PUPDR   = 0x00000000;
-
+  
   /* Connect PIx pins to FMC Alternate function */
   GPIOI->AFR[0]  = 0xCCCCCCCC;
   GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */
+  /* Configure PIx pins in Alternate function mode */ 
   GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */
+  /* Configure PIx pins speed to 50 MHz */ 
   GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */
+  /* Configure PIx pins Output type to push-pull */  
   GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */
+  /* No pull-up, pull-down for PIx pins */ 
   GPIOI->PUPDR   = 0x00000000;
-
+  
 /*-- FMC Configuration -------------------------------------------------------*/
   /* Enable the FMC interface clock */
   RCC->AHB3ENR |= 0x00000001;
@@ -415,50 +415,50 @@ void SystemInit_ExtMemCtl(void)
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
 
   FMC_Bank5_6->SDCR[0] = 0x000019E4;
-  FMC_Bank5_6->SDTR[0] = 0x01115351;
-
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
   /* SDRAM initialization sequence */
   /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011;
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
 
   /* Delay */
   for (index = 0; index<1000; index++);
-
+  
   /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;
+  FMC_Bank5_6->SDCMR = 0x00000012;           
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
-
+  
   /* Auto refresh command */
   FMC_Bank5_6->SDCMR = 0x00000073;
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
-
+ 
   /* MRD register program */
   FMC_Bank5_6->SDCMR = 0x00046014;
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
   /* Set refresh count */
   tmpreg = FMC_Bank5_6->SDRTR;
   FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-
+  
   /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0];
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
   FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
@@ -466,7 +466,7 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[2]  = 0x00001011;
   FMC_Bank1->BTCR[3]  = 0x00000201;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
 #if defined(STM32F469xx) || defined(STM32F479xx)
   /* Configure and enable Bank1_SRAM2 */
   FMC_Bank1->BTCR[2]  = 0x00001091;
@@ -474,7 +474,7 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
 
-  (void)(tmp);
+  (void)(tmp); 
 }
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
@@ -500,13 +500,13 @@ void SystemInit_ExtMemCtl(void)
       clock */
   RCC->AHB1ENR |= 0x0000007D;
 #else
-  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
       clock */
   RCC->AHB1ENR |= 0x000001F8;
-#endif /* STM32F446xx */
+#endif /* STM32F446xx */  
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
+  
 #if defined(STM32F446xx)
   /* Connect PAx pins to FMC Alternate function */
   GPIOA->AFR[0]  |= 0xC0000000;
@@ -536,78 +536,78 @@ void SystemInit_ExtMemCtl(void)
   /* Connect PDx pins to FMC Alternate function */
   GPIOD->AFR[0]  = 0x000000CC;
   GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */
+  /* Configure PDx pins in Alternate function mode */  
   GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */
+  /* Configure PDx pins speed to 50 MHz */  
   GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */
+  /* Configure PDx pins Output type to push-pull */  
   GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
+  /* No pull-up, pull-down for PDx pins */ 
   GPIOD->PUPDR   = 0x00000000;
 
   /* Connect PEx pins to FMC Alternate function */
   GPIOE->AFR[0]  = 0xC00000CC;
   GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
+  /* Configure PEx pins in Alternate function mode */ 
   GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */
+  /* Configure PEx pins speed to 50 MHz */ 
   GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */
+  /* Configure PEx pins Output type to push-pull */  
   GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
+  /* No pull-up, pull-down for PEx pins */ 
   GPIOE->PUPDR   = 0x00000000;
 
   /* Connect PFx pins to FMC Alternate function */
   GPIOF->AFR[0]  = 0xCCCCCCCC;
   GPIOF->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PFx pins in Alternate function mode */
+  /* Configure PFx pins in Alternate function mode */   
   GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */
+  /* Configure PFx pins speed to 50 MHz */ 
   GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */
+  /* Configure PFx pins Output type to push-pull */  
   GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
+  /* No pull-up, pull-down for PFx pins */ 
   GPIOF->PUPDR   = 0x00000000;
 
   /* Connect PGx pins to FMC Alternate function */
   GPIOG->AFR[0]  = 0xCCCCCCCC;
   GPIOG->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PGx pins in Alternate function mode */
+  /* Configure PGx pins in Alternate function mode */ 
   GPIOG->MODER   = 0xAAAAAAAA;
-  /* Configure PGx pins speed to 50 MHz */
+  /* Configure PGx pins speed to 50 MHz */ 
   GPIOG->OSPEEDR = 0xAAAAAAAA;
-  /* Configure PGx pins Output type to push-pull */
+  /* Configure PGx pins Output type to push-pull */  
   GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
+  /* No pull-up, pull-down for PGx pins */ 
   GPIOG->PUPDR   = 0x00000000;
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx)  
   /* Connect PHx pins to FMC Alternate function */
   GPIOH->AFR[0]  = 0x00C0CC00;
   GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */
+  /* Configure PHx pins in Alternate function mode */ 
   GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */
+  /* Configure PHx pins speed to 50 MHz */ 
   GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */
+  /* Configure PHx pins Output type to push-pull */  
   GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */
+  /* No pull-up, pull-down for PHx pins */ 
   GPIOH->PUPDR   = 0x00000000;
-
+  
   /* Connect PIx pins to FMC Alternate function */
   GPIOI->AFR[0]  = 0xCCCCCCCC;
   GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */
+  /* Configure PIx pins in Alternate function mode */ 
   GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */
+  /* Configure PIx pins speed to 50 MHz */ 
   GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */
+  /* Configure PIx pins Output type to push-pull */  
   GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */
+  /* No pull-up, pull-down for PIx pins */ 
   GPIOI->PUPDR   = 0x00000000;
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
+  
 /*-- FMC Configuration -------------------------------------------------------*/
   /* Enable the FMC interface clock */
   RCC->AHB3ENR |= 0x00000001;
@@ -617,65 +617,65 @@ void SystemInit_ExtMemCtl(void)
   /* Configure and enable SDRAM bank1 */
 #if defined(STM32F446xx)
   FMC_Bank5_6->SDCR[0] = 0x00001954;
-#else
+#else  
   FMC_Bank5_6->SDCR[0] = 0x000019E4;
 #endif /* STM32F446xx */
-  FMC_Bank5_6->SDTR[0] = 0x01115351;
-
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
   /* SDRAM initialization sequence */
   /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011;
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
 
   /* Delay */
   for (index = 0; index<1000; index++);
-
+  
   /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;
+  FMC_Bank5_6->SDCMR = 0x00000012;           
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
-
+  
   /* Auto refresh command */
 #if defined(STM32F446xx)
   FMC_Bank5_6->SDCMR = 0x000000F3;
-#else
+#else  
   FMC_Bank5_6->SDCMR = 0x00000073;
 #endif /* STM32F446xx */
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
   }
-
+ 
   /* MRD register program */
 #if defined(STM32F446xx)
   FMC_Bank5_6->SDCMR = 0x00044014;
-#else
+#else  
   FMC_Bank5_6->SDCMR = 0x00046014;
 #endif /* STM32F446xx */
   timeout = 0xFFFF;
   while((tmpreg != 0) && (timeout-- > 0))
   {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
   /* Set refresh count */
   tmpreg = FMC_Bank5_6->SDRTR;
 #if defined(STM32F446xx)
   FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
-#else
+#else    
   FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
 #endif /* STM32F446xx */
-
+  
   /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0];
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
   FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
 #endif /* DATA_IN_ExtSDRAM */
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
@@ -691,55 +691,55 @@ void SystemInit_ExtMemCtl(void)
   RCC->AHB1ENR   |= 0x00000078;
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
-
+  
   /* Connect PDx pins to FMC Alternate function */
   GPIOD->AFR[0]  = 0x00CCC0CC;
   GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */
+  /* Configure PDx pins in Alternate function mode */  
   GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */
+  /* Configure PDx pins speed to 100 MHz */  
   GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */
+  /* Configure PDx pins Output type to push-pull */  
   GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
+  /* No pull-up, pull-down for PDx pins */ 
   GPIOD->PUPDR   = 0x00000000;
 
   /* Connect PEx pins to FMC Alternate function */
   GPIOE->AFR[0]  = 0xC00CC0CC;
   GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
+  /* Configure PEx pins in Alternate function mode */ 
   GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */
+  /* Configure PEx pins speed to 100 MHz */ 
   GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */
+  /* Configure PEx pins Output type to push-pull */  
   GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
+  /* No pull-up, pull-down for PEx pins */ 
   GPIOE->PUPDR   = 0x00000000;
 
   /* Connect PFx pins to FMC Alternate function */
   GPIOF->AFR[0]  = 0x00CCCCCC;
   GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */
+  /* Configure PFx pins in Alternate function mode */   
   GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */
+  /* Configure PFx pins speed to 100 MHz */ 
   GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */
+  /* Configure PFx pins Output type to push-pull */  
   GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
+  /* No pull-up, pull-down for PFx pins */ 
   GPIOF->PUPDR   = 0x00000000;
 
   /* Connect PGx pins to FMC Alternate function */
   GPIOG->AFR[0]  = 0x00CCCCCC;
   GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */
+  /* Configure PGx pins in Alternate function mode */ 
   GPIOG->MODER   = 0x00085AAA;
-  /* Configure PGx pins speed to 100 MHz */
+  /* Configure PGx pins speed to 100 MHz */ 
   GPIOG->OSPEEDR = 0x000CAFFF;
-  /* Configure PGx pins Output type to push-pull */
+  /* Configure PGx pins Output type to push-pull */  
   GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
+  /* No pull-up, pull-down for PGx pins */ 
   GPIOG->PUPDR   = 0x00000000;
-
+  
 /*-- FMC/FSMC Configuration --------------------------------------------------*/
   /* Enable the FMC/FSMC interface clock */
   RCC->AHB3ENR         |= 0x00000001;
@@ -751,7 +751,7 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[2]  = 0x00001011;
   FMC_Bank1->BTCR[3]  = 0x00000201;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
 #if defined(STM32F469xx) || defined(STM32F479xx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
@@ -768,12 +768,12 @@ void SystemInit_ExtMemCtl(void)
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || defined(STM32F412Cx) */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */
-  (void)(tmp);
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || defined(STM32F412Cx)  */ 
+  (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
 /**
@@ -787,4 +787,4 @@ void SystemInit_ExtMemCtl(void)
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
-- 
cgit v1.2.3


From 24d1fd2bf1325ea6ede4a73cc6e8251d486f42a4 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Tue, 17 Mar 2020 00:48:19 -0700
Subject: PR Cleanup.

---
 lib/lwip                                         | 1 +
 lib/mbedtls                                      | 1 +
 lib/mynewt-nimble                                | 1 +
 lib/stm32lib                                     | 1 +
 ports/stm/boards/thunderpack/mpconfigboard.h     | 2 +-
 ports/stm/peripherals/stm32f4/periph.h           | 2 +-
 ports/stm/peripherals/stm32f4/pins.h             | 2 +-
 ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 1 -
 ports/stm/supervisor/usb.c                       | 2 +-
 ports/stm/system_stm32f4xx.c                     | 2 +-
 10 files changed, 9 insertions(+), 6 deletions(-)
 create mode 160000 lib/lwip
 create mode 160000 lib/mbedtls
 create mode 160000 lib/mynewt-nimble
 create mode 160000 lib/stm32lib

(limited to 'ports/stm/supervisor')

diff --git a/lib/lwip b/lib/lwip
new file mode 160000
index 000000000..159e31b68
--- /dev/null
+++ b/lib/lwip
@@ -0,0 +1 @@
+Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10
diff --git a/lib/mbedtls b/lib/mbedtls
new file mode 160000
index 000000000..3f8d78411
--- /dev/null
+++ b/lib/mbedtls
@@ -0,0 +1 @@
+Subproject commit 3f8d78411a26e833db18d9fbde0e2f0baeda87f0
diff --git a/lib/mynewt-nimble b/lib/mynewt-nimble
new file mode 160000
index 000000000..223714cb1
--- /dev/null
+++ b/lib/mynewt-nimble
@@ -0,0 +1 @@
+Subproject commit 223714cb16c255cfa701929c0de6d7579bfd2cdd
diff --git a/lib/stm32lib b/lib/stm32lib
new file mode 160000
index 000000000..668d7a9e5
--- /dev/null
+++ b/lib/stm32lib
@@ -0,0 +1 @@
+Subproject commit 668d7a9e54aea98f8fe8a858eac1d3daa80fa824
diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h
index 18977c131..c9602d412 100644
--- a/ports/stm/boards/thunderpack/mpconfigboard.h
+++ b/ports/stm/boards/thunderpack/mpconfigboard.h
@@ -40,4 +40,4 @@
 #define MICROPY_HW_LED_STATUS (&pin_PA03)
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PB06)
-#define DEFAULT_I2C_BUS_SDA (&pin_PB07)
\ No newline at end of file
+#define DEFAULT_I2C_BUS_SDA (&pin_PB07)
diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h
index 1dfa7ac45..5ac8b4061 100644
--- a/ports/stm/peripherals/stm32f4/periph.h
+++ b/ports/stm/peripherals/stm32f4/periph.h
@@ -184,4 +184,4 @@ typedef struct {
 #include "stm32f407xx/periph.h"
 #endif
 
-#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
\ No newline at end of file
+#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__
diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h
index ce2980969..53040995d 100644
--- a/ports/stm/peripherals/stm32f4/pins.h
+++ b/ports/stm/peripherals/stm32f4/pins.h
@@ -96,4 +96,4 @@ extern const mp_obj_type_t mcu_pin_type;
 #include "stm32f407xx/pins.h"
 #endif
 
-#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
\ No newline at end of file
+#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
index 68a75f463..2eb296723 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
@@ -239,4 +239,3 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
 		default: break;
 	}
 }
-
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index b2c417b11..0c5e70dd8 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -111,4 +111,4 @@ void init_usb_hardware(void) {
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
     init_usb_vbus_sense();
-}
\ No newline at end of file
+}
diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/system_stm32f4xx.c
index 5fb2946e8..caa4f9caf 100644
--- a/ports/stm/system_stm32f4xx.c
+++ b/ports/stm/system_stm32f4xx.c
@@ -785,4 +785,4 @@ void SystemInit_ExtMemCtl(void)
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-- 
cgit v1.2.3


From 679314a22ed78ede26b7d01646e4fd82aeb30b68 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Wed, 18 Mar 2020 00:35:20 -0700
Subject: Fix disable VBUS sensing.

---
 ports/stm/supervisor/usb.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'ports/stm/supervisor')

diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 0c5e70dd8..6cb9feb4b 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -41,7 +41,12 @@ STATIC void init_usb_vbus_sense(void) {
 #if (BOARD_NO_VBUS_SENSE)
     // Disable VBUS sensing
     #ifdef USB_OTG_GCCFG_VBDEN
+        // Deactivate VBUS Sensing B
         USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+        // B-peripheral session valid override enable
+        USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+        USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
     #else
         USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
         USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-- 
cgit v1.2.3


From 284073584a66c0fde03e439fbdb54a4a5dc34790 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Thu, 19 Mar 2020 00:01:32 -0700
Subject: Cleanup

---
 ports/stm/boards/thunderpack/mpconfigboard.mk    | 2 +-
 ports/stm/common-hal/busio/UART.c                | 4 ----
 ports/stm/peripherals/stm32f4/periph.h           | 7 -------
 ports/stm/peripherals/stm32f4/pins.h             | 3 ---
 ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 1 +
 ports/stm/supervisor/internal_flash.h            | 2 +-
 6 files changed, 3 insertions(+), 16 deletions(-)

(limited to 'ports/stm/supervisor')

diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk
index 3efd6a8bd..0bf5b57a8 100644
--- a/ports/stm/boards/thunderpack/mpconfigboard.mk
+++ b/ports/stm/boards/thunderpack/mpconfigboard.mk
@@ -1,6 +1,6 @@
 USB_VID = 0x239A
 USB_PID = 0x806A
-USB_PRODUCT = "Thunderpack powered by ST"
+USB_PRODUCT = "Thunderpack STM32F411"
 USB_MANUFACTURER = "Jeremy Gillick"
 USB_DEVICES = "CDC,MSC"
 
diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c
index 20648bf3d..0b434fd02 100644
--- a/ports/stm/common-hal/busio/UART.c
+++ b/ports/stm/common-hal/busio/UART.c
@@ -443,11 +443,9 @@ STATIC void uart_clock_enable(uint16_t mask) {
     #endif
     #ifdef USART3
     if (mask & (1 << 2)) {
-        #ifndef STM32F412Cx
         __HAL_RCC_USART3_FORCE_RESET();
         __HAL_RCC_USART3_RELEASE_RESET();
         __HAL_RCC_USART3_CLK_ENABLE();
-        #endif
     }
     #endif
     #ifdef UART4
@@ -518,11 +516,9 @@ STATIC void uart_clock_disable(uint16_t mask) {
     #endif
     #ifdef USART3
     if (mask & (1 << 2)) {
-        #ifndef STM32F412Cx
         __HAL_RCC_USART3_FORCE_RESET();
         __HAL_RCC_USART3_RELEASE_RESET();
         __HAL_RCC_USART3_CLK_DISABLE();
-        #endif
     }
     #endif
     #ifdef UART4
diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h
index 5ac8b4061..d311afe4a 100644
--- a/ports/stm/peripherals/stm32f4/periph.h
+++ b/ports/stm/peripherals/stm32f4/periph.h
@@ -154,13 +154,6 @@ typedef struct {
 #include "stm32f411xe/periph.h"
 #endif
 
-#ifdef BOARD_THUNDERPACK_STM32F412
-#define HAS_DAC 0
-#define HAS_TRNG 1
-#define HAS_BASIC_TIM 1
-#include "stm32f412cx_thunderpack/periph.h"
-#endif
-
 #ifdef STM32F412Zx
 #define HAS_DAC 0
 #define HAS_TRNG 1
diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h
index 53040995d..44ef4c1ba 100644
--- a/ports/stm/peripherals/stm32f4/pins.h
+++ b/ports/stm/peripherals/stm32f4/pins.h
@@ -83,9 +83,6 @@ extern const mp_obj_type_t mcu_pin_type;
 #ifdef STM32F411xE
 #include "stm32f411xe/pins.h"
 #endif
-#ifdef BOARD_THUNDERPACK_STM32F412
-#include "stm32f412cx_thunderpack/pins.h"
-#endif
 #ifdef STM32F412Zx
 #include "stm32f412zx/pins.h"
 #endif
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
index 2eb296723..68a75f463 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
@@ -239,3 +239,4 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
 		default: break;
 	}
 }
+
diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h
index 92d1baddc..9f16a799d 100644
--- a/ports/stm/supervisor/internal_flash.h
+++ b/ports/stm/supervisor/internal_flash.h
@@ -42,7 +42,7 @@
 #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
 #endif
 
-#if (defined(STM32F412Zx) || defined(STM32F412Cx))
+#ifdef STM32F412Zx
 #define STM32_FLASH_SIZE 0x100000 //1MB
 #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
 #endif
-- 
cgit v1.2.3


From d76b76cb1db59b85ef1300f6afb1aee97e5e0c72 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Sun, 22 Mar 2020 02:22:59 -0700
Subject: Add non-volatile memory support to STM

---
 ports/stm/boards/STM32F411VETx_nvm_FLASH.ld     | 118 ++++++++++++++++++++++++
 ports/stm/boards/thunderpack/mpconfigboard.h    |  11 ++-
 ports/stm/boards/thunderpack/mpconfigboard.mk   |   4 +-
 ports/stm/common-hal/microcontroller/__init__.c |  12 +++
 ports/stm/common-hal/nvm/ByteArray.c            |  73 +++++++++++++++
 ports/stm/common-hal/nvm/ByteArray.h            |  43 +++++++++
 ports/stm/common-hal/nvm/__init__.c             |  27 ++++++
 ports/stm/supervisor/internal_flash.h           |   4 +
 8 files changed, 286 insertions(+), 6 deletions(-)
 create mode 100644 ports/stm/boards/STM32F411VETx_nvm_FLASH.ld
 create mode 100644 ports/stm/common-hal/nvm/ByteArray.c
 create mode 100644 ports/stm/common-hal/nvm/ByteArray.h
 create mode 100644 ports/stm/common-hal/nvm/__init__.c

(limited to 'ports/stm/supervisor')

diff --git a/ports/stm/boards/STM32F411VETx_nvm_FLASH.ld b/ports/stm/boards/STM32F411VETx_nvm_FLASH.ld
new file mode 100644
index 000000000..8382cb781
--- /dev/null
+++ b/ports/stm/boards/STM32F411VETx_nvm_FLASH.ld
@@ -0,0 +1,118 @@
+/*
+    GNU linker script for STM32F411 via Micropython
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
+    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 32K /* sectors 1,2 are 16K */
+    FLASH_NVM (rwx) : ORIGIN = 0x0800C000, LENGTH = 16K /* sector 3 is 16K */
+    FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 448K /* sector 4 is 64K, sectors 5,6,7 are 128K */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+
+/* Define the top end of the stack.  The stack is full descending so begins just
+   above last byte of RAM.  Note that EABI requires the stack to be 8-byte
+   aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_start = _ebss; /* heap starts just after statically allocated memory */
+_heap_end = 0x2001c000; /* tunable */
+
+ENTRY(Reset_Handler)
+
+/* define output sections */
+SECTIONS
+{
+    /* The startup code goes first into FLASH */
+    .isr_vector :
+    {
+        . = ALIGN(4);
+        KEEP(*(.isr_vector)) /* Startup code */
+
+        /* This first flash block is 16K annd the isr vectors only take up
+           about 400 bytes. Micropython pads this with files, but this didn't
+           work with the size of Circuitpython's ff object. */
+
+        . = ALIGN(4);
+    } >FLASH_ISR
+
+    /* Non-volitile memory */
+    .nvm_data :
+    {
+        . = ALIGN(4);
+        KEEP(*(.nvm_data))
+        . = ALIGN(4);
+    } >FLASH_NVM
+
+    /* The program code and other data goes into FLASH */
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text*)          /* .text* sections (code) */
+        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    /*  *(.glue_7)   */    /* glue arm to thumb code */
+    /*  *(.glue_7t)  */    /* glue thumb to arm code */
+
+        . = ALIGN(4);
+        _etext = .;        /* define a global symbol at end of code */
+    } >FLASH_TEXT
+
+    /* used by the startup to initialize data */
+    _sidata = LOADADDR(.data);
+
+    /* This is the initialized data section
+    The program executes knowing that the data is in the RAM
+    but the loader puts the initial values in the FLASH (inidata).
+    It is one task of the startup to copy the initial values from FLASH to RAM. */
+    .data :
+    {
+        . = ALIGN(4);
+        _sdata = .;        /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
+        *(.data*)          /* .data* sections */
+
+        . = ALIGN(4);
+        _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
+    } >RAM AT> FLASH_TEXT
+
+    /* Uninitialized data section */
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;         /* define a global symbol at bss start; used by startup code */
+        *(.bss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        _ebss = .;         /* define a global symbol at bss end; used by startup code and GC */
+    } >RAM
+
+    /* this is to define the start of the heap, and make sure we have a minimum size */
+    .heap :
+    {
+        . = ALIGN(4);
+        . = . + _minimum_heap_size;
+        . = ALIGN(4);
+    } >RAM
+
+    /* this just checks there is enough RAM for the stack */
+    .stack :
+    {
+        . = ALIGN(4);
+        . = . + _minimum_stack_size;
+        . = ALIGN(4);
+    } >RAM
+
+    .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h
index 0e66f2a71..62bf7609d 100644
--- a/ports/stm/boards/thunderpack/mpconfigboard.h
+++ b/ports/stm/boards/thunderpack/mpconfigboard.h
@@ -26,17 +26,18 @@
 #define MICROPY_HW_BOARD_NAME       "THUNDERPACK"
 #define MICROPY_HW_MCU_NAME         "STM32F411CE"
 
-#define FLASH_SIZE                  (0x80000)
-#define FLASH_PAGE_SIZE             (0x4000)
-#define BOARD_FLASH_SIZE            (FLASH_SIZE - 0x2000 - 0xC000)
+#define FLASH_SIZE                         (0x80000)
+#define FLASH_PAGE_SIZE                    (0x4000)
+#define CIRCUITPY_INTERNAL_NVM_SIZE        (0x4000)
+#define CIRCUITPY_INTERNAL_NVM_START_ADDR  (0x0800C000)
+#define CIRCUITPY_INTERNAL_NVM_SECTOR      FLASH_SECTOR_3
+#define BOARD_FLASH_SIZE            (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000)
 
 #define BOARD_OSC_DIV               (24)
 #define BOARD_OVERWRITE_SWD         (1)
 #define BOARD_NO_VBUS_SENSE         (1)
 
 // Status LEDs
-#define MICROPY_HW_LED_TX      (&pin_PA00)
-#define MICROPY_HW_LED_RX      (&pin_PB01)
 #define MICROPY_HW_LED_STATUS  (&pin_PA02)
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PB06)
diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk
index 0bf5b57a8..6fcaae6ab 100644
--- a/ports/stm/boards/thunderpack/mpconfigboard.mk
+++ b/ports/stm/boards/thunderpack/mpconfigboard.mk
@@ -7,12 +7,14 @@ USB_DEVICES = "CDC,MSC"
 INTERNAL_FLASH_FILESYSTEM = 1
 LONGINT_IMPL = NONE
 
+CIRCUITPY_NVM = 1
+
 MCU_SERIES = m4
 MCU_VARIANT = stm32f4
 MCU_SUB_VARIANT = stm32f411xe
 MCU_PACKAGE = 48
 CMSIS_MCU = STM32F411xE
-LD_FILE = boards/STM32F411VETx_FLASH.ld
+LD_FILE = boards/STM32F411VETx_nvm_FLASH.ld
 STARTUP_FILE = startup_stm32f411xe.s
 
 
diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c
index 0c680eb05..85e66fb00 100644
--- a/ports/stm/common-hal/microcontroller/__init__.c
+++ b/ports/stm/common-hal/microcontroller/__init__.c
@@ -32,6 +32,7 @@
 #include "common-hal/microcontroller/Pin.h"
 #include "common-hal/microcontroller/Processor.h"
 
+#include "shared-bindings/nvm/ByteArray.h"
 #include "shared-bindings/microcontroller/__init__.h"
 #include "shared-bindings/microcontroller/Pin.h"
 #include "shared-bindings/microcontroller/Processor.h"
@@ -109,6 +110,17 @@ const mcu_processor_obj_t common_hal_mcu_processor_obj = {
     },
 };
 
+#if CIRCUITPY_INTERNAL_NVM_SIZE > 0
+// The singleton nvm.ByteArray object.
+const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = {
+    .base = {
+        .type = &nvm_bytearray_type,
+    },
+    .len = NVM_BYTEARRAY_BUFFER,
+    .start_address = (uint8_t*) (CIRCUITPY_INTERNAL_NVM_START_ADDR)
+};
+#endif
+
 STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = {
 #if MCU_PACKAGE >= 100
   { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
diff --git a/ports/stm/common-hal/nvm/ByteArray.c b/ports/stm/common-hal/nvm/ByteArray.c
new file mode 100644
index 000000000..1aaf54653
--- /dev/null
+++ b/ports/stm/common-hal/nvm/ByteArray.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "common-hal/nvm/ByteArray.h"
+
+#include "stm32f4xx_hal.h"
+
+#include "supervisor/shared/stack.h"
+
+#include <stdint.h>
+#include <string.h>
+
+uint32_t common_hal_nvm_bytearray_get_length(nvm_bytearray_obj_t *self) {
+    return self->len;
+}
+
+bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self,
+        uint32_t start_index, uint8_t* values, uint32_t len) {
+    // Copy flash to buffer
+    uint8_t buffer[self->len];
+    memcpy(buffer, self->start_address, self->len);
+
+    // Set bytes in buffer
+    memmove(buffer + start_index, values, len);
+
+    // Erase flash sector
+    HAL_FLASH_Unlock();
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR );
+    FLASH_Erase_Sector(CIRCUITPY_INTERNAL_NVM_SECTOR, VOLTAGE_RANGE_3);
+
+    // Write bytes to flash
+    uint32_t i;
+    uint32_t flash_addr = (uint32_t)self->start_address;
+    for (i = 0; i < self->len; i++, flash_addr++) {
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, flash_addr, buffer[i]) != HAL_OK) {
+            HAL_FLASH_Lock();
+            return false;
+        }
+    }
+    
+    // Finish up
+    HAL_FLASH_Lock();
+    return true;
+}
+
+// NVM memory is memory mapped so reading it is easy.
+void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t *self,
+    uint32_t start_index, uint32_t len, uint8_t* values) {
+    memcpy(values, self->start_address + start_index, len);
+}
diff --git a/ports/stm/common-hal/nvm/ByteArray.h b/ports/stm/common-hal/nvm/ByteArray.h
new file mode 100644
index 000000000..8ad64cb81
--- /dev/null
+++ b/ports/stm/common-hal/nvm/ByteArray.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_NVM_BYTEARRAY_H
+#define MICROPY_INCLUDED_STM32_COMMON_HAL_NVM_BYTEARRAY_H
+
+#include "py/obj.h"
+
+// STM flash is saved in sectors (not pages), at a minimum size of 16k.
+// To limit the RAM usage during writing, we want to set a smaller
+// maximum value.
+#define NVM_BYTEARRAY_BUFFER 512
+
+typedef struct {
+    mp_obj_base_t base;
+    uint8_t* start_address;
+    uint32_t len;
+} nvm_bytearray_obj_t;
+
+#endif // MICROPY_INCLUDED_STM32_COMMON_HAL_NVM_BYTEARRAY_H
diff --git a/ports/stm/common-hal/nvm/__init__.c b/ports/stm/common-hal/nvm/__init__.c
new file mode 100644
index 000000000..f0792430f
--- /dev/null
+++ b/ports/stm/common-hal/nvm/__init__.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// No nvm module functions.
diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h
index 9f16a799d..859470ff0 100644
--- a/ports/stm/supervisor/internal_flash.h
+++ b/ports/stm/supervisor/internal_flash.h
@@ -39,8 +39,12 @@
 
 #ifdef STM32F411xE
 #define STM32_FLASH_SIZE 0x80000 //512KiB
+#ifdef CIRCUITPY_NVM
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x8000 //32KiB
+#else
 #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
 #endif
+#endif
 
 #ifdef STM32F412Zx
 #define STM32_FLASH_SIZE 0x100000 //1MB
-- 
cgit v1.2.3


From 29ce7567098dd6b5b093b1bd5a3e0ff553c91801 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Sun, 22 Mar 2020 18:41:19 -0700
Subject: PR feedback.

---
 ports/stm/boards/thunderpack/pins.c | 8 ++++----
 ports/stm/supervisor/usb.c          | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'ports/stm/supervisor')

diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c
index 830e99dae..04394993e 100644
--- a/ports/stm/boards/thunderpack/pins.c
+++ b/ports/stm/boards/thunderpack/pins.c
@@ -10,10 +10,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) },
     { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) },
     { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) },
-    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) },  //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, //USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, 
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) },
     { MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_PA13) },
     { MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_PA14) },
 
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 6cb9feb4b..93b5ae769 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -85,7 +85,7 @@ void init_usb_hardware(void) {
     never_reset_pin_number(0, 12);
 
     /* Configure VBUS Pin */
-#if (BOARD_NO_VBUS_SENSE)
+#if (BOARD_NO_VBUS_SENSE == 0)
     GPIO_InitStruct.Pin = GPIO_PIN_9;
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
-- 
cgit v1.2.3


From 8ed4deee9d49b477a1a11cea52248122caaef3d5 Mon Sep 17 00:00:00 2001
From: jgillick <j_gillick@yahoo.com>
Date: Mon, 23 Mar 2020 23:06:55 -0700
Subject: Rename pins

---
 ports/stm/boards/thunderpack/pins.c | 35 ++++++++++++++++-------------------
 ports/stm/supervisor/usb.c          |  2 +-
 2 files changed, 17 insertions(+), 20 deletions(-)

(limited to 'ports/stm/supervisor')

diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c
index 04394993e..559d9658e 100644
--- a/ports/stm/boards/thunderpack/pins.c
+++ b/ports/stm/boards/thunderpack/pins.c
@@ -1,26 +1,23 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
-    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
-    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
-    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
-    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
-    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
-    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) },
-    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) },
-    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) },
-    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, 
-    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) },
-    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) },
-    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) },
-    { MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_PA13) },
-    { MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA2), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PA3), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_PA4), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA5), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA6), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA7), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PA8), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PA9), MP_ROM_PTR(&pin_PA09) }, 
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
 
-    { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) },
-    { MP_ROM_QSTR(MP_QSTR_B5), MP_ROM_PTR(&pin_PB05) },
-    { MP_ROM_QSTR(MP_QSTR_B6), MP_ROM_PTR(&pin_PB06) },
-    { MP_ROM_QSTR(MP_QSTR_B7), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_PB5), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB6), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB7), MP_ROM_PTR(&pin_PB07) },
 
     { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PA00) },
     { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PA01) },
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index 93b5ae769..8bfdcde40 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -85,7 +85,7 @@ void init_usb_hardware(void) {
     never_reset_pin_number(0, 12);
 
     /* Configure VBUS Pin */
-#if (BOARD_NO_VBUS_SENSE == 0)
+#if  !(BOARD_NO_VBUS_SENSE)
     GPIO_InitStruct.Pin = GPIO_PIN_9;
     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
-- 
cgit v1.2.3