From 6f153804da4734bebd2abbc750c7679c0bf3dc3d Mon Sep 17 00:00:00 2001 From: jgillick Date: Sat, 14 Mar 2020 00:03:14 -0700 Subject: Add initial thunderpack port files. --- ports/stm/boards/STM32F412CGUx_FLASH.ld | 189 ++++++++ ports/stm/boards/startup_stm32f412cx_thunderpack.s | 521 +++++++++++++++++++++ ports/stm/boards/thunderpack/board.c | 38 ++ ports/stm/boards/thunderpack/mpconfigboard.h | 37 ++ ports/stm/boards/thunderpack/mpconfigboard.mk | 22 + ports/stm/boards/thunderpack/pins.c | 95 ++++ ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h | 442 +++++++++++++++++ .../stm32f4/stm32f412cx_thunderpack/clocks.c | 77 +++ .../stm32f4/stm32f412cx_thunderpack/gpio.c | 242 ++++++++++ .../stm32f4/stm32f412cx_thunderpack/periph.c | 107 +++++ .../stm32f4/stm32f412cx_thunderpack/periph.h | 58 +++ .../stm32f4/stm32f412cx_thunderpack/pins.c | 161 +++++++ .../stm32f4/stm32f412cx_thunderpack/pins.h | 158 +++++++ 13 files changed, 2147 insertions(+) create mode 100644 ports/stm/boards/STM32F412CGUx_FLASH.ld create mode 100644 ports/stm/boards/startup_stm32f412cx_thunderpack.s create mode 100644 ports/stm/boards/thunderpack/board.c create mode 100644 ports/stm/boards/thunderpack/mpconfigboard.h create mode 100644 ports/stm/boards/thunderpack/mpconfigboard.mk create mode 100644 ports/stm/boards/thunderpack/pins.c create mode 100644 ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h create mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.h create mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c create mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h (limited to 'ports/stm') diff --git a/ports/stm/boards/STM32F412CGUx_FLASH.ld b/ports/stm/boards/STM32F412CGUx_FLASH.ld new file mode 100644 index 000000000..c394b8646 --- /dev/null +++ b/ports/stm/boards/STM32F412CGUx_FLASH.ld @@ -0,0 +1,189 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by System Workbench for STM32 +** +** Abstract : Linker script for STM32F412CGUx series +** 1024Kbytes FLASH and 256Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20040000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/ports/stm/boards/startup_stm32f412cx_thunderpack.s b/ports/stm/boards/startup_stm32f412cx_thunderpack.s new file mode 100644 index 000000000..1c344ec08 --- /dev/null +++ b/ports/stm/boards/startup_stm32f412cx_thunderpack.s @@ -0,0 +1,521 @@ +/** + ****************************************************************************** + * @file startup_stm32f412Cx.s + * @author MCD Application Team + * @brief STM32F412Cx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ +/* bl __libc_init_array */ +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/boards/thunderpack/board.c b/ports/stm/boards/thunderpack/board.c new file mode 100644 index 000000000..4421970ee --- /dev/null +++ b/ports/stm/boards/thunderpack/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" + +void board_init(void) { +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { + +} diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h new file mode 100644 index 000000000..e37408928 --- /dev/null +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -0,0 +1,37 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +//Micropython setup +#define MICROPY_HW_BOARD_NAME "THUNDERPACK" +#define MICROPY_HW_MCU_NAME "STM32F412xGU" + +#define FLASH_SIZE (0x100000) +#define FLASH_PAGE_SIZE (0x4000) + +#define BOARD_OSC_DIV (24) +#define BOARD_NO_VBUS_SENSE (1) + +#define DEFAULT_I2C_BUS_SCL (&pin_PB06) +#define DEFAULT_I2C_BUS_SDA (&pin_PB07) diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk new file mode 100644 index 000000000..a5febd580 --- /dev/null +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -0,0 +1,22 @@ +USB_VID = 0x0483 +USB_PID = 0xdf11 +USB_PRODUCT = "Thunderpack" +USB_MANUFACTURER = "Jeremy Gillick" +USB_DEVICES = "CDC,MSC,HID" + +INTERNAL_FLASH_FILESYSTEM = 1 +LONGINT_IMPL = NONE + +# QSPI_FLASH_FILESYSTEM = 1 +# EXTERNAL_FLASH_DEVICE_COUNT = 1 +# EXTERNAL_FLASH_DEVICES = N25Q128A +# LONGINT_IMPL = MPZ + +MCU_SERIES = m4 +MCU_VARIANT = stm32f4 +MCU_SUB_VARIANT = stm32f412cx_thunderpack +MCU_PACKAGE = 48 +CMSIS_MCU = STM32F412Zx +LD_FILE = boards/STM32F412CGUx_FLASH.ld + + diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c new file mode 100644 index 000000000..db0b3cde1 --- /dev/null +++ b/ports/stm/boards/thunderpack/pins.c @@ -0,0 +1,95 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { + // { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + // { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + // { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + // { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + // { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + // { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, + // { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, + // { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, + // { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + // { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + // { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + // { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + // { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + // { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + // { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + // { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + // { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, + // { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, + // { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + // { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + // { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + // { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + // { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + // { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + // { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + // { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + // { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, + // { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + // { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + // { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + // { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + // { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + // { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, + // { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, + // { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, + // { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, + // { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, + // { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, + // { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + // { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + // { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + // { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + // { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB10) }, + // { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, + // { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA15) }, + // { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB08) }, + // { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PG10) }, + // { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PG11) }, + // { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PF03) }, + // { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PF10) }, + // { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG12) }, + // { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PF04) }, + // { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG13) }, + // { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, //USART6 TX + // { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, //USART6 RX + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA01) }, + // { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC01) }, + // { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, + // { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC04) }, + // { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC05) }, //alt PB09, see F401ZG-DISCO manual + // { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB00) }, //alt PB10, see F401ZG-DISCO manual + + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PA03) }, + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h b/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h new file mode 100644 index 000000000..530c7e605 --- /dev/null +++ b/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h @@ -0,0 +1,442 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +#define HAL_SRAM_MODULE_ENABLED +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +#define HAL_QSPI_MODULE_ENABLED +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)24000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c new file mode 100644 index 000000000..0f2537df8 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c @@ -0,0 +1,77 @@ + +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "stm32f4xx_hal.h" +#include "py/mpconfig.h" + +void stm32f4_peripherals_clocks_init(void) { + //System clock init + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the + * device is clocked below the maximum system frequency, to update the + * voltage scaling value regarding system frequency refer to product + * datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; + RCC_OscInitStruct.PLL.PLLN = 200; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PLLI2S.PLLI2SM = 12; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 3; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 72; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + * clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); +} diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c new file mode 100644 index 000000000..8f47ba319 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c @@ -0,0 +1,242 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* GPIO PIN REFERENCE +#define LED3_Pin GPIO_PIN_2 +#define LED3_GPIO_Port GPIOE +#define LED4_Pin GPIO_PIN_3 +#define LED4_GPIO_Port GPIOE +#define DFSDM_DATIN3_Pin GPIO_PIN_4 +#define DFSDM_DATIN3_GPIO_Port GPIOE +#define A0_Pin GPIO_PIN_0 +#define A0_GPIO_Port GPIOF +#define LCD_BLCTRL_Pin GPIO_PIN_5 +#define LCD_BLCTRL_GPIO_Port GPIOF +#define QSPI_BK1_IO3_Pin GPIO_PIN_6 +#define QSPI_BK1_IO3_GPIO_Port GPIOF +#define QSPI_BK1_IO2_Pin GPIO_PIN_7 +#define QSPI_BK1_IO2_GPIO_Port GPIOF +#define QSPI_BK1_IO0_Pin GPIO_PIN_8 +#define QSPI_BK1_IO0_GPIO_Port GPIOF +#define QSPI_BK1_IO1_Pin GPIO_PIN_9 +#define QSPI_BK1_IO1_GPIO_Port GPIOF +#define STLK_MCO_Pin GPIO_PIN_0 +#define STLK_MCO_GPIO_Port GPIOH +#define DFSDM_CKOUT_Pin GPIO_PIN_2 +#define DFSDM_CKOUT_GPIO_Port GPIOC +#define JOY_SEL_Pin GPIO_PIN_0 +#define JOY_SEL_GPIO_Port GPIOA +#define STLINK_RX_Pin GPIO_PIN_2 +#define STLINK_RX_GPIO_Port GPIOA +#define STLINK_TX_Pin GPIO_PIN_3 +#define STLINK_TX_GPIO_Port GPIOA +#define CODEC_I2S3_WS_Pin GPIO_PIN_4 +#define CODEC_I2S3_WS_GPIO_Port GPIOA +#define DFSDM_DATIN0_Pin GPIO_PIN_1 +#define DFSDM_DATIN0_GPIO_Port GPIOB +#define QSPI_CLK_Pin GPIO_PIN_2 +#define QSPI_CLK_GPIO_Port GPIOB +#define EXT_RESET_Pin GPIO_PIN_11 +#define EXT_RESET_GPIO_Port GPIOF +#define CTP_RST_Pin GPIO_PIN_12 +#define CTP_RST_GPIO_Port GPIOF +#define JOY_RIGHT_Pin GPIO_PIN_14 +#define JOY_RIGHT_GPIO_Port GPIOF +#define JOY_LEFT_Pin GPIO_PIN_15 +#define JOY_LEFT_GPIO_Port GPIOF +#define JOY_UP_Pin GPIO_PIN_0 +#define JOY_UP_GPIO_Port GPIOG +#define JOY_DOWN_Pin GPIO_PIN_1 +#define JOY_DOWN_GPIO_Port GPIOG +#define D4_Pin GPIO_PIN_7 +#define D4_GPIO_Port GPIOE +#define D5_Pin GPIO_PIN_8 +#define D5_GPIO_Port GPIOE +#define D6_Pin GPIO_PIN_9 +#define D6_GPIO_Port GPIOE +#define D7_Pin GPIO_PIN_10 +#define D7_GPIO_Port GPIOE +#define D8_Pin GPIO_PIN_11 +#define D8_GPIO_Port GPIOE +#define D9_Pin GPIO_PIN_12 +#define D9_GPIO_Port GPIOE +#define D10_Pin GPIO_PIN_13 +#define D10_GPIO_Port GPIOE +#define D11_Pin GPIO_PIN_14 +#define D11_GPIO_Port GPIOE +#define D12_Pin GPIO_PIN_15 +#define D12_GPIO_Port GPIOE +#define I2C2_SCL_Pin GPIO_PIN_10 +#define I2C2_SCL_GPIO_Port GPIOB +#define M2_CKIN_Pin GPIO_PIN_11 +#define M2_CKIN_GPIO_Port GPIOB +#define CODEC_I2S3_SCK_Pin GPIO_PIN_12 +#define CODEC_I2S3_SCK_GPIO_Port GPIOB +#define D13_Pin GPIO_PIN_8 +#define D13_GPIO_Port GPIOD +#define D14_Pin GPIO_PIN_9 +#define D14_GPIO_Port GPIOD +#define D15_Pin GPIO_PIN_10 +#define D15_GPIO_Port GPIOD +#define LCD_RESET_Pin GPIO_PIN_11 +#define LCD_RESET_GPIO_Port GPIOD +#define D0_Pin GPIO_PIN_14 +#define D0_GPIO_Port GPIOD +#define D1_Pin GPIO_PIN_15 +#define D1_GPIO_Port GPIOD +#define CODEC_INT_Pin GPIO_PIN_2 +#define CODEC_INT_GPIO_Port GPIOG +#define LCD_TE_Pin GPIO_PIN_4 +#define LCD_TE_GPIO_Port GPIOG +#define CTP_INT_Pin GPIO_PIN_5 +#define CTP_INT_GPIO_Port GPIOG +#define QSPI_BK1_NCS_Pin GPIO_PIN_6 +#define QSPI_BK1_NCS_GPIO_Port GPIOG +#define USB_OTGFS_OVRCR_Pin GPIO_PIN_7 +#define USB_OTGFS_OVRCR_GPIO_Port GPIOG +#define USB_OTGFS_PPWR_EN_Pin GPIO_PIN_8 +#define USB_OTGFS_PPWR_EN_GPIO_Port GPIOG +#define CODEC_I2S3_MCK_Pin GPIO_PIN_7 +#define CODEC_I2S3_MCK_GPIO_Port GPIOC +#define uSD_D0_Pin GPIO_PIN_8 +#define uSD_D0_GPIO_Port GPIOC +#define uSD_D1_Pin GPIO_PIN_9 +#define uSD_D1_GPIO_Port GPIOC +#define M2_CKINA8_Pin GPIO_PIN_8 +#define M2_CKINA8_GPIO_Port GPIOA +#define USB_OTGFS_VBUS_Pin GPIO_PIN_9 +#define USB_OTGFS_VBUS_GPIO_Port GPIOA +#define USB_OTGFS_ID_Pin GPIO_PIN_10 +#define USB_OTGFS_ID_GPIO_Port GPIOA +#define USB_OTGFS_DM_Pin GPIO_PIN_11 +#define USB_OTGFS_DM_GPIO_Port GPIOA +#define USB_OTGFS_DP_Pin GPIO_PIN_12 +#define USB_OTGFS_DP_GPIO_Port GPIOA +#define SWDIO_Pin GPIO_PIN_13 +#define SWDIO_GPIO_Port GPIOA +#define SWCLK_Pin GPIO_PIN_14 +#define SWCLK_GPIO_Port GPIOA +#define uSD_D2_Pin GPIO_PIN_10 +#define uSD_D2_GPIO_Port GPIOC +#define uSD_D3_Pin GPIO_PIN_11 +#define uSD_D3_GPIO_Port GPIOC +#define uSD_CLK_Pin GPIO_PIN_12 +#define uSD_CLK_GPIO_Port GPIOC +#define D2_Pin GPIO_PIN_0 +#define D2_GPIO_Port GPIOD +#define D3_Pin GPIO_PIN_1 +#define D3_GPIO_Port GPIOD +#define uSD_CMD_Pin GPIO_PIN_2 +#define uSD_CMD_GPIO_Port GPIOD +#define uSD_DETECT_Pin GPIO_PIN_3 +#define uSD_DETECT_GPIO_Port GPIOD +#define FMC_NOE_Pin GPIO_PIN_4 +#define FMC_NOE_GPIO_Port GPIOD +#define FMC_NWE_Pin GPIO_PIN_5 +#define FMC_NWE_GPIO_Port GPIOD +#define FMC_NE1_Pin GPIO_PIN_7 +#define FMC_NE1_GPIO_Port GPIOD +#define SWO_Pin GPIO_PIN_3 +#define SWO_GPIO_Port GPIOB +#define CODEC_I2S3ext_SD_Pin GPIO_PIN_4 +#define CODEC_I2S3ext_SD_GPIO_Port GPIOB +#define CODEC_I2S3_SD_Pin GPIO_PIN_5 +#define CODEC_I2S3_SD_GPIO_Port GPIOB +#define I2C1_SCL_Pin GPIO_PIN_6 +#define I2C1_SCL_GPIO_Port GPIOB +#define I2C1_SDA_Pin GPIO_PIN_7 +#define I2C1_SDA_GPIO_Port GPIOB +#define I2C2_SDA_Pin GPIO_PIN_9 +#define I2C2_SDA_GPIO_Port GPIOB +#define LED1_Pin GPIO_PIN_0 +#define LED1_GPIO_Port GPIOE +#define LED2_Pin GPIO_PIN_1 +#define LED2_GPIO_Port GPIOE +*/ + +#include "stm32f4xx_hal.h" +#include "stm32f4/gpio.h" +#include "common-hal/microcontroller/Pin.h" + +void stm32f4_peripherals_gpio_init(void) { + //Enable all GPIO for now + GPIO_InitTypeDef GPIO_InitStruct = {0}; + // __HAL_RCC_GPIOE_CLK_ENABLE(); + // __HAL_RCC_GPIOC_CLK_ENABLE(); + // __HAL_RCC_GPIOF_CLK_ENABLE(); + // __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + // __HAL_RCC_GPIOG_CLK_ENABLE(); + // __HAL_RCC_GPIOD_CLK_ENABLE(); + + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET); + //HAL_GPIO_WritePin(USB_OTGFS_PPWR_EN_GPIO_Port, USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_SET); + + //Configure LED pins + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + //Status LED chain + stm32f4_peripherals_status_led(0,1); + stm32f4_peripherals_status_led(1,1); + stm32f4_peripherals_status_led(2,1); + stm32f4_peripherals_status_led(3,1); + + //Never reset pins + // never_reset_pin_number(2,13); //PC13 anti tamp + // never_reset_pin_number(2,14); //PC14 OSC32_IN + // never_reset_pin_number(2,15); //PC15 OSC32_OUT + never_reset_pin_number(0,13); //PA13 SWDIO + never_reset_pin_number(0,14); //PA14 SWCLK + //never_reset_pin_number(0,15); //PA15 JTDI + //never_reset_pin_number(1,3); //PB3 JTDO + //never_reset_pin_number(1,4); //PB4 JTRST + + // Port H is not included in GPIO port array + // never_reset_pin_number(5,0); //PH0 JTDO + // never_reset_pin_number(5,1); //PH1 JTRST +} + +void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { + switch(led) + { + case 0: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, state); + break; + case 1: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, state); + break; + case 2: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, state); + break; + case 3: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, state); + break; + default: break; + } +} + + diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c new file mode 100644 index 000000000..aa9d7abf5 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c @@ -0,0 +1,107 @@ + /* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "stm32f4/pins.h" +#include "stm32f4/periph.h" + +// I2C + +I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, NULL, NULL}; + +const mcu_i2c_sda_obj_t mcu_i2c_sda_list[8] = { + I2C_SDA(1, 4, &pin_PB07), +}; + +const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = { + I2C_SCL(1, 4, &pin_PB06), +}; + +// SPI + +SPI_TypeDef * mcu_spi_banks[5] = {SPI1, NULL, NULL, NULL, NULL}; + +const mcu_spi_sck_obj_t mcu_spi_sck_list[15] = { + SPI(1, 5, &pin_PA05), +}; + +const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14] = { + SPI(1, 5, &pin_PA07), + SPI(1, 5, &pin_PB05), +}; + +const mcu_spi_miso_obj_t mcu_spi_miso_list[12] = { + SPI(1, 5, &pin_PA06), +}; + +const mcu_spi_nss_obj_t mcu_spi_nss_list[12] = { + SPI(1, 5, &pin_PA04), +}; + +//UART + +USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, NULL, NULL, NULL, NULL, NULL}; +bool mcu_uart_has_usart[MAX_UART] = {true, false, false, false, false, false}; + +const mcu_uart_tx_obj_t mcu_uart_tx_list[11] = { + UART(1, 7, &pin_PA09), + UART(1, 7, &pin_PB06), +}; + +const mcu_uart_rx_obj_t mcu_uart_rx_list[12] = { + UART(1, 7, &pin_PA10), + UART(1, 7, &pin_PB07), +}; + +//Timers +//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, NULL, + NULL, NULL, TIM13, TIM14}; + +const mcu_tim_pin_obj_t mcu_tim_pin_list[60] = { + TIM(2,1,1,&pin_PA00), + TIM(5,2,1,&pin_PA00), + TIM(2,1,2,&pin_PA01), + TIM(5,2,2,&pin_PA01), + TIM(2,1,3,&pin_PA02), + TIM(5,2,3,&pin_PA02), + TIM(2,1,4,&pin_PA03), + TIM(5,2,4,&pin_PA03), + TIM(9,3,1,&pin_PA02), + TIM(9,3,2,&pin_PA03), + TIM(3,2,1,&pin_PA06), + TIM(13,9,1,&pin_PA06), + TIM(3,2,2,&pin_PA07), + TIM(14,9,1,&pin_PA07), + TIM(1,1,1,&pin_PA08), + TIM(1,1,2,&pin_PA09), + TIM(1,1,3,&pin_PA10), + TIM(1,1,4,&pin_PA11), + TIM(3,2,2,&pin_PB05), + TIM(4,2,1,&pin_PB06), + TIM(4,2,2,&pin_PB07), +}; diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.h b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.h new file mode 100644 index 000000000..e0141e6da --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.h @@ -0,0 +1,58 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H +#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H + +//I2C +extern I2C_TypeDef * mcu_i2c_banks[3]; + +extern const mcu_i2c_sda_obj_t mcu_i2c_sda_list[8]; +extern const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4]; + + +//SPI +extern SPI_TypeDef * mcu_spi_banks[5]; + +extern const mcu_spi_sck_obj_t mcu_spi_sck_list[15]; +extern const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14]; +extern const mcu_spi_miso_obj_t mcu_spi_miso_list[12]; +extern const mcu_spi_nss_obj_t mcu_spi_nss_list[12]; + +//UART +extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +extern bool mcu_uart_has_usart[MAX_UART]; + +extern const mcu_uart_tx_obj_t mcu_uart_tx_list[11]; +extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12]; + +//Timers +#define TIM_BANK_ARRAY_LEN 14 +#define TIM_PIN_ARRAY_LEN 60 +TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; + +#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c new file mode 100644 index 000000000..c56de5a29 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c @@ -0,0 +1,161 @@ + /* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "stm32f4/pins.h" + +const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); +const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); +const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); +const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); +const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); + +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT + +const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10)); +const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11)); +const mcu_pin_obj_t pin_PC02 = PIN(2, 2, ADC_INPUT(ADC_1,12)); +const mcu_pin_obj_t pin_PC03 = PIN(2, 3, ADC_INPUT(ADC_1,13)); + +const mcu_pin_obj_t pin_PA00 = PIN(0, 0, ADC_INPUT(ADC_1,0)); +const mcu_pin_obj_t pin_PA01 = PIN(0, 1, ADC_INPUT(ADC_1,1)); +const mcu_pin_obj_t pin_PA02 = PIN(0, 2, ADC_INPUT(ADC_1,2)); +const mcu_pin_obj_t pin_PA03 = PIN(0, 3, ADC_INPUT(ADC_1,3)); +const mcu_pin_obj_t pin_PA04 = PIN(0, 4, ADC_INPUT(ADC_1,4)); +const mcu_pin_obj_t pin_PA05 = PIN(0, 5, ADC_INPUT(ADC_1,5)); +const mcu_pin_obj_t pin_PA06 = PIN(0, 6, ADC_INPUT(ADC_1,6)); +const mcu_pin_obj_t pin_PA07 = PIN(0, 7, ADC_INPUT(ADC_1,7)); + +const mcu_pin_obj_t pin_PC04 = PIN(2, 4, ADC_INPUT(ADC_1,14)); +const mcu_pin_obj_t pin_PC05 = PIN(2, 5, ADC_INPUT(ADC_1,15)); + +const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_1,8)); +const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_1,9)); +const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); + +const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); +const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); +const mcu_pin_obj_t pin_PE09 = PIN(4, 9, NO_ADC); +const mcu_pin_obj_t pin_PE10 = PIN(4, 10, NO_ADC); +const mcu_pin_obj_t pin_PE11 = PIN(4, 11, NO_ADC); +const mcu_pin_obj_t pin_PE12 = PIN(4, 12, NO_ADC); +const mcu_pin_obj_t pin_PE13 = PIN(4, 13, NO_ADC); +const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC); +const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC); + +const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); +const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); +const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); +const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); +const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC); + +const mcu_pin_obj_t pin_PD08 = PIN(3, 8, NO_ADC); +const mcu_pin_obj_t pin_PD09 = PIN(3, 9, NO_ADC); +const mcu_pin_obj_t pin_PD10 = PIN(3, 10, NO_ADC); +const mcu_pin_obj_t pin_PD11 = PIN(3, 11, NO_ADC); +const mcu_pin_obj_t pin_PD12 = PIN(3, 12, NO_ADC); +const mcu_pin_obj_t pin_PD13 = PIN(3, 13, NO_ADC); +const mcu_pin_obj_t pin_PD14 = PIN(3, 14, NO_ADC); +const mcu_pin_obj_t pin_PD15 = PIN(3, 15, NO_ADC); + +const mcu_pin_obj_t pin_PG02 = PIN(6, 2, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG03 = PIN(6, 3, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG04 = PIN(6, 4, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG05 = PIN(6, 5, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG06 = PIN(6, 6, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG07 = PIN(6, 7, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG08 = PIN(6, 8, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PC06 = PIN(2, 6, NO_ADC); +const mcu_pin_obj_t pin_PC07 = PIN(2, 7, NO_ADC); +const mcu_pin_obj_t pin_PC08 = PIN(2, 8, NO_ADC); +const mcu_pin_obj_t pin_PC09 = PIN(2, 9, NO_ADC); + +const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC); +const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); +const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); +const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); +const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); +const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); +const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); +const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); + +const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC); +const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC); +const mcu_pin_obj_t pin_PC12 = PIN(2, 12, NO_ADC); + +const mcu_pin_obj_t pin_PD00 = PIN(3, 0, NO_ADC); +const mcu_pin_obj_t pin_PD01 = PIN(3, 1, NO_ADC); +const mcu_pin_obj_t pin_PD02 = PIN(3, 2, NO_ADC); +const mcu_pin_obj_t pin_PD03 = PIN(3, 3, NO_ADC); +const mcu_pin_obj_t pin_PD04 = PIN(3, 4, NO_ADC); +const mcu_pin_obj_t pin_PD05 = PIN(3, 5, NO_ADC); +const mcu_pin_obj_t pin_PD06 = PIN(3, 6, NO_ADC); +const mcu_pin_obj_t pin_PD07 = PIN(3, 7, NO_ADC); + +const mcu_pin_obj_t pin_PG09 = PIN(6, 9, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG10 = PIN(6, 10, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG11 = PIN(6, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG12 = PIN(6, 12, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG13 = PIN(6, 13, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG14 = PIN(6, 14, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG15 = PIN(6, 15, NO_ADC); // 144 only + +const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC); +const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC); +const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC); +const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC); +const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC); +const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); +const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); + +const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC); +const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h new file mode 100644 index 000000000..180f5c316 --- /dev/null +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h @@ -0,0 +1,158 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H +#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H + +//Pins in datasheet order: DocID028087 Rev 7 page 50. LQFP100 only +//pg 50 +extern const mcu_pin_obj_t pin_PE02; +extern const mcu_pin_obj_t pin_PE03; +extern const mcu_pin_obj_t pin_PE04; +extern const mcu_pin_obj_t pin_PE05; +extern const mcu_pin_obj_t pin_PE06; +extern const mcu_pin_obj_t pin_PC13; +extern const mcu_pin_obj_t pin_PC14; +//pg 51 +extern const mcu_pin_obj_t pin_PC15; +extern const mcu_pin_obj_t pin_PF00; // 144 only +extern const mcu_pin_obj_t pin_PF01; // 144 only +extern const mcu_pin_obj_t pin_PF02; // 144 only +extern const mcu_pin_obj_t pin_PF03; // 144 only +extern const mcu_pin_obj_t pin_PF04; // 144 only +extern const mcu_pin_obj_t pin_PF05; // 144 only +extern const mcu_pin_obj_t pin_PF06; // 144 only +extern const mcu_pin_obj_t pin_PF07; // 144 only +extern const mcu_pin_obj_t pin_PF08; // 144 only +extern const mcu_pin_obj_t pin_PF09; // 144 only +extern const mcu_pin_obj_t pin_PF10; // 144 only +//pg 52 +extern const mcu_pin_obj_t pin_PC00; +extern const mcu_pin_obj_t pin_PC01; +extern const mcu_pin_obj_t pin_PC02; +extern const mcu_pin_obj_t pin_PC03; +extern const mcu_pin_obj_t pin_PA00; +extern const mcu_pin_obj_t pin_PA01; +extern const mcu_pin_obj_t pin_PA02; +//pg 53 +extern const mcu_pin_obj_t pin_PA03; +extern const mcu_pin_obj_t pin_PA04; +extern const mcu_pin_obj_t pin_PA05; +extern const mcu_pin_obj_t pin_PA06; +extern const mcu_pin_obj_t pin_PA07; +extern const mcu_pin_obj_t pin_PC04; +//pg 54 +extern const mcu_pin_obj_t pin_PC05; +extern const mcu_pin_obj_t pin_PB00; +extern const mcu_pin_obj_t pin_PB01; +extern const mcu_pin_obj_t pin_PB02; +extern const mcu_pin_obj_t pin_PF11; // 144 only +extern const mcu_pin_obj_t pin_PF12; // 144 only +extern const mcu_pin_obj_t pin_PF13; // 144 only +extern const mcu_pin_obj_t pin_PF14; // 144 only +extern const mcu_pin_obj_t pin_PF15; // 144 only +extern const mcu_pin_obj_t pin_PG00; // 144 only +extern const mcu_pin_obj_t pin_PG01; // 144 only +//pg 55 +extern const mcu_pin_obj_t pin_PE07; +extern const mcu_pin_obj_t pin_PE08; +extern const mcu_pin_obj_t pin_PE09; +extern const mcu_pin_obj_t pin_PE10; +extern const mcu_pin_obj_t pin_PE11; +extern const mcu_pin_obj_t pin_PE12; +extern const mcu_pin_obj_t pin_PE13; +extern const mcu_pin_obj_t pin_PE14; +//pg 56 +extern const mcu_pin_obj_t pin_PE15; +extern const mcu_pin_obj_t pin_PB10; +extern const mcu_pin_obj_t pin_PB11; // 144 only +extern const mcu_pin_obj_t pin_PB12; +extern const mcu_pin_obj_t pin_PB13; +//pg 57 +extern const mcu_pin_obj_t pin_PB14; +extern const mcu_pin_obj_t pin_PB15; +extern const mcu_pin_obj_t pin_PD08; +extern const mcu_pin_obj_t pin_PD09; +extern const mcu_pin_obj_t pin_PD10; +extern const mcu_pin_obj_t pin_PD11; +extern const mcu_pin_obj_t pin_PD12; +//pg 58 +extern const mcu_pin_obj_t pin_PD13; +extern const mcu_pin_obj_t pin_PD14; +extern const mcu_pin_obj_t pin_PD15; +extern const mcu_pin_obj_t pin_PG02; // 144 only +extern const mcu_pin_obj_t pin_PG03; // 144 only +extern const mcu_pin_obj_t pin_PG04; // 144 only +extern const mcu_pin_obj_t pin_PG05; // 144 only +extern const mcu_pin_obj_t pin_PG06; // 144 only +extern const mcu_pin_obj_t pin_PG07; // 144 only +extern const mcu_pin_obj_t pin_PG08; // 144 only +//pg 59 +extern const mcu_pin_obj_t pin_PC06; +extern const mcu_pin_obj_t pin_PC07; +extern const mcu_pin_obj_t pin_PC08; +extern const mcu_pin_obj_t pin_PC09; +extern const mcu_pin_obj_t pin_PA08; +extern const mcu_pin_obj_t pin_PA09; +extern const mcu_pin_obj_t pin_PA10; +//pg 60 +extern const mcu_pin_obj_t pin_PA11; +extern const mcu_pin_obj_t pin_PA12; +extern const mcu_pin_obj_t pin_PA13; +extern const mcu_pin_obj_t pin_PA14; +extern const mcu_pin_obj_t pin_PA15; +extern const mcu_pin_obj_t pin_PC10; +extern const mcu_pin_obj_t pin_PC11; +//pg 61 +extern const mcu_pin_obj_t pin_PC12; +extern const mcu_pin_obj_t pin_PD00; +extern const mcu_pin_obj_t pin_PD01; +extern const mcu_pin_obj_t pin_PD02; +extern const mcu_pin_obj_t pin_PD03; +extern const mcu_pin_obj_t pin_PD04; +extern const mcu_pin_obj_t pin_PD05; +extern const mcu_pin_obj_t pin_PD06; +extern const mcu_pin_obj_t pin_PD07; +//pg 62 +extern const mcu_pin_obj_t pin_PG09; // 144 only +extern const mcu_pin_obj_t pin_PG10; // 144 only +extern const mcu_pin_obj_t pin_PG11; // 144 only +extern const mcu_pin_obj_t pin_PG12; // 144 only +extern const mcu_pin_obj_t pin_PG13; // 144 only +extern const mcu_pin_obj_t pin_PG14; // 144 only +extern const mcu_pin_obj_t pin_PG15; // 144 only +extern const mcu_pin_obj_t pin_PB03; +extern const mcu_pin_obj_t pin_PB04; +//pg 63 +extern const mcu_pin_obj_t pin_PB05; +extern const mcu_pin_obj_t pin_PB06; +extern const mcu_pin_obj_t pin_PB07; +extern const mcu_pin_obj_t pin_PB08; +extern const mcu_pin_obj_t pin_PB09; +extern const mcu_pin_obj_t pin_PE00; +extern const mcu_pin_obj_t pin_PE01; + +#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H -- cgit v1.2.3 From f884c2b9b68baba4031f7cc95aa04d01fed218bf Mon Sep 17 00:00:00 2001 From: jgillick Date: Sun, 15 Mar 2020 19:34:41 -0700 Subject: Incremental update --- ports/stm/boards/STM32F412CGUx_FLASH.ld | 189 ------------- ports/stm/boards/thunderpack/mpconfigboard.h | 10 +- ports/stm/boards/thunderpack/mpconfigboard.mk | 9 +- ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h | 2 +- ports/stm/peripherals/stm32f4/pins.h | 11 +- .../stm32f4/stm32f412cx_thunderpack/clocks.c | 14 +- .../stm32f4/stm32f412cx_thunderpack/gpio.c | 89 +++--- ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 10 +- ports/stm/supervisor/internal_flash.h | 2 +- ports/stm/system_stm32f4xx.c | 308 +++++++++++---------- 10 files changed, 225 insertions(+), 419 deletions(-) delete mode 100644 ports/stm/boards/STM32F412CGUx_FLASH.ld (limited to 'ports/stm') diff --git a/ports/stm/boards/STM32F412CGUx_FLASH.ld b/ports/stm/boards/STM32F412CGUx_FLASH.ld deleted file mode 100644 index c394b8646..000000000 --- a/ports/stm/boards/STM32F412CGUx_FLASH.ld +++ /dev/null @@ -1,189 +0,0 @@ -/* -****************************************************************************** -** - -** File : LinkerScript.ld -** -** Author : Auto-generated by System Workbench for STM32 -** -** Abstract : Linker script for STM32F412CGUx series -** 1024Kbytes FLASH and 256Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed “as is,” without any warranty -** of any kind. -** -***************************************************************************** -** @attention -** -**

© COPYRIGHT(c) 2019 STMicroelectronics

-** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of STMicroelectronics nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20040000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h index e37408928..18977c131 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.h +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -23,7 +23,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -//Micropython setup +#define BOARD_THUNDERPACK_STM32F412 #define MICROPY_HW_BOARD_NAME "THUNDERPACK" #define MICROPY_HW_MCU_NAME "STM32F412xGU" @@ -33,5 +33,11 @@ #define BOARD_OSC_DIV (24) #define BOARD_NO_VBUS_SENSE (1) +#define CP_RGB_STATUS_LED +#define CP_RGB_STATUS_R (&pin_PA00) +#define CP_RGB_STATUS_G (&pin_PA01) +#define CP_RGB_STATUS_B (&pin_PA02) +#define MICROPY_HW_LED_STATUS (&pin_PA03) + #define DEFAULT_I2C_BUS_SCL (&pin_PB06) -#define DEFAULT_I2C_BUS_SDA (&pin_PB07) +#define DEFAULT_I2C_BUS_SDA (&pin_PB07) \ No newline at end of file diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index a5febd580..9827b9e06 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -7,16 +7,11 @@ USB_DEVICES = "CDC,MSC,HID" INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = NONE -# QSPI_FLASH_FILESYSTEM = 1 -# EXTERNAL_FLASH_DEVICE_COUNT = 1 -# EXTERNAL_FLASH_DEVICES = N25Q128A -# LONGINT_IMPL = MPZ - MCU_SERIES = m4 MCU_VARIANT = stm32f4 MCU_SUB_VARIANT = stm32f412cx_thunderpack MCU_PACKAGE = 48 -CMSIS_MCU = STM32F412Zx -LD_FILE = boards/STM32F412CGUx_FLASH.ld +CMSIS_MCU = STM32F412Cx +LD_FILE = boards/STM32F412ZGTx_FLASH.ld diff --git a/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h b/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h index 530c7e605..15162dfcc 100644 --- a/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h +++ b/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h @@ -70,7 +70,7 @@ #define HAL_PCD_MODULE_ENABLED /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_QSPI_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ /* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */ diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h index 44ef4c1ba..7e8baf89d 100644 --- a/ports/stm/peripherals/stm32f4/pins.h +++ b/ports/stm/peripherals/stm32f4/pins.h @@ -40,7 +40,7 @@ typedef struct { mp_obj_base_t base; uint8_t port:4; uint8_t number:4; - uint8_t adc_unit:3; + uint8_t adc_unit:3; uint8_t adc_channel:5; } mcu_pin_obj_t; @@ -51,8 +51,8 @@ typedef struct { #define ADC_3 4 //STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin, -//but all 3 ADCs will share the same input number per pin. -//F4 family has 3 ADC max, 24 channels max. +//but all 3 ADCs will share the same input number per pin. +//F4 family has 3 ADC max, 24 channels max. #define ADC_INPUT(mask, number) \ .adc_unit = mask, \ .adc_channel = number, @@ -64,7 +64,7 @@ typedef struct { extern const mp_obj_type_t mcu_pin_type; // STM32 can have up to 9 ports, each restricted to 16 pins -// We split the pin/port evenly, in contrast to nrf. +// We split the pin/port evenly, in contrast to nrf. #define PIN(p_port, p_number, p_adc) \ { \ { &mcu_pin_type }, \ @@ -83,6 +83,9 @@ extern const mp_obj_type_t mcu_pin_type; #ifdef STM32F411xE #include "stm32f411xe/pins.h" #endif +#ifdef BOARD_THUNDERPACK_STM32F412 +#include "stm32f412cx_thunderpack/pins.h" +#endif #ifdef STM32F412Zx #include "stm32f412zx/pins.h" #endif diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c index 0f2537df8..3e2766516 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c @@ -47,8 +47,8 @@ void stm32f4_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; - RCC_OscInitStruct.PLL.PLLN = 200; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 100; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 7; RCC_OscInitStruct.PLL.PLLR = 2; @@ -57,18 +57,16 @@ void stm32f4_peripherals_clocks_init(void) { /* Select PLLSAI output as USB clock source */ PeriphClkInitStruct.PLLI2S.PLLI2SM = 12; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 3; - PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.PLLI2S.PLLI2SN = 72; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 * clocks dividers */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | - RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c index 8f47ba319..7172a2520 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c @@ -182,61 +182,52 @@ #include "common-hal/microcontroller/Pin.h" void stm32f4_peripherals_gpio_init(void) { - //Enable all GPIO for now - GPIO_InitTypeDef GPIO_InitStruct = {0}; - // __HAL_RCC_GPIOE_CLK_ENABLE(); - // __HAL_RCC_GPIOC_CLK_ENABLE(); - // __HAL_RCC_GPIOF_CLK_ENABLE(); - // __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - // __HAL_RCC_GPIOG_CLK_ENABLE(); - // __HAL_RCC_GPIOD_CLK_ENABLE(); + //Enable all GPIO for now + GPIO_InitTypeDef GPIO_InitStruct = {0}; + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET); - //HAL_GPIO_WritePin(USB_OTGFS_PPWR_EN_GPIO_Port, USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_SET); + //Configure LED pins + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET); + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - //Configure LED pins - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + //Status LED chain + stm32f4_peripherals_status_led(0,1); + stm32f4_peripherals_status_led(1,0); + stm32f4_peripherals_status_led(2,0); + stm32f4_peripherals_status_led(3,0); - //Status LED chain - stm32f4_peripherals_status_led(0,1); - stm32f4_peripherals_status_led(1,1); - stm32f4_peripherals_status_led(2,1); - stm32f4_peripherals_status_led(3,1); - - //Never reset pins - // never_reset_pin_number(2,13); //PC13 anti tamp - // never_reset_pin_number(2,14); //PC14 OSC32_IN - // never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK - //never_reset_pin_number(0,15); //PA15 JTDI - //never_reset_pin_number(1,3); //PB3 JTDO - //never_reset_pin_number(1,4); //PB4 JTRST - - // Port H is not included in GPIO port array - // never_reset_pin_number(5,0); //PH0 JTDO - // never_reset_pin_number(5,1); //PH1 JTRST + //Never reset pins + never_reset_pin_number(2,13); //PC13 anti tamp + never_reset_pin_number(2,14); //PC14 OSC32_IN + never_reset_pin_number(2,15); //PC15 OSC32_OUT + never_reset_pin_number(0,13); //PA13 SWDIO + never_reset_pin_number(0,14); //PA14 SWCLK } void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { - switch(led) - { - case 0: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, state); - break; - case 1: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, state); - break; - case 2: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, state); - break; - case 3: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, state); - break; - default: break; - } + switch(led) + { + case 0: + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, state); + break; + case 1: + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, state); + break; + case 2: + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, state); + break; + case 3: + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, state); + break; + default: break; + } } diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index d17ab4e01..4ec6b107f 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -220,7 +220,7 @@ void stm32f4_peripherals_gpio_init(void) { //never_reset_pin_number(1,4); //PB4 JTRST // Port H is not included in GPIO port array - // never_reset_pin_number(5,0); //PH0 JTDO + // never_reset_pin_number(5,0); //PH0 JTDO // never_reset_pin_number(5,1); //PH1 JTRST } @@ -228,13 +228,13 @@ void stm32f4_peripherals_gpio_init(void) { void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { switch(led) { - case 0: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, (state ^ 1)); + case 0: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, (state ^ 1)); break; - case 1: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, (state ^ 1)); + case 1: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, (state ^ 1)); break; - case 2: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, (state ^ 1)); + case 2: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, (state ^ 1)); break; - case 3: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, (state ^ 1)); + case 3: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, (state ^ 1)); break; default: break; } diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 9f16a799d..92d1baddc 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -42,7 +42,7 @@ #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #endif -#ifdef STM32F412Zx +#if (defined(STM32F412Zx) || defined(STM32F412Cx)) #define STM32_FLASH_SIZE 0x100000 //1MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #endif diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/system_stm32f4xx.c index caa4f9caf..dd9ab1acd 100644 --- a/ports/stm/system_stm32f4xx.c +++ b/ports/stm/system_stm32f4xx.c @@ -1,6 +1,6 @@ /* * Taken from ST Cube library and modified. See below for original header. - * + * * Modifications copyright (c) 2019 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -28,16 +28,16 @@ * @author MCD Application Team * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * - * This file provides two functions and one global variable to be called from + * This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and + * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. @@ -79,8 +79,8 @@ /** @addtogroup stm32f4xx_system * @{ - */ - + */ + /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ @@ -89,7 +89,7 @@ #include "stm32f4xx.h" #include "py/mpconfig.h" -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -117,11 +117,12 @@ /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\ + || defined(STM32F412Cx) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ - STM32F412Zx || STM32F412Vx */ - + STM32F412Zx || STM32F412Vx || STM32F412Zx*/ + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* #define DATA_IN_ExtSDRAM */ @@ -131,7 +132,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ @@ -153,7 +154,7 @@ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. @@ -170,7 +171,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; */ #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); + static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /** @@ -183,7 +184,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory + * Initialize the FPU setting, vector table location and External memory * configuration. * @param None * @retval None @@ -214,7 +215,7 @@ void SystemInit(void) RCC->CIR = 0x00000000; #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); + SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /* Configure the Vector Table location add offset address ------------------*/ @@ -232,41 +233,41 @@ void SystemInit(void) * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value * depends on the application requirements), user has to ensure that HSE_VALUE * is same as the real frequency of the crystal used. Otherwise, this function * may have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. - * + * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - + /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; @@ -282,10 +283,10 @@ void SystemCoreClockUpdate(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - + if (pllsource != 0) { /* HSE used as PLL clock source */ @@ -334,79 +335,79 @@ void SystemInit_ExtMemCtl(void) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; - + /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -414,50 +415,50 @@ void SystemInit_ExtMemCtl(void) tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); FMC_Bank5_6->SDCR[0] = 0x000019E4; - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ FMC_Bank5_6->SDCMR = 0x00000073; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ FMC_Bank5_6->SDCMR = 0x00046014; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) @@ -465,7 +466,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001091; @@ -473,7 +474,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ - (void)(tmp); + (void)(tmp); } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) @@ -499,13 +500,13 @@ void SystemInit_ExtMemCtl(void) clock */ RCC->AHB1ENR |= 0x0000007D; #else - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001F8; -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + #if defined(STM32F446xx) /* Connect PAx pins to FMC Alternate function */ GPIOA->AFR[0] |= 0xC0000000; @@ -535,78 +536,78 @@ void SystemInit_ExtMemCtl(void) /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ + /* Configure PDx pins speed to 50 MHz */ GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ + /* Configure PEx pins speed to 50 MHz */ GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) + || defined(STM32F469xx) || defined(STM32F479xx) /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -616,72 +617,73 @@ void SystemInit_ExtMemCtl(void) /* Configure and enable SDRAM bank1 */ #if defined(STM32F446xx) FMC_Bank5_6->SDCR[0] = 0x00001954; -#else +#else FMC_Bank5_6->SDCR[0] = 0x000019E4; #endif /* STM32F446xx */ - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x000000F3; -#else +#else FMC_Bank5_6->SDCMR = 0x00000073; #endif /* STM32F446xx */ timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x00044014; -#else +#else FMC_Bank5_6->SDCMR = 0x00046014; #endif /* STM32F446xx */ timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; #if defined(STM32F446xx) FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); -#else +#else FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); #endif /* STM32F446xx */ - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #endif /* DATA_IN_ExtSDRAM */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\ + || defined(STM32F412Cx) #if defined(DATA_IN_ExtSRAM) /*-- GPIOs Configuration -----------------------------------------------------*/ @@ -689,55 +691,55 @@ void SystemInit_ExtMemCtl(void) RCC->AHB1ENR |= 0x00000078; /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0x00CCCCCC; GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ + /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0x00CCCCCC; GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00085AAA; - /* Configure PGx pins speed to 100 MHz */ + /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000CAFFF; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /*-- FMC/FSMC Configuration --------------------------------------------------*/ /* Enable the FMC/FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -749,7 +751,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); @@ -759,7 +761,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ - || defined(STM32F412Zx) || defined(STM32F412Vx) + || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Cx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); /* Configure and enable Bank1_SRAM2 */ @@ -770,8 +772,8 @@ void SystemInit_ExtMemCtl(void) #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ - (void)(tmp); + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); } #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ /** -- cgit v1.2.3 From 5dbdf72472b2d441667a667c8a02c0617491bdb8 Mon Sep 17 00:00:00 2001 From: jgillick Date: Sun, 15 Mar 2020 19:36:16 -0700 Subject: Fix LED port. --- ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c | 8 ++++---- ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c index 7172a2520..d2844f1a6 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c @@ -215,16 +215,16 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { switch(led) { case 0: - HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, state); + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, state); break; case 1: - HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, state); + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, state); break; case 2: - HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, state); + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, state); break; case 3: - HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, state); + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, state); break; default: break; } diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index 4ec6b107f..fde10be3c 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -228,13 +228,13 @@ void stm32f4_peripherals_gpio_init(void) { void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { switch(led) { - case 0: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, (state ^ 1)); + case 0: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, (state ^ 1)); break; - case 1: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, (state ^ 1)); + case 1: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, (state ^ 1)); break; - case 2: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, (state ^ 1)); + case 2: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, (state ^ 1)); break; - case 3: HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, (state ^ 1)); + case 3: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, (state ^ 1)); break; default: break; } -- cgit v1.2.3 From 8a93a81a2628a644b8bcc656b96881b6de35fa98 Mon Sep 17 00:00:00 2001 From: jgillick Date: Sun, 15 Mar 2020 22:31:36 -0700 Subject: Chip specific code. --- ports/stm/common-hal/busio/UART.c | 4 + ports/stm/peripherals/stm32f4/periph.h | 45 +++++--- .../stm32f4/stm32f412cx_thunderpack/periph.c | 128 ++++++++++++++++++++- .../stm32f4/stm32f412cx_thunderpack/pins.c | 36 +++--- .../stm32f4/stm32f412cx_thunderpack/pins.h | 36 +++--- ports/stm/supervisor/usb.c | 8 +- 6 files changed, 193 insertions(+), 64 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c index 0b434fd02..20648bf3d 100644 --- a/ports/stm/common-hal/busio/UART.c +++ b/ports/stm/common-hal/busio/UART.c @@ -443,9 +443,11 @@ STATIC void uart_clock_enable(uint16_t mask) { #endif #ifdef USART3 if (mask & (1 << 2)) { + #ifndef STM32F412Cx __HAL_RCC_USART3_FORCE_RESET(); __HAL_RCC_USART3_RELEASE_RESET(); __HAL_RCC_USART3_CLK_ENABLE(); + #endif } #endif #ifdef UART4 @@ -516,9 +518,11 @@ STATIC void uart_clock_disable(uint16_t mask) { #endif #ifdef USART3 if (mask & (1 << 2)) { + #ifndef STM32F412Cx __HAL_RCC_USART3_FORCE_RESET(); __HAL_RCC_USART3_RELEASE_RESET(); __HAL_RCC_USART3_CLK_DISABLE(); + #endif } #endif #ifdef UART4 diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h index d311afe4a..663df4bed 100644 --- a/ports/stm/peripherals/stm32f4/periph.h +++ b/ports/stm/peripherals/stm32f4/periph.h @@ -33,9 +33,9 @@ #include "stm32f4xx_hal.h" #include "stm32f4/pins.h" -// I2C +// I2C // TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. +// find a compelling reason to store more unique data in them. typedef struct { uint8_t i2c_index:4; // Index of the I2C unit (1 to 3) @@ -44,8 +44,8 @@ typedef struct { } mcu_i2c_sda_obj_t; typedef struct { - uint8_t i2c_index:4; - uint8_t altfn_index:4; + uint8_t i2c_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_i2c_scl_obj_t; @@ -64,9 +64,9 @@ typedef struct { .pin = scl_pin, \ } -// SPI +// SPI // TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. +// find a compelling reason to store more unique data in them. typedef struct { uint8_t spi_index:4; //Up to 6 SPI units @@ -75,20 +75,20 @@ typedef struct { } mcu_spi_sck_obj_t; typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; + uint8_t spi_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_spi_mosi_obj_t; typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; + uint8_t spi_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_spi_miso_obj_t; typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; + uint8_t spi_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_spi_nss_obj_t; @@ -101,17 +101,17 @@ typedef struct { // UART // TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. +// find a compelling reason to store more unique data in them. typedef struct { - uint8_t uart_index:4; - uint8_t altfn_index:4; + uint8_t uart_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_uart_tx_obj_t; typedef struct { - uint8_t uart_index:4; - uint8_t altfn_index:4; + uint8_t uart_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_uart_rx_obj_t; @@ -124,8 +124,8 @@ typedef struct { //Timers typedef struct { - uint8_t tim_index:4; - uint8_t altfn_index:4; + uint8_t tim_index:4; + uint8_t altfn_index:4; uint8_t channel_index:4; const mcu_pin_obj_t * pin; } mcu_tim_pin_obj_t; @@ -154,6 +154,13 @@ typedef struct { #include "stm32f411xe/periph.h" #endif +#ifdef BOARD_THUNDERPACK_STM32F412 +#define HAS_DAC 0 +#define HAS_TRNG 1 +#define HAS_BASIC_TIM 1 +#include "stm32f412cx_thunderpack/periph.h" +#endif + #ifdef STM32F412Zx #define HAS_DAC 0 #define HAS_TRNG 1 diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c index aa9d7abf5..f5effa80e 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c @@ -31,56 +31,133 @@ // I2C -I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, NULL, NULL}; +I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; const mcu_i2c_sda_obj_t mcu_i2c_sda_list[8] = { I2C_SDA(1, 4, &pin_PB07), + I2C_SDA(1, 4, &pin_PB09), + I2C_SDA(2, 4, &pin_PB11), //not on LQFP100 + I2C_SDA(2, 9, &pin_PB09), + I2C_SDA(2, 9, &pin_PB03), + I2C_SDA(3, 4, &pin_PC09), + I2C_SDA(3, 9, &pin_PB04), + I2C_SDA(3, 9, &pin_PB08) }; const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = { I2C_SCL(1, 4, &pin_PB06), + I2C_SCL(1, 4, &pin_PB08), + I2C_SCL(2, 4, &pin_PB10), + I2C_SCL(3, 4, &pin_PA08) }; // SPI -SPI_TypeDef * mcu_spi_banks[5] = {SPI1, NULL, NULL, NULL, NULL}; +SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5}; const mcu_spi_sck_obj_t mcu_spi_sck_list[15] = { SPI(1, 5, &pin_PA05), + SPI(1, 5, &pin_PB03), + SPI(2, 5, &pin_PB10), + SPI(2, 5, &pin_PB13), + SPI(2, 5, &pin_PC07), + SPI(2, 5, &pin_PD03), + SPI(3, 6, &pin_PB03), + SPI(3, 7, &pin_PB12), + SPI(3, 6, &pin_PC10), + SPI(4, 6, &pin_PB13), + SPI(4, 5, &pin_PE02), + SPI(4, 5, &pin_PE12), + SPI(5, 6, &pin_PB00), + SPI(5, 6, &pin_PE02), + SPI(5, 6, &pin_PE12) }; const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14] = { SPI(1, 5, &pin_PA07), SPI(1, 5, &pin_PB05), + SPI(2, 5, &pin_PB15), + SPI(2, 5, &pin_PC03), + SPI(3, 6, &pin_PB05), + SPI(3, 6, &pin_PC12), + SPI(3, 5, &pin_PD06), + SPI(4, 5, &pin_PA01), + SPI(4, 5, &pin_PE06), + SPI(4, 5, &pin_PE14), + SPI(5, 6, &pin_PA10), + SPI(5, 6, &pin_PB08), + SPI(5, 6, &pin_PE06), + SPI(5, 6, &pin_PE14) }; const mcu_spi_miso_obj_t mcu_spi_miso_list[12] = { SPI(1, 5, &pin_PA06), + SPI(1, 5, &pin_PB04), + SPI(2, 5, &pin_PB14), + SPI(2, 5, &pin_PC02), + SPI(3, 6, &pin_PB04), + SPI(3, 6, &pin_PC11), + SPI(4, 6, &pin_PA11), + SPI(4, 5, &pin_PE05), + SPI(4, 5, &pin_PE13), + SPI(5, 6, &pin_PA12), + SPI(5, 6, &pin_PE05), + SPI(5, 6, &pin_PE13) }; const mcu_spi_nss_obj_t mcu_spi_nss_list[12] = { SPI(1, 5, &pin_PA04), + SPI(1, 5, &pin_PA15), + SPI(2, 5, &pin_PB09), + SPI(2, 5, &pin_PB12), + SPI(3, 6, &pin_PA04), + SPI(3, 6, &pin_PA15), + SPI(4, 6, &pin_PB12), + SPI(4, 5, &pin_PE04), + SPI(4, 5, &pin_PE11), + SPI(5, 6, &pin_PB01), + SPI(5, 6, &pin_PE04), + SPI(5, 6, &pin_PE11) }; //UART -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, NULL, NULL, NULL, NULL, NULL}; -bool mcu_uart_has_usart[MAX_UART] = {true, false, false, false, false, false}; +USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, NULL, NULL, USART6}; +bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; const mcu_uart_tx_obj_t mcu_uart_tx_list[11] = { + UART(2, 7, &pin_PA02), UART(1, 7, &pin_PA09), + UART(1, 7, &pin_PA15), + UART(6, 8, &pin_PA11), UART(1, 7, &pin_PB06), + UART(3, 7, &pin_PB10), + UART(6, 8, &pin_PC06), + UART(3, 7, &pin_PC10), + UART(2, 7, &pin_PD05), + UART(3, 7, &pin_PD08), + UART(6, 8, &pin_PG14), }; const mcu_uart_rx_obj_t mcu_uart_rx_list[12] = { + UART(2, 7, &pin_PA03), UART(1, 7, &pin_PA10), + UART(6, 8, &pin_PA12), + UART(1, 7, &pin_PB03), UART(1, 7, &pin_PB07), + UART(3, 7, &pin_PB11), + UART(3, 7, &pin_PC05), + UART(6, 8, &pin_PC07), + UART(3, 7, &pin_PC11), + UART(2, 7, &pin_PD06), + UART(3, 7, &pin_PD09), + UART(6, 8, &pin_PG09), }; //Timers //TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, NULL, - NULL, NULL, TIM13, TIM14}; +TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, + TIM11, TIM12, TIM13, TIM14}; const mcu_tim_pin_obj_t mcu_tim_pin_list[60] = { TIM(2,1,1,&pin_PA00), @@ -101,7 +178,46 @@ const mcu_tim_pin_obj_t mcu_tim_pin_list[60] = { TIM(1,1,2,&pin_PA09), TIM(1,1,3,&pin_PA10), TIM(1,1,4,&pin_PA11), + TIM(2,1,1,&pin_PA15), + TIM(3,2,3,&pin_PB00), + TIM(3,2,4,&pin_PB01), + TIM(2,1,2,&pin_PB03), + TIM(3,2,1,&pin_PB04), TIM(3,2,2,&pin_PB05), TIM(4,2,1,&pin_PB06), TIM(4,2,2,&pin_PB07), + TIM(4,2,3,&pin_PB08), + TIM(10,2,1,&pin_PB08), + TIM(4,2,4,&pin_PB09), + TIM(11,2,1,&pin_PB09), + TIM(2,1,3,&pin_PB10), + TIM(2,1,4,&pin_PB11), + TIM(12,9,1,&pin_PB14), + TIM(12,9,2,&pin_PB15), + TIM(3,2,1,&pin_PC06), + TIM(3,2,2,&pin_PC07), + TIM(3,2,3,&pin_PC08), + TIM(3,2,4,&pin_PC09), + TIM(8,3,1,&pin_PC06), + TIM(8,3,2,&pin_PC07), + TIM(8,3,3,&pin_PC08), + TIM(8,3,4,&pin_PC09), + TIM(4,2,1,&pin_PD12), + TIM(4,2,2,&pin_PD13), + TIM(4,2,3,&pin_PD14), + TIM(4,2,4,&pin_PD15), + TIM(9,3,1,&pin_PE05), + TIM(9,3,2,&pin_PE06), + TIM(1,1,1,&pin_PE09), + TIM(1,1,2,&pin_PE11), + TIM(1,1,3,&pin_PE13), + TIM(1,1,4,&pin_PE14), + TIM(10,3,1,&pin_PF06), + TIM(11,3,1,&pin_PF07), + TIM(13,9,1,&pin_PF08), + TIM(14,9,1,&pin_PF09), + TIM(5,2,1,&pin_PF03), + TIM(5,2,2,&pin_PF04), + TIM(5,2,3,&pin_PF05), + TIM(5,2,4,&pin_PF10), }; diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c index c56de5a29..fddab5ef1 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c @@ -38,17 +38,17 @@ const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT -const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); // 144 only const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10)); const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11)); @@ -71,14 +71,14 @@ const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_1,8)); const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_1,9)); const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); -const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only +const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h index 180f5c316..07c22d528 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h @@ -38,17 +38,17 @@ extern const mcu_pin_obj_t pin_PC13; extern const mcu_pin_obj_t pin_PC14; //pg 51 extern const mcu_pin_obj_t pin_PC15; -extern const mcu_pin_obj_t pin_PF00; // 144 only -extern const mcu_pin_obj_t pin_PF01; // 144 only -extern const mcu_pin_obj_t pin_PF02; // 144 only -extern const mcu_pin_obj_t pin_PF03; // 144 only -extern const mcu_pin_obj_t pin_PF04; // 144 only -extern const mcu_pin_obj_t pin_PF05; // 144 only -extern const mcu_pin_obj_t pin_PF06; // 144 only -extern const mcu_pin_obj_t pin_PF07; // 144 only -extern const mcu_pin_obj_t pin_PF08; // 144 only -extern const mcu_pin_obj_t pin_PF09; // 144 only -extern const mcu_pin_obj_t pin_PF10; // 144 only +extern const mcu_pin_obj_t pin_PF00; // 144 only +extern const mcu_pin_obj_t pin_PF01; // 144 only +extern const mcu_pin_obj_t pin_PF02; // 144 only +extern const mcu_pin_obj_t pin_PF03; // 144 only +extern const mcu_pin_obj_t pin_PF04; // 144 only +extern const mcu_pin_obj_t pin_PF05; // 144 only +extern const mcu_pin_obj_t pin_PF06; // 144 only +extern const mcu_pin_obj_t pin_PF07; // 144 only +extern const mcu_pin_obj_t pin_PF08; // 144 only +extern const mcu_pin_obj_t pin_PF09; // 144 only +extern const mcu_pin_obj_t pin_PF10; // 144 only //pg 52 extern const mcu_pin_obj_t pin_PC00; extern const mcu_pin_obj_t pin_PC01; @@ -69,13 +69,13 @@ extern const mcu_pin_obj_t pin_PC05; extern const mcu_pin_obj_t pin_PB00; extern const mcu_pin_obj_t pin_PB01; extern const mcu_pin_obj_t pin_PB02; -extern const mcu_pin_obj_t pin_PF11; // 144 only -extern const mcu_pin_obj_t pin_PF12; // 144 only -extern const mcu_pin_obj_t pin_PF13; // 144 only -extern const mcu_pin_obj_t pin_PF14; // 144 only -extern const mcu_pin_obj_t pin_PF15; // 144 only -extern const mcu_pin_obj_t pin_PG00; // 144 only -extern const mcu_pin_obj_t pin_PG01; // 144 only +extern const mcu_pin_obj_t pin_PF11; // 144 only +extern const mcu_pin_obj_t pin_PF12; // 144 only +extern const mcu_pin_obj_t pin_PF13; // 144 only +extern const mcu_pin_obj_t pin_PF14; // 144 only +extern const mcu_pin_obj_t pin_PF15; // 144 only +extern const mcu_pin_obj_t pin_PG00; // 144 only +extern const mcu_pin_obj_t pin_PG01; // 144 only //pg 55 extern const mcu_pin_obj_t pin_PE07; extern const mcu_pin_obj_t pin_PE08; diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 358c2de5b..86a51d750 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -59,13 +59,13 @@ STATIC void init_usb_vbus_sense(void) { } void init_usb_hardware(void) { - //TODO: if future chips overload this with options, move to peripherals management. + //TODO: if future chips overload this with options, move to peripherals management. GPIO_InitTypeDef GPIO_InitStruct = {0}; /**USB_OTG_FS GPIO Configuration PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ __HAL_RCC_GPIOA_CLK_ENABLE(); @@ -80,11 +80,13 @@ void init_usb_hardware(void) { never_reset_pin_number(0, 12); /* Configure VBUS Pin */ +#if (BOARD_NO_VBUS_SENSE) GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); never_reset_pin_number(0, 9); +#endif /* This for ID line debug */ GPIO_InitStruct.Pin = GPIO_PIN_10; @@ -103,7 +105,7 @@ void init_usb_hardware(void) { HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); never_reset_pin_number(0, 8); #endif - + /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); -- cgit v1.2.3 From 07549b7fd955cb1368a58d12e82e005865305f26 Mon Sep 17 00:00:00 2001 From: jgillick Date: Tue, 17 Mar 2020 00:27:04 -0700 Subject: Bring back trimmed spaces. --- ports/stm/peripherals/stm32f4/periph.h | 40 +-- ports/stm/peripherals/stm32f4/pins.h | 10 +- ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 3 +- ports/stm/supervisor/usb.c | 8 +- ports/stm/system_stm32f4xx.c | 304 +++++++++++------------ 5 files changed, 182 insertions(+), 183 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h index 663df4bed..1dfa7ac45 100644 --- a/ports/stm/peripherals/stm32f4/periph.h +++ b/ports/stm/peripherals/stm32f4/periph.h @@ -33,9 +33,9 @@ #include "stm32f4xx_hal.h" #include "stm32f4/pins.h" -// I2C +// I2C // TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. +// find a compelling reason to store more unique data in them. typedef struct { uint8_t i2c_index:4; // Index of the I2C unit (1 to 3) @@ -44,8 +44,8 @@ typedef struct { } mcu_i2c_sda_obj_t; typedef struct { - uint8_t i2c_index:4; - uint8_t altfn_index:4; + uint8_t i2c_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_i2c_scl_obj_t; @@ -64,9 +64,9 @@ typedef struct { .pin = scl_pin, \ } -// SPI +// SPI // TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. +// find a compelling reason to store more unique data in them. typedef struct { uint8_t spi_index:4; //Up to 6 SPI units @@ -75,20 +75,20 @@ typedef struct { } mcu_spi_sck_obj_t; typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; + uint8_t spi_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_spi_mosi_obj_t; typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; + uint8_t spi_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_spi_miso_obj_t; typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; + uint8_t spi_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_spi_nss_obj_t; @@ -101,17 +101,17 @@ typedef struct { // UART // TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. +// find a compelling reason to store more unique data in them. typedef struct { - uint8_t uart_index:4; - uint8_t altfn_index:4; + uint8_t uart_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_uart_tx_obj_t; typedef struct { - uint8_t uart_index:4; - uint8_t altfn_index:4; + uint8_t uart_index:4; + uint8_t altfn_index:4; const mcu_pin_obj_t * pin; } mcu_uart_rx_obj_t; @@ -124,8 +124,8 @@ typedef struct { //Timers typedef struct { - uint8_t tim_index:4; - uint8_t altfn_index:4; + uint8_t tim_index:4; + uint8_t altfn_index:4; uint8_t channel_index:4; const mcu_pin_obj_t * pin; } mcu_tim_pin_obj_t; @@ -184,4 +184,4 @@ typedef struct { #include "stm32f407xx/periph.h" #endif -#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__ +#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__ \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h index 7e8baf89d..ce2980969 100644 --- a/ports/stm/peripherals/stm32f4/pins.h +++ b/ports/stm/peripherals/stm32f4/pins.h @@ -40,7 +40,7 @@ typedef struct { mp_obj_base_t base; uint8_t port:4; uint8_t number:4; - uint8_t adc_unit:3; + uint8_t adc_unit:3; uint8_t adc_channel:5; } mcu_pin_obj_t; @@ -51,8 +51,8 @@ typedef struct { #define ADC_3 4 //STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin, -//but all 3 ADCs will share the same input number per pin. -//F4 family has 3 ADC max, 24 channels max. +//but all 3 ADCs will share the same input number per pin. +//F4 family has 3 ADC max, 24 channels max. #define ADC_INPUT(mask, number) \ .adc_unit = mask, \ .adc_channel = number, @@ -64,7 +64,7 @@ typedef struct { extern const mp_obj_type_t mcu_pin_type; // STM32 can have up to 9 ports, each restricted to 16 pins -// We split the pin/port evenly, in contrast to nrf. +// We split the pin/port evenly, in contrast to nrf. #define PIN(p_port, p_number, p_adc) \ { \ { &mcu_pin_type }, \ @@ -96,4 +96,4 @@ extern const mp_obj_type_t mcu_pin_type; #include "stm32f407xx/pins.h" #endif -#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__ +#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__ \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index fde10be3c..68a75f463 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -220,7 +220,7 @@ void stm32f4_peripherals_gpio_init(void) { //never_reset_pin_number(1,4); //PB4 JTRST // Port H is not included in GPIO port array - // never_reset_pin_number(5,0); //PH0 JTDO + // never_reset_pin_number(5,0); //PH0 JTDO // never_reset_pin_number(5,1); //PH1 JTRST } @@ -240,4 +240,3 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { } } - diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 86a51d750..b2c417b11 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -59,13 +59,13 @@ STATIC void init_usb_vbus_sense(void) { } void init_usb_hardware(void) { - //TODO: if future chips overload this with options, move to peripherals management. + //TODO: if future chips overload this with options, move to peripherals management. GPIO_InitTypeDef GPIO_InitStruct = {0}; /**USB_OTG_FS GPIO Configuration PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ __HAL_RCC_GPIOA_CLK_ENABLE(); @@ -105,10 +105,10 @@ void init_usb_hardware(void) { HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); never_reset_pin_number(0, 8); #endif - + /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); init_usb_vbus_sense(); -} +} \ No newline at end of file diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/system_stm32f4xx.c index dd9ab1acd..23a133647 100644 --- a/ports/stm/system_stm32f4xx.c +++ b/ports/stm/system_stm32f4xx.c @@ -1,6 +1,6 @@ /* * Taken from ST Cube library and modified. See below for original header. - * + * * Modifications copyright (c) 2019 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -28,16 +28,16 @@ * @author MCD Application Team * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * - * This file provides two functions and one global variable to be called from + * This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and + * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. @@ -79,8 +79,8 @@ /** @addtogroup stm32f4xx_system * @{ - */ - + */ + /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ @@ -89,7 +89,7 @@ #include "stm32f4xx.h" #include "py/mpconfig.h" -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -121,8 +121,8 @@ || defined(STM32F412Cx) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ - STM32F412Zx || STM32F412Vx || STM32F412Zx*/ - + STM32F412Zx || STM32F412Vx || STM32F412Cx */ + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* #define DATA_IN_ExtSDRAM */ @@ -132,7 +132,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ @@ -154,7 +154,7 @@ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. @@ -171,7 +171,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; */ #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); + static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /** @@ -184,7 +184,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory + * Initialize the FPU setting, vector table location and External memory * configuration. * @param None * @retval None @@ -215,7 +215,7 @@ void SystemInit(void) RCC->CIR = 0x00000000; #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); + SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /* Configure the Vector Table location add offset address ------------------*/ @@ -233,41 +233,41 @@ void SystemInit(void) * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value * depends on the application requirements), user has to ensure that HSE_VALUE * is same as the real frequency of the crystal used. Otherwise, this function * may have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. - * + * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - + /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; @@ -283,10 +283,10 @@ void SystemCoreClockUpdate(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - + if (pllsource != 0) { /* HSE used as PLL clock source */ @@ -335,79 +335,79 @@ void SystemInit_ExtMemCtl(void) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; - + /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -415,50 +415,50 @@ void SystemInit_ExtMemCtl(void) tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); FMC_Bank5_6->SDCR[0] = 0x000019E4; - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ FMC_Bank5_6->SDCMR = 0x00000073; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ FMC_Bank5_6->SDCMR = 0x00046014; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) @@ -466,7 +466,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001091; @@ -474,7 +474,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ - (void)(tmp); + (void)(tmp); } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) @@ -500,13 +500,13 @@ void SystemInit_ExtMemCtl(void) clock */ RCC->AHB1ENR |= 0x0000007D; #else - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001F8; -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + #if defined(STM32F446xx) /* Connect PAx pins to FMC Alternate function */ GPIOA->AFR[0] |= 0xC0000000; @@ -536,78 +536,78 @@ void SystemInit_ExtMemCtl(void) /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ + /* Configure PDx pins speed to 50 MHz */ GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ + /* Configure PEx pins speed to 50 MHz */ GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) + || defined(STM32F469xx) || defined(STM32F479xx) /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -617,65 +617,65 @@ void SystemInit_ExtMemCtl(void) /* Configure and enable SDRAM bank1 */ #if defined(STM32F446xx) FMC_Bank5_6->SDCR[0] = 0x00001954; -#else +#else FMC_Bank5_6->SDCR[0] = 0x000019E4; #endif /* STM32F446xx */ - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x000000F3; -#else +#else FMC_Bank5_6->SDCMR = 0x00000073; #endif /* STM32F446xx */ timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x00044014; -#else +#else FMC_Bank5_6->SDCMR = 0x00046014; #endif /* STM32F446xx */ timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; #if defined(STM32F446xx) FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); -#else +#else FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); #endif /* STM32F446xx */ - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #endif /* DATA_IN_ExtSDRAM */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ @@ -691,55 +691,55 @@ void SystemInit_ExtMemCtl(void) RCC->AHB1ENR |= 0x00000078; /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0x00CCCCCC; GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ + /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0x00CCCCCC; GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00085AAA; - /* Configure PGx pins speed to 100 MHz */ + /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000CAFFF; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /*-- FMC/FSMC Configuration --------------------------------------------------*/ /* Enable the FMC/FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -751,7 +751,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); @@ -768,12 +768,12 @@ void SystemInit_ExtMemCtl(void) FSMC_Bank1->BTCR[2] = 0x00001011; FSMC_Bank1->BTCR[3] = 0x00000201; FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || defined(STM32F412Cx) */ #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ - (void)(tmp); + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || defined(STM32F412Cx) */ + (void)(tmp); } #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ /** @@ -787,4 +787,4 @@ void SystemInit_ExtMemCtl(void) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file -- cgit v1.2.3 From cbc0e0344da6785aa7d734f9dc267fa5973a3956 Mon Sep 17 00:00:00 2001 From: jgillick Date: Tue, 17 Mar 2020 00:36:12 -0700 Subject: Revert changes to system_stm32f4xx.c --- ports/stm/system_stm32f4xx.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/system_stm32f4xx.c index 23a133647..5fb2946e8 100644 --- a/ports/stm/system_stm32f4xx.c +++ b/ports/stm/system_stm32f4xx.c @@ -117,11 +117,10 @@ /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\ - || defined(STM32F412Cx) + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ - STM32F412Zx || STM32F412Vx || STM32F412Cx */ + STM32F412Zx || STM32F412Vx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) @@ -682,8 +681,7 @@ void SystemInit_ExtMemCtl(void) #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\ - || defined(STM32F412Cx) + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) #if defined(DATA_IN_ExtSRAM) /*-- GPIOs Configuration -----------------------------------------------------*/ @@ -761,18 +759,18 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ - || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Cx) + || defined(STM32F412Zx) || defined(STM32F412Vx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); /* Configure and enable Bank1_SRAM2 */ FSMC_Bank1->BTCR[2] = 0x00001011; FSMC_Bank1->BTCR[3] = 0x00000201; FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || defined(STM32F412Cx) */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || defined(STM32F412Cx) */ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ (void)(tmp); } #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ -- cgit v1.2.3 From d41ef45a9b8e8b50ad3907ea16ba2c38658af73f Mon Sep 17 00:00:00 2001 From: jgillick Date: Tue, 17 Mar 2020 00:36:18 -0700 Subject: Update clock. --- ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c index 3e2766516..607870058 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c @@ -55,10 +55,11 @@ void stm32f4_peripherals_clocks_init(void) { HAL_RCC_OscConfig(&RCC_OscInitStruct); /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 72; PeriphClkInitStruct.PLLI2S.PLLI2SM = 12; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 3; - PeriphClkInitStruct.PLLI2S.PLLI2SN = 72; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); -- cgit v1.2.3 From 24d1fd2bf1325ea6ede4a73cc6e8251d486f42a4 Mon Sep 17 00:00:00 2001 From: jgillick Date: Tue, 17 Mar 2020 00:48:19 -0700 Subject: PR Cleanup. --- lib/lwip | 1 + lib/mbedtls | 1 + lib/mynewt-nimble | 1 + lib/stm32lib | 1 + ports/stm/boards/thunderpack/mpconfigboard.h | 2 +- ports/stm/peripherals/stm32f4/periph.h | 2 +- ports/stm/peripherals/stm32f4/pins.h | 2 +- ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 1 - ports/stm/supervisor/usb.c | 2 +- ports/stm/system_stm32f4xx.c | 2 +- 10 files changed, 9 insertions(+), 6 deletions(-) create mode 160000 lib/lwip create mode 160000 lib/mbedtls create mode 160000 lib/mynewt-nimble create mode 160000 lib/stm32lib (limited to 'ports/stm') diff --git a/lib/lwip b/lib/lwip new file mode 160000 index 000000000..159e31b68 --- /dev/null +++ b/lib/lwip @@ -0,0 +1 @@ +Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10 diff --git a/lib/mbedtls b/lib/mbedtls new file mode 160000 index 000000000..3f8d78411 --- /dev/null +++ b/lib/mbedtls @@ -0,0 +1 @@ +Subproject commit 3f8d78411a26e833db18d9fbde0e2f0baeda87f0 diff --git a/lib/mynewt-nimble b/lib/mynewt-nimble new file mode 160000 index 000000000..223714cb1 --- /dev/null +++ b/lib/mynewt-nimble @@ -0,0 +1 @@ +Subproject commit 223714cb16c255cfa701929c0de6d7579bfd2cdd diff --git a/lib/stm32lib b/lib/stm32lib new file mode 160000 index 000000000..668d7a9e5 --- /dev/null +++ b/lib/stm32lib @@ -0,0 +1 @@ +Subproject commit 668d7a9e54aea98f8fe8a858eac1d3daa80fa824 diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h index 18977c131..c9602d412 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.h +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -40,4 +40,4 @@ #define MICROPY_HW_LED_STATUS (&pin_PA03) #define DEFAULT_I2C_BUS_SCL (&pin_PB06) -#define DEFAULT_I2C_BUS_SDA (&pin_PB07) \ No newline at end of file +#define DEFAULT_I2C_BUS_SDA (&pin_PB07) diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h index 1dfa7ac45..5ac8b4061 100644 --- a/ports/stm/peripherals/stm32f4/periph.h +++ b/ports/stm/peripherals/stm32f4/periph.h @@ -184,4 +184,4 @@ typedef struct { #include "stm32f407xx/periph.h" #endif -#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__ \ No newline at end of file +#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__ diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h index ce2980969..53040995d 100644 --- a/ports/stm/peripherals/stm32f4/pins.h +++ b/ports/stm/peripherals/stm32f4/pins.h @@ -96,4 +96,4 @@ extern const mp_obj_type_t mcu_pin_type; #include "stm32f407xx/pins.h" #endif -#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__ \ No newline at end of file +#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__ diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index 68a75f463..2eb296723 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -239,4 +239,3 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { default: break; } } - diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index b2c417b11..0c5e70dd8 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -111,4 +111,4 @@ void init_usb_hardware(void) { __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); init_usb_vbus_sense(); -} \ No newline at end of file +} diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/system_stm32f4xx.c index 5fb2946e8..caa4f9caf 100644 --- a/ports/stm/system_stm32f4xx.c +++ b/ports/stm/system_stm32f4xx.c @@ -785,4 +785,4 @@ void SystemInit_ExtMemCtl(void) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3 From d6342af98014c0cc9e3c6b3010f06db88aa470b2 Mon Sep 17 00:00:00 2001 From: Jeff Epler Date: Tue, 17 Mar 2020 09:33:03 -0500 Subject: ulab: rename enable macro so it appears in the support matrix --- ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk | 2 +- ports/atmel-samd/mpconfigport.mk | 6 +++--- ports/nrf/mpconfigport.mk | 2 +- ports/stm/mpconfigport.mk | 2 +- ports/unix/mpconfigport.mk | 2 +- py/circuitpy_defns.mk | 2 +- py/circuitpy_mpconfig.h | 2 +- py/circuitpy_mpconfig.mk | 4 ++-- py/mpconfig.h | 4 ++-- py/objmodule.c | 2 +- py/py.mk | 4 ++-- 11 files changed, 16 insertions(+), 16 deletions(-) (limited to 'ports/stm') diff --git a/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk b/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk index eb3c81485..5429bcf86 100644 --- a/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk +++ b/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk @@ -16,4 +16,4 @@ CIRCUITPY_NETWORK = 0 CIRCUITPY_PS2IO = 0 CIRCUITPY_AUDIOMP3 = 0 -MICROPY_PY_ULAB = 0 +CIRCUITPY_ULAB = 0 diff --git a/ports/atmel-samd/mpconfigport.mk b/ports/atmel-samd/mpconfigport.mk index 6b6b335d3..c2408feae 100644 --- a/ports/atmel-samd/mpconfigport.mk +++ b/ports/atmel-samd/mpconfigport.mk @@ -40,7 +40,7 @@ endif # SAMD21 needs separate endpoint pairs for MSC BULK IN and BULK OUT, otherwise it's erratic. USB_MSC_EP_NUM_OUT = 1 -MICROPY_PY_ULAB = 0 +CIRCUITPY_ULAB = 0 endif # samd21 @@ -64,9 +64,9 @@ ifndef CIRCUITPY_SAMD CIRCUITPY_SAMD = 1 endif -ifndef MICROPY_PY_ULAB +ifndef CIRCUITPY_ULAB ifneq ($(CIRCUITPY_SMALL_BUILD),1) -MICROPY_PY_ULAB = 1 +CIRCUITPY_ULAB = 1 endif endif diff --git a/ports/nrf/mpconfigport.mk b/ports/nrf/mpconfigport.mk index db1b6b03e..fcc59c484 100644 --- a/ports/nrf/mpconfigport.mk +++ b/ports/nrf/mpconfigport.mk @@ -69,5 +69,5 @@ NRF_DEFINES += -DNRF52840_XXAA -DNRF52840 # Defined here because system_nrf52840.c doesn't #include any of our own include files. CFLAGS += -DCONFIG_NFCT_PINS_AS_GPIOS -MICROPY_PY_ULAB = 1 +CIRCUITPY_ULAB = 1 endif diff --git a/ports/stm/mpconfigport.mk b/ports/stm/mpconfigport.mk index 493f32c63..529a94248 100644 --- a/ports/stm/mpconfigport.mk +++ b/ports/stm/mpconfigport.mk @@ -71,7 +71,7 @@ endif CFLAGS += -DMICROPY_CPYTHON_COMPAT=1 -MICROPY_PY_ULAB = 1 +CIRCUITPY_ULAB = 1 #ifeq ($(MCU_SUB_VARIANT), stm32f412zx) #endif diff --git a/ports/unix/mpconfigport.mk b/ports/unix/mpconfigport.mk index 4cb1804d4..6bb1c9693 100644 --- a/ports/unix/mpconfigport.mk +++ b/ports/unix/mpconfigport.mk @@ -41,4 +41,4 @@ MICROPY_PY_JNI = 0 # as submodules (currently affects only libffi). MICROPY_STANDALONE = 0 -MICROPY_PY_ULAB = 1 +CIRCUITPY_ULAB = 1 diff --git a/py/circuitpy_defns.mk b/py/circuitpy_defns.mk index 92021d0d0..f84d0b5b1 100644 --- a/py/circuitpy_defns.mk +++ b/py/circuitpy_defns.mk @@ -431,7 +431,7 @@ $(addprefix lib/,\ libm/atanf.c \ libm/atan2f.c \ ) -ifeq ($(MICROPY_PY_ULAB),1) +ifeq ($(CIRCUITPY_ULAB),1) SRC_LIBM += \ $(addprefix lib/,\ libm/acoshf.c \ diff --git a/py/circuitpy_mpconfig.h b/py/circuitpy_mpconfig.h index acff27bcf..04e191264 100644 --- a/py/circuitpy_mpconfig.h +++ b/py/circuitpy_mpconfig.h @@ -581,7 +581,7 @@ extern const struct _mp_obj_module_t ustack_module; #define JSON_MODULE #endif -#if defined(MICROPY_PY_ULAB) && MICROPY_PY_ULAB +#if defined(CIRCUITPY_ULAB) && CIRCUITPY_ULAB #define ULAB_MODULE \ { MP_ROM_QSTR(MP_QSTR_ulab), MP_ROM_PTR(&ulab_user_cmodule) }, #else diff --git a/py/circuitpy_mpconfig.mk b/py/circuitpy_mpconfig.mk index 21b1abd9b..1a375efc6 100644 --- a/py/circuitpy_mpconfig.mk +++ b/py/circuitpy_mpconfig.mk @@ -340,8 +340,8 @@ endif CFLAGS += -DCIRCUITPY_SERIAL_UART=$(CIRCUITPY_SERIAL_UART) # ulab numerics library -ifndef MICROPY_PY_ULAB -MICROPY_PY_ULAB = $(CIRCUITPY_FULL_BUILD) +ifndef CIRCUITPY_ULAB +CIRCUITPY_ULAB = $(CIRCUITPY_FULL_BUILD) endif # Enabled micropython.native decorator (experimental) diff --git a/py/mpconfig.h b/py/mpconfig.h index 01572f546..513f04f6e 100755 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -1178,8 +1178,8 @@ typedef double mp_float_t; #define MICROPY_PY_UJSON (0) #endif -#ifndef MICROPY_PY_ULAB -#define MICROPY_PY_ULAB (0) +#ifndef CIRCUITPY_ULAB +#define CIRCUITPY_ULAB (0) #endif #ifndef MICROPY_PY_URE diff --git a/py/objmodule.c b/py/objmodule.c index 7405a6919..b6a8a084e 100644 --- a/py/objmodule.c +++ b/py/objmodule.c @@ -213,7 +213,7 @@ STATIC const mp_rom_map_elem_t mp_builtin_module_table[] = { { MP_ROM_QSTR(MP_QSTR_ujson), MP_ROM_PTR(&mp_module_ujson) }, #endif #endif -#if MICROPY_PY_ULAB +#if CIRCUITPY_ULAB #if CIRCUITPY // CircuitPython: Defined in MICROPY_PORT_BUILTIN_MODULES, so not defined here. // TODO: move to shared-bindings/ diff --git a/py/py.mk b/py/py.mk index 5e044947a..d70c6c33e 100644 --- a/py/py.mk +++ b/py/py.mk @@ -105,7 +105,7 @@ $(BUILD)/$(BTREE_DIR)/%.o: CFLAGS += -Wno-old-style-definition -Wno-sign-compare $(BUILD)/extmod/modbtree.o: CFLAGS += $(BTREE_DEFS) endif -ifeq ($(MICROPY_PY_ULAB),1) +ifeq ($(CIRCUITPY_ULAB),1) SRC_MOD += $(addprefix extmod/ulab/code/, \ create.c \ fft.c \ @@ -117,7 +117,7 @@ poly.c \ ulab.c \ vectorise.c \ ) -CFLAGS_MOD += -DMICROPY_PY_ULAB=1 -DMODULE_ULAB_ENABLED=1 +CFLAGS_MOD += -DCIRCUITPY_ULAB=1 -DMODULE_ULAB_ENABLED=1 $(BUILD)/extmod/ulab/code/%.o: CFLAGS += -Wno-sign-compare -Wno-missing-prototypes -Wno-unused-parameter -Wno-missing-declarations -Wno-error -Wno-shadow -Wno-maybe-uninitialized -DCIRCUITPY endif -- cgit v1.2.3 From 679314a22ed78ede26b7d01646e4fd82aeb30b68 Mon Sep 17 00:00:00 2001 From: jgillick Date: Wed, 18 Mar 2020 00:35:20 -0700 Subject: Fix disable VBUS sensing. --- ports/stm/supervisor/usb.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'ports/stm') diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 0c5e70dd8..6cb9feb4b 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -41,7 +41,12 @@ STATIC void init_usb_vbus_sense(void) { #if (BOARD_NO_VBUS_SENSE) // Disable VBUS sensing #ifdef USB_OTG_GCCFG_VBDEN + // Deactivate VBUS Sensing B USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + // B-peripheral session valid override enable + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; #else USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; -- cgit v1.2.3 From 9be2ab60082fa56d652e0335698ba0855b3c41ba Mon Sep 17 00:00:00 2001 From: jgillick Date: Wed, 18 Mar 2020 23:55:18 -0700 Subject: Change the board to use an STM32F411 chip. --- ports/stm/boards/startup_stm32f412cx_thunderpack.s | 521 --------------------- ports/stm/boards/thunderpack/mpconfigboard.h | 20 +- ports/stm/boards/thunderpack/mpconfigboard.mk | 15 +- ports/stm/boards/thunderpack/pins.c | 118 ++--- ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h | 94 ++-- .../stm32f4/stm32f412cx_thunderpack/clocks.c | 76 --- .../stm32f4/stm32f412cx_thunderpack/gpio.c | 233 --------- .../stm32f4/stm32f412cx_thunderpack/periph.c | 223 --------- .../stm32f4/stm32f412cx_thunderpack/periph.h | 58 --- .../stm32f4/stm32f412cx_thunderpack/pins.c | 161 ------- .../stm32f4/stm32f412cx_thunderpack/pins.h | 158 ------- 11 files changed, 94 insertions(+), 1583 deletions(-) delete mode 100644 ports/stm/boards/startup_stm32f412cx_thunderpack.s delete mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c delete mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c delete mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c delete mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.h delete mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c delete mode 100644 ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h (limited to 'ports/stm') diff --git a/ports/stm/boards/startup_stm32f412cx_thunderpack.s b/ports/stm/boards/startup_stm32f412cx_thunderpack.s deleted file mode 100644 index 1c344ec08..000000000 --- a/ports/stm/boards/startup_stm32f412cx_thunderpack.s +++ /dev/null @@ -1,521 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f412Cx.s - * @author MCD Application Team - * @brief STM32F412Cx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ -/* bl __libc_init_array */ -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word 0 /* Reserved */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM6_IRQHandler /* TIM6 */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ - .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak FMPI2C1_EV_IRQHandler - .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler - - .weak FMPI2C1_ER_IRQHandler - .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h index c9602d412..0e66f2a71 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.h +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -23,21 +23,21 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#define BOARD_THUNDERPACK_STM32F412 #define MICROPY_HW_BOARD_NAME "THUNDERPACK" -#define MICROPY_HW_MCU_NAME "STM32F412xGU" +#define MICROPY_HW_MCU_NAME "STM32F411CE" -#define FLASH_SIZE (0x100000) +#define FLASH_SIZE (0x80000) #define FLASH_PAGE_SIZE (0x4000) +#define BOARD_FLASH_SIZE (FLASH_SIZE - 0x2000 - 0xC000) -#define BOARD_OSC_DIV (24) -#define BOARD_NO_VBUS_SENSE (1) +#define BOARD_OSC_DIV (24) +#define BOARD_OVERWRITE_SWD (1) +#define BOARD_NO_VBUS_SENSE (1) -#define CP_RGB_STATUS_LED -#define CP_RGB_STATUS_R (&pin_PA00) -#define CP_RGB_STATUS_G (&pin_PA01) -#define CP_RGB_STATUS_B (&pin_PA02) -#define MICROPY_HW_LED_STATUS (&pin_PA03) +// Status LEDs +#define MICROPY_HW_LED_TX (&pin_PA00) +#define MICROPY_HW_LED_RX (&pin_PB01) +#define MICROPY_HW_LED_STATUS (&pin_PA02) #define DEFAULT_I2C_BUS_SCL (&pin_PB06) #define DEFAULT_I2C_BUS_SDA (&pin_PB07) diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index 9827b9e06..3efd6a8bd 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -1,17 +1,18 @@ -USB_VID = 0x0483 -USB_PID = 0xdf11 -USB_PRODUCT = "Thunderpack" +USB_VID = 0x239A +USB_PID = 0x806A +USB_PRODUCT = "Thunderpack powered by ST" USB_MANUFACTURER = "Jeremy Gillick" -USB_DEVICES = "CDC,MSC,HID" +USB_DEVICES = "CDC,MSC" INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = NONE MCU_SERIES = m4 MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f412cx_thunderpack +MCU_SUB_VARIANT = stm32f411xe MCU_PACKAGE = 48 -CMSIS_MCU = STM32F412Cx -LD_FILE = boards/STM32F412ZGTx_FLASH.ld +CMSIS_MCU = STM32F411xE +LD_FILE = boards/STM32F411VETx_FLASH.ld +STARTUP_FILE = startup_stm32f411xe.s diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c index db0b3cde1..830e99dae 100644 --- a/ports/stm/boards/thunderpack/pins.c +++ b/ports/stm/boards/thunderpack/pins.c @@ -1,95 +1,37 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - // { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - // { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - // { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - // { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - // { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, - // { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - // { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, - // { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, - // { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, - // { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - // { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - // { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - // { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - // { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - // { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - // { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - // { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - // { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, - // { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, - // { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, - // { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, - // { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - // { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - // { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - // { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - // { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - // { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - // { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, - // { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - // { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - // { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - // { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - // { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - // { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, - // { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, - // { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, - // { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, - // { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, - // { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, - // { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - // { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - // { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - // { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - // { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, - // { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB10) }, - // { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, - // { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA15) }, - // { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB08) }, - // { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PG10) }, - // { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PG11) }, - // { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PF03) }, - // { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PF10) }, - // { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG12) }, - // { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PF04) }, - // { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG13) }, - // { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, //USART6 TX - // { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, //USART6 RX - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA01) }, - // { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC01) }, - // { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, - // { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC04) }, - // { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC05) }, //alt PB09, see F401ZG-DISCO manual - // { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB00) }, //alt PB10, see F401ZG-DISCO manual + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, //USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, //USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, //USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, //USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) }, - { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_B5), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_B6), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_B7), MP_ROM_PTR(&pin_PB07) }, - { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PA03) }, + + { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PB04) }, + + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) }, + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h b/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h index 15162dfcc..5cb563422 100644 --- a/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h +++ b/ports/stm/boards/thunderpack/stm32f4xx_hal_conf.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f4xx_hal_conf_template.h * @author MCD Application Team - * @brief HAL configuration template file. + * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f4xx_hal_conf.h. ****************************************************************************** @@ -17,7 +17,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -32,45 +32,46 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED /* #define HAL_DCMI_MODULE_ENABLED */ /* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ -#define HAL_SRAM_MODULE_ENABLED +/* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ #define HAL_I2C_MODULE_ENABLED #define HAL_I2S_MODULE_ENABLED /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ -#define HAL_RNG_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ -#define HAL_SD_MODULE_ENABLED +/* #define HAL_SD_MODULE_ENABLED */ /* #define HAL_MMC_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED +/* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ /* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */ @@ -89,10 +90,10 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)24000000U) /*!< Value of the External oscillator in Hz */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) @@ -102,35 +103,36 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations - in voltage and temperature.*/ + in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ + /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ @@ -143,16 +145,16 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -169,7 +171,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -177,9 +179,9 @@ /* Section 2: PHY configuration section */ -/* DP83848_PHY_ADDRESS Address*/ +/* DP83848_PHY_ADDRESS Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY ((uint32_t)0x000000FFU) /* PHY Configuration delay */ #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) @@ -191,7 +193,7 @@ #define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -206,7 +208,7 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ @@ -224,7 +226,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -242,7 +244,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -260,13 +262,9 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ -#ifdef HAL_SMBUS_MODULE_ENABLED -#include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - #ifdef HAL_DMA2D_MODULE_ENABLED #include "stm32f4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ @@ -286,7 +284,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -301,11 +299,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -386,7 +384,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -414,14 +412,14 @@ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32f4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ - + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -430,13 +428,13 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_CONF_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c deleted file mode 100644 index 607870058..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c +++ /dev/null @@ -1,76 +0,0 @@ - -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ -#include "stm32f4xx_hal.h" -#include "py/mpconfig.h" - -void stm32f4_peripherals_clocks_init(void) { - //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the - * device is clocked below the maximum system frequency, to update the - * voltage scaling value regarding system frequency refer to product - * datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 12; - RCC_OscInitStruct.PLL.PLLN = 100; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - RCC_OscInitStruct.PLL.PLLR = 2; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLLSAI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; - PeriphClkInitStruct.PLLI2S.PLLI2SN = 72; - PeriphClkInitStruct.PLLI2S.PLLI2SM = 12; - PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; - PeriphClkInitStruct.PLLI2S.PLLI2SQ = 3; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; - PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - * clocks dividers */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); -} diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c deleted file mode 100644 index d2844f1a6..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/gpio.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * This file is part of the Micro Python project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/* GPIO PIN REFERENCE -#define LED3_Pin GPIO_PIN_2 -#define LED3_GPIO_Port GPIOE -#define LED4_Pin GPIO_PIN_3 -#define LED4_GPIO_Port GPIOE -#define DFSDM_DATIN3_Pin GPIO_PIN_4 -#define DFSDM_DATIN3_GPIO_Port GPIOE -#define A0_Pin GPIO_PIN_0 -#define A0_GPIO_Port GPIOF -#define LCD_BLCTRL_Pin GPIO_PIN_5 -#define LCD_BLCTRL_GPIO_Port GPIOF -#define QSPI_BK1_IO3_Pin GPIO_PIN_6 -#define QSPI_BK1_IO3_GPIO_Port GPIOF -#define QSPI_BK1_IO2_Pin GPIO_PIN_7 -#define QSPI_BK1_IO2_GPIO_Port GPIOF -#define QSPI_BK1_IO0_Pin GPIO_PIN_8 -#define QSPI_BK1_IO0_GPIO_Port GPIOF -#define QSPI_BK1_IO1_Pin GPIO_PIN_9 -#define QSPI_BK1_IO1_GPIO_Port GPIOF -#define STLK_MCO_Pin GPIO_PIN_0 -#define STLK_MCO_GPIO_Port GPIOH -#define DFSDM_CKOUT_Pin GPIO_PIN_2 -#define DFSDM_CKOUT_GPIO_Port GPIOC -#define JOY_SEL_Pin GPIO_PIN_0 -#define JOY_SEL_GPIO_Port GPIOA -#define STLINK_RX_Pin GPIO_PIN_2 -#define STLINK_RX_GPIO_Port GPIOA -#define STLINK_TX_Pin GPIO_PIN_3 -#define STLINK_TX_GPIO_Port GPIOA -#define CODEC_I2S3_WS_Pin GPIO_PIN_4 -#define CODEC_I2S3_WS_GPIO_Port GPIOA -#define DFSDM_DATIN0_Pin GPIO_PIN_1 -#define DFSDM_DATIN0_GPIO_Port GPIOB -#define QSPI_CLK_Pin GPIO_PIN_2 -#define QSPI_CLK_GPIO_Port GPIOB -#define EXT_RESET_Pin GPIO_PIN_11 -#define EXT_RESET_GPIO_Port GPIOF -#define CTP_RST_Pin GPIO_PIN_12 -#define CTP_RST_GPIO_Port GPIOF -#define JOY_RIGHT_Pin GPIO_PIN_14 -#define JOY_RIGHT_GPIO_Port GPIOF -#define JOY_LEFT_Pin GPIO_PIN_15 -#define JOY_LEFT_GPIO_Port GPIOF -#define JOY_UP_Pin GPIO_PIN_0 -#define JOY_UP_GPIO_Port GPIOG -#define JOY_DOWN_Pin GPIO_PIN_1 -#define JOY_DOWN_GPIO_Port GPIOG -#define D4_Pin GPIO_PIN_7 -#define D4_GPIO_Port GPIOE -#define D5_Pin GPIO_PIN_8 -#define D5_GPIO_Port GPIOE -#define D6_Pin GPIO_PIN_9 -#define D6_GPIO_Port GPIOE -#define D7_Pin GPIO_PIN_10 -#define D7_GPIO_Port GPIOE -#define D8_Pin GPIO_PIN_11 -#define D8_GPIO_Port GPIOE -#define D9_Pin GPIO_PIN_12 -#define D9_GPIO_Port GPIOE -#define D10_Pin GPIO_PIN_13 -#define D10_GPIO_Port GPIOE -#define D11_Pin GPIO_PIN_14 -#define D11_GPIO_Port GPIOE -#define D12_Pin GPIO_PIN_15 -#define D12_GPIO_Port GPIOE -#define I2C2_SCL_Pin GPIO_PIN_10 -#define I2C2_SCL_GPIO_Port GPIOB -#define M2_CKIN_Pin GPIO_PIN_11 -#define M2_CKIN_GPIO_Port GPIOB -#define CODEC_I2S3_SCK_Pin GPIO_PIN_12 -#define CODEC_I2S3_SCK_GPIO_Port GPIOB -#define D13_Pin GPIO_PIN_8 -#define D13_GPIO_Port GPIOD -#define D14_Pin GPIO_PIN_9 -#define D14_GPIO_Port GPIOD -#define D15_Pin GPIO_PIN_10 -#define D15_GPIO_Port GPIOD -#define LCD_RESET_Pin GPIO_PIN_11 -#define LCD_RESET_GPIO_Port GPIOD -#define D0_Pin GPIO_PIN_14 -#define D0_GPIO_Port GPIOD -#define D1_Pin GPIO_PIN_15 -#define D1_GPIO_Port GPIOD -#define CODEC_INT_Pin GPIO_PIN_2 -#define CODEC_INT_GPIO_Port GPIOG -#define LCD_TE_Pin GPIO_PIN_4 -#define LCD_TE_GPIO_Port GPIOG -#define CTP_INT_Pin GPIO_PIN_5 -#define CTP_INT_GPIO_Port GPIOG -#define QSPI_BK1_NCS_Pin GPIO_PIN_6 -#define QSPI_BK1_NCS_GPIO_Port GPIOG -#define USB_OTGFS_OVRCR_Pin GPIO_PIN_7 -#define USB_OTGFS_OVRCR_GPIO_Port GPIOG -#define USB_OTGFS_PPWR_EN_Pin GPIO_PIN_8 -#define USB_OTGFS_PPWR_EN_GPIO_Port GPIOG -#define CODEC_I2S3_MCK_Pin GPIO_PIN_7 -#define CODEC_I2S3_MCK_GPIO_Port GPIOC -#define uSD_D0_Pin GPIO_PIN_8 -#define uSD_D0_GPIO_Port GPIOC -#define uSD_D1_Pin GPIO_PIN_9 -#define uSD_D1_GPIO_Port GPIOC -#define M2_CKINA8_Pin GPIO_PIN_8 -#define M2_CKINA8_GPIO_Port GPIOA -#define USB_OTGFS_VBUS_Pin GPIO_PIN_9 -#define USB_OTGFS_VBUS_GPIO_Port GPIOA -#define USB_OTGFS_ID_Pin GPIO_PIN_10 -#define USB_OTGFS_ID_GPIO_Port GPIOA -#define USB_OTGFS_DM_Pin GPIO_PIN_11 -#define USB_OTGFS_DM_GPIO_Port GPIOA -#define USB_OTGFS_DP_Pin GPIO_PIN_12 -#define USB_OTGFS_DP_GPIO_Port GPIOA -#define SWDIO_Pin GPIO_PIN_13 -#define SWDIO_GPIO_Port GPIOA -#define SWCLK_Pin GPIO_PIN_14 -#define SWCLK_GPIO_Port GPIOA -#define uSD_D2_Pin GPIO_PIN_10 -#define uSD_D2_GPIO_Port GPIOC -#define uSD_D3_Pin GPIO_PIN_11 -#define uSD_D3_GPIO_Port GPIOC -#define uSD_CLK_Pin GPIO_PIN_12 -#define uSD_CLK_GPIO_Port GPIOC -#define D2_Pin GPIO_PIN_0 -#define D2_GPIO_Port GPIOD -#define D3_Pin GPIO_PIN_1 -#define D3_GPIO_Port GPIOD -#define uSD_CMD_Pin GPIO_PIN_2 -#define uSD_CMD_GPIO_Port GPIOD -#define uSD_DETECT_Pin GPIO_PIN_3 -#define uSD_DETECT_GPIO_Port GPIOD -#define FMC_NOE_Pin GPIO_PIN_4 -#define FMC_NOE_GPIO_Port GPIOD -#define FMC_NWE_Pin GPIO_PIN_5 -#define FMC_NWE_GPIO_Port GPIOD -#define FMC_NE1_Pin GPIO_PIN_7 -#define FMC_NE1_GPIO_Port GPIOD -#define SWO_Pin GPIO_PIN_3 -#define SWO_GPIO_Port GPIOB -#define CODEC_I2S3ext_SD_Pin GPIO_PIN_4 -#define CODEC_I2S3ext_SD_GPIO_Port GPIOB -#define CODEC_I2S3_SD_Pin GPIO_PIN_5 -#define CODEC_I2S3_SD_GPIO_Port GPIOB -#define I2C1_SCL_Pin GPIO_PIN_6 -#define I2C1_SCL_GPIO_Port GPIOB -#define I2C1_SDA_Pin GPIO_PIN_7 -#define I2C1_SDA_GPIO_Port GPIOB -#define I2C2_SDA_Pin GPIO_PIN_9 -#define I2C2_SDA_GPIO_Port GPIOB -#define LED1_Pin GPIO_PIN_0 -#define LED1_GPIO_Port GPIOE -#define LED2_Pin GPIO_PIN_1 -#define LED2_GPIO_Port GPIOE -*/ - -#include "stm32f4xx_hal.h" -#include "stm32f4/gpio.h" -#include "common-hal/microcontroller/Pin.h" - -void stm32f4_peripherals_gpio_init(void) { - //Enable all GPIO for now - GPIO_InitTypeDef GPIO_InitStruct = {0}; - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - - //Configure LED pins - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET); - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - //Status LED chain - stm32f4_peripherals_status_led(0,1); - stm32f4_peripherals_status_led(1,0); - stm32f4_peripherals_status_led(2,0); - stm32f4_peripherals_status_led(3,0); - - //Never reset pins - never_reset_pin_number(2,13); //PC13 anti tamp - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK -} - -void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { - switch(led) - { - case 0: - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, state); - break; - case 1: - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, state); - break; - case 2: - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, state); - break; - case 3: - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, state); - break; - default: break; - } -} - - diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c deleted file mode 100644 index f5effa80e..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.c +++ /dev/null @@ -1,223 +0,0 @@ - /* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" -#include "py/mphal.h" -#include "stm32f4/pins.h" -#include "stm32f4/periph.h" - -// I2C - -I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; - -const mcu_i2c_sda_obj_t mcu_i2c_sda_list[8] = { - I2C_SDA(1, 4, &pin_PB07), - I2C_SDA(1, 4, &pin_PB09), - I2C_SDA(2, 4, &pin_PB11), //not on LQFP100 - I2C_SDA(2, 9, &pin_PB09), - I2C_SDA(2, 9, &pin_PB03), - I2C_SDA(3, 4, &pin_PC09), - I2C_SDA(3, 9, &pin_PB04), - I2C_SDA(3, 9, &pin_PB08) -}; - -const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = { - I2C_SCL(1, 4, &pin_PB06), - I2C_SCL(1, 4, &pin_PB08), - I2C_SCL(2, 4, &pin_PB10), - I2C_SCL(3, 4, &pin_PA08) -}; - -// SPI - -SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5}; - -const mcu_spi_sck_obj_t mcu_spi_sck_list[15] = { - SPI(1, 5, &pin_PA05), - SPI(1, 5, &pin_PB03), - SPI(2, 5, &pin_PB10), - SPI(2, 5, &pin_PB13), - SPI(2, 5, &pin_PC07), - SPI(2, 5, &pin_PD03), - SPI(3, 6, &pin_PB03), - SPI(3, 7, &pin_PB12), - SPI(3, 6, &pin_PC10), - SPI(4, 6, &pin_PB13), - SPI(4, 5, &pin_PE02), - SPI(4, 5, &pin_PE12), - SPI(5, 6, &pin_PB00), - SPI(5, 6, &pin_PE02), - SPI(5, 6, &pin_PE12) -}; - -const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14] = { - SPI(1, 5, &pin_PA07), - SPI(1, 5, &pin_PB05), - SPI(2, 5, &pin_PB15), - SPI(2, 5, &pin_PC03), - SPI(3, 6, &pin_PB05), - SPI(3, 6, &pin_PC12), - SPI(3, 5, &pin_PD06), - SPI(4, 5, &pin_PA01), - SPI(4, 5, &pin_PE06), - SPI(4, 5, &pin_PE14), - SPI(5, 6, &pin_PA10), - SPI(5, 6, &pin_PB08), - SPI(5, 6, &pin_PE06), - SPI(5, 6, &pin_PE14) -}; - -const mcu_spi_miso_obj_t mcu_spi_miso_list[12] = { - SPI(1, 5, &pin_PA06), - SPI(1, 5, &pin_PB04), - SPI(2, 5, &pin_PB14), - SPI(2, 5, &pin_PC02), - SPI(3, 6, &pin_PB04), - SPI(3, 6, &pin_PC11), - SPI(4, 6, &pin_PA11), - SPI(4, 5, &pin_PE05), - SPI(4, 5, &pin_PE13), - SPI(5, 6, &pin_PA12), - SPI(5, 6, &pin_PE05), - SPI(5, 6, &pin_PE13) -}; - -const mcu_spi_nss_obj_t mcu_spi_nss_list[12] = { - SPI(1, 5, &pin_PA04), - SPI(1, 5, &pin_PA15), - SPI(2, 5, &pin_PB09), - SPI(2, 5, &pin_PB12), - SPI(3, 6, &pin_PA04), - SPI(3, 6, &pin_PA15), - SPI(4, 6, &pin_PB12), - SPI(4, 5, &pin_PE04), - SPI(4, 5, &pin_PE11), - SPI(5, 6, &pin_PB01), - SPI(5, 6, &pin_PE04), - SPI(5, 6, &pin_PE11) -}; - -//UART - -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, NULL, NULL, USART6}; -bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; - -const mcu_uart_tx_obj_t mcu_uart_tx_list[11] = { - UART(2, 7, &pin_PA02), - UART(1, 7, &pin_PA09), - UART(1, 7, &pin_PA15), - UART(6, 8, &pin_PA11), - UART(1, 7, &pin_PB06), - UART(3, 7, &pin_PB10), - UART(6, 8, &pin_PC06), - UART(3, 7, &pin_PC10), - UART(2, 7, &pin_PD05), - UART(3, 7, &pin_PD08), - UART(6, 8, &pin_PG14), -}; - -const mcu_uart_rx_obj_t mcu_uart_rx_list[12] = { - UART(2, 7, &pin_PA03), - UART(1, 7, &pin_PA10), - UART(6, 8, &pin_PA12), - UART(1, 7, &pin_PB03), - UART(1, 7, &pin_PB07), - UART(3, 7, &pin_PB11), - UART(3, 7, &pin_PC05), - UART(6, 8, &pin_PC07), - UART(3, 7, &pin_PC11), - UART(2, 7, &pin_PD06), - UART(3, 7, &pin_PD09), - UART(6, 8, &pin_PG09), -}; - -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, - TIM11, TIM12, TIM13, TIM14}; - -const mcu_tim_pin_obj_t mcu_tim_pin_list[60] = { - TIM(2,1,1,&pin_PA00), - TIM(5,2,1,&pin_PA00), - TIM(2,1,2,&pin_PA01), - TIM(5,2,2,&pin_PA01), - TIM(2,1,3,&pin_PA02), - TIM(5,2,3,&pin_PA02), - TIM(2,1,4,&pin_PA03), - TIM(5,2,4,&pin_PA03), - TIM(9,3,1,&pin_PA02), - TIM(9,3,2,&pin_PA03), - TIM(3,2,1,&pin_PA06), - TIM(13,9,1,&pin_PA06), - TIM(3,2,2,&pin_PA07), - TIM(14,9,1,&pin_PA07), - TIM(1,1,1,&pin_PA08), - TIM(1,1,2,&pin_PA09), - TIM(1,1,3,&pin_PA10), - TIM(1,1,4,&pin_PA11), - TIM(2,1,1,&pin_PA15), - TIM(3,2,3,&pin_PB00), - TIM(3,2,4,&pin_PB01), - TIM(2,1,2,&pin_PB03), - TIM(3,2,1,&pin_PB04), - TIM(3,2,2,&pin_PB05), - TIM(4,2,1,&pin_PB06), - TIM(4,2,2,&pin_PB07), - TIM(4,2,3,&pin_PB08), - TIM(10,2,1,&pin_PB08), - TIM(4,2,4,&pin_PB09), - TIM(11,2,1,&pin_PB09), - TIM(2,1,3,&pin_PB10), - TIM(2,1,4,&pin_PB11), - TIM(12,9,1,&pin_PB14), - TIM(12,9,2,&pin_PB15), - TIM(3,2,1,&pin_PC06), - TIM(3,2,2,&pin_PC07), - TIM(3,2,3,&pin_PC08), - TIM(3,2,4,&pin_PC09), - TIM(8,3,1,&pin_PC06), - TIM(8,3,2,&pin_PC07), - TIM(8,3,3,&pin_PC08), - TIM(8,3,4,&pin_PC09), - TIM(4,2,1,&pin_PD12), - TIM(4,2,2,&pin_PD13), - TIM(4,2,3,&pin_PD14), - TIM(4,2,4,&pin_PD15), - TIM(9,3,1,&pin_PE05), - TIM(9,3,2,&pin_PE06), - TIM(1,1,1,&pin_PE09), - TIM(1,1,2,&pin_PE11), - TIM(1,1,3,&pin_PE13), - TIM(1,1,4,&pin_PE14), - TIM(10,3,1,&pin_PF06), - TIM(11,3,1,&pin_PF07), - TIM(13,9,1,&pin_PF08), - TIM(14,9,1,&pin_PF09), - TIM(5,2,1,&pin_PF03), - TIM(5,2,2,&pin_PF04), - TIM(5,2,3,&pin_PF05), - TIM(5,2,4,&pin_PF10), -}; diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.h b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.h deleted file mode 100644 index e0141e6da..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/periph.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H - -//I2C -extern I2C_TypeDef * mcu_i2c_banks[3]; - -extern const mcu_i2c_sda_obj_t mcu_i2c_sda_list[8]; -extern const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4]; - - -//SPI -extern SPI_TypeDef * mcu_spi_banks[5]; - -extern const mcu_spi_sck_obj_t mcu_spi_sck_list[15]; -extern const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14]; -extern const mcu_spi_miso_obj_t mcu_spi_miso_list[12]; -extern const mcu_spi_nss_obj_t mcu_spi_nss_list[12]; - -//UART -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; -extern bool mcu_uart_has_usart[MAX_UART]; - -extern const mcu_uart_tx_obj_t mcu_uart_tx_list[11]; -extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12]; - -//Timers -#define TIM_BANK_ARRAY_LEN 14 -#define TIM_PIN_ARRAY_LEN 60 -TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; -const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; - -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c deleted file mode 100644 index fddab5ef1..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.c +++ /dev/null @@ -1,161 +0,0 @@ - /* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "py/obj.h" -#include "py/mphal.h" -#include "stm32f4/pins.h" - -const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); -const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); -const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); -const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); -const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); - -const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp -const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN -const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT - -const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); // 144 only - -const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10)); -const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11)); -const mcu_pin_obj_t pin_PC02 = PIN(2, 2, ADC_INPUT(ADC_1,12)); -const mcu_pin_obj_t pin_PC03 = PIN(2, 3, ADC_INPUT(ADC_1,13)); - -const mcu_pin_obj_t pin_PA00 = PIN(0, 0, ADC_INPUT(ADC_1,0)); -const mcu_pin_obj_t pin_PA01 = PIN(0, 1, ADC_INPUT(ADC_1,1)); -const mcu_pin_obj_t pin_PA02 = PIN(0, 2, ADC_INPUT(ADC_1,2)); -const mcu_pin_obj_t pin_PA03 = PIN(0, 3, ADC_INPUT(ADC_1,3)); -const mcu_pin_obj_t pin_PA04 = PIN(0, 4, ADC_INPUT(ADC_1,4)); -const mcu_pin_obj_t pin_PA05 = PIN(0, 5, ADC_INPUT(ADC_1,5)); -const mcu_pin_obj_t pin_PA06 = PIN(0, 6, ADC_INPUT(ADC_1,6)); -const mcu_pin_obj_t pin_PA07 = PIN(0, 7, ADC_INPUT(ADC_1,7)); - -const mcu_pin_obj_t pin_PC04 = PIN(2, 4, ADC_INPUT(ADC_1,14)); -const mcu_pin_obj_t pin_PC05 = PIN(2, 5, ADC_INPUT(ADC_1,15)); - -const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_1,8)); -const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_1,9)); -const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); - -const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); // 144 only - -const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); // 144 only - -const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); -const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); -const mcu_pin_obj_t pin_PE09 = PIN(4, 9, NO_ADC); -const mcu_pin_obj_t pin_PE10 = PIN(4, 10, NO_ADC); -const mcu_pin_obj_t pin_PE11 = PIN(4, 11, NO_ADC); -const mcu_pin_obj_t pin_PE12 = PIN(4, 12, NO_ADC); -const mcu_pin_obj_t pin_PE13 = PIN(4, 13, NO_ADC); -const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC); -const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC); - -const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); -const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); -const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); -const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); -const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC); - -const mcu_pin_obj_t pin_PD08 = PIN(3, 8, NO_ADC); -const mcu_pin_obj_t pin_PD09 = PIN(3, 9, NO_ADC); -const mcu_pin_obj_t pin_PD10 = PIN(3, 10, NO_ADC); -const mcu_pin_obj_t pin_PD11 = PIN(3, 11, NO_ADC); -const mcu_pin_obj_t pin_PD12 = PIN(3, 12, NO_ADC); -const mcu_pin_obj_t pin_PD13 = PIN(3, 13, NO_ADC); -const mcu_pin_obj_t pin_PD14 = PIN(3, 14, NO_ADC); -const mcu_pin_obj_t pin_PD15 = PIN(3, 15, NO_ADC); - -const mcu_pin_obj_t pin_PG02 = PIN(6, 2, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG03 = PIN(6, 3, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG04 = PIN(6, 4, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG05 = PIN(6, 5, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG06 = PIN(6, 6, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG07 = PIN(6, 7, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG08 = PIN(6, 8, NO_ADC); // 144 only - -const mcu_pin_obj_t pin_PC06 = PIN(2, 6, NO_ADC); -const mcu_pin_obj_t pin_PC07 = PIN(2, 7, NO_ADC); -const mcu_pin_obj_t pin_PC08 = PIN(2, 8, NO_ADC); -const mcu_pin_obj_t pin_PC09 = PIN(2, 9, NO_ADC); - -const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC); -const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); -const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); -const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); -const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); -const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); -const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); -const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); - -const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC); -const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC); -const mcu_pin_obj_t pin_PC12 = PIN(2, 12, NO_ADC); - -const mcu_pin_obj_t pin_PD00 = PIN(3, 0, NO_ADC); -const mcu_pin_obj_t pin_PD01 = PIN(3, 1, NO_ADC); -const mcu_pin_obj_t pin_PD02 = PIN(3, 2, NO_ADC); -const mcu_pin_obj_t pin_PD03 = PIN(3, 3, NO_ADC); -const mcu_pin_obj_t pin_PD04 = PIN(3, 4, NO_ADC); -const mcu_pin_obj_t pin_PD05 = PIN(3, 5, NO_ADC); -const mcu_pin_obj_t pin_PD06 = PIN(3, 6, NO_ADC); -const mcu_pin_obj_t pin_PD07 = PIN(3, 7, NO_ADC); - -const mcu_pin_obj_t pin_PG09 = PIN(6, 9, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG10 = PIN(6, 10, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG11 = PIN(6, 11, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG12 = PIN(6, 12, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG13 = PIN(6, 13, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG14 = PIN(6, 14, NO_ADC); // 144 only -const mcu_pin_obj_t pin_PG15 = PIN(6, 15, NO_ADC); // 144 only - -const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC); -const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC); -const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC); -const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC); -const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC); -const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); -const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); - -const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC); -const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h deleted file mode 100644 index 07c22d528..000000000 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/pins.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H - -//Pins in datasheet order: DocID028087 Rev 7 page 50. LQFP100 only -//pg 50 -extern const mcu_pin_obj_t pin_PE02; -extern const mcu_pin_obj_t pin_PE03; -extern const mcu_pin_obj_t pin_PE04; -extern const mcu_pin_obj_t pin_PE05; -extern const mcu_pin_obj_t pin_PE06; -extern const mcu_pin_obj_t pin_PC13; -extern const mcu_pin_obj_t pin_PC14; -//pg 51 -extern const mcu_pin_obj_t pin_PC15; -extern const mcu_pin_obj_t pin_PF00; // 144 only -extern const mcu_pin_obj_t pin_PF01; // 144 only -extern const mcu_pin_obj_t pin_PF02; // 144 only -extern const mcu_pin_obj_t pin_PF03; // 144 only -extern const mcu_pin_obj_t pin_PF04; // 144 only -extern const mcu_pin_obj_t pin_PF05; // 144 only -extern const mcu_pin_obj_t pin_PF06; // 144 only -extern const mcu_pin_obj_t pin_PF07; // 144 only -extern const mcu_pin_obj_t pin_PF08; // 144 only -extern const mcu_pin_obj_t pin_PF09; // 144 only -extern const mcu_pin_obj_t pin_PF10; // 144 only -//pg 52 -extern const mcu_pin_obj_t pin_PC00; -extern const mcu_pin_obj_t pin_PC01; -extern const mcu_pin_obj_t pin_PC02; -extern const mcu_pin_obj_t pin_PC03; -extern const mcu_pin_obj_t pin_PA00; -extern const mcu_pin_obj_t pin_PA01; -extern const mcu_pin_obj_t pin_PA02; -//pg 53 -extern const mcu_pin_obj_t pin_PA03; -extern const mcu_pin_obj_t pin_PA04; -extern const mcu_pin_obj_t pin_PA05; -extern const mcu_pin_obj_t pin_PA06; -extern const mcu_pin_obj_t pin_PA07; -extern const mcu_pin_obj_t pin_PC04; -//pg 54 -extern const mcu_pin_obj_t pin_PC05; -extern const mcu_pin_obj_t pin_PB00; -extern const mcu_pin_obj_t pin_PB01; -extern const mcu_pin_obj_t pin_PB02; -extern const mcu_pin_obj_t pin_PF11; // 144 only -extern const mcu_pin_obj_t pin_PF12; // 144 only -extern const mcu_pin_obj_t pin_PF13; // 144 only -extern const mcu_pin_obj_t pin_PF14; // 144 only -extern const mcu_pin_obj_t pin_PF15; // 144 only -extern const mcu_pin_obj_t pin_PG00; // 144 only -extern const mcu_pin_obj_t pin_PG01; // 144 only -//pg 55 -extern const mcu_pin_obj_t pin_PE07; -extern const mcu_pin_obj_t pin_PE08; -extern const mcu_pin_obj_t pin_PE09; -extern const mcu_pin_obj_t pin_PE10; -extern const mcu_pin_obj_t pin_PE11; -extern const mcu_pin_obj_t pin_PE12; -extern const mcu_pin_obj_t pin_PE13; -extern const mcu_pin_obj_t pin_PE14; -//pg 56 -extern const mcu_pin_obj_t pin_PE15; -extern const mcu_pin_obj_t pin_PB10; -extern const mcu_pin_obj_t pin_PB11; // 144 only -extern const mcu_pin_obj_t pin_PB12; -extern const mcu_pin_obj_t pin_PB13; -//pg 57 -extern const mcu_pin_obj_t pin_PB14; -extern const mcu_pin_obj_t pin_PB15; -extern const mcu_pin_obj_t pin_PD08; -extern const mcu_pin_obj_t pin_PD09; -extern const mcu_pin_obj_t pin_PD10; -extern const mcu_pin_obj_t pin_PD11; -extern const mcu_pin_obj_t pin_PD12; -//pg 58 -extern const mcu_pin_obj_t pin_PD13; -extern const mcu_pin_obj_t pin_PD14; -extern const mcu_pin_obj_t pin_PD15; -extern const mcu_pin_obj_t pin_PG02; // 144 only -extern const mcu_pin_obj_t pin_PG03; // 144 only -extern const mcu_pin_obj_t pin_PG04; // 144 only -extern const mcu_pin_obj_t pin_PG05; // 144 only -extern const mcu_pin_obj_t pin_PG06; // 144 only -extern const mcu_pin_obj_t pin_PG07; // 144 only -extern const mcu_pin_obj_t pin_PG08; // 144 only -//pg 59 -extern const mcu_pin_obj_t pin_PC06; -extern const mcu_pin_obj_t pin_PC07; -extern const mcu_pin_obj_t pin_PC08; -extern const mcu_pin_obj_t pin_PC09; -extern const mcu_pin_obj_t pin_PA08; -extern const mcu_pin_obj_t pin_PA09; -extern const mcu_pin_obj_t pin_PA10; -//pg 60 -extern const mcu_pin_obj_t pin_PA11; -extern const mcu_pin_obj_t pin_PA12; -extern const mcu_pin_obj_t pin_PA13; -extern const mcu_pin_obj_t pin_PA14; -extern const mcu_pin_obj_t pin_PA15; -extern const mcu_pin_obj_t pin_PC10; -extern const mcu_pin_obj_t pin_PC11; -//pg 61 -extern const mcu_pin_obj_t pin_PC12; -extern const mcu_pin_obj_t pin_PD00; -extern const mcu_pin_obj_t pin_PD01; -extern const mcu_pin_obj_t pin_PD02; -extern const mcu_pin_obj_t pin_PD03; -extern const mcu_pin_obj_t pin_PD04; -extern const mcu_pin_obj_t pin_PD05; -extern const mcu_pin_obj_t pin_PD06; -extern const mcu_pin_obj_t pin_PD07; -//pg 62 -extern const mcu_pin_obj_t pin_PG09; // 144 only -extern const mcu_pin_obj_t pin_PG10; // 144 only -extern const mcu_pin_obj_t pin_PG11; // 144 only -extern const mcu_pin_obj_t pin_PG12; // 144 only -extern const mcu_pin_obj_t pin_PG13; // 144 only -extern const mcu_pin_obj_t pin_PG14; // 144 only -extern const mcu_pin_obj_t pin_PG15; // 144 only -extern const mcu_pin_obj_t pin_PB03; -extern const mcu_pin_obj_t pin_PB04; -//pg 63 -extern const mcu_pin_obj_t pin_PB05; -extern const mcu_pin_obj_t pin_PB06; -extern const mcu_pin_obj_t pin_PB07; -extern const mcu_pin_obj_t pin_PB08; -extern const mcu_pin_obj_t pin_PB09; -extern const mcu_pin_obj_t pin_PE00; -extern const mcu_pin_obj_t pin_PE01; - -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H -- cgit v1.2.3 From 284073584a66c0fde03e439fbdb54a4a5dc34790 Mon Sep 17 00:00:00 2001 From: jgillick Date: Thu, 19 Mar 2020 00:01:32 -0700 Subject: Cleanup --- ports/stm/boards/thunderpack/mpconfigboard.mk | 2 +- ports/stm/common-hal/busio/UART.c | 4 ---- ports/stm/peripherals/stm32f4/periph.h | 7 ------- ports/stm/peripherals/stm32f4/pins.h | 3 --- ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 1 + ports/stm/supervisor/internal_flash.h | 2 +- 6 files changed, 3 insertions(+), 16 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index 3efd6a8bd..0bf5b57a8 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -1,6 +1,6 @@ USB_VID = 0x239A USB_PID = 0x806A -USB_PRODUCT = "Thunderpack powered by ST" +USB_PRODUCT = "Thunderpack STM32F411" USB_MANUFACTURER = "Jeremy Gillick" USB_DEVICES = "CDC,MSC" diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c index 20648bf3d..0b434fd02 100644 --- a/ports/stm/common-hal/busio/UART.c +++ b/ports/stm/common-hal/busio/UART.c @@ -443,11 +443,9 @@ STATIC void uart_clock_enable(uint16_t mask) { #endif #ifdef USART3 if (mask & (1 << 2)) { - #ifndef STM32F412Cx __HAL_RCC_USART3_FORCE_RESET(); __HAL_RCC_USART3_RELEASE_RESET(); __HAL_RCC_USART3_CLK_ENABLE(); - #endif } #endif #ifdef UART4 @@ -518,11 +516,9 @@ STATIC void uart_clock_disable(uint16_t mask) { #endif #ifdef USART3 if (mask & (1 << 2)) { - #ifndef STM32F412Cx __HAL_RCC_USART3_FORCE_RESET(); __HAL_RCC_USART3_RELEASE_RESET(); __HAL_RCC_USART3_CLK_DISABLE(); - #endif } #endif #ifdef UART4 diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h index 5ac8b4061..d311afe4a 100644 --- a/ports/stm/peripherals/stm32f4/periph.h +++ b/ports/stm/peripherals/stm32f4/periph.h @@ -154,13 +154,6 @@ typedef struct { #include "stm32f411xe/periph.h" #endif -#ifdef BOARD_THUNDERPACK_STM32F412 -#define HAS_DAC 0 -#define HAS_TRNG 1 -#define HAS_BASIC_TIM 1 -#include "stm32f412cx_thunderpack/periph.h" -#endif - #ifdef STM32F412Zx #define HAS_DAC 0 #define HAS_TRNG 1 diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/stm32f4/pins.h index 53040995d..44ef4c1ba 100644 --- a/ports/stm/peripherals/stm32f4/pins.h +++ b/ports/stm/peripherals/stm32f4/pins.h @@ -83,9 +83,6 @@ extern const mp_obj_type_t mcu_pin_type; #ifdef STM32F411xE #include "stm32f411xe/pins.h" #endif -#ifdef BOARD_THUNDERPACK_STM32F412 -#include "stm32f412cx_thunderpack/pins.h" -#endif #ifdef STM32F412Zx #include "stm32f412zx/pins.h" #endif diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index 2eb296723..68a75f463 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -239,3 +239,4 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { default: break; } } + diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 92d1baddc..9f16a799d 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -42,7 +42,7 @@ #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #endif -#if (defined(STM32F412Zx) || defined(STM32F412Cx)) +#ifdef STM32F412Zx #define STM32_FLASH_SIZE 0x100000 //1MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #endif -- cgit v1.2.3 From d9e491a9e863509f240609f6d69fb21de35fec32 Mon Sep 17 00:00:00 2001 From: jgillick Date: Thu, 19 Mar 2020 00:02:23 -0700 Subject: Remove unnecessary change --- ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c | 1 + 1 file changed, 1 insertion(+) (limited to 'ports/stm') diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index 68a75f463..d17ab4e01 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -240,3 +240,4 @@ void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { } } + -- cgit v1.2.3 From d76b76cb1db59b85ef1300f6afb1aee97e5e0c72 Mon Sep 17 00:00:00 2001 From: jgillick Date: Sun, 22 Mar 2020 02:22:59 -0700 Subject: Add non-volatile memory support to STM --- ports/stm/boards/STM32F411VETx_nvm_FLASH.ld | 118 ++++++++++++++++++++++++ ports/stm/boards/thunderpack/mpconfigboard.h | 11 ++- ports/stm/boards/thunderpack/mpconfigboard.mk | 4 +- ports/stm/common-hal/microcontroller/__init__.c | 12 +++ ports/stm/common-hal/nvm/ByteArray.c | 73 +++++++++++++++ ports/stm/common-hal/nvm/ByteArray.h | 43 +++++++++ ports/stm/common-hal/nvm/__init__.c | 27 ++++++ ports/stm/supervisor/internal_flash.h | 4 + 8 files changed, 286 insertions(+), 6 deletions(-) create mode 100644 ports/stm/boards/STM32F411VETx_nvm_FLASH.ld create mode 100644 ports/stm/common-hal/nvm/ByteArray.c create mode 100644 ports/stm/common-hal/nvm/ByteArray.h create mode 100644 ports/stm/common-hal/nvm/__init__.c (limited to 'ports/stm') diff --git a/ports/stm/boards/STM32F411VETx_nvm_FLASH.ld b/ports/stm/boards/STM32F411VETx_nvm_FLASH.ld new file mode 100644 index 000000000..8382cb781 --- /dev/null +++ b/ports/stm/boards/STM32F411VETx_nvm_FLASH.ld @@ -0,0 +1,118 @@ +/* + GNU linker script for STM32F411 via Micropython +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ + FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 32K /* sectors 1,2 are 16K */ + FLASH_NVM (rwx) : ORIGIN = 0x0800C000, LENGTH = 16K /* sector 3 is 16K */ + FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 448K /* sector 4 is 64K, sectors 5,6,7 are 128K */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define the top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = _ebss; /* heap starts just after statically allocated memory */ +_heap_end = 0x2001c000; /* tunable */ + +ENTRY(Reset_Handler) + +/* define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + + /* This first flash block is 16K annd the isr vectors only take up + about 400 bytes. Micropython pads this with files, but this didn't + work with the size of Circuitpython's ff object. */ + + . = ALIGN(4); + } >FLASH_ISR + + /* Non-volitile memory */ + .nvm_data : + { + . = ALIGN(4); + KEEP(*(.nvm_data)) + . = ALIGN(4); + } >FLASH_NVM + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text*) /* .text* sections (code) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + /* *(.glue_7) */ /* glue arm to thumb code */ + /* *(.glue_7t) */ /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH_TEXT + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM AT> FLASH_TEXT + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start; used by startup code */ + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ + } >RAM + + /* this is to define the start of the heap, and make sure we have a minimum size */ + .heap : + { + . = ALIGN(4); + . = . + _minimum_heap_size; + . = ALIGN(4); + } >RAM + + /* this just checks there is enough RAM for the stack */ + .stack : + { + . = ALIGN(4); + . = . + _minimum_stack_size; + . = ALIGN(4); + } >RAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h index 0e66f2a71..62bf7609d 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.h +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -26,17 +26,18 @@ #define MICROPY_HW_BOARD_NAME "THUNDERPACK" #define MICROPY_HW_MCU_NAME "STM32F411CE" -#define FLASH_SIZE (0x80000) -#define FLASH_PAGE_SIZE (0x4000) -#define BOARD_FLASH_SIZE (FLASH_SIZE - 0x2000 - 0xC000) +#define FLASH_SIZE (0x80000) +#define FLASH_PAGE_SIZE (0x4000) +#define CIRCUITPY_INTERNAL_NVM_SIZE (0x4000) +#define CIRCUITPY_INTERNAL_NVM_START_ADDR (0x0800C000) +#define CIRCUITPY_INTERNAL_NVM_SECTOR FLASH_SECTOR_3 +#define BOARD_FLASH_SIZE (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000) #define BOARD_OSC_DIV (24) #define BOARD_OVERWRITE_SWD (1) #define BOARD_NO_VBUS_SENSE (1) // Status LEDs -#define MICROPY_HW_LED_TX (&pin_PA00) -#define MICROPY_HW_LED_RX (&pin_PB01) #define MICROPY_HW_LED_STATUS (&pin_PA02) #define DEFAULT_I2C_BUS_SCL (&pin_PB06) diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index 0bf5b57a8..6fcaae6ab 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -7,12 +7,14 @@ USB_DEVICES = "CDC,MSC" INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = NONE +CIRCUITPY_NVM = 1 + MCU_SERIES = m4 MCU_VARIANT = stm32f4 MCU_SUB_VARIANT = stm32f411xe MCU_PACKAGE = 48 CMSIS_MCU = STM32F411xE -LD_FILE = boards/STM32F411VETx_FLASH.ld +LD_FILE = boards/STM32F411VETx_nvm_FLASH.ld STARTUP_FILE = startup_stm32f411xe.s diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c index 0c680eb05..85e66fb00 100644 --- a/ports/stm/common-hal/microcontroller/__init__.c +++ b/ports/stm/common-hal/microcontroller/__init__.c @@ -32,6 +32,7 @@ #include "common-hal/microcontroller/Pin.h" #include "common-hal/microcontroller/Processor.h" +#include "shared-bindings/nvm/ByteArray.h" #include "shared-bindings/microcontroller/__init__.h" #include "shared-bindings/microcontroller/Pin.h" #include "shared-bindings/microcontroller/Processor.h" @@ -109,6 +110,17 @@ const mcu_processor_obj_t common_hal_mcu_processor_obj = { }, }; +#if CIRCUITPY_INTERNAL_NVM_SIZE > 0 +// The singleton nvm.ByteArray object. +const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { + .base = { + .type = &nvm_bytearray_type, + }, + .len = NVM_BYTEARRAY_BUFFER, + .start_address = (uint8_t*) (CIRCUITPY_INTERNAL_NVM_START_ADDR) +}; +#endif + STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { #if MCU_PACKAGE >= 100 { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, diff --git a/ports/stm/common-hal/nvm/ByteArray.c b/ports/stm/common-hal/nvm/ByteArray.c new file mode 100644 index 000000000..1aaf54653 --- /dev/null +++ b/ports/stm/common-hal/nvm/ByteArray.c @@ -0,0 +1,73 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "common-hal/nvm/ByteArray.h" + +#include "stm32f4xx_hal.h" + +#include "supervisor/shared/stack.h" + +#include +#include + +uint32_t common_hal_nvm_bytearray_get_length(nvm_bytearray_obj_t *self) { + return self->len; +} + +bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, + uint32_t start_index, uint8_t* values, uint32_t len) { + // Copy flash to buffer + uint8_t buffer[self->len]; + memcpy(buffer, self->start_address, self->len); + + // Set bytes in buffer + memmove(buffer + start_index, values, len); + + // Erase flash sector + HAL_FLASH_Unlock(); + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR ); + FLASH_Erase_Sector(CIRCUITPY_INTERNAL_NVM_SECTOR, VOLTAGE_RANGE_3); + + // Write bytes to flash + uint32_t i; + uint32_t flash_addr = (uint32_t)self->start_address; + for (i = 0; i < self->len; i++, flash_addr++) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, flash_addr, buffer[i]) != HAL_OK) { + HAL_FLASH_Lock(); + return false; + } + } + + // Finish up + HAL_FLASH_Lock(); + return true; +} + +// NVM memory is memory mapped so reading it is easy. +void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t *self, + uint32_t start_index, uint32_t len, uint8_t* values) { + memcpy(values, self->start_address + start_index, len); +} diff --git a/ports/stm/common-hal/nvm/ByteArray.h b/ports/stm/common-hal/nvm/ByteArray.h new file mode 100644 index 000000000..8ad64cb81 --- /dev/null +++ b/ports/stm/common-hal/nvm/ByteArray.h @@ -0,0 +1,43 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_NVM_BYTEARRAY_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_NVM_BYTEARRAY_H + +#include "py/obj.h" + +// STM flash is saved in sectors (not pages), at a minimum size of 16k. +// To limit the RAM usage during writing, we want to set a smaller +// maximum value. +#define NVM_BYTEARRAY_BUFFER 512 + +typedef struct { + mp_obj_base_t base; + uint8_t* start_address; + uint32_t len; +} nvm_bytearray_obj_t; + +#endif // MICROPY_INCLUDED_STM32_COMMON_HAL_NVM_BYTEARRAY_H diff --git a/ports/stm/common-hal/nvm/__init__.c b/ports/stm/common-hal/nvm/__init__.c new file mode 100644 index 000000000..f0792430f --- /dev/null +++ b/ports/stm/common-hal/nvm/__init__.c @@ -0,0 +1,27 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// No nvm module functions. diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 9f16a799d..859470ff0 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -39,8 +39,12 @@ #ifdef STM32F411xE #define STM32_FLASH_SIZE 0x80000 //512KiB +#ifdef CIRCUITPY_NVM +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x8000 //32KiB +#else #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #endif +#endif #ifdef STM32F412Zx #define STM32_FLASH_SIZE 0x100000 //1MB -- cgit v1.2.3 From 68195a8dfe0bec239a38cc01ad2b74160bbdacd6 Mon Sep 17 00:00:00 2001 From: jgillick Date: Sun, 22 Mar 2020 15:19:53 -0700 Subject: Update NVM_BYTEARRAY_BUFFER_LEN --- ports/stm/boards/thunderpack/mpconfigboard.h | 11 +++++++++-- ports/stm/common-hal/microcontroller/__init__.c | 2 +- ports/stm/common-hal/nvm/ByteArray.h | 4 +++- 3 files changed, 13 insertions(+), 4 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h index 62bf7609d..270600b3c 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.h +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -26,11 +26,18 @@ #define MICROPY_HW_BOARD_NAME "THUNDERPACK" #define MICROPY_HW_MCU_NAME "STM32F411CE" -#define FLASH_SIZE (0x80000) -#define FLASH_PAGE_SIZE (0x4000) +// Non-volatile memory config #define CIRCUITPY_INTERNAL_NVM_SIZE (0x4000) #define CIRCUITPY_INTERNAL_NVM_START_ADDR (0x0800C000) #define CIRCUITPY_INTERNAL_NVM_SECTOR FLASH_SECTOR_3 + +// Putting the entire flash sector in the NVM byte array buffer +// would take up too much RAM. This limits how much of the sector we use. +#define NVM_BYTEARRAY_BUFFER_LEN 512 + +// Flash config +#define FLASH_SIZE (0x80000) +#define FLASH_PAGE_SIZE (0x4000) #define BOARD_FLASH_SIZE (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000) #define BOARD_OSC_DIV (24) diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c index 85e66fb00..b69407eff 100644 --- a/ports/stm/common-hal/microcontroller/__init__.c +++ b/ports/stm/common-hal/microcontroller/__init__.c @@ -116,7 +116,7 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .base = { .type = &nvm_bytearray_type, }, - .len = NVM_BYTEARRAY_BUFFER, + .len = NVM_BYTEARRAY_BUFFER_LEN, .start_address = (uint8_t*) (CIRCUITPY_INTERNAL_NVM_START_ADDR) }; #endif diff --git a/ports/stm/common-hal/nvm/ByteArray.h b/ports/stm/common-hal/nvm/ByteArray.h index 8ad64cb81..0d7ecf6ab 100644 --- a/ports/stm/common-hal/nvm/ByteArray.h +++ b/ports/stm/common-hal/nvm/ByteArray.h @@ -32,7 +32,9 @@ // STM flash is saved in sectors (not pages), at a minimum size of 16k. // To limit the RAM usage during writing, we want to set a smaller // maximum value. -#define NVM_BYTEARRAY_BUFFER 512 +#ifndef NVM_BYTEARRAY_BUFFER_LEN +#define NVM_BYTEARRAY_BUFFER_LEN 512 +#endif typedef struct { mp_obj_base_t base; -- cgit v1.2.3 From a79ac35173d29b473f64492b089f74e88a13d8bd Mon Sep 17 00:00:00 2001 From: jgillick Date: Sun, 22 Mar 2020 15:20:58 -0700 Subject: Rename NVM_BYTEARRAY_BUFFER_SIZE --- ports/stm/boards/thunderpack/mpconfigboard.h | 2 +- ports/stm/common-hal/microcontroller/__init__.c | 2 +- ports/stm/common-hal/nvm/ByteArray.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/boards/thunderpack/mpconfigboard.h b/ports/stm/boards/thunderpack/mpconfigboard.h index 270600b3c..0b3c55819 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.h +++ b/ports/stm/boards/thunderpack/mpconfigboard.h @@ -33,7 +33,7 @@ // Putting the entire flash sector in the NVM byte array buffer // would take up too much RAM. This limits how much of the sector we use. -#define NVM_BYTEARRAY_BUFFER_LEN 512 +#define NVM_BYTEARRAY_BUFFER_SIZE 512 // Flash config #define FLASH_SIZE (0x80000) diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c index b69407eff..d407ecfe5 100644 --- a/ports/stm/common-hal/microcontroller/__init__.c +++ b/ports/stm/common-hal/microcontroller/__init__.c @@ -116,7 +116,7 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .base = { .type = &nvm_bytearray_type, }, - .len = NVM_BYTEARRAY_BUFFER_LEN, + .len = NVM_BYTEARRAY_BUFFER_SIZE, .start_address = (uint8_t*) (CIRCUITPY_INTERNAL_NVM_START_ADDR) }; #endif diff --git a/ports/stm/common-hal/nvm/ByteArray.h b/ports/stm/common-hal/nvm/ByteArray.h index 0d7ecf6ab..b6ea36de3 100644 --- a/ports/stm/common-hal/nvm/ByteArray.h +++ b/ports/stm/common-hal/nvm/ByteArray.h @@ -32,8 +32,8 @@ // STM flash is saved in sectors (not pages), at a minimum size of 16k. // To limit the RAM usage during writing, we want to set a smaller // maximum value. -#ifndef NVM_BYTEARRAY_BUFFER_LEN -#define NVM_BYTEARRAY_BUFFER_LEN 512 +#ifndef NVM_BYTEARRAY_BUFFER_SIZE +#define NVM_BYTEARRAY_BUFFER_SIZE 512 #endif typedef struct { -- cgit v1.2.3 From 29ce7567098dd6b5b093b1bd5a3e0ff553c91801 Mon Sep 17 00:00:00 2001 From: jgillick Date: Sun, 22 Mar 2020 18:41:19 -0700 Subject: PR feedback. --- ports/stm/boards/thunderpack/pins.c | 8 ++++---- ports/stm/supervisor/usb.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c index 830e99dae..04394993e 100644 --- a/ports/stm/boards/thunderpack/pins.c +++ b/ports/stm/boards/thunderpack/pins.c @@ -10,10 +10,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, //USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, { MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_PA13) }, { MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_PA14) }, diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 6cb9feb4b..93b5ae769 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -85,7 +85,7 @@ void init_usb_hardware(void) { never_reset_pin_number(0, 12); /* Configure VBUS Pin */ -#if (BOARD_NO_VBUS_SENSE) +#if (BOARD_NO_VBUS_SENSE == 0) GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; -- cgit v1.2.3 From 8ed4deee9d49b477a1a11cea52248122caaef3d5 Mon Sep 17 00:00:00 2001 From: jgillick Date: Mon, 23 Mar 2020 23:06:55 -0700 Subject: Rename pins --- ports/stm/boards/thunderpack/pins.c | 35 ++++++++++++++++------------------- ports/stm/supervisor/usb.c | 2 +- 2 files changed, 17 insertions(+), 20 deletions(-) (limited to 'ports/stm') diff --git a/ports/stm/boards/thunderpack/pins.c b/ports/stm/boards/thunderpack/pins.c index 04394993e..559d9658e 100644 --- a/ports/stm/boards/thunderpack/pins.c +++ b/ports/stm/boards/thunderpack/pins.c @@ -1,26 +1,23 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA2), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA3), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA4), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA5), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA6), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA7), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PA8), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA9), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_B5), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_B6), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_B7), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_PB5), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB6), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB7), MP_ROM_PTR(&pin_PB07) }, { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PA00) }, { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PA01) }, diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 93b5ae769..8bfdcde40 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -85,7 +85,7 @@ void init_usb_hardware(void) { never_reset_pin_number(0, 12); /* Configure VBUS Pin */ -#if (BOARD_NO_VBUS_SENSE == 0) +#if !(BOARD_NO_VBUS_SENSE) GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; -- cgit v1.2.3 From 9e0c00dfd42504a53f000da374355829da7c7c77 Mon Sep 17 00:00:00 2001 From: siddacious Date: Wed, 25 Mar 2020 22:43:18 -0700 Subject: adding a backlight polarity flag to Display --- ports/atmel-samd/boards/hallowing_m0_express/board.c | 3 ++- ports/atmel-samd/boards/hallowing_m4_express/board.c | 3 ++- ports/atmel-samd/boards/monster_m4sk/board.c | 3 ++- ports/atmel-samd/boards/pewpew_m4/board.c | 3 ++- ports/atmel-samd/boards/pybadge/board.c | 3 ++- ports/atmel-samd/boards/pybadge_airlift/board.c | 3 ++- ports/atmel-samd/boards/pygamer/board.c | 3 ++- ports/atmel-samd/boards/pygamer_advance/board.c | 3 ++- ports/atmel-samd/boards/pyportal/board.c | 3 ++- ports/atmel-samd/boards/pyportal_titano/board.c | 3 ++- ports/atmel-samd/boards/ugame10/board.c | 3 ++- ports/nrf/boards/clue_nrf52840_express/board.c | 3 ++- ports/nrf/boards/ohs2020_badge/board.c | 11 +++++------ ports/stm/boards/meowbit_v121/board.c | 3 ++- shared-bindings/displayio/Display.c | 7 +++++-- shared-bindings/displayio/Display.h | 2 +- shared-module/displayio/Display.c | 5 ++++- shared-module/displayio/Display.h | 1 + 18 files changed, 42 insertions(+), 23 deletions(-) (limited to 'ports/stm') diff --git a/ports/atmel-samd/boards/hallowing_m0_express/board.c b/ports/atmel-samd/boards/hallowing_m0_express/board.c index b4c54062f..07546abf5 100644 --- a/ports/atmel-samd/boards/hallowing_m0_express/board.c +++ b/ports/atmel-samd/boards/hallowing_m0_express/board.c @@ -108,7 +108,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/hallowing_m4_express/board.c b/ports/atmel-samd/boards/hallowing_m4_express/board.c index 6bb2a591f..6822368d7 100644 --- a/ports/atmel-samd/boards/hallowing_m4_express/board.c +++ b/ports/atmel-samd/boards/hallowing_m4_express/board.c @@ -88,7 +88,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/monster_m4sk/board.c b/ports/atmel-samd/boards/monster_m4sk/board.c index 2377f4a9d..eeafdb4b8 100644 --- a/ports/atmel-samd/boards/monster_m4sk/board.c +++ b/ports/atmel-samd/boards/monster_m4sk/board.c @@ -89,7 +89,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/pewpew_m4/board.c b/ports/atmel-samd/boards/pewpew_m4/board.c index 5f5a01e48..ef259e27a 100644 --- a/ports/atmel-samd/boards/pewpew_m4/board.c +++ b/ports/atmel-samd/boards/pewpew_m4/board.c @@ -139,7 +139,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands false, // auto_refresh - 20); // native_frames_per_second + 20, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/pybadge/board.c b/ports/atmel-samd/boards/pybadge/board.c index bead06f3c..1209c027e 100644 --- a/ports/atmel-samd/boards/pybadge/board.c +++ b/ports/atmel-samd/boards/pybadge/board.c @@ -111,7 +111,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/pybadge_airlift/board.c b/ports/atmel-samd/boards/pybadge_airlift/board.c index 061f3d777..dfbf7023f 100644 --- a/ports/atmel-samd/boards/pybadge_airlift/board.c +++ b/ports/atmel-samd/boards/pybadge_airlift/board.c @@ -89,7 +89,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/pygamer/board.c b/ports/atmel-samd/boards/pygamer/board.c index 70d4a05dc..6df485fa9 100644 --- a/ports/atmel-samd/boards/pygamer/board.c +++ b/ports/atmel-samd/boards/pygamer/board.c @@ -111,7 +111,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/pygamer_advance/board.c b/ports/atmel-samd/boards/pygamer_advance/board.c index ff2da34a2..ad5abd3f6 100644 --- a/ports/atmel-samd/boards/pygamer_advance/board.c +++ b/ports/atmel-samd/boards/pygamer_advance/board.c @@ -89,7 +89,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/pyportal/board.c b/ports/atmel-samd/boards/pyportal/board.c index 2a7289778..a86f0ee48 100644 --- a/ports/atmel-samd/boards/pyportal/board.c +++ b/ports/atmel-samd/boards/pyportal/board.c @@ -100,7 +100,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/pyportal_titano/board.c b/ports/atmel-samd/boards/pyportal_titano/board.c index 828ceebc4..a9ded1760 100644 --- a/ports/atmel-samd/boards/pyportal_titano/board.c +++ b/ports/atmel-samd/boards/pyportal_titano/board.c @@ -117,7 +117,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/ugame10/board.c b/ports/atmel-samd/boards/ugame10/board.c index ce389a2b1..96f2361fd 100644 --- a/ports/atmel-samd/boards/ugame10/board.c +++ b/ports/atmel-samd/boards/ugame10/board.c @@ -108,7 +108,8 @@ void board_init(void) { false, // single_byte_bounds false, // data as commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/nrf/boards/clue_nrf52840_express/board.c b/ports/nrf/boards/clue_nrf52840_express/board.c index e342c6d93..03b212f9e 100644 --- a/ports/nrf/boards/clue_nrf52840_express/board.c +++ b/ports/nrf/boards/clue_nrf52840_express/board.c @@ -88,7 +88,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/nrf/boards/ohs2020_badge/board.c b/ports/nrf/boards/ohs2020_badge/board.c index c777d707a..106bbd6e1 100644 --- a/ports/nrf/boards/ohs2020_badge/board.c +++ b/ports/nrf/boards/ohs2020_badge/board.c @@ -81,16 +81,15 @@ void board_init(void) { 0x37, // set vertical scroll command display_init_sequence, sizeof(display_init_sequence), - //NULL, // backlight pin - &pin_P0_02, // backlight pin + &pin_P0_02, // backlight pin NO_BRIGHTNESS_COMMAND, - 0.0f, // brightness (ignored) - false, // auto_brightness + 1.0f, // brightness (ignored) + true, // auto_brightness false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second - + 60, // native_frames_per_second + false); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/ports/stm/boards/meowbit_v121/board.c b/ports/stm/boards/meowbit_v121/board.c index a0ae98824..da87f00ec 100644 --- a/ports/stm/boards/meowbit_v121/board.c +++ b/ports/stm/boards/meowbit_v121/board.c @@ -109,7 +109,8 @@ void board_init(void) { false, // single_byte_bounds false, // data_as_commands true, // auto_refresh - 60); // native_frames_per_second + 60, // native_frames_per_second + true); // backlight_on_high } bool board_requests_safe_mode(void) { diff --git a/shared-bindings/displayio/Display.c b/shared-bindings/displayio/Display.c index 991c828be..3ef7e74e9 100644 --- a/shared-bindings/displayio/Display.c +++ b/shared-bindings/displayio/Display.c @@ -104,9 +104,10 @@ //| :param bool data_as_commands: Treat all init and boundary data as SPI commands. Certain displays require this. //| :param bool auto_refresh: Automatically refresh the screen //| :param int native_frames_per_second: Number of display refreshes per second that occur with the given init_sequence. +//| :param bool backlight_on_high: If True, pulling the backlight pin high turns the backlight on. //| STATIC mp_obj_t displayio_display_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { - enum { ARG_display_bus, ARG_init_sequence, ARG_width, ARG_height, ARG_colstart, ARG_rowstart, ARG_rotation, ARG_color_depth, ARG_grayscale, ARG_pixels_in_byte_share_row, ARG_bytes_per_cell, ARG_reverse_pixels_in_byte, ARG_set_column_command, ARG_set_row_command, ARG_write_ram_command, ARG_set_vertical_scroll, ARG_backlight_pin, ARG_brightness_command, ARG_brightness, ARG_auto_brightness, ARG_single_byte_bounds, ARG_data_as_commands, ARG_auto_refresh, ARG_native_frames_per_second }; + enum { ARG_display_bus, ARG_init_sequence, ARG_width, ARG_height, ARG_colstart, ARG_rowstart, ARG_rotation, ARG_color_depth, ARG_grayscale, ARG_pixels_in_byte_share_row, ARG_bytes_per_cell, ARG_reverse_pixels_in_byte, ARG_set_column_command, ARG_set_row_command, ARG_write_ram_command, ARG_set_vertical_scroll, ARG_backlight_pin, ARG_brightness_command, ARG_brightness, ARG_auto_brightness, ARG_single_byte_bounds, ARG_data_as_commands, ARG_auto_refresh, ARG_native_frames_per_second, ARG_backlight_on_high }; static const mp_arg_t allowed_args[] = { { MP_QSTR_display_bus, MP_ARG_REQUIRED | MP_ARG_OBJ }, { MP_QSTR_init_sequence, MP_ARG_REQUIRED | MP_ARG_OBJ }, @@ -132,6 +133,7 @@ STATIC mp_obj_t displayio_display_make_new(const mp_obj_type_t *type, size_t n_a { MP_QSTR_data_as_commands, MP_ARG_BOOL | MP_ARG_KW_ONLY, {.u_bool = false} }, { MP_QSTR_auto_refresh, MP_ARG_BOOL | MP_ARG_KW_ONLY, {.u_bool = true} }, { MP_QSTR_native_frames_per_second, MP_ARG_INT | MP_ARG_KW_ONLY, {.u_int = 60} }, + { MP_QSTR_backlight_on_high, MP_ARG_BOOL | MP_ARG_KW_ONLY, {.u_bool = true} }, }; mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); @@ -178,7 +180,8 @@ STATIC mp_obj_t displayio_display_make_new(const mp_obj_type_t *type, size_t n_a args[ARG_single_byte_bounds].u_bool, args[ARG_data_as_commands].u_bool, args[ARG_auto_refresh].u_bool, - args[ARG_native_frames_per_second].u_int + args[ARG_native_frames_per_second].u_int, + args[ARG_backlight_on_high].u_bool ); return self; diff --git a/shared-bindings/displayio/Display.h b/shared-bindings/displayio/Display.h index b82a68ebe..8c2e20262 100644 --- a/shared-bindings/displayio/Display.h +++ b/shared-bindings/displayio/Display.h @@ -45,7 +45,7 @@ void common_hal_displayio_display_construct(displayio_display_obj_t* self, uint8_t set_column_command, uint8_t set_row_command, uint8_t write_ram_command, uint8_t set_vertical_scroll, uint8_t* init_sequence, uint16_t init_sequence_len, const mcu_pin_obj_t* backlight_pin, uint16_t brightness_command, mp_float_t brightness, bool auto_brightness, - bool single_byte_bounds, bool data_as_commands, bool auto_refresh, uint16_t native_frames_per_second); + bool single_byte_bounds, bool data_as_commands, bool auto_refresh, uint16_t native_frames_per_second, bool backlight_on_high); bool common_hal_displayio_display_show(displayio_display_obj_t* self, displayio_group_t* root_group); diff --git a/shared-module/displayio/Display.c b/shared-module/displayio/Display.c index 299c8ad35..820fbcce6 100644 --- a/shared-module/displayio/Display.c +++ b/shared-module/displayio/Display.c @@ -50,7 +50,7 @@ void common_hal_displayio_display_construct(displayio_display_obj_t* self, uint8_t set_row_command, uint8_t write_ram_command, uint8_t set_vertical_scroll, uint8_t* init_sequence, uint16_t init_sequence_len, const mcu_pin_obj_t* backlight_pin, uint16_t brightness_command, mp_float_t brightness, bool auto_brightness, - bool single_byte_bounds, bool data_as_commands, bool auto_refresh, uint16_t native_frames_per_second) { + bool single_byte_bounds, bool data_as_commands, bool auto_refresh, uint16_t native_frames_per_second, bool backlight_on_high) { // Turn off auto-refresh as we init. self->auto_refresh = false; uint16_t ram_width = 0x100; @@ -159,6 +159,9 @@ mp_float_t common_hal_displayio_display_get_brightness(displayio_display_obj_t* bool common_hal_displayio_display_set_brightness(displayio_display_obj_t* self, mp_float_t brightness) { self->updating_backlight = true; + if (!self->backlight_on_high){ + brightness = 1.0-brightness; + } bool ok = false; if (self->backlight_pwm.base.type == &pulseio_pwmout_type) { common_hal_pulseio_pwmout_set_duty_cycle(&self->backlight_pwm, (uint16_t) (0xffff * brightness)); diff --git a/shared-module/displayio/Display.h b/shared-module/displayio/Display.h index e5fe0a708..8adaf597f 100644 --- a/shared-module/displayio/Display.h +++ b/shared-module/displayio/Display.h @@ -55,6 +55,7 @@ typedef struct { bool data_as_commands; bool auto_brightness; bool updating_backlight; + bool backlight_on_high; } displayio_display_obj_t; void displayio_display_background(displayio_display_obj_t* self); -- cgit v1.2.3