summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJeff Epler <jepler@unpythonic.net>2021-03-26 10:54:13 -0500
committerJeff Epler <jepler@unpythonic.net>2021-03-26 10:54:13 -0500
commit231cb1ffd954dad45223bcc6fd22f344089536f1 (patch)
tree3cf0000ffeaf4acce5daf3029967fc2ae7c67314
parent1d48054aeaa2762a752462a058a27afb1daac860 (diff)
mimxrt10xx: Use the proper "betweenTransferDelay" (et al) values
Set the betweenTransferDelay to the SCK low-time, to avoid long pauses between bytes (transfers) while preventing the last SCK cycle in a byte from being a runt pulse. Compared to an earlier revision of this change, which just set the delays all to zero, this doesn't break using an AirLift, which was sensitive to the runt pulses (the simple loopback-wire test didn't detect the problem)
-rw-r--r--ports/mimxrt10xx/common-hal/busio/SPI.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/ports/mimxrt10xx/common-hal/busio/SPI.c b/ports/mimxrt10xx/common-hal/busio/SPI.c
index 13cc910d8..0783171c9 100644
--- a/ports/mimxrt10xx/common-hal/busio/SPI.c
+++ b/ports/mimxrt10xx/common-hal/busio/SPI.c
@@ -238,15 +238,10 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
baudrate = 30000000; // "Absolute maximum frequency of operation (fop) is 30 MHz" -- IMXRT1010CEC.pdf
}
- LPSPI_Enable(self->spi, false);
- uint32_t tcrPrescaleValue;
- self->baudrate = LPSPI_MasterSetBaudRate(self->spi, baudrate, LPSPI_MASTER_CLK_FREQ, &tcrPrescaleValue);
- self->spi->TCR = (self->spi->TCR & ~LPSPI_TCR_PRESCALE_MASK) | LPSPI_TCR_PRESCALE(tcrPrescaleValue);
- LPSPI_Enable(self->spi, true);
-
if ((polarity == common_hal_busio_spi_get_polarity(self)) &&
(phase == common_hal_busio_spi_get_phase(self)) &&
- (bits == ((self->spi->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT)) + 1) {
+ (bits == ((self->spi->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT)) + 1 &&
+ (baudrate == common_hal_busio_spi_get_frequency(self))) {
return true;
}
@@ -257,10 +252,22 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
config.cpol = polarity;
config.cpha = phase;
config.bitsPerFrame = bits;
+ // The between-transfer-delay must be equal to the SCK low-time.
+ // Setting it lower introduces runt pulses, while setting it higher
+ // wastes time.
+ config.betweenTransferDelayInNanoSec = 1000000000 / config.baudRate / 2;
LPSPI_Deinit(self->spi);
LPSPI_MasterInit(self->spi, &config, LPSPI_MASTER_CLK_FREQ);
+ // Recompute the actual baudrate so that we can set the baudrate
+ // (frequency) property. We don't need to set TCR because it was
+ // established by LPSPI_MasterInit, above
+ uint32_t tcrPrescaleValue;
+ LPSPI_Enable(self->spi, false);
+ self->baudrate = LPSPI_MasterSetBaudRate(self->spi, baudrate, LPSPI_MASTER_CLK_FREQ, &tcrPrescaleValue);
+ LPSPI_Enable(self->spi, true);
+
return true;
}