atmel-samd: Add basic support for experimental Metro M0 with an external flash chip.

12 files changed, 904 insertions, 0 deletions

diff --git a/atmel-samd/boards/metro_m0_flash/conf_access.h b/atmel-samd/boards/metro_m0_flash/conf_access.h
new file mode 100644
index 000000000..8cf104e69
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/conf_access.h
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Memory access control configuration file.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _CONF_ACCESS_H_
+#define _CONF_ACCESS_H_
+
+#include "compiler.h"
+#include "board.h"
+
+
+/*! \name Activation of Logical Unit Numbers
+ */
+//! @{
+#define LUN_0                ENABLE    //!< On-Chip Virtual Memory.
+#define LUN_1                DISABLE   //!< AT45DBX Data Flash.
+#define LUN_2                DISABLE   //!< SD/MMC Card over SPI.
+#define LUN_3                DISABLE   //!< SD/MMC Card over MCI Slot 0.
+#define LUN_4                DISABLE
+#define LUN_5                DISABLE
+#define LUN_6                DISABLE
+#define LUN_7                DISABLE
+#define LUN_USB              DISABLE   //!< Host Mass-Storage Memory.
+//! @}
+
+/*! \name LUN 0 Definitions
+ */
+//! @{
+#define LUN_0_INCLUDE                           "rom_fs.h"
+#define Lun_0_test_unit_ready                   rom_fs_test_unit_ready
+#define Lun_0_read_capacity                     rom_fs_read_capacity
+#define Lun_0_unload                            NULL /* Can not be unloaded */
+#define Lun_0_wr_protect                        rom_fs_wr_protect
+#define Lun_0_removal                           rom_fs_removal
+#define Lun_0_usb_read_10                       rom_fs_usb_read_10
+#define Lun_0_usb_write_10                      rom_fs_usb_write_10
+#define LUN_0_NAME                              "\"On-Chip ROM\""
+//! @}
+
+#define MEM_USB                                 LUN_USB
+
+/*! \name Actions Associated with Memory Accesses
+ *
+ * Write here the action to associate with each memory access.
+ *
+ * \warning Be careful not to waste time in order not to disturb the functions.
+ */
+//! @{
+#define memory_start_read_action(nb_sectors)
+#define memory_stop_read_action()
+#define memory_start_write_action(nb_sectors)
+#define memory_stop_write_action()
+//! @}
+
+/*! \name Activation of Interface Features
+ */
+//! @{
+#define ACCESS_USB           true    //!< MEM <-> USB interface.
+#define ACCESS_MEM_TO_RAM    false   //!< MEM <-> RAM interface.
+#define ACCESS_STREAM        false   //!< Streaming MEM <-> MEM interface.
+#define ACCESS_STREAM_RECORD false   //!< Streaming MEM <-> MEM interface in record mode.
+#define ACCESS_MEM_TO_MEM    false   //!< MEM <-> MEM interface.
+#define ACCESS_CODEC         false   //!< Codec interface.
+//! @}
+
+/*! \name Specific Options for Access Control
+ */
+//! @{
+#define GLOBAL_WR_PROTECT    false   //!< Management of a global write protection.
+//! @}
+
+
+#endif // _CONF_ACCESS_H_
diff --git a/atmel-samd/boards/metro_m0_flash/conf_board.h b/atmel-samd/boards/metro_m0_flash/conf_board.h
new file mode 100644
index 000000000..7b88c97fc
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/conf_board.h
@@ -0,0 +1,14 @@
+/**
+ * \file
+ *
+ * \brief User board configuration template
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_BOARD_H
+#define CONF_BOARD_H
+
+#endif // CONF_BOARD_H
diff --git a/atmel-samd/boards/metro_m0_flash/conf_clocks.h b/atmel-samd/boards/metro_m0_flash/conf_clocks.h
new file mode 100644
index 000000000..20ee967e2
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/conf_clocks.h
@@ -0,0 +1,197 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Clock configuration
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+#  define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+#  define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT     false
+#  define CONF_CLOCK_FLASH_WAIT_STATES            2
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+#  define CONF_CLOCK_XOSC32K_ENABLE               true
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            false
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       true
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+#  define CONF_CLOCK_DFLL_ENABLE                  true
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED
+#  define CONF_CLOCK_DFLL_ON_DEMAND               true
+
+/* DFLL open loop mode configuration */
+#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)
+
+/* DFLL closed loop mode configuration */
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32768)
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)
+
+/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
+#  define CONF_CLOCK_DPLL_ENABLE                  false
+#  define CONF_CLOCK_DPLL_ON_DEMAND               true
+#  define CONF_CLOCK_DPLL_RUN_IN_STANDBY          false
+#  define CONF_CLOCK_DPLL_LOCK_BYPASS             false
+#  define CONF_CLOCK_DPLL_WAKE_UP_FAST            false
+#  define CONF_CLOCK_DPLL_LOW_POWER_ENABLE        false
+
+#  define CONF_CLOCK_DPLL_LOCK_TIME               SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
+#  define CONF_CLOCK_DPLL_REFERENCE_CLOCK         SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
+#  define CONF_CLOCK_DPLL_FILTER                  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
+
+#  define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY     32768
+#  define CONF_CLOCK_DPLL_REFERENCE_DIVIDER       1
+#  define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY        48000000
+
+/* DPLL GCLK reference configuration */
+#  define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR  GCLK_GENERATOR_1
+/* DPLL GCLK lock timer configuration */
+#  define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR     GCLK_GENERATOR_1
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        true
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_DFLL
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 */
+#  define CONF_CLOCK_GCLK_1_ENABLE                true
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         true
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                false
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             32
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 */
+#  define CONF_CLOCK_GCLK_3_ENABLE                true
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 4 */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 8 */
+#  define CONF_CLOCK_GCLK_8_ENABLE                false
+#  define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_8_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_8_PRESCALER             1
+#  define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE         false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
diff --git a/atmel-samd/boards/metro_m0_flash/conf_sleepmgr.h b/atmel-samd/boards/metro_m0_flash/conf_sleepmgr.h
new file mode 100644
index 000000000..281a36078
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/conf_sleepmgr.h
@@ -0,0 +1,52 @@
+/**
+ * \file
+ *
+ * \brief Sleep manager configuration
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_SLEEPMGR_H_INCLUDED
+#define CONF_SLEEPMGR_H_INCLUDED
+
+#define CONFIG_SLEEPMGR_ENABLE
+
+#endif /* CONF_SLEEPMGR_H_INCLUDED */
diff --git a/atmel-samd/boards/metro_m0_flash/conf_usb.h b/atmel-samd/boards/metro_m0_flash/conf_usb.h
new file mode 100644
index 000000000..5ffa56f2a
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/conf_usb.h
@@ -0,0 +1,150 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifndef CONF_USB_H_INCLUDED
+#define CONF_USB_H_INCLUDED
+
+#define  USB_DEVICE_MAJOR_VERSION         1
+#define  USB_DEVICE_MINOR_VERSION         0
+#define  USB_DEVICE_POWER                 100 // Consumption on Vbus line (mA)
+#define  USB_DEVICE_ATTR                  \
+	(USB_CONFIG_ATTR_BUS_POWERED)
+//	(USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED)
+//	(USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED)
+
+//! USB Device string definitions (Optional)
+#ifndef USB_DEVICE_MANUFACTURE_NAME
+#  define USB_DEVICE_MANUFACTURE_NAME "Adafruit Industries"
+#endif
+
+#ifndef USB_DEVICE_PRODUCT_NAME
+#  define USB_DEVICE_PRODUCT_NAME "Metro M0 with Flash (Experimental)"
+#endif
+// #define  USB_DEVICE_SERIAL_NAME           "12...EF"
+#define  USB_DEVICE_GET_SERIAL_NAME_POINTER  serial_number
+#define  USB_DEVICE_GET_SERIAL_NAME_LENGTH   32
+extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH];
+
+//! Control endpoint size
+#define  USB_DEVICE_EP_CTRL_SIZE       64
+
+//! Two interfaces for this device (CDC COM + CDC DATA + MSC)
+#define  USB_DEVICE_NB_INTERFACE       3
+
+// (3 | USB_EP_DIR_IN)  // CDC Notify endpoint
+// (4 | USB_EP_DIR_IN)  // CDC TX
+// (5 | USB_EP_DIR_OUT) // CDC RX
+// (1 | USB_EP_DIR_IN)  // MSC IN
+// (2 | USB_EP_DIR_OUT) // MSC OUT
+#define  USB_DEVICE_MAX_EP           5
+
+#define UDI_CDC_PORT_NB 1
+#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port)
+extern bool mp_cdc_enable(uint8_t port);
+#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port)
+extern void mp_cdc_disable(uint8_t port);
+#define  UDI_CDC_LOW_RATE
+
+#define  UDI_CDC_DEFAULT_RATE             115200
+#define  UDI_CDC_DEFAULT_STOPBITS         CDC_STOP_BITS_1
+#define  UDI_CDC_DEFAULT_PARITY           CDC_PAR_NONE
+#define  UDI_CDC_DEFAULT_DATABITS         8
+
+#define  UDI_CDC_RX_NOTIFY(port)           usb_rx_notify()
+void usb_rx_notify(void);
+#define  UDI_CDC_SET_CODING_EXT(port,cfg)
+#define  UDI_CDC_SET_DTR_EXT(port,set)
+#define  UDI_CDC_SET_RTS_EXT(port,set)
+
+/**
+ * USB CDC low level configuration
+ * In standalone these configurations are defined by the CDC module.
+ * For composite device, these configuration must be defined here
+ * @{
+ */
+//! Endpoint numbers definition
+
+#define  UDI_CDC_COMM_EP_0             (3 | USB_EP_DIR_IN)  // Notify endpoint
+#define  UDI_CDC_DATA_EP_IN_0          (4 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_0         (5 | USB_EP_DIR_OUT) // RX
+
+//! Interface numbers
+#define  UDI_CDC_COMM_IFACE_NUMBER_0   0
+#define  UDI_CDC_DATA_IFACE_NUMBER_0   1
+
+/**
+ * Configuration of MSC interface
+ * @{
+ */
+//! Vendor name and Product version of MSC interface
+#define UDI_MSC_GLOBAL_VENDOR_ID            \
+   'A', 'T', 'M', 'E', 'L', ' ', ' ', ' '
+#define UDI_MSC_GLOBAL_PRODUCT_VERSION            \
+   '1', '.', '0', '0'
+
+//! Interface callback definition
+#define  UDI_MSC_ENABLE_EXT()          mp_msc_enable()
+extern bool mp_msc_enable();
+#define  UDI_MSC_DISABLE_EXT()         mp_msc_disable()
+extern void mp_msc_disable();
+
+//! Enable id string of interface to add an extra USB string
+#define  UDI_MSC_STRING_ID                5
+
+/**
+ * USB MSC low level configuration
+ * In standalone these configurations are defined by the MSC module.
+ * For composite device, these configuration must be defined here
+ * @{
+ */
+//! Endpoint numbers definition
+#define  UDI_MSC_EP_IN                 (1 | USB_EP_DIR_IN)
+#define  UDI_MSC_EP_OUT                (2 | USB_EP_DIR_OUT)
+
+//! Interface number
+#define  UDI_MSC_IFACE_NUMBER          2
+
+/**
+ * Description of Composite Device
+ * @{
+ */
+//! USB Interfaces descriptor structure
+#define UDI_COMPOSITE_DESC_T \
+	usb_iad_desc_t       udi_cdc_iad; \
+	udi_cdc_comm_desc_t  udi_cdc_comm; \
+	udi_cdc_data_desc_t  udi_cdc_data; \
+	udi_msc_desc_t       udi_msc
+
+//! USB Interfaces descriptor value for Full Speed
+#define UDI_COMPOSITE_DESC_FS \
+	.udi_cdc_iad   = UDI_CDC_IAD_DESC_0, \
+	.udi_cdc_comm  = UDI_CDC_COMM_DESC_0, \
+	.udi_cdc_data  = UDI_CDC_DATA_DESC_0_FS, \
+	.udi_msc       = UDI_MSC_DESC_FS
+
+//! USB Interfaces descriptor value for High Speed
+#define UDI_COMPOSITE_DESC_HS \
+	.udi_cdc_iad   = UDI_CDC_IAD_DESC_0, \
+	.udi_cdc_comm  = UDI_CDC_COMM_DESC_0, \
+	.udi_cdc_data  = UDI_CDC_DATA_DESC_0_HS, \
+	.udi_msc       = UDI_MSC_DESC_HS
+
+//! USB Interface APIs
+#define UDI_COMPOSITE_API \
+	&udi_api_cdc_comm, \
+	&udi_api_cdc_data, \
+	&udi_api_msc
+//@}
+
+/**
+ * USB Device Driver Configuration
+ * @{
+ */
+//@}
+
+//! The includes of classes and other headers must be done at the end of this file to avoid compile error
+#include "udi_cdc.h"
+#include "udi_msc.h"
+
+#endif
diff --git a/atmel-samd/boards/metro_m0_flash/init.c b/atmel-samd/boards/metro_m0_flash/init.c
new file mode 100644
index 000000000..af8b08ff7
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/init.c
@@ -0,0 +1,31 @@
+/**
+ * \file
+ *
+ * \brief User board initialization template
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "board.h"
+#include "conf_board.h"
+#include "mpconfigboard.h"
+#include "asf/sam0/drivers/port/port.h"
+
+void board_init(void)
+{
+    /* This function is meant to contain board-specific initialization code
+     * for, e.g., the I/O pins. The initialization can rely on application-
+     * specific board configuration, found in conf_board.h.
+     */
+    struct port_config pin_conf;
+    port_get_config_defaults(&pin_conf);
+
+    pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+    port_pin_set_config(MICROPY_HW_LED_TX, &pin_conf);
+    port_pin_set_output_level(MICROPY_HW_LED_TX, true);
+
+    port_pin_set_config(MICROPY_HW_LED_RX, &pin_conf);
+    port_pin_set_output_level(MICROPY_HW_LED_RX, true);
+}
diff --git a/atmel-samd/boards/metro_m0_flash/mpconfigboard.h b/atmel-samd/boards/metro_m0_flash/mpconfigboard.h
new file mode 100644
index 000000000..b577ca663
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/mpconfigboard.h
@@ -0,0 +1,10 @@
+// LEDs
+#define MICROPY_HW_LED1              PIN_PA17 // red
+// #define UART_REPL
+#define USB_REPL
+
+#define MICROPY_HW_BOARD_NAME "Adafruit Metro M0 with Flash (Experimental)"
+#define MICROPY_HW_MCU_NAME "samd21g18"
+
+#define MICROPY_HW_LED_TX   PIN_PA27
+#define MICROPY_HW_LED_RX   PIN_PB03
diff --git a/atmel-samd/boards/metro_m0_flash/mpconfigboard.mk b/atmel-samd/boards/metro_m0_flash/mpconfigboard.mk
new file mode 100644
index 000000000..253932c14
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/mpconfigboard.mk
@@ -0,0 +1,3 @@
+LD_FILE = boards/samd21x18-bootloader-external-flash.ld
+USB_VID = 0x239A
+USB_PID = 0x8015
diff --git a/atmel-samd/boards/metro_m0_flash/pins.c b/atmel-samd/boards/metro_m0_flash/pins.c
new file mode 100644
index 000000000..db0c6ee4c
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/pins.c
@@ -0,0 +1,192 @@
+#include "pins.h"
+#include "asf/sam0/drivers/system/system.h"
+
+PIN(PA02, true, ADC_POSITIVE_INPUT_PIN0, NO_TIMER, NO_TIMER, NO_SERCOM,
+    NO_SERCOM);
+PIN(PB08, true, ADC_POSITIVE_INPUT_PIN2,
+  TIMER(TC4, 0, 0, 0, PIN_PB08E_TC4_WO0, MUX_PB08E_TC4_WO0),
+  NO_TIMER,
+  SERCOM(SERCOM4, 0, PINMUX_PB08D_SERCOM4_PAD0),
+  NO_SERCOM);
+PIN(PB09, true, ADC_POSITIVE_INPUT_PIN3,
+  TIMER(TC4, 0, 1, 1, PIN_PB09E_TC4_WO1, MUX_PB09E_TC4_WO1),
+  NO_TIMER,
+  SERCOM(SERCOM4, 1, PINMUX_PB09D_SERCOM4_PAD1),
+  NO_SERCOM);
+PIN(PA04, true, ADC_POSITIVE_INPUT_PIN4,
+  TIMER(0, TCC0, 0, 0, PIN_PA04E_TCC0_WO0, MUX_PA04E_TCC0_WO0),
+  NO_TIMER,
+  SERCOM(SERCOM0, 0, PINMUX_PA04D_SERCOM0_PAD0),
+  NO_SERCOM);
+PIN(PA05, true, ADC_POSITIVE_INPUT_PIN5,
+  TIMER(0, TCC0, 1, 1, PIN_PA05E_TCC0_WO1, MUX_PA05E_TCC0_WO1),
+  NO_TIMER,
+  SERCOM(SERCOM0, 1, PINMUX_PA05D_SERCOM0_PAD1),
+  NO_SERCOM);
+PIN(PB02, true, ADC_POSITIVE_INPUT_PIN10,
+  NO_TIMER,
+  NO_TIMER,
+  SERCOM(SERCOM5, 0, PINMUX_PB02D_SERCOM5_PAD0),
+  NO_SERCOM);
+PIN(PA11, true, ADC_POSITIVE_INPUT_PIN19,
+  TIMER(0, TCC1, 1, 1, PIN_PA11E_TCC1_WO1, MUX_PA11E_TCC1_WO1),
+  TIMER(0, TCC0, 3, 3, PIN_PA11F_TCC0_WO3, MUX_PA11F_TCC0_WO3),
+  SERCOM(SERCOM0, 3, PINMUX_PA11C_SERCOM0_PAD3),
+  SERCOM(SERCOM2, 3, PINMUX_PA11D_SERCOM2_PAD3));
+PIN(PA10, true, ADC_POSITIVE_INPUT_PIN18,
+  TIMER(0, TCC1, 0, 0, PIN_PA10E_TCC1_WO0, MUX_PA10E_TCC1_WO0),
+  TIMER(0, TCC0, 2, 2, PIN_PA10F_TCC0_WO2, MUX_PA10F_TCC0_WO2),
+  SERCOM(SERCOM0, 2, PINMUX_PA10C_SERCOM0_PAD2),
+  SERCOM(SERCOM2, 2, PINMUX_PA10D_SERCOM2_PAD2));
+PIN(PA14, false, NO_ADC_INPUT,
+  TIMER(TC3, 0, 0, 0, PIN_PA14E_TC3_WO0, MUX_PA14E_TC3_WO0),
+  TIMER(0, TCC0, 0, 4, PIN_PA14F_TCC0_WO4, MUX_PA14F_TCC0_WO4),
+  SERCOM(SERCOM2, 2, PINMUX_PA14C_SERCOM2_PAD2),
+  SERCOM(SERCOM4, 2, PINMUX_PA14D_SERCOM4_PAD2));
+PIN(PA09, true, ADC_POSITIVE_INPUT_PIN17,
+  TIMER(0, TCC0, 1, 1, PIN_PA09E_TCC0_WO1, MUX_PA09E_TCC0_WO1),
+  TIMER(0, TCC1, 3, 3, PIN_PA09F_TCC1_WO3, MUX_PA09F_TCC1_WO3),
+  SERCOM(SERCOM0, 1, PINMUX_PA09C_SERCOM0_PAD1),
+  SERCOM(SERCOM2, 1, PINMUX_PA09D_SERCOM2_PAD1));
+PIN(PA08, true, ADC_POSITIVE_INPUT_PIN16,
+  TIMER(0, TCC0, 0, 0, PIN_PA08E_TCC0_WO0, MUX_PA08E_TCC0_WO0),
+  TIMER(0, TCC1, 2, 2, PIN_PA08F_TCC1_WO2, MUX_PA08F_TCC1_WO2),
+  SERCOM(SERCOM0, 0, PINMUX_PA08C_SERCOM0_PAD0),
+  SERCOM(SERCOM2, 0, PINMUX_PA08D_SERCOM2_PAD0));
+PIN(PA15, false, NO_ADC_INPUT,
+  TIMER(TC3, 0, 1, 1, PIN_PA15E_TC3_WO1, MUX_PA15E_TC3_WO1),
+  TIMER(0, TCC0, 1, 5, PIN_PA15F_TCC0_WO5, MUX_PA15F_TCC0_WO5),
+  SERCOM(SERCOM2, 3, PINMUX_PA15C_SERCOM2_PAD3),
+  SERCOM(SERCOM4, 3, PINMUX_PA15D_SERCOM4_PAD3));
+PIN(PA20, false, NO_ADC_INPUT,
+  TIMER(0, TCC0, 2, 6, PIN_PA20F_TCC0_WO6, MUX_PA20F_TCC0_WO6),
+  NO_TIMER,
+  SERCOM(SERCOM5, 2, PINMUX_PA20C_SERCOM5_PAD2),
+  SERCOM(SERCOM3, 2, PINMUX_PA20D_SERCOM3_PAD2));
+PIN(PA21, false, NO_ADC_INPUT,
+  TIMER(0, TCC0, 3, 7, PIN_PA21F_TCC0_WO7, MUX_PA21F_TCC0_WO7),
+  NO_TIMER,
+  SERCOM(SERCOM5, 3, PINMUX_PA21C_SERCOM5_PAD3),
+  SERCOM(SERCOM3, 3, PINMUX_PA21D_SERCOM3_PAD3));
+PIN(PA06, true, ADC_POSITIVE_INPUT_PIN6,
+  TIMER(0, TCC1, 0, 0, PIN_PA06E_TCC1_WO0, MUX_PA06E_TCC1_WO0),
+  NO_TIMER,
+  SERCOM(SERCOM0, 2, PINMUX_PA06D_SERCOM0_PAD2),
+  NO_SERCOM);
+PIN(PA07, true, ADC_POSITIVE_INPUT_PIN7,
+  TIMER(0, TCC1, 1, 1, PIN_PA07E_TCC1_WO1, MUX_PA07E_TCC1_WO1),
+  NO_TIMER,
+  SERCOM(SERCOM0, 3, PINMUX_PA07D_SERCOM0_PAD3),
+  NO_SERCOM);
+PIN(PA18, false, NO_ADC_INPUT,
+  TIMER(TC3, 0, 0, 0, PIN_PA18E_TC3_WO0, MUX_PA18E_TC3_WO0),
+  TIMER(0, TCC0, 2, 2, PIN_PA18F_TCC0_WO2, MUX_PA18F_TCC0_WO2),
+  SERCOM(SERCOM1, 2, PINMUX_PA18C_SERCOM1_PAD2),
+  SERCOM(SERCOM3, 2, PINMUX_PA18D_SERCOM3_PAD2));
+PIN(PA16, false, NO_ADC_INPUT,
+  TIMER(0, TCC2, 0, 0, PIN_PA16E_TCC2_WO0, MUX_PA16E_TCC2_WO0),
+  TIMER(0, TCC0, 2, 6, PIN_PA16F_TCC0_WO6, MUX_PA16F_TCC0_WO6),
+  SERCOM(SERCOM1, 0, PINMUX_PA16C_SERCOM1_PAD0),
+  SERCOM(SERCOM3, 0, PINMUX_PA16D_SERCOM3_PAD0));
+PIN(PA19, false, NO_ADC_INPUT,
+  TIMER(TC3, 0, 1, 1, PIN_PA19E_TC3_WO1, MUX_PA19E_TC3_WO1),
+  TIMER(0, TCC0, 3, 3, PIN_PA19F_TCC0_WO3, MUX_PA19F_TCC0_WO3),
+  SERCOM(SERCOM1, 3, PINMUX_PA19C_SERCOM1_PAD3),
+  SERCOM(SERCOM3, 3, PINMUX_PA19C_SERCOM1_PAD3));
+PIN(PA17, false, NO_ADC_INPUT,
+  TIMER(0, TCC2, 1, 1, PIN_PA17E_TCC2_WO1, MUX_PA17E_TCC2_WO1),
+  TIMER(0, TCC0, 3, 7, PIN_PA17F_TCC0_WO7, MUX_PA17F_TCC0_WO7),
+  SERCOM(SERCOM1, 1, PINMUX_PA17C_SERCOM1_PAD1),
+  SERCOM(SERCOM3, 1, PINMUX_PA17D_SERCOM3_PAD1));
+PIN(PA22, false, NO_ADC_INPUT,
+  TIMER(TC4, 0, 0, 0, PIN_PA22E_TC4_WO0, MUX_PA22E_TC4_WO0),
+  TIMER(0, TCC0, 0, 4, PIN_PA22F_TCC0_WO4, MUX_PA22F_TCC0_WO4),
+  SERCOM(SERCOM3, 0, PINMUX_PA22C_SERCOM3_PAD0),
+  SERCOM(SERCOM5, 0, PINMUX_PA22D_SERCOM5_PAD0));
+PIN(PA23, false, NO_ADC_INPUT,
+  TIMER(TC4, 0, 1, 1, PIN_PA23E_TC4_WO1, MUX_PA23E_TC4_WO1),
+  TIMER(0, TCC0, 1, 5, PIN_PA23F_TCC0_WO5, MUX_PA23F_TCC0_WO5),
+  SERCOM(SERCOM3, 1, PINMUX_PA23C_SERCOM3_PAD1),
+  SERCOM(SERCOM5, 1, PINMUX_PA23C_SERCOM3_PAD1));
+PIN(PB11, false, NO_ADC_INPUT,
+  TIMER(TC5, 0, 1, 1, PIN_PB11E_TC5_WO1, MUX_PB11E_TC5_WO1),
+  TIMER(0, TCC0, 1, 5, PIN_PB11F_TCC0_WO5, MUX_PB11F_TCC0_WO5),
+  SERCOM(SERCOM4, 3, PINMUX_PB11D_SERCOM4_PAD3),
+  NO_SERCOM);
+PIN(PB10, false, NO_ADC_INPUT,
+  TIMER(TC5, 0, 0, 0, PIN_PA23E_TC4_WO1, MUX_PA23E_TC4_WO1),
+  TIMER(0, TCC0, 0, 4, PIN_PA23F_TCC0_WO5, MUX_PA23F_TCC0_WO5),
+  SERCOM(SERCOM4, 2, PINMUX_PB10D_SERCOM4_PAD2),
+  NO_SERCOM);
+PIN(PA12, false, NO_ADC_INPUT,
+  TIMER(0, TCC2, 0, 0, PIN_PA12E_TCC2_WO0, MUX_PA12E_TCC2_WO0),
+  TIMER(0, TCC0, 2, 6, PIN_PA12F_TCC0_WO6, MUX_PA12F_TCC0_WO6),
+  SERCOM(SERCOM4, 0, PINMUX_PA12D_SERCOM4_PAD0),    
+  SERCOM(SERCOM2, 0, PINMUX_PA12C_SERCOM2_PAD0));
+PIN(PA13, false, NO_ADC_INPUT,
+  TIMER(0, TCC2, 1, 1, PIN_PA13E_TCC2_WO1, MUX_PA13E_TCC2_WO1),
+  TIMER(0, TCC0, 3, 7, PIN_PA13F_TCC0_WO7, MUX_PA13F_TCC0_WO7),
+  SERCOM(SERCOM4, 1, PINMUX_PA13D_SERCOM4_PAD1),
+  SERCOM(SERCOM2, 1, PINMUX_PA13C_SERCOM2_PAD1));
+
+STATIC const mp_map_elem_t pin_cpu_pins_locals_dict_table[] = {
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA02), (mp_obj_t)&pin_PA02 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PB08), (mp_obj_t)&pin_PB08 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PB09), (mp_obj_t)&pin_PB09 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA04), (mp_obj_t)&pin_PA04 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA05), (mp_obj_t)&pin_PA05 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PB02), (mp_obj_t)&pin_PB02 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA11), (mp_obj_t)&pin_PA11 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA10), (mp_obj_t)&pin_PA10 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA14), (mp_obj_t)&pin_PA14 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA09), (mp_obj_t)&pin_PA09 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA08), (mp_obj_t)&pin_PA08 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA15), (mp_obj_t)&pin_PA15 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA20), (mp_obj_t)&pin_PA20 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA21), (mp_obj_t)&pin_PA21 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA06), (mp_obj_t)&pin_PA06 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA07), (mp_obj_t)&pin_PA07 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA18), (mp_obj_t)&pin_PA18 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA16), (mp_obj_t)&pin_PA16 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA19), (mp_obj_t)&pin_PA19 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA17), (mp_obj_t)&pin_PA17 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA22), (mp_obj_t)&pin_PA22 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA23), (mp_obj_t)&pin_PA23 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PB11), (mp_obj_t)&pin_PB11 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PB10), (mp_obj_t)&pin_PB10 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA12), (mp_obj_t)&pin_PA12 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_PA13), (mp_obj_t)&pin_PA13 },
+};
+MP_DEFINE_CONST_DICT(pin_cpu_pins_locals_dict, pin_cpu_pins_locals_dict_table);
+
+STATIC const mp_map_elem_t pin_board_pins_locals_dict_table[] = {
+  { MP_OBJ_NEW_QSTR(MP_QSTR_A0), (mp_obj_t)&pin_PA02 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_A1), (mp_obj_t)&pin_PB08 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_A2), (mp_obj_t)&pin_PB09 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_A3), (mp_obj_t)&pin_PA04 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_A4), (mp_obj_t)&pin_PA05 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_A5), (mp_obj_t)&pin_PB02 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D0), (mp_obj_t)&pin_PA11 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_RX), (mp_obj_t)&pin_PA11 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D1), (mp_obj_t)&pin_PA10 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_TX), (mp_obj_t)&pin_PA10 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D2), (mp_obj_t)&pin_PA14 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D3), (mp_obj_t)&pin_PA09 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D4), (mp_obj_t)&pin_PA08 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D5), (mp_obj_t)&pin_PA15 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D6), (mp_obj_t)&pin_PA20 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D7), (mp_obj_t)&pin_PA21 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D8), (mp_obj_t)&pin_PA06 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D9), (mp_obj_t)&pin_PA07 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D10), (mp_obj_t)&pin_PA18 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D11), (mp_obj_t)&pin_PA16 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D12), (mp_obj_t)&pin_PA19 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_D13), (mp_obj_t)&pin_PA17 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), (mp_obj_t)&pin_PA22 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), (mp_obj_t)&pin_PA23 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_SCK),  (mp_obj_t)&pin_PB11 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_MOSI), (mp_obj_t)&pin_PB10 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_MISO), (mp_obj_t)&pin_PA12 },
+  { MP_OBJ_NEW_QSTR(MP_QSTR_FLASH_CS),   (mp_obj_t)&pin_PA13 },
+};
+MP_DEFINE_CONST_DICT(pin_board_pins_locals_dict, pin_board_pins_locals_dict_table);
diff --git a/atmel-samd/boards/metro_m0_flash/pins.h b/atmel-samd/boards/metro_m0_flash/pins.h
new file mode 100644
index 000000000..266026906
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/pins.h
@@ -0,0 +1,32 @@
+
+#ifndef __MICROPY_INCLUDED_ATMEL_SAMD_BOARDS_FEATHER_M0_BLE_PINS_H__
+#define __MICROPY_INCLUDED_ATMEL_SAMD_BOARDS_FEATHER_M0_BLE_PINS_H__
+
+#include "modmachine_pin.h"
+
+extern const pin_obj_t pin_PA02;
+extern const pin_obj_t pin_PB08;
+extern const pin_obj_t pin_PB09;
+extern const pin_obj_t pin_PA04;
+extern const pin_obj_t pin_PA05;
+extern const pin_obj_t pin_PB02;
+extern const pin_obj_t pin_PB11;
+extern const pin_obj_t pin_PB10;
+extern const pin_obj_t pin_PB21;
+extern const pin_obj_t pin_PA11;
+extern const pin_obj_t pin_PA10;
+extern const pin_obj_t pin_PA22;
+extern const pin_obj_t pin_PA23;
+extern const pin_obj_t pin_PA15;
+extern const pin_obj_t pin_PA20;
+extern const pin_obj_t pin_PA07;
+extern const pin_obj_t pin_PA18;
+extern const pin_obj_t pin_PA16;
+extern const pin_obj_t pin_PA19;
+extern const pin_obj_t pin_PA17;
+extern const pin_obj_t pin_PB11;
+extern const pin_obj_t pin_PB10;
+extern const pin_obj_t pin_PA12;
+extern const pin_obj_t pin_PA13;
+
+#endif  // __MICROPY_INCLUDED_ATMEL_SAMD_BOARDS_FEATHER_M0_BLE_PINS_H__
diff --git a/atmel-samd/boards/metro_m0_flash/user_board.h b/atmel-samd/boards/metro_m0_flash/user_board.h
new file mode 100644
index 000000000..39980a7d2
--- /dev/null
+++ b/atmel-samd/boards/metro_m0_flash/user_board.h
@@ -0,0 +1,40 @@
+/**
+ * \file
+ *
+ * \brief User board definition template
+ *
+ */
+
+ /* This file is intended to contain definitions and configuration details for
+ * features and devices that are available on the board, e.g., frequency and
+ * startup time for an external crystal, external memory devices, LED and USART
+ * pins.
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef USER_BOARD_H
+#define USER_BOARD_H
+
+#include <conf_board.h>
+
+// External oscillator settings.
+// Uncomment and set correct values if external oscillator is used.
+
+// External oscillator frequency
+//#define BOARD_XOSC_HZ          8000000
+
+// External oscillator type.
+//!< External clock signal
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_EXTERNAL
+//!< 32.768 kHz resonator on TOSC
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_32KHZ
+//!< 0.4 to 16 MHz resonator on XTALS
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_XTAL
+
+// External oscillator startup time
+//#define BOARD_XOSC_STARTUP_US  500000
+
+
+#endif // USER_BOARD_H
diff --git a/atmel-samd/boards/samd21x18-bootloader-external-flash.ld b/atmel-samd/boards/samd21x18-bootloader-external-flash.ld
new file mode 100644
index 000000000..0003c7239
--- /dev/null
+++ b/atmel-samd/boards/samd21x18-bootloader-external-flash.ld
@@ -0,0 +1,68 @@
+/*
+    GNU linker script for SAMD21
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x00000000 + 0x2000, LENGTH = 0x00040000 - 0x2000 /* Leave 8KiB for the bootloader. */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x008000 /* 32 KiB */
+}
+
+/* top end of the stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* define output sections */
+SECTIONS
+{
+    /* The program code and other data goes into FLASH */
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors)) /* isr vector table */
+        *(.text)           /* .text sections (code) */
+        *(.text*)          /* .text* sections (code) */
+        *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+
+        . = ALIGN(4);
+        _etext = .;        /* define a global symbol at end of code */
+        _sidata = _etext;  /* This is used by the startup in order to initialize the .data secion */
+    } >FLASH
+
+
+    /* This is the initialized data section
+    The program executes knowing that the data is in the RAM
+    but the loader puts the initial values in the FLASH (inidata).
+    It is one task of the startup to copy the initial values from FLASH to RAM. */
+    .data : AT ( _sidata )
+    {
+        . = ALIGN(4);
+        _srelocate = .;        /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
+        *(.ramfunc)
+        *(.ramfunc*)
+        *(.data)           /* .data sections */
+        *(.data*)          /* .data* sections */
+
+        . = ALIGN(4);
+        _erelocate = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
+    } >RAM
+
+    /* Uninitialized data section */
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        _szero = .;         /* define a global symbol at bss start; used by startup code */
+        *(.bss)
+        *(.bss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        _ezero = .;         /* define a global symbol at bss end; used by startup code */
+        _ebss = .;
+    } >RAM
+
+    .ARM.attributes 0 : { *(.ARM.attributes) }
+}