address review comments

5 files changed, 17 insertions, 26 deletions

diff --git a/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c b/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c
index 6258818c8..cbb067104 100644
--- a/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c
+++ b/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c
@@ -213,17 +213,17 @@ void frequencyin_samd51_start_dpll() {
     // Will also enable the Lock Bypass due to low-frequency sources causing DPLL unlocks
     // as outlined in the Errata (1.12.1)
     OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(2999);
-    if (BOARD_HAS_CRYSTAL) { // we can use XOSC32K directly as the source
-        OSC32KCTRL->XOSC32K.bit.EN32K = 1;
-        OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(1) |
-                                         OSCCTRL_DPLLCTRLB_LBYPASS;
-    } else {
-        // can't use OSCULP32K directly; need to setup a GCLK as a reference,
-        // which must be done in samd/clocks.c to avoid waiting for sync
-        return;
-        //OSC32KCTRL->OSCULP32K.bit.EN32K = 1;
-        //OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(0);
-    }
+#if BOARD_HAS_CRYSTAL
+    // we can use XOSC32K directly as the source
+    OSC32KCTRL->XOSC32K.bit.EN32K = 1;
+    OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(1) | OSCCTRL_DPLLCTRLB_LBYPASS;
+#else
+    // can't use OSCULP32K directly; need to setup a GCLK as a reference,
+    // which must be done in samd/clocks.c to avoid waiting for sync
+    return;
+    //OSC32KCTRL->OSCULP32K.bit.EN32K = 1;
+    //OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(0);
+#endif
     OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
 
     while (!(OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY)) {}
diff --git a/ports/nrf/README.md b/ports/nrf/README.md
index 64f5b8aff..88dd47273 100644
--- a/ports/nrf/README.md
+++ b/ports/nrf/README.md
@@ -5,21 +5,13 @@ This is a port of CircuitPython to the Nordic Semiconductor nRF52 series of chip
 > **NOTE**: There are board-specific READMEs that may be more up to date than the
   generic board-neutral documentation below.
 
-## Compile and Flash
-
-Prerequisite steps for building the nrf port:
-
-    git clone <URL>.git circuitpython
-    cd circuitpython
-    git submodule update --init --recursive
-    make -C mpy-cross
+## Flash
 
 Some boards have UF2 bootloaders and can simply be flashed in the normal way, by copying
 firmware.uf2 to the BOOT drive.
 
-To build and flash issue the following command inside the ports/nrf/ folder:
+For some boards, you can use the `flash` target:
 
-	make BOARD=pca10056
 	make BOARD=pca10056 flash
 
 ## Segger Targets
diff --git a/ports/nrf/common-hal/_bleio/Adapter.c b/ports/nrf/common-hal/_bleio/Adapter.c
index 1c9f1fcfa..cee40a5a0 100644
--- a/ports/nrf/common-hal/_bleio/Adapter.c
+++ b/ports/nrf/common-hal/_bleio/Adapter.c
@@ -59,8 +59,8 @@ const nvm_bytearray_obj_t common_hal_bleio_nvm_obj = {
     .base = {
         .type = &nvm_bytearray_type,
     },
-    .len = CIRCUITPY_BLE_CONFIG_SIZE,
     .start_address = (uint8_t*) CIRCUITPY_BLE_CONFIG_START_ADDR,
+    .len = CIRCUITPY_BLE_CONFIG_SIZE,
 };
 
 STATIC void softdevice_assert_handler(uint32_t id, uint32_t pc, uint32_t info) {
diff --git a/ports/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h
index c6d148234..71bf6bc8f 100644
--- a/ports/nrf/mpconfigport.h
+++ b/ports/nrf/mpconfigport.h
@@ -81,12 +81,10 @@
 // firmware
 // internal CIRCUITPY flash filesystem (optional)
 // BLE config (bonding info, etc.) (optional)
-// microntroller.nvm (optional)
+// microcontroller.nvm (optional)
 // bootloader (note the MBR at 0x0 redirects to the bootloader here, in high flash)
 // bootloader settings
 
-// Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld
-
 // Define these regions starting up from the bottom of flash:
 
 #define MBR_START_ADDR  (0x0)
@@ -101,6 +99,7 @@
 
 // Define these regions starting down from the bootloader:
 
+// Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld
 #define BOOTLOADER_START_ADDR          (0x000F4000)
 #define BOOTLOADER_SIZE                (0xA000)     // 40kiB
 #define BOOTLOADER_SETTINGS_START_ADDR (0x000FF000)
diff --git a/ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.h b/ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.h
index 1d47142a8..3ab9a5585 100644
--- a/ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.h
+++ b/ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.h
@@ -33,4 +33,4 @@
 #define FLASH_PAGE_SIZE             (0x4000)
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PB10)
-#define DEFAULT_I2C_BUS_SDA (&pin_PB09)
\ No newline at end of file
+#define DEFAULT_I2C_BUS_SDA (&pin_PB09)