diff options
| author | jgillick <j_gillick@yahoo.com> | 2020-03-17 00:36:18 -0700 |
|---|---|---|
| committer | jgillick <j_gillick@yahoo.com> | 2020-03-17 00:36:18 -0700 |
| commit | d41ef45a9b8e8b50ad3907ea16ba2c38658af73f (patch) | |
| tree | 27f3fc71de0c45e68ee1f9093fe1bb3f54573b55 | |
| parent | cbc0e0344da6785aa7d734f9dc267fa5973a3956 (diff) | |
Update clock.
| -rw-r--r-- | ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c index 3e2766516..607870058 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c +++ b/ports/stm/peripherals/stm32f4/stm32f412cx_thunderpack/clocks.c @@ -55,10 +55,11 @@ void stm32f4_peripherals_clocks_init(void) { HAL_RCC_OscConfig(&RCC_OscInitStruct); /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 72; PeriphClkInitStruct.PLLI2S.PLLI2SM = 12; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 3; - PeriphClkInitStruct.PLLI2S.PLLI2SN = 72; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); |