Merge pull request #2754 from maholli/non-standard-nvm

Add non-standard nvm to QSPI for external flash support

11 files changed, 288 insertions, 32 deletions

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 3dda76db4..826ca279c 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -222,6 +222,7 @@ jobs:
         - "pybadge_airlift"
         - "pyboard_v11"
         - "pycubed"
+        - "pycubed_mram"
         - "pygamer"
         - "pygamer_advance"
         - "pyportal"
diff --git a/ports/atmel-samd/boards/pycubed/mpconfigboard.h b/ports/atmel-samd/boards/pycubed/mpconfigboard.h
index 49a98e8d4..8d046c75b 100644
--- a/ports/atmel-samd/boards/pycubed/mpconfigboard.h
+++ b/ports/atmel-samd/boards/pycubed/mpconfigboard.h
@@ -3,6 +3,7 @@
 #define MICROPY_HW_MCU_NAME "samd51j19"
 #define CIRCUITPY_MCU_FAMILY samd51
 
+#define MICROPY_HW_LED_STATUS (&pin_PA16)
 #define MICROPY_HW_NEOPIXEL   (&pin_PA21)
 
 #define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11)
@@ -16,6 +17,7 @@
 
 #define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000 - CIRCUITPY_INTERNAL_NVM_SIZE)
 
+// External flash W25Q80DV 
 #define EXTERNAL_FLASH_QSPI_DUAL
 
 #define BOARD_HAS_CRYSTAL 1
diff --git a/ports/atmel-samd/boards/pycubed/mpconfigboard.mk b/ports/atmel-samd/boards/pycubed/mpconfigboard.mk
index adaeecb89..b7b8073ab 100644
--- a/ports/atmel-samd/boards/pycubed/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/pycubed/mpconfigboard.mk
@@ -1,4 +1,3 @@
-LD_FILE = boards/samd51x19-bootloader-external-flash.ld
 USB_VID = 0x04D8
 USB_PID = 0xEC44
 USB_PRODUCT = "PyCubed"
@@ -12,6 +11,8 @@ EXTERNAL_FLASH_DEVICE_COUNT = 1
 EXTERNAL_FLASH_DEVICES = W25Q80DV
 LONGINT_IMPL = MPZ
 
+CIRCUITPY_DRIVE_LABEL = "PYCUBED"
+
 # Not needed.
 CIRCUITPY_AUDIOBUSIO = 0
 CIRCUITPY_DISPLAYIO = 0
diff --git a/ports/atmel-samd/boards/pycubed_mram/board.c b/ports/atmel-samd/boards/pycubed_mram/board.c
new file mode 100644
index 000000000..31b081209
--- /dev/null
+++ b/ports/atmel-samd/boards/pycubed_mram/board.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+#include <string.h>
+
+#include "boards/board.h"
+#include "py/mpconfig.h"
+#include "shared-bindings/nvm/ByteArray.h"
+#include "common-hal/microcontroller/Pin.h"
+#include "hal/include/hal_gpio.h"
+#include "shared-bindings/pulseio/PWMOut.h"
+
+nvm_bytearray_obj_t bootcnt = {
+    .base = {
+        .type = &nvm_bytearray_type
+            },
+    .len = ( uint32_t) 8192,
+    .start_address = (uint8_t*) (0x00080000 - 8192)
+    };
+
+
+void board_init(void) {
+    pulseio_pwmout_obj_t pwm;
+    common_hal_pulseio_pwmout_construct(&pwm, &pin_PA23, 4096, 2, false);
+    common_hal_pulseio_pwmout_never_reset(&pwm);
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+    uint8_t value_out = 0;
+    common_hal_nvm_bytearray_get_bytes(&bootcnt,0,1,&value_out);
+    ++value_out;
+    common_hal_nvm_bytearray_set_bytes(&bootcnt,0,&value_out,1);
+}
\ No newline at end of file
diff --git a/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.h b/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.h
new file mode 100644
index 000000000..e2a733025
--- /dev/null
+++ b/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.h
@@ -0,0 +1,39 @@
+#define MICROPY_HW_BOARD_NAME "PyCubedv04-MRAM"
+#define MICROPY_HW_MCU_NAME "samd51j19"
+#define CIRCUITPY_MCU_FAMILY samd51
+
+#define MICROPY_HW_LED_STATUS (&pin_PA16)
+#define MICROPY_HW_NEOPIXEL   (&pin_PA21)
+
+#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11)
+#define MICROPY_PORT_B (PORT_PA21 | PORT_PB10 | PORT_PB11)
+#define MICROPY_PORT_C        (0)
+#define MICROPY_PORT_D 		  (0)
+
+#define SPI_FLASH_WP_PIN            &pin_PA10
+#define SPI_FLASH_HOLD_PIN          &pin_PA11
+
+// External flash MR2xH40 MRAM
+#define EXTERNAL_FLASH_QSPI_SINGLE
+#define EXTERNAL_FLASH_NO_JEDEC
+
+#define AUTORESET_DELAY_MS 500
+
+#define CIRCUITPY_INTERNAL_NVM_SIZE 8192
+
+#define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000 - CIRCUITPY_INTERNAL_NVM_SIZE)
+
+#define BOARD_HAS_CRYSTAL 1
+
+#define DEFAULT_I2C_BUS_SCL  (&pin_PB13)
+#define DEFAULT_I2C_BUS_SDA  (&pin_PB12)
+
+#define DEFAULT_SPI_BUS_SCK  (&pin_PA13)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PA12)
+#define DEFAULT_SPI_BUS_MISO (&pin_PA14)
+
+#define DEFAULT_UART_BUS_TX  (&pin_PB02)
+#define DEFAULT_UART_BUS_RX  (&pin_PB03)
+
+#define IGNORE_PIN_PA24     1
+#define IGNORE_PIN_PA25     1
diff --git a/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.mk b/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.mk
new file mode 100644
index 000000000..f49bb3fef
--- /dev/null
+++ b/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.mk
@@ -0,0 +1,27 @@
+USB_VID = 0x04D8
+USB_PID = 0xEC44
+USB_PRODUCT = "PyCubed"
+USB_MANUFACTURER = "maholli"
+
+CHIP_VARIANT = SAMD51J19A
+CHIP_FAMILY = samd51
+
+QSPI_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICE_COUNT = 1
+EXTERNAL_FLASH_DEVICES = MR2xH40
+LONGINT_IMPL = MPZ
+
+CIRCUITPY_DRIVE_LABEL = "PYCUBED"
+
+# Not needed.
+CIRCUITPY_AUDIOBUSIO = 0
+CIRCUITPY_DISPLAYIO = 0
+CIRCUITPY_FRAMEBUFFERIO = 0
+CIRCUITPY_GAMEPAD = 0
+CIRCUITPY_RGBMATRIX = 0
+CIRCUITPY_PS2IO = 0
+
+FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_BusDevice
+FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel
+FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Register
+FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_SD
diff --git a/ports/atmel-samd/boards/pycubed_mram/pins.c b/ports/atmel-samd/boards/pycubed_mram/pins.c
new file mode 100644
index 000000000..e494fb54b
--- /dev/null
+++ b/ports/atmel-samd/boards/pycubed_mram/pins.c
@@ -0,0 +1,55 @@
+#include "shared-bindings/board/__init__.h"
+#include "boards/board.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_SCK),      MP_ROM_PTR(&pin_PA13)  },
+    { MP_ROM_QSTR(MP_QSTR_MOSI),     MP_ROM_PTR(&pin_PA12)  },
+    { MP_ROM_QSTR(MP_QSTR_MISO),     MP_ROM_PTR(&pin_PA14)  },
+    { MP_ROM_QSTR(MP_QSTR_xSDCS),    MP_ROM_PTR(&pin_PA27)  },
+
+    { MP_ROM_QSTR(MP_QSTR_RELAY_A),  MP_ROM_PTR(&pin_PB15)  },
+    { MP_ROM_QSTR(MP_QSTR_BURN1),    MP_ROM_PTR(&pin_PB31)  },
+    { MP_ROM_QSTR(MP_QSTR_BURN2),    MP_ROM_PTR(&pin_PA15)  },
+
+    { MP_ROM_QSTR(MP_QSTR_BATTERY),  MP_ROM_PTR(&pin_PA06)  },
+    { MP_ROM_QSTR(MP_QSTR_L1PROG),   MP_ROM_PTR(&pin_PA07)  },
+    { MP_ROM_QSTR(MP_QSTR_AIN4),     MP_ROM_PTR(&pin_PA04)  },
+    { MP_ROM_QSTR(MP_QSTR_AIN5),     MP_ROM_PTR(&pin_PA05)  },
+    { MP_ROM_QSTR(MP_QSTR_CHRG),     MP_ROM_PTR(&pin_PB08)  },
+    { MP_ROM_QSTR(MP_QSTR_DAC0),     MP_ROM_PTR(&pin_PA02)  },
+    { MP_ROM_QSTR(MP_QSTR_PA17),     MP_ROM_PTR(&pin_PA17)  },
+    { MP_ROM_QSTR(MP_QSTR_PA18),     MP_ROM_PTR(&pin_PA18)  },
+    { MP_ROM_QSTR(MP_QSTR_PA19),     MP_ROM_PTR(&pin_PA19)  },
+    { MP_ROM_QSTR(MP_QSTR_PA20),     MP_ROM_PTR(&pin_PA20)  },
+    { MP_ROM_QSTR(MP_QSTR_PA22),     MP_ROM_PTR(&pin_PA22)  },
+    { MP_ROM_QSTR(MP_QSTR_PB16),     MP_ROM_PTR(&pin_PB16)  },
+    { MP_ROM_QSTR(MP_QSTR_PB17),     MP_ROM_PTR(&pin_PB17)  },
+    { MP_ROM_QSTR(MP_QSTR_PB22),     MP_ROM_PTR(&pin_PB22)  },
+    { MP_ROM_QSTR(MP_QSTR_PB23),     MP_ROM_PTR(&pin_PB23)  },
+
+    { MP_ROM_QSTR(MP_QSTR_RF1_RST),  MP_ROM_PTR(&pin_PB00)  },
+    { MP_ROM_QSTR(MP_QSTR_RF1_CS),   MP_ROM_PTR(&pin_PB30)  },
+    { MP_ROM_QSTR(MP_QSTR_RF1_IO0),  MP_ROM_PTR(&pin_PB05)  },
+    { MP_ROM_QSTR(MP_QSTR_RF1_IO4),  MP_ROM_PTR(&pin_PB04)  },
+
+    { MP_ROM_QSTR(MP_QSTR_RF2_RST),   MP_ROM_PTR(&pin_PB14)  },
+    { MP_ROM_QSTR(MP_QSTR_RF2_CS),    MP_ROM_PTR(&pin_PB09)  },
+    { MP_ROM_QSTR(MP_QSTR_RF2_IO1),   MP_ROM_PTR(&pin_PB06)  },
+    { MP_ROM_QSTR(MP_QSTR_RF2_BSY),   MP_ROM_PTR(&pin_PB07)  },
+
+    { MP_ROM_QSTR(MP_QSTR_EN_GPS),   MP_ROM_PTR(&pin_PB01)  },
+    { MP_ROM_QSTR(MP_QSTR_TX),       MP_ROM_PTR(&pin_PB02)  },
+    { MP_ROM_QSTR(MP_QSTR_RX),       MP_ROM_PTR(&pin_PB03)  },
+
+    { MP_ROM_QSTR(MP_QSTR_SDA),      MP_ROM_PTR(&pin_PB12)  },
+    { MP_ROM_QSTR(MP_QSTR_SCL),      MP_ROM_PTR(&pin_PB13)  },
+
+    { MP_ROM_QSTR(MP_QSTR_WDT_WDI),  MP_ROM_PTR(&pin_PA23)  },
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA21)  },
+
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+    { MP_ROM_QSTR(MP_QSTR_I2C),  MP_ROM_PTR(&board_i2c_obj)  },
+    { MP_ROM_QSTR(MP_QSTR_SPI),  MP_ROM_PTR(&board_spi_obj)  },
+
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/atmel-samd/supervisor/qspi_flash.c b/ports/atmel-samd/supervisor/qspi_flash.c
index eca47b164..aaed2a0ee 100644
--- a/ports/atmel-samd/supervisor/qspi_flash.c
+++ b/ports/atmel-samd/supervisor/qspi_flash.c
@@ -166,7 +166,10 @@ bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) {
 bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
     samd_peripherals_disable_and_clear_cache();
 
-    #ifdef EXTERNAL_FLASH_QSPI_DUAL
+    #ifdef EXTERNAL_FLASH_QSPI_SINGLE
+    QSPI->INSTRCTRL.bit.INSTR = CMD_READ_DATA;
+    uint32_t mode = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI;
+    #elif defined(EXTERNAL_FLASH_QSPI_DUAL)
     QSPI->INSTRCTRL.bit.INSTR = CMD_DUAL_READ;
     uint32_t mode = QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT;
     #else
@@ -174,6 +177,15 @@ bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
     uint32_t mode = QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT;
     #endif
 
+    #ifdef EXTERNAL_FLASH_QSPI_SINGLE
+    QSPI->INSTRFRAME.reg = mode |
+                           QSPI_INSTRFRAME_ADDRLEN_24BITS |
+                           QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
+                           QSPI_INSTRFRAME_INSTREN |
+                           QSPI_INSTRFRAME_ADDREN |
+                           QSPI_INSTRFRAME_DATAEN |
+                           QSPI_INSTRFRAME_DUMMYLEN(0);
+    #else
     QSPI->INSTRFRAME.reg = mode |
                            QSPI_INSTRFRAME_ADDRLEN_24BITS |
                            QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
@@ -181,6 +193,7 @@ bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
                            QSPI_INSTRFRAME_ADDREN |
                            QSPI_INSTRFRAME_DATAEN |
                            QSPI_INSTRFRAME_DUMMYLEN(8);
+    #endif
 
     memcpy(data, ((uint8_t *) QSPI_AHB) + address, length);
     // TODO(tannewt): Fix DMA and enable it.
diff --git a/supervisor/shared/external_flash/common_commands.h b/supervisor/shared/external_flash/common_commands.h
index cc0da2175..2eaa84833 100644
--- a/supervisor/shared/external_flash/common_commands.h
+++ b/supervisor/shared/external_flash/common_commands.h
@@ -43,5 +43,6 @@
 #define CMD_QUAD_READ 0x6b
 #define CMD_ENABLE_RESET 0x66
 #define CMD_RESET 0x99
+#define CMD_WAKE 0xab
 
 #endif  // MICROPY_INCLUDED_ATMEL_SAMD_EXTERNAL_FLASH_COMMON_COMMANDS_H
diff --git a/supervisor/shared/external_flash/devices.h b/supervisor/shared/external_flash/devices.h
index 57c52e2ea..f99fad4e7 100644
--- a/supervisor/shared/external_flash/devices.h
+++ b/supervisor/shared/external_flash/devices.h
@@ -64,6 +64,15 @@ typedef struct {
     // True when the status register is a single byte. This implies the Quad Enable bit is in the
     // first byte and the Read Status Register 2 command (0x35) is unsupported.
     bool single_status_byte: 1;
+
+    // Does not support using a ready bit within the status register
+    bool no_ready_bit: 1;
+
+    // Does not support the erase command (0x20)
+    bool no_erase_cmd: 1;
+
+    // Device does not have a reset command
+    bool no_reset_cmd: 1;
 } external_flash_device;
 
 // Settings for the Adesto Tech AT25DF081A 1MiB SPI flash. It's on the SAMD21
@@ -426,6 +435,27 @@ typedef struct {
     .single_status_byte = false, \
 }
 
+// Settings for the Everspin MR20H40 / MR25H40 magnetic non-volatile RAM
+// Datasheet: https://www.everspin.com/supportdocs/MR25H40CDFR
+#define MR2xH40 {\
+    .total_size = (1 << 22), /* 4 MiB */ \
+    .start_up_time_us = 10000, \
+    .manufacturer_id = 0xef, /*no JDEC*/ \
+    .memory_type = 0x40, /*no JDEC*/ \
+    .capacity = 0x14, /*no JDEC*/ \
+    .max_clock_speed_mhz = 10, \
+    .quad_enable_bit_mask = 0x00, \
+    .has_sector_protection = false, \
+    .supports_fast_read = false, \
+    .supports_qspi = false, \
+    .supports_qspi_writes = false, \
+    .write_status_register_split = false, \
+    .single_status_byte = true, \
+    .no_ready_bit = true, \
+    .no_erase_cmd = true, \
+    .no_reset_cmd = true, \
+}
+
 // Settings for the Macronix MX25L1606 2MiB SPI flash.
 // Datasheet:
 #define MX25L1606  {\
diff --git a/supervisor/shared/external_flash/external_flash.c b/supervisor/shared/external_flash/external_flash.c
index bfc434664..5bde7fd48 100644
--- a/supervisor/shared/external_flash/external_flash.c
+++ b/supervisor/shared/external_flash/external_flash.c
@@ -27,7 +27,6 @@
 
 #include <stdint.h>
 #include <string.h>
-
 #include "supervisor/flash.h"
 #include "supervisor/spi_flash_api.h"
 #include "supervisor/shared/external_flash/common_commands.h"
@@ -58,9 +57,13 @@ static supervisor_allocation* supervisor_cache = NULL;
 
 // Wait until both the write enable and write in progress bits have cleared.
 static bool wait_for_flash_ready(void) {
-    uint8_t read_status_response[1] = {0x00};
     bool ok = true;
     // Both the write enable and write in progress bits should be low.
+    if (flash_device->no_ready_bit){
+        // For NVM without a ready bit in status register
+        return ok;
+    }
+    uint8_t read_status_response[1] = {0x00};
     do {
         ok = spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1);
     } while (ok && (read_status_response[0] & 0x3) != 0);
@@ -92,15 +95,18 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len
     }
     // Don't bother writing if the data is all 1s. Thats equivalent to the flash
     // state after an erase.
-    bool all_ones = true;
-    for (uint16_t i = 0; i < data_length; i++) {
-        if (data[i] != 0xff) {
-            all_ones = false;
-            break;
+    if (!flash_device->no_erase_cmd){
+        // Only do this if the device has an erase command
+        bool all_ones = true;
+        for (uint16_t i = 0; i < data_length; i++) {
+            if (data[i] != 0xff) {
+                all_ones = false;
+                break;
+            }
+        }
+        if (all_ones) {
+            return true;
         }
-    }
-    if (all_ones) {
-        return true;
     }
 
     for (uint32_t bytes_written = 0;
@@ -121,6 +127,10 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len
 static bool page_erased(uint32_t sector_address) {
     // Check the first few bytes to catch the common case where there is data
     // without using a bunch of memory.
+    if (flash_device->no_erase_cmd){
+        // skip this if device doesn't have an erase command.
+        return true;
+    }
     uint8_t short_buffer[4];
     if (read_flash(sector_address, short_buffer, 4)) {
         for (uint16_t i = 0; i < 4; i++) {
@@ -151,10 +161,16 @@ static bool page_erased(uint32_t sector_address) {
 static bool erase_sector(uint32_t sector_address) {
     // Before we erase the sector we need to wait for any writes to finish and
     // and then enable the write again.
+    if (flash_device->no_erase_cmd){
+        // skip this if device doesn't have an erase command.
+        return true;
+    }
     if (!wait_for_flash_ready() || !write_enable()) {
         return false;
     }
-
+    if (flash_device->no_erase_cmd) {
+        return true;
+    }
     spi_flash_sector_command(CMD_SECTOR_ERASE, sector_address);
     return true;
 }
@@ -192,25 +208,33 @@ void supervisor_flash_init(void) {
 
     spi_flash_init();
 
+#ifdef EXTERNAL_FLASH_NO_JEDEC
+    // For NVM that don't have JEDEC response
+    spi_flash_command(CMD_WAKE);
+    for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
+        const external_flash_device* possible_device = &possible_devices[i];
+        flash_device = possible_device;
+        break;
+    }
+#else
     // The response will be 0xff if the flash needs more time to start up.
     uint8_t jedec_id_response[3] = {0xff, 0xff, 0xff};
     while (jedec_id_response[0] == 0xff) {
         spi_flash_read_command(CMD_READ_JEDEC_ID, jedec_id_response, 3);
     }
-
-    for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
-        const external_flash_device* possible_device = &possible_devices[i];
-        if (jedec_id_response[0] == possible_device->manufacturer_id &&
-            jedec_id_response[1] == possible_device->memory_type &&
-            jedec_id_response[2] == possible_device->capacity) {
-            flash_device = possible_device;
-            break;
+        for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
+            const external_flash_device* possible_device = &possible_devices[i];
+            if (jedec_id_response[0] == possible_device->manufacturer_id &&
+                jedec_id_response[1] == possible_device->memory_type &&
+                jedec_id_response[2] == possible_device->capacity) {
+                flash_device = possible_device;
+                break;
+            }
+        }
+#endif
+        if (flash_device == NULL) {
+            return;
         }
-    }
-
-    if (flash_device == NULL) {
-        return;
-    }
 
     // We don't know what state the flash is in so wait for any remaining writes and then reset.
     uint8_t read_status_response[1] = {0x00};
@@ -219,14 +243,16 @@ void supervisor_flash_init(void) {
         spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1);
     } while ((read_status_response[0] & 0x1) != 0);
     if (!flash_device->single_status_byte) {
-      // The suspended write/erase bit should be low.
-      do {
-        spi_flash_read_command(CMD_READ_STATUS2, read_status_response, 1);
-      } while ((read_status_response[0] & 0x80) != 0);
+        // The suspended write/erase bit should be low.
+        do {
+            spi_flash_read_command(CMD_READ_STATUS2, read_status_response, 1);
+        } while ((read_status_response[0] & 0x80) != 0);
     }
 
-    spi_flash_command(CMD_ENABLE_RESET);
-    spi_flash_command(CMD_RESET);
+    if (!(flash_device->no_reset_cmd)){
+        spi_flash_command(CMD_ENABLE_RESET);
+        spi_flash_command(CMD_RESET);
+    }
 
     // Wait 30us for the reset
     common_hal_mcu_delay_us(30);