diff options
| author | Scott Shawcroft <scott@tannewt.org> | 2017-09-22 18:05:51 -0700 |
|---|---|---|
| committer | Dan Halbert <halbert@halwitz.org> | 2017-09-22 21:05:51 -0400 |
| commit | 6839fff31303463d5c7942387fa498895edf1abf (patch) | |
| tree | f4c5b94c6534c8d5c65ea6b7209cd2d681508f5f /atmel-samd/asf4/samd21/config | |
| parent | 3ad01ddb04b160b74b4baee9fce043da17dbcef5 (diff) | |
Move to ASF4 and introduce SAMD51 support. (#258)3.0.0-alpha.0
* atmel-samd: Remove ASF3. This will break builds.
* atmel-samd: Add ASF4 for the SAMD21 and SAMD51.
* Introduce the supervisor concept to facilitate porting.
The supervisor is the code which runs individual MicroPython VMs. By
splitting it out we make it more consistent and easier to find.
This also adds very basic SAMD21 and SAMD51 support using the
supervisor. Only the REPL currently works.
This begins the work for #178.
Diffstat (limited to 'atmel-samd/asf4/samd21/config')
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_adc_config.h | 296 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_dac_config.h | 86 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_dmac_config.h | 3057 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_gclk_config.h | 618 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h | 38 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_pm_config.h | 134 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_rtc_config.h | 117 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_sercom_config.h | 534 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h | 678 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_systick_config.h | 18 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_tc_config.h | 181 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/hpl_usb_config.h | 355 | ||||
| -rw-r--r-- | atmel-samd/asf4/samd21/config/peripheral_clk_config.h | 369 |
13 files changed, 6481 insertions, 0 deletions
diff --git a/atmel-samd/asf4/samd21/config/hpl_adc_config.h b/atmel-samd/asf4/samd21/config/hpl_adc_config.h new file mode 100644 index 000000000..ea69d4a69 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_adc_config.h @@ -0,0 +1,296 @@ +/* Auto-generated config file hpl_adc_config.h */ +#ifndef HPL_ADC_CONFIG_H +#define HPL_ADC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_ADC_0_ENABLE +#define CONF_ADC_0_ENABLE 1 +#endif + +// <h> Basic Configuration + +// <o> Conversion resolution +// <0x0=>12-bit +// <0x1=>16-bit (averaging must be enabled) +// <0x2=>10-bit +// <0x3=>8-bit +// <i> Defines the bit resolution for the ADC sample values (RESSEL) +// <id> adc_resolution +#ifndef CONF_ADC_0_RESSEL +#define CONF_ADC_0_RESSEL 0x0 +#endif + +// <o> Reference Selection +// <0x0=>1.0V voltage reference +// <0x1=>1/1.48 VDDANA +// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V) +// <0x3=>External reference A +// <0x4=>External reference B +// <i> Select the reference for the ADC (REFSEL) +// <id> adc_reference +#ifndef CONF_ADC_0_REFSEL +#define CONF_ADC_0_REFSEL 0x0 +#endif + +// <o> Prescaler configuration +// <0x0=>Peripheral clock divided by 4 +// <0x1=>Peripheral clock divided by 8 +// <0x2=>Peripheral clock divided by 16 +// <0x3=>Peripheral clock divided by 32 +// <0x4=>Peripheral clock divided by 64 +// <0x5=>Peripheral clock divided by 128 +// <0x6=>Peripheral clock divided by 256 +// <0x7=>Peripheral clock divided by 512 +// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER) +// <id> adc_prescaler +#ifndef CONF_ADC_0_PRESCALER +#define CONF_ADC_0_PRESCALER 0x0 +#endif + +// <q> Free Running Mode +// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN) +// <id> adc_freerunning_mode +#ifndef CONF_ADC_0_FREERUN +#define CONF_ADC_0_FREERUN 0 +#endif + +// <q> Differential Mode +// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE) +// <id> adc_differential_mode +#ifndef CONF_ADC_0_DIFFMODE +#define CONF_ADC_0_DIFFMODE 0 +#endif + +// <o> Positive Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x08=>ADC AIN8 pin +// <0x09=>ADC AIN9 pin +// <0x0A=>ADC AIN10 pin +// <0x0B=>ADC AIN11 pin +// <0x0C=>ADC AIN12 pin +// <0x0D=>ADC AIN13 pin +// <0x0E=>ADC AIN14 pin +// <0x0F=>ADC AIN15 pin +// <0x10=>ADC AIN16 pin +// <0x11=>ADC AIN17 pin +// <0x12=>ADC AIN18 pin +// <0x13=>ADC AIN19 pin +// <0x18=>Temperature reference +// <0x19=>Bandgap voltage +// <0x1A=>1/4 scaled core supply +// <0x1B=>1/4 scaled I/O supply +// <0x1C=>DAC output +// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS) +// <id> adc_pinmux_positive +#ifndef CONF_ADC_0_MUXPOS +#define CONF_ADC_0_MUXPOS 0x0 +#endif + +// <o> Negative Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x18=>Internal ground +// <0x19=>I/O ground +// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG) +// <id> adc_pinmux_negative +#ifndef CONF_ADC_0_MUXNEG +#define CONF_ADC_0_MUXNEG 0x0 +#endif + +// </h> + +// <e> Advanced Configuration +// <id> adc_advanced_settings +#ifndef CONF_ADC_0_ADVANCED_CONFIG +#define CONF_ADC_0_ADVANCED_CONFIG 0 +#endif + +// <q> Run in standby +// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY) +// <id> adc_arch_runstdby +#ifndef CONF_ADC_0_RUNSTDBY +#define CONF_ADC_0_RUNSTDBY 0 +#endif + +// <q>Debug Run +// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN) +// <id> adc_arch_dbgrun +#ifndef CONF_ADC_0_DBGRUN +#define CONF_ADC_0_DBGRUN 0 +#endif + +// <q> Left-Adjusted Result +// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ) +// <id> adc_arch_leftadj +#ifndef CONF_ADC_0_LEFTADJ +#define CONF_ADC_0_LEFTADJ 0 +#endif + +// <q> Reference Buffer Offset Compensation Enable +// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP) +// <id> adc_arch_refcomp +#ifndef CONF_ADC_0_REFCOMP +#define CONF_ADC_0_REFCOMP 0 +#endif + +// <q> Digital Correction Logic Enabled +// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN) +// <id> adc_arch_corren +#ifndef CONF_ADC_0_CORREN +#define CONF_ADC_0_CORREN 0 +#endif + +// <o> Offset Correction Value <0-4095> +// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR) +// <id> adc_arch_offsetcorr +#ifndef CONF_ADC_0_OFFSETCORR +#define CONF_ADC_0_OFFSETCORR 0 +#endif + +// <o> Gain Correction Value <0-4095> +// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR) +// <id> adc_arch_gaincorr +#ifndef CONF_ADC_0_GAINCORR +#define CONF_ADC_0_GAINCORR 0 +#endif + +// <o> Gain Factor Selection +// <0x0=>1x +// <0x1=>2x +// <0x2=>4x +// <0x3=>8x +// <0x4=>16x +// <0xF=>1/2x +// <i> These bits set the gain factor of the ADC gain stage. (GAIN) +// <id> adc_arch_gain +#ifndef CONF_ADC_0_GAIN +#define CONF_ADC_0_GAIN 0x0 +#endif + +// <o> Adjusting Result / Division Coefficient <0-7> +// <i> These bits define the division coefficient in 2n steps. (ADJRES) +// <id> adc_arch_adjres +#ifndef CONF_ADC_0_ADJRES +#define CONF_ADC_0_ADJRES 0x0 +#endif + +// <o.0..10> Number of Samples to be Collected +// <0x0=>1 sample +// <0x1=>2 samples +// <0x2=>4 samples +// <0x3=>8 samples +// <0x4=>16 samples +// <0x5=>32 samples +// <0x6=>64 samples +// <0x7=>128 samples +// <0x8=>256 samples +// <0x9=>512 samples +// <0xA=>1024 samples +// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM) +// <id> adc_arch_samplenum +#ifndef CONF_ADC_0_SAMPLENUM +#define CONF_ADC_0_SAMPLENUM 0x0 +#endif + +// <o> Sampling Time Length <0-63> +// <i> These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) +// <id> adc_arch_samplen +#ifndef CONF_ADC_0_SAMPLEN +#define CONF_ADC_0_SAMPLEN 0 +#endif + +// <o> Window Monitor Mode +// <0x0=>No window mode +// <0x1=>Mode 1: RESULT above lower threshold +// <0x2=>Mode 2: RESULT beneath upper threshold +// <0x3=>Mode 3: RESULT inside lower and upper threshold +// <0x4=>Mode 4: RESULT outside lower and upper threshold +// <i> These bits enable and define the window monitor mode. (WINMODE) +// <id> adc_arch_winmode +#ifndef CONF_ADC_0_WINMODE +#define CONF_ADC_0_WINMODE 0x0 +#endif + +// <o> Window Monitor Lower Threshold <0-65535> +// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT) +// <id> adc_arch_winlt +#ifndef CONF_ADC_0_WINLT +#define CONF_ADC_0_WINLT 0 +#endif + +// <o> Window Monitor Upper Threshold <0-65535> +// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT) +// <id> adc_arch_winut +#ifndef CONF_ADC_0_WINUT +#define CONF_ADC_0_WINUT 0 +#endif + +// <o> Number of Input Channels Included in Scan <0-15> +// <i>This register gives the number of input sources included in pin scan. The number of input sources included is INPUTSCAN + 1. 0 disables the input scan feature. (INPUTSCAN) +// <id> adc_arch_inputscan +#ifndef CONF_ADC_0_INPUTSCAN +#define CONF_ADC_0_INPUTSCAN 0 +#endif + +// <o> Positive Mux Setting Offset <0-15> +// <i>When inputscan is enabled this value define the pin offset, which means that the actual input pin sampled is the muxpos pin + input offset. (INPUTOFFSET) +// <id> adc_arch_inputoffset +#ifndef CONF_ADC_0_INPUTOFFSET +#define CONF_ADC_0_INPUTOFFSET 0 +#endif + +// </e> + +// <e> Event Control +// <id> adc_arch_event_settings +#ifndef CONF_ADC_0_EVENT_CONFIG +#define CONF_ADC_0_EVENT_CONFIG 0 +#endif + +// <q> Window Monitor Event Out +// <i> Enables event output on window event (WINMONEO) +// <id> adc_arch_winmoneo +#ifndef CONF_ADC_0_WINMONEO +#define CONF_ADC_0_WINMONEO 0 +#endif + +// <q> Result Ready Event Out +// <i> Enables event output on result ready event (RESRDEO) +// <id> adc_arch_resrdyeo +#ifndef CONF_ADC_0_RESRDYEO +#define CONF_ADC_0_RESRDYEO 0 +#endif + +// <q> Trigger Synchronization On Event +// <i> Trigger a flush operation and a new conversion on event in (SYNCEI) +// <id> adc_arch_syncei +#ifndef CONF_ADC_0_SYNCEI +#define CONF_ADC_0_SYNCEI 0 +#endif + +// <q> Trigger Conversion On Event +// <i> Trigger a conversion on event. (STARTEI) +// <id> adc_arch_startei +#ifndef CONF_ADC_0_STARTEI +#define CONF_ADC_0_STARTEI 0 +#endif + +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_ADC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_dac_config.h b/atmel-samd/asf4/samd21/config/hpl_dac_config.h new file mode 100644 index 000000000..4b1b152fb --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_dac_config.h @@ -0,0 +1,86 @@ +/* Auto-generated config file hpl_dac_config.h */ +#ifndef HPL_DAC_CONFIG_H +#define HPL_DAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Basic configuration +// <o> Reference Selection +// <0x00=> Internal 1.0v reference +// <0x01=> AVCC +// <0x02=> External reference +// <id> dac_arch_refsel +#ifndef CONF_DAC_REFSEL +#define CONF_DAC_REFSEL 0 +#endif +// </h> + +// <e> Advanced Configuration +// <id> dac_advanced_settings +#ifndef CONF_DAC_ADVANCED_CONFIG +#define CONF_DAC_ADVANCED_CONFIG 0 +#endif + +// <q> Run in standby +// <i> Indicates whether the DAC will continue running in standby sleep mode or not +// <id> dac_arch_runstdby +#ifndef CONF_DAC_RUNSTDBY +#define CONF_DAC_RUNSTDBY 0 +#endif + +// <q> Bypass DATABUF Write Protection +// <i> Indicate whether DATABUF write protection is bypass +// <id> dac_arch_bdwp +#ifndef CONF_DAC_BDWP +#define CONF_DAC_BDWP 0 +#endif + +// <q> Voltage Pump Disable +// <i> Indicate whether voltage pump is disable or not +// <id> dac_arch_vpd +#ifndef CONF_DAC_VPD +#define CONF_DAC_VPD 0 +#endif + +// <q> Left Adjusted Data +// <i> Indicate how the data is adjusted in the Data and Data Buffer register +// <id> dac_arch_leftadj +#ifndef CONF_DAC_LEFTADJ +#define CONF_DAC_LEFTADJ 0 +#endif + +// <q> Internal Output Enable +// <i> Indicate whether internal output is enable or not +// <id> dac_arch_ioen +#ifndef CONF_DAC_IOEN +#define CONF_DAC_IOEN 0 +#endif + +// <q> External Output Enable +// <i> Indicate whether external output is enable or not +// <id> dac_arch_eoen +#ifndef CONF_DAC_EOEN +#define CONF_DAC_EOEN 1 +#endif + +// </e> + +// <h> Event configuration +// <q> Data Buffer Empty Event Output +// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// <id> dac_arch_emptyeo +#ifndef CONF_DAC_EMPTYEO +#define CONF_DAC_EMPTYEO 0 +#endif + +// <q> Start Conversion on Event Input +// <i> Indicate whether Start Conversion is enabled and data are loaded from the Data Buffer register to the Data register upon event reception or not +// <id> dac_arch_startei +#ifndef CONF_DAC_STARTEI +#define CONF_DAC_STARTEI 0 +#endif +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_DAC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_dmac_config.h b/atmel-samd/asf4/samd21/config/hpl_dmac_config.h new file mode 100644 index 000000000..3667e873b --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_dmac_config.h @@ -0,0 +1,3057 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <e> DMAC enable +// <i> Indicates whether dmac is enabled or not +// <id> dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// <q> Priority Level 0 +// <i> Indicates whether Priority Level 0 is enabled or not +// <id> dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 0 +#endif + +// <o> Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// <i> Defines Level 0 Arbitration for DMA channels +// <id> dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// <o> Level 0 Channel Priority Number <0x00-0xFF> +// <id> dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// <q> Priority Level 1 +// <i> Indicates whether Priority Level 1 is enabled or not +// <id> dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 0 +#endif + +// <o> Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// <i> Defines Level 1 Arbitration for DMA channels +// <id> dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// <o> Level 1 Channel Priority Number <0x00-0xFF> +// <id> dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// <q> Priority Level 2 +// <i> Indicates whether Priority Level 2 is enabled or not +// <id> dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// <o> Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// <i> Defines Level 2 Arbitration for DMA channels +// <id> dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// <o> Level 2 Channel Priority Number <0x00-0xFF> +// <id> dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// <q> Priority Level 3 +// <i> Indicates whether Priority Level 3 is enabled or not +// <id> dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// <o> Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// <i> Defines Level 3 Arbitration for DMA channels +// <id> dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// <o> Level 3 Channel Priority Number <0x00-0xFF> +// <id> dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// <q> Debug Run +// <i> Indicates whether Debug Run is enabled or not +// <id> dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// <e> Channel 0 settings +// <id> dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 0 is enabled or not +// <id> dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// </e> + +// <e> Channel 1 settings +// <id> dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 1 is enabled or not +// <id> dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// </e> + +// <e> Channel 2 settings +// <id> dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 2 is enabled or not +// <id> dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// </e> + +// <e> Channel 3 settings +// <id> dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 3 is enabled or not +// <id> dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// </e> + +// <e> Channel 4 settings +// <id> dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 4 is enabled or not +// <id> dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// </e> + +// <e> Channel 5 settings +// <id> dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 5 is enabled or not +// <id> dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// </e> + +// <e> Channel 6 settings +// <id> dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 6 is enabled or not +// <id> dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// </e> + +// <e> Channel 7 settings +// <id> dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 7 is enabled or not +// <id> dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// </e> + +// <e> Channel 8 settings +// <id> dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 8 is enabled or not +// <id> dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// </e> + +// <e> Channel 9 settings +// <id> dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 9 is enabled or not +// <id> dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// </e> + +// <e> Channel 10 settings +// <id> dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 10 is enabled or not +// <id> dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// </e> + +// <e> Channel 11 settings +// <id> dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 11 is enabled or not +// <id> dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// </e> + +// <e> Channel 12 settings +// <id> dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 12 is enabled or not +// <id> dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// </e> + +// <e> Channel 13 settings +// <id> dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 13 is enabled or not +// <id> dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// </e> + +// <e> Channel 14 settings +// <id> dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 14 is enabled or not +// <id> dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// </e> + +// <e> Channel 15 settings +// <id> dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// <q> Channel Enable +// <i> Indicates whether channel 15 is enabled or not +// <id> dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// </e> + +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_gclk_config.h b/atmel-samd/asf4/samd21/config/hpl_gclk_config.h new file mode 100644 index 000000000..790aa293a --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_gclk_config.h @@ -0,0 +1,618 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <e> Generic clock generator 0 configuration +// <i> Indicates whether generic clock 0 configuration is enabled or not +// <id> enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// <h> Generic Clock Generator Control +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_0_RUNSTDBY +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +// <id> gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif + +// <y> Generic clock generator 0 source +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M) +// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M) +// <i> This defines the clock source for generic clock generator 0 +// <id> gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SRC +#define CONF_GCLK_GEN_0_SRC GCLK_GENCTRL_SRC_OSC8M +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 0 division <0x0000-0xFFFF> +// <i> +// <id> gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif + +// </h> +// </e>// <e> Generic clock generator 1 configuration +// <i> Indicates whether generic clock 1 configuration is enabled or not +// <id> enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_1_RUNSTDBY +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +// <id> gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif + +// <y> Generic clock generator 1 source +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M) +// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M) +// <i> This defines the clock source for generic clock generator 1 +// <id> gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SRC +#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 1 division <0x0000-0xFFFF> +// <i> +// <id> gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif + +// </h> +// </e>// <e> Generic clock generator 2 configuration +// <i> Indicates whether generic clock 2 configuration is enabled or not +// <id> enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_2_RUNSTDBY +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +// <id> gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif + +// <y> Generic clock generator 2 source +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M) +// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M) +// <i> This defines the clock source for generic clock generator 2 +// <id> gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SRC +#define CONF_GCLK_GEN_2_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 2 division <0x0000-0xFFFF> +// <i> +// <id> gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif + +// </h> +// </e>// <e> Generic clock generator 3 configuration +// <i> Indicates whether generic clock 3 configuration is enabled or not +// <id> enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_3_RUNSTDBY +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +// <id> gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif + +// <y> Generic clock generator 3 source +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M) +// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M) +// <i> This defines the clock source for generic clock generator 3 +// <id> gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SRC +#define CONF_GCLK_GEN_3_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 3 division <0x0000-0xFFFF> +// <i> +// <id> gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif + +// </h> +// </e>// <e> Generic clock generator 4 configuration +// <i> Indicates whether generic clock 4 configuration is enabled or not +// <id> enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_4_RUNSTDBY +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +// <id> gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif + +// <y> Generic clock generator 4 source +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M) +// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M) +// <i> This defines the clock source for generic clock generator 4 +// <id> gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SRC +#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 4 division <0x0000-0xFFFF> +// <i> +// <id> gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif + +// </h> +// </e>// <e> Generic clock generator 5 configuration +// <i> Indicates whether generic clock 5 configuration is enabled or not +// <id> enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_5_RUNSTDBY +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +// <id> gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif + +// <y> Generic clock generator 5 source +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M) +// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M) +// <i> This defines the clock source for generic clock generator 5 +// <id> gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SRC +#define CONF_GCLK_GEN_5_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 5 division <0x0000-0xFFFF> +// <i> +// <id> gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif + +// </h> +// </e>// <e> Generic clock generator 6 configuration +// <i> Indicates whether generic clock 6 configuration is enabled or not +// <id> enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_6_RUNSTDBY +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +// <id> gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif + +// <y> Generic clock generator 6 source +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M) +// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M) +// <i> This defines the clock source for generic clock generator 6 +// <id> gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SRC +#define CONF_GCLK_GEN_6_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 6 division <0x0000-0xFFFF> +// <i> +// <id> gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif + +// </h> +// </e>// <e> Generic clock generator 7 configuration +// <i> Indicates whether generic clock 7 configuration is enabled or not +// <id> enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_7_RUNSTDBY +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +// <id> gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif + +// <y> Generic clock generator 7 source +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M) +// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M) +// <i> This defines the clock source for generic clock generator 7 +// <id> gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SRC +#define CONF_GCLK_GEN_7_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 7 division <0x0000-0xFFFF> +// <i> +// <id> gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif + +// </h> +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h b/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h new file mode 100644 index 000000000..88d6bb93f --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h @@ -0,0 +1,38 @@ +/* Auto-generated config file hpl_nvmctrl_config.h */ +#ifndef HPL_NVMCTRL_CONFIG_H +#define HPL_NVMCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Basic Settings + +// <o> Read Mode Selection +// <0x00=> No Miss Penalty +// <0x01=> Low Power +// <0x02=> Deterministic +// <id> nvm_arch_read_mode +#ifndef CONF_NVM_READ_MODE +#define CONF_NVM_READ_MODE 0 +#endif + +// <o> Power Reduction Mode During Sleep +// <0x00=> Wake On Access +// <0x01=> Wake Up Instant +// <0x03=> Disabled +// <id> nvm_arch_sleepprm +#ifndef CONF_NVM_SLEEPPRM +#define CONF_NVM_SLEEPPRM 0 +#endif + +// <q> Cache Disable +// <i> Indicate whether cache is disable or not +// <id> nvm_arch_cache +#ifndef CONF_NVM_CACHE +#define CONF_NVM_CACHE 0 +#endif + +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_NVMCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_pm_config.h b/atmel-samd/asf4/samd21/config/hpl_pm_config.h new file mode 100644 index 000000000..b4c704d12 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_pm_config.h @@ -0,0 +1,134 @@ +/* Auto-generated config file hpl_pm_config.h */ +#ifndef HPL_PM_CONFIG_H +#define HPL_PM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include <peripheral_clk_config.h> + +// <e> System Configuration +// <i> Indicates whether configuration for system is enabled or not +// <id> enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// <h> CPU Clock Settings +// <y> CPU Clock source +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 +// <i> This defines the clock source for the CPU +// <id> cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// <y> CPU clock Prescalar +// <PM_CPUSEL_CPUDIV_DIV1_Val"> 1 +// <PM_CPUSEL_CPUDIV_DIV2_Val"> 2 +// <PM_CPUSEL_CPUDIV_DIV4_Val"> 4 +// <PM_CPUSEL_CPUDIV_DIV8_Val"> 8 +// <PM_CPUSEL_CPUDIV_DIV16_Val"> 16 +// <PM_CPUSEL_CPUDIV_DIV32_Val"> 32 +// <PM_CPUSEL_CPUDIV_DIV64_Val"> 64 +// <PM_CPUSEL_CPUDIV_DIV128_Val"> 128 +// <i> Prescalar for Main CPU clock +// <id> cpu_div +#ifndef CONF_CPU_DIV +#define CONF_CPU_DIV PM_CPUSEL_CPUDIV_DIV1_Val +#endif +// </h> + +// <h> NVM Settings +// <o> NVM Wait States +// <i> These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// <id> nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// </h> + +// <h> APBA Clock Select +// <y> APBA clock prescalar +// <PM_APBASEL_APBADIV_DIV1"> 1 +// <PM_APBASEL_APBADIV_DIV2"> 2 +// <PM_APBASEL_APBADIV_DIV4"> 4 +// <PM_APBASEL_APBADIV_DIV8"> 8 +// <PM_APBASEL_APBADIV_DIV16"> 16 +// <PM_APBASEL_APBADIV_DIV32"> 32 +// <PM_APBASEL_APBADIV_DIV64"> 64 +// <PM_APBASEL_APBADIV_DIV128"> 128 +// <i> APBA clock prescalar +// <id> apba_div +#ifndef CONF_APBA_DIV +#define CONF_APBA_DIV PM_APBASEL_APBADIV_DIV1 +#endif +// </h> + +#if CONF_APBA_DIV < CONF_CPU_DIV +#warning APBA DIV cannot less than CPU DIV +#endif + +// <h> APBB Clock Select +// <y> APBB clock prescalar +// <PM_APBBSEL_APBBDIV_DIV1"> 1 +// <PM_APBBSEL_APBBDIV_DIV2"> 2 +// <PM_APBBSEL_APBBDIV_DIV4"> 4 +// <PM_APBBSEL_APBBDIV_DIV8"> 8 +// <PM_APBBSEL_APBBDIV_DIV16"> 16 +// <PM_APBBSEL_APBBDIV_DIV32"> 32 +// <PM_APBBSEL_APBBDIV_DIV64"> 64 +// <PM_APBBSEL_APBBDIV_DIV128"> 128 +// <i> APBB clock prescalar +// <id> apbb_div +#ifndef CONF_APBB_DIV +#define CONF_APBB_DIV PM_APBBSEL_APBBDIV_DIV1 +#endif +// </h> + +#if CONF_APBB_DIV < CONF_CPU_DIV +#warning APBB DIV cannot less than CPU DIV +#endif + +// <h> APBC Clock Select +// <y> APBC clock prescalar +// <PM_APBCSEL_APBCDIV_DIV1"> 1 +// <PM_APBCSEL_APBCDIV_DIV2"> 2 +// <PM_APBCSEL_APBCDIV_DIV4"> 4 +// <PM_APBCSEL_APBCDIV_DIV8"> 8 +// <PM_APBCSEL_APBCDIV_DIV16"> 16 +// <PM_APBCSEL_APBCDIV_DIV32"> 32 +// <PM_APBCSEL_APBCDIV_DIV64"> 64 +// <PM_APBCSEL_APBCDIV_DIV128"> 128 +// <i> APBC clock prescalar +// <id> apbc_div +#ifndef CONF_APBC_DIV +#define CONF_APBC_DIV PM_APBCSEL_APBCDIV_DIV1 +#endif +// </h> + +#if CONF_APBC_DIV < CONF_CPU_DIV +#warning APBC DIV cannot less than CPU DIV +#endif + +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_PM_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_rtc_config.h b/atmel-samd/asf4/samd21/config/hpl_rtc_config.h new file mode 100644 index 000000000..929c70c8c --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_rtc_config.h @@ -0,0 +1,117 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// <o> Prescaler configuration +// <0x0=>Peripheral clock divided by 1 +// <0x1=>Peripheral clock divided by 2 +// <0x2=>Peripheral clock divided by 4 +// <0x3=>Peripheral clock divided by 8 +// <0x4=>Peripheral clock divided by 16 +// <0x5=>Peripheral clock divided by 32 +// <0x6=>Peripheral clock divided by 64 +// <0x7=>Peripheral clock divided by 128 +// <0x8=>Peripheral clock divided by 256 +// <0x9=>Peripheral clock divided by 512 +// <0xA=>Peripheral clock divided by 1024 +// <i> These bits define the RTC clock relative to the peripheral clock +// <id> rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER +#define CONF_RTC_PRESCALER 0x0 + +#endif + +// <o> Compare Value <1-4294967295> +// <i> These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), +// <i> by default 1M clock input, 1 prescaler, 1024 compare value, the ticks period equals to 1ms. +// <id> rtc_arch_comp_val + +#ifndef CONF_RTC_COMP_VAL +#define CONF_RTC_COMP_VAL 1024 + +#endif + +// <e> Event control +// <id> rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// <q> Periodic Interval 0 Event Output +// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated +// <id> rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// <q> Periodic Interval 1 Event Output +// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated +// <id> rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// <q> Periodic Interval 2 Event Output +// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated +// <id> rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// <q> Periodic Interval 3 Event Output +// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated +// <id> rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// <q> Periodic Interval 4 Event Output +// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated +// <id> rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// <q> Periodic Interval 5 Event Output +// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated +// <id> rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// <q> Periodic Interval 6 Event Output +// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated +// <id> rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// <q> Periodic Interval 7 Event Output +// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated +// <id> rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// <q> Compare 0 Event Output +// <i> This bit indicates whether Compare O event is enabled and will be generated +// <id> rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// <q> Overflow Event Output +// <i> This bit indicates whether Overflow event is enabled and will be generated +// <id> rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// </e> + +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_sercom_config.h b/atmel-samd/asf4/samd21/config/hpl_sercom_config.h new file mode 100644 index 000000000..50515745d --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_sercom_config.h @@ -0,0 +1,534 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include <peripheral_clk_config.h> + +// Enable configuration of module +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_0_SPI_MODE +#define CONF_SERCOM_0_SPI_MODE 0x03 +#endif + +// <h> Basic Configuration + +// <q> Receive buffer enable +// <i> Enable receive buffer to receive data from slave (RXEN) +// <id> spi_master_rx_enable +#ifndef CONF_SERCOM_0_SPI_RXEN +#define CONF_SERCOM_0_SPI_RXEN 0x1 +#endif + +// <o> Character Size +// <i> Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// <id> spi_master_character_size +#ifndef CONF_SERCOM_0_SPI_CHSIZE +#define CONF_SERCOM_0_SPI_CHSIZE 0x0 +#endif + +// <o> Baud rate <1-12000000> +// <i> The SPI data transfer rate +// <id> spi_master_baud_rate +#ifndef CONF_SERCOM_0_SPI_BAUD +#define CONF_SERCOM_0_SPI_BAUD 50000 +#endif + +// </h> + +// <e> Advanced Configuration +// <id> spi_master_advanced +#ifndef CONF_SERCOM_0_SPI_ADVANCED +#define CONF_SERCOM_0_SPI_ADVANCED 0 +#endif + +// <o> Dummy byte <0x00-0x1ff> +// <id> spi_master_dummybyte +// <i> Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE +#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff +#endif + +// <o> Data Order +// <0=>MSB first +// <1=>LSB first +// <i> I least significant or most significant bit is shifted out first (DORD) +// <id> spi_master_arch_dord +#ifndef CONF_SERCOM_0_SPI_DORD +#define CONF_SERCOM_0_SPI_DORD 0x0 +#endif + +// <o> Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// <id> spi_master_arch_cpol +#ifndef CONF_SERCOM_0_SPI_CPOL +#define CONF_SERCOM_0_SPI_CPOL 0x0 +#endif + +// <o> Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// <id> spi_master_arch_cpha +#ifndef CONF_SERCOM_0_SPI_CPHA +#define CONF_SERCOM_0_SPI_CPHA 0x0 +#endif + +// <o> Immediate Buffer Overflow Notification +// <i> Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// <id> spi_master_arch_ibon +#ifndef CONF_SERCOM_0_SPI_IBON +#define CONF_SERCOM_0_SPI_IBON 0x0 +#endif + +// <q> Run in stand-by +// <i> Module stays active in stand-by sleep mode. (RUNSTDBY) +// <id> spi_master_arch_runstdby +#ifndef CONF_SERCOM_0_SPI_RUNSTDBY +#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0 +#endif + +// <o> Debug Stop Mode +// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// <id> spi_master_arch_dbgstop +#ifndef CONF_SERCOM_0_SPI_DBGSTOP +#define CONF_SERCOM_0_SPI_DBGSTOP 0 +#endif + +// </e> + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_0_SPI_AMODE_EN +#define CONF_SERCOM_0_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_AMODE +#define CONF_SERCOM_0_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDR +#define CONF_SERCOM_0_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDRMASK +#define CONF_SERCOM_0_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_SSDE +#define CONF_SERCOM_0_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_MSSEN +#define CONF_SERCOM_0_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_0_SPI_PLOADEN +#define CONF_SERCOM_0_SPI_PLOADEN 0 +#endif + +// <o> Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// <id> spi_master_rxpo +#ifndef CONF_SERCOM_0_SPI_RXPO +#define CONF_SERCOM_0_SPI_RXPO 2 +#endif + +// <o> Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// <id> spi_master_txpo +#ifndef CONF_SERCOM_0_SPI_TXPO +#define CONF_SERCOM_0_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_0_SPI_BAUD_RATE +#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1 +#endif + +#include <peripheral_clk_config.h> + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 1 +#endif + +// <h> Basic + +// <o> I2C Bus clock speed (Hz) <1-400000> +// <i> I2C Bus clock (SCL) speed measured in Hz +// <id> i2c_master_baud_rate +#ifndef CONF_SERCOM_1_I2CM_BAUD +#define CONF_SERCOM_1_I2CM_BAUD 100000 +#endif + +// </h> + +// <e> Advanced +// <id> i2c_master_advanced +#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 +#endif + +// <o> TRise (ns) <0-300> +// <i> Determined by the bus impedance, check electric characteristics in the datasheet +// <i> Standard Fast Mode: typical 215ns, max 300ns +// <i> Fast Mode +: typical 60ns, max 100ns +// <i> High Speed Mode: typical 20ns, max 40ns +// <id> i2c_master_arch_trise + +#ifndef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// <q> Master SCL Low Extended Time-Out (MEXTTOEN) +// <i> This enables the master SCL low extend time-out +// <id> i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN +#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 +#endif + +// <q> Slave SCL Low Extend Time-Out (SEXTTOEN) +// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// <id> i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN +#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 +#endif + +// <q> SCL Low Time-Out (LOWTOUT) +// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// <id> i2c_master_arch_lowtout +#ifndef CONF_SERCOM_1_I2CM_LOWTOUT +#define CONF_SERCOM_1_I2CM_LOWTOUT 0 +#endif + +// <o> Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be +// <id> i2c_master_arch_inactout +#ifndef CONF_SERCOM_1_I2CM_INACTOUT +#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 +#endif + +// <o> SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// <i> Defines the SDA hold time with respect to the negative edge of SCL +// <id> i2c_master_arch_sdahold +#ifndef CONF_SERCOM_1_I2CM_SDAHOLD +#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 +#endif + +// <q> Run in stand-by +// <i> Determine if the module shall run in standby sleep mode +// <id> i2c_master_arch_runstdby +#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY +#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 +#endif + +// <o> Debug Stop Mode +// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// <id> i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 +#endif + +// </e> + +#ifndef CONF_SERCOM_1_I2CM_SPEED +#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10)) +#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE +#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_1_I2CM_BAUD_RATE \ + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include <peripheral_clk_config.h> + +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 +#endif + +// <h> Basic Configuration + +// <q> Receive buffer enable +// <i> Enable input buffer in SERCOM module +// <id> usart_rx_enable +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 +#endif + +// <q> Transmitt buffer enable +// <i> Enable output buffer in SERCOM module +// <id> usart_tx_enable +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 +#endif + +// <o> Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// <i> Parity bit mode for USART frame +// <id> usart_parity +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 +#endif + +// <o> Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// <i> Data character size in USART frame +// <id> usart_character_size +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#endif + +// <o> Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// <i> Number of stop bits in USART frame +// <id> usart_stop_bit +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 +#endif + +// <o> Baud rate <1-3000000> +// <i> USART baud rate setting +// <id> usart_baud_rate +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 9600 +#endif + +// </h> + +// <e> Advanced configuration +// <id> usart_advanced +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 +#endif + +// <q> Run in stand-by +// <i> Keep the module running in standby sleep mode +// <id> usart_arch_runstdby +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#endif + +// <q> Immediate Buffer Overflow Notification +// <i> Controls when the BUFOVF status bit is asserted +// <id> usart_arch_ibon +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 +#endif + +// <q> Start of Frame Detection Enable +// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// <id> usart_arch_sfde +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 +#endif + +// <q> Collision Detection Enable +// <i> Collision detection enable +// <id> usart_arch_cloden +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 +#endif + +// <o> Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// <id> usart_arch_clock_mode +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 +#endif + +// <o> Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x3=>3x +// <i> How many over-sampling bits used when samling data state +// <id> usart_arch_sampr +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 +#endif + +// <o> Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// <i> Adjust which samples to use for data sampling in asynchronous mode +// <id> usart_arch_sampa +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 +#endif + +// <o> Fractional Part <0-7> +// <i> Fractional part of the baud rate if baud rate generator is in fractional mode +// <id> usart_arch_fractional +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#endif + +// <o> Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// <i> Data order of the data bits in the frame +// <id> usart_arch_dord +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_2_USART_CPOL 0 + +// <o> Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// <id> usart_arch_enc +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 +#endif + +// <o> Debug Stop Mode +// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// <id> usart_arch_dbgstop +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#endif + +// </e> + +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA09 */ +#endif + +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA08 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h b/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h new file mode 100644 index 000000000..ab4c48d52 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h @@ -0,0 +1,678 @@ +/* Auto-generated config file hpl_sysctrl_config.h */ +#ifndef HPL_SYSCTRL_CONFIG_H +#define HPL_SYSCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_DFLL_OPEN_LOOP_MODE 0 +#define CONF_DFLL_CLOSED_LOOP_MODE 1 + +#define CONF_XOSC_STARTUP_TIME_31MCS 0 +#define CONF_XOSC_STARTUP_TIME_61MCS 1 +#define CONF_XOSC_STARTUP_TIME_122MCS 2 +#define CONF_XOSC_STARTUP_TIME_244MCS 3 +#define CONF_XOSC_STARTUP_TIME_488MCS 4 +#define CONF_XOSC_STARTUP_TIME_977MCS 5 +#define CONF_XOSC_STARTUP_TIME_1953MCS 6 +#define CONF_XOSC_STARTUP_TIME_3906MCS 7 +#define CONF_XOSC_STARTUP_TIME_7813MCS 8 +#define CONF_XOSC_STARTUP_TIME_15625MCS 9 +#define CONF_XOSC_STARTUP_TIME_31250MCS 10 +#define CONF_XOSC_STARTUP_TIME_62500MCS 11 +#define CONF_XOSC_STARTUP_TIME_125000MCS 12 +#define CONF_XOSC_STARTUP_TIME_250000MCS 13 +#define CONF_XOSC_STARTUP_TIME_500000MCS 14 +#define CONF_XOSC_STARTUP_TIME_1000000MCS 15 + +#define CONF_OSC_STARTUP_TIME_92MCS 0 +#define CONF_OSC_STARTUP_TIME_122MCS 1 +#define CONF_OSC_STARTUP_TIME_183MCS 2 +#define CONF_OSC_STARTUP_TIME_305MCS 3 +#define CONF_OSC_STARTUP_TIME_549MCS 4 +#define CONF_OSC_STARTUP_TIME_1038MCS 5 +#define CONF_OSC_STARTUP_TIME_2014MCS 6 +#define CONF_OSC_STARTUP_TIME_3967MCS 7 + +#define CONF_XOSC32K_STARTUP_TIME_122MCS 0 +#define CONF_XOSC32K_STARTUP_TIME_1068MCS 1 +#define CONF_XOSC32K_STARTUP_TIME_65592MCS 2 +#define CONF_XOSC32K_STARTUP_TIME_125092MCS 3 +#define CONF_XOSC32K_STARTUP_TIME_500092MCS 4 +#define CONF_XOSC32K_STARTUP_TIME_1000092MCS 5 +#define CONF_XOSC32K_STARTUP_TIME_2000092MCS 6 +#define CONF_XOSC32K_STARTUP_TIME_4000092MCS 7 + +// <e> 8MHz Internal Oscillator Configuration +// <i> Indicates whether configuration for OSC8M is enabled or not +// <id> enable_osc8m +#ifndef CONF_OSC8M_CONFIG +#define CONF_OSC8M_CONFIG 1 +#endif + +// <h> 8MHz Internal Oscillator (OSC8M) Control +// <q> Internal 8M Oscillator Enable +// <i> Indicates whether Internal 8 Mhz Oscillator is enabled or not +// <id> osc8m_arch_enable +#ifndef CONF_OSC8M_ENABLE +#define CONF_OSC8M_ENABLE 1 +#endif + +// <q> On Demand Control +// <i> Indicates whether On Demand Control is enabled or not. +// <i> If enabled, the oscillator will only be running when requested by a peripheral. +// <i> If disabled, the oscillator will always be running when enabled. +// <id> osc8m_arch_ondemand +#ifndef CONF_OSC8M_ONDEMAND +#define CONF_OSC8M_ONDEMAND 1 +#endif + +// <q> Run In Standby +// <i> Run In standby Mode +// <i> If this bit is 0: The oscillator is disabled in standby sleep mode. +// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode. +// <id> osc8m_arch_runstdby +#ifndef CONF_OSC8M_RUNSTDBY +#define CONF_OSC8M_RUNSTDBY 0 +#endif + +// <y> Prescaler +// <SYSCTRL_OSC8M_PRESC_0_Val"> 1 +// <SYSCTRL_OSC8M_PRESC_1_Val"> 2 +// <SYSCTRL_OSC8M_PRESC_2_Val"> 4 +// <SYSCTRL_OSC8M_PRESC_3_Val"> 8 +// <i> Prescaler for Internal 8Mhz OSC +// <i> Default: No Prescaling +// <id> osc8m_presc +#ifndef CONF_OSC8M_PRESC +#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val +#endif + +// <q> Overwrite Default Osc Calibration +// <i> Overwrite Default Osc Calibration +// <id> osc8m_arch_overwrite_calibration +#ifndef CONF_OSC8M_OVERWRITE_CALIBRATION +#define CONF_OSC8M_OVERWRITE_CALIBRATION 0 +#endif + +// <o>Osc Calibration Value <0-65535> +// <i> Set the Oscillator Calibration Value +// <i> Default: 1 +// <id> osc8m_arch_calib +#ifndef CONF_OSC8M_CALIB +#define CONF_OSC8M_CALIB 0 +#endif + +// </h> +// </e> + +// <e> 32kHz Internal Oscillator Configuration +// <i> Indicates whether configuration for OSC32K is enabled or not +// <id> enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 0 +#endif + +// <h> 32kHz Internal Oscillator (OSC32K) Control +// <q> Internal 32K Oscillator Enable +// <i> Indicates whether Internal 32K Oscillator is enabled or not +// <id> osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif + +// <q> On Demand Control +// <i> Enable On Demand +// <i> If this bit is 0: The oscillator is always on, if enabled. +// <i> If this bit is 1, the oscillator will only be running when requested by a peripheral. +// <id> osc32k_arch_ondemand +#ifndef CONF_OSC32K_ONDEMAND +#define CONF_OSC32K_ONDEMAND 1 +#endif + +// <q> Run In Standby +// <i> Run In standby Mode +// <i> If this bit is 0: The oscillator is disabled in standby sleep mode. +// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode. +// <id> osc32k_arch_runstdby +#ifndef CONF_OSC32K_RUNSTDBY +#define CONF_OSC32K_RUNSTDBY 0 +#endif + +// <q> Enable 32Khz Output +// <i> Enable 32 Khz Output +// <id> osc32k_arch_en32k +#ifndef CONF_OSC32K_EN32K +#define CONF_OSC32K_EN32K 0 +#endif + +// <q> Enable 1K +// <i> Enable 1K +// <id> osc32k_arch_en1k +#ifndef CONF_OSC32K_EN1K +#define CONF_OSC32K_EN1K 0 +#endif + +// <q> Write Lock +// <i> Write Lock +// <id> osc32k_arch_wrtlock +#ifndef CONF_OSC32K_WRTLOCK +#define CONF_OSC32K_WRTLOCK 0 +#endif + +// <y> Start up time for the 32K Oscillator +// <CONF_OSC_STARTUP_TIME_92MCS"> 3 Clock Cycles (92us) +// <CONF_OSC_STARTUP_TIME_122MCS"> 4 Clock Cycles (122us) +// <CONF_OSC_STARTUP_TIME_183MCS"> 6 Clock Cycles (183us) +// <CONF_OSC_STARTUP_TIME_305MCS"> 10 Clock Cycles (305us) +// <CONF_OSC_STARTUP_TIME_549MCS"> 18 Clock Cycles (549us) +// <CONF_OSC_STARTUP_TIME_1038MCS"> 34 Clock Cycles (1038us) +// <CONF_OSC_STARTUP_TIME_2014MCS"> 66 Clock Cycles (2014us) +// <CONF_OSC_STARTUP_TIME_3967MCS"> 130 Clock Cycles (3967us) +// <i> Start Up Time for the 32K Oscillator +// <i> Default: 10 Clock Cycles (305us) +// <id> osc32k_arch_startup +#ifndef CONF_OSC32K_STARTUP +#define CONF_OSC32K_STARTUP CONF_OSC_STARTUP_TIME_92MCS +#endif + +// <q> Overwrite Default Osc Calibration +// <i> Overwrite Default Osc Calibration +// <id> osc32k_arch_overwrite_calibration +#ifndef CONF_OSC32K_OVERWRITE_CALIBRATION +#define CONF_OSC32K_OVERWRITE_CALIBRATION 0 +#endif + +// <o>Osc Calibration Value <0-65535> +// <i> Set the Oscillator Calibration Value +// <i> Default: 0 +// <id> osc32k_arch_calib +#ifndef CONF_OSC32K_CALIB +#define CONF_OSC32K_CALIB 0 +#endif + +// </h> +// </e> + +// <e> 32kHz External Crystal Oscillator Configuration +// <i> Indicates whether configuration for External 32K Osc is enabled or not +// <id> enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// <h> 32kHz External Crystal Oscillator (XOSC32K) Control +// <q> External 32K Oscillator Enable +// <i> Indicates whether External 32K Oscillator is enabled or not +// <id> xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// <q> On Demand +// <i> Enable On Demand. +// <i> If this bit is 0: The oscillator is always on, if enabled. +// <i> If this bit is 1: the oscillator will only be running when requested by a peripheral. +// <id> xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// <q> Run In Standby +// <i> Run In standby Mode +// <i> If this bit is 0: The oscillator is disabled in standby sleep mode. +// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode. +// <id> xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// <q> Enable 1K +// <i> Enable 1K +// <id> xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// <q> Enable 32Khz Output +// <i> Enable 32 Khz Output +// <id> xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// <q> Enable XTAL +// <i> Enable XTAL +// <id> xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 0 +#endif + +// <q> Write Lock +// <i> Write Lock +// <id> xosc32k_arch_wrtlock +#ifndef CONF_XOSC32K_WRTLOCK +#define CONF_XOSC32K_WRTLOCK 0 +#endif + +// <q> Automatic Amplitude Control Enable +// <i> Indicates whether Automatic Amplitude Control is Enabled or not +// <id> xosc32k_arch_aampen +#ifndef CONF_XOSC32K_AAMPEN +#define CONF_XOSC32K_AAMPEN 0 +#endif + +// <y> Start up time for the 32K Oscillator +// <CONF_XOSC32K_STARTUP_TIME_122MCS"> 122 us +// <CONF_XOSC32K_STARTUP_TIME_1068MCS"> 1068 us +// <CONF_XOSC32K_STARTUP_TIME_65592MCS"> 62592 us +// <CONF_XOSC32K_STARTUP_TIME_125092MCS"> 1125092 us +// <CONF_XOSC32K_STARTUP_TIME_500092MCS"> 500092 us +// <CONF_XOSC32K_STARTUP_TIME_1000092MCS"> 1000092 us +// <CONF_XOSC32K_STARTUP_TIME_2000092MCS"> 2000092 us +// <CONF_XOSC32K_STARTUP_TIME_4000092MCS"> 4000092 us +// <i> Start Up Time for the 32K Oscillator +// <i> Default: 122 us +// <id> xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP CONF_XOSC32K_STARTUP_TIME_122MCS +#endif + +// </h> +// </e> + +// <e> External Multipurpose Crystal Oscillator Configuration +// <i> Indicates whether configuration for External Multipurpose Osc is enabled or not +// <id> enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// <o> Frequency <400000-32000000> +// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// <id> xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// <h> External Multipurpose Crystal Oscillator (XOSC) Control +// <q> Enable +// <i> Indicates whether External Multipurpose Oscillator is enabled or not +// <id> xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// <q> On Demand +// <i> Enable On Demand +// <i> If this bit is 0: The oscillator is always on, if enabled. +// <i> If this bit is 1: the oscillator will only be running when requested by a peripheral. +// <id> xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// <q> Run In Standby +// <i> Run In standby Mode +// <i> If this bit is 0: The oscillator is disabled in standby sleep mode. +// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode. +// <id> xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// <q> Enable XTAL +// <i> Enable XTAL +// <id> xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif + +// <q> Automatic Amplitude Control Enable +// <i> Indicates whether Automatic Amplitude Control is Enabled or not +// <id> xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// <y> Gain of the Oscillator +// <SYSCTRL_XOSC_GAIN_0_Val"> 2Mhz +// <SYSCTRL_XOSC_GAIN_1_Val"> 4Mhz +// <SYSCTRL_XOSC_GAIN_2_Val"> 8Mhz +// <SYSCTRL_XOSC_GAIN_3_Val"> 16Mhz +// <SYSCTRL_XOSC_GAIN_4_Val"> 30Mhz +// <i> Select the Gain of the oscillator +// <id> xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val +#endif + +// <y> Start up time for the External Oscillator +// <CONF_XOSC_STARTUP_TIME_31MCS"> 31 us +// <CONF_XOSC_STARTUP_TIME_61MCS"> 61 us +// <CONF_XOSC_STARTUP_TIME_122MCS"> 122 us +// <CONF_XOSC_STARTUP_TIME_244MCS"> 244 us +// <CONF_XOSC_STARTUP_TIME_488MCS"> 488 us +// <CONF_XOSC_STARTUP_TIME_977MCS"> 977 us +// <CONF_XOSC_STARTUP_TIME_1953MCS"> 1953 us +// <CONF_XOSC_STARTUP_TIME_3906MCS"> 3906 us +// <CONF_XOSC_STARTUP_TIME_7813MCS"> 7813 us +// <CONF_XOSC_STARTUP_TIME_15625MCS"> 15625 us +// <CONF_XOSC_STARTUP_TIME_31250MCS"> 31250 us +// <CONF_XOSC_STARTUP_TIME_62500MCS"> 62500 us +// <CONF_XOSC_STARTUP_TIME_125000MCS"> 125000 us +// <CONF_XOSC_STARTUP_TIME_250000MCS"> 250000 us +// <CONF_XOSC_STARTUP_TIME_500000MCS"> 500000 us +// <CONF_XOSC_STARTUP_TIME_1000000MCS"> 1000000 us +// <i> Start Up Time for the External Oscillator +// <i> Default: 31 us +// <id> xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS +#endif + +// </h> +// </e> + +// <e> 32kHz Ultra Low Power Internal Oscillator Configuration +// <i> Indicates whether configuration for OSCULP32K is enabled or not +// <id> enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// <h> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control +// <q> Write Lock +// <i> Locks the OSCULP32K register for future writes to fix the OSCULP32K configuration +// <id> osculp32k_arch_wrtlock +#ifndef CONF_OSCULP32K_WRTLOCK +#define CONF_OSCULP32K_WRTLOCK 0 +#endif + +// <q> Overwrite Default Osc Calibration +// <i> Overwrite Default Osc Calibration +// <id> osculp32k_arch_overwrite_calibration +#ifndef CONF_OSCULP32K_OVERWRITE_CALIBRATION +#define CONF_OSCULP32K_OVERWRITE_CALIBRATION 0 +#endif + +// <o>Osc Calibration Value <0-255> +// <i> Set the Oscillator Calibration Value +// <i> Default: 0 +// <id> osculp32k_arch_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0 +#endif + +// </h> +// </e> + +// <e> DFLL Configuration +// <i> Indicates whether configuration for DFLL is enabled or not +// <id> enable_dfll48m +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// <y> Reference Clock Source +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 +// <i> Select the clock source. +// <id> dfll48m_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_CLKCTRL_GEN_GCLK4_Val +#endif + +// <h> DFLL Control +// <q> DFLL Enable +// <i> Indicates whether DFLL is enabled or not +// <id> dfll48m_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// <q> Wait Lock +// <i> Indicates whether Wait Lock is Enables or not +// <id> dfll48m_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 0 +#endif + +// <q> Bypass Coarse Lock +// <i> Indicates whether Bypass coarse lock is enabled or not +// <id> dfll48m_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// <q> Quick Lock Disable +// <i> Quick Lock Disable +// <id> dfll48m_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// <q> Chill Cycle Disable +// <i> Chill Cycle Disable +// <id> dfll48m_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// <q> On Demand +// <i> Enable On Demand +// <i> If this bit is 0: The DFLL is always on, if enabled. +// <i> If this bit is 1: the DFLL will only be running when requested by a peripheral. +// <id> dfll48m_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 1 +#endif + +// <q> Run In Standby +// <i> Run In standby Mode +// <i> If this bit is 0: The DFLL is disabled in standby sleep mode. +// <i> If this bit is 1: The DFLL is not stopped in standby sleep mode. +// <id> dfll48m_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// <q> USB Clock Recovery Mode +// <i> USB Clock Recovery Mode +// <id> dfll48m_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 1 +#endif + +#if CONF_DFLL_USBCRM == 1 +#if CONF_DFLL_QLDIS == 1 +#warning QLDIS must be cleared to speed up the lock phase +#endif +#if CONF_DFLL_CCDIS == 0 +#warning CCDIS should be set to speed up the lock phase +#endif +#endif + +// <q> Lose Lock After Wake +// <i> Lose Lock After Wake +// <id> dfll48m_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// <q> Stable DFLL Frequency +// <i> Stable DFLL Frequency +// <i> If 0: FINE calibration tracks changes in output frequency. +// <i> If 1: FINE calibration register value will be fixed after a fine lock. +// <id> dfll48m_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// <y> Operating Mode Selection +// <CONF_DFLL_OPEN_LOOP_MODE"> Open Loop Mode +// <CONF_DFLL_CLOSED_LOOP_MODE"> Closed Loop Mode +// <i> Mode +// <id> dfll48m_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE CONF_DFLL_CLOSED_LOOP_MODE +#endif + +// <o> Coarse Maximum Step <0x0-0x1F> +// <id> dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 1 +#endif + +// <o> Fine Maximum Step <0x0-0x3FF> +// <id> dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 1 +#endif + +// <o>DFLL Multiply Factor<0-65535> +// <i> Set the DFLL Multiply Factor +// <i> Default: 0 +// <id> dfll48m_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0 +#endif + +// <e> DFLL Calibration Overwrite +// <i> Indicates whether Overwrite Calibration value of DFLL +// <id> dfll48m_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 1 +#endif + +// <o> Coarse Value <0x0-0x3F> +// <id> dfll48m_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0xa) +#endif + +// <o> Fine Value <0x0-0x3FF> +// <id> dfll48m_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x200) +#endif + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 +#define CONF_DEFAULT_CORASE \ + ((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos) + +#define CONF_DFLLVAL \ + SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \ + | SYSCTRL_DFLLVAL_FINE(512) + +#else +#define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE) + +#endif +//</e> + +// </h> +// </e> + +// <e> DPLL Configuration +// <i> Indicates whether configuration for DPLL is enabled or not +// <id> enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 0 +#endif + +// <y> Reference Clock Source +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 +// <i> Select the clock source. +// <id> fdpll96m_ref_clock +#ifndef CONF_DPLL_GCLK +#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +#if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K) +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val +#elif (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC) +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val +#else +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val +#endif + +// <h> DPLL Control +// <q> ON Demand +// <i> Enable On Demand +// <i> If this bit is 0: The DFLL is always on, if enabled. +// <i> If this bit is 1: the DFLL will only be running when requested by a peripheral. +// <id> fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// <q> Run In Standby +// <i> Run In standby Mode +// <i> If this bit is 0: The DFLL is disabled in standby sleep mode. +// <i> If this bit is 1: The DFLL is not stopped in standby sleep mode. +// <id> fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// <q> DPLL Enable +// <i> Indicates whether DPLL is enabled or not +// <id> fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 0 +#endif + +// <q> Lock ByPass +// <i> Enabling it makes the CLK_FDPLL96M always running otherwise it will be turned off when lock signal is low +// <id> fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// <o>Clock Divider <0-2047> +// <i> Clock Division Factor (Applicable if reference clock is XOSC) +// <id> fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// <o>DPLL LDRFRAC<0-15> +// <i> Set the fractional part of the frequency multiplier. +// <id> fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 13 +#endif + +// <o>DPLL LDR <0-4095> +// <i> Set the integer part of the frequency multiplier. +// <id> fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 1463 +#endif + +// </h> +// </e> + +#define CONF_DPLL_LTIME SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val +#define CONF_DPLL_WUF 0 +#define CONF_DPLL_LPEN 0 +#define CONF_DPLL_FILTER SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val + +// <<< end of configuration section >>> + +#endif // HPL_SYSCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_systick_config.h b/atmel-samd/asf4/samd21/config/hpl_systick_config.h new file mode 100644 index 000000000..a7f2f3620 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Advanced settings +// <q> SysTick exception request +// <i> Indicates whether the generation of SysTick exception is enabled or not +// <id> systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_tc_config.h b/atmel-samd/asf4/samd21/config/hpl_tc_config.h new file mode 100644 index 000000000..90e9b0735 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_tc_config.h @@ -0,0 +1,181 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include <peripheral_clk_config.h> + +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 1 +#endif + +// <h> Basic settings + +// <y> Prescaler +// <TC_CTRLA_PRESCALER_DIV1_Val"> No division +// <TC_CTRLA_PRESCALER_DIV2_Val"> Divide by 2 +// <TC_CTRLA_PRESCALER_DIV4_Val"> Divide by 4 +// <TC_CTRLA_PRESCALER_DIV8_Val"> Divide by 8 +// <TC_CTRLA_PRESCALER_DIV16_Val"> Divide by 16 +// <TC_CTRLA_PRESCALER_DIV64_Val"> Divide by 64 +// <TC_CTRLA_PRESCALER_DIV256_Val"> Divide by 256 +// <TC_CTRLA_PRESCALER_DIV1024_Val"> Divide by 1024 +// <i> This defines the prescaler value +// <id> tc_prescaler +#ifndef CONF_TC3_PRESCALER +#define CONF_TC3_PRESCALER TC_CTRLA_PRESCALER_DIV8_Val +#endif + +//<o> Period Value <0x00000000-0xFFFFFFFF> +// <id> tc_per +#ifndef CONF_TC3_PER +#define CONF_TC3_PER 0x32 +#endif +// </h> + +// <h> PWM Waveform Output settings +// <o> Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// <i> The unit of this value is us. +// <id> tc_arch_wave_per_val +#ifndef CONF_TC3_WAVE_PER_VAL +#define CONF_TC3_WAVE_PER_VAL 0x3e8 +#endif + +// <o> Waveform Duty Value (0.1%) <0x00-0x03E8> +// <i> The unit of this value is 1/1000. +// <id> tc_arch_wave_duty_val +#ifndef CONF_TC3_WAVE_DUTY_VAL +#define CONF_TC3_WAVE_DUTY_VAL 0x1f4 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC3_CC0 \ + ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 64000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 256000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1024000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) +#endif + +// </h> + +// <h> Advanced settings +// <y> Mode +// <TC_CTRLA_MODE_COUNT16_Val"> Counter in 16-bit mode +// <TC_CTRLA_MODE_COUNT32_Val"> Counter in 32-bit mode +// <i> These bits mode +// <id> tc_arch_mode +#ifndef CONF_TC3_MODE +#define CONF_TC3_MODE TC_CTRLA_MODE_COUNT16_Val +#endif +// </h> + +// <h> Advanced settings +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val + +// <q> Run in standby +// <i> Indicates whether the will continue running in standby sleep mode or not +// <id> tc_arch_runstdby +#ifndef CONF_TC3_RUNSTDBY +#define CONF_TC3_RUNSTDBY 0 +#endif + +// <y> Prescaler and Counter Synchronization Selection +// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK +// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock +// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter +// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// <id> tc_arch_presync +#ifndef CONF_TC3_PRESCSYNC +#define CONF_TC3_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_DIR 0 +//#define CONF_TC3_ONESHOT 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_INVEN0 0 +//#define CONF_TC3_INVEN1 0 +//#define CONF_TC3_CPTEN0 0 +//#define CONF_TC3_CPTEN1 0 + +// <q> Debug Running Mode +// <i> Indicates whether the Debug Running Mode is enabled or not +// <id> tc_arch_dbgrun +#ifndef CONF_TC3_DBGRUN +#define CONF_TC3_DBGRUN 0 +#endif + +// </h> + +// <e> Event control +// <id> timer_event_control +#ifndef CONF_TC3_EVENT_CONTROL_ENABLE +#define CONF_TC3_EVENT_CONTROL_ENABLE 0 +#endif + +// <q> Overflow/Underflow Event Output +// <i> Generates event for counter overflows/underflows +// <id> tc_arch_ovfeo +#ifndef CONF_TC3_OVFEO +#define CONF_TC3_OVFEO 0 +#endif + +// <q> TC Event Asynchronous input +// <i> Enables Asynchronous input events to the TC +// <id> tc_arch_tcei +#ifndef CONF_TC3_TCEI +#define CONF_TC3_TCEI 0 +#endif + +// <q> TC Inverted Event Input Polarity +// <i> Used to invert the asynchronous input event source +// <id> tc_arch_tceinv +#ifndef CONF_TC3_TCINV +#define CONF_TC3_TCINV 0 +#endif + +// <y> Event Action +// <i> Defines the event action the TC will perform on an event +// <TC_EVCTRL_EVACT_OFF_Val"> Event action disabled +// <TC_EVCTRL_EVACT_RETRIGGER_Val"> Start, restart or retrigger TC on event +// <TC_EVCTRL_EVACT_COUNT_Val"> Count on event +// <TC_EVCTRL_EVACT_START_Val"> Start TC on event +// <TC_EVCTRL_EVACT_PPW_Val"> Period captured in CC0, pulse width in CC1 +// <TC_EVCTRL_EVACT_PWP_Val"> Period captured in CC1, pulse width in CC0 +// <id> tc_arch_evact +#ifndef CONF_TC3_EVACT +#define CONF_TC3_EVACT TC_EVCTRL_EVACT_OFF_Val +#endif + +// <q> Match/Capture channel 0 Event +// <i> Enables the generation of an event for every match or capture on channel 0 +// <id> tc_arch_mceo0 +#ifndef CONF_TC3_MCEO0 +#define CONF_TC3_MCEO0 0 +#endif +// <q> Match/Capture channel 1 Event +// <i> Enables the generation of an event for every match or capture on channel 1 +// <id> tc_arch_mceo1 +#ifndef CONF_TC3_MCEO1 +#define CONF_TC3_MCEO1 0 +#endif + +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_usb_config.h b/atmel-samd/asf4/samd21/config/hpl_usb_config.h new file mode 100644 index 000000000..73a9fea44 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_usb_config.h @@ -0,0 +1,355 @@ +/* Auto-generated config file hpl_usb_config.h */ +#ifndef HPL_USB_CONFIG_H +#define HPL_USB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_USB_N_0 0 +#define CONF_USB_N_1 1 +#define CONF_USB_N_2 2 +#define CONF_USB_N_3 3 +#define CONF_USB_N_4 4 +#define CONF_USB_N_5 5 +#define CONF_USB_N_6 6 +#define CONF_USB_N_7 7 +#define CONF_USB_N_8 8 +#define CONF_USB_N_9 9 +#define CONF_USB_N_10 10 +#define CONF_USB_N_11 11 +#define CONF_USB_N_12 12 +#define CONF_USB_N_13 13 +#define CONF_USB_N_14 14 +#define CONF_USB_N_15 15 + +#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) +#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) + +// <h> USB Device HAL Configuration + +// <y> Max number of endpoints supported +// <i> Limits the number of endpoints (described by EP address) can be used in app. +// <CONF_USB_N_1"> 1 (EP0 only) +// <CONF_USB_N_2"> 2 (EP0 + 1 endpoint) +// <CONF_USB_N_3"> 3 (EP0 + 2 endpoints) +// <CONF_USB_N_4"> 4 (EP0 + 3 endpoints) +// <CONF_USB_N_5"> 5 (EP0 + 4 endpoints) +// <CONF_USB_N_6"> 6 (EP0 + 5 endpoints) +// <CONF_USB_N_7"> 7 (EP0 + 6 endpoints) +// <CONF_USB_N_8"> 8 (EP0 + 7 endpoints) +// <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config) +// <id> usbd_num_ep_sp +#ifndef CONF_USB_D_NUM_EP_SP +#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 +#endif + +// </h> + +// <y> Max Endpoint Number supported +// <i> Limits the max endpoint number. +// <i> USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. +// <i> Reduce the value according to specific device design, to cut-off memory usage. +// <CONF_USB_N_0"> 0 (only EP0) +// <CONF_USB_N_1"> 1 (EP 0x81 or 0x01) +// <CONF_USB_N_2"> 2 (EP 0x82 or 0x02) +// <CONF_USB_N_3"> 3 (EP 0x83 or 0x03) +// <CONF_USB_N_4"> 4 (EP 0x84 or 0x04) +// <CONF_USB_N_5"> 5 (EP 0x85 or 0x05) +// <CONF_USB_N_6"> 6 (EP 0x86 or 0x06) +// <CONF_USB_N_7"> 7 (EP 0x87 or 0x07) +// <CONF_USB_EP_N_MAX"> Max possible (by HW) +// <i> The number of physical endpoints - 1 +// <id> usbd_arch_max_ep_n +#ifndef CONF_USB_D_MAX_EP_N +#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 +#endif + +// <y> USB Speed Limit +// <i> Limits the working speed of the device. +// <USB_SPEED_FS"> Full speed +// <USB_SPEED_LS"> Low Speed +// <id> usbd_arch_speed +#ifndef CONF_USB_D_SPEED +#define CONF_USB_D_SPEED USB_SPEED_FS +#endif + +// <o> Cache buffer size for EP0 +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <id> usb_arch_ep0_cache +#ifndef CONF_USB_EP0_CACHE +#define CONF_USB_EP0_CACHE 64 +#endif + +// <h> Cache configuration EP1 +// <o> Cache buffer size for EP1 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep1_cache +#ifndef CONF_USB_EP1_CACHE +#define CONF_USB_EP1_CACHE 64 +#endif + +// <o> Cache buffer size for EP1 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep1_I_CACHE +#ifndef CONF_USB_EP1_I_CACHE +#define CONF_USB_EP1_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP2 +// <o> Cache buffer size for EP2 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep2_cache +#ifndef CONF_USB_EP2_CACHE +#define CONF_USB_EP2_CACHE 64 +#endif + +// <o> Cache buffer size for EP2 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep2_I_CACHE +#ifndef CONF_USB_EP2_I_CACHE +#define CONF_USB_EP2_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP3 +// <o> Cache buffer size for EP3 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep3_cache +#ifndef CONF_USB_EP3_CACHE +#define CONF_USB_EP3_CACHE 64 +#endif + +// <o> Cache buffer size for EP3 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep3_I_CACHE +#ifndef CONF_USB_EP3_I_CACHE +#define CONF_USB_EP3_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP4 +// <o> Cache buffer size for EP4 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep4_cache +#ifndef CONF_USB_EP4_CACHE +#define CONF_USB_EP4_CACHE 64 +#endif + +// <o> Cache buffer size for EP4 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep4_I_CACHE +#ifndef CONF_USB_EP4_I_CACHE +#define CONF_USB_EP4_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP5 +// <o> Cache buffer size for EP5 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep5_cache +#ifndef CONF_USB_EP5_CACHE +#define CONF_USB_EP5_CACHE 64 +#endif + +// <o> Cache buffer size for EP5 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep5_I_CACHE +#ifndef CONF_USB_EP5_I_CACHE +#define CONF_USB_EP5_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP6 +// <o> Cache buffer size for EP6 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep6_cache +#ifndef CONF_USB_EP6_CACHE +#define CONF_USB_EP6_CACHE 64 +#endif + +// <o> Cache buffer size for EP6 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep6_I_CACHE +#ifndef CONF_USB_EP6_I_CACHE +#define CONF_USB_EP6_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP7 +// <o> Cache buffer size for EP7 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep7_cache +#ifndef CONF_USB_EP7_CACHE +#define CONF_USB_EP7_CACHE 64 +#endif + +// <o> Cache buffer size for EP7 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep7_I_CACHE +#ifndef CONF_USB_EP7_I_CACHE +#define CONF_USB_EP7_I_CACHE 0 +#endif +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_USB_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/peripheral_clk_config.h b/atmel-samd/asf4/samd21/config/peripheral_clk_config.h new file mode 100644 index 000000000..f3bb927f9 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/peripheral_clk_config.h @@ -0,0 +1,369 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <y> ADC Clock Source +// <id> adc_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the clock source for ADC. +#ifndef CONF_GCLK_ADC_SRC +#define CONF_GCLK_ADC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_ADC_FREQUENCY + * \brief ADC's Clock frequency + */ +#ifndef CONF_GCLK_ADC_FREQUENCY +#define CONF_GCLK_ADC_FREQUENCY 1000000 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +// <y> Core Clock Source +// <id> core_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// <y> Slow Clock Source +// <id> slow_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000 +#endif + +// <y> Core Clock Source +// <id> core_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// <y> Slow Clock Source +// <id> slow_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 400000 +#endif + +// <y> Core Clock Source +// <id> core_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// <y> Slow Clock Source +// <id> slow_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 400000 +#endif + +// <y> RTC Clock Source +// <id> rtc_clk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 1000000 +#endif + +// <y> TC Clock Source +// <id> tc_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the clock source for TC. +#ifndef CONF_GCLK_TC3_SRC +#define CONF_GCLK_TC3_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC3_FREQUENCY + * \brief TC3's Clock frequency + */ +#ifndef CONF_GCLK_TC3_FREQUENCY +#define CONF_GCLK_TC3_FREQUENCY 1000000 +#endif + +// <y> DAC Clock Source +// <id> dac_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the clock source for DAC. +#ifndef CONF_GCLK_DAC_SRC +#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_DAC_FREQUENCY + * \brief DAC's Clock frequency + */ +#ifndef CONF_GCLK_DAC_FREQUENCY +#define CONF_GCLK_DAC_FREQUENCY 1000000 +#endif + +// <y> USB Clock Source +// <id> usb_gclk_selection + +// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <i> Select the clock source for USB. +#ifndef CONF_GCLK_USB_SRC +#define CONF_GCLK_USB_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_USB_FREQUENCY + * \brief USB's Clock frequency + */ +#ifndef CONF_GCLK_USB_FREQUENCY +#define CONF_GCLK_USB_FREQUENCY 1000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H |