Move to ASF4 and introduce SAMD51 support. (#258)3.0.0-alpha.0

* atmel-samd: Remove ASF3. This will break builds.

* atmel-samd: Add ASF4 for the SAMD21 and SAMD51.

* Introduce the supervisor concept to facilitate porting.

The supervisor is the code which runs individual MicroPython VMs. By
splitting it out we make it more consistent and easier to find.

This also adds very basic SAMD21 and SAMD51 support using the
supervisor. Only the REPL currently works.

This begins the work for #178.

26 files changed, 69980 insertions, 0 deletions

diff --git a/atmel-samd/asf4/samd21/hri/hri_ac_d21.h b/atmel-samd/asf4/samd21/hri/hri_ac_d21.h
new file mode 100644
index 000000000..3efd86b22
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_ac_d21.h
@@ -0,0 +1,1586 @@
+/**
+ * \file
+ *
+ * \brief SAM AC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_AC_COMPONENT_
+#ifndef _HRI_AC_D21_H_INCLUDED_
+#define _HRI_AC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AC_CRITICAL_SECTIONS)
+#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AC_CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_ac_evctrl_reg_t;
+typedef uint32_t hri_ac_compctrl_reg_t;
+typedef uint8_t  hri_ac_ctrla_reg_t;
+typedef uint8_t  hri_ac_ctrlb_reg_t;
+typedef uint8_t  hri_ac_intenset_reg_t;
+typedef uint8_t  hri_ac_intflag_reg_t;
+typedef uint8_t  hri_ac_scaler_reg_t;
+typedef uint8_t  hri_ac_statusa_reg_t;
+typedef uint8_t  hri_ac_statusb_reg_t;
+typedef uint8_t  hri_ac_statusc_reg_t;
+typedef uint8_t  hri_ac_winctrl_reg_t;
+
+static inline void hri_ac_wait_for_sync(const void *const hw)
+{
+	while (((const Ac *)hw)->STATUSB.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_ac_is_syncing(const void *const hw)
+{
+	return ((const Ac *)hw)->STATUSB.bit.SYNCBUSY;
+}
+
+static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+}
+
+static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+}
+
+static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+}
+
+static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+}
+
+static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+}
+
+static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+}
+
+static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data)
+{
+	((Ac *)hw)->INTENSET.reg = data;
+	((Ac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	((Ac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= ~AC_CTRLA_ENABLE;
+	tmp |= value << AC_CTRLA_ENABLE_Pos;
+	((Ac *)hw)->CTRLA.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_RUNSTDBY_Msk;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_RUNSTDBY_Msk) >> AC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= ~AC_CTRLA_RUNSTDBY_Msk;
+	tmp |= value << AC_CTRLA_RUNSTDBY_Pos;
+	((Ac *)hw)->CTRLA.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_RUNSTDBY_Msk;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_RUNSTDBY_Msk;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_LPMUX_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_LPMUX;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_LPMUX_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_LPMUX) >> AC_CTRLA_LPMUX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_CTRLA_LPMUX_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= ~AC_CTRLA_LPMUX;
+	tmp |= value << AC_CTRLA_LPMUX_Pos;
+	((Ac *)hw)->CTRLA.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_LPMUX_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_LPMUX;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_LPMUX_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_LPMUX;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw)
+{
+	return ((Ac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO0;
+	tmp |= value << AC_EVCTRL_COMPEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO1;
+	tmp |= value << AC_EVCTRL_COMPEO1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_WINEO0;
+	tmp |= value << AC_EVCTRL_WINEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI0;
+	tmp |= value << AC_EVCTRL_COMPEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI1;
+	tmp |= value << AC_EVCTRL_COMPEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WEN0;
+	tmp |= value << AC_WINCTRL_WEN0_Pos;
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WINTSEL0_Msk;
+	tmp |= AC_WINCTRL_WINTSEL0(data);
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->WINCTRL.reg;
+}
+
+static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_ENABLE;
+	tmp |= value << AC_COMPCTRL_ENABLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SINGLE;
+	tmp |= value << AC_COMPCTRL_SINGLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SWAP;
+	tmp |= value << AC_COMPCTRL_SWAP_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_HYST_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_HYST_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST) >> AC_COMPCTRL_HYST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYST_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYST;
+	tmp |= value << AC_COMPCTRL_HYST_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYST_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYST_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index,
+                                                                 hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SPEED_Msk;
+	tmp |= AC_COMPCTRL_SPEED(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_INTSEL_Msk;
+	tmp |= AC_COMPCTRL_INTSEL(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXNEG_Msk;
+	tmp |= AC_COMPCTRL_MUXNEG(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXPOS_Msk;
+	tmp |= AC_COMPCTRL_MUXPOS(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index,
+                                                               hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_OUT_Msk;
+	tmp |= AC_COMPCTRL_OUT(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_FLEN_Msk;
+	tmp |= AC_COMPCTRL_FLEN(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	hri_ac_wait_for_sync(hw);
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ac *)hw)->COMPCTRL[index].reg;
+}
+
+static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index,
+                                                             hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= ~AC_SCALER_VALUE_Msk;
+	tmp |= AC_SCALER_VALUE(data);
+	((Ac *)hw)->SCALER[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index)
+{
+	return ((Ac *)hw)->SCALER[index].reg;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos;
+}
+
+static inline bool hri_ac_get_STATUSB_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_SYNCBUSY) >> AC_STATUSB_SYNCBUSY_Pos;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_ac_get_STATUSC_STATE0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_STATE0) >> AC_STATUSC_STATE0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSC_STATE1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_STATE1) >> AC_STATUSC_STATE1_Pos;
+}
+
+static inline hri_ac_statusc_reg_t hri_ac_get_STATUSC_WSTATE0_bf(const void *const hw, hri_ac_statusc_reg_t mask)
+{
+	return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_WSTATE0(mask)) >> AC_STATUSC_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusc_reg_t hri_ac_read_STATUSC_WSTATE0_bf(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_WSTATE0_Msk) >> AC_STATUSC_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusc_reg_t hri_ac_get_STATUSC_reg(const void *const hw, hri_ac_statusc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusc_reg_t hri_ac_read_STATUSC_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSC.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AC_D21_H_INCLUDED */
+#endif /* _SAMD21_AC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_adc_d21.h b/atmel-samd/asf4/samd21/hri/hri_adc_d21.h
new file mode 100644
index 000000000..f511c59f4
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_adc_d21.h
@@ -0,0 +1,2513 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_ADC_COMPONENT_
+#ifndef _HRI_ADC_D21_H_INCLUDED_
+#define _HRI_ADC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ADC_CRITICAL_SECTIONS)
+#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ADC_CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_adc_calib_reg_t;
+typedef uint16_t hri_adc_ctrlb_reg_t;
+typedef uint16_t hri_adc_gaincorr_reg_t;
+typedef uint16_t hri_adc_offsetcorr_reg_t;
+typedef uint16_t hri_adc_result_reg_t;
+typedef uint16_t hri_adc_winlt_reg_t;
+typedef uint16_t hri_adc_winut_reg_t;
+typedef uint32_t hri_adc_inputctrl_reg_t;
+typedef uint8_t  hri_adc_avgctrl_reg_t;
+typedef uint8_t  hri_adc_ctrla_reg_t;
+typedef uint8_t  hri_adc_dbgctrl_reg_t;
+typedef uint8_t  hri_adc_evctrl_reg_t;
+typedef uint8_t  hri_adc_intenset_reg_t;
+typedef uint8_t  hri_adc_intflag_reg_t;
+typedef uint8_t  hri_adc_refctrl_reg_t;
+typedef uint8_t  hri_adc_sampctrl_reg_t;
+typedef uint8_t  hri_adc_status_reg_t;
+typedef uint8_t  hri_adc_swtrig_reg_t;
+typedef uint8_t  hri_adc_winctrl_reg_t;
+
+static inline void hri_adc_wait_for_sync(const void *const hw)
+{
+	while (((const Adc *)hw)->STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_adc_is_syncing(const void *const hw)
+{
+	return ((const Adc *)hw)->STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos;
+}
+
+static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos;
+}
+
+static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+}
+
+static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos;
+}
+
+static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+}
+
+static inline void hri_adc_set_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_SYNCRDY;
+}
+
+static inline bool hri_adc_get_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_SYNCRDY) >> ADC_INTENSET_SYNCRDY_Pos;
+}
+
+static inline void hri_adc_write_INTEN_SYNCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_SYNCRDY;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_SYNCRDY;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_SYNCRDY;
+}
+
+static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data)
+{
+	((Adc *)hw)->INTENSET.reg = data;
+	((Adc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline bool hri_adc_get_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_SYNCRDY) >> ADC_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline bool hri_adc_get_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_SYNCRDY) >> ADC_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_SYNCRDY;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	((Adc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ENABLE;
+	tmp |= value << ADC_CTRLA_ENABLE_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_RUNSTDBY;
+	tmp |= value << ADC_CTRLA_RUNSTDBY_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFCOMP;
+	tmp |= value << ADC_REFCTRL_REFCOMP_Pos;
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFSEL_Msk;
+	tmp |= ADC_REFCTRL_REFSEL(data);
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->REFCTRL.reg;
+}
+
+static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk;
+	tmp |= ADC_AVGCTRL_SAMPLENUM(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_ADJRES_Msk;
+	tmp |= ADC_AVGCTRL_ADJRES(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->AVGCTRL.reg;
+}
+
+static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk;
+	tmp |= ADC_SAMPCTRL_SAMPLEN(data);
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SAMPCTRL.reg;
+}
+
+static inline void hri_adc_set_CTRLB_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_DIFFMODE;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_DIFFMODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_DIFFMODE) >> ADC_CTRLB_DIFFMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_DIFFMODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_DIFFMODE;
+	tmp |= value << ADC_CTRLB_DIFFMODE_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_DIFFMODE;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_DIFFMODE;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_LEFTADJ;
+	tmp |= value << ADC_CTRLB_LEFTADJ_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_FREERUN;
+	tmp |= value << ADC_CTRLB_FREERUN_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_CORREN;
+	tmp |= value << ADC_CTRLB_CORREN_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_RESSEL_Msk;
+	tmp |= ADC_CTRLB_RESSEL(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_PRESCALER_Msk;
+	tmp |= ADC_CTRLB_PRESCALER(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CTRLB.reg;
+}
+
+static inline void hri_adc_set_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINCTRL.reg |= ADC_WINCTRL_WINMODE(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winctrl_reg_t hri_adc_get_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINCTRL.reg;
+	tmp = (tmp & ADC_WINCTRL_WINMODE(mask)) >> ADC_WINCTRL_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINCTRL.reg;
+	tmp &= ~ADC_WINCTRL_WINMODE_Msk;
+	tmp |= ADC_WINCTRL_WINMODE(data);
+	((Adc *)hw)->WINCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINCTRL.reg &= ~ADC_WINCTRL_WINMODE(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINCTRL.reg ^= ADC_WINCTRL_WINMODE(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winctrl_reg_t hri_adc_read_WINCTRL_WINMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINCTRL.reg;
+	tmp = (tmp & ADC_WINCTRL_WINMODE_Msk) >> ADC_WINCTRL_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winctrl_reg_t hri_adc_get_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->WINCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winctrl_reg_t hri_adc_read_WINCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->WINCTRL.reg;
+}
+
+static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_FLUSH;
+	tmp |= value << ADC_SWTRIG_FLUSH_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_START;
+	tmp |= value << ADC_SWTRIG_START_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SWTRIG.reg;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk;
+	tmp |= ADC_INPUTCTRL_MUXPOS(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk;
+	tmp |= ADC_INPUTCTRL_MUXNEG(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_INPUTSCAN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_INPUTSCAN_bf(const void *const       hw,
+                                                                         hri_adc_inputctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_INPUTSCAN(mask)) >> ADC_INPUTCTRL_INPUTSCAN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_INPUTSCAN_Msk;
+	tmp |= ADC_INPUTCTRL_INPUTSCAN(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_INPUTSCAN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_INPUTSCAN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_INPUTSCAN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_INPUTSCAN_Msk) >> ADC_INPUTCTRL_INPUTSCAN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_INPUTOFFSET(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_INPUTOFFSET_bf(const void *const       hw,
+                                                                           hri_adc_inputctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_INPUTOFFSET(mask)) >> ADC_INPUTCTRL_INPUTOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_INPUTOFFSET_Msk;
+	tmp |= ADC_INPUTCTRL_INPUTOFFSET(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_INPUTOFFSET(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_INPUTOFFSET(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_INPUTOFFSET_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_INPUTOFFSET_Msk) >> ADC_INPUTCTRL_INPUTOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_GAIN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_GAIN(mask)) >> ADC_INPUTCTRL_GAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_GAIN_Msk;
+	tmp |= ADC_INPUTCTRL_GAIN(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_GAIN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_GAIN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_GAIN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_GAIN_Msk) >> ADC_INPUTCTRL_GAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INPUTCTRL.reg;
+}
+
+static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTEI;
+	tmp |= value << ADC_EVCTRL_STARTEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_SYNCEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_SYNCEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_SYNCEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_SYNCEI) >> ADC_EVCTRL_SYNCEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_SYNCEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_SYNCEI;
+	tmp |= value << ADC_EVCTRL_SYNCEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_SYNCEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_SYNCEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_SYNCEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_SYNCEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_RESRDYEO;
+	tmp |= value << ADC_EVCTRL_RESRDYEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_WINMONEO;
+	tmp |= value << ADC_EVCTRL_WINMONEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= ~ADC_WINLT_WINLT_Msk;
+	tmp |= ADC_WINLT_WINLT(data);
+	((Adc *)hw)->WINLT.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw)
+{
+	return ((Adc *)hw)->WINLT.reg;
+}
+
+static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= ~ADC_WINUT_WINUT_Msk;
+	tmp |= ADC_WINUT_WINUT(data);
+	((Adc *)hw)->WINUT.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	hri_adc_wait_for_sync(hw);
+	((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw)
+{
+	return ((Adc *)hw)->WINUT.reg;
+}
+
+static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= ~ADC_GAINCORR_GAINCORR_Msk;
+	tmp |= ADC_GAINCORR_GAINCORR(data);
+	((Adc *)hw)->GAINCORR.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw)
+{
+	return ((Adc *)hw)->GAINCORR.reg;
+}
+
+static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const        hw,
+                                                                            hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk;
+	tmp |= ADC_OFFSETCORR_OFFSETCORR(data);
+	((Adc *)hw)->OFFSETCORR.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw)
+{
+	return ((Adc *)hw)->OFFSETCORR.reg;
+}
+
+static inline void hri_adc_set_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_LINEARITY_CAL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_LINEARITY_CAL(mask)) >> ADC_CALIB_LINEARITY_CAL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_LINEARITY_CAL_Msk;
+	tmp |= ADC_CALIB_LINEARITY_CAL(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_LINEARITY_CAL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_LINEARITY_CAL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_LINEARITY_CAL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_LINEARITY_CAL_Msk) >> ADC_CALIB_LINEARITY_CAL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIAS_CAL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIAS_CAL(mask)) >> ADC_CALIB_BIAS_CAL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIAS_CAL_Msk;
+	tmp |= ADC_CALIB_BIAS_CAL(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIAS_CAL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIAS_CAL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIAS_CAL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIAS_CAL_Msk) >> ADC_CALIB_BIAS_CAL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CALIB.reg;
+}
+
+static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= ~ADC_DBGCTRL_DBGRUN;
+	tmp |= value << ADC_DBGCTRL_DBGRUN_Pos;
+	((Adc *)hw)->DBGCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->DBGCTRL.reg;
+}
+
+static inline bool hri_adc_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_SYNCBUSY) >> ADC_STATUS_SYNCBUSY_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->STATUS.reg;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask)
+{
+	hri_adc_wait_for_sync(hw);
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw);
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESULT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESULT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ADC_D21_H_INCLUDED */
+#endif /* _SAMD21_ADC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_d21.h b/atmel-samd/asf4/samd21/hri/hri_d21.h
new file mode 100644
index 000000000..adaf36067
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_d21.h
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 HRI top-level header file
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HRI_D21_H_INCLUDED_
+#define _HRI_D21_H_INCLUDED_
+
+#include <sam.h>
+#include <hri_ac_d21.h>
+#include <hri_adc_d21.h>
+#include <hri_dac_d21.h>
+#include <hri_dmac_d21.h>
+#include <hri_dsu_d21.h>
+#include <hri_eic_d21.h>
+#include <hri_evsys_d21.h>
+#include <hri_gclk_d21.h>
+#include <hri_hmatrixb_d21.h>
+#include <hri_i2s_d21.h>
+#include <hri_mtb_d21.h>
+#include <hri_nvic_d21.h>
+#include <hri_nvmctrl_d21.h>
+#include <hri_pac_d21.h>
+#include <hri_pm_d21.h>
+#include <hri_port_d21.h>
+#include <hri_rtc_d21.h>
+#include <hri_sercom_d21.h>
+#include <hri_sysctrl_d21.h>
+#include <hri_systemcontrol_d21.h>
+#include <hri_systick_d21.h>
+#include <hri_tc_d21.h>
+#include <hri_tcc_d21.h>
+#include <hri_usb_d21.h>
+#include <hri_wdt_d21.h>
+
+#endif /* _HRI_D21_H_INCLUDED_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_dac_d21.h b/atmel-samd/asf4/samd21/hri/hri_dac_d21.h
new file mode 100644
index 000000000..f4444bf11
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_dac_d21.h
@@ -0,0 +1,1033 @@
+/**
+ * \file
+ *
+ * \brief SAM DAC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_DAC_COMPONENT_
+#ifndef _HRI_DAC_D21_H_INCLUDED_
+#define _HRI_DAC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DAC_CRITICAL_SECTIONS)
+#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DAC_CRITICAL_SECTION_ENTER()
+#define DAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dac_data_reg_t;
+typedef uint16_t hri_dac_databuf_reg_t;
+typedef uint8_t  hri_dac_ctrla_reg_t;
+typedef uint8_t  hri_dac_ctrlb_reg_t;
+typedef uint8_t  hri_dac_evctrl_reg_t;
+typedef uint8_t  hri_dac_intenset_reg_t;
+typedef uint8_t  hri_dac_intflag_reg_t;
+typedef uint8_t  hri_dac_status_reg_t;
+
+static inline void hri_dac_wait_for_sync(const void *const hw)
+{
+	while (((const Dac *)hw)->STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_dac_is_syncing(const void *const hw)
+{
+	return ((const Dac *)hw)->STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_dac_set_INTEN_UNDERRUN_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN;
+}
+
+static inline bool hri_dac_get_INTEN_UNDERRUN_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN) >> DAC_INTENSET_UNDERRUN_Pos;
+}
+
+static inline void hri_dac_write_INTEN_UNDERRUN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_UNDERRUN_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN;
+}
+
+static inline void hri_dac_set_INTEN_EMPTY_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY;
+}
+
+static inline bool hri_dac_get_INTEN_EMPTY_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY) >> DAC_INTENSET_EMPTY_Pos;
+}
+
+static inline void hri_dac_write_INTEN_EMPTY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_EMPTY_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY;
+}
+
+static inline void hri_dac_set_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_SYNCRDY;
+}
+
+static inline bool hri_dac_get_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_SYNCRDY) >> DAC_INTENSET_SYNCRDY_Pos;
+}
+
+static inline void hri_dac_write_INTEN_SYNCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_SYNCRDY;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_SYNCRDY;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_SYNCRDY;
+}
+
+static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	((Dac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw)
+{
+	return ((Dac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data)
+{
+	((Dac *)hw)->INTENSET.reg = data;
+	((Dac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	((Dac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_dac_get_INTFLAG_UNDERRUN_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_UNDERRUN_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN;
+}
+
+static inline bool hri_dac_get_INTFLAG_EMPTY_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_EMPTY_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY;
+}
+
+static inline bool hri_dac_get_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_SYNCRDY) >> DAC_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_dac_get_interrupt_UNDERRUN_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_UNDERRUN_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN;
+}
+
+static inline bool hri_dac_get_interrupt_EMPTY_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_EMPTY_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY;
+}
+
+static inline bool hri_dac_get_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_SYNCRDY) >> DAC_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_SYNCRDY;
+}
+
+static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Dac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask)
+{
+	((Dac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= ~DAC_CTRLA_ENABLE;
+	tmp |= value << DAC_CTRLA_ENABLE_Pos;
+	((Dac *)hw)->CTRLA.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_RUNSTDBY;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_RUNSTDBY) >> DAC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= ~DAC_CTRLA_RUNSTDBY;
+	tmp |= value << DAC_CTRLA_RUNSTDBY_Pos;
+	((Dac *)hw)->CTRLA.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_RUNSTDBY;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_RUNSTDBY;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw)
+{
+	return ((Dac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_dac_set_CTRLB_EOEN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_EOEN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLB_EOEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_EOEN) >> DAC_CTRLB_EOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLB_EOEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_EOEN;
+	tmp |= value << DAC_CTRLB_EOEN_Pos;
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_EOEN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_EOEN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_EOEN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_EOEN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLB_IOEN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_IOEN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLB_IOEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_IOEN) >> DAC_CTRLB_IOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLB_IOEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_IOEN;
+	tmp |= value << DAC_CTRLB_IOEN_Pos;
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_IOEN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_IOEN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_IOEN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_IOEN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_LEFTADJ;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_LEFTADJ) >> DAC_CTRLB_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_LEFTADJ;
+	tmp |= value << DAC_CTRLB_LEFTADJ_Pos;
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_LEFTADJ;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_LEFTADJ;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLB_VPD_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_VPD;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLB_VPD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_VPD) >> DAC_CTRLB_VPD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLB_VPD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_VPD;
+	tmp |= value << DAC_CTRLB_VPD_Pos;
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_VPD_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_VPD;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_VPD_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_VPD;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLB_BDWP_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_BDWP;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLB_BDWP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_BDWP) >> DAC_CTRLB_BDWP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLB_BDWP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_BDWP;
+	tmp |= value << DAC_CTRLB_BDWP_Pos;
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_BDWP_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_BDWP;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_BDWP_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_BDWP;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_REFSEL_Msk;
+	tmp |= DAC_CTRLB_REFSEL(data);
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw)
+{
+	return ((Dac *)hw)->CTRLB.reg;
+}
+
+static inline void hri_dac_set_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_STARTEI) >> DAC_EVCTRL_STARTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_STARTEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_STARTEI;
+	tmp |= value << DAC_EVCTRL_STARTEI_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_EMPTYEO_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_EMPTYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_EMPTYEO) >> DAC_EVCTRL_EMPTYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_EMPTYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_EMPTYEO;
+	tmp |= value << DAC_EVCTRL_EMPTYEO_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_EMPTYEO_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_EMPTYEO_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Dac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_dac_set_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->DATA.reg |= DAC_DATA_DATA(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_data_reg_t hri_dac_get_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->DATA.reg;
+	tmp = (tmp & DAC_DATA_DATA(mask)) >> DAC_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->DATA.reg;
+	tmp &= ~DAC_DATA_DATA_Msk;
+	tmp |= DAC_DATA_DATA(data);
+	((Dac *)hw)->DATA.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->DATA.reg &= ~DAC_DATA_DATA(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->DATA.reg ^= DAC_DATA_DATA(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_data_reg_t hri_dac_read_DATA_DATA_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->DATA.reg;
+	tmp = (tmp & DAC_DATA_DATA_Msk) >> DAC_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DATA_reg(const void *const hw, hri_dac_data_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATA.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_data_reg_t hri_dac_get_DATA_reg(const void *const hw, hri_dac_data_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_DATA_reg(const void *const hw, hri_dac_data_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATA.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DATA_reg(const void *const hw, hri_dac_data_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATA.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DATA_reg(const void *const hw, hri_dac_data_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATA.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_data_reg_t hri_dac_read_DATA_reg(const void *const hw)
+{
+	return ((Dac *)hw)->DATA.reg;
+}
+
+static inline void hri_dac_set_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->DATABUF.reg |= DAC_DATABUF_DATABUF(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_databuf_reg_t hri_dac_get_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->DATABUF.reg;
+	tmp = (tmp & DAC_DATABUF_DATABUF(mask)) >> DAC_DATABUF_DATABUF_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->DATABUF.reg;
+	tmp &= ~DAC_DATABUF_DATABUF_Msk;
+	tmp |= DAC_DATABUF_DATABUF(data);
+	((Dac *)hw)->DATABUF.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->DATABUF.reg &= ~DAC_DATABUF_DATABUF(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	hri_dac_wait_for_sync(hw);
+	((Dac *)hw)->DATABUF.reg ^= DAC_DATABUF_DATABUF(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_databuf_reg_t hri_dac_read_DATABUF_DATABUF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw);
+	tmp = ((Dac *)hw)->DATABUF.reg;
+	tmp = (tmp & DAC_DATABUF_DATABUF_Msk) >> DAC_DATABUF_DATABUF_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATABUF.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_databuf_reg_t hri_dac_get_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DATABUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATABUF.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATABUF.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATABUF.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_databuf_reg_t hri_dac_read_DATABUF_reg(const void *const hw)
+{
+	return ((Dac *)hw)->DATABUF.reg;
+}
+
+static inline bool hri_dac_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	hri_dac_wait_for_sync(hw);
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_SYNCBUSY) >> DAC_STATUS_SYNCBUSY_Pos;
+}
+
+static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw)
+{
+	return ((Dac *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DAC_D21_H_INCLUDED */
+#endif /* _SAMD21_DAC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h b/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h
new file mode 100644
index 000000000..229091701
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h
@@ -0,0 +1,4308 @@
+/**
+ * \file
+ *
+ * \brief SAM DMAC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_DMAC_COMPONENT_
+#ifndef _HRI_DMAC_D21_H_INCLUDED_
+#define _HRI_DMAC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DMAC_CRITICAL_SECTIONS)
+#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DMAC_CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dmac_crcctrl_reg_t;
+typedef uint16_t hri_dmac_ctrl_reg_t;
+typedef uint16_t hri_dmac_intpend_reg_t;
+typedef uint16_t hri_dmacdescriptor_btcnt_reg_t;
+typedef uint16_t hri_dmacdescriptor_btctrl_reg_t;
+typedef uint32_t hri_dmac_active_reg_t;
+typedef uint32_t hri_dmac_baseaddr_reg_t;
+typedef uint32_t hri_dmac_busych_reg_t;
+typedef uint32_t hri_dmac_chctrlb_reg_t;
+typedef uint32_t hri_dmac_crcchksum_reg_t;
+typedef uint32_t hri_dmac_crcdatain_reg_t;
+typedef uint32_t hri_dmac_intstatus_reg_t;
+typedef uint32_t hri_dmac_pendch_reg_t;
+typedef uint32_t hri_dmac_prictrl0_reg_t;
+typedef uint32_t hri_dmac_swtrigctrl_reg_t;
+typedef uint32_t hri_dmac_wrbaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_descaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t;
+typedef uint8_t  hri_dmac_chctrla_reg_t;
+typedef uint8_t  hri_dmac_chid_reg_t;
+typedef uint8_t  hri_dmac_chintenset_reg_t;
+typedef uint8_t  hri_dmac_chintflag_reg_t;
+typedef uint8_t  hri_dmac_chstatus_reg_t;
+typedef uint8_t  hri_dmac_crcstatus_reg_t;
+typedef uint8_t  hri_dmac_dbgctrl_reg_t;
+typedef uint8_t  hri_dmac_qosctrl_reg_t;
+
+static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data)
+{
+	((Dmac *)hw)->CHINTENSET.reg = data;
+	((Dmac *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_DMAENABLE;
+	tmp |= value << DMAC_CTRL_DMAENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_CRCENABLE;
+	tmp |= value << DMAC_CTRL_CRCENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN0;
+	tmp |= value << DMAC_CTRL_LVLEN0_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN1;
+	tmp |= value << DMAC_CTRL_LVLEN1_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN2;
+	tmp |= value << DMAC_CTRL_LVLEN2_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN3;
+	tmp |= value << DMAC_CTRL_LVLEN3_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const      hw,
+                                                                         hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk;
+	tmp |= DMAC_CRCCTRL_CRCPOLY(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk;
+	tmp |= DMAC_CRCCTRL_CRCSRC(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const        hw,
+                                                                           hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk;
+	tmp |= DMAC_CRCDATAIN_CRCDATAIN(data);
+	((Dmac *)hw)->CRCDATAIN.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCDATAIN.reg;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const        hw,
+                                                                           hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk;
+	tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data);
+	((Dmac *)hw)->CRCCHKSUM.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCHKSUM.reg;
+}
+
+static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= ~DMAC_DBGCTRL_DBGRUN;
+	tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos;
+	((Dmac *)hw)->DBGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk;
+	tmp |= DMAC_QOSCTRL_WRBQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_FQOS_Msk;
+	tmp |= DMAC_QOSCTRL_FQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_DQOS_Msk;
+	tmp |= DMAC_QOSCTRL_DQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->QOSCTRL.reg;
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const         hw,
+                                                                    hri_dmac_swtrigctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->SWTRIGCTRL.reg;
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN0;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN1;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN2;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN3;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PRICTRL0.reg;
+}
+
+static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TERR;
+	tmp |= value << DMAC_INTPEND_TERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TCMPL;
+	tmp |= value << DMAC_INTPEND_TCMPL_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_SUSP;
+	tmp |= value << DMAC_INTPEND_SUSP_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_FERR;
+	tmp |= value << DMAC_INTPEND_FERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_BUSY;
+	tmp |= value << DMAC_INTPEND_BUSY_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_PEND;
+	tmp |= value << DMAC_INTPEND_PEND_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_ID_Msk;
+	tmp |= DMAC_INTPEND_ID(data);
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTPEND.reg;
+}
+
+static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const       hw,
+                                                                        hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= ~DMAC_BASEADDR_BASEADDR_Msk;
+	tmp |= DMAC_BASEADDR_BASEADDR(data);
+	((Dmac *)hw)->BASEADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BASEADDR.reg;
+}
+
+static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= ~DMAC_WRBADDR_WRBADDR_Msk;
+	tmp |= DMAC_WRBADDR_WRBADDR(data);
+	((Dmac *)hw)->WRBADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->WRBADDR.reg;
+}
+
+static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp &= ~DMAC_CHID_ID_Msk;
+	tmp |= DMAC_CHID_ID(data);
+	((Dmac *)hw)->CHID.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHID.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((Dmac *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHCTRLA.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVIE;
+	tmp |= value << DMAC_CHCTRLB_EVIE_Pos;
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVOE;
+	tmp |= value << DMAC_CHCTRLB_EVOE_Pos;
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVACT_Msk;
+	tmp |= DMAC_CHCTRLB_EVACT(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_LVL_Msk;
+	tmp |= DMAC_CHCTRLB_LVL(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLB_TRIGSRC(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLB_TRIGACT(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHCTRLB.reg;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PENDCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PENDCH.reg;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->ACTIVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->ACTIVE.reg;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CRCSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCSTATUS.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_VALID;
+	tmp |= value << DMAC_BTCTRL_VALID_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_SRCINC;
+	tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_DSTINC;
+	tmp |= value << DMAC_BTCTRL_DSTINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSEL;
+	tmp |= value << DMAC_BTCTRL_STEPSEL_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_EVOSEL_Msk;
+	tmp |= DMAC_BTCTRL_EVOSEL(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const               hw,
+                                                              hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk;
+	tmp |= DMAC_BTCTRL_BLOCKACT(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk;
+	tmp |= DMAC_BTCTRL_BEATSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk;
+	tmp |= DMAC_BTCTRL_STEPSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const               hw,
+                                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCTRL.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const              hw,
+                                                                                   hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= ~DMAC_BTCNT_BTCNT_Msk;
+	tmp |= DMAC_BTCNT_BTCNT(data);
+	((DmacDescriptor *)hw)->BTCNT.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const              hw,
+                                                                              hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCNT.reg;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t
+hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= ~DMAC_SRCADDR_SRCADDR_Msk;
+	tmp |= DMAC_SRCADDR_SRCADDR(data);
+	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->SRCADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_DSTADDR_Msk;
+	tmp |= DMAC_DSTADDR_DSTADDR(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DSTADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                               hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= ~DMAC_DESCADDR_DESCADDR_Msk;
+	tmp |= DMAC_DESCADDR_DESCADDR(data);
+	((DmacDescriptor *)hw)->DESCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                  hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DESCADDR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DMAC_D21_H_INCLUDED */
+#endif /* _SAMD21_DMAC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h b/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h
new file mode 100644
index 000000000..cd001e0a7
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h
@@ -0,0 +1,979 @@
+/**
+ * \file
+ *
+ * \brief SAM DSU
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_DSU_COMPONENT_
+#ifndef _HRI_DSU_D21_H_INCLUDED_
+#define _HRI_DSU_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DSU_CRITICAL_SECTIONS)
+#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DSU_CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_dsu_addr_reg_t;
+typedef uint32_t hri_dsu_cid0_reg_t;
+typedef uint32_t hri_dsu_cid1_reg_t;
+typedef uint32_t hri_dsu_cid2_reg_t;
+typedef uint32_t hri_dsu_cid3_reg_t;
+typedef uint32_t hri_dsu_data_reg_t;
+typedef uint32_t hri_dsu_dcc_reg_t;
+typedef uint32_t hri_dsu_did_reg_t;
+typedef uint32_t hri_dsu_end_reg_t;
+typedef uint32_t hri_dsu_entry_reg_t;
+typedef uint32_t hri_dsu_length_reg_t;
+typedef uint32_t hri_dsu_memtype_reg_t;
+typedef uint32_t hri_dsu_pid0_reg_t;
+typedef uint32_t hri_dsu_pid1_reg_t;
+typedef uint32_t hri_dsu_pid2_reg_t;
+typedef uint32_t hri_dsu_pid3_reg_t;
+typedef uint32_t hri_dsu_pid4_reg_t;
+typedef uint8_t  hri_dsu_ctrl_reg_t;
+typedef uint8_t  hri_dsu_statusa_reg_t;
+typedef uint8_t  hri_dsu_statusb_reg_t;
+
+static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CTRL.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_ADDR_Msk;
+	tmp |= DSU_ADDR_ADDR(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ADDR.reg;
+}
+
+static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= ~DSU_LENGTH_LENGTH_Msk;
+	tmp |= DSU_LENGTH_LENGTH(data);
+	((Dsu *)hw)->LENGTH.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->LENGTH.reg;
+}
+
+static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= ~DSU_DATA_DATA_Msk;
+	tmp |= DSU_DATA_DATA(data);
+	((Dsu *)hw)->DATA.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DATA.reg;
+}
+
+static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= ~DSU_DCC_DATA_Msk;
+	tmp |= DSU_DCC_DATA(data);
+	((Dsu *)hw)->DCC[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCC[index].reg;
+}
+
+static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSB.reg;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DID.reg;
+}
+
+static inline bool hri_dsu_get_ENTRY_EPRES_bit(const void *const hw, uint8_t index)
+{
+	return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_EPRES) >> DSU_ENTRY_EPRES_Pos;
+}
+
+static inline bool hri_dsu_get_ENTRY_FMT_bit(const void *const hw, uint8_t index)
+{
+	return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_FMT) >> DSU_ENTRY_FMT_Pos;
+}
+
+static inline hri_dsu_entry_reg_t hri_dsu_get_ENTRY_ADDOFF_bf(const void *const hw, uint8_t index,
+                                                              hri_dsu_entry_reg_t mask)
+{
+	return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_ADDOFF(mask)) >> DSU_ENTRY_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry_reg_t hri_dsu_read_ENTRY_ADDOFF_bf(const void *const hw, uint8_t index)
+{
+	return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_ADDOFF_Msk) >> DSU_ENTRY_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry_reg_t hri_dsu_get_ENTRY_reg(const void *const hw, uint8_t index, hri_dsu_entry_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry_reg_t hri_dsu_read_ENTRY_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->ENTRY[index].reg;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->END.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->END.reg;
+}
+
+static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->MEMTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->MEMTYPE.reg;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID4.reg;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID0.reg;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID1.reg;
+}
+
+static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID2.reg;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID3.reg;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID0.reg;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID1.reg;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID2.reg;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID3.reg;
+}
+
+static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSA.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DSU_D21_H_INCLUDED */
+#endif /* _SAMD21_DSU_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_eic_d21.h b/atmel-samd/asf4/samd21/hri/hri_eic_d21.h
new file mode 100644
index 000000000..89919db6e
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_eic_d21.h
@@ -0,0 +1,3233 @@
+/**
+ * \file
+ *
+ * \brief SAM EIC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_EIC_COMPONENT_
+#ifndef _HRI_EIC_D21_H_INCLUDED_
+#define _HRI_EIC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EIC_CRITICAL_SECTIONS)
+#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EIC_CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_eic_config_reg_t;
+typedef uint32_t hri_eic_evctrl_reg_t;
+typedef uint32_t hri_eic_intenset_reg_t;
+typedef uint32_t hri_eic_intflag_reg_t;
+typedef uint32_t hri_eic_wakeup_reg_t;
+typedef uint8_t  hri_eic_ctrl_reg_t;
+typedef uint8_t  hri_eic_nmictrl_reg_t;
+typedef uint8_t  hri_eic_nmiflag_reg_t;
+typedef uint8_t  hri_eic_status_reg_t;
+
+static inline void hri_eic_wait_for_sync(const void *const hw)
+{
+	while (((const Eic *)hw)->STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_eic_is_syncing(const void *const hw)
+{
+	return ((const Eic *)hw)->STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT0_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT0;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT0_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT0) >> EIC_INTENSET_EXTINT0_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT0;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT0;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT0_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT0;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT1_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT1;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT1_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT1) >> EIC_INTENSET_EXTINT1_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT1;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT1;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT1_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT1;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT2_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT2;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT2_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT2) >> EIC_INTENSET_EXTINT2_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT2;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT2;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT2_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT2;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT3_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT3;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT3_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT3) >> EIC_INTENSET_EXTINT3_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT3;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT3;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT3_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT3;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT4_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT4;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT4_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT4) >> EIC_INTENSET_EXTINT4_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT4;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT4;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT4_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT4;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT5_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT5;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT5_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT5) >> EIC_INTENSET_EXTINT5_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT5;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT5;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT5_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT5;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT6_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT6;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT6_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT6) >> EIC_INTENSET_EXTINT6_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT6;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT6;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT6_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT6;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT7_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT7;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT7_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT7) >> EIC_INTENSET_EXTINT7_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT7;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT7;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT7_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT7;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT8_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT8;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT8_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT8) >> EIC_INTENSET_EXTINT8_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT8_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT8;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT8;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT8_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT8;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT9_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT9;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT9_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT9) >> EIC_INTENSET_EXTINT9_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT9_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT9;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT9;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT9_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT9;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT10_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT10;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT10_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT10) >> EIC_INTENSET_EXTINT10_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT10_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT10;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT10;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT10_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT10;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT11_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT11;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT11_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT11) >> EIC_INTENSET_EXTINT11_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT11_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT11;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT11;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT11_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT11;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT12_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT12;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT12_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT12) >> EIC_INTENSET_EXTINT12_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT12_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT12;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT12;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT12_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT12;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT13_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT13;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT13_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT13) >> EIC_INTENSET_EXTINT13_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT13_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT13;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT13;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT13_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT13;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT14_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT14;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT14_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT14) >> EIC_INTENSET_EXTINT14_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT14_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT14;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT14;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT14_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT14;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT15_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT15;
+}
+
+static inline bool hri_eic_get_INTEN_EXTINT15_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT15) >> EIC_INTENSET_EXTINT15_Pos;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT15_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT15;
+	} else {
+		((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT15;
+	}
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT15_bit(const void *const hw)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT15;
+}
+
+static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTENSET.reg;
+}
+
+static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = data;
+	((Eic *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw)
+{
+	return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos;
+}
+
+static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw)
+{
+	((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMIFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMIFLAG.reg;
+}
+
+static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	((Eic *)hw)->NMIFLAG.reg = mask;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT0_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT0) >> EIC_INTFLAG_EXTINT0_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT0_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT0;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT1_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT1) >> EIC_INTFLAG_EXTINT1_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT1_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT1;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT2_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT2) >> EIC_INTFLAG_EXTINT2_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT2_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT2;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT3_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT3) >> EIC_INTFLAG_EXTINT3_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT3_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT3;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT4_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT4) >> EIC_INTFLAG_EXTINT4_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT4_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT4;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT5_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT5) >> EIC_INTFLAG_EXTINT5_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT5_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT5;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT6_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT6) >> EIC_INTFLAG_EXTINT6_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT6_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT6;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT7_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT7) >> EIC_INTFLAG_EXTINT7_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT7_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT7;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT8_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT8) >> EIC_INTFLAG_EXTINT8_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT8_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT8;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT9_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT9) >> EIC_INTFLAG_EXTINT9_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT9_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT9;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT10_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT10) >> EIC_INTFLAG_EXTINT10_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT10_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT10;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT11_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT11) >> EIC_INTFLAG_EXTINT11_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT11_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT11;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT12_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT12) >> EIC_INTFLAG_EXTINT12_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT12_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT12;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT13_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT13) >> EIC_INTFLAG_EXTINT13_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT13_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT13;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT14_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT14) >> EIC_INTFLAG_EXTINT14_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT14_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT14;
+}
+
+static inline bool hri_eic_get_INTFLAG_EXTINT15_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT15) >> EIC_INTFLAG_EXTINT15_Pos;
+}
+
+static inline void hri_eic_clear_INTFLAG_EXTINT15_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT15;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT0_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT0) >> EIC_INTFLAG_EXTINT0_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT0_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT0;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT1_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT1) >> EIC_INTFLAG_EXTINT1_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT1_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT1;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT2_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT2) >> EIC_INTFLAG_EXTINT2_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT2_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT2;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT3_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT3) >> EIC_INTFLAG_EXTINT3_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT3_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT3;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT4_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT4) >> EIC_INTFLAG_EXTINT4_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT4_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT4;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT5_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT5) >> EIC_INTFLAG_EXTINT5_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT5_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT5;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT6_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT6) >> EIC_INTFLAG_EXTINT6_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT6_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT6;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT7_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT7) >> EIC_INTFLAG_EXTINT7_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT7_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT7;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT8_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT8) >> EIC_INTFLAG_EXTINT8_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT8_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT8;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT9_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT9) >> EIC_INTFLAG_EXTINT9_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT9_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT9;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT10_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT10) >> EIC_INTFLAG_EXTINT10_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT10_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT10;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT11_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT11) >> EIC_INTFLAG_EXTINT11_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT11_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT11;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT12_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT12) >> EIC_INTFLAG_EXTINT12_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT12_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT12;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT13_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT13) >> EIC_INTFLAG_EXTINT13_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT13_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT13;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT14_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT14) >> EIC_INTFLAG_EXTINT14_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT14_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT14;
+}
+
+static inline bool hri_eic_get_interrupt_EXTINT15_bit(const void *const hw)
+{
+	return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT15) >> EIC_INTFLAG_EXTINT15_Pos;
+}
+
+static inline void hri_eic_clear_interrupt_EXTINT15_bit(const void *const hw)
+{
+	((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT15;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	((Eic *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_eic_set_CTRL_SWRST_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	hri_eic_wait_for_sync(hw);
+	((Eic *)hw)->CTRL.reg |= EIC_CTRL_SWRST;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw);
+	tmp = ((Eic *)hw)->CTRL.reg;
+	tmp = (tmp & EIC_CTRL_SWRST) >> EIC_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	hri_eic_wait_for_sync(hw);
+	((Eic *)hw)->CTRL.reg |= EIC_CTRL_ENABLE;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw);
+	tmp = ((Eic *)hw)->CTRL.reg;
+	tmp = (tmp & EIC_CTRL_ENABLE) >> EIC_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	hri_eic_wait_for_sync(hw);
+	tmp = ((Eic *)hw)->CTRL.reg;
+	tmp &= ~EIC_CTRL_ENABLE;
+	tmp |= value << EIC_CTRL_ENABLE_Pos;
+	((Eic *)hw)->CTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	hri_eic_wait_for_sync(hw);
+	((Eic *)hw)->CTRL.reg &= ~EIC_CTRL_ENABLE;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	hri_eic_wait_for_sync(hw);
+	((Eic *)hw)->CTRL.reg ^= EIC_CTRL_ENABLE;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrl_reg_t hri_eic_get_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrl_reg_t hri_eic_read_CTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->CTRL.reg;
+}
+
+static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIFILTEN;
+	tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMISENSE_Msk;
+	tmp |= EIC_NMICTRL_NMISENSE(data);
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMICTRL.reg;
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO0) >> EIC_EVCTRL_EXTINTEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO0;
+	tmp |= value << EIC_EVCTRL_EXTINTEO0_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO1) >> EIC_EVCTRL_EXTINTEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO1;
+	tmp |= value << EIC_EVCTRL_EXTINTEO1_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO2_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO2) >> EIC_EVCTRL_EXTINTEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO2;
+	tmp |= value << EIC_EVCTRL_EXTINTEO2_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO2_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO2_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO3_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO3) >> EIC_EVCTRL_EXTINTEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO3;
+	tmp |= value << EIC_EVCTRL_EXTINTEO3_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO3_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO3_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO4_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO4) >> EIC_EVCTRL_EXTINTEO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO4;
+	tmp |= value << EIC_EVCTRL_EXTINTEO4_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO4_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO4_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO5_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO5) >> EIC_EVCTRL_EXTINTEO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO5;
+	tmp |= value << EIC_EVCTRL_EXTINTEO5_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO5_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO5_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO6_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO6) >> EIC_EVCTRL_EXTINTEO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO6;
+	tmp |= value << EIC_EVCTRL_EXTINTEO6_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO6_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO6_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO7_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO7) >> EIC_EVCTRL_EXTINTEO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO7;
+	tmp |= value << EIC_EVCTRL_EXTINTEO7_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO7_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO7_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO8_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO8;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO8) >> EIC_EVCTRL_EXTINTEO8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO8;
+	tmp |= value << EIC_EVCTRL_EXTINTEO8_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO8_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO8;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO8_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO8;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO9_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO9;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO9) >> EIC_EVCTRL_EXTINTEO9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO9;
+	tmp |= value << EIC_EVCTRL_EXTINTEO9_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO9_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO9;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO9_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO9;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO10_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO10;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO10) >> EIC_EVCTRL_EXTINTEO10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO10;
+	tmp |= value << EIC_EVCTRL_EXTINTEO10_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO10_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO10;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO10_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO10;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO11_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO11;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO11) >> EIC_EVCTRL_EXTINTEO11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO11;
+	tmp |= value << EIC_EVCTRL_EXTINTEO11_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO11_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO11;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO11_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO11;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO12_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO12;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO12) >> EIC_EVCTRL_EXTINTEO12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO12;
+	tmp |= value << EIC_EVCTRL_EXTINTEO12_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO12_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO12;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO12_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO12;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO13_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO13;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO13) >> EIC_EVCTRL_EXTINTEO13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO13;
+	tmp |= value << EIC_EVCTRL_EXTINTEO13_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO13_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO13;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO13_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO13;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO14_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO14;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO14) >> EIC_EVCTRL_EXTINTEO14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO14;
+	tmp |= value << EIC_EVCTRL_EXTINTEO14_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO14_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO14;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO14_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO14;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO15_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO15;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_EVCTRL_EXTINTEO15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO15) >> EIC_EVCTRL_EXTINTEO15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO15;
+	tmp |= value << EIC_EVCTRL_EXTINTEO15_Pos;
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO15_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO15;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO15_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO15;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN0) >> EIC_WAKEUP_WAKEUPEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN0;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN0_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN1) >> EIC_WAKEUP_WAKEUPEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN1;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN1_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN2_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN2) >> EIC_WAKEUP_WAKEUPEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN2;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN2_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN2_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN2_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN3_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN3) >> EIC_WAKEUP_WAKEUPEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN3;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN3_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN3_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN3_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN4_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN4) >> EIC_WAKEUP_WAKEUPEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN4;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN4_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN4_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN4_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN5_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN5) >> EIC_WAKEUP_WAKEUPEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN5;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN5_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN5_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN5_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN6_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN6) >> EIC_WAKEUP_WAKEUPEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN6;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN6_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN6_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN6_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN7_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN7) >> EIC_WAKEUP_WAKEUPEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN7;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN7_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN7_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN7_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN8_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN8;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN8) >> EIC_WAKEUP_WAKEUPEN8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN8;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN8_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN8_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN8;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN8_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN8;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN9_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN9;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN9) >> EIC_WAKEUP_WAKEUPEN9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN9;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN9_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN9_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN9;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN9_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN9;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN10_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN10;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN10) >> EIC_WAKEUP_WAKEUPEN10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN10;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN10_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN10_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN10;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN10_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN10;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN11_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN11;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN11) >> EIC_WAKEUP_WAKEUPEN11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN11;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN11_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN11_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN11;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN11_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN11;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN12_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN12;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN12) >> EIC_WAKEUP_WAKEUPEN12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN12;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN12_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN12_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN12;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN12_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN12;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN13_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN13;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN13) >> EIC_WAKEUP_WAKEUPEN13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN13;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN13_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN13_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN13;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN13_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN13;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN14_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN14;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN14) >> EIC_WAKEUP_WAKEUPEN14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN14;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN14_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN14_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN14;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN14_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN14;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_WAKEUPEN15_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN15;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_WAKEUP_WAKEUPEN15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp = (tmp & EIC_WAKEUP_WAKEUPEN15) >> EIC_WAKEUP_WAKEUPEN15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_WAKEUPEN15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= ~EIC_WAKEUP_WAKEUPEN15;
+	tmp |= value << EIC_WAKEUP_WAKEUPEN15_Pos;
+	((Eic *)hw)->WAKEUP.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_WAKEUPEN15_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN15;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_WAKEUPEN15_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN15;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_wakeup_reg_t hri_eic_get_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->WAKEUP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->WAKEUP.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_wakeup_reg_t hri_eic_read_WAKEUP_reg(const void *const hw)
+{
+	return ((Eic *)hw)->WAKEUP.reg;
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN0;
+	tmp |= value << EIC_CONFIG_FILTEN0_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN1;
+	tmp |= value << EIC_CONFIG_FILTEN1_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN2;
+	tmp |= value << EIC_CONFIG_FILTEN2_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN3;
+	tmp |= value << EIC_CONFIG_FILTEN3_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN4;
+	tmp |= value << EIC_CONFIG_FILTEN4_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN5;
+	tmp |= value << EIC_CONFIG_FILTEN5_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN6;
+	tmp |= value << EIC_CONFIG_FILTEN6_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN7;
+	tmp |= value << EIC_CONFIG_FILTEN7_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE0_Msk;
+	tmp |= EIC_CONFIG_SENSE0(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE1_Msk;
+	tmp |= EIC_CONFIG_SENSE1(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE2_Msk;
+	tmp |= EIC_CONFIG_SENSE2(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE3_Msk;
+	tmp |= EIC_CONFIG_SENSE3(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE4_Msk;
+	tmp |= EIC_CONFIG_SENSE4(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE5_Msk;
+	tmp |= EIC_CONFIG_SENSE5(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE6_Msk;
+	tmp |= EIC_CONFIG_SENSE6(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE7_Msk;
+	tmp |= EIC_CONFIG_SENSE7(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index,
+                                                          hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index)
+{
+	return ((Eic *)hw)->CONFIG[index].reg;
+}
+
+static inline bool hri_eic_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Eic *)hw)->STATUS.reg & EIC_STATUS_SYNCBUSY) >> EIC_STATUS_SYNCBUSY_Pos;
+}
+
+static inline hri_eic_status_reg_t hri_eic_get_STATUS_reg(const void *const hw, hri_eic_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_status_reg_t hri_eic_read_STATUS_reg(const void *const hw)
+{
+	return ((Eic *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EIC_D21_H_INCLUDED */
+#endif /* _SAMD21_EIC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h b/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h
new file mode 100644
index 000000000..a624728b7
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h
@@ -0,0 +1,1729 @@
+/**
+ * \file
+ *
+ * \brief SAM EVSYS
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_EVSYS_COMPONENT_
+#ifndef _HRI_EVSYS_D21_H_INCLUDED_
+#define _HRI_EVSYS_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS)
+#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EVSYS_CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_evsys_user_reg_t;
+typedef uint32_t hri_evsys_channel_reg_t;
+typedef uint32_t hri_evsys_chstatus_reg_t;
+typedef uint32_t hri_evsys_intenset_reg_t;
+typedef uint32_t hri_evsys_intflag_reg_t;
+typedef uint8_t  hri_evsys_ctrl_reg_t;
+
+static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0;
+}
+
+static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1;
+}
+
+static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2;
+}
+
+static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3;
+}
+
+static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4;
+}
+
+static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5;
+}
+
+static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6;
+}
+
+static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7;
+}
+
+static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0;
+}
+
+static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1;
+}
+
+static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2;
+}
+
+static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3;
+}
+
+static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4;
+}
+
+static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5;
+}
+
+static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6;
+}
+
+static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7;
+}
+
+static inline void hri_evsys_set_INTEN_OVR8_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR8) >> EVSYS_INTENSET_OVR8_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR8_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR8_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8;
+}
+
+static inline void hri_evsys_set_INTEN_OVR9_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR9) >> EVSYS_INTENSET_OVR9_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR9_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR9_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9;
+}
+
+static inline void hri_evsys_set_INTEN_OVR10_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR10) >> EVSYS_INTENSET_OVR10_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR10_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR10_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10;
+}
+
+static inline void hri_evsys_set_INTEN_OVR11_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR11) >> EVSYS_INTENSET_OVR11_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR11_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR11_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11;
+}
+
+static inline void hri_evsys_set_INTEN_EVD8_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD8) >> EVSYS_INTENSET_EVD8_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD8_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD8_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8;
+}
+
+static inline void hri_evsys_set_INTEN_EVD9_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD9) >> EVSYS_INTENSET_EVD9_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD9_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD9_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9;
+}
+
+static inline void hri_evsys_set_INTEN_EVD10_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD10) >> EVSYS_INTENSET_EVD10_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD10_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD10_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10;
+}
+
+static inline void hri_evsys_set_INTEN_EVD11_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD11) >> EVSYS_INTENSET_EVD11_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD11_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD11_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11;
+}
+
+static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	((Evsys *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTENSET.reg;
+}
+
+static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data)
+{
+	((Evsys *)hw)->INTENSET.reg = data;
+	((Evsys *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	((Evsys *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR8_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR9_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR10_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR11_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD8_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD9_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD10_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD11_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR8_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR9_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR10_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR11_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD8_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD9_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD10_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD11_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11;
+}
+
+static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask)
+{
+	((Evsys *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_evsys_write_CTRL_reg(const void *const hw, hri_evsys_ctrl_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_SWEVT_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_SWEVT;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_SWEVT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_SWEVT) >> EVSYS_CHANNEL_SWEVT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_SWEVT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_SWEVT;
+	tmp |= value << EVSYS_CHANNEL_SWEVT_Pos;
+	((Evsys *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_SWEVT_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_SWEVT;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_SWEVT_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_SWEVT;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_CHANNEL_bf(const void *const       hw,
+                                                                       hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_CHANNEL(mask)) >> EVSYS_CHANNEL_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_CHANNEL_Msk;
+	tmp |= EVSYS_CHANNEL_CHANNEL(data);
+	((Evsys *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_CHANNEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_CHANNEL_Msk) >> EVSYS_CHANNEL_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((Evsys *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((Evsys *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const       hw,
+                                                                      hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((Evsys *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CHANNEL.reg;
+}
+
+static inline void hri_evsys_set_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg |= EVSYS_USER_USER(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->USER.reg;
+	tmp = (tmp & EVSYS_USER_USER(mask)) >> EVSYS_USER_USER_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t data)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->USER.reg;
+	tmp &= ~EVSYS_USER_USER_Msk;
+	tmp |= EVSYS_USER_USER(data);
+	((Evsys *)hw)->USER.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg &= ~EVSYS_USER_USER(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg ^= EVSYS_USER_USER(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_USER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->USER.reg;
+	tmp = (tmp & EVSYS_USER_USER_Msk) >> EVSYS_USER_USER_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg |= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->USER.reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t data)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->USER.reg;
+	tmp &= ~EVSYS_USER_CHANNEL_Msk;
+	tmp |= EVSYS_USER_CHANNEL(data);
+	((Evsys *)hw)->USER.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg &= ~EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg ^= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->USER.reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_USER_reg(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->USER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_reg(const void *const hw, hri_evsys_user_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_reg(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_reg(const void *const hw, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->USER.reg;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY8) >> EVSYS_CHSTATUS_USRRDY8_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY9) >> EVSYS_CHSTATUS_USRRDY9_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY10) >> EVSYS_CHSTATUS_USRRDY10_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY11) >> EVSYS_CHSTATUS_USRRDY11_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY8) >> EVSYS_CHSTATUS_CHBUSY8_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY9) >> EVSYS_CHSTATUS_CHBUSY9_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY10) >> EVSYS_CHSTATUS_CHBUSY10_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY11) >> EVSYS_CHSTATUS_CHBUSY11_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CHSTATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EVSYS_D21_H_INCLUDED */
+#endif /* _SAMD21_EVSYS_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h b/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h
new file mode 100644
index 000000000..39aa44eab
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h
@@ -0,0 +1,933 @@
+/**
+ * \file
+ *
+ * \brief SAM GCLK
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_GCLK_COMPONENT_
+#ifndef _HRI_GCLK_D21_H_INCLUDED_
+#define _HRI_GCLK_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_GCLK_CRITICAL_SECTIONS)
+#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define GCLK_CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_gclk_clkctrl_reg_t;
+typedef uint32_t hri_gclk_genctrl_reg_t;
+typedef uint32_t hri_gclk_gendiv_reg_t;
+typedef uint8_t  hri_gclk_ctrl_reg_t;
+typedef uint8_t  hri_gclk_status_reg_t;
+
+static inline void hri_gclk_wait_for_sync(const void *const hw)
+{
+	while (((const Gclk *)hw)->STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_gclk_is_syncing(const void *const hw)
+{
+	return ((const Gclk *)hw)->STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_gclk_set_CTRL_SWRST_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->CTRL.reg |= GCLK_CTRL_SWRST;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->CTRL.reg;
+	tmp = (tmp & GCLK_CTRL_SWRST) >> GCLK_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_set_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRL.reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrl_reg_t hri_gclk_get_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Gclk *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRL.reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRL.reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRL.reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrl_reg_t hri_gclk_read_CTRL_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->CTRL.reg;
+}
+
+static inline void hri_gclk_set_CLKCTRL_CLKEN_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_CLKCTRL_CLKEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp = (tmp & GCLK_CLKCTRL_CLKEN) >> GCLK_CLKCTRL_CLKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_CLKCTRL_CLKEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp &= ~GCLK_CLKCTRL_CLKEN;
+	tmp |= value << GCLK_CLKCTRL_CLKEN_Pos;
+	((Gclk *)hw)->CLKCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CLKCTRL_CLKEN_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CLKCTRL_CLKEN_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_CLKEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_CLKCTRL_WRTLOCK_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_CLKCTRL_WRTLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp = (tmp & GCLK_CLKCTRL_WRTLOCK) >> GCLK_CLKCTRL_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_CLKCTRL_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp &= ~GCLK_CLKCTRL_WRTLOCK;
+	tmp |= value << GCLK_CLKCTRL_WRTLOCK_Pos;
+	((Gclk *)hw)->CLKCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CLKCTRL_WRTLOCK_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CLKCTRL_WRTLOCK_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp = (tmp & GCLK_CLKCTRL_ID(mask)) >> GCLK_CLKCTRL_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t data)
+{
+	uint16_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp &= ~GCLK_CLKCTRL_ID_Msk;
+	tmp |= GCLK_CLKCTRL_ID(data);
+	((Gclk *)hw)->CLKCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp = (tmp & GCLK_CLKCTRL_ID_Msk) >> GCLK_CLKCTRL_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp = (tmp & GCLK_CLKCTRL_GEN(mask)) >> GCLK_CLKCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t data)
+{
+	uint16_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp &= ~GCLK_CLKCTRL_GEN_Msk;
+	tmp |= GCLK_CLKCTRL_GEN(data);
+	((Gclk *)hw)->CLKCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_GEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp = (tmp & GCLK_CLKCTRL_GEN_Msk) >> GCLK_CLKCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Gclk *)hw)->CLKCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CLKCTRL.reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->CLKCTRL.reg;
+}
+
+static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= ~GCLK_GENCTRL_GENEN;
+	tmp |= value << GCLK_GENCTRL_GENEN_Pos;
+	((Gclk *)hw)->GENCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_GENEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_IDC;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= ~GCLK_GENCTRL_IDC;
+	tmp |= value << GCLK_GENCTRL_IDC_Pos;
+	((Gclk *)hw)->GENCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_IDC;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_IDC;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_OOV;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= ~GCLK_GENCTRL_OOV;
+	tmp |= value << GCLK_GENCTRL_OOV_Pos;
+	((Gclk *)hw)->GENCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_OOV;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_OOV;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_OE;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= ~GCLK_GENCTRL_OE;
+	tmp |= value << GCLK_GENCTRL_OE_Pos;
+	((Gclk *)hw)->GENCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_OE;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_OE;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_DIVSEL;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= ~GCLK_GENCTRL_DIVSEL;
+	tmp |= value << GCLK_GENCTRL_DIVSEL_Pos;
+	((Gclk *)hw)->GENCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_DIVSEL;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_DIVSEL;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_RUNSTDBY;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= ~GCLK_GENCTRL_RUNSTDBY;
+	tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos;
+	((Gclk *)hw)->GENCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_RUNSTDBY;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_RUNSTDBY;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_ID(mask)) >> GCLK_GENCTRL_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= ~GCLK_GENCTRL_ID_Msk;
+	tmp |= GCLK_GENCTRL_ID(data);
+	((Gclk *)hw)->GENCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_ID_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_ID_Msk) >> GCLK_GENCTRL_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_SRC(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= ~GCLK_GENCTRL_SRC_Msk;
+	tmp |= GCLK_GENCTRL_SRC(data);
+	((Gclk *)hw)->GENCTRL.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_SRC(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	hri_gclk_wait_for_sync(hw);
+	((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_SRC(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw);
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL.reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL.reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL.reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL.reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->GENCTRL.reg;
+}
+
+static inline void hri_gclk_set_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg |= GCLK_GENDIV_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENDIV.reg;
+	tmp = (tmp & GCLK_GENDIV_ID(mask)) >> GCLK_GENDIV_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENDIV.reg;
+	tmp &= ~GCLK_GENDIV_ID_Msk;
+	tmp |= GCLK_GENDIV_ID(data);
+	((Gclk *)hw)->GENDIV.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg &= ~GCLK_GENDIV_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg ^= GCLK_GENDIV_ID(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_ID_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENDIV.reg;
+	tmp = (tmp & GCLK_GENDIV_ID_Msk) >> GCLK_GENDIV_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg |= GCLK_GENDIV_DIV(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENDIV.reg;
+	tmp = (tmp & GCLK_GENDIV_DIV(mask)) >> GCLK_GENDIV_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENDIV.reg;
+	tmp &= ~GCLK_GENDIV_DIV_Msk;
+	tmp |= GCLK_GENDIV_DIV(data);
+	((Gclk *)hw)->GENDIV.reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg &= ~GCLK_GENDIV_DIV(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg ^= GCLK_GENDIV_DIV(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_DIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENDIV.reg;
+	tmp = (tmp & GCLK_GENDIV_DIV_Msk) >> GCLK_GENDIV_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENDIV.reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->GENDIV.reg;
+}
+
+static inline bool hri_gclk_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->STATUS.reg & GCLK_STATUS_SYNCBUSY) >> GCLK_STATUS_SYNCBUSY_Pos;
+}
+
+static inline hri_gclk_status_reg_t hri_gclk_get_STATUS_reg(const void *const hw, hri_gclk_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Gclk *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gclk_status_reg_t hri_gclk_read_STATUS_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_GCLK_D21_H_INCLUDED */
+#endif /* _SAMD21_GCLK_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h b/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h
new file mode 100644
index 000000000..d9c598687
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h
@@ -0,0 +1,289 @@
+/**
+ * \file
+ *
+ * \brief SAM HMATRIXB
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_HMATRIXB_COMPONENT_
+#ifndef _HRI_HMATRIXB_D21_H_INCLUDED_
+#define _HRI_HMATRIXB_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS)
+#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define HMATRIXB_CRITICAL_SECTION_ENTER()
+#define HMATRIXB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_hmatrixb_pras_reg_t;
+typedef uint32_t hri_hmatrixb_prbs_reg_t;
+typedef uint32_t hri_hmatrixb_sfr_reg_t;
+typedef uint32_t hri_hmatrixbprs_pras_reg_t;
+typedef uint32_t hri_hmatrixbprs_prbs_reg_t;
+
+static inline void hri_hmatrixb_set_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->SFR[index].reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_get_SFR_reg(const void *const hw, uint8_t index,
+                                                              hri_hmatrixb_sfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->SFR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->SFR[index].reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->SFR[index].reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->SFR[index].reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_read_SFR_reg(const void *const hw, uint8_t index)
+{
+	return ((Hmatrixb *)hw)->SFR[index].reg;
+}
+
+static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((HmatrixbPrs *)hw)->PRAS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw)
+{
+	return ((HmatrixbPrs *)hw)->PRAS.reg;
+}
+
+static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((HmatrixbPrs *)hw)->PRBS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw)
+{
+	return ((HmatrixbPrs *)hw)->PRBS.reg;
+}
+
+static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_hmatrixb_pras_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_pras_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg;
+}
+
+static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_hmatrixb_prbs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_prbs_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_HMATRIXB_D21_H_INCLUDED */
+#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h b/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h
new file mode 100644
index 000000000..5ab2f76c0
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h
@@ -0,0 +1,2516 @@
+/**
+ * \file
+ *
+ * \brief SAM I2S
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_I2S_COMPONENT_
+#ifndef _HRI_I2S_D21_H_INCLUDED_
+#define _HRI_I2S_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_I2S_CRITICAL_SECTIONS)
+#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define I2S_CRITICAL_SECTION_ENTER()
+#define I2S_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_i2s_intenset_reg_t;
+typedef uint16_t hri_i2s_intflag_reg_t;
+typedef uint16_t hri_i2s_syncbusy_reg_t;
+typedef uint32_t hri_i2s_clkctrl_reg_t;
+typedef uint32_t hri_i2s_data_reg_t;
+typedef uint32_t hri_i2s_serctrl_reg_t;
+typedef uint8_t  hri_i2s_ctrla_reg_t;
+
+static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg)
+{
+	while (((I2s *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg)
+{
+	return ((I2s *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
+}
+
+static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
+}
+
+static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
+}
+
+static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
+}
+
+static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
+}
+
+static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
+}
+
+static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
+}
+
+static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
+}
+
+static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
+}
+
+static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
+}
+
+static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
+}
+
+static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
+}
+
+static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
+}
+
+static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
+}
+
+static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
+}
+
+static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
+}
+
+static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	((I2s *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw)
+{
+	return ((I2s *)hw)->INTENSET.reg;
+}
+
+static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data)
+{
+	((I2s *)hw)->INTENSET.reg = data;
+	((I2s *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	((I2s *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
+}
+
+static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
+}
+
+static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
+}
+
+static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
+}
+
+static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
+}
+
+static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
+}
+
+static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
+}
+
+static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
+}
+
+static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
+}
+
+static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw)
+{
+	return ((I2s *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
+{
+	((I2s *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_ENABLE;
+	tmp |= value << I2S_CTRLA_ENABLE_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_CKEN0;
+	tmp |= value << I2S_CTRLA_CKEN0_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_CKEN1;
+	tmp |= value << I2S_CTRLA_CKEN1_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_SEREN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SEREN0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_SEREN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_SEREN0) >> I2S_CTRLA_SEREN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_SEREN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_SEREN0;
+	tmp |= value << I2S_CTRLA_SEREN0_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_SEREN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_SEREN0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_SEREN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_SEREN0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_SEREN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SEREN1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_SEREN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_SEREN1) >> I2S_CTRLA_SEREN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_SEREN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_SEREN1;
+	tmp |= value << I2S_CTRLA_SEREN1_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_SEREN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_SEREN1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_SEREN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw,
+	                      I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1
+	                          | I2S_SYNCBUSY_SEREN0
+	                          | I2S_SYNCBUSY_SEREN1);
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_SEREN1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw)
+{
+	return ((I2s *)hw)->CTRLA.reg;
+}
+
+static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_BITDELAY;
+	tmp |= value << I2S_CLKCTRL_BITDELAY_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSSEL;
+	tmp |= value << I2S_CLKCTRL_FSSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSINV;
+	tmp |= value << I2S_CLKCTRL_FSINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SCKSEL;
+	tmp |= value << I2S_CLKCTRL_SCKSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKSEL;
+	tmp |= value << I2S_CLKCTRL_MCKSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKEN;
+	tmp |= value << I2S_CLKCTRL_MCKEN_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSOUTINV;
+	tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SCKOUTINV;
+	tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKOUTINV;
+	tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index,
+                                                                    hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk;
+	tmp |= I2S_CLKCTRL_SLOTSIZE(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk;
+	tmp |= I2S_CLKCTRL_NBSLOTS(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk;
+	tmp |= I2S_CLKCTRL_FSWIDTH(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index,
+                                                                  hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKDIV_Msk;
+	tmp |= I2S_CLKCTRL_MCKDIV(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index,
+                                                                     hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk;
+	tmp |= I2S_CLKCTRL_MCKOUTDIV(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((I2s *)hw)->CLKCTRL[index].reg;
+}
+
+static inline void hri_i2s_set_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_TXSAME) >> I2S_SERCTRL_TXSAME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_TXSAME;
+	tmp |= value << I2S_SERCTRL_TXSAME_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_CLKSEL) >> I2S_SERCTRL_CLKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_CLKSEL;
+	tmp |= value << I2S_SERCTRL_CLKSEL_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTADJ) >> I2S_SERCTRL_SLOTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTADJ;
+	tmp |= value << I2S_SERCTRL_SLOTADJ_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_WORDADJ) >> I2S_SERCTRL_WORDADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_WORDADJ;
+	tmp |= value << I2S_SERCTRL_WORDADJ_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_BITREV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_BITREV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_BITREV) >> I2S_SERCTRL_BITREV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_BITREV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_BITREV;
+	tmp |= value << I2S_SERCTRL_BITREV_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_BITREV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_BITREV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTDIS0) >> I2S_SERCTRL_SLOTDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTDIS0;
+	tmp |= value << I2S_SERCTRL_SLOTDIS0_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTDIS1) >> I2S_SERCTRL_SLOTDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTDIS1;
+	tmp |= value << I2S_SERCTRL_SLOTDIS1_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTDIS2) >> I2S_SERCTRL_SLOTDIS2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTDIS2;
+	tmp |= value << I2S_SERCTRL_SLOTDIS2_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTDIS3) >> I2S_SERCTRL_SLOTDIS3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTDIS3;
+	tmp |= value << I2S_SERCTRL_SLOTDIS3_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTDIS4) >> I2S_SERCTRL_SLOTDIS4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTDIS4;
+	tmp |= value << I2S_SERCTRL_SLOTDIS4_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTDIS5) >> I2S_SERCTRL_SLOTDIS5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTDIS5;
+	tmp |= value << I2S_SERCTRL_SLOTDIS5_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTDIS6) >> I2S_SERCTRL_SLOTDIS6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTDIS6;
+	tmp |= value << I2S_SERCTRL_SLOTDIS6_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SLOTDIS7) >> I2S_SERCTRL_SLOTDIS7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SLOTDIS7;
+	tmp |= value << I2S_SERCTRL_SLOTDIS7_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_MONO_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_MONO_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_MONO) >> I2S_SERCTRL_MONO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_MONO_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_MONO;
+	tmp |= value << I2S_SERCTRL_MONO_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_MONO_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_MONO_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_DMA_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_DMA_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_DMA) >> I2S_SERCTRL_DMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_DMA_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_DMA;
+	tmp |= value << I2S_SERCTRL_DMA_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_DMA_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_DMA_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_RXLOOP) >> I2S_SERCTRL_RXLOOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_RXLOOP;
+	tmp |= value << I2S_SERCTRL_RXLOOP_Pos;
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_serctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SERMODE(mask)) >> I2S_SERCTRL_SERMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_SERMODE_Msk;
+	tmp |= I2S_SERCTRL_SERMODE(data);
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_SERMODE_Msk) >> I2S_SERCTRL_SERMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index,
+                                                                     hri_i2s_serctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_TXDEFAULT(mask)) >> I2S_SERCTRL_TXDEFAULT_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_TXDEFAULT_Msk;
+	tmp |= I2S_SERCTRL_TXDEFAULT(data);
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_TXDEFAULT_Msk) >> I2S_SERCTRL_TXDEFAULT_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index,
+                                                                    hri_i2s_serctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_DATASIZE(mask)) >> I2S_SERCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_DATASIZE_Msk;
+	tmp |= I2S_SERCTRL_DATASIZE(data);
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_DATASIZE_Msk) >> I2S_SERCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index,
+                                                                  hri_i2s_serctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_EXTEND(mask)) >> I2S_SERCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= ~I2S_SERCTRL_EXTEND_Msk;
+	tmp |= I2S_SERCTRL_EXTEND(data);
+	((I2s *)hw)->SERCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp = (tmp & I2S_SERCTRL_EXTEND_Msk) >> I2S_SERCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_i2s_serctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->SERCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->SERCTRL[index].reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((I2s *)hw)->SERCTRL[index].reg;
+}
+
+static inline void hri_i2s_set_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	((I2s *)hw)->DATA[index].reg |= I2S_DATA_DATA(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_data_reg_t hri_i2s_get_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask)
+{
+	uint32_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->DATA[index].reg;
+	tmp = (tmp & I2S_DATA_DATA(mask)) >> I2S_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->DATA[index].reg;
+	tmp &= ~I2S_DATA_DATA_Msk;
+	tmp |= I2S_DATA_DATA(data);
+	((I2s *)hw)->DATA[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	((I2s *)hw)->DATA[index].reg &= ~I2S_DATA_DATA(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	((I2s *)hw)->DATA[index].reg ^= I2S_DATA_DATA(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_data_reg_t hri_i2s_read_DATA_DATA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->DATA[index].reg;
+	tmp = (tmp & I2S_DATA_DATA_Msk) >> I2S_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->DATA[index].reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_data_reg_t hri_i2s_get_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->DATA[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->DATA[index].reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->DATA[index].reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->DATA[index].reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_data_reg_t hri_i2s_read_DATA_reg(const void *const hw, uint8_t index)
+{
+	return ((I2s *)hw)->DATA[index].reg;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_SEREN0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SEREN0) >> I2S_SYNCBUSY_SEREN0_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_SEREN1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SEREN1) >> I2S_SYNCBUSY_SEREN1_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_DATA0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_DATA0) >> I2S_SYNCBUSY_DATA0_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_DATA1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_DATA1) >> I2S_SYNCBUSY_DATA1_Pos;
+}
+
+static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((I2s *)hw)->SYNCBUSY.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_I2S_D21_H_INCLUDED */
+#endif /* _SAMD21_I2S_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h b/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h
new file mode 100644
index 000000000..09f5f66d6
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h
@@ -0,0 +1,560 @@
+/**
+ * \file
+ *
+ * \brief SAM MTB
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_MTB_COMPONENT_
+#ifndef _HRI_MTB_D21_H_INCLUDED_
+#define _HRI_MTB_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MTB_CRITICAL_SECTIONS)
+#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MTB_CRITICAL_SECTION_ENTER()
+#define MTB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mtb_authstatus_reg_t;
+typedef uint32_t hri_mtb_base_reg_t;
+typedef uint32_t hri_mtb_cid0_reg_t;
+typedef uint32_t hri_mtb_cid1_reg_t;
+typedef uint32_t hri_mtb_cid2_reg_t;
+typedef uint32_t hri_mtb_cid3_reg_t;
+typedef uint32_t hri_mtb_claimset_reg_t;
+typedef uint32_t hri_mtb_devarch_reg_t;
+typedef uint32_t hri_mtb_devid_reg_t;
+typedef uint32_t hri_mtb_devtype_reg_t;
+typedef uint32_t hri_mtb_flow_reg_t;
+typedef uint32_t hri_mtb_itctrl_reg_t;
+typedef uint32_t hri_mtb_lockaccess_reg_t;
+typedef uint32_t hri_mtb_lockstatus_reg_t;
+typedef uint32_t hri_mtb_master_reg_t;
+typedef uint32_t hri_mtb_pid0_reg_t;
+typedef uint32_t hri_mtb_pid1_reg_t;
+typedef uint32_t hri_mtb_pid2_reg_t;
+typedef uint32_t hri_mtb_pid3_reg_t;
+typedef uint32_t hri_mtb_pid4_reg_t;
+typedef uint32_t hri_mtb_pid5_reg_t;
+typedef uint32_t hri_mtb_pid6_reg_t;
+typedef uint32_t hri_mtb_pid7_reg_t;
+typedef uint32_t hri_mtb_position_reg_t;
+
+static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	((Mtb *)hw)->CLAIMSET.reg = mask;
+}
+
+static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CLAIMSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CLAIMSET.reg;
+}
+
+static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data)
+{
+	((Mtb *)hw)->CLAIMSET.reg = data;
+	((Mtb *)hw)->CLAIMCLR.reg = ~data;
+}
+
+static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	((Mtb *)hw)->CLAIMCLR.reg = mask;
+}
+
+static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->POSITION.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->POSITION.reg;
+}
+
+static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->MASTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->MASTER.reg;
+}
+
+static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->FLOW.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->FLOW.reg;
+}
+
+static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->ITCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->ITCTRL.reg;
+}
+
+static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->LOCKACCESS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->LOCKACCESS.reg;
+}
+
+static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->BASE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->BASE.reg;
+}
+
+static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->LOCKSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->LOCKSTATUS.reg;
+}
+
+static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->AUTHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->AUTHSTATUS.reg;
+}
+
+static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVARCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVARCH.reg;
+}
+
+static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVID.reg;
+}
+
+static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVTYPE.reg;
+}
+
+static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID4.reg;
+}
+
+static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID5.reg;
+}
+
+static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID6.reg;
+}
+
+static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID7.reg;
+}
+
+static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID0.reg;
+}
+
+static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID1.reg;
+}
+
+static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID2.reg;
+}
+
+static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID3.reg;
+}
+
+static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID0.reg;
+}
+
+static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID1.reg;
+}
+
+static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID2.reg;
+}
+
+static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID3.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MTB_D21_H_INCLUDED */
+#endif /* _SAMD21_MTB_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h b/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h
new file mode 100644
index 000000000..366387209
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h
@@ -0,0 +1,2304 @@
+/**
+ * \file
+ *
+ * \brief SAM NVIC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_NVIC_COMPONENT_
+#ifndef _HRI_NVIC_D21_H_INCLUDED_
+#define _HRI_NVIC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVIC_CRITICAL_SECTIONS)
+#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVIC_CRITICAL_SECTION_ENTER()
+#define NVIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_nvic_nvicicer_reg_t;
+typedef uint32_t hri_nvic_nvicicpr_reg_t;
+typedef uint32_t hri_nvic_nvicipr0_reg_t;
+typedef uint32_t hri_nvic_nvicipr1_reg_t;
+typedef uint32_t hri_nvic_nvicipr2_reg_t;
+typedef uint32_t hri_nvic_nvicipr3_reg_t;
+typedef uint32_t hri_nvic_nvicipr4_reg_t;
+typedef uint32_t hri_nvic_nvicipr5_reg_t;
+typedef uint32_t hri_nvic_nvicipr6_reg_t;
+typedef uint32_t hri_nvic_nvicipr7_reg_t;
+typedef uint32_t hri_nvic_nviciser_reg_t;
+typedef uint32_t hri_nvic_nvicispr_reg_t;
+
+static inline void hri_nvic_set_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISER.reg |= NVIC_NVICISER_SETENA(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nviciser_reg_t hri_nvic_get_NVICISER_SETENA_bf(const void *const       hw,
+                                                                      hri_nvic_nviciser_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICISER.reg;
+	tmp = (tmp & NVIC_NVICISER_SETENA(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICISER.reg;
+	tmp &= ~NVIC_NVICISER_SETENA_Msk;
+	tmp |= NVIC_NVICISER_SETENA(data);
+	((Nvic *)hw)->NVICISER.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISER.reg &= ~NVIC_NVICISER_SETENA(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISER.reg ^= NVIC_NVICISER_SETENA(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nviciser_reg_t hri_nvic_read_NVICISER_SETENA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICISER.reg;
+	tmp = (tmp & NVIC_NVICISER_SETENA_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISER.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nviciser_reg_t hri_nvic_get_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICISER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISER.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISER.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISER.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nviciser_reg_t hri_nvic_read_NVICISER_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICISER.reg;
+}
+
+static inline void hri_nvic_set_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICER.reg |= NVIC_NVICICER_CLRENA(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicicer_reg_t hri_nvic_get_NVICICER_CLRENA_bf(const void *const       hw,
+                                                                      hri_nvic_nvicicer_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICICER.reg;
+	tmp = (tmp & NVIC_NVICICER_CLRENA(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICICER.reg;
+	tmp &= ~NVIC_NVICICER_CLRENA_Msk;
+	tmp |= NVIC_NVICICER_CLRENA(data);
+	((Nvic *)hw)->NVICICER.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICER.reg &= ~NVIC_NVICICER_CLRENA(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICER.reg ^= NVIC_NVICICER_CLRENA(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicicer_reg_t hri_nvic_read_NVICICER_CLRENA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICICER.reg;
+	tmp = (tmp & NVIC_NVICICER_CLRENA_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICER.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicicer_reg_t hri_nvic_get_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICICER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICER.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICER.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICER.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicicer_reg_t hri_nvic_read_NVICICER_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICICER.reg;
+}
+
+static inline void hri_nvic_set_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISPR.reg |= NVIC_NVICISPR_SETPEND(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicispr_reg_t hri_nvic_get_NVICISPR_SETPEND_bf(const void *const       hw,
+                                                                       hri_nvic_nvicispr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICISPR.reg;
+	tmp = (tmp & NVIC_NVICISPR_SETPEND(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICISPR.reg;
+	tmp &= ~NVIC_NVICISPR_SETPEND_Msk;
+	tmp |= NVIC_NVICISPR_SETPEND(data);
+	((Nvic *)hw)->NVICISPR.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISPR.reg &= ~NVIC_NVICISPR_SETPEND(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISPR.reg ^= NVIC_NVICISPR_SETPEND(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicispr_reg_t hri_nvic_read_NVICISPR_SETPEND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICISPR.reg;
+	tmp = (tmp & NVIC_NVICISPR_SETPEND_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISPR.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicispr_reg_t hri_nvic_get_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICISPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISPR.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISPR.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICISPR.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicispr_reg_t hri_nvic_read_NVICISPR_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICISPR.reg;
+}
+
+static inline void hri_nvic_set_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICPR.reg |= NVIC_NVICICPR_CLRPEND(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicicpr_reg_t hri_nvic_get_NVICICPR_CLRPEND_bf(const void *const       hw,
+                                                                       hri_nvic_nvicicpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICICPR.reg;
+	tmp = (tmp & NVIC_NVICICPR_CLRPEND(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICICPR.reg;
+	tmp &= ~NVIC_NVICICPR_CLRPEND_Msk;
+	tmp |= NVIC_NVICICPR_CLRPEND(data);
+	((Nvic *)hw)->NVICICPR.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICPR.reg &= ~NVIC_NVICICPR_CLRPEND(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICPR.reg ^= NVIC_NVICICPR_CLRPEND(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicicpr_reg_t hri_nvic_read_NVICICPR_CLRPEND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICICPR.reg;
+	tmp = (tmp & NVIC_NVICICPR_CLRPEND_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICPR.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicicpr_reg_t hri_nvic_get_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICICPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICPR.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICPR.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICICPR.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicicpr_reg_t hri_nvic_read_NVICICPR_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICICPR.reg;
+}
+
+static inline void hri_nvic_set_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI0(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp = (tmp & NVIC_NVICIPR0_PRI0(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp &= ~NVIC_NVICIPR0_PRI0_Msk;
+	tmp |= NVIC_NVICIPR0_PRI0(data);
+	((Nvic *)hw)->NVICIPR0.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI0(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI0(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp = (tmp & NVIC_NVICIPR0_PRI0_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI1(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp = (tmp & NVIC_NVICIPR0_PRI1(mask)) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp &= ~NVIC_NVICIPR0_PRI1_Msk;
+	tmp |= NVIC_NVICIPR0_PRI1(data);
+	((Nvic *)hw)->NVICIPR0.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI1(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI1(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp = (tmp & NVIC_NVICIPR0_PRI1_Msk) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI2(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp = (tmp & NVIC_NVICIPR0_PRI2(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp &= ~NVIC_NVICIPR0_PRI2_Msk;
+	tmp |= NVIC_NVICIPR0_PRI2(data);
+	((Nvic *)hw)->NVICIPR0.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI2(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI2(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp = (tmp & NVIC_NVICIPR0_PRI2_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI3(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp = (tmp & NVIC_NVICIPR0_PRI3(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp &= ~NVIC_NVICIPR0_PRI3_Msk;
+	tmp |= NVIC_NVICIPR0_PRI3(data);
+	((Nvic *)hw)->NVICIPR0.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI3(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI3(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp = (tmp & NVIC_NVICIPR0_PRI3_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR0.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICIPR0.reg;
+}
+
+static inline void hri_nvic_set_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI4(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp = (tmp & NVIC_NVICIPR1_PRI4(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp &= ~NVIC_NVICIPR1_PRI4_Msk;
+	tmp |= NVIC_NVICIPR1_PRI4(data);
+	((Nvic *)hw)->NVICIPR1.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI4(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI4(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI4_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp = (tmp & NVIC_NVICIPR1_PRI4_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI5(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp = (tmp & NVIC_NVICIPR1_PRI5(mask)) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp &= ~NVIC_NVICIPR1_PRI5_Msk;
+	tmp |= NVIC_NVICIPR1_PRI5(data);
+	((Nvic *)hw)->NVICIPR1.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI5(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI5(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI5_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp = (tmp & NVIC_NVICIPR1_PRI5_Msk) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI6(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp = (tmp & NVIC_NVICIPR1_PRI6(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp &= ~NVIC_NVICIPR1_PRI6_Msk;
+	tmp |= NVIC_NVICIPR1_PRI6(data);
+	((Nvic *)hw)->NVICIPR1.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI6(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI6(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI6_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp = (tmp & NVIC_NVICIPR1_PRI6_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI7(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp = (tmp & NVIC_NVICIPR1_PRI7(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp &= ~NVIC_NVICIPR1_PRI7_Msk;
+	tmp |= NVIC_NVICIPR1_PRI7(data);
+	((Nvic *)hw)->NVICIPR1.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI7(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI7(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI7_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp = (tmp & NVIC_NVICIPR1_PRI7_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR1.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICIPR1.reg;
+}
+
+static inline void hri_nvic_set_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI8(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp = (tmp & NVIC_NVICIPR2_PRI8(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp &= ~NVIC_NVICIPR2_PRI8_Msk;
+	tmp |= NVIC_NVICIPR2_PRI8(data);
+	((Nvic *)hw)->NVICIPR2.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI8(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI8(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI8_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp = (tmp & NVIC_NVICIPR2_PRI8_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI9(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp = (tmp & NVIC_NVICIPR2_PRI9(mask)) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp &= ~NVIC_NVICIPR2_PRI9_Msk;
+	tmp |= NVIC_NVICIPR2_PRI9(data);
+	((Nvic *)hw)->NVICIPR2.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI9(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI9(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI9_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp = (tmp & NVIC_NVICIPR2_PRI9_Msk) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI10(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp = (tmp & NVIC_NVICIPR2_PRI10(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp &= ~NVIC_NVICIPR2_PRI10_Msk;
+	tmp |= NVIC_NVICIPR2_PRI10(data);
+	((Nvic *)hw)->NVICIPR2.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI10(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI10(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI10_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp = (tmp & NVIC_NVICIPR2_PRI10_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI11(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp = (tmp & NVIC_NVICIPR2_PRI11(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp &= ~NVIC_NVICIPR2_PRI11_Msk;
+	tmp |= NVIC_NVICIPR2_PRI11(data);
+	((Nvic *)hw)->NVICIPR2.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI11(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI11(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI11_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp = (tmp & NVIC_NVICIPR2_PRI11_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR2.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICIPR2.reg;
+}
+
+static inline void hri_nvic_set_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI12(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp = (tmp & NVIC_NVICIPR3_PRI12(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp &= ~NVIC_NVICIPR3_PRI12_Msk;
+	tmp |= NVIC_NVICIPR3_PRI12(data);
+	((Nvic *)hw)->NVICIPR3.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI12(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI12(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI12_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp = (tmp & NVIC_NVICIPR3_PRI12_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI13(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp = (tmp & NVIC_NVICIPR3_PRI13(mask)) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp &= ~NVIC_NVICIPR3_PRI13_Msk;
+	tmp |= NVIC_NVICIPR3_PRI13(data);
+	((Nvic *)hw)->NVICIPR3.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI13(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI13(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI13_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp = (tmp & NVIC_NVICIPR3_PRI13_Msk) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI14(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp = (tmp & NVIC_NVICIPR3_PRI14(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp &= ~NVIC_NVICIPR3_PRI14_Msk;
+	tmp |= NVIC_NVICIPR3_PRI14(data);
+	((Nvic *)hw)->NVICIPR3.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI14(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI14(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI14_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp = (tmp & NVIC_NVICIPR3_PRI14_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI15(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp = (tmp & NVIC_NVICIPR3_PRI15(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp &= ~NVIC_NVICIPR3_PRI15_Msk;
+	tmp |= NVIC_NVICIPR3_PRI15(data);
+	((Nvic *)hw)->NVICIPR3.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI15(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI15(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI15_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp = (tmp & NVIC_NVICIPR3_PRI15_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR3.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICIPR3.reg;
+}
+
+static inline void hri_nvic_set_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI16(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp = (tmp & NVIC_NVICIPR4_PRI16(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp &= ~NVIC_NVICIPR4_PRI16_Msk;
+	tmp |= NVIC_NVICIPR4_PRI16(data);
+	((Nvic *)hw)->NVICIPR4.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI16(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI16(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI16_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp = (tmp & NVIC_NVICIPR4_PRI16_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI17(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp = (tmp & NVIC_NVICIPR4_PRI17(mask)) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp &= ~NVIC_NVICIPR4_PRI17_Msk;
+	tmp |= NVIC_NVICIPR4_PRI17(data);
+	((Nvic *)hw)->NVICIPR4.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI17(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI17(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI17_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp = (tmp & NVIC_NVICIPR4_PRI17_Msk) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI18(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp = (tmp & NVIC_NVICIPR4_PRI18(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp &= ~NVIC_NVICIPR4_PRI18_Msk;
+	tmp |= NVIC_NVICIPR4_PRI18(data);
+	((Nvic *)hw)->NVICIPR4.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI18(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI18(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI18_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp = (tmp & NVIC_NVICIPR4_PRI18_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI19(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp = (tmp & NVIC_NVICIPR4_PRI19(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp &= ~NVIC_NVICIPR4_PRI19_Msk;
+	tmp |= NVIC_NVICIPR4_PRI19(data);
+	((Nvic *)hw)->NVICIPR4.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI19(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI19(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI19_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp = (tmp & NVIC_NVICIPR4_PRI19_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR4.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICIPR4.reg;
+}
+
+static inline void hri_nvic_set_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI20(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp = (tmp & NVIC_NVICIPR5_PRI20(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp &= ~NVIC_NVICIPR5_PRI20_Msk;
+	tmp |= NVIC_NVICIPR5_PRI20(data);
+	((Nvic *)hw)->NVICIPR5.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI20(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI20(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI20_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp = (tmp & NVIC_NVICIPR5_PRI20_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI21(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp = (tmp & NVIC_NVICIPR5_PRI21(mask)) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp &= ~NVIC_NVICIPR5_PRI21_Msk;
+	tmp |= NVIC_NVICIPR5_PRI21(data);
+	((Nvic *)hw)->NVICIPR5.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI21(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI21(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI21_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp = (tmp & NVIC_NVICIPR5_PRI21_Msk) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI22(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp = (tmp & NVIC_NVICIPR5_PRI22(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp &= ~NVIC_NVICIPR5_PRI22_Msk;
+	tmp |= NVIC_NVICIPR5_PRI22(data);
+	((Nvic *)hw)->NVICIPR5.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI22(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI22(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI22_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp = (tmp & NVIC_NVICIPR5_PRI22_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI23(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp = (tmp & NVIC_NVICIPR5_PRI23(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp &= ~NVIC_NVICIPR5_PRI23_Msk;
+	tmp |= NVIC_NVICIPR5_PRI23(data);
+	((Nvic *)hw)->NVICIPR5.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI23(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI23(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI23_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp = (tmp & NVIC_NVICIPR5_PRI23_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR5.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICIPR5.reg;
+}
+
+static inline void hri_nvic_set_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI24(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp = (tmp & NVIC_NVICIPR6_PRI24(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp &= ~NVIC_NVICIPR6_PRI24_Msk;
+	tmp |= NVIC_NVICIPR6_PRI24(data);
+	((Nvic *)hw)->NVICIPR6.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI24(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI24(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI24_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp = (tmp & NVIC_NVICIPR6_PRI24_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI25(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp = (tmp & NVIC_NVICIPR6_PRI25(mask)) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp &= ~NVIC_NVICIPR6_PRI25_Msk;
+	tmp |= NVIC_NVICIPR6_PRI25(data);
+	((Nvic *)hw)->NVICIPR6.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI25(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI25(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI25_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp = (tmp & NVIC_NVICIPR6_PRI25_Msk) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI26(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp = (tmp & NVIC_NVICIPR6_PRI26(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp &= ~NVIC_NVICIPR6_PRI26_Msk;
+	tmp |= NVIC_NVICIPR6_PRI26(data);
+	((Nvic *)hw)->NVICIPR6.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI26(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI26(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI26_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp = (tmp & NVIC_NVICIPR6_PRI26_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI27(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp = (tmp & NVIC_NVICIPR6_PRI27(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp &= ~NVIC_NVICIPR6_PRI27_Msk;
+	tmp |= NVIC_NVICIPR6_PRI27(data);
+	((Nvic *)hw)->NVICIPR6.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI27(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI27(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI27_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp = (tmp & NVIC_NVICIPR6_PRI27_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR6.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICIPR6.reg;
+}
+
+static inline void hri_nvic_set_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI28(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp = (tmp & NVIC_NVICIPR7_PRI28(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp &= ~NVIC_NVICIPR7_PRI28_Msk;
+	tmp |= NVIC_NVICIPR7_PRI28(data);
+	((Nvic *)hw)->NVICIPR7.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI28(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI28(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI28_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp = (tmp & NVIC_NVICIPR7_PRI28_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI29(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp = (tmp & NVIC_NVICIPR7_PRI29(mask)) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp &= ~NVIC_NVICIPR7_PRI29_Msk;
+	tmp |= NVIC_NVICIPR7_PRI29(data);
+	((Nvic *)hw)->NVICIPR7.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI29(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI29(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI29_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp = (tmp & NVIC_NVICIPR7_PRI29_Msk) >> 8;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI30(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp = (tmp & NVIC_NVICIPR7_PRI30(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp &= ~NVIC_NVICIPR7_PRI30_Msk;
+	tmp |= NVIC_NVICIPR7_PRI30(data);
+	((Nvic *)hw)->NVICIPR7.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI30(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI30(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI30_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp = (tmp & NVIC_NVICIPR7_PRI30_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI31(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp = (tmp & NVIC_NVICIPR7_PRI31(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data)
+{
+	uint32_t tmp;
+	NVIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp &= ~NVIC_NVICIPR7_PRI31_Msk;
+	tmp |= NVIC_NVICIPR7_PRI31(data);
+	((Nvic *)hw)->NVICIPR7.reg = tmp;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI31(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI31(mask);
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI31_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp = (tmp & NVIC_NVICIPR7_PRI31_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_nvic_set_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->NVICIPR7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->NVICIPR7.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->NVICIPR7.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVIC_D21_H_INCLUDED */
+#endif /* _SAMD21_NVIC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h b/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h
new file mode 100644
index 000000000..dcf781f98
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h
@@ -0,0 +1,1024 @@
+/**
+ * \file
+ *
+ * \brief SAM NVMCTRL
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_NVMCTRL_COMPONENT_
+#ifndef _HRI_NVMCTRL_D21_H_INCLUDED_
+#define _HRI_NVMCTRL_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS)
+#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVMCTRL_CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_nvmctrl_ctrla_reg_t;
+typedef uint16_t hri_nvmctrl_lock_reg_t;
+typedef uint16_t hri_nvmctrl_status_reg_t;
+typedef uint32_t hri_nvmctrl_addr_reg_t;
+typedef uint32_t hri_nvmctrl_ctrlb_reg_t;
+typedef uint32_t hri_nvmctrl_param_reg_t;
+typedef uint8_t  hri_nvmctrl_intenset_reg_t;
+typedef uint8_t  hri_nvmctrl_intflag_reg_t;
+
+static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR;
+}
+
+static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_nvmctrl_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = data;
+	((Nvmctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_nvmctrl_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CMD_Msk;
+	tmp |= NVMCTRL_CTRLA_CMD(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk;
+	tmp |= NVMCTRL_CTRLA_CMDEX(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLA.reg;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_MANW;
+	tmp |= value << NVMCTRL_CTRLB_MANW_Pos;
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_CACHEDIS;
+	tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos;
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_RWS_Msk;
+	tmp |= NVMCTRL_CTRLB_RWS(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const       hw,
+                                                                        hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk;
+	tmp |= NVMCTRL_CTRLB_SLEEPPRM(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const       hw,
+                                                                        hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_READMODE_Msk;
+	tmp |= NVMCTRL_CTRLB_READMODE(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLB.reg;
+}
+
+static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= ~NVMCTRL_PARAM_NVMP_Msk;
+	tmp |= NVMCTRL_PARAM_NVMP(data);
+	((Nvmctrl *)hw)->PARAM.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= ~NVMCTRL_PARAM_PSZ_Msk;
+	tmp |= NVMCTRL_PARAM_PSZ(data);
+	((Nvmctrl *)hw)->PARAM.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->PARAM.reg;
+}
+
+static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= ~NVMCTRL_ADDR_ADDR_Msk;
+	tmp |= NVMCTRL_ADDR_ADDR(data);
+	((Nvmctrl *)hw)->ADDR.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ADDR.reg;
+}
+
+static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp &= ~NVMCTRL_LOCK_LOCK_Msk;
+	tmp |= NVMCTRL_LOCK_LOCK(data);
+	((Nvmctrl *)hw)->LOCK.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->LOCK.reg;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVMCTRL_D21_H_INCLUDED */
+#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_pac_d21.h b/atmel-samd/asf4/samd21/hri/hri_pac_d21.h
new file mode 100644
index 000000000..fbd75c46c
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_pac_d21.h
@@ -0,0 +1,130 @@
+/**
+ * \file
+ *
+ * \brief SAM PAC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_PAC_COMPONENT_
+#ifndef _HRI_PAC_D21_H_INCLUDED_
+#define _HRI_PAC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PAC_CRITICAL_SECTIONS)
+#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PAC_CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pac_wpset_reg_t;
+
+static inline void hri_pac_set_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask)
+{
+	((Pac *)hw)->WPSET.reg = PAC_WPSET_WP(mask);
+}
+
+static inline hri_pac_wpset_reg_t hri_pac_get_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WPSET.reg;
+	tmp = (tmp & PAC_WPSET_WP(mask)) >> PAC_WPSET_WP_Pos;
+	return tmp;
+}
+
+static inline hri_pac_wpset_reg_t hri_pac_read_WP_WP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WPSET.reg;
+	tmp = (tmp & PAC_WPSET_WP_Msk) >> PAC_WPSET_WP_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t data)
+{
+	((Pac *)hw)->WPSET.reg = PAC_WPSET_WP(data);
+	((Pac *)hw)->WPCLR.reg = ~PAC_WPSET_WP(data);
+}
+
+static inline void hri_pac_clear_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask)
+{
+	((Pac *)hw)->WPCLR.reg = PAC_WPSET_WP(mask);
+}
+
+static inline void hri_pac_set_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask)
+{
+	((Pac *)hw)->WPSET.reg = mask;
+}
+
+static inline hri_pac_wpset_reg_t hri_pac_get_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WPSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_wpset_reg_t hri_pac_read_WP_reg(const void *const hw)
+{
+	return ((Pac *)hw)->WPSET.reg;
+}
+
+static inline void hri_pac_write_WP_reg(const void *const hw, hri_pac_wpset_reg_t data)
+{
+	((Pac *)hw)->WPSET.reg = data;
+	((Pac *)hw)->WPCLR.reg = ~data;
+}
+
+static inline void hri_pac_clear_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask)
+{
+	((Pac *)hw)->WPCLR.reg = mask;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PAC_D21_H_INCLUDED */
+#endif /* _SAMD21_PAC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_pm_d21.h b/atmel-samd/asf4/samd21/hri/hri_pm_d21.h
new file mode 100644
index 000000000..41f84b5ea
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_pm_d21.h
@@ -0,0 +1,2545 @@
+/**
+ * \file
+ *
+ * \brief SAM PM
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_PM_COMPONENT_
+#ifndef _HRI_PM_D21_H_INCLUDED_
+#define _HRI_PM_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PM_CRITICAL_SECTIONS)
+#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PM_CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pm_ahbmask_reg_t;
+typedef uint32_t hri_pm_apbamask_reg_t;
+typedef uint32_t hri_pm_apbbmask_reg_t;
+typedef uint32_t hri_pm_apbcmask_reg_t;
+typedef uint8_t  hri_pm_apbasel_reg_t;
+typedef uint8_t  hri_pm_apbbsel_reg_t;
+typedef uint8_t  hri_pm_apbcsel_reg_t;
+typedef uint8_t  hri_pm_cpusel_reg_t;
+typedef uint8_t  hri_pm_ctrl_reg_t;
+typedef uint8_t  hri_pm_intenset_reg_t;
+typedef uint8_t  hri_pm_intflag_reg_t;
+typedef uint8_t  hri_pm_rcause_reg_t;
+typedef uint8_t  hri_pm_sleep_reg_t;
+
+static inline void hri_pm_set_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENSET.reg = PM_INTENSET_CKRDY;
+}
+
+static inline bool hri_pm_get_INTEN_CKRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_CKRDY) >> PM_INTENSET_CKRDY_Pos;
+}
+
+static inline void hri_pm_write_INTEN_CKRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pm *)hw)->INTENCLR.reg = PM_INTENSET_CKRDY;
+	} else {
+		((Pm *)hw)->INTENSET.reg = PM_INTENSET_CKRDY;
+	}
+}
+
+static inline void hri_pm_clear_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENCLR.reg = PM_INTENSET_CKRDY;
+}
+
+static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data)
+{
+	((Pm *)hw)->INTENSET.reg = data;
+	((Pm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pm_get_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_CKRDY) >> PM_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_pm_clear_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_CKRDY;
+}
+
+static inline bool hri_pm_get_interrupt_CKRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_CKRDY) >> PM_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_pm_clear_interrupt_CKRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_CKRDY;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	((Pm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pm_set_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRL.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrl_reg_t hri_pm_get_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRL.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRL.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRL.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrl_reg_t hri_pm_read_CTRL_reg(const void *const hw)
+{
+	return ((Pm *)hw)->CTRL.reg;
+}
+
+static inline void hri_pm_set_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEP.reg |= PM_SLEEP_IDLE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleep_reg_t hri_pm_get_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEP.reg;
+	tmp = (tmp & PM_SLEEP_IDLE(mask)) >> PM_SLEEP_IDLE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->SLEEP.reg;
+	tmp &= ~PM_SLEEP_IDLE_Msk;
+	tmp |= PM_SLEEP_IDLE(data);
+	((Pm *)hw)->SLEEP.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEP.reg &= ~PM_SLEEP_IDLE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEP.reg ^= PM_SLEEP_IDLE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleep_reg_t hri_pm_read_SLEEP_IDLE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEP.reg;
+	tmp = (tmp & PM_SLEEP_IDLE_Msk) >> PM_SLEEP_IDLE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEP.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleep_reg_t hri_pm_get_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEP.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEP.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEP.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleep_reg_t hri_pm_read_SLEEP_reg(const void *const hw)
+{
+	return ((Pm *)hw)->SLEEP.reg;
+}
+
+static inline void hri_pm_set_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CPUSEL.reg |= PM_CPUSEL_CPUDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_cpusel_reg_t hri_pm_get_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CPUSEL.reg;
+	tmp = (tmp & PM_CPUSEL_CPUDIV(mask)) >> PM_CPUSEL_CPUDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->CPUSEL.reg;
+	tmp &= ~PM_CPUSEL_CPUDIV_Msk;
+	tmp |= PM_CPUSEL_CPUDIV(data);
+	((Pm *)hw)->CPUSEL.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CPUSEL.reg &= ~PM_CPUSEL_CPUDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CPUSEL.reg ^= PM_CPUSEL_CPUDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_cpusel_reg_t hri_pm_read_CPUSEL_CPUDIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CPUSEL.reg;
+	tmp = (tmp & PM_CPUSEL_CPUDIV_Msk) >> PM_CPUSEL_CPUDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CPUSEL.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_cpusel_reg_t hri_pm_get_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CPUSEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CPUSEL.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CPUSEL.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CPUSEL.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_cpusel_reg_t hri_pm_read_CPUSEL_reg(const void *const hw)
+{
+	return ((Pm *)hw)->CPUSEL.reg;
+}
+
+static inline void hri_pm_set_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBASEL.reg |= PM_APBASEL_APBADIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbasel_reg_t hri_pm_get_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBASEL.reg;
+	tmp = (tmp & PM_APBASEL_APBADIV(mask)) >> PM_APBASEL_APBADIV_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBASEL.reg;
+	tmp &= ~PM_APBASEL_APBADIV_Msk;
+	tmp |= PM_APBASEL_APBADIV(data);
+	((Pm *)hw)->APBASEL.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBASEL.reg &= ~PM_APBASEL_APBADIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBASEL.reg ^= PM_APBASEL_APBADIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbasel_reg_t hri_pm_read_APBASEL_APBADIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBASEL.reg;
+	tmp = (tmp & PM_APBASEL_APBADIV_Msk) >> PM_APBASEL_APBADIV_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBASEL.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbasel_reg_t hri_pm_get_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBASEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBASEL.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBASEL.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBASEL.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbasel_reg_t hri_pm_read_APBASEL_reg(const void *const hw)
+{
+	return ((Pm *)hw)->APBASEL.reg;
+}
+
+static inline void hri_pm_set_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBSEL.reg |= PM_APBBSEL_APBBDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbbsel_reg_t hri_pm_get_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBBSEL.reg;
+	tmp = (tmp & PM_APBBSEL_APBBDIV(mask)) >> PM_APBBSEL_APBBDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBBSEL.reg;
+	tmp &= ~PM_APBBSEL_APBBDIV_Msk;
+	tmp |= PM_APBBSEL_APBBDIV(data);
+	((Pm *)hw)->APBBSEL.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBSEL.reg &= ~PM_APBBSEL_APBBDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBSEL.reg ^= PM_APBBSEL_APBBDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbbsel_reg_t hri_pm_read_APBBSEL_APBBDIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBBSEL.reg;
+	tmp = (tmp & PM_APBBSEL_APBBDIV_Msk) >> PM_APBBSEL_APBBDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBSEL.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbbsel_reg_t hri_pm_get_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBBSEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBSEL.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBSEL.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBSEL.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbbsel_reg_t hri_pm_read_APBBSEL_reg(const void *const hw)
+{
+	return ((Pm *)hw)->APBBSEL.reg;
+}
+
+static inline void hri_pm_set_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCSEL.reg |= PM_APBCSEL_APBCDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbcsel_reg_t hri_pm_get_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBCSEL.reg;
+	tmp = (tmp & PM_APBCSEL_APBCDIV(mask)) >> PM_APBCSEL_APBCDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCSEL.reg;
+	tmp &= ~PM_APBCSEL_APBCDIV_Msk;
+	tmp |= PM_APBCSEL_APBCDIV(data);
+	((Pm *)hw)->APBCSEL.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCSEL.reg &= ~PM_APBCSEL_APBCDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCSEL.reg ^= PM_APBCSEL_APBCDIV(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbcsel_reg_t hri_pm_read_APBCSEL_APBCDIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBCSEL.reg;
+	tmp = (tmp & PM_APBCSEL_APBCDIV_Msk) >> PM_APBCSEL_APBCDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCSEL.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbcsel_reg_t hri_pm_get_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->APBCSEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCSEL.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCSEL.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCSEL.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbcsel_reg_t hri_pm_read_APBCSEL_reg(const void *const hw)
+{
+	return ((Pm *)hw)->APBCSEL.reg;
+}
+
+static inline void hri_pm_set_AHBMASK_HPB0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_AHBMASK_HPB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp = (tmp & PM_AHBMASK_HPB0) >> PM_AHBMASK_HPB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_AHBMASK_HPB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp &= ~PM_AHBMASK_HPB0;
+	tmp |= value << PM_AHBMASK_HPB0_Pos;
+	((Pm *)hw)->AHBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_AHBMASK_HPB0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_AHBMASK_HPB0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_AHBMASK_HPB1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_AHBMASK_HPB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp = (tmp & PM_AHBMASK_HPB1) >> PM_AHBMASK_HPB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_AHBMASK_HPB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp &= ~PM_AHBMASK_HPB1;
+	tmp |= value << PM_AHBMASK_HPB1_Pos;
+	((Pm *)hw)->AHBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_AHBMASK_HPB1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_AHBMASK_HPB1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_AHBMASK_HPB2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_AHBMASK_HPB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp = (tmp & PM_AHBMASK_HPB2) >> PM_AHBMASK_HPB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_AHBMASK_HPB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp &= ~PM_AHBMASK_HPB2;
+	tmp |= value << PM_AHBMASK_HPB2_Pos;
+	((Pm *)hw)->AHBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_AHBMASK_HPB2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_AHBMASK_HPB2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_AHBMASK_DSU_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_DSU;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_AHBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp = (tmp & PM_AHBMASK_DSU) >> PM_AHBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_AHBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp &= ~PM_AHBMASK_DSU;
+	tmp |= value << PM_AHBMASK_DSU_Pos;
+	((Pm *)hw)->AHBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_AHBMASK_DSU_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_DSU;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_AHBMASK_DSU_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_DSU;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_NVMCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp = (tmp & PM_AHBMASK_NVMCTRL) >> PM_AHBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp &= ~PM_AHBMASK_NVMCTRL;
+	tmp |= value << PM_AHBMASK_NVMCTRL_Pos;
+	((Pm *)hw)->AHBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_NVMCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_NVMCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_AHBMASK_DMAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_DMAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_AHBMASK_DMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp = (tmp & PM_AHBMASK_DMAC) >> PM_AHBMASK_DMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_AHBMASK_DMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp &= ~PM_AHBMASK_DMAC;
+	tmp |= value << PM_AHBMASK_DMAC_Pos;
+	((Pm *)hw)->AHBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_AHBMASK_DMAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_DMAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_AHBMASK_DMAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_DMAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_AHBMASK_USB_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_USB;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_AHBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp = (tmp & PM_AHBMASK_USB) >> PM_AHBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_AHBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp &= ~PM_AHBMASK_USB;
+	tmp |= value << PM_AHBMASK_USB_Pos;
+	((Pm *)hw)->AHBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_AHBMASK_USB_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_USB;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_AHBMASK_USB_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_USB;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ahbmask_reg_t hri_pm_get_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->AHBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->AHBMASK.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ahbmask_reg_t hri_pm_read_AHBMASK_reg(const void *const hw)
+{
+	return ((Pm *)hw)->AHBMASK.reg;
+}
+
+static inline void hri_pm_set_APBAMASK_PAC0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_PAC0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBAMASK_PAC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp = (tmp & PM_APBAMASK_PAC0) >> PM_APBAMASK_PAC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBAMASK_PAC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp &= ~PM_APBAMASK_PAC0;
+	tmp |= value << PM_APBAMASK_PAC0_Pos;
+	((Pm *)hw)->APBAMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBAMASK_PAC0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_PAC0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBAMASK_PAC0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_PAC0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBAMASK_PM_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_PM;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBAMASK_PM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp = (tmp & PM_APBAMASK_PM) >> PM_APBAMASK_PM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBAMASK_PM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp &= ~PM_APBAMASK_PM;
+	tmp |= value << PM_APBAMASK_PM_Pos;
+	((Pm *)hw)->APBAMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBAMASK_PM_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_PM;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBAMASK_PM_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_PM;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBAMASK_SYSCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_SYSCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBAMASK_SYSCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp = (tmp & PM_APBAMASK_SYSCTRL) >> PM_APBAMASK_SYSCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBAMASK_SYSCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp &= ~PM_APBAMASK_SYSCTRL;
+	tmp |= value << PM_APBAMASK_SYSCTRL_Pos;
+	((Pm *)hw)->APBAMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBAMASK_SYSCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_SYSCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBAMASK_SYSCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_SYSCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBAMASK_GCLK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_GCLK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBAMASK_GCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp = (tmp & PM_APBAMASK_GCLK) >> PM_APBAMASK_GCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBAMASK_GCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp &= ~PM_APBAMASK_GCLK;
+	tmp |= value << PM_APBAMASK_GCLK_Pos;
+	((Pm *)hw)->APBAMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBAMASK_GCLK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_GCLK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBAMASK_GCLK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_GCLK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBAMASK_WDT_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_WDT;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBAMASK_WDT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp = (tmp & PM_APBAMASK_WDT) >> PM_APBAMASK_WDT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBAMASK_WDT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp &= ~PM_APBAMASK_WDT;
+	tmp |= value << PM_APBAMASK_WDT_Pos;
+	((Pm *)hw)->APBAMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBAMASK_WDT_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_WDT;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBAMASK_WDT_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_WDT;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBAMASK_RTC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_RTC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBAMASK_RTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp = (tmp & PM_APBAMASK_RTC) >> PM_APBAMASK_RTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBAMASK_RTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp &= ~PM_APBAMASK_RTC;
+	tmp |= value << PM_APBAMASK_RTC_Pos;
+	((Pm *)hw)->APBAMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBAMASK_RTC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_RTC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBAMASK_RTC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_RTC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBAMASK_EIC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_EIC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBAMASK_EIC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp = (tmp & PM_APBAMASK_EIC) >> PM_APBAMASK_EIC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBAMASK_EIC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp &= ~PM_APBAMASK_EIC;
+	tmp |= value << PM_APBAMASK_EIC_Pos;
+	((Pm *)hw)->APBAMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBAMASK_EIC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_EIC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBAMASK_EIC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_EIC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbamask_reg_t hri_pm_get_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBAMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBAMASK.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbamask_reg_t hri_pm_read_APBAMASK_reg(const void *const hw)
+{
+	return ((Pm *)hw)->APBAMASK.reg;
+}
+
+static inline void hri_pm_set_APBBMASK_PAC1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_PAC1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBBMASK_PAC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp = (tmp & PM_APBBMASK_PAC1) >> PM_APBBMASK_PAC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBBMASK_PAC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp &= ~PM_APBBMASK_PAC1;
+	tmp |= value << PM_APBBMASK_PAC1_Pos;
+	((Pm *)hw)->APBBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBMASK_PAC1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_PAC1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBMASK_PAC1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_PAC1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBBMASK_DSU_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_DSU;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp = (tmp & PM_APBBMASK_DSU) >> PM_APBBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp &= ~PM_APBBMASK_DSU;
+	tmp |= value << PM_APBBMASK_DSU_Pos;
+	((Pm *)hw)->APBBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBMASK_DSU_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_DSU;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBMASK_DSU_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_DSU;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_NVMCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp = (tmp & PM_APBBMASK_NVMCTRL) >> PM_APBBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp &= ~PM_APBBMASK_NVMCTRL;
+	tmp |= value << PM_APBBMASK_NVMCTRL_Pos;
+	((Pm *)hw)->APBBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_NVMCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_NVMCTRL;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBBMASK_PORT_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_PORT;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBBMASK_PORT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp = (tmp & PM_APBBMASK_PORT) >> PM_APBBMASK_PORT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBBMASK_PORT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp &= ~PM_APBBMASK_PORT;
+	tmp |= value << PM_APBBMASK_PORT_Pos;
+	((Pm *)hw)->APBBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBMASK_PORT_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_PORT;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBMASK_PORT_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_PORT;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBBMASK_DMAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_DMAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBBMASK_DMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp = (tmp & PM_APBBMASK_DMAC) >> PM_APBBMASK_DMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBBMASK_DMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp &= ~PM_APBBMASK_DMAC;
+	tmp |= value << PM_APBBMASK_DMAC_Pos;
+	((Pm *)hw)->APBBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBMASK_DMAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_DMAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBMASK_DMAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_DMAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBBMASK_USB_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_USB;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp = (tmp & PM_APBBMASK_USB) >> PM_APBBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp &= ~PM_APBBMASK_USB;
+	tmp |= value << PM_APBBMASK_USB_Pos;
+	((Pm *)hw)->APBBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBMASK_USB_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_USB;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBMASK_USB_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_USB;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_HMATRIX;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp = (tmp & PM_APBBMASK_HMATRIX) >> PM_APBBMASK_HMATRIX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp &= ~PM_APBBMASK_HMATRIX;
+	tmp |= value << PM_APBBMASK_HMATRIX_Pos;
+	((Pm *)hw)->APBBMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_HMATRIX;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_HMATRIX;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbbmask_reg_t hri_pm_get_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBBMASK.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbbmask_reg_t hri_pm_read_APBBMASK_reg(const void *const hw)
+{
+	return ((Pm *)hw)->APBBMASK.reg;
+}
+
+static inline void hri_pm_set_APBCMASK_PAC2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_PAC2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_PAC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_PAC2) >> PM_APBCMASK_PAC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_PAC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_PAC2;
+	tmp |= value << PM_APBCMASK_PAC2_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_PAC2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_PAC2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_PAC2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_PAC2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_EVSYS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_EVSYS) >> PM_APBCMASK_EVSYS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_EVSYS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_EVSYS;
+	tmp |= value << PM_APBCMASK_EVSYS_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_EVSYS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_EVSYS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_SERCOM0) >> PM_APBCMASK_SERCOM0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_SERCOM0;
+	tmp |= value << PM_APBCMASK_SERCOM0_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_SERCOM1) >> PM_APBCMASK_SERCOM1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_SERCOM1;
+	tmp |= value << PM_APBCMASK_SERCOM1_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_SERCOM2) >> PM_APBCMASK_SERCOM2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_SERCOM2;
+	tmp |= value << PM_APBCMASK_SERCOM2_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM3;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_SERCOM3) >> PM_APBCMASK_SERCOM3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_SERCOM3;
+	tmp |= value << PM_APBCMASK_SERCOM3_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM3;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM3;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM4;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_SERCOM4) >> PM_APBCMASK_SERCOM4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_SERCOM4;
+	tmp |= value << PM_APBCMASK_SERCOM4_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM4;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM4;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM5;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_SERCOM5) >> PM_APBCMASK_SERCOM5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_SERCOM5;
+	tmp |= value << PM_APBCMASK_SERCOM5_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM5;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM5;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_TCC0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_TCC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_TCC0) >> PM_APBCMASK_TCC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_TCC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_TCC0;
+	tmp |= value << PM_APBCMASK_TCC0_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_TCC0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_TCC0_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC0;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_TCC1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_TCC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_TCC1) >> PM_APBCMASK_TCC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_TCC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_TCC1;
+	tmp |= value << PM_APBCMASK_TCC1_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_TCC1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_TCC1_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC1;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_TCC2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_TCC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_TCC2) >> PM_APBCMASK_TCC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_TCC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_TCC2;
+	tmp |= value << PM_APBCMASK_TCC2_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_TCC2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_TCC2_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC2;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_TC3_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC3;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_TC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_TC3) >> PM_APBCMASK_TC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_TC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_TC3;
+	tmp |= value << PM_APBCMASK_TC3_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_TC3_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC3;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_TC3_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC3;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_TC4_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC4;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_TC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_TC4) >> PM_APBCMASK_TC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_TC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_TC4;
+	tmp |= value << PM_APBCMASK_TC4_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_TC4_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC4;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_TC4_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC4;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_TC5_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC5;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_TC5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_TC5) >> PM_APBCMASK_TC5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_TC5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_TC5;
+	tmp |= value << PM_APBCMASK_TC5_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_TC5_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC5;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_TC5_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC5;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_TC6_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC6;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_TC6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_TC6) >> PM_APBCMASK_TC6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_TC6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_TC6;
+	tmp |= value << PM_APBCMASK_TC6_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_TC6_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC6;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_TC6_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC6;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_TC7_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC7;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_TC7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_TC7) >> PM_APBCMASK_TC7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_TC7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_TC7;
+	tmp |= value << PM_APBCMASK_TC7_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_TC7_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC7;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_TC7_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC7;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_ADC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_ADC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_ADC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_ADC) >> PM_APBCMASK_ADC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_ADC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_ADC;
+	tmp |= value << PM_APBCMASK_ADC_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_ADC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_ADC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_ADC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_ADC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_AC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_AC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_AC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_AC) >> PM_APBCMASK_AC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_AC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_AC;
+	tmp |= value << PM_APBCMASK_AC_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_AC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_AC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_AC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_AC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_DAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_DAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_DAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_DAC) >> PM_APBCMASK_DAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_DAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_DAC;
+	tmp |= value << PM_APBCMASK_DAC_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_DAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_DAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_DAC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_DAC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_PTC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_PTC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_PTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_PTC) >> PM_APBCMASK_PTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_PTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_PTC;
+	tmp |= value << PM_APBCMASK_PTC_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_PTC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_PTC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_PTC_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_PTC;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_I2S_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_I2S;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_APBCMASK_I2S_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp = (tmp & PM_APBCMASK_I2S) >> PM_APBCMASK_I2S_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_I2S_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= ~PM_APBCMASK_I2S;
+	tmp |= value << PM_APBCMASK_I2S_Pos;
+	((Pm *)hw)->APBCMASK.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_I2S_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_I2S;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_I2S_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_I2S;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbcmask_reg_t hri_pm_get_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pm *)hw)->APBCMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->APBCMASK.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_apbcmask_reg_t hri_pm_read_APBCMASK_reg(const void *const hw)
+{
+	return ((Pm *)hw)->APBCMASK.reg;
+}
+
+static inline bool hri_pm_get_RCAUSE_POR_bit(const void *const hw)
+{
+	return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_POR) >> PM_RCAUSE_POR_Pos;
+}
+
+static inline bool hri_pm_get_RCAUSE_BOD12_bit(const void *const hw)
+{
+	return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_BOD12) >> PM_RCAUSE_BOD12_Pos;
+}
+
+static inline bool hri_pm_get_RCAUSE_BOD33_bit(const void *const hw)
+{
+	return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_BOD33) >> PM_RCAUSE_BOD33_Pos;
+}
+
+static inline bool hri_pm_get_RCAUSE_EXT_bit(const void *const hw)
+{
+	return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_EXT) >> PM_RCAUSE_EXT_Pos;
+}
+
+static inline bool hri_pm_get_RCAUSE_WDT_bit(const void *const hw)
+{
+	return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_WDT) >> PM_RCAUSE_WDT_Pos;
+}
+
+static inline bool hri_pm_get_RCAUSE_SYST_bit(const void *const hw)
+{
+	return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_SYST) >> PM_RCAUSE_SYST_Pos;
+}
+
+static inline hri_pm_rcause_reg_t hri_pm_get_RCAUSE_reg(const void *const hw, hri_pm_rcause_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->RCAUSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_rcause_reg_t hri_pm_read_RCAUSE_reg(const void *const hw)
+{
+	return ((Pm *)hw)->RCAUSE.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PM_D21_H_INCLUDED */
+#endif /* _SAMD21_PM_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_port_d21.h b/atmel-samd/asf4/samd21/hri/hri_port_d21.h
new file mode 100644
index 000000000..cf37b2a40
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_port_d21.h
@@ -0,0 +1,1324 @@
+/**
+ * \file
+ *
+ * \brief SAM PORT
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_PORT_COMPONENT_
+#ifndef _HRI_PORT_D21_H_INCLUDED_
+#define _HRI_PORT_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PORT_CRITICAL_SECTIONS)
+#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PORT_CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_port_ctrl_reg_t;
+typedef uint32_t hri_port_dir_reg_t;
+typedef uint32_t hri_port_in_reg_t;
+typedef uint32_t hri_port_out_reg_t;
+typedef uint32_t hri_port_wrconfig_reg_t;
+typedef uint32_t hri_portgroup_ctrl_reg_t;
+typedef uint32_t hri_portgroup_dir_reg_t;
+typedef uint32_t hri_portgroup_in_reg_t;
+typedef uint32_t hri_portgroup_out_reg_t;
+typedef uint32_t hri_portgroup_wrconfig_reg_t;
+typedef uint8_t  hri_port_pincfg_reg_t;
+typedef uint8_t  hri_port_pmux_reg_t;
+typedef uint8_t  hri_portgroup_pincfg_reg_t;
+typedef uint8_t  hri_portgroup_pmux_reg_t;
+
+static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask);
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data);
+	((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data);
+}
+
+static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->DIR.reg;
+}
+
+static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = data;
+	((PortGroup *)hw)->DIRCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = mask;
+}
+
+static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask);
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data);
+	((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data);
+}
+
+static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->OUT.reg;
+}
+
+static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = data;
+	((PortGroup *)hw)->OUTCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = mask;
+}
+
+static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((PortGroup *)hw)->CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->CTRL.reg;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index,
+                                                             hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PMUX[index].reg;
+}
+
+static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index,
+                                                                 hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PINCFG[index].reg;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask)
+{
+	return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw)
+{
+	return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->IN.reg;
+}
+
+static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask);
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data);
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data);
+}
+
+static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].DIR.reg;
+}
+
+static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = data;
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask;
+}
+
+static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask);
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data);
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data);
+}
+
+static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].OUT.reg;
+}
+
+static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = data;
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
+}
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((Port *)hw)->Group[submodule_index].CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].CTRL.reg;
+}
+
+static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                         hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                        hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                            hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+}
+
+static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                  bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                            uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_in_reg_t mask)
+{
+	return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index)
+{
+	return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].IN.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PORT_D21_H_INCLUDED */
+#endif /* _SAMD21_PORT_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h b/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h
new file mode 100644
index 000000000..49808d60a
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h
@@ -0,0 +1,5921 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_RTC_COMPONENT_
+#ifndef _HRI_RTC_D21_H_INCLUDED_
+#define _HRI_RTC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RTC_CRITICAL_SECTIONS)
+#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RTC_CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_rtcmode0_ctrl_reg_t;
+typedef uint16_t hri_rtcmode0_evctrl_reg_t;
+typedef uint16_t hri_rtcmode0_readreq_reg_t;
+typedef uint16_t hri_rtcmode1_comp_reg_t;
+typedef uint16_t hri_rtcmode1_count_reg_t;
+typedef uint16_t hri_rtcmode1_ctrl_reg_t;
+typedef uint16_t hri_rtcmode1_evctrl_reg_t;
+typedef uint16_t hri_rtcmode1_per_reg_t;
+typedef uint16_t hri_rtcmode1_readreq_reg_t;
+typedef uint16_t hri_rtcmode2_ctrl_reg_t;
+typedef uint16_t hri_rtcmode2_evctrl_reg_t;
+typedef uint16_t hri_rtcmode2_readreq_reg_t;
+typedef uint32_t hri_rtcalarm_alarm_reg_t;
+typedef uint32_t hri_rtcmode0_comp_reg_t;
+typedef uint32_t hri_rtcmode0_count_reg_t;
+typedef uint32_t hri_rtcmode2_alarm_reg_t;
+typedef uint32_t hri_rtcmode2_clock_reg_t;
+typedef uint8_t  hri_rtcalarm_mask_reg_t;
+typedef uint8_t  hri_rtcmode0_dbgctrl_reg_t;
+typedef uint8_t  hri_rtcmode0_freqcorr_reg_t;
+typedef uint8_t  hri_rtcmode0_intenset_reg_t;
+typedef uint8_t  hri_rtcmode0_intflag_reg_t;
+typedef uint8_t  hri_rtcmode0_status_reg_t;
+typedef uint8_t  hri_rtcmode1_dbgctrl_reg_t;
+typedef uint8_t  hri_rtcmode1_freqcorr_reg_t;
+typedef uint8_t  hri_rtcmode1_intenset_reg_t;
+typedef uint8_t  hri_rtcmode1_intflag_reg_t;
+typedef uint8_t  hri_rtcmode1_status_reg_t;
+typedef uint8_t  hri_rtcmode2_dbgctrl_reg_t;
+typedef uint8_t  hri_rtcmode2_freqcorr_reg_t;
+typedef uint8_t  hri_rtcmode2_intenset_reg_t;
+typedef uint8_t  hri_rtcmode2_intflag_reg_t;
+typedef uint8_t  hri_rtcmode2_mask_reg_t;
+typedef uint8_t  hri_rtcmode2_status_reg_t;
+
+static inline void hri_rtcmode0_wait_for_sync(const void *const hw)
+{
+	while (((const Rtc *)hw)->MODE0.STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_rtcmode0_is_syncing(const void *const hw)
+{
+	return ((const Rtc *)hw)->MODE0.STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_rtcmode1_wait_for_sync(const void *const hw)
+{
+	while (((const Rtc *)hw)->MODE1.STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_rtcmode1_is_syncing(const void *const hw)
+{
+	return ((const Rtc *)hw)->MODE1.STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_rtcmode2_wait_for_sync(const void *const hw)
+{
+	while (((const Rtc *)hw)->MODE2.STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_rtcmode2_is_syncing(const void *const hw)
+{
+	return ((const Rtc *)hw)->MODE2.STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcalarm_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcalarm_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcalarm_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_SYNCRDY;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_SYNCRDY) >> RTC_MODE2_INTENSET_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_SYNCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_SYNCRDY;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_SYNCRDY;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_SYNCRDY;
+}
+
+static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode2_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTENSET.reg;
+}
+
+static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = data;
+	((Rtc *)hw)->MODE2.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = mask;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_SYNCRDY) >> RTC_MODE2_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_SYNCRDY) >> RTC_MODE2_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode2_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = mask;
+}
+
+static inline void hri_rtcmode2_set_CTRL_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp = (tmp & RTC_MODE2_CTRL_SWRST) >> RTC_MODE2_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp = (tmp & RTC_MODE2_CTRL_ENABLE) >> RTC_MODE2_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp &= ~RTC_MODE2_CTRL_ENABLE;
+	tmp |= value << RTC_MODE2_CTRL_ENABLE_Pos;
+	((Rtc *)hw)->MODE2.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRL_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_CLKREP;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRL_CLKREP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp = (tmp & RTC_MODE2_CTRL_CLKREP) >> RTC_MODE2_CTRL_CLKREP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRL_CLKREP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp &= ~RTC_MODE2_CTRL_CLKREP;
+	tmp |= value << RTC_MODE2_CTRL_CLKREP_Pos;
+	((Rtc *)hw)->MODE2.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRL_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_CLKREP;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRL_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRL_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_MATCHCLR;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRL_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp = (tmp & RTC_MODE2_CTRL_MATCHCLR) >> RTC_MODE2_CTRL_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRL_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp &= ~RTC_MODE2_CTRL_MATCHCLR;
+	tmp |= value << RTC_MODE2_CTRL_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE2.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRL_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_MATCHCLR;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRL_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_MATCHCLR;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp = (tmp & RTC_MODE2_CTRL_MODE(mask)) >> RTC_MODE2_CTRL_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp &= ~RTC_MODE2_CTRL_MODE_Msk;
+	tmp |= RTC_MODE2_CTRL_MODE(data);
+	((Rtc *)hw)->MODE2.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp = (tmp & RTC_MODE2_CTRL_MODE_Msk) >> RTC_MODE2_CTRL_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_PRESCALER_bf(const void *const       hw,
+                                                                         hri_rtcmode2_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp = (tmp & RTC_MODE2_CTRL_PRESCALER(mask)) >> RTC_MODE2_CTRL_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp &= ~RTC_MODE2_CTRL_PRESCALER_Msk;
+	tmp |= RTC_MODE2_CTRL_PRESCALER(data);
+	((Rtc *)hw)->MODE2.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp = (tmp & RTC_MODE2_CTRL_PRESCALER_Msk) >> RTC_MODE2_CTRL_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.CTRL.reg;
+}
+
+static inline void hri_rtcmode2_set_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_READREQ_RCONT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_READREQ_RCONT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.READREQ.reg;
+	tmp &= ~RTC_READREQ_RCONT;
+	tmp |= value << RTC_READREQ_RCONT_Pos;
+	((Rtc *)hw)->MODE2.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_READREQ_RREQ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_READREQ_RREQ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.READREQ.reg;
+	tmp &= ~RTC_READREQ_RREQ;
+	tmp |= value << RTC_READREQ_RREQ_Pos;
+	((Rtc *)hw)->MODE2.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_get_READREQ_ADDR_bf(const void *const          hw,
+                                                                          hri_rtcmode2_readreq_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.READREQ.reg;
+	tmp &= ~RTC_READREQ_ADDR_Msk;
+	tmp |= RTC_READREQ_ADDR(data);
+	((Rtc *)hw)->MODE2.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_read_READREQ_ADDR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_get_READREQ_reg(const void *const          hw,
+                                                                      hri_rtcmode2_readreq_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.READREQ.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.READREQ.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_read_READREQ_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.READREQ.reg;
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode2_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg;
+	tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg;
+	tmp &= ~RTC_DBGCTRL_DBGRUN;
+	tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
+	((Rtc *)hw)->MODE2.DBGCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.DBGCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_get_DBGCTRL_reg(const void *const          hw,
+                                                                      hri_rtcmode2_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.DBGCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.DBGCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.DBGCTRL.reg;
+}
+
+static inline void hri_rtcmode2_set_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_FREQCORR_SIGN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_SIGN;
+	tmp |= value << RTC_FREQCORR_SIGN_Pos;
+	((Rtc *)hw)->MODE2.FREQCORR.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_VALUE_bf(const void *const           hw,
+                                                                             hri_rtcmode2_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_VALUE_Msk;
+	tmp |= RTC_FREQCORR_VALUE(data);
+	((Rtc *)hw)->MODE2.FREQCORR.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_VALUE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.FREQCORR.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_reg(const void *const           hw,
+                                                                        hri_rtcmode2_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.FREQCORR.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.FREQCORR.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.FREQCORR.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.FREQCORR.reg;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk;
+	tmp |= RTC_MODE2_CLOCK_SECOND(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk;
+	tmp |= RTC_MODE2_CLOCK_MINUTE(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk;
+	tmp |= RTC_MODE2_CLOCK_HOUR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const        hw,
+                                                                     hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_DAY_Msk;
+	tmp |= RTC_MODE2_CLOCK_DAY(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const        hw,
+                                                                       hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk;
+	tmp |= RTC_MODE2_CLOCK_MONTH(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk;
+	tmp |= RTC_MODE2_CLOCK_YEAR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode2_wait_for_sync(hw);
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.CLOCK.reg;
+}
+
+static inline bool hri_rtcmode2_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos;
+}
+
+static inline void hri_rtcmode2_clear_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.STATUS.reg = RTC_STATUS_SYNCBUSY;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_status_reg_t hri_rtcmode2_get_STATUS_reg(const void *const         hw,
+                                                                    hri_rtcmode2_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_clear_STATUS_reg(const void *const hw, hri_rtcmode2_status_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.STATUS.reg = mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_status_reg_t hri_rtcmode2_read_STATUS_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.STATUS.reg;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_SYNCRDY;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_SYNCRDY) >> RTC_MODE0_INTENSET_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_SYNCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_SYNCRDY;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_SYNCRDY;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_SYNCRDY;
+}
+
+static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode0_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTENSET.reg;
+}
+
+static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = data;
+	((Rtc *)hw)->MODE0.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = mask;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_SYNCRDY) >> RTC_MODE0_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_SYNCRDY) >> RTC_MODE0_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode0_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = mask;
+}
+
+static inline void hri_rtcmode0_set_CTRL_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp = (tmp & RTC_MODE0_CTRL_SWRST) >> RTC_MODE0_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp = (tmp & RTC_MODE0_CTRL_ENABLE) >> RTC_MODE0_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp &= ~RTC_MODE0_CTRL_ENABLE;
+	tmp |= value << RTC_MODE0_CTRL_ENABLE_Pos;
+	((Rtc *)hw)->MODE0.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRL_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRL_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp = (tmp & RTC_MODE0_CTRL_MATCHCLR) >> RTC_MODE0_CTRL_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRL_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp &= ~RTC_MODE0_CTRL_MATCHCLR;
+	tmp |= value << RTC_MODE0_CTRL_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE0.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRL_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_MATCHCLR;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRL_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_MATCHCLR;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp = (tmp & RTC_MODE0_CTRL_MODE(mask)) >> RTC_MODE0_CTRL_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp &= ~RTC_MODE0_CTRL_MODE_Msk;
+	tmp |= RTC_MODE0_CTRL_MODE(data);
+	((Rtc *)hw)->MODE0.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp = (tmp & RTC_MODE0_CTRL_MODE_Msk) >> RTC_MODE0_CTRL_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_PRESCALER_bf(const void *const       hw,
+                                                                         hri_rtcmode0_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp = (tmp & RTC_MODE0_CTRL_PRESCALER(mask)) >> RTC_MODE0_CTRL_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp &= ~RTC_MODE0_CTRL_PRESCALER_Msk;
+	tmp |= RTC_MODE0_CTRL_PRESCALER(data);
+	((Rtc *)hw)->MODE0.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp = (tmp & RTC_MODE0_CTRL_PRESCALER_Msk) >> RTC_MODE0_CTRL_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.CTRL.reg;
+}
+
+static inline void hri_rtcmode0_set_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_READREQ_RCONT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_READREQ_RCONT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.READREQ.reg;
+	tmp &= ~RTC_READREQ_RCONT;
+	tmp |= value << RTC_READREQ_RCONT_Pos;
+	((Rtc *)hw)->MODE0.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_READREQ_RREQ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_READREQ_RREQ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.READREQ.reg;
+	tmp &= ~RTC_READREQ_RREQ;
+	tmp |= value << RTC_READREQ_RREQ_Pos;
+	((Rtc *)hw)->MODE0.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_get_READREQ_ADDR_bf(const void *const          hw,
+                                                                          hri_rtcmode0_readreq_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.READREQ.reg;
+	tmp &= ~RTC_READREQ_ADDR_Msk;
+	tmp |= RTC_READREQ_ADDR(data);
+	((Rtc *)hw)->MODE0.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_read_READREQ_ADDR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_get_READREQ_reg(const void *const          hw,
+                                                                      hri_rtcmode0_readreq_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.READREQ.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.READREQ.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_read_READREQ_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.READREQ.reg;
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode0_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= ~RTC_DBGCTRL_DBGRUN;
+	tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_get_DBGCTRL_reg(const void *const          hw,
+                                                                      hri_rtcmode0_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+}
+
+static inline void hri_rtcmode0_set_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_FREQCORR_SIGN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_SIGN;
+	tmp |= value << RTC_FREQCORR_SIGN_Pos;
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_VALUE_bf(const void *const           hw,
+                                                                             hri_rtcmode0_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_VALUE_Msk;
+	tmp |= RTC_FREQCORR_VALUE(data);
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_VALUE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_reg(const void *const           hw,
+                                                                        hri_rtcmode0_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.FREQCORR.reg;
+}
+
+static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= ~RTC_MODE0_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE0_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE0.COUNT.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.COUNT.reg;
+}
+
+static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= ~RTC_MODE0_COMP_COMP_Msk;
+	tmp |= RTC_MODE0_COMP_COMP(data);
+	((Rtc *)hw)->MODE0.COMP[index].reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode0_wait_for_sync(hw);
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	return ((Rtc *)hw)->MODE0.COMP[index].reg;
+}
+
+static inline bool hri_rtcmode0_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos;
+}
+
+static inline void hri_rtcmode0_clear_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.STATUS.reg = RTC_STATUS_SYNCBUSY;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_status_reg_t hri_rtcmode0_get_STATUS_reg(const void *const         hw,
+                                                                    hri_rtcmode0_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_clear_STATUS_reg(const void *const hw, hri_rtcmode0_status_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.STATUS.reg = mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_status_reg_t hri_rtcmode0_read_STATUS_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.STATUS.reg;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_SYNCRDY;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_SYNCRDY) >> RTC_MODE1_INTENSET_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_SYNCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_SYNCRDY;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_SYNCRDY;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_SYNCRDY;
+}
+
+static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode1_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTENSET.reg;
+}
+
+static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = data;
+	((Rtc *)hw)->MODE1.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = mask;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_SYNCRDY) >> RTC_MODE1_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_SYNCRDY) >> RTC_MODE1_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode1_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = mask;
+}
+
+static inline void hri_rtcmode1_set_CTRL_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_SWRST;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp = (tmp & RTC_MODE1_CTRL_SWRST) >> RTC_MODE1_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp = (tmp & RTC_MODE1_CTRL_ENABLE) >> RTC_MODE1_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp &= ~RTC_MODE1_CTRL_ENABLE;
+	tmp |= value << RTC_MODE1_CTRL_ENABLE_Pos;
+	((Rtc *)hw)->MODE1.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_ENABLE;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp = (tmp & RTC_MODE1_CTRL_MODE(mask)) >> RTC_MODE1_CTRL_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp &= ~RTC_MODE1_CTRL_MODE_Msk;
+	tmp |= RTC_MODE1_CTRL_MODE(data);
+	((Rtc *)hw)->MODE1.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_MODE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp = (tmp & RTC_MODE1_CTRL_MODE_Msk) >> RTC_MODE1_CTRL_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_PRESCALER_bf(const void *const       hw,
+                                                                         hri_rtcmode1_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp = (tmp & RTC_MODE1_CTRL_PRESCALER(mask)) >> RTC_MODE1_CTRL_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp &= ~RTC_MODE1_CTRL_PRESCALER_Msk;
+	tmp |= RTC_MODE1_CTRL_PRESCALER(data);
+	((Rtc *)hw)->MODE1.CTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_PRESCALER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp = (tmp & RTC_MODE1_CTRL_PRESCALER_Msk) >> RTC_MODE1_CTRL_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.CTRL.reg;
+}
+
+static inline void hri_rtcmode1_set_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_READREQ_RCONT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_READREQ_RCONT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.READREQ.reg;
+	tmp &= ~RTC_READREQ_RCONT;
+	tmp |= value << RTC_READREQ_RCONT_Pos;
+	((Rtc *)hw)->MODE1.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_READREQ_RCONT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_RCONT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_READREQ_RREQ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_READREQ_RREQ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.READREQ.reg;
+	tmp &= ~RTC_READREQ_RREQ;
+	tmp |= value << RTC_READREQ_RREQ_Pos;
+	((Rtc *)hw)->MODE1.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_READREQ_RREQ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_RREQ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_get_READREQ_ADDR_bf(const void *const          hw,
+                                                                          hri_rtcmode1_readreq_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.READREQ.reg;
+	tmp &= ~RTC_READREQ_ADDR_Msk;
+	tmp |= RTC_READREQ_ADDR(data);
+	((Rtc *)hw)->MODE1.READREQ.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_ADDR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_read_READREQ_ADDR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.READREQ.reg;
+	tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_get_READREQ_reg(const void *const          hw,
+                                                                      hri_rtcmode1_readreq_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.READREQ.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.READREQ.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_read_READREQ_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.READREQ.reg;
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode1_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg;
+	tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg;
+	tmp &= ~RTC_DBGCTRL_DBGRUN;
+	tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
+	((Rtc *)hw)->MODE1.DBGCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.DBGCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_get_DBGCTRL_reg(const void *const          hw,
+                                                                      hri_rtcmode1_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.DBGCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.DBGCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.DBGCTRL.reg;
+}
+
+static inline void hri_rtcmode1_set_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_FREQCORR_SIGN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_SIGN;
+	tmp |= value << RTC_FREQCORR_SIGN_Pos;
+	((Rtc *)hw)->MODE1.FREQCORR.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_VALUE_bf(const void *const           hw,
+                                                                             hri_rtcmode1_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_VALUE_Msk;
+	tmp |= RTC_FREQCORR_VALUE(data);
+	((Rtc *)hw)->MODE1.FREQCORR.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_VALUE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.FREQCORR.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_reg(const void *const           hw,
+                                                                        hri_rtcmode1_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.FREQCORR.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.FREQCORR.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.FREQCORR.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.FREQCORR.reg;
+}
+
+static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= ~RTC_MODE1_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE1_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE1.COUNT.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.COUNT.reg;
+}
+
+static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= ~RTC_MODE1_PER_PER_Msk;
+	tmp |= RTC_MODE1_PER_PER(data);
+	((Rtc *)hw)->MODE1.PER.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.PER.reg;
+}
+
+static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= ~RTC_MODE1_COMP_COMP_Msk;
+	tmp |= RTC_MODE1_COMP_COMP(data);
+	((Rtc *)hw)->MODE1.COMP[index].reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	hri_rtcmode1_wait_for_sync(hw);
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw);
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	return ((Rtc *)hw)->MODE1.COMP[index].reg;
+}
+
+static inline bool hri_rtcmode1_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos;
+}
+
+static inline void hri_rtcmode1_clear_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.STATUS.reg = RTC_STATUS_SYNCBUSY;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_status_reg_t hri_rtcmode1_get_STATUS_reg(const void *const         hw,
+                                                                    hri_rtcmode1_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_clear_STATUS_reg(const void *const hw, hri_rtcmode1_status_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.STATUS.reg = mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_status_reg_t hri_rtcmode1_read_STATUS_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RTC_D21_H_INCLUDED */
+#endif /* _SAMD21_RTC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h b/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h
new file mode 100644
index 000000000..52b72b7ba
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h
@@ -0,0 +1,7188 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_SERCOM_COMPONENT_
+#ifndef _HRI_SERCOM_D21_H_INCLUDED_
+#define _HRI_SERCOM_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS)
+#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SERCOM_CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sercomi2cm_status_reg_t;
+typedef uint16_t hri_sercomi2cs_status_reg_t;
+typedef uint16_t hri_sercomspi_status_reg_t;
+typedef uint16_t hri_sercomusart_baud_reg_t;
+typedef uint16_t hri_sercomusart_data_reg_t;
+typedef uint16_t hri_sercomusart_status_reg_t;
+typedef uint32_t hri_sercomi2cm_addr_reg_t;
+typedef uint32_t hri_sercomi2cm_baud_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cm_syncbusy_reg_t;
+typedef uint32_t hri_sercomi2cs_addr_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cs_syncbusy_reg_t;
+typedef uint32_t hri_sercomspi_addr_reg_t;
+typedef uint32_t hri_sercomspi_ctrla_reg_t;
+typedef uint32_t hri_sercomspi_ctrlb_reg_t;
+typedef uint32_t hri_sercomspi_data_reg_t;
+typedef uint32_t hri_sercomspi_syncbusy_reg_t;
+typedef uint32_t hri_sercomusart_ctrla_reg_t;
+typedef uint32_t hri_sercomusart_ctrlb_reg_t;
+typedef uint32_t hri_sercomusart_syncbusy_reg_t;
+typedef uint8_t  hri_sercomi2cm_data_reg_t;
+typedef uint8_t  hri_sercomi2cm_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomi2cm_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cm_intflag_reg_t;
+typedef uint8_t  hri_sercomi2cs_data_reg_t;
+typedef uint8_t  hri_sercomi2cs_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cs_intflag_reg_t;
+typedef uint8_t  hri_sercomspi_baud_reg_t;
+typedef uint8_t  hri_sercomspi_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomspi_intenset_reg_t;
+typedef uint8_t  hri_sercomspi_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomusart_intenset_reg_t;
+typedef uint8_t  hri_sercomusart_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_rxpl_reg_t;
+
+static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = mask;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const            hw,
+                                                                       hri_sercomspi_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTENSET.reg;
+}
+
+static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = data;
+	((Sercom *)hw)->SPI.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_sercomspi_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTFLAG.reg;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_ENABLE;
+	tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_IBON;
+	tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPHA;
+	tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPOL;
+	tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DORD;
+	tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk;
+	tmp |= SERCOM_SPI_CTRLA_MODE(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DOPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DIPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk;
+	tmp |= SERCOM_SPI_CTRLA_FORM(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.CTRLA.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_SSDE;
+	tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_MSSEN;
+	tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_RXEN;
+	tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const         hw,
+                                                                          hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const         hw,
+                                                                         hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_AMODE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.CTRLB.reg;
+}
+
+static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const        hw,
+                                                                      hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk;
+	tmp |= SERCOM_SPI_BAUD_BAUD(data);
+	((Sercom *)hw)->SPI.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.BAUD.reg;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDR(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const        hw,
+                                                                          hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.ADDR.reg;
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DATA.reg;
+}
+
+static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->SPI.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const           hw,
+                                                                        hri_sercomspi_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DBGCTRL.reg;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const            hw,
+                                                                          hri_sercomspi_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const          hw,
+                                                                      hri_sercomspi_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = data;
+	((Sercom *)hw)->I2CM.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSERR;
+	tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_ARBLOST;
+	tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_RXNACK;
+	tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD;
+	tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LENERR;
+	tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const           hw,
+                                                                                hri_sercomi2cm_status_reg_t mask)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk;
+	tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data);
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cm_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.STATUS.reg |= mask;
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.STATUS.reg = data;
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.STATUS.reg ^= mask;
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const          hw,
+                                                                              hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_QCEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CM_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const         hw,
+                                                                           hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const         hw,
+                                                                          hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const         hw,
+                                                                             hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.BAUD.reg;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LENEN;
+	tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_HS;
+	tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CM_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const         hw,
+                                                                       hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk;
+	tmp |= SERCOM_I2CM_ADDR_LEN(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.DATA.reg;
+}
+
+static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const          hw,
+                                                                          hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD(mask)) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRAC_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_FRAC_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD_Msk) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const          hw,
+                                                                             hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRAC_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const          hw,
+                                                                                 hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD(mask)) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRACFP_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_FRACFP_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD_Msk) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRACFP_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_USARTFP_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const          hw,
+                                                                                  hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD(mask)) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_USARTFP_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_USARTFP_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_USARTFP_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_USARTFP_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD_Msk) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const          hw,
+                                                                      hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_reg(const void *const          hw,
+                                                                           hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_reg(const void *const          hw,
+                                                                             hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_reg(const void *const          hw,
+                                                                              hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = mask;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const              hw,
+                                                                           hri_sercomusart_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTENSET.reg;
+}
+
+static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = data;
+	((Sercom *)hw)->USART.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const             hw,
+                                                                            hri_sercomusart_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTFLAG.reg;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_ENABLE;
+	tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_IBON;
+	tmp |= value << SERCOM_USART_CTRLA_IBON_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CMODE;
+	tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CPOL;
+	tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_DORD;
+	tmp |= value << SERCOM_USART_CTRLA_DORD_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_MODE_Msk;
+	tmp |= SERCOM_USART_CTRLA_MODE(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPR(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_TXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_RXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPA(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_FORM_Msk;
+	tmp |= SERCOM_USART_CTRLA_FORM(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.CTRLA.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SBMODE;
+	tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_COLDEN;
+	tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SFDE;
+	tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_ENC;
+	tmp |= value << SERCOM_USART_CTRLB_ENC_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_PMODE;
+	tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_TXEN;
+	tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_RXEN;
+	tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_USART_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.CTRLB.reg;
+}
+
+static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const          hw,
+                                                                          hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= ~SERCOM_USART_RXPL_RXPL_Msk;
+	tmp |= SERCOM_USART_RXPL_RXPL(data);
+	((Sercom *)hw)->USART.RXPL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const          hw,
+                                                                      hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.RXPL.reg;
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DATA.reg;
+}
+
+static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->USART.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const             hw,
+                                                                            hri_sercomusart_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DBGCTRL.reg;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const              hw,
+                                                                              hri_sercomusart_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const            hw,
+                                                                          hri_sercomusart_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.STATUS.reg;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cs_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = data;
+	((Sercom *)hw)->I2CS.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cs_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_GCMD;
+	tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_AMODE(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_GENCEN;
+	tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const         hw,
+                                                                            hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.ADDR.reg;
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.DATA.reg;
+}
+
+static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cs_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SERCOM_D21_H_INCLUDED */
+#endif /* _SAMD21_SERCOM_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h b/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h
new file mode 100644
index 000000000..879a2f939
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h
@@ -0,0 +1,4760 @@
+/**
+ * \file
+ *
+ * \brief SAM SYSCTRL
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_SYSCTRL_COMPONENT_
+#ifndef _HRI_SYSCTRL_D21_H_INCLUDED_
+#define _HRI_SYSCTRL_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SYSCTRL_CRITICAL_SECTIONS)
+#define SYSCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SYSCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SYSCTRL_CRITICAL_SECTION_ENTER()
+#define SYSCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sysctrl_dfllctrl_reg_t;
+typedef uint16_t hri_sysctrl_vreg_reg_t;
+typedef uint16_t hri_sysctrl_xosc32k_reg_t;
+typedef uint16_t hri_sysctrl_xosc_reg_t;
+typedef uint32_t hri_sysctrl_bod33_reg_t;
+typedef uint32_t hri_sysctrl_dfllmul_reg_t;
+typedef uint32_t hri_sysctrl_dfllval_reg_t;
+typedef uint32_t hri_sysctrl_dpllctrlb_reg_t;
+typedef uint32_t hri_sysctrl_dpllratio_reg_t;
+typedef uint32_t hri_sysctrl_intenset_reg_t;
+typedef uint32_t hri_sysctrl_intflag_reg_t;
+typedef uint32_t hri_sysctrl_osc32k_reg_t;
+typedef uint32_t hri_sysctrl_osc8m_reg_t;
+typedef uint32_t hri_sysctrl_pclksr_reg_t;
+typedef uint32_t hri_sysctrl_vref_reg_t;
+typedef uint8_t  hri_sysctrl_dfllsync_reg_t;
+typedef uint8_t  hri_sysctrl_dpllctrla_reg_t;
+typedef uint8_t  hri_sysctrl_dpllstatus_reg_t;
+typedef uint8_t  hri_sysctrl_osculp32k_reg_t;
+
+static inline void hri_sysctrl_set_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSCRDY;
+}
+
+static inline bool hri_sysctrl_get_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_XOSCRDY) >> SYSCTRL_INTENSET_XOSCRDY_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSCRDY;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSCRDY;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSCRDY;
+}
+
+static inline void hri_sysctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline bool hri_sysctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_XOSC32KRDY) >> SYSCTRL_INTENSET_XOSC32KRDY_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSC32KRDY;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSC32KRDY;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline void hri_sysctrl_set_INTEN_OSC32KRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC32KRDY;
+}
+
+static inline bool hri_sysctrl_get_INTEN_OSC32KRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_OSC32KRDY) >> SYSCTRL_INTENSET_OSC32KRDY_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_OSC32KRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC32KRDY;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC32KRDY;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_OSC32KRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC32KRDY;
+}
+
+static inline void hri_sysctrl_set_INTEN_OSC8MRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC8MRDY;
+}
+
+static inline bool hri_sysctrl_get_INTEN_OSC8MRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_OSC8MRDY) >> SYSCTRL_INTENSET_OSC8MRDY_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_OSC8MRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC8MRDY;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC8MRDY;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_OSC8MRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC8MRDY;
+}
+
+static inline void hri_sysctrl_set_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRDY;
+}
+
+static inline bool hri_sysctrl_get_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLRDY) >> SYSCTRL_INTENSET_DFLLRDY_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRDY;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRDY;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRDY;
+}
+
+static inline void hri_sysctrl_set_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLOOB;
+}
+
+static inline bool hri_sysctrl_get_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLOOB) >> SYSCTRL_INTENSET_DFLLOOB_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLOOB;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLOOB;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLOOB;
+}
+
+static inline void hri_sysctrl_set_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline bool hri_sysctrl_get_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLLCKF) >> SYSCTRL_INTENSET_DFLLLCKF_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKF;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKF;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline void hri_sysctrl_set_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline bool hri_sysctrl_get_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLLCKC) >> SYSCTRL_INTENSET_DFLLLCKC_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKC;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKC;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline void hri_sysctrl_set_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRCS;
+}
+
+static inline bool hri_sysctrl_get_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLRCS) >> SYSCTRL_INTENSET_DFLLRCS_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRCS;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRCS;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRCS;
+}
+
+static inline void hri_sysctrl_set_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33RDY;
+}
+
+static inline bool hri_sysctrl_get_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_BOD33RDY) >> SYSCTRL_INTENSET_BOD33RDY_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_BOD33RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33RDY;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33RDY;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33RDY;
+}
+
+static inline void hri_sysctrl_set_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33DET;
+}
+
+static inline bool hri_sysctrl_get_INTEN_BOD33DET_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_BOD33DET) >> SYSCTRL_INTENSET_BOD33DET_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_BOD33DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33DET;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33DET;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33DET;
+}
+
+static inline void hri_sysctrl_set_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_B33SRDY;
+}
+
+static inline bool hri_sysctrl_get_INTEN_B33SRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_B33SRDY) >> SYSCTRL_INTENSET_B33SRDY_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_B33SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_B33SRDY;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_B33SRDY;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_B33SRDY;
+}
+
+static inline void hri_sysctrl_set_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKR;
+}
+
+static inline bool hri_sysctrl_get_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLCKR) >> SYSCTRL_INTENSET_DPLLLCKR_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKR;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKR;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKR;
+}
+
+static inline void hri_sysctrl_set_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKF;
+}
+
+static inline bool hri_sysctrl_get_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLCKF) >> SYSCTRL_INTENSET_DPLLLCKF_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKF;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKF;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKF;
+}
+
+static inline void hri_sysctrl_set_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLTO;
+}
+
+static inline bool hri_sysctrl_get_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLTO) >> SYSCTRL_INTENSET_DPLLLTO_Pos;
+}
+
+static inline void hri_sysctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLTO;
+	} else {
+		((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLTO;
+	}
+}
+
+static inline void hri_sysctrl_clear_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLTO;
+}
+
+static inline void hri_sysctrl_set_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t mask)
+{
+	((Sysctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_sysctrl_intenset_reg_t hri_sysctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_sysctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sysctrl_intenset_reg_t hri_sysctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_sysctrl_write_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t data)
+{
+	((Sysctrl *)hw)->INTENSET.reg = data;
+	((Sysctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_sysctrl_clear_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t mask)
+{
+	((Sysctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSCRDY) >> SYSCTRL_INTFLAG_XOSCRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSCRDY;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSC32KRDY) >> SYSCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_OSC32KRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC32KRDY) >> SYSCTRL_INTFLAG_OSC32KRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_OSC32KRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC32KRDY;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_OSC8MRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC8MRDY) >> SYSCTRL_INTFLAG_OSC8MRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_OSC8MRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC8MRDY;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRDY) >> SYSCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLOOB) >> SYSCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKF) >> SYSCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKC) >> SYSCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRCS) >> SYSCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33RDY) >> SYSCTRL_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33DET) >> SYSCTRL_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_B33SRDY) >> SYSCTRL_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKR) >> SYSCTRL_INTFLAG_DPLLLCKR_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKR;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKF) >> SYSCTRL_INTFLAG_DPLLLCKF_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKF;
+}
+
+static inline bool hri_sysctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLTO) >> SYSCTRL_INTFLAG_DPLLLTO_Pos;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLTO;
+}
+
+static inline bool hri_sysctrl_get_interrupt_XOSCRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSCRDY) >> SYSCTRL_INTFLAG_XOSCRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_XOSCRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSCRDY;
+}
+
+static inline bool hri_sysctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSC32KRDY) >> SYSCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_sysctrl_get_interrupt_OSC32KRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC32KRDY) >> SYSCTRL_INTFLAG_OSC32KRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_OSC32KRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC32KRDY;
+}
+
+static inline bool hri_sysctrl_get_interrupt_OSC8MRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC8MRDY) >> SYSCTRL_INTFLAG_OSC8MRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_OSC8MRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC8MRDY;
+}
+
+static inline bool hri_sysctrl_get_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRDY) >> SYSCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_sysctrl_get_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLOOB) >> SYSCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_sysctrl_get_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKF) >> SYSCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_sysctrl_get_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKC) >> SYSCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_sysctrl_get_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRCS) >> SYSCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_sysctrl_get_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33RDY) >> SYSCTRL_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_sysctrl_get_interrupt_BOD33DET_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33DET) >> SYSCTRL_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_BOD33DET_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_sysctrl_get_interrupt_B33SRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_B33SRDY) >> SYSCTRL_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_B33SRDY_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_sysctrl_get_interrupt_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKR) >> SYSCTRL_INTFLAG_DPLLLCKR_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKR;
+}
+
+static inline bool hri_sysctrl_get_interrupt_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKF) >> SYSCTRL_INTFLAG_DPLLLCKF_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKF;
+}
+
+static inline bool hri_sysctrl_get_interrupt_DPLLLTO_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLTO) >> SYSCTRL_INTFLAG_DPLLLTO_Pos;
+}
+
+static inline void hri_sysctrl_clear_interrupt_DPLLLTO_bit(const void *const hw)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLTO;
+}
+
+static inline hri_sysctrl_intflag_reg_t hri_sysctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_sysctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sysctrl_intflag_reg_t hri_sysctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_sysctrl_clear_INTFLAG_reg(const void *const hw, hri_sysctrl_intflag_reg_t mask)
+{
+	((Sysctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_sysctrl_set_XOSC_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_ENABLE) >> SYSCTRL_XOSC_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp &= ~SYSCTRL_XOSC_ENABLE;
+	tmp |= value << SYSCTRL_XOSC_ENABLE_Pos;
+	((Sysctrl *)hw)->XOSC.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC_XTALEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_XTALEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_XTALEN) >> SYSCTRL_XOSC_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp &= ~SYSCTRL_XOSC_XTALEN;
+	tmp |= value << SYSCTRL_XOSC_XTALEN_Pos;
+	((Sysctrl *)hw)->XOSC.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC_XTALEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_XTALEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC_XTALEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_XTALEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_RUNSTDBY) >> SYSCTRL_XOSC_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp &= ~SYSCTRL_XOSC_RUNSTDBY;
+	tmp |= value << SYSCTRL_XOSC_RUNSTDBY_Pos;
+	((Sysctrl *)hw)->XOSC.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_ONDEMAND) >> SYSCTRL_XOSC_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp &= ~SYSCTRL_XOSC_ONDEMAND;
+	tmp |= value << SYSCTRL_XOSC_ONDEMAND_Pos;
+	((Sysctrl *)hw)->XOSC.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC_AMPGC_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_AMPGC;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC_AMPGC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_AMPGC) >> SYSCTRL_XOSC_AMPGC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC_AMPGC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp &= ~SYSCTRL_XOSC_AMPGC;
+	tmp |= value << SYSCTRL_XOSC_AMPGC_Pos;
+	((Sysctrl *)hw)->XOSC.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC_AMPGC_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_AMPGC;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC_AMPGC_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_AMPGC;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_GAIN(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_GAIN(mask)) >> SYSCTRL_XOSC_GAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t data)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp &= ~SYSCTRL_XOSC_GAIN_Msk;
+	tmp |= SYSCTRL_XOSC_GAIN(data);
+	((Sysctrl *)hw)->XOSC.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_GAIN(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_GAIN(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_GAIN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_GAIN_Msk) >> SYSCTRL_XOSC_GAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_STARTUP(mask)) >> SYSCTRL_XOSC_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t data)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp &= ~SYSCTRL_XOSC_STARTUP_Msk;
+	tmp |= SYSCTRL_XOSC_STARTUP(data);
+	((Sysctrl *)hw)->XOSC.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp = (tmp & SYSCTRL_XOSC_STARTUP_Msk) >> SYSCTRL_XOSC_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->XOSC.reg;
+}
+
+static inline void hri_sysctrl_set_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_ENABLE) >> SYSCTRL_XOSC32K_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_ENABLE;
+	tmp |= value << SYSCTRL_XOSC32K_ENABLE_Pos;
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_XTALEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_XTALEN) >> SYSCTRL_XOSC32K_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_XTALEN;
+	tmp |= value << SYSCTRL_XOSC32K_XTALEN_Pos;
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_XTALEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_XTALEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC32K_EN32K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_EN32K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC32K_EN32K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_EN32K) >> SYSCTRL_XOSC32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_EN32K;
+	tmp |= value << SYSCTRL_XOSC32K_EN32K_Pos;
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_EN32K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_EN32K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_EN32K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_EN32K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC32K_EN1K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_EN1K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC32K_EN1K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_EN1K) >> SYSCTRL_XOSC32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_EN1K;
+	tmp |= value << SYSCTRL_XOSC32K_EN1K_Pos;
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_EN1K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_EN1K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_EN1K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_EN1K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC32K_AAMPEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_AAMPEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC32K_AAMPEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_AAMPEN) >> SYSCTRL_XOSC32K_AAMPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_AAMPEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_AAMPEN;
+	tmp |= value << SYSCTRL_XOSC32K_AAMPEN_Pos;
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_AAMPEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_AAMPEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_AAMPEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_AAMPEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_RUNSTDBY) >> SYSCTRL_XOSC32K_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_RUNSTDBY;
+	tmp |= value << SYSCTRL_XOSC32K_RUNSTDBY_Pos;
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_ONDEMAND) >> SYSCTRL_XOSC32K_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_ONDEMAND;
+	tmp |= value << SYSCTRL_XOSC32K_ONDEMAND_Pos;
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_WRTLOCK) >> SYSCTRL_XOSC32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_WRTLOCK;
+	tmp |= value << SYSCTRL_XOSC32K_WRTLOCK_Pos;
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_get_XOSC32K_STARTUP_bf(const void *const         hw,
+                                                                           hri_sysctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_STARTUP(mask)) >> SYSCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= ~SYSCTRL_XOSC32K_STARTUP_Msk;
+	tmp |= SYSCTRL_XOSC32K_STARTUP(data);
+	((Sysctrl *)hw)->XOSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_read_XOSC32K_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & SYSCTRL_XOSC32K_STARTUP_Msk) >> SYSCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_get_XOSC32K_reg(const void *const         hw,
+                                                                    hri_sysctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->XOSC32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->XOSC32K.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_read_XOSC32K_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->XOSC32K.reg;
+}
+
+static inline void hri_sysctrl_set_OSC32K_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC32K_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_ENABLE) >> SYSCTRL_OSC32K_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= ~SYSCTRL_OSC32K_ENABLE;
+	tmp |= value << SYSCTRL_OSC32K_ENABLE_Pos;
+	((Sysctrl *)hw)->OSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC32K_EN32K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_EN32K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC32K_EN32K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_EN32K) >> SYSCTRL_OSC32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= ~SYSCTRL_OSC32K_EN32K;
+	tmp |= value << SYSCTRL_OSC32K_EN32K_Pos;
+	((Sysctrl *)hw)->OSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_EN32K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_EN32K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_EN32K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_EN32K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC32K_EN1K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_EN1K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC32K_EN1K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_EN1K) >> SYSCTRL_OSC32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= ~SYSCTRL_OSC32K_EN1K;
+	tmp |= value << SYSCTRL_OSC32K_EN1K_Pos;
+	((Sysctrl *)hw)->OSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_EN1K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_EN1K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_EN1K_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_EN1K;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_RUNSTDBY) >> SYSCTRL_OSC32K_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= ~SYSCTRL_OSC32K_RUNSTDBY;
+	tmp |= value << SYSCTRL_OSC32K_RUNSTDBY_Pos;
+	((Sysctrl *)hw)->OSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC32K_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC32K_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_ONDEMAND) >> SYSCTRL_OSC32K_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= ~SYSCTRL_OSC32K_ONDEMAND;
+	tmp |= value << SYSCTRL_OSC32K_ONDEMAND_Pos;
+	((Sysctrl *)hw)->OSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC32K_WRTLOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_WRTLOCK) >> SYSCTRL_OSC32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= ~SYSCTRL_OSC32K_WRTLOCK;
+	tmp |= value << SYSCTRL_OSC32K_WRTLOCK_Pos;
+	((Sysctrl *)hw)->OSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_STARTUP_bf(const void *const        hw,
+                                                                         hri_sysctrl_osc32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_STARTUP(mask)) >> SYSCTRL_OSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= ~SYSCTRL_OSC32K_STARTUP_Msk;
+	tmp |= SYSCTRL_OSC32K_STARTUP(data);
+	((Sysctrl *)hw)->OSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_STARTUP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_STARTUP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_STARTUP_Msk) >> SYSCTRL_OSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_CALIB_bf(const void *const        hw,
+                                                                       hri_sysctrl_osc32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_CALIB(mask)) >> SYSCTRL_OSC32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= ~SYSCTRL_OSC32K_CALIB_Msk;
+	tmp |= SYSCTRL_OSC32K_CALIB(data);
+	((Sysctrl *)hw)->OSC32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp = (tmp & SYSCTRL_OSC32K_CALIB_Msk) >> SYSCTRL_OSC32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC32K.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->OSC32K.reg;
+}
+
+static inline void hri_sysctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg |= SYSCTRL_OSCULP32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & SYSCTRL_OSCULP32K_WRTLOCK) >> SYSCTRL_OSCULP32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~SYSCTRL_OSCULP32K_WRTLOCK;
+	tmp |= value << SYSCTRL_OSCULP32K_WRTLOCK_Pos;
+	((Sysctrl *)hw)->OSCULP32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg &= ~SYSCTRL_OSCULP32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg ^= SYSCTRL_OSCULP32K_WRTLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg |= SYSCTRL_OSCULP32K_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_get_OSCULP32K_CALIB_bf(const void *const           hw,
+                                                                             hri_sysctrl_osculp32k_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & SYSCTRL_OSCULP32K_CALIB(mask)) >> SYSCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t data)
+{
+	uint8_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~SYSCTRL_OSCULP32K_CALIB_Msk;
+	tmp |= SYSCTRL_OSCULP32K_CALIB(data);
+	((Sysctrl *)hw)->OSCULP32K.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg &= ~SYSCTRL_OSCULP32K_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg ^= SYSCTRL_OSCULP32K_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_get_OSCULP32K_reg(const void *const           hw,
+                                                                        hri_sysctrl_osculp32k_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->OSCULP32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSCULP32K.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_read_OSCULP32K_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->OSCULP32K.reg;
+}
+
+static inline void hri_sysctrl_set_OSC8M_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC8M_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_ENABLE) >> SYSCTRL_OSC8M_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC8M_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp &= ~SYSCTRL_OSC8M_ENABLE;
+	tmp |= value << SYSCTRL_OSC8M_ENABLE_Pos;
+	((Sysctrl *)hw)->OSC8M.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC8M_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC8M_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC8M_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC8M_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_RUNSTDBY) >> SYSCTRL_OSC8M_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC8M_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp &= ~SYSCTRL_OSC8M_RUNSTDBY;
+	tmp |= value << SYSCTRL_OSC8M_RUNSTDBY_Pos;
+	((Sysctrl *)hw)->OSC8M.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC8M_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC8M_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC8M_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_OSC8M_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_ONDEMAND) >> SYSCTRL_OSC8M_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_OSC8M_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp &= ~SYSCTRL_OSC8M_ONDEMAND;
+	tmp |= value << SYSCTRL_OSC8M_ONDEMAND_Pos;
+	((Sysctrl *)hw)->OSC8M.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC8M_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC8M_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_PRESC(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_PRESC(mask)) >> SYSCTRL_OSC8M_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp &= ~SYSCTRL_OSC8M_PRESC_Msk;
+	tmp |= SYSCTRL_OSC8M_PRESC(data);
+	((Sysctrl *)hw)->OSC8M.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_PRESC(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_PRESC(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_PRESC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_PRESC_Msk) >> SYSCTRL_OSC8M_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_CALIB(mask)) >> SYSCTRL_OSC8M_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp &= ~SYSCTRL_OSC8M_CALIB_Msk;
+	tmp |= SYSCTRL_OSC8M_CALIB(data);
+	((Sysctrl *)hw)->OSC8M.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_CALIB_Msk) >> SYSCTRL_OSC8M_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_FRANGE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_FRANGE_bf(const void *const       hw,
+                                                                      hri_sysctrl_osc8m_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_FRANGE(mask)) >> SYSCTRL_OSC8M_FRANGE_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp &= ~SYSCTRL_OSC8M_FRANGE_Msk;
+	tmp |= SYSCTRL_OSC8M_FRANGE(data);
+	((Sysctrl *)hw)->OSC8M.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_FRANGE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_FRANGE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_FRANGE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp = (tmp & SYSCTRL_OSC8M_FRANGE_Msk) >> SYSCTRL_OSC8M_FRANGE_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->OSC8M.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->OSC8M.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->OSC8M.reg;
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_ENABLE) >> SYSCTRL_DFLLCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_ENABLE;
+	tmp |= value << SYSCTRL_DFLLCTRL_ENABLE_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_MODE) >> SYSCTRL_DFLLCTRL_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_MODE;
+	tmp |= value << SYSCTRL_DFLLCTRL_MODE_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_MODE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_MODE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_STABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_STABLE) >> SYSCTRL_DFLLCTRL_STABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_STABLE;
+	tmp |= value << SYSCTRL_DFLLCTRL_STABLE_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_STABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_STABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_LLAW;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_LLAW) >> SYSCTRL_DFLLCTRL_LLAW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_LLAW;
+	tmp |= value << SYSCTRL_DFLLCTRL_LLAW_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_LLAW;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_LLAW;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_USBCRM;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_USBCRM) >> SYSCTRL_DFLLCTRL_USBCRM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_USBCRM;
+	tmp |= value << SYSCTRL_DFLLCTRL_USBCRM_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_USBCRM;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_USBCRM;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_RUNSTDBY) >> SYSCTRL_DFLLCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_RUNSTDBY;
+	tmp |= value << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_ONDEMAND) >> SYSCTRL_DFLLCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_ONDEMAND;
+	tmp |= value << SYSCTRL_DFLLCTRL_ONDEMAND_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_CCDIS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_CCDIS) >> SYSCTRL_DFLLCTRL_CCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_CCDIS;
+	tmp |= value << SYSCTRL_DFLLCTRL_CCDIS_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_CCDIS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_CCDIS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_QLDIS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_QLDIS) >> SYSCTRL_DFLLCTRL_QLDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_QLDIS;
+	tmp |= value << SYSCTRL_DFLLCTRL_QLDIS_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_QLDIS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_QLDIS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_BPLCKC;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_BPLCKC) >> SYSCTRL_DFLLCTRL_BPLCKC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_BPLCKC;
+	tmp |= value << SYSCTRL_DFLLCTRL_BPLCKC_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_BPLCKC;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_BPLCKC;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_WAITLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & SYSCTRL_DFLLCTRL_WAITLOCK) >> SYSCTRL_DFLLCTRL_WAITLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~SYSCTRL_DFLLCTRL_WAITLOCK;
+	tmp |= value << SYSCTRL_DFLLCTRL_WAITLOCK_Pos;
+	((Sysctrl *)hw)->DFLLCTRL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_WAITLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_WAITLOCK;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllctrl_reg_t hri_sysctrl_get_DFLLCTRL_reg(const void *const          hw,
+                                                                      hri_sysctrl_dfllctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLCTRL.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllctrl_reg_t hri_sysctrl_read_DFLLCTRL_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->DFLLCTRL.reg;
+}
+
+static inline void hri_sysctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_FINE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_FINE_bf(const void *const         hw,
+                                                                        hri_sysctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & SYSCTRL_DFLLVAL_FINE(mask)) >> SYSCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~SYSCTRL_DFLLVAL_FINE_Msk;
+	tmp |= SYSCTRL_DFLLVAL_FINE(data);
+	((Sysctrl *)hw)->DFLLVAL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_FINE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_FINE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_FINE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & SYSCTRL_DFLLVAL_FINE_Msk) >> SYSCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_COARSE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_COARSE_bf(const void *const         hw,
+                                                                          hri_sysctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & SYSCTRL_DFLLVAL_COARSE(mask)) >> SYSCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~SYSCTRL_DFLLVAL_COARSE_Msk;
+	tmp |= SYSCTRL_DFLLVAL_COARSE(data);
+	((Sysctrl *)hw)->DFLLVAL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_COARSE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_COARSE(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_COARSE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & SYSCTRL_DFLLVAL_COARSE_Msk) >> SYSCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_DIFF(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_DIFF_bf(const void *const         hw,
+                                                                        hri_sysctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & SYSCTRL_DFLLVAL_DIFF(mask)) >> SYSCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~SYSCTRL_DFLLVAL_DIFF_Msk;
+	tmp |= SYSCTRL_DFLLVAL_DIFF(data);
+	((Sysctrl *)hw)->DFLLVAL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_DIFF(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_DIFF(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_DIFF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & SYSCTRL_DFLLVAL_DIFF_Msk) >> SYSCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_reg(const void *const         hw,
+                                                                    hri_sysctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLVAL.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->DFLLVAL.reg;
+}
+
+static inline void hri_sysctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_MUL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_MUL_bf(const void *const         hw,
+                                                                       hri_sysctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & SYSCTRL_DFLLMUL_MUL(mask)) >> SYSCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~SYSCTRL_DFLLMUL_MUL_Msk;
+	tmp |= SYSCTRL_DFLLMUL_MUL(data);
+	((Sysctrl *)hw)->DFLLMUL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_MUL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_MUL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_MUL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & SYSCTRL_DFLLMUL_MUL_Msk) >> SYSCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_FSTEP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_FSTEP_bf(const void *const         hw,
+                                                                         hri_sysctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & SYSCTRL_DFLLMUL_FSTEP(mask)) >> SYSCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~SYSCTRL_DFLLMUL_FSTEP_Msk;
+	tmp |= SYSCTRL_DFLLMUL_FSTEP(data);
+	((Sysctrl *)hw)->DFLLMUL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_FSTEP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_FSTEP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_FSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & SYSCTRL_DFLLMUL_FSTEP_Msk) >> SYSCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_CSTEP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_CSTEP_bf(const void *const         hw,
+                                                                         hri_sysctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & SYSCTRL_DFLLMUL_CSTEP(mask)) >> SYSCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~SYSCTRL_DFLLMUL_CSTEP_Msk;
+	tmp |= SYSCTRL_DFLLMUL_CSTEP(data);
+	((Sysctrl *)hw)->DFLLMUL.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_CSTEP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_CSTEP(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_CSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & SYSCTRL_DFLLMUL_CSTEP_Msk) >> SYSCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_reg(const void *const         hw,
+                                                                    hri_sysctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLMUL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLMUL.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->DFLLMUL.reg;
+}
+
+static inline void hri_sysctrl_set_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLSYNC.reg |= SYSCTRL_DFLLSYNC_READREQ;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & SYSCTRL_DFLLSYNC_READREQ) >> SYSCTRL_DFLLSYNC_READREQ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~SYSCTRL_DFLLSYNC_READREQ;
+	tmp |= value << SYSCTRL_DFLLSYNC_READREQ_Pos;
+	((Sysctrl *)hw)->DFLLSYNC.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLSYNC.reg &= ~SYSCTRL_DFLLSYNC_READREQ;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLSYNC.reg ^= SYSCTRL_DFLLSYNC_READREQ;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLSYNC.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllsync_reg_t hri_sysctrl_get_DFLLSYNC_reg(const void *const          hw,
+                                                                      hri_sysctrl_dfllsync_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->DFLLSYNC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLSYNC.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLSYNC.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DFLLSYNC.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dfllsync_reg_t hri_sysctrl_read_DFLLSYNC_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->DFLLSYNC.reg;
+}
+
+static inline void hri_sysctrl_set_BOD33_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_BOD33_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_ENABLE) >> SYSCTRL_BOD33_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= ~SYSCTRL_BOD33_ENABLE;
+	tmp |= value << SYSCTRL_BOD33_ENABLE_Pos;
+	((Sysctrl *)hw)->BOD33.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_BOD33_HYST_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_HYST;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_BOD33_HYST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_HYST) >> SYSCTRL_BOD33_HYST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_HYST_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= ~SYSCTRL_BOD33_HYST;
+	tmp |= value << SYSCTRL_BOD33_HYST_Pos;
+	((Sysctrl *)hw)->BOD33.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_HYST_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_HYST;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_HYST_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_HYST;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_RUNSTDBY) >> SYSCTRL_BOD33_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= ~SYSCTRL_BOD33_RUNSTDBY;
+	tmp |= value << SYSCTRL_BOD33_RUNSTDBY_Pos;
+	((Sysctrl *)hw)->BOD33.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_BOD33_MODE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_MODE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_BOD33_MODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_MODE) >> SYSCTRL_BOD33_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_MODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= ~SYSCTRL_BOD33_MODE;
+	tmp |= value << SYSCTRL_BOD33_MODE_Pos;
+	((Sysctrl *)hw)->BOD33.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_MODE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_MODE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_MODE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_MODE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_BOD33_CEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_CEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_BOD33_CEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_CEN) >> SYSCTRL_BOD33_CEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_CEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= ~SYSCTRL_BOD33_CEN;
+	tmp |= value << SYSCTRL_BOD33_CEN_Pos;
+	((Sysctrl *)hw)->BOD33.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_CEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_CEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_CEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_CEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_ACTION(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_ACTION_bf(const void *const       hw,
+                                                                      hri_sysctrl_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_ACTION(mask)) >> SYSCTRL_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= ~SYSCTRL_BOD33_ACTION_Msk;
+	tmp |= SYSCTRL_BOD33_ACTION(data);
+	((Sysctrl *)hw)->BOD33.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_ACTION(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_ACTION(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_ACTION_Msk) >> SYSCTRL_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_PSEL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_PSEL(mask)) >> SYSCTRL_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= ~SYSCTRL_BOD33_PSEL_Msk;
+	tmp |= SYSCTRL_BOD33_PSEL(data);
+	((Sysctrl *)hw)->BOD33.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_PSEL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_PSEL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_PSEL_Msk) >> SYSCTRL_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_LEVEL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_LEVEL(mask)) >> SYSCTRL_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= ~SYSCTRL_BOD33_LEVEL_Msk;
+	tmp |= SYSCTRL_BOD33_LEVEL(data);
+	((Sysctrl *)hw)->BOD33.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_LEVEL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_LEVEL(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp = (tmp & SYSCTRL_BOD33_LEVEL_Msk) >> SYSCTRL_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->BOD33.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->BOD33.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->BOD33.reg;
+}
+
+static inline void hri_sysctrl_set_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg |= SYSCTRL_VREG_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->VREG.reg;
+	tmp = (tmp & SYSCTRL_VREG_RUNSTDBY) >> SYSCTRL_VREG_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_VREG_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->VREG.reg;
+	tmp &= ~SYSCTRL_VREG_RUNSTDBY;
+	tmp |= value << SYSCTRL_VREG_RUNSTDBY_Pos;
+	((Sysctrl *)hw)->VREG.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg &= ~SYSCTRL_VREG_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg ^= SYSCTRL_VREG_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_VREG_FORCELDO_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg |= SYSCTRL_VREG_FORCELDO;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_VREG_FORCELDO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->VREG.reg;
+	tmp = (tmp & SYSCTRL_VREG_FORCELDO) >> SYSCTRL_VREG_FORCELDO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_VREG_FORCELDO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->VREG.reg;
+	tmp &= ~SYSCTRL_VREG_FORCELDO;
+	tmp |= value << SYSCTRL_VREG_FORCELDO_Pos;
+	((Sysctrl *)hw)->VREG.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_VREG_FORCELDO_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg &= ~SYSCTRL_VREG_FORCELDO;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_VREG_FORCELDO_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg ^= SYSCTRL_VREG_FORCELDO;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_vreg_reg_t hri_sysctrl_get_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sysctrl *)hw)->VREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREG.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_vreg_reg_t hri_sysctrl_read_VREG_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->VREG.reg;
+}
+
+static inline void hri_sysctrl_set_VREF_TSEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_TSEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_VREF_TSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->VREF.reg;
+	tmp = (tmp & SYSCTRL_VREF_TSEN) >> SYSCTRL_VREF_TSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_VREF_TSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->VREF.reg;
+	tmp &= ~SYSCTRL_VREF_TSEN;
+	tmp |= value << SYSCTRL_VREF_TSEN_Pos;
+	((Sysctrl *)hw)->VREF.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_VREF_TSEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_TSEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_VREF_TSEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_TSEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_VREF_BGOUTEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_VREF_BGOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->VREF.reg;
+	tmp = (tmp & SYSCTRL_VREF_BGOUTEN) >> SYSCTRL_VREF_BGOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_VREF_BGOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->VREF.reg;
+	tmp &= ~SYSCTRL_VREF_BGOUTEN;
+	tmp |= value << SYSCTRL_VREF_BGOUTEN_Pos;
+	((Sysctrl *)hw)->VREF.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_VREF_BGOUTEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_VREF_BGOUTEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_BGOUTEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_vref_reg_t hri_sysctrl_get_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->VREF.reg;
+	tmp = (tmp & SYSCTRL_VREF_CALIB(mask)) >> SYSCTRL_VREF_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->VREF.reg;
+	tmp &= ~SYSCTRL_VREF_CALIB_Msk;
+	tmp |= SYSCTRL_VREF_CALIB(data);
+	((Sysctrl *)hw)->VREF.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_CALIB(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_vref_reg_t hri_sysctrl_read_VREF_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->VREF.reg;
+	tmp = (tmp & SYSCTRL_VREF_CALIB_Msk) >> SYSCTRL_VREF_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_vref_reg_t hri_sysctrl_get_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->VREF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->VREF.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_vref_reg_t hri_sysctrl_read_VREF_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->VREF.reg;
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLA_ENABLE) >> SYSCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << SYSCTRL_DPLLCTRLA_ENABLE_Pos;
+	((Sysctrl *)hw)->DPLLCTRLA.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_ENABLE;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLA_RUNSTDBY) >> SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((Sysctrl *)hw)->DPLLCTRLA.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_RUNSTDBY;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLA_ONDEMAND) >> SYSCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((Sysctrl *)hw)->DPLLCTRLA.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_ONDEMAND;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrla_reg_t hri_sysctrl_get_DPLLCTRLA_reg(const void *const           hw,
+                                                                        hri_sysctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLA.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrla_reg_t hri_sysctrl_read_DPLLCTRLA_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->DPLLCTRLA.reg;
+}
+
+static inline void hri_sysctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg |= SYSCTRL_DPLLRATIO_LDR(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_LDR_bf(const void *const           hw,
+                                                                           hri_sysctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & SYSCTRL_DPLLRATIO_LDR(mask)) >> SYSCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLRATIO.reg;
+	tmp &= ~SYSCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= SYSCTRL_DPLLRATIO_LDR(data);
+	((Sysctrl *)hw)->DPLLRATIO.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg &= ~SYSCTRL_DPLLRATIO_LDR(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg ^= SYSCTRL_DPLLRATIO_LDR(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_LDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & SYSCTRL_DPLLRATIO_LDR_Msk) >> SYSCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg |= SYSCTRL_DPLLRATIO_LDRFRAC(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const           hw,
+                                                                               hri_sysctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & SYSCTRL_DPLLRATIO_LDRFRAC(mask)) >> SYSCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLRATIO.reg;
+	tmp &= ~SYSCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= SYSCTRL_DPLLRATIO_LDRFRAC(data);
+	((Sysctrl *)hw)->DPLLRATIO.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg &= ~SYSCTRL_DPLLRATIO_LDRFRAC(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg ^= SYSCTRL_DPLLRATIO_LDRFRAC(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & SYSCTRL_DPLLRATIO_LDRFRAC_Msk) >> SYSCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_reg(const void *const           hw,
+                                                                        hri_sysctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLRATIO.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->DPLLRATIO.reg;
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LPEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_LPEN) >> SYSCTRL_DPLLCTRLB_LPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLB_LPEN;
+	tmp |= value << SYSCTRL_DPLLCTRLB_LPEN_Pos;
+	((Sysctrl *)hw)->DPLLCTRLB.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LPEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LPEN;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_WUF;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_WUF) >> SYSCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLB_WUF;
+	tmp |= value << SYSCTRL_DPLLCTRLB_WUF_Pos;
+	((Sysctrl *)hw)->DPLLCTRLB.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_WUF;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_WUF;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LBYPASS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sysctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_LBYPASS) >> SYSCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << SYSCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((Sysctrl *)hw)->DPLLCTRLB.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LBYPASS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LBYPASS;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_FILTER(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_FILTER_bf(const void *const           hw,
+                                                                              hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_FILTER(mask)) >> SYSCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= SYSCTRL_DPLLCTRLB_FILTER(data);
+	((Sysctrl *)hw)->DPLLCTRLB.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_FILTER(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_FILTER(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_FILTER_Msk) >> SYSCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_REFCLK(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_REFCLK_bf(const void *const           hw,
+                                                                              hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_REFCLK(mask)) >> SYSCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= SYSCTRL_DPLLCTRLB_REFCLK(data);
+	((Sysctrl *)hw)->DPLLCTRLB.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_REFCLK(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_REFCLK(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_REFCLK_Msk) >> SYSCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LTIME(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_LTIME_bf(const void *const           hw,
+                                                                             hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_LTIME(mask)) >> SYSCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= SYSCTRL_DPLLCTRLB_LTIME(data);
+	((Sysctrl *)hw)->DPLLCTRLB.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LTIME(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LTIME(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_LTIME_Msk) >> SYSCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_DIV(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_DIV_bf(const void *const           hw,
+                                                                           hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_DIV(mask)) >> SYSCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~SYSCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= SYSCTRL_DPLLCTRLB_DIV(data);
+	((Sysctrl *)hw)->DPLLCTRLB.reg = tmp;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_DIV(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_DIV(mask);
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_DIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & SYSCTRL_DPLLCTRLB_DIV_Msk) >> SYSCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_sysctrl_set_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg |= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_reg(const void *const           hw,
+                                                                        hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sysctrl_write_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg = data;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg &= ~mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sysctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask)
+{
+	SYSCTRL_CRITICAL_SECTION_ENTER();
+	((Sysctrl *)hw)->DPLLCTRLB.reg ^= mask;
+	SYSCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->DPLLCTRLB.reg;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_XOSCRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_XOSCRDY) >> SYSCTRL_PCLKSR_XOSCRDY_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) >> SYSCTRL_PCLKSR_XOSC32KRDY_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_OSC32KRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY) >> SYSCTRL_PCLKSR_OSC32KRDY_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY) >> SYSCTRL_PCLKSR_OSC8MRDY_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_DFLLRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) >> SYSCTRL_PCLKSR_DFLLRDY_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_DFLLOOB_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLOOB) >> SYSCTRL_PCLKSR_DFLLOOB_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) >> SYSCTRL_PCLKSR_DFLLLCKF_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) >> SYSCTRL_PCLKSR_DFLLLCKC_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_DFLLRCS_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRCS) >> SYSCTRL_PCLKSR_DFLLRCS_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_BOD33RDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_BOD33RDY) >> SYSCTRL_PCLKSR_BOD33RDY_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_BOD33DET_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_BOD33DET) >> SYSCTRL_PCLKSR_BOD33DET_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_B33SRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_B33SRDY) >> SYSCTRL_PCLKSR_B33SRDY_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLCKR) >> SYSCTRL_PCLKSR_DPLLLCKR_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLCKF) >> SYSCTRL_PCLKSR_DPLLLCKF_Pos;
+}
+
+static inline bool hri_sysctrl_get_PCLKSR_DPLLLTO_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLTO) >> SYSCTRL_PCLKSR_DPLLLTO_Pos;
+}
+
+static inline hri_sysctrl_pclksr_reg_t hri_sysctrl_get_PCLKSR_reg(const void *const hw, hri_sysctrl_pclksr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sysctrl *)hw)->PCLKSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sysctrl_pclksr_reg_t hri_sysctrl_read_PCLKSR_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->PCLKSR.reg;
+}
+
+static inline bool hri_sysctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_LOCK) >> SYSCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_sysctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_CLKRDY) >> SYSCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline bool hri_sysctrl_get_DPLLSTATUS_ENABLE_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE) >> SYSCTRL_DPLLSTATUS_ENABLE_Pos;
+}
+
+static inline bool hri_sysctrl_get_DPLLSTATUS_DIV_bit(const void *const hw)
+{
+	return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_DIV) >> SYSCTRL_DPLLSTATUS_DIV_Pos;
+}
+
+static inline hri_sysctrl_dpllstatus_reg_t hri_sysctrl_get_DPLLSTATUS_reg(const void *const            hw,
+                                                                          hri_sysctrl_dpllstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sysctrl *)hw)->DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sysctrl_dpllstatus_reg_t hri_sysctrl_read_DPLLSTATUS_reg(const void *const hw)
+{
+	return ((Sysctrl *)hw)->DPLLSTATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SYSCTRL_D21_H_INCLUDED */
+#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h b/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h
new file mode 100644
index 000000000..5969d32bf
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h
@@ -0,0 +1,1477 @@
+/**
+ * \file
+ *
+ * \brief SAM SystemControl
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_SystemControl_COMPONENT_
+#ifndef _HRI_SystemControl_D21_H_INCLUDED_
+#define _HRI_SystemControl_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS)
+#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SystemControl_CRITICAL_SECTION_ENTER()
+#define SystemControl_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_systemcontrol_aircr_reg_t;
+typedef uint32_t hri_systemcontrol_ccr_reg_t;
+typedef uint32_t hri_systemcontrol_cpuid_reg_t;
+typedef uint32_t hri_systemcontrol_icsr_reg_t;
+typedef uint32_t hri_systemcontrol_scr_reg_t;
+typedef uint32_t hri_systemcontrol_shpr2_reg_t;
+typedef uint32_t hri_systemcontrol_shpr3_reg_t;
+typedef uint32_t hri_systemcontrol_vtor_reg_t;
+
+static inline void hri_systemcontrol_set_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_REVISION(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const             hw,
+                                                                                    hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_REVISION(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= ~SystemControl_CPUID_REVISION_Msk;
+	tmp |= SystemControl_CPUID_REVISION(data);
+	((Systemcontrol *)hw)->CPUID.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_REVISION(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_REVISION(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_REVISION_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_PARTNO(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const             hw,
+                                                                                  hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_PARTNO(mask)) >> 4;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= ~SystemControl_CPUID_PARTNO_Msk;
+	tmp |= SystemControl_CPUID_PARTNO(data);
+	((Systemcontrol *)hw)->CPUID.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_PARTNO(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_PARTNO(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_PARTNO_Msk) >> 4;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_ARCHITECTURE(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t
+hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CPUID_ARCHITECTURE_bf(const void *const             hw,
+                                                                 hri_systemcontrol_cpuid_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= ~SystemControl_CPUID_ARCHITECTURE_Msk;
+	tmp |= SystemControl_CPUID_ARCHITECTURE(data);
+	((Systemcontrol *)hw)->CPUID.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CPUID_ARCHITECTURE_bf(const void *const             hw,
+                                                                 hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_ARCHITECTURE(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CPUID_ARCHITECTURE_bf(const void *const             hw,
+                                                                  hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_ARCHITECTURE(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_VARIANT(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const             hw,
+                                                                                   hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_VARIANT(mask)) >> 20;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= ~SystemControl_CPUID_VARIANT_Msk;
+	tmp |= SystemControl_CPUID_VARIANT(data);
+	((Systemcontrol *)hw)->CPUID.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_VARIANT(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_VARIANT(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_VARIANT_Msk) >> 20;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_IMPLEMENTER(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t
+hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CPUID_IMPLEMENTER_bf(const void *const             hw,
+                                                                hri_systemcontrol_cpuid_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= ~SystemControl_CPUID_IMPLEMENTER_Msk;
+	tmp |= SystemControl_CPUID_IMPLEMENTER(data);
+	((Systemcontrol *)hw)->CPUID.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CPUID_IMPLEMENTER_bf(const void *const             hw,
+                                                                hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_IMPLEMENTER(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CPUID_IMPLEMENTER_bf(const void *const             hw,
+                                                                 hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_IMPLEMENTER(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp = (tmp & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const             hw,
+                                                                            hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPUID.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CPUID.reg;
+}
+
+static inline void hri_systemcontrol_set_ICSR_PENDSTCLR_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTCLR;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_ICSR_PENDSTCLR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp = (tmp & SystemControl_ICSR_PENDSTCLR) >> 25;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_PENDSTCLR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= ~SystemControl_ICSR_PENDSTCLR;
+	tmp |= value << 25;
+	((Systemcontrol *)hw)->ICSR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_PENDSTCLR_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTCLR;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_PENDSTCLR_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTCLR;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_ICSR_PENDSTSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_ICSR_PENDSTSET_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp = (tmp & SystemControl_ICSR_PENDSTSET) >> 26;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_PENDSTSET_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= ~SystemControl_ICSR_PENDSTSET;
+	tmp |= value << 26;
+	((Systemcontrol *)hw)->ICSR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_PENDSTSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_PENDSTSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_ICSR_PENDSVCLR_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSVCLR;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_ICSR_PENDSVCLR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp = (tmp & SystemControl_ICSR_PENDSVCLR) >> 27;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_PENDSVCLR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= ~SystemControl_ICSR_PENDSVCLR;
+	tmp |= value << 27;
+	((Systemcontrol *)hw)->ICSR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_PENDSVCLR_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSVCLR;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_PENDSVCLR_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSVCLR;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_ICSR_PENDSVSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSVSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_ICSR_PENDSVSET_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp = (tmp & SystemControl_ICSR_PENDSVSET) >> 28;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_PENDSVSET_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= ~SystemControl_ICSR_PENDSVSET;
+	tmp |= value << 28;
+	((Systemcontrol *)hw)->ICSR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_PENDSVSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSVSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_PENDSVSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSVSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_ICSR_NMIPENDSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_NMIPENDSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_ICSR_NMIPENDSET_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp = (tmp & SystemControl_ICSR_NMIPENDSET) >> 31;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_NMIPENDSET_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= ~SystemControl_ICSR_NMIPENDSET;
+	tmp |= value << 31;
+	((Systemcontrol *)hw)->ICSR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_NMIPENDSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_NMIPENDSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_NMIPENDSET_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_NMIPENDSET;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_VECTPENDING(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_VECTPENDING_bf(const void *const            hw,
+                                                                                     hri_systemcontrol_icsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp = (tmp & SystemControl_ICSR_VECTPENDING(mask)) >> 12;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= ~SystemControl_ICSR_VECTPENDING_Msk;
+	tmp |= SystemControl_ICSR_VECTPENDING(data);
+	((Systemcontrol *)hw)->ICSR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_VECTPENDING(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_VECTPENDING(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_VECTPENDING_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp = (tmp & SystemControl_ICSR_VECTPENDING_Msk) >> 12;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_icsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->ICSR.reg;
+}
+
+static inline void hri_systemcontrol_set_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg |= SystemControl_VTOR_TBLOFF(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_TBLOFF_bf(const void *const            hw,
+                                                                                hri_systemcontrol_vtor_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->VTOR.reg;
+	tmp = (tmp & SystemControl_VTOR_TBLOFF(mask)) >> 7;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->VTOR.reg;
+	tmp &= ~SystemControl_VTOR_TBLOFF_Msk;
+	tmp |= SystemControl_VTOR_TBLOFF(data);
+	((Systemcontrol *)hw)->VTOR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg &= ~SystemControl_VTOR_TBLOFF(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg ^= SystemControl_VTOR_TBLOFF(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_TBLOFF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->VTOR.reg;
+	tmp = (tmp & SystemControl_VTOR_TBLOFF_Msk) >> 7;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_vtor_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->VTOR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->VTOR.reg;
+}
+
+static inline void hri_systemcontrol_set_AIRCR_VECTCLRACTIVE_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_VECTCLRACTIVE;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_AIRCR_VECTCLRACTIVE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp = (tmp & SystemControl_AIRCR_VECTCLRACTIVE) >> 1;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_AIRCR_VECTCLRACTIVE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp &= ~SystemControl_AIRCR_VECTCLRACTIVE;
+	tmp |= value << 1;
+	((Systemcontrol *)hw)->AIRCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AIRCR_VECTCLRACTIVE_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_VECTCLRACTIVE;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AIRCR_VECTCLRACTIVE_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_VECTCLRACTIVE;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_AIRCR_SYSRESETREQ_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_SYSRESETREQ;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_AIRCR_SYSRESETREQ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp = (tmp & SystemControl_AIRCR_SYSRESETREQ) >> 2;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_AIRCR_SYSRESETREQ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp &= ~SystemControl_AIRCR_SYSRESETREQ;
+	tmp |= value << 2;
+	((Systemcontrol *)hw)->AIRCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AIRCR_SYSRESETREQ_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_SYSRESETREQ;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AIRCR_SYSRESETREQ_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_SYSRESETREQ;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_AIRCR_ENDIANNESS_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_ENDIANNESS;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_AIRCR_ENDIANNESS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp = (tmp & SystemControl_AIRCR_ENDIANNESS) >> 15;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_AIRCR_ENDIANNESS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp &= ~SystemControl_AIRCR_ENDIANNESS;
+	tmp |= value << 15;
+	((Systemcontrol *)hw)->AIRCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AIRCR_ENDIANNESS_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_ENDIANNESS;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AIRCR_ENDIANNESS_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_ENDIANNESS;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_VECTKEY(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_VECTKEY_bf(const void *const             hw,
+                                                                                   hri_systemcontrol_aircr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp = (tmp & SystemControl_AIRCR_VECTKEY(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp &= ~SystemControl_AIRCR_VECTKEY_Msk;
+	tmp |= SystemControl_AIRCR_VECTKEY(data);
+	((Systemcontrol *)hw)->AIRCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_VECTKEY(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_VECTKEY(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_VECTKEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp = (tmp & SystemControl_AIRCR_VECTKEY_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_aircr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->AIRCR.reg;
+}
+
+static inline void hri_systemcontrol_set_SCR_SLEEPONEXIT_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPONEXIT;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_SCR_SLEEPONEXIT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp = (tmp & SystemControl_SCR_SLEEPONEXIT) >> 1;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_SCR_SLEEPONEXIT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp &= ~SystemControl_SCR_SLEEPONEXIT;
+	tmp |= value << 1;
+	((Systemcontrol *)hw)->SCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SCR_SLEEPONEXIT_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPONEXIT;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SCR_SLEEPONEXIT_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPONEXIT;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_SCR_SLEEPDEEP_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPDEEP;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_SCR_SLEEPDEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp = (tmp & SystemControl_SCR_SLEEPDEEP) >> 2;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_SCR_SLEEPDEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp &= ~SystemControl_SCR_SLEEPDEEP;
+	tmp |= value << 2;
+	((Systemcontrol *)hw)->SCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SCR_SLEEPDEEP_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPDEEP;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SCR_SLEEPDEEP_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPDEEP;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_SCR_SEVONPEND_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SEVONPEND;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_SCR_SEVONPEND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp = (tmp & SystemControl_SCR_SEVONPEND) >> 4;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_SCR_SEVONPEND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp &= ~SystemControl_SCR_SEVONPEND;
+	tmp |= value << 4;
+	((Systemcontrol *)hw)->SCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SCR_SEVONPEND_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SEVONPEND;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SCR_SEVONPEND_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SEVONPEND;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_scr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SCR.reg;
+}
+
+static inline void hri_systemcontrol_set_CCR_UNALIGN_TRP_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_UNALIGN_TRP;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CCR.reg;
+	tmp = (tmp & SystemControl_CCR_UNALIGN_TRP) >> 3;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_CCR_UNALIGN_TRP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->CCR.reg;
+	tmp &= ~SystemControl_CCR_UNALIGN_TRP;
+	tmp |= value << 3;
+	((Systemcontrol *)hw)->CCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CCR_UNALIGN_TRP_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_UNALIGN_TRP;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CCR_UNALIGN_TRP_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_UNALIGN_TRP;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_CCR_STKALIGN_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_STKALIGN;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CCR.reg;
+	tmp = (tmp & SystemControl_CCR_STKALIGN) >> 9;
+	return (bool)tmp;
+}
+
+static inline void hri_systemcontrol_write_CCR_STKALIGN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->CCR.reg;
+	tmp &= ~SystemControl_CCR_STKALIGN;
+	tmp |= value << 9;
+	((Systemcontrol *)hw)->CCR.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CCR_STKALIGN_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_STKALIGN;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CCR_STKALIGN_bit(const void *const hw)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_STKALIGN;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_set_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_ccr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CCR.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg |= SystemControl_SHPR2_PRI_11(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_PRI_11_bf(const void *const             hw,
+                                                                                  hri_systemcontrol_shpr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
+	tmp = (tmp & SystemControl_SHPR2_PRI_11(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
+	tmp &= ~SystemControl_SHPR2_PRI_11_Msk;
+	tmp |= SystemControl_SHPR2_PRI_11(data);
+	((Systemcontrol *)hw)->SHPR2.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg &= ~SystemControl_SHPR2_PRI_11(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg ^= SystemControl_SHPR2_PRI_11(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_PRI_11_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
+	tmp = (tmp & SystemControl_SHPR2_PRI_11_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR2.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg |= SystemControl_SHPR3_PRI_14(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_PRI_14_bf(const void *const             hw,
+                                                                                  hri_systemcontrol_shpr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp = (tmp & SystemControl_SHPR3_PRI_14(mask)) >> 16;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp &= ~SystemControl_SHPR3_PRI_14_Msk;
+	tmp |= SystemControl_SHPR3_PRI_14(data);
+	((Systemcontrol *)hw)->SHPR3.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg &= ~SystemControl_SHPR3_PRI_14(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg ^= SystemControl_SHPR3_PRI_14(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_PRI_14_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp = (tmp & SystemControl_SHPR3_PRI_14_Msk) >> 16;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg |= SystemControl_SHPR3_PRI_15(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_PRI_15_bf(const void *const             hw,
+                                                                                  hri_systemcontrol_shpr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp = (tmp & SystemControl_SHPR3_PRI_15(mask)) >> 24;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
+{
+	uint32_t tmp;
+	SystemControl_CRITICAL_SECTION_ENTER();
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp &= ~SystemControl_SHPR3_PRI_15_Msk;
+	tmp |= SystemControl_SHPR3_PRI_15(data);
+	((Systemcontrol *)hw)->SHPR3.reg = tmp;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg &= ~SystemControl_SHPR3_PRI_15(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg ^= SystemControl_SHPR3_PRI_15(mask);
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_PRI_15_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp = (tmp & SystemControl_SHPR3_PRI_15_Msk) >> 24;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR3.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SystemControl_D21_H_INCLUDED */
+#endif /* _SAMD21_SystemControl_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_systick_d21.h b/atmel-samd/asf4/samd21/hri/hri_systick_d21.h
new file mode 100644
index 000000000..34d4558c0
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_systick_d21.h
@@ -0,0 +1,620 @@
+/**
+ * \file
+ *
+ * \brief SAM SysTick
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_SysTick_COMPONENT_
+#ifndef _HRI_SysTick_D21_H_INCLUDED_
+#define _HRI_SysTick_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SysTick_CRITICAL_SECTIONS)
+#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SysTick_CRITICAL_SECTION_ENTER()
+#define SysTick_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_systick_calib_reg_t;
+typedef uint32_t hri_systick_csr_reg_t;
+typedef uint32_t hri_systick_cvr_reg_t;
+typedef uint32_t hri_systick_rvr_reg_t;
+
+static inline void hri_systick_set_CSR_ENABLE_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg |= SysTick_CSR_ENABLE;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systick_get_CSR_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp = (tmp & SysTick_CSR_ENABLE) >> 0;
+	return (bool)tmp;
+}
+
+static inline void hri_systick_write_CSR_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp &= ~SysTick_CSR_ENABLE;
+	tmp |= value << 0;
+	((Systick *)hw)->CSR.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CSR_ENABLE_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg &= ~SysTick_CSR_ENABLE;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CSR_ENABLE_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg ^= SysTick_CSR_ENABLE;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_set_CSR_TICKINT_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg |= SysTick_CSR_TICKINT;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systick_get_CSR_TICKINT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp = (tmp & SysTick_CSR_TICKINT) >> 1;
+	return (bool)tmp;
+}
+
+static inline void hri_systick_write_CSR_TICKINT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp &= ~SysTick_CSR_TICKINT;
+	tmp |= value << 1;
+	((Systick *)hw)->CSR.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CSR_TICKINT_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg &= ~SysTick_CSR_TICKINT;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CSR_TICKINT_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg ^= SysTick_CSR_TICKINT;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_set_CSR_CLKSOURCE_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg |= SysTick_CSR_CLKSOURCE;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systick_get_CSR_CLKSOURCE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp = (tmp & SysTick_CSR_CLKSOURCE) >> 2;
+	return (bool)tmp;
+}
+
+static inline void hri_systick_write_CSR_CLKSOURCE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp &= ~SysTick_CSR_CLKSOURCE;
+	tmp |= value << 2;
+	((Systick *)hw)->CSR.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CSR_CLKSOURCE_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg &= ~SysTick_CSR_CLKSOURCE;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CSR_CLKSOURCE_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg ^= SysTick_CSR_CLKSOURCE;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_set_CSR_COUNTFLAG_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg |= SysTick_CSR_COUNTFLAG;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systick_get_CSR_COUNTFLAG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp = (tmp & SysTick_CSR_COUNTFLAG) >> 16;
+	return (bool)tmp;
+}
+
+static inline void hri_systick_write_CSR_COUNTFLAG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp &= ~SysTick_CSR_COUNTFLAG;
+	tmp |= value << 16;
+	((Systick *)hw)->CSR.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CSR_COUNTFLAG_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg &= ~SysTick_CSR_COUNTFLAG;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CSR_COUNTFLAG_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg ^= SysTick_CSR_COUNTFLAG;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CSR.reg;
+}
+
+static inline void hri_systick_set_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg |= SysTick_RVR_RELOAD(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_get_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->RVR.reg;
+	tmp = (tmp & SysTick_RVR_RELOAD(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_systick_write_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t data)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->RVR.reg;
+	tmp &= ~SysTick_RVR_RELOAD_Msk;
+	tmp |= SysTick_RVR_RELOAD(data);
+	((Systick *)hw)->RVR.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg &= ~SysTick_RVR_RELOAD(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg ^= SysTick_RVR_RELOAD(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_read_RVR_RELOAD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->RVR.reg;
+	tmp = (tmp & SysTick_RVR_RELOAD_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->RVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->RVR.reg;
+}
+
+static inline void hri_systick_set_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg |= SysTick_CVR_CURRENT(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_get_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CVR.reg;
+	tmp = (tmp & SysTick_CVR_CURRENT(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_systick_write_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t data)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->CVR.reg;
+	tmp &= ~SysTick_CVR_CURRENT_Msk;
+	tmp |= SysTick_CVR_CURRENT(data);
+	((Systick *)hw)->CVR.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg &= ~SysTick_CVR_CURRENT(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg ^= SysTick_CVR_CURRENT(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_read_CVR_CURRENT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CVR.reg;
+	tmp = (tmp & SysTick_CVR_CURRENT_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CVR.reg;
+}
+
+static inline void hri_systick_set_CALIB_SKEW_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg |= SysTick_CALIB_SKEW;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp = (tmp & SysTick_CALIB_SKEW) >> 30;
+	return (bool)tmp;
+}
+
+static inline void hri_systick_write_CALIB_SKEW_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp &= ~SysTick_CALIB_SKEW;
+	tmp |= value << 30;
+	((Systick *)hw)->CALIB.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CALIB_SKEW_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_SKEW;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CALIB_SKEW_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_SKEW;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_set_CALIB_NOREF_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg |= SysTick_CALIB_NOREF;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp = (tmp & SysTick_CALIB_NOREF) >> 31;
+	return (bool)tmp;
+}
+
+static inline void hri_systick_write_CALIB_NOREF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp &= ~SysTick_CALIB_NOREF;
+	tmp |= value << 31;
+	((Systick *)hw)->CALIB.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CALIB_NOREF_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_NOREF;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CALIB_NOREF_bit(const void *const hw)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_NOREF;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_set_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg |= SysTick_CALIB_TENMS(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp = (tmp & SysTick_CALIB_TENMS(mask)) >> 0;
+	return tmp;
+}
+
+static inline void hri_systick_write_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t data)
+{
+	uint32_t tmp;
+	SysTick_CRITICAL_SECTION_ENTER();
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp &= ~SysTick_CALIB_TENMS_Msk;
+	tmp |= SysTick_CALIB_TENMS(data);
+	((Systick *)hw)->CALIB.reg = tmp;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_TENMS(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_TENMS(mask);
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp = (tmp & SysTick_CALIB_TENMS_Msk) >> 0;
+	return tmp;
+}
+
+static inline void hri_systick_set_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CALIB_reg(const void *const hw, hri_systick_calib_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CALIB.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CALIB.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SysTick_D21_H_INCLUDED */
+#endif /* _SAMD21_SysTick_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_tc_d21.h b/atmel-samd/asf4/samd21/hri/hri_tc_d21.h
new file mode 100644
index 000000000..08058f4f7
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_tc_d21.h
@@ -0,0 +1,2190 @@
+/**
+ * \file
+ *
+ * \brief SAM TC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_TC_COMPONENT_
+#ifndef _HRI_TC_D21_H_INCLUDED_
+#define _HRI_TC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TC_CRITICAL_SECTIONS)
+#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TC_CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tc_cc16_reg_t;
+typedef uint16_t hri_tc_count16_reg_t;
+typedef uint16_t hri_tc_ctrla_reg_t;
+typedef uint16_t hri_tc_evctrl_reg_t;
+typedef uint16_t hri_tc_readreq_reg_t;
+typedef uint32_t hri_tc_cc32_reg_t;
+typedef uint32_t hri_tc_count32_reg_t;
+typedef uint8_t  hri_tc_cc8_reg_t;
+typedef uint8_t  hri_tc_count8_reg_t;
+typedef uint8_t  hri_tc_ctrlbset_reg_t;
+typedef uint8_t  hri_tc_ctrlc_reg_t;
+typedef uint8_t  hri_tc_dbgctrl_reg_t;
+typedef uint8_t  hri_tc_intenset_reg_t;
+typedef uint8_t  hri_tc_intflag_reg_t;
+typedef uint8_t  hri_tc_per_reg_t;
+typedef uint8_t  hri_tc_status_reg_t;
+
+static inline void hri_tc_wait_for_sync(const void *const hw)
+{
+	while (((const Tc *)hw)->COUNT8.STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_tc_is_syncing(const void *const hw)
+{
+	return ((const Tc *)hw)->COUNT8.STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= ~TC_COUNT16_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT16_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT16.COUNT.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tc_count16_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.COUNT.reg;
+}
+
+static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= ~TC_COUNT16_CC_CC_Msk;
+	tmp |= TC_COUNT16_CC_CC(data);
+	((Tc *)hw)->COUNT16.CC[index].reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index)
+{
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+}
+
+static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= ~TC_COUNT32_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT32_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT32.COUNT.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tc_count32_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT32.COUNT.reg;
+}
+
+static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= ~TC_COUNT32_CC_CC_Msk;
+	tmp |= TC_COUNT32_CC_CC(data);
+	((Tc *)hw)->COUNT32.CC[index].reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
+{
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+}
+
+static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+	} else {
+		((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+}
+
+static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+	} else {
+		((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(data);
+	((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT8.CTRLBSET.reg = mask;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.CTRLBSET.reg;
+}
+
+static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT8.CTRLBSET.reg = data;
+	((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT8.CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF;
+}
+
+static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF;
+	} else {
+		((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF;
+}
+
+static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR;
+}
+
+static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR;
+	} else {
+		((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR;
+}
+
+static inline void hri_tc_set_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_SYNCRDY;
+}
+
+static inline bool hri_tc_get_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_SYNCRDY) >> TC_INTENSET_SYNCRDY_Pos;
+}
+
+static inline void hri_tc_write_INTEN_SYNCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_SYNCRDY;
+	} else {
+		((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_SYNCRDY;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_SYNCRDY_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_SYNCRDY;
+}
+
+static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0;
+}
+
+static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0;
+	} else {
+		((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0;
+}
+
+static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1;
+}
+
+static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1;
+	} else {
+		((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1;
+}
+
+static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT8.INTENSET.reg = mask;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.INTENSET.reg;
+}
+
+static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data)
+{
+	((Tc *)hw)->COUNT8.INTENSET.reg = data;
+	((Tc *)hw)->COUNT8.INTENCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT8.INTENCLR.reg = mask;
+}
+
+static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_SYNCRDY) >> TC_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_SYNCRDY_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_SYNCRDY) >> TC_INTFLAG_SYNCRDY_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_SYNCRDY_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_SYNCRDY;
+}
+
+static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.INTFLAG.reg;
+}
+
+static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	((Tc *)hw)->COUNT8.INTFLAG.reg = mask;
+}
+
+static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_SWRST;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ENABLE;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ENABLE;
+	tmp |= value << TC_CTRLA_ENABLE_Pos;
+	((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ENABLE;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_RUNSTDBY;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp &= ~TC_CTRLA_RUNSTDBY;
+	tmp |= value << TC_CTRLA_RUNSTDBY_Pos;
+	((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_RUNSTDBY;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_MODE(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp &= ~TC_CTRLA_MODE_Msk;
+	tmp |= TC_CTRLA_MODE(data);
+	((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_MODE(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_MODE(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_WAVEGEN(mask)) >> TC_CTRLA_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp &= ~TC_CTRLA_WAVEGEN_Msk;
+	tmp |= TC_CTRLA_WAVEGEN(data);
+	((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_WAVEGEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_WAVEGEN_Msk) >> TC_CTRLA_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCALER(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCALER_Msk;
+	tmp |= TC_CTRLA_PRESCALER(data);
+	((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TC_CTRLA_PRESCSYNC(data);
+	((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLA.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.CTRLA.reg;
+}
+
+static inline void hri_tc_set_READREQ_RCONT_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_RCONT;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_READREQ_RCONT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.READREQ.reg;
+	tmp = (tmp & TC_READREQ_RCONT) >> TC_READREQ_RCONT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_READREQ_RCONT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.READREQ.reg;
+	tmp &= ~TC_READREQ_RCONT;
+	tmp |= value << TC_READREQ_RCONT_Pos;
+	((Tc *)hw)->COUNT8.READREQ.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_READREQ_RCONT_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_RCONT;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_READREQ_RCONT_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_RCONT;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_READREQ_RREQ_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_RREQ;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_READREQ_RREQ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.READREQ.reg;
+	tmp = (tmp & TC_READREQ_RREQ) >> TC_READREQ_RREQ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_READREQ_RREQ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.READREQ.reg;
+	tmp &= ~TC_READREQ_RREQ;
+	tmp |= value << TC_READREQ_RREQ_Pos;
+	((Tc *)hw)->COUNT8.READREQ.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_READREQ_RREQ_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_RREQ;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_READREQ_RREQ_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_RREQ;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_ADDR(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_readreq_reg_t hri_tc_get_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.READREQ.reg;
+	tmp = (tmp & TC_READREQ_ADDR(mask)) >> TC_READREQ_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.READREQ.reg;
+	tmp &= ~TC_READREQ_ADDR_Msk;
+	tmp |= TC_READREQ_ADDR(data);
+	((Tc *)hw)->COUNT8.READREQ.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_ADDR(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_ADDR(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_readreq_reg_t hri_tc_read_READREQ_ADDR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.READREQ.reg;
+	tmp = (tmp & TC_READREQ_ADDR_Msk) >> TC_READREQ_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_readreq_reg_t hri_tc_get_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.READREQ.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.READREQ.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_readreq_reg_t hri_tc_read_READREQ_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.READREQ.reg;
+}
+
+static inline void hri_tc_set_CTRLC_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLC_INVEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp = (tmp & TC_CTRLC_INVEN0) >> TC_CTRLC_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLC_INVEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp &= ~TC_CTRLC_INVEN0;
+	tmp |= value << TC_CTRLC_INVEN0_Pos;
+	((Tc *)hw)->COUNT8.CTRLC.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLC_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLC_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLC_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLC_INVEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp = (tmp & TC_CTRLC_INVEN1) >> TC_CTRLC_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLC_INVEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp &= ~TC_CTRLC_INVEN1;
+	tmp |= value << TC_CTRLC_INVEN1_Pos;
+	((Tc *)hw)->COUNT8.CTRLC.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLC_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLC_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLC_CPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_CPTEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLC_CPTEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp = (tmp & TC_CTRLC_CPTEN0) >> TC_CTRLC_CPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLC_CPTEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp &= ~TC_CTRLC_CPTEN0;
+	tmp |= value << TC_CTRLC_CPTEN0_Pos;
+	((Tc *)hw)->COUNT8.CTRLC.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLC_CPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_CPTEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLC_CPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_CPTEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLC_CPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_CPTEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLC_CPTEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp = (tmp & TC_CTRLC_CPTEN1) >> TC_CTRLC_CPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLC_CPTEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp &= ~TC_CTRLC_CPTEN1;
+	tmp |= value << TC_CTRLC_CPTEN1_Pos;
+	((Tc *)hw)->COUNT8.CTRLC.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLC_CPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_CPTEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLC_CPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_CPTEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrlc_reg_t hri_tc_get_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CTRLC.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrlc_reg_t hri_tc_read_CTRLC_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.CTRLC.reg;
+}
+
+static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg;
+	tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg;
+	tmp &= ~TC_DBGCTRL_DBGRUN;
+	tmp |= value << TC_DBGCTRL_DBGRUN_Pos;
+	((Tc *)hw)->COUNT8.DBGCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.DBGCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.DBGCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.DBGCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.DBGCTRL.reg;
+}
+
+static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCINV;
+	tmp |= value << TC_EVCTRL_TCINV_Pos;
+	((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCEI;
+	tmp |= value << TC_EVCTRL_TCEI_Pos;
+	((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_OVFEO;
+	tmp |= value << TC_EVCTRL_OVFEO_Pos;
+	((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO0;
+	tmp |= value << TC_EVCTRL_MCEO0_Pos;
+	((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO1;
+	tmp |= value << TC_EVCTRL_MCEO1_Pos;
+	((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_EVACT_Msk;
+	tmp |= TC_EVCTRL_EVACT(data);
+	((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.EVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.EVCTRL.reg;
+}
+
+static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= ~TC_COUNT8_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT8_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT8.COUNT.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tc_count8_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.COUNT.reg;
+}
+
+static inline void hri_tc_set_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_per_reg_t hri_tc_get_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_PER_PER_bf(const void *const hw, hri_tc_per_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= ~TC_COUNT8_PER_PER_Msk;
+	tmp |= TC_COUNT8_PER_PER(data);
+	((Tc *)hw)->COUNT8.PER.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_per_reg_t hri_tc_read_PER_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_PER_reg(const void *const hw, hri_tc_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_per_reg_t hri_tc_get_PER_reg(const void *const hw, hri_tc_per_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_PER_reg(const void *const hw, hri_tc_per_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_PER_reg(const void *const hw, hri_tc_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_PER_reg(const void *const hw, hri_tc_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_per_reg_t hri_tc_read_PER_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.PER.reg;
+}
+
+static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= ~TC_COUNT8_CC_CC_Msk;
+	tmp |= TC_COUNT8_CC_CC(data);
+	((Tc *)hw)->COUNT8.CC[index].reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index)
+{
+	return ((Tc *)hw)->COUNT8.CC[index].reg;
+}
+
+static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos;
+}
+
+static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos;
+}
+
+static inline bool hri_tc_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SYNCBUSY) >> TC_STATUS_SYNCBUSY_Pos;
+}
+
+static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT8.STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TC_D21_H_INCLUDED */
+#endif /* _SAMD21_TC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h b/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h
new file mode 100644
index 000000000..051c8c821
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h
@@ -0,0 +1,10318 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_TCC_COMPONENT_
+#ifndef _HRI_TCC_D21_H_INCLUDED_
+#define _HRI_TCC_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TCC_CRITICAL_SECTIONS)
+#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TCC_CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tcc_patt_reg_t;
+typedef uint16_t hri_tcc_pattb_reg_t;
+typedef uint32_t hri_tcc_cc_reg_t;
+typedef uint32_t hri_tcc_ccb_reg_t;
+typedef uint32_t hri_tcc_count_reg_t;
+typedef uint32_t hri_tcc_ctrla_reg_t;
+typedef uint32_t hri_tcc_drvctrl_reg_t;
+typedef uint32_t hri_tcc_evctrl_reg_t;
+typedef uint32_t hri_tcc_fctrla_reg_t;
+typedef uint32_t hri_tcc_fctrlb_reg_t;
+typedef uint32_t hri_tcc_intenset_reg_t;
+typedef uint32_t hri_tcc_intflag_reg_t;
+typedef uint32_t hri_tcc_per_reg_t;
+typedef uint32_t hri_tcc_perb_reg_t;
+typedef uint32_t hri_tcc_status_reg_t;
+typedef uint32_t hri_tcc_syncbusy_reg_t;
+typedef uint32_t hri_tcc_wave_reg_t;
+typedef uint32_t hri_tcc_waveb_reg_t;
+typedef uint32_t hri_tcc_wexctrl_reg_t;
+typedef uint8_t  hri_tcc_ctrlbset_reg_t;
+typedef uint8_t  hri_tcc_dbgctrl_reg_t;
+
+static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_DITH4_COUNT(mask)) >> TCC_COUNT_DITH4_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_DITH4_COUNT_Msk;
+	tmp |= TCC_COUNT_DITH4_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH4_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH4_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_DITH4_COUNT_Msk) >> TCC_COUNT_DITH4_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH5_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_DITH5_COUNT(mask)) >> TCC_COUNT_DITH5_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_DITH5_COUNT_Msk;
+	tmp |= TCC_COUNT_DITH5_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH5_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH5_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_DITH5_COUNT_Msk) >> TCC_COUNT_DITH5_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH6_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_DITH6_COUNT(mask)) >> TCC_COUNT_DITH6_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_DITH6_COUNT_Msk;
+	tmp |= TCC_COUNT_DITH6_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH6_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH6_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_DITH6_COUNT_Msk) >> TCC_COUNT_DITH6_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHERCY(mask)) >> TCC_PER_DITH4_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH4_DITHERCY_Msk;
+	tmp |= TCC_PER_DITH4_DITHERCY(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHERCY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHERCY_Msk) >> TCC_PER_DITH4_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_PER(mask)) >> TCC_PER_DITH4_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH4_PER_Msk;
+	tmp |= TCC_PER_DITH4_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_PER_Msk) >> TCC_PER_DITH4_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHERCY(mask)) >> TCC_PER_DITH5_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH5_DITHERCY_Msk;
+	tmp |= TCC_PER_DITH5_DITHERCY(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHERCY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHERCY_Msk) >> TCC_PER_DITH5_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_PER(mask)) >> TCC_PER_DITH5_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH5_PER_Msk;
+	tmp |= TCC_PER_DITH5_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_PER_Msk) >> TCC_PER_DITH5_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHERCY(mask)) >> TCC_PER_DITH6_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH6_DITHERCY_Msk;
+	tmp |= TCC_PER_DITH6_DITHERCY(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHERCY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHERCY_Msk) >> TCC_PER_DITH6_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_PER(mask)) >> TCC_PER_DITH6_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH6_PER_Msk;
+	tmp |= TCC_PER_DITH6_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_PER_Msk) >> TCC_PER_DITH6_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index,
+                                                                hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHERCY(mask)) >> TCC_CC_DITH4_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH4_DITHERCY_Msk;
+	tmp |= TCC_CC_DITH4_DITHERCY(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHERCY_Msk) >> TCC_CC_DITH4_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_CC(mask)) >> TCC_CC_DITH4_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH4_CC_Msk;
+	tmp |= TCC_CC_DITH4_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_CC_Msk) >> TCC_CC_DITH4_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index,
+                                                                hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHERCY(mask)) >> TCC_CC_DITH5_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH5_DITHERCY_Msk;
+	tmp |= TCC_CC_DITH5_DITHERCY(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHERCY_Msk) >> TCC_CC_DITH5_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_CC(mask)) >> TCC_CC_DITH5_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH5_CC_Msk;
+	tmp |= TCC_CC_DITH5_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_CC_Msk) >> TCC_CC_DITH5_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index,
+                                                                hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHERCY(mask)) >> TCC_CC_DITH6_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH6_DITHERCY_Msk;
+	tmp |= TCC_CC_DITH6_DITHERCY(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHERCY(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHERCY_Msk) >> TCC_CC_DITH6_DITHERCY_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_CC(mask)) >> TCC_CC_DITH6_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH6_CC_Msk;
+	tmp |= TCC_CC_DITH6_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_CC_Msk) >> TCC_CC_DITH6_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH4_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH4_DITHERCYB(mask)) >> TCC_PERB_DITH4_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= ~TCC_PERB_DITH4_DITHERCYB_Msk;
+	tmp |= TCC_PERB_DITH4_DITHERCYB(data);
+	((Tcc *)hw)->PERB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH4_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH4_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_DITHERCYB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH4_DITHERCYB_Msk) >> TCC_PERB_DITH4_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH4_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH4_PERB(mask)) >> TCC_PERB_DITH4_PERB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= ~TCC_PERB_DITH4_PERB_Msk;
+	tmp |= TCC_PERB_DITH4_PERB(data);
+	((Tcc *)hw)->PERB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH4_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH4_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_PERB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH4_PERB_Msk) >> TCC_PERB_DITH4_PERB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH5_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH5_DITHERCYB(mask)) >> TCC_PERB_DITH5_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= ~TCC_PERB_DITH5_DITHERCYB_Msk;
+	tmp |= TCC_PERB_DITH5_DITHERCYB(data);
+	((Tcc *)hw)->PERB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH5_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH5_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_DITHERCYB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH5_DITHERCYB_Msk) >> TCC_PERB_DITH5_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH5_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH5_PERB(mask)) >> TCC_PERB_DITH5_PERB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= ~TCC_PERB_DITH5_PERB_Msk;
+	tmp |= TCC_PERB_DITH5_PERB(data);
+	((Tcc *)hw)->PERB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH5_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH5_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_PERB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH5_PERB_Msk) >> TCC_PERB_DITH5_PERB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH6_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH6_DITHERCYB(mask)) >> TCC_PERB_DITH6_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= ~TCC_PERB_DITH6_DITHERCYB_Msk;
+	tmp |= TCC_PERB_DITH6_DITHERCYB(data);
+	((Tcc *)hw)->PERB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH6_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH6_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_DITHERCYB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH6_DITHERCYB_Msk) >> TCC_PERB_DITH6_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH6_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH6_PERB(mask)) >> TCC_PERB_DITH6_PERB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= ~TCC_PERB_DITH6_PERB_Msk;
+	tmp |= TCC_PERB_DITH6_PERB(data);
+	((Tcc *)hw)->PERB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH6_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH6_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_PERB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_DITH6_PERB_Msk) >> TCC_PERB_DITH6_PERB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= TCC_PERB_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_PERB(mask)) >> TCC_PERB_PERB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= ~TCC_PERB_PERB_Msk;
+	tmp |= TCC_PERB_PERB(data);
+	((Tcc *)hw)->PERB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~TCC_PERB_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= TCC_PERB_PERB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_PERB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp = (tmp & TCC_PERB_PERB_Msk) >> TCC_PERB_PERB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERB.reg;
+}
+
+static inline void hri_tcc_set_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERB.reg;
+}
+
+static inline void hri_tcc_set_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERB.reg;
+}
+
+static inline void hri_tcc_set_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERB_reg(const void *const hw, hri_tcc_perb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERB.reg;
+}
+
+static inline void hri_tcc_set_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH4_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH4_DITHERCYB(mask)) >> TCC_CCB_DITH4_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= ~TCC_CCB_DITH4_DITHERCYB_Msk;
+	tmp |= TCC_CCB_DITH4_DITHERCYB(data);
+	((Tcc *)hw)->CCB[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH4_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH4_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH4_DITHERCYB_Msk) >> TCC_CCB_DITH4_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH4_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index,
+                                                             hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH4_CCB(mask)) >> TCC_CCB_DITH4_CCB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= ~TCC_CCB_DITH4_CCB_Msk;
+	tmp |= TCC_CCB_DITH4_CCB(data);
+	((Tcc *)hw)->CCB[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH4_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH4_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH4_CCB_Msk) >> TCC_CCB_DITH4_CCB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH5_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH5_DITHERCYB(mask)) >> TCC_CCB_DITH5_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= ~TCC_CCB_DITH5_DITHERCYB_Msk;
+	tmp |= TCC_CCB_DITH5_DITHERCYB(data);
+	((Tcc *)hw)->CCB[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH5_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH5_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH5_DITHERCYB_Msk) >> TCC_CCB_DITH5_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH5_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index,
+                                                             hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH5_CCB(mask)) >> TCC_CCB_DITH5_CCB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= ~TCC_CCB_DITH5_CCB_Msk;
+	tmp |= TCC_CCB_DITH5_CCB(data);
+	((Tcc *)hw)->CCB[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH5_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH5_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH5_CCB_Msk) >> TCC_CCB_DITH5_CCB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH6_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH6_DITHERCYB(mask)) >> TCC_CCB_DITH6_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= ~TCC_CCB_DITH6_DITHERCYB_Msk;
+	tmp |= TCC_CCB_DITH6_DITHERCYB(data);
+	((Tcc *)hw)->CCB[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH6_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH6_DITHERCYB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH6_DITHERCYB_Msk) >> TCC_CCB_DITH6_DITHERCYB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH6_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index,
+                                                             hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH6_CCB(mask)) >> TCC_CCB_DITH6_CCB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= ~TCC_CCB_DITH6_CCB_Msk;
+	tmp |= TCC_CCB_DITH6_CCB(data);
+	((Tcc *)hw)->CCB[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH6_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH6_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_DITH6_CCB_Msk) >> TCC_CCB_DITH6_CCB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= TCC_CCB_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_CCB(mask)) >> TCC_CCB_CCB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= ~TCC_CCB_CCB_Msk;
+	tmp |= TCC_CCB_CCB(data);
+	((Tcc *)hw)->CCB[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_CCB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_CCB_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp = (tmp & TCC_CCB_CCB_Msk) >> TCC_CCB_CCB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCB[index].reg;
+}
+
+static inline void hri_tcc_set_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCB[index].reg;
+}
+
+static inline void hri_tcc_set_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCB[index].reg;
+}
+
+static inline void hri_tcc_set_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCB[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCB[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCB[index].reg;
+}
+
+static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = data;
+	((Tcc *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+}
+
+static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+}
+
+static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+}
+
+static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+}
+
+static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+}
+
+static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+}
+
+static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+}
+
+static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+}
+
+static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+}
+
+static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+}
+
+static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+}
+
+static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+}
+
+static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+}
+
+static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+}
+
+static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+}
+
+static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+}
+
+static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+}
+
+static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data)
+{
+	((Tcc *)hw)->INTENSET.reg = data;
+	((Tcc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	((Tcc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ENABLE;
+	tmp |= value << TCC_CTRLA_ENABLE_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RUNSTDBY;
+	tmp |= value << TCC_CTRLA_RUNSTDBY_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ALOCK;
+	tmp |= value << TCC_CTRLA_ALOCK_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN0;
+	tmp |= value << TCC_CTRLA_CPTEN0_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN1;
+	tmp |= value << TCC_CTRLA_CPTEN1_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN2;
+	tmp |= value << TCC_CTRLA_CPTEN2_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN3;
+	tmp |= value << TCC_CTRLA_CPTEN3_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RESOLUTION_Msk;
+	tmp |= TCC_CTRLA_RESOLUTION(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCALER_Msk;
+	tmp |= TCC_CTRLA_PRESCALER(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TCC_CTRLA_PRESCSYNC(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_KEEP;
+	tmp |= value << TCC_FCTRLA_KEEP_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_QUAL;
+	tmp |= value << TCC_FCTRLA_QUAL_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_RESTART;
+	tmp |= value << TCC_FCTRLA_RESTART_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_SRC_Msk;
+	tmp |= TCC_FCTRLA_SRC(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANK_Msk;
+	tmp |= TCC_FCTRLA_BLANK(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_HALT_Msk;
+	tmp |= TCC_FCTRLA_HALT(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CHSEL_Msk;
+	tmp |= TCC_FCTRLA_CHSEL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CAPTURE_Msk;
+	tmp |= TCC_FCTRLA_CAPTURE(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLA_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLA_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_KEEP;
+	tmp |= value << TCC_FCTRLB_KEEP_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_QUAL;
+	tmp |= value << TCC_FCTRLB_QUAL_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_RESTART;
+	tmp |= value << TCC_FCTRLB_RESTART_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_SRC_Msk;
+	tmp |= TCC_FCTRLB_SRC(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANK_Msk;
+	tmp |= TCC_FCTRLB_BLANK(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_HALT_Msk;
+	tmp |= TCC_FCTRLB_HALT(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CHSEL_Msk;
+	tmp |= TCC_FCTRLB_CHSEL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CAPTURE_Msk;
+	tmp |= TCC_FCTRLB_CAPTURE(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLB_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLB_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLB.reg;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN0;
+	tmp |= value << TCC_WEXCTRL_DTIEN0_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN1;
+	tmp |= value << TCC_WEXCTRL_DTIEN1_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN2;
+	tmp |= value << TCC_WEXCTRL_DTIEN2_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN3;
+	tmp |= value << TCC_WEXCTRL_DTIEN3_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_OTMX_Msk;
+	tmp |= TCC_WEXCTRL_OTMX(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTLS_Msk;
+	tmp |= TCC_WEXCTRL_DTLS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTHS_Msk;
+	tmp |= TCC_WEXCTRL_DTHS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->WEXCTRL.reg;
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE0;
+	tmp |= value << TCC_DRVCTRL_NRE0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE1;
+	tmp |= value << TCC_DRVCTRL_NRE1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE2;
+	tmp |= value << TCC_DRVCTRL_NRE2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE3;
+	tmp |= value << TCC_DRVCTRL_NRE3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE4;
+	tmp |= value << TCC_DRVCTRL_NRE4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE5;
+	tmp |= value << TCC_DRVCTRL_NRE5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE6;
+	tmp |= value << TCC_DRVCTRL_NRE6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE7;
+	tmp |= value << TCC_DRVCTRL_NRE7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV0;
+	tmp |= value << TCC_DRVCTRL_NRV0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV1;
+	tmp |= value << TCC_DRVCTRL_NRV1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV2;
+	tmp |= value << TCC_DRVCTRL_NRV2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV3;
+	tmp |= value << TCC_DRVCTRL_NRV3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV4;
+	tmp |= value << TCC_DRVCTRL_NRV4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV5;
+	tmp |= value << TCC_DRVCTRL_NRV5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV6;
+	tmp |= value << TCC_DRVCTRL_NRV6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV7;
+	tmp |= value << TCC_DRVCTRL_NRV7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN0;
+	tmp |= value << TCC_DRVCTRL_INVEN0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN1;
+	tmp |= value << TCC_DRVCTRL_INVEN1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN2;
+	tmp |= value << TCC_DRVCTRL_INVEN2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN3;
+	tmp |= value << TCC_DRVCTRL_INVEN3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN4;
+	tmp |= value << TCC_DRVCTRL_INVEN4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN5;
+	tmp |= value << TCC_DRVCTRL_INVEN5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN6;
+	tmp |= value << TCC_DRVCTRL_INVEN6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN7;
+	tmp |= value << TCC_DRVCTRL_INVEN7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL0(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL1(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DRVCTRL.reg;
+}
+
+static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_DBGRUN;
+	tmp |= value << TCC_DBGCTRL_DBGRUN_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_FDDBD;
+	tmp |= value << TCC_DBGCTRL_FDDBD_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_OVFEO;
+	tmp |= value << TCC_EVCTRL_OVFEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TRGEO;
+	tmp |= value << TCC_EVCTRL_TRGEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTEO;
+	tmp |= value << TCC_EVCTRL_CNTEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV0;
+	tmp |= value << TCC_EVCTRL_TCINV0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV1;
+	tmp |= value << TCC_EVCTRL_TCINV1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI0;
+	tmp |= value << TCC_EVCTRL_TCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI1;
+	tmp |= value << TCC_EVCTRL_TCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI0;
+	tmp |= value << TCC_EVCTRL_MCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI1;
+	tmp |= value << TCC_EVCTRL_MCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI2;
+	tmp |= value << TCC_EVCTRL_MCEI2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI3;
+	tmp |= value << TCC_EVCTRL_MCEI3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO0;
+	tmp |= value << TCC_EVCTRL_MCEO0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO1;
+	tmp |= value << TCC_EVCTRL_MCEO1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO2;
+	tmp |= value << TCC_EVCTRL_MCEO2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO3;
+	tmp |= value << TCC_EVCTRL_MCEO3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT0_Msk;
+	tmp |= TCC_EVCTRL_EVACT0(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT1_Msk;
+	tmp |= TCC_EVCTRL_EVACT1(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTSEL_Msk;
+	tmp |= TCC_EVCTRL_CNTSEL(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE0;
+	tmp |= value << TCC_PATT_PGE0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE1;
+	tmp |= value << TCC_PATT_PGE1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE2;
+	tmp |= value << TCC_PATT_PGE2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE3;
+	tmp |= value << TCC_PATT_PGE3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE4;
+	tmp |= value << TCC_PATT_PGE4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE5;
+	tmp |= value << TCC_PATT_PGE5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE6;
+	tmp |= value << TCC_PATT_PGE6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE7;
+	tmp |= value << TCC_PATT_PGE7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV0;
+	tmp |= value << TCC_PATT_PGV0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV1;
+	tmp |= value << TCC_PATT_PGV1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV2;
+	tmp |= value << TCC_PATT_PGV2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV3;
+	tmp |= value << TCC_PATT_PGV3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV4;
+	tmp |= value << TCC_PATT_PGV4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV5;
+	tmp |= value << TCC_PATT_PGV5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV6;
+	tmp |= value << TCC_PATT_PGV6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV7;
+	tmp |= value << TCC_PATT_PGV7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PATT.reg;
+}
+
+static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CIPEREN;
+	tmp |= value << TCC_WAVE_CIPEREN_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN0;
+	tmp |= value << TCC_WAVE_CICCEN0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN1;
+	tmp |= value << TCC_WAVE_CICCEN1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN2;
+	tmp |= value << TCC_WAVE_CICCEN2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN3;
+	tmp |= value << TCC_WAVE_CICCEN3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL0;
+	tmp |= value << TCC_WAVE_POL0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL1;
+	tmp |= value << TCC_WAVE_POL1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL2;
+	tmp |= value << TCC_WAVE_POL2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL3;
+	tmp |= value << TCC_WAVE_POL3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP0;
+	tmp |= value << TCC_WAVE_SWAP0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP1;
+	tmp |= value << TCC_WAVE_SWAP1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP2;
+	tmp |= value << TCC_WAVE_SWAP2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP3;
+	tmp |= value << TCC_WAVE_SWAP3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_WAVEGEN_Msk;
+	tmp |= TCC_WAVE_WAVEGEN(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_RAMP_Msk;
+	tmp |= TCC_WAVE_RAMP(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->WAVE.reg;
+}
+
+static inline void hri_tcc_set_PATTB_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGEB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGEB0) >> TCC_PATTB_PGEB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGEB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGEB0;
+	tmp |= value << TCC_PATTB_PGEB0_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGEB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGEB1) >> TCC_PATTB_PGEB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGEB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGEB1;
+	tmp |= value << TCC_PATTB_PGEB1_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGEB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGEB2) >> TCC_PATTB_PGEB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGEB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGEB2;
+	tmp |= value << TCC_PATTB_PGEB2_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGEB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGEB3) >> TCC_PATTB_PGEB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGEB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGEB3;
+	tmp |= value << TCC_PATTB_PGEB3_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGEB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGEB4) >> TCC_PATTB_PGEB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGEB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGEB4;
+	tmp |= value << TCC_PATTB_PGEB4_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGEB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGEB5) >> TCC_PATTB_PGEB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGEB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGEB5;
+	tmp |= value << TCC_PATTB_PGEB5_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGEB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGEB6) >> TCC_PATTB_PGEB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGEB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGEB6;
+	tmp |= value << TCC_PATTB_PGEB6_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGEB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGEB7) >> TCC_PATTB_PGEB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGEB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGEB7;
+	tmp |= value << TCC_PATTB_PGEB7_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGVB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGVB0) >> TCC_PATTB_PGVB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGVB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGVB0;
+	tmp |= value << TCC_PATTB_PGVB0_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGVB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGVB1) >> TCC_PATTB_PGVB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGVB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGVB1;
+	tmp |= value << TCC_PATTB_PGVB1_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGVB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGVB2) >> TCC_PATTB_PGVB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGVB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGVB2;
+	tmp |= value << TCC_PATTB_PGVB2_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGVB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGVB3) >> TCC_PATTB_PGVB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGVB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGVB3;
+	tmp |= value << TCC_PATTB_PGVB3_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGVB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGVB4) >> TCC_PATTB_PGVB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGVB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGVB4;
+	tmp |= value << TCC_PATTB_PGVB4_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGVB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGVB5) >> TCC_PATTB_PGVB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGVB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGVB5;
+	tmp |= value << TCC_PATTB_PGVB5_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGVB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGVB6) >> TCC_PATTB_PGVB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGVB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGVB6;
+	tmp |= value << TCC_PATTB_PGVB6_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTB_PGVB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp = (tmp & TCC_PATTB_PGVB7) >> TCC_PATTB_PGVB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTB_PGVB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= ~TCC_PATTB_PGVB7;
+	tmp |= value << TCC_PATTB_PGVB7_Pos;
+	((Tcc *)hw)->PATTB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattb_reg_t hri_tcc_get_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattb_reg_t hri_tcc_read_PATTB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PATTB.reg;
+}
+
+static inline void hri_tcc_set_WAVEB_CIPERENB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CIPERENB;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_CIPERENB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_CIPERENB) >> TCC_WAVEB_CIPERENB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_CIPERENB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_CIPERENB;
+	tmp |= value << TCC_WAVEB_CIPERENB_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_CIPERENB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CIPERENB;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_CIPERENB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CIPERENB;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_CICCENB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_CICCENB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_CICCENB0) >> TCC_WAVEB_CICCENB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_CICCENB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_CICCENB0;
+	tmp |= value << TCC_WAVEB_CICCENB0_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_CICCENB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_CICCENB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_CICCENB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_CICCENB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_CICCENB1) >> TCC_WAVEB_CICCENB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_CICCENB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_CICCENB1;
+	tmp |= value << TCC_WAVEB_CICCENB1_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_CICCENB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_CICCENB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_CICCENB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_CICCENB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_CICCENB2) >> TCC_WAVEB_CICCENB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_CICCENB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_CICCENB2;
+	tmp |= value << TCC_WAVEB_CICCENB2_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_CICCENB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_CICCENB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_CICCENB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_CICCENB3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_CICCENB3) >> TCC_WAVEB_CICCENB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_CICCENB3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_CICCENB3;
+	tmp |= value << TCC_WAVEB_CICCENB3_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_CICCENB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_CICCENB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_POLB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_POLB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_POLB0) >> TCC_WAVEB_POLB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_POLB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_POLB0;
+	tmp |= value << TCC_WAVEB_POLB0_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_POLB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_POLB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_POLB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_POLB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_POLB1) >> TCC_WAVEB_POLB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_POLB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_POLB1;
+	tmp |= value << TCC_WAVEB_POLB1_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_POLB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_POLB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_POLB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_POLB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_POLB2) >> TCC_WAVEB_POLB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_POLB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_POLB2;
+	tmp |= value << TCC_WAVEB_POLB2_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_POLB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_POLB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_POLB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_POLB3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_POLB3) >> TCC_WAVEB_POLB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_POLB3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_POLB3;
+	tmp |= value << TCC_WAVEB_POLB3_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_POLB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_POLB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_SWAPB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_SWAPB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_SWAPB0) >> TCC_WAVEB_SWAPB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_SWAPB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_SWAPB0;
+	tmp |= value << TCC_WAVEB_SWAPB0_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_SWAPB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_SWAPB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_SWAPB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_SWAPB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_SWAPB1) >> TCC_WAVEB_SWAPB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_SWAPB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_SWAPB1;
+	tmp |= value << TCC_WAVEB_SWAPB1_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_SWAPB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_SWAPB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_SWAPB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_SWAPB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_SWAPB2) >> TCC_WAVEB_SWAPB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_SWAPB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_SWAPB2;
+	tmp |= value << TCC_WAVEB_SWAPB2_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_SWAPB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_SWAPB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_SWAPB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVEB_SWAPB3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_SWAPB3) >> TCC_WAVEB_SWAPB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_SWAPB3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_SWAPB3;
+	tmp |= value << TCC_WAVEB_SWAPB3_Pos;
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_SWAPB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_SWAPB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_WAVEGENB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_WAVEGENB(mask)) >> TCC_WAVEB_WAVEGENB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_WAVEGENB_Msk;
+	tmp |= TCC_WAVEB_WAVEGENB(data);
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_WAVEGENB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_WAVEGENB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_WAVEGENB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_WAVEGENB_Msk) >> TCC_WAVEB_WAVEGENB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_RAMPB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_RAMPB(mask)) >> TCC_WAVEB_RAMPB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= ~TCC_WAVEB_RAMPB_Msk;
+	tmp |= TCC_WAVEB_RAMPB(data);
+	((Tcc *)hw)->WAVEB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_RAMPB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_RAMPB(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_RAMPB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp = (tmp & TCC_WAVEB_RAMPB_Msk) >> TCC_WAVEB_RAMPB_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVEB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVEB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->WAVEB.reg;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PATTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATTB) >> TCC_SYNCBUSY_PATTB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_WAVEB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVEB) >> TCC_SYNCBUSY_WAVEB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PERB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PERB) >> TCC_SYNCBUSY_PERB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CCB0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB0) >> TCC_SYNCBUSY_CCB0_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CCB1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB1) >> TCC_SYNCBUSY_CCB1_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CCB2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB2) >> TCC_SYNCBUSY_CCB2_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CCB3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB3) >> TCC_SYNCBUSY_CCB3_Pos;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg;
+}
+
+static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PATTBV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBV) >> TCC_STATUS_PATTBV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PATTBV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBV;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_WAVEBV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_WAVEBV) >> TCC_STATUS_WAVEBV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_WAVEBV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_WAVEBV;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PERBV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBV) >> TCC_STATUS_PERBV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PERBV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBV;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBV0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV0) >> TCC_STATUS_CCBV0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBV1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV1) >> TCC_STATUS_CCBV1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBV2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV2) >> TCC_STATUS_CCBV2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBV3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV3) >> TCC_STATUS_CCBV3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TCC_D21_H_INCLUDED */
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_usb_d21.h b/atmel-samd/asf4/samd21/hri/hri_usb_d21.h
new file mode 100644
index 000000000..f0aa01f37
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_usb_d21.h
@@ -0,0 +1,9811 @@
+/**
+ * \file
+ *
+ * \brief SAM USB
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_USB_COMPONENT_
+#ifndef _HRI_USB_D21_H_INCLUDED_
+#define _HRI_USB_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_USB_CRITICAL_SECTIONS)
+#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define USB_CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t;
+typedef uint16_t hri_usbdesc_bank_extreg_reg_t;
+typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t;
+typedef uint16_t hri_usbdevice_ctrlb_reg_t;
+typedef uint16_t hri_usbdevice_descriptor_extreg_reg_t;
+typedef uint16_t hri_usbdevice_epintsmry_reg_t;
+typedef uint16_t hri_usbdevice_fnum_reg_t;
+typedef uint16_t hri_usbdevice_intenset_reg_t;
+typedef uint16_t hri_usbdevice_intflag_reg_t;
+typedef uint16_t hri_usbdevice_padcal_reg_t;
+typedef uint16_t hri_usbhost_ctrlb_reg_t;
+typedef uint16_t hri_usbhost_descriptor_ctrl_pipe_reg_t;
+typedef uint16_t hri_usbhost_descriptor_extreg_reg_t;
+typedef uint16_t hri_usbhost_descriptor_status_pipe_reg_t;
+typedef uint16_t hri_usbhost_fnum_reg_t;
+typedef uint16_t hri_usbhost_intenset_reg_t;
+typedef uint16_t hri_usbhost_intflag_reg_t;
+typedef uint16_t hri_usbhost_padcal_reg_t;
+typedef uint16_t hri_usbhost_pintsmry_reg_t;
+typedef uint32_t hri_usbdesc_bank_addr_reg_t;
+typedef uint32_t hri_usbdesc_bank_pcksize_reg_t;
+typedef uint32_t hri_usbdevice_descadd_reg_t;
+typedef uint32_t hri_usbdevice_descriptor_addr_reg_t;
+typedef uint32_t hri_usbdevice_descriptor_pcksize_reg_t;
+typedef uint32_t hri_usbhost_descadd_reg_t;
+typedef uint32_t hri_usbhost_descriptor_addr_reg_t;
+typedef uint32_t hri_usbhost_descriptor_pcksize_reg_t;
+typedef uint8_t  hri_usbdesc_bank_status_bk_reg_t;
+typedef uint8_t  hri_usbdevice_ctrla_reg_t;
+typedef uint8_t  hri_usbdevice_dadd_reg_t;
+typedef uint8_t  hri_usbdevice_descriptor_status_bk_reg_t;
+typedef uint8_t  hri_usbdevice_epcfg_reg_t;
+typedef uint8_t  hri_usbdevice_epintenset_reg_t;
+typedef uint8_t  hri_usbdevice_epintflag_reg_t;
+typedef uint8_t  hri_usbdevice_epstatus_reg_t;
+typedef uint8_t  hri_usbdevice_fsmstatus_reg_t;
+typedef uint8_t  hri_usbdevice_qosctrl_reg_t;
+typedef uint8_t  hri_usbdevice_status_reg_t;
+typedef uint8_t  hri_usbdevice_syncbusy_reg_t;
+typedef uint8_t  hri_usbendpoint_epcfg_reg_t;
+typedef uint8_t  hri_usbendpoint_epintenset_reg_t;
+typedef uint8_t  hri_usbendpoint_epintflag_reg_t;
+typedef uint8_t  hri_usbendpoint_epstatus_reg_t;
+typedef uint8_t  hri_usbhost_binterval_reg_t;
+typedef uint8_t  hri_usbhost_ctrla_reg_t;
+typedef uint8_t  hri_usbhost_descriptor_status_bk_reg_t;
+typedef uint8_t  hri_usbhost_flenhigh_reg_t;
+typedef uint8_t  hri_usbhost_fsmstatus_reg_t;
+typedef uint8_t  hri_usbhost_hsofc_reg_t;
+typedef uint8_t  hri_usbhost_pcfg_reg_t;
+typedef uint8_t  hri_usbhost_pintenset_reg_t;
+typedef uint8_t  hri_usbhost_pintflag_reg_t;
+typedef uint8_t  hri_usbhost_pstatus_reg_t;
+typedef uint8_t  hri_usbhost_qosctrl_reg_t;
+typedef uint8_t  hri_usbhost_status_reg_t;
+typedef uint8_t  hri_usbhost_syncbusy_reg_t;
+typedef uint8_t  hri_usbpipe_binterval_reg_t;
+typedef uint8_t  hri_usbpipe_pcfg_reg_t;
+typedef uint8_t  hri_usbpipe_pintenset_reg_t;
+typedef uint8_t  hri_usbpipe_pintflag_reg_t;
+typedef uint8_t  hri_usbpipe_pstatus_reg_t;
+
+static inline void hri_usbdevice_wait_for_sync(const void *const hw, hri_usbdevice_syncbusy_reg_t reg)
+{
+	while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_usbdevice_is_syncing(const void *const hw, hri_usbdevice_syncbusy_reg_t reg)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_usbhost_wait_for_sync(const void *const hw, hri_usbhost_syncbusy_reg_t reg)
+{
+	while (((Usb *)hw)->HOST.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_usbhost_is_syncing(const void *const hw, hri_usbhost_syncbusy_reg_t reg)
+{
+	return ((Usb *)hw)->HOST.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)
+	       >> USB_HOST_PSTATUS_DTGL_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK)
+	       >> USB_HOST_PSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE)
+	       >> USB_HOST_PSTATUS_PFREEZE_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY)
+	       >> USB_HOST_PSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY)
+	       >> USB_HOST_PSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbpipe_pstatus_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask;
+}
+
+static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbpipe_pstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pstatus_reg_t data)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data;
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pstatus_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0)
+	       >> USB_HOST_PINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1)
+	       >> USB_HOST_PINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL)
+	       >> USB_HOST_PINTENSET_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR)
+	       >> USB_HOST_PINTENSET_PERR_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP)
+	       >> USB_HOST_PINTENSET_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL)
+	       >> USB_HOST_PINTENSET_STALL_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pintenset_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask;
+}
+
+static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbpipe_pintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg;
+}
+
+static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbpipe_pintenset_reg_t data)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data;
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbpipe_pintenset_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbpipe_pintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbpipe_pintflag_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_BK;
+	tmp |= value << USB_HOST_PCFG_BK_Pos;
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTOKEN_Msk;
+	tmp |= USB_HOST_PCFG_PTOKEN(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTYPE_Msk;
+	tmp |= USB_HOST_PCFG_PTYPE(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+}
+
+static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                   uint8_t           submodule_index,
+                                                                                   hri_usbpipe_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_binterval_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk;
+	tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbpipe_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_binterval_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+}
+
+static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)
+	       >> USB_HOST_PSTATUS_DTGL_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK)
+	       >> USB_HOST_PSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE)
+	       >> USB_HOST_PSTATUS_PFREEZE_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY)
+	       >> USB_HOST_PSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY)
+	       >> USB_HOST_PSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_pstatus_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask;
+}
+
+static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_pstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg;
+}
+
+static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pstatus_reg_t data)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pstatus_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0)
+	       >> USB_HOST_PINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1)
+	       >> USB_HOST_PINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL)
+	       >> USB_HOST_PINTENSET_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR)
+	       >> USB_HOST_PINTENSET_PERR_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP)
+	       >> USB_HOST_PINTENSET_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL)
+	       >> USB_HOST_PINTENSET_STALL_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pintenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask;
+}
+
+static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbhost_pintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg;
+}
+
+static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_pintenset_reg_t data)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_pintenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbhost_pintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbhost_pintflag_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask;
+}
+
+static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_BK;
+	tmp |= value << USB_HOST_PCFG_BK_Pos;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTOKEN_Msk;
+	tmp |= USB_HOST_PCFG_PTOKEN(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTYPE_Msk;
+	tmp |= USB_HOST_PCFG_PTYPE(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+}
+
+static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                   uint8_t           submodule_index,
+                                                                                   hri_usbhost_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_binterval_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk;
+	tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbhost_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_binterval_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+}
+
+static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+}
+
+static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF;
+}
+
+static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+}
+
+static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST;
+}
+
+static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+}
+
+static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM;
+}
+
+static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM;
+}
+
+static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER;
+}
+
+static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+}
+
+static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN;
+}
+
+static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+}
+
+static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC;
+}
+
+static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = mask;
+}
+
+static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const          hw,
+                                                                   hri_usbhost_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.INTENSET.reg;
+}
+
+static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = data;
+	((Usb *)hw)->HOST.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = mask;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+}
+
+static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+}
+
+static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+}
+
+static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+}
+
+static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+}
+
+static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+}
+
+static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_usbhost_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.INTFLAG.reg;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = mask;
+}
+
+static inline void hri_usbhost_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_ENABLE;
+	tmp |= value << USB_CTRLA_ENABLE_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_RUNSTDBY;
+	tmp |= value << USB_CTRLA_RUNSTDBY_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLA_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLA_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_MODE;
+	tmp |= value << USB_CTRLA_MODE_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrla_reg_t hri_usbhost_get_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrla_reg_t hri_usbhost_read_CTRLA_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.CTRLA.reg;
+}
+
+static inline void hri_usbhost_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_CQOS_bf(const void *const         hw,
+                                                                        hri_usbhost_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_CQOS_Msk;
+	tmp |= USB_QOSCTRL_CQOS(data);
+	((Usb *)hw)->HOST.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_CQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_DQOS_bf(const void *const         hw,
+                                                                        hri_usbhost_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_DQOS_Msk;
+	tmp |= USB_QOSCTRL_DQOS(data);
+	((Usb *)hw)->HOST.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_reg(const void *const         hw,
+                                                                    hri_usbhost_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.QOSCTRL.reg;
+}
+
+static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_RESUME;
+	tmp |= value << USB_HOST_CTRLB_RESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_TSTJ;
+	tmp |= value << USB_HOST_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_TSTK;
+	tmp |= value << USB_HOST_CTRLB_TSTK_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_SOFE;
+	tmp |= value << USB_HOST_CTRLB_SOFE_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_BUSRESET;
+	tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_VBUSOK;
+	tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_L1RESUME;
+	tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const       hw,
+                                                                       hri_usbhost_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk;
+	tmp |= USB_HOST_CTRLB_SPDCONF(data);
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.CTRLB.reg;
+}
+
+static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= ~USB_HOST_HSOFC_FLENCE;
+	tmp |= value << USB_HOST_HSOFC_FLENCE_Pos;
+	((Usb *)hw)->HOST.HSOFC.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= ~USB_HOST_HSOFC_FLENC_Msk;
+	tmp |= USB_HOST_HSOFC_FLENC(data);
+	((Usb *)hw)->HOST.HSOFC.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.HSOFC.reg;
+}
+
+static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= ~USB_HOST_FNUM_MFNUM_Msk;
+	tmp |= USB_HOST_FNUM_MFNUM(data);
+	((Usb *)hw)->HOST.FNUM.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= ~USB_HOST_FNUM_FNUM_Msk;
+	tmp |= USB_HOST_FNUM_FNUM(data);
+	((Usb *)hw)->HOST.FNUM.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FNUM.reg;
+}
+
+static inline void hri_usbhost_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_DESCADD_bf(const void *const         hw,
+                                                                           hri_usbhost_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp &= ~USB_DESCADD_DESCADD_Msk;
+	tmp |= USB_DESCADD_DESCADD(data);
+	((Usb *)hw)->HOST.DESCADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_DESCADD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_reg(const void *const         hw,
+                                                                    hri_usbhost_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.DESCADD.reg;
+}
+
+static inline void hri_usbhost_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSP_bf(const void *const        hw,
+                                                                        hri_usbhost_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSP_Msk;
+	tmp |= USB_PADCAL_TRANSP(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSN_bf(const void *const        hw,
+                                                                        hri_usbhost_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSN_Msk;
+	tmp |= USB_PADCAL_TRANSN(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRIM_bf(const void *const        hw,
+                                                                      hri_usbhost_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRIM_Msk;
+	tmp |= USB_PADCAL_TRIM(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRIM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.PADCAL.reg;
+}
+
+static inline bool hri_usbhost_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_usbhost_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_usbhost_syncbusy_reg_t hri_usbhost_get_SYNCBUSY_reg(const void *const          hw,
+                                                                      hri_usbhost_syncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_syncbusy_reg_t hri_usbhost_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.SYNCBUSY.reg;
+}
+
+static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(const void *const           hw,
+                                                                                hri_usbhost_fsmstatus_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_reg(const void *const           hw,
+                                                                        hri_usbhost_fsmstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FSMSTATUS.reg;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const          hw,
+                                                                              hri_usbhost_flenhigh_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const          hw,
+                                                                      hri_usbhost_flenhigh_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.FLENHIGH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FLENHIGH.reg;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const          hw,
+                                                                      hri_usbhost_pintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.PINTSMRY.reg;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const        hw,
+                                                                       hri_usbhost_status_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos;
+}
+
+static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const        hw,
+                                                                           hri_usbhost_status_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos;
+}
+
+static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.STATUS.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                                 hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const           hw,
+                                                                             hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                     hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                     hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                      hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                            hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                            hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                             hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                                hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                  hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                  hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                   hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const             hw,
+                                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t
+hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const                hw,
+                                                             hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdevice_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                         hri_usbdevice_descriptor_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdevice_descriptor_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdevice_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdevice_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                            uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdevice_descriptor_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdevice_descriptor_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdevice_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdevice_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw,
+                                                                                        uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                      bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdevice_descriptor_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void
+hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdevice_descriptor_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                            hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdevice_descriptor_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdevice_descriptor_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdevice_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                              uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdevice_descriptor_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdevice_descriptor_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdevice_descriptor_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdevice_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                            uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR)
+	       >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_status_bk_reg_t
+hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdevice_descriptor_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdevice_descriptor_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descriptor_status_bk_reg_t
+hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+}
+
+static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const            hw,
+                                                                       hri_usbdevice_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = data;
+	((Usb *)hw)->DEVICE.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = mask;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_usbdevice_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_ENABLE;
+	tmp |= value << USB_CTRLA_ENABLE_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_RUNSTDBY;
+	tmp |= value << USB_CTRLA_RUNSTDBY_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLA_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLA_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_MODE;
+	tmp |= value << USB_CTRLA_MODE_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_get_CTRLA_reg(const void *const         hw,
+                                                                    hri_usbdevice_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_read_CTRLA_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.CTRLA.reg;
+}
+
+static inline void hri_usbdevice_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_CQOS_bf(const void *const           hw,
+                                                                            hri_usbdevice_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_CQOS_Msk;
+	tmp |= USB_QOSCTRL_CQOS(data);
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_CQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_DQOS_bf(const void *const           hw,
+                                                                            hri_usbdevice_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_DQOS_Msk;
+	tmp |= USB_QOSCTRL_DQOS(data);
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_reg(const void *const           hw,
+                                                                        hri_usbdevice_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+}
+
+static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_DETACH;
+	tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_UPRSM;
+	tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_NREPLY;
+	tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTJ;
+	tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTK;
+	tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_OPMODE2;
+	tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_GNAK;
+	tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk;
+	tmp |= USB_DEVICE_CTRLB_SPDCONF(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk;
+	tmp |= USB_DEVICE_CTRLB_LPMHDSK(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.CTRLB.reg;
+}
+
+static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_ADDEN;
+	tmp |= value << USB_DEVICE_DADD_ADDEN_Pos;
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const        hw,
+                                                                      hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_DADD_Msk;
+	tmp |= USB_DEVICE_DADD_DADD(data);
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DADD.reg;
+}
+
+static inline void hri_usbdevice_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_DESCADD_bf(const void *const           hw,
+                                                                               hri_usbdevice_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp &= ~USB_DESCADD_DESCADD_Msk;
+	tmp |= USB_DESCADD_DESCADD(data);
+	((Usb *)hw)->DEVICE.DESCADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_DESCADD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_reg(const void *const           hw,
+                                                                        hri_usbdevice_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DESCADD.reg;
+}
+
+static inline void hri_usbdevice_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSP_bf(const void *const          hw,
+                                                                            hri_usbdevice_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSP_Msk;
+	tmp |= USB_PADCAL_TRANSP(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSN_bf(const void *const          hw,
+                                                                            hri_usbdevice_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSN_Msk;
+	tmp |= USB_PADCAL_TRANSN(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRIM_bf(const void *const          hw,
+                                                                          hri_usbdevice_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRIM_Msk;
+	tmp |= USB_PADCAL_TRIM(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRIM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_reg(const void *const          hw,
+                                                                      hri_usbdevice_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.PADCAL.reg;
+}
+
+static inline bool hri_usbdevice_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_usbdevice_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_get_SYNCBUSY_reg(const void *const            hw,
+                                                                          hri_usbdevice_syncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const          hw,
+                                                                           hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const          hw,
+                                                                               hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const          hw,
+                                                                      hri_usbdevice_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.STATUS.reg;
+}
+
+static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(const void *const             hw,
+                                                                                    hri_usbdevice_fsmstatus_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_reg(const void *const             hw,
+                                                                            hri_usbdevice_fsmstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FSMSTATUS.reg;
+}
+
+static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const        hw,
+                                                                       hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const        hw,
+                                                                      hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FNUM.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const             hw,
+                                                                            hri_usbdevice_epintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t
+hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t
+hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t
+hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw,
+                                                                                 uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbendpoint_epintflag_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdevice_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_epintenset_reg_t
+hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbdevice_epintflag_reg_t
+hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw,
+                                                                             uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbdevice_epintflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                               hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_HOST_ADDR_ADDR_Msk;
+	tmp |= USB_HOST_ADDR_ADDR(data);
+	((UsbHostDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const           hw,
+                                                                           hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                    hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                        hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                           hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_SIZE(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                                     hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_SUBPID_Msk;
+	tmp |= USB_HOST_EXTREG_SUBPID(data);
+	((UsbHostDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk;
+	tmp |= USB_HOST_EXTREG_VARIABLE(data);
+	((UsbHostDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const             hw,
+                                                                               hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->EXTREG.reg;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PDADDR(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PERMAX(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t
+hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER)
+	       >> USB_HOST_STATUS_PIPE_DAPIDER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER)
+	       >> USB_HOST_STATUS_PIPE_CRC16ER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t
+hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask))
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const                  hw,
+                                                                  hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk)
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t
+hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const                  hw,
+                                                             hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbhost_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_addr_reg_t
+hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                       hri_usbhost_descriptor_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbhost_descriptor_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_HOST_ADDR_ADDR_Msk;
+	tmp |= USB_HOST_ADDR_ADDR(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbhost_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbhost_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                        uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbhost_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_addr_reg_t
+hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                   hri_usbhost_descriptor_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbhost_descriptor_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbhost_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbhost_descriptor_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                    bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbhost_descriptor_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_pcksize_reg_t
+hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbhost_descriptor_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                             uint8_t           submodule_index,
+                                                                             hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_pcksize_reg_t
+hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                          hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbhost_descriptor_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_SIZE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw,
+                                                                                              uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                      hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbhost_descriptor_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbhost_descriptor_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                          uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                           hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbhost_descriptor_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_SUBPID_Msk;
+	tmp |= USB_HOST_EXTREG_SUBPID(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw,
+                                                                                              uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbhost_descriptor_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk;
+	tmp |= USB_HOST_EXTREG_VARIABLE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw,
+                                                                                                uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbhost_descriptor_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbhost_descriptor_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                        uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_descriptor_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PDADDR(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_descriptor_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_descriptor_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PERMAX(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbhost_descriptor_ctrl_pipe_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_descriptor_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw,
+                                                                                              uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR)
+	       >> USB_HOST_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW)
+	       >> USB_HOST_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_status_bk_reg_t
+hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbhost_descriptor_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbhost_descriptor_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw,
+                                                                                              uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg;
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER)
+	       >> USB_HOST_STATUS_PIPE_DTGLER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER)
+	       >> USB_HOST_STATUS_PIPE_DAPIDER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER)
+	       >> USB_HOST_STATUS_PIPE_PIDER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER)
+	       >> USB_HOST_STATUS_PIPE_TOUTER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER)
+	       >> USB_HOST_STATUS_PIPE_CRC16ER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_status_pipe_reg_t
+hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_descriptor_status_pipe_reg_t mask)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask))
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_descriptor_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_status_pipe_reg_t
+hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk)
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline hri_usbhost_descriptor_status_pipe_reg_t
+hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbhost_descriptor_status_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbhost_descriptor_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_descriptor_status_pipe_reg_t
+hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_USB_D21_H_INCLUDED */
+#endif /* _SAMD21_USB_COMPONENT_ */
diff --git a/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h b/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h
new file mode 100644
index 000000000..90c307ba6
--- /dev/null
+++ b/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h
@@ -0,0 +1,616 @@
+/**
+ * \file
+ *
+ * \brief SAM WDT
+ *
+ * Copyright (C) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+#ifdef _SAMD21_WDT_COMPONENT_
+#ifndef _HRI_WDT_D21_H_INCLUDED_
+#define _HRI_WDT_D21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_WDT_CRITICAL_SECTIONS)
+#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define WDT_CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_wdt_clear_reg_t;
+typedef uint8_t hri_wdt_config_reg_t;
+typedef uint8_t hri_wdt_ctrl_reg_t;
+typedef uint8_t hri_wdt_ewctrl_reg_t;
+typedef uint8_t hri_wdt_intenset_reg_t;
+typedef uint8_t hri_wdt_intflag_reg_t;
+typedef uint8_t hri_wdt_status_reg_t;
+
+static inline void hri_wdt_wait_for_sync(const void *const hw)
+{
+	while (((const Wdt *)hw)->STATUS.bit.SYNCBUSY)
+		;
+}
+
+static inline bool hri_wdt_is_syncing(const void *const hw)
+{
+	return ((const Wdt *)hw)->STATUS.bit.SYNCBUSY;
+}
+
+static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+}
+
+static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos;
+}
+
+static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+	} else {
+		((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+	}
+}
+
+static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+}
+
+static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTENSET.reg;
+}
+
+static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data)
+{
+	((Wdt *)hw)->INTENSET.reg = data;
+	((Wdt *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	((Wdt *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CLEAR.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg |= WDT_CTRL_ENABLE;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CTRL.reg;
+	tmp = (tmp & WDT_CTRL_ENABLE) >> WDT_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CTRL.reg;
+	tmp &= ~WDT_CTRL_ENABLE;
+	tmp |= value << WDT_CTRL_ENABLE_Pos;
+	((Wdt *)hw)->CTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_ENABLE;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_ENABLE;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRL_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg |= WDT_CTRL_WEN;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRL_WEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CTRL.reg;
+	tmp = (tmp & WDT_CTRL_WEN) >> WDT_CTRL_WEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRL_WEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CTRL.reg;
+	tmp &= ~WDT_CTRL_WEN;
+	tmp |= value << WDT_CTRL_WEN_Pos;
+	((Wdt *)hw)->CTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRL_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_WEN;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRL_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_WEN;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRL_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg |= WDT_CTRL_ALWAYSON;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRL_ALWAYSON_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CTRL.reg;
+	tmp = (tmp & WDT_CTRL_ALWAYSON) >> WDT_CTRL_ALWAYSON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRL_ALWAYSON_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CTRL.reg;
+	tmp &= ~WDT_CTRL_ALWAYSON;
+	tmp |= value << WDT_CTRL_ALWAYSON_Pos;
+	((Wdt *)hw)->CTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRL_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_ALWAYSON;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRL_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_ALWAYSON;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRL.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrl_reg_t hri_wdt_get_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRL.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRL.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRL.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrl_reg_t hri_wdt_read_CTRL_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->CTRL.reg;
+}
+
+static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_PER_Msk;
+	tmp |= WDT_CONFIG_PER(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_WINDOW_Msk;
+	tmp |= WDT_CONFIG_WINDOW(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	hri_wdt_wait_for_sync(hw);
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw);
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->CONFIG.reg;
+}
+
+static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= ~WDT_EWCTRL_EWOFFSET_Msk;
+	tmp |= WDT_EWCTRL_EWOFFSET(data);
+	((Wdt *)hw)->EWCTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->EWCTRL.reg;
+}
+
+static inline bool hri_wdt_get_STATUS_SYNCBUSY_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->STATUS.reg & WDT_STATUS_SYNCBUSY) >> WDT_STATUS_SYNCBUSY_Pos;
+}
+
+static inline hri_wdt_status_reg_t hri_wdt_get_STATUS_reg(const void *const hw, hri_wdt_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_status_reg_t hri_wdt_read_STATUS_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_WDT_D21_H_INCLUDED */
+#endif /* _SAMD21_WDT_COMPONENT_ */