Move to ASF4 and introduce SAMD51 support. (#258)3.0.0-alpha.0

* atmel-samd: Remove ASF3. This will break builds.

* atmel-samd: Add ASF4 for the SAMD21 and SAMD51.

* Introduce the supervisor concept to facilitate porting.

The supervisor is the code which runs individual MicroPython VMs. By
splitting it out we make it more consistent and easier to find.

This also adds very basic SAMD21 and SAMD51 support using the
supervisor. Only the REPL currently works.

This begins the work for #178.

3 files changed, 56 insertions, 0 deletions

diff --git a/atmel-samd/tools/samd21.json b/atmel-samd/tools/samd21.json
new file mode 100644
index 000000000..8a2b098a1
--- /dev/null
+++ b/atmel-samd/tools/samd21.json
@@ -0,0 +1 @@
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diff --git a/atmel-samd/tools/samd51.json b/atmel-samd/tools/samd51.json
new file mode 100644
index 000000000..5fe35c073
--- /dev/null
+++ b/atmel-samd/tools/samd51.json
@@ -0,0 +1 @@
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(XOSC1)","gclk_arch_gen_4_runstdby":false,"gclk_gen_4_div_sel":false,"gclk_arch_gen_4_oe":false,"gclk_arch_gen_4_oov":false,"gclk_arch_gen_4_idc":false,"gclk_arch_gen_4_enable":false,"gclk_gen_4_div":1,"enable_gclk_gen_5":false,"gclk_gen_5_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_5_runstdby":false,"gclk_gen_5_div_sel":false,"gclk_arch_gen_5_oe":false,"gclk_arch_gen_5_oov":false,"gclk_arch_gen_5_idc":false,"gclk_arch_gen_5_enable":false,"gclk_gen_5_div":1,"enable_gclk_gen_6":false,"gclk_gen_6_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_6_runstdby":false,"gclk_gen_6_div_sel":false,"gclk_arch_gen_6_oe":false,"gclk_arch_gen_6_oov":false,"gclk_arch_gen_6_idc":false,"gclk_arch_gen_6_enable":false,"gclk_gen_6_div":1,"enable_gclk_gen_7":false,"gclk_gen_7_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_7_runstdby":false,"gclk_gen_7_div_sel":false,"gclk_arch_gen_7_oe":false,"gclk_arch_gen_7_oov":false,"gclk_arch_gen_7_idc":false,"gclk_arch_gen_7_enable":false,"gclk_gen_7_div":1,"enable_gclk_gen_8":false,"gclk_gen_8_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_8_runstdby":false,"gclk_gen_8_div_sel":false,"gclk_arch_gen_8_oe":false,"gclk_arch_gen_8_oov":false,"gclk_arch_gen_8_idc":false,"gclk_arch_gen_8_enable":false,"gclk_gen_8_div":1,"enable_gclk_gen_9":false,"gclk_gen_9_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_9_runstdby":false,"gclk_gen_9_div_sel":false,"gclk_arch_gen_9_oe":false,"gclk_arch_gen_9_oov":false,"gclk_arch_gen_9_idc":false,"gclk_arch_gen_9_enable":false,"gclk_gen_9_div":1,"enable_gclk_gen_10":false,"gclk_gen_10_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_10_runstdby":false,"gclk_gen_10_div_sel":false,"gclk_arch_gen_10_oe":false,"gclk_arch_gen_10_oov":false,"gclk_arch_gen_10_idc":false,"gclk_arch_gen_10_enable":false,"gclk_gen_10_div":1,"enable_gclk_gen_11":false,"gclk_gen_11_oscillator":"External Crystal Oscillator 8-48MHz (XOSC1)","gclk_arch_gen_11_runstdby":false,"gclk_gen_11_div_sel":false,"gclk_arch_gen_11_oe":false,"gclk_arch_gen_11_oov":false,"gclk_arch_gen_11_idc":false,"gclk_arch_gen_11_enable":false,"gclk_gen_11_div":1},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::GCLK::driver_definition::GCLK::HAL:HPL:GCLK","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK","module":"GCLK"}},{"functionality":null,"identifier":"OSC32KCTRL","user_label":"OSC32KCTRL","api":"HAL:HPL:OSC32KCTRL","configuration":{"enable_rtc_source":false,"rtc_source_oscillator":"32kHz Ultra Low Power Internal Oscillator (OSCULP32K)","rtc_1khz_selection":true,"enable_xosc32k":false,"xosc32k_arch_enable":false,"xosc32k_arch_startup":"62592us","xosc32k_arch_ondemand":true,"xosc32k_arch_runstdby":false,"xosc32k_arch_en1k":false,"xosc32k_arch_en32k":false,"xosc32k_arch_swben":false,"xosc32k_arch_cfden":false,"xosc32k_arch_cfdeo":false,"xosc32k_arch_xtalen":false,"xosc32k_arch_cgm":"Standard mode","enable_osculp32k":true,"osculp32k_calib_enable":false,"osculp32k_calib":0},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::OSC32KCTRL::driver_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL","module":"OSC32KCTRL"}},{"functionality":null,"identifier":"MCLK","user_label":"MCLK","api":"HAL:HPL:MCLK","configuration":{"enable_cpu_clock":true,"cpu_clock_source":"Generic clock generator 0","cpu_div":"1","mclk_arch_lpdiv":"Divide by 4","mclk_arch_bupdiv":"Divide by 8","mclk_arch_hsdiv":"Divide by 1","nvm_wait_states":"0"},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::MCLK::driver_definition::MCLK::HAL:HPL:MCLK","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK","module":"MCLK"},"clocks":{"domain_group":{"nodes":[{"name":"CPU","input":"CPU"}],"configuration":{}}}},{"functionality":null,"identifier":"DMAC","user_label":"DMAC","api":"HAL:HPL:DMAC","configuration":{"dmac_enable":false,"dmac_lvlen0":true,"dmac_rrlvlen0":"Static arbitration scheme for channel with priority 0","dmac_lvlpri0":0,"dmac_lvlen1":true,"dmac_rrlvlen1":"Static arbitration scheme for channel with priority 1","dmac_lvlpri1":0,"dmac_lvlen2":true,"dmac_rrlvlen2":"Static arbitration scheme for channel with priority 2","dmac_lvlpri2":0,"dmac_lvlen3":true,"dmac_rrlvlen3":"Static arbitration scheme for channel with priority 3","dmac_lvlpri3":0,"dmac_dbgrun":false,"dmac_channel_0_settings":false,"dmac_runstdby_0":false,"dmac_trigact_0":"One trigger required for each block transfer","dmac_trifsrc_0":"Only software/event triggers","dmac_lvl_0":"Channel priority 0","dmac_evoe_0":false,"dmac_evie_0":false,"dmac_evact_0":"No action","dmac_stepsize_0":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_0":"Step size settings apply to the destination address","dmac_srcinc_0":false,"dmac_dstinc_0":false,"dmac_beatsize_0":"8-bit bus transfer","dmac_blockact_0":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_0":"Event generation disabled","dmac_channel_1_settings":false,"dmac_runstdby_1":false,"dmac_trigact_1":"One trigger required for each block transfer","dmac_trifsrc_1":"Only software/event triggers","dmac_lvl_1":"Channel priority 0","dmac_evoe_1":false,"dmac_evie_1":false,"dmac_evact_1":"No action","dmac_stepsize_1":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_1":"Step size settings apply to the destination address","dmac_srcinc_1":false,"dmac_dstinc_1":false,"dmac_beatsize_1":"8-bit bus transfer","dmac_blockact_1":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_1":"Event generation disabled","dmac_channel_2_settings":false,"dmac_runstdby_2":false,"dmac_trigact_2":"One trigger required for each block transfer","dmac_trifsrc_2":"Only software/event triggers","dmac_lvl_2":"Channel priority 0","dmac_evoe_2":false,"dmac_evie_2":false,"dmac_evact_2":"No action","dmac_stepsize_2":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_2":"Step size settings apply to the destination address","dmac_srcinc_2":false,"dmac_dstinc_2":false,"dmac_beatsize_2":"8-bit bus transfer","dmac_blockact_2":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_2":"Event generation disabled","dmac_channel_3_settings":false,"dmac_runstdby_3":false,"dmac_trigact_3":"One trigger required for each block transfer","dmac_trifsrc_3":"Only software/event triggers","dmac_lvl_3":"Channel priority 0","dmac_evoe_3":false,"dmac_evie_3":false,"dmac_evact_3":"No action","dmac_stepsize_3":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_3":"Step size settings apply to the destination address","dmac_srcinc_3":false,"dmac_dstinc_3":false,"dmac_beatsize_3":"8-bit bus transfer","dmac_blockact_3":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_3":"Event generation disabled","dmac_channel_4_settings":false,"dmac_runstdby_4":false,"dmac_trigact_4":"One trigger required for each block transfer","dmac_trifsrc_4":"Only software/event triggers","dmac_lvl_4":"Channel priority 0","dmac_evoe_4":false,"dmac_evie_4":false,"dmac_evact_4":"No action","dmac_stepsize_4":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_4":"Step size settings apply to the destination address","dmac_srcinc_4":false,"dmac_dstinc_4":false,"dmac_beatsize_4":"8-bit bus transfer","dmac_blockact_4":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_4":"Event generation disabled","dmac_channel_5_settings":false,"dmac_runstdby_5":false,"dmac_trigact_5":"One trigger required for each block transfer","dmac_trifsrc_5":"Only software/event triggers","dmac_lvl_5":"Channel priority 0","dmac_evoe_5":false,"dmac_evie_5":false,"dmac_evact_5":"No action","dmac_stepsize_5":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_5":"Step size settings apply to the destination address","dmac_srcinc_5":false,"dmac_dstinc_5":false,"dmac_beatsize_5":"8-bit bus transfer","dmac_blockact_5":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_5":"Event generation disabled","dmac_channel_6_settings":false,"dmac_runstdby_6":false,"dmac_trigact_6":"One trigger required for each block transfer","dmac_trifsrc_6":"Only software/event triggers","dmac_lvl_6":"Channel priority 0","dmac_evoe_6":false,"dmac_evie_6":false,"dmac_evact_6":"No action","dmac_stepsize_6":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_6":"Step size settings apply to the destination address","dmac_srcinc_6":false,"dmac_dstinc_6":false,"dmac_beatsize_6":"8-bit bus transfer","dmac_blockact_6":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_6":"Event generation disabled","dmac_channel_7_settings":false,"dmac_runstdby_7":false,"dmac_trigact_7":"One trigger required for each block transfer","dmac_trifsrc_7":"Only software/event triggers","dmac_lvl_7":"Channel priority 0","dmac_evoe_7":false,"dmac_evie_7":false,"dmac_evact_7":"No action","dmac_stepsize_7":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_7":"Step size settings apply to the destination address","dmac_srcinc_7":false,"dmac_dstinc_7":false,"dmac_beatsize_7":"8-bit bus transfer","dmac_blockact_7":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_7":"Event generation disabled","dmac_channel_8_settings":false,"dmac_runstdby_8":false,"dmac_trigact_8":"One trigger required for each block transfer","dmac_trifsrc_8":"Only software/event triggers","dmac_lvl_8":"Channel priority 0","dmac_evoe_8":false,"dmac_evie_8":false,"dmac_evact_8":"No action","dmac_stepsize_8":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_8":"Step size settings apply to the destination address","dmac_srcinc_8":false,"dmac_dstinc_8":false,"dmac_beatsize_8":"8-bit bus transfer","dmac_blockact_8":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_8":"Event generation disabled","dmac_channel_9_settings":false,"dmac_runstdby_9":false,"dmac_trigact_9":"One trigger required for each block transfer","dmac_trifsrc_9":"Only software/event triggers","dmac_lvl_9":"Channel priority 0","dmac_evoe_9":false,"dmac_evie_9":false,"dmac_evact_9":"No action","dmac_stepsize_9":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_9":"Step size settings apply to the destination address","dmac_srcinc_9":false,"dmac_dstinc_9":false,"dmac_beatsize_9":"8-bit bus transfer","dmac_blockact_9":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_9":"Event generation disabled","dmac_channel_10_settings":false,"dmac_runstdby_10":false,"dmac_trigact_10":"One trigger required for each block transfer","dmac_trifsrc_10":"Only software/event triggers","dmac_lvl_10":"Channel priority 0","dmac_evoe_10":false,"dmac_evie_10":false,"dmac_evact_10":"No action","dmac_stepsize_10":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_10":"Step size settings apply to the destination address","dmac_srcinc_10":false,"dmac_dstinc_10":false,"dmac_beatsize_10":"8-bit bus transfer","dmac_blockact_10":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_10":"Event generation disabled","dmac_channel_11_settings":false,"dmac_runstdby_11":false,"dmac_trigact_11":"One trigger required for each block transfer","dmac_trifsrc_11":"Only software/event triggers","dmac_lvl_11":"Channel priority 0","dmac_evoe_11":false,"dmac_evie_11":false,"dmac_evact_11":"No action","dmac_stepsize_11":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_11":"Step size settings apply to the destination address","dmac_srcinc_11":false,"dmac_dstinc_11":false,"dmac_beatsize_11":"8-bit bus transfer","dmac_blockact_11":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_11":"Event generation disabled","dmac_channel_12_settings":false,"dmac_runstdby_12":false,"dmac_trigact_12":"One trigger required for each block transfer","dmac_trifsrc_12":"Only software/event triggers","dmac_lvl_12":"Channel priority 0","dmac_evoe_12":false,"dmac_evie_12":false,"dmac_evact_12":"No action","dmac_stepsize_12":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_12":"Step size settings apply to the destination address","dmac_srcinc_12":false,"dmac_dstinc_12":false,"dmac_beatsize_12":"8-bit bus transfer","dmac_blockact_12":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_12":"Event generation disabled","dmac_channel_13_settings":false,"dmac_runstdby_13":false,"dmac_trigact_13":"One trigger required for each block transfer","dmac_trifsrc_13":"Only software/event triggers","dmac_lvl_13":"Channel priority 0","dmac_evoe_13":false,"dmac_evie_13":false,"dmac_evact_13":"No action","dmac_stepsize_13":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_13":"Step size settings apply to the destination address","dmac_srcinc_13":false,"dmac_dstinc_13":false,"dmac_beatsize_13":"8-bit bus transfer","dmac_blockact_13":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_13":"Event generation disabled","dmac_channel_14_settings":false,"dmac_runstdby_14":false,"dmac_trigact_14":"One trigger required for each block transfer","dmac_trifsrc_14":"Only software/event triggers","dmac_lvl_14":"Channel priority 0","dmac_evoe_14":false,"dmac_evie_14":false,"dmac_evact_14":"No action","dmac_stepsize_14":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_14":"Step size settings apply to the destination address","dmac_srcinc_14":false,"dmac_dstinc_14":false,"dmac_beatsize_14":"8-bit bus transfer","dmac_blockact_14":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_14":"Event generation disabled","dmac_channel_15_settings":false,"dmac_runstdby_15":false,"dmac_trigact_15":"One trigger required for each block transfer","dmac_trifsrc_15":"Only software/event triggers","dmac_lvl_15":"Channel priority 0","dmac_evoe_15":false,"dmac_evie_15":false,"dmac_evact_15":"No action","dmac_stepsize_15":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_15":"Step size settings apply to the destination address","dmac_srcinc_15":false,"dmac_dstinc_15":false,"dmac_beatsize_15":"8-bit bus transfer","dmac_blockact_15":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_15":"Event generation disabled","dmac_channel_16_settings":false,"dmac_runstdby_16":false,"dmac_trigact_16":"One trigger required for each block transfer","dmac_trifsrc_16":"Only software/event triggers","dmac_lvl_16":"Channel priority 0","dmac_evoe_16":false,"dmac_evie_16":false,"dmac_evact_16":"No action","dmac_stepsize_16":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_16":"Step size settings apply to the destination address","dmac_srcinc_16":false,"dmac_dstinc_16":false,"dmac_beatsize_16":"8-bit bus transfer","dmac_blockact_16":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_16":"Event generation disabled","dmac_channel_17_settings":false,"dmac_runstdby_17":false,"dmac_trigact_17":"One trigger required for each block transfer","dmac_trifsrc_17":"Only software/event triggers","dmac_lvl_17":"Channel priority 0","dmac_evoe_17":false,"dmac_evie_17":false,"dmac_evact_17":"No action","dmac_stepsize_17":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_17":"Step size settings apply to the destination address","dmac_srcinc_17":false,"dmac_dstinc_17":false,"dmac_beatsize_17":"8-bit bus transfer","dmac_blockact_17":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_17":"Event generation disabled","dmac_channel_18_settings":false,"dmac_runstdby_18":false,"dmac_trigact_18":"One trigger required for each block transfer","dmac_trifsrc_18":"Only software/event triggers","dmac_lvl_18":"Channel priority 0","dmac_evoe_18":false,"dmac_evie_18":false,"dmac_evact_18":"No action","dmac_stepsize_18":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_18":"Step size settings apply to the destination address","dmac_srcinc_18":false,"dmac_dstinc_18":false,"dmac_beatsize_18":"8-bit bus transfer","dmac_blockact_18":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_18":"Event generation disabled","dmac_channel_19_settings":false,"dmac_runstdby_19":false,"dmac_trigact_19":"One trigger required for each block transfer","dmac_trifsrc_19":"Only software/event triggers","dmac_lvl_19":"Channel priority 0","dmac_evoe_19":false,"dmac_evie_19":false,"dmac_evact_19":"No action","dmac_stepsize_19":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_19":"Step size settings apply to the destination address","dmac_srcinc_19":false,"dmac_dstinc_19":false,"dmac_beatsize_19":"8-bit bus transfer","dmac_blockact_19":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_19":"Event generation disabled","dmac_channel_20_settings":false,"dmac_runstdby_20":false,"dmac_trigact_20":"One trigger required for each block transfer","dmac_trifsrc_20":"Only software/event triggers","dmac_lvl_20":"Channel priority 0","dmac_evoe_20":false,"dmac_evie_20":false,"dmac_evact_20":"No action","dmac_stepsize_20":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_20":"Step size settings apply to the destination address","dmac_srcinc_20":false,"dmac_dstinc_20":false,"dmac_beatsize_20":"8-bit bus transfer","dmac_blockact_20":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_20":"Event generation disabled","dmac_channel_21_settings":false,"dmac_runstdby_21":false,"dmac_trigact_21":"One trigger required for each block transfer","dmac_trifsrc_21":"Only software/event triggers","dmac_lvl_21":"Channel priority 0","dmac_evoe_21":false,"dmac_evie_21":false,"dmac_evact_21":"No action","dmac_stepsize_21":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_21":"Step size settings apply to the destination address","dmac_srcinc_21":false,"dmac_dstinc_21":false,"dmac_beatsize_21":"8-bit bus transfer","dmac_blockact_21":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_21":"Event generation disabled","dmac_channel_22_settings":false,"dmac_runstdby_22":false,"dmac_trigact_22":"One trigger required for each block transfer","dmac_trifsrc_22":"Only software/event triggers","dmac_lvl_22":"Channel priority 0","dmac_evoe_22":false,"dmac_evie_22":false,"dmac_evact_22":"No action","dmac_stepsize_22":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_22":"Step size settings apply to the destination address","dmac_srcinc_22":false,"dmac_dstinc_22":false,"dmac_beatsize_22":"8-bit bus transfer","dmac_blockact_22":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_22":"Event generation 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selected","evsys_channel_7":"No channel output selected","evsys_channel_8":"No channel output selected","evsys_channel_9":"No channel output selected","evsys_channel_10":"No channel output selected","evsys_channel_11":"No channel output selected","evsys_channel_12":"No channel output selected","evsys_channel_17":"No channel output selected","evsys_channel_18":"No channel output selected","evsys_channel_19":"No channel output selected","evsys_channel_20":"No channel output selected","evsys_channel_21":"No channel output selected","evsys_channel_22":"No channel output selected","evsys_channel_23":"No channel output selected","evsys_channel_24":"No channel output selected","evsys_channel_25":"No channel output selected","evsys_channel_26":"No channel output selected","evsys_channel_27":"No channel output selected","evsys_channel_28":"No channel output selected","evsys_channel_29":"No channel output selected","evsys_channel_30":"No channel output selected","evsys_channel_31":"No channel output selected","evsys_channel_32":"No channel output selected","evsys_channel_33":"No channel output selected","evsys_channel_34":"No channel output selected","evsys_channel_35":"No channel output selected","evsys_channel_36":"No channel output selected","evsys_channel_37":"No channel output selected","evsys_channel_38":"No channel output selected","evsys_channel_39":"No channel output selected","evsys_channel_40":"No channel output selected","evsys_channel_41":"No channel output selected","evsys_channel_42":"No channel output selected","evsys_channel_43":"No channel output selected","evsys_channel_44":"No channel output selected","evsys_channel_45":"No channel output selected","evsys_channel_46":"No channel output selected","evsys_channel_47":"No channel output selected","evsys_channel_48":"No channel output selected","evsys_channel_49":"No channel output selected","evsys_channel_50":"No channel output selected","evsys_channel_51":"No channel output selected","evsys_channel_52":"No channel output selected","evsys_channel_53":"No channel output selected","evsys_channel_54":"No channel output selected","evsys_channel_55":"No channel output selected","evsys_channel_56":"No channel output selected","evsys_channel_57":"No channel output selected","evsys_channel_58":"No channel output selected","evsys_channel_59":"No channel output selected","evsys_channel_60":"No channel output selected","evsys_channel_61":"No channel output selected","evsys_channel_62":"No channel output selected","evsys_channel_63":"No channel output selected","evsys_channel_64":"No channel output selected","evsys_channel_65":"No channel output selected","evsys_channel_66":"No channel output selected"},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::EVSYS::driver_definition::Event.System::HAL:Driver:Event.system","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system","module":"EVSYS"},"clocks":{"domain_group":{"nodes":[{"name":"Channel 0","input":"Generic clock generator 0"},{"name":"Channel 1","input":"Generic clock generator 0"},{"name":"Channel 2","input":"Generic clock generator 0"},{"name":"Channel 3","input":"Generic clock generator 0"},{"name":"Channel 4","input":"Generic clock generator 0"},{"name":"Channel 5","input":"Generic clock generator 0"},{"name":"Channel 6","input":"Generic clock generator 0"},{"name":"Channel 7","input":"Generic clock generator 0"},{"name":"Channel 8","input":"Generic clock generator 0"},{"name":"Channel 9","input":"Generic clock generator 0"},{"name":"Channel 10","input":"Generic clock generator 0"},{"name":"Channel 11","input":"Generic clock generator 0"}],"configuration":{"evsys_clk_selection_0":"Generic clock generator 0","evsys_clk_selection_1":"Generic clock generator 0","evsys_clk_selection_2":"Generic clock generator 0","evsys_clk_selection_3":"Generic clock generator 0","evsys_clk_selection_4":"Generic clock generator 0","evsys_clk_selection_5":"Generic clock generator 0","evsys_clk_selection_6":"Generic clock generator 0","evsys_clk_selection_7":"Generic clock generator 0","evsys_clk_selection_8":"Generic clock generator 0","evsys_clk_selection_9":"Generic clock generator 0","evsys_clk_selection_10":"Generic clock generator 0","evsys_clk_selection_11":"Generic clock generator 0"}}}},{"functionality":"PWM","identifier":"PWM_0","user_label":"PWM_0","api":"HAL:Driver:PWM","configuration":{"tc_prescaler":"No division","tc_arch_wave_per_val":1000,"tc_arch_wave_duty_val":500,"tc_mode":"Counter in 16-bit mode","tc_per":50,"tc_arch_presync":"Reload or reset counter on next GCLK","tc_arch_runstdby":false,"tc_arch_ondemand":false,"tc_arch_alock":"The Lock Update bit is not affected on overflow/underflow and re-trigger event","tc_arch_dbgrun":false,"timer_event_control":false,"tc_arch_mceo0":false,"tc_arch_mceo1":false,"tc_arch_ovfeo":false,"tc_arch_tcei":false,"tc_arch_tcinv":false,"tc_arch_evact":"Event action disabled"},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::TC::driver_definition::PWM::HAL:Driver:PWM","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::TC0::driver_config_definition::PWM::HAL:Driver:PWM","module":"TC0"},"clocks":{"domain_group":{"nodes":[{"name":"TC","input":"Generic clock generator 0"}],"configuration":{"tc_gclk_selection":"Generic clock generator 0"}}}},{"functionality":"RAND","identifier":"RAND_0","user_label":"RAND_0","api":"HAL:Driver:RAND_Sync","configuration":{"trng_runstdby":false,"trng_datardyeo":false},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::TRNG::driver_definition::RAND::HAL:Driver:RAND.Sync","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::TRNG::driver_config_definition::RAND::HAL:Driver:RAND.Sync","module":"TRNG"}},{"functionality":"SPI","identifier":"SPI_0","user_label":"SPI_0","api":"HAL:Driver:SPI_Master_Sync","configuration":{"spi_master_rx_enable":true,"spi_master_character_size":"8 bits","spi_master_baud_rate":50000,"spi_master_advanced":false,"spi_master_dummybyte":511,"spi_master_arch_dord":"MSB first","spi_master_arch_cpol":"SCK is low when idle","spi_master_arch_cpha":"Sample input on leading edge","spi_master_arch_ibon":"In data stream","spi_master_arch_runstdby":false,"spi_master_arch_dbgstop":"Keep running"},"dependencies":{},"optional_signals":[],"variant":{"specification":"TXPO=0, RXPO=2","required_signals":[{"label":"MOSI","identifier":"SPI_0:MOSI","name":"SERCOM0/PAD/0","pad":"PA04","configuration":null,"definition":"","mode":"Enabled"},{"label":"MISO","identifier":"SPI_0:MISO","name":"SERCOM0/PAD/2","pad":"PA06","configuration":null,"definition":"","mode":"Enabled"},{"label":"SCK","identifier":"SPI_0:SCK","name":"SERCOM0/PAD/1","pad":"PA05","configuration":null,"definition":"","mode":"Enabled"}]},"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::SERCOM::driver_definition::SPI.Master::HAL:Driver:SPI.Master.Sync","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM0::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync","module":"SERCOM0"},"clocks":{"domain_group":{"nodes":[{"name":"Slow","input":"Generic clock generator 3"},{"name":"Core","input":"Generic clock generator 0"}],"configuration":{"core_gclk_selection":"Generic clock generator 0","slow_gclk_selection":"Generic clock generator 3"}}}},{"functionality":"USB","identifier":"USB_DEVICE_INSTANCE","user_label":"USB_DEVICE_INSTANCE","api":"HAL:Driver:USB_Device","configuration":{"usbd_num_ep_sp":"4 (EP0 + 3 endpoints)","usbd_arch_max_ep_n":"2 (EP 0x82 or 0x02)","usbd_arch_speed":"Full speed","usb_arch_ep0_cache":"Cached by 64 bytes buffer","usb_arch_ep1_cache":"Cached by 64 bytes buffer","usb_ep1_I_CACHE":"No cache","usb_arch_ep2_cache":"Cached by 64 bytes buffer","usb_ep2_I_CACHE":"No cache","usb_arch_ep3_cache":"Cached by 64 bytes buffer","usb_ep3_I_CACHE":"No cache","usb_arch_ep4_cache":"Cached by 64 bytes buffer","usb_ep4_I_CACHE":"No cache","usb_arch_ep5_cache":"Cached by 64 bytes buffer","usb_ep5_I_CACHE":"No cache","usb_arch_ep6_cache":"Cached by 64 bytes buffer","usb_ep6_I_CACHE":"No cache","usb_arch_ep7_cache":"Cached by 64 bytes buffer","usb_ep7_I_CACHE":"No cache"},"dependencies":{},"optional_signals":[],"variant":{"specification":"default","required_signals":[{"label":"Data-","identifier":"USB_DEVICE_INSTANCE:Data-","name":"USB/DM","pad":"PA24","configuration":null,"definition":"","mode":"Enabled"},{"label":"Data+","identifier":"USB_DEVICE_INSTANCE:Data+","name":"USB/DP","pad":"PA25","configuration":null,"definition":"","mode":"Enabled"}]},"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::USB::driver_definition::USB.Device::HAL:Driver:USB.Device","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device","module":"USB"},"clocks":{"domain_group":{"nodes":[{"name":"USB","input":"Generic clock generator 0"}],"configuration":{"usb_gclk_selection":"Generic clock generator 0"}}}},{"functionality":"USART","identifier":"USART_0","user_label":"USART_0","api":"HAL:Driver:USART_Sync","configuration":{"usart_rx_enable":true,"usart_tx_enable":true,"usart_parity":"No parity","usart_character_size":"8 bits","usart_stop_bit":"One stop bit","usart_baud_rate":9600,"usart_advanced":false,"usart_arch_runstdby":false,"usart_arch_ibon":false,"usart_arch_sfde":false,"usart_arch_cloden":false,"usart_arch_clock_mode":"USART with internal clock","usart_arch_sampr":"16x arithmetic","usart_arch_sampa":"7-8-9 (3-4-5 8-bit over-sampling)","usart_arch_fractional":0,"usart_arch_dord":"LSB is transmitted first","usart_arch_enc":"No encoding","usart_arch_dbgstop":"Keep running"},"dependencies":{},"optional_signals":[],"variant":{"specification":"TXPO=0, RXPO=1, CMODE=0","required_signals":[{"label":"TX","identifier":"USART_0:TX","name":"SERCOM1/PAD/0","pad":"PA00","configuration":null,"definition":"","mode":"Enabled"},{"label":"RX","identifier":"USART_0:RX","name":"SERCOM1/PAD/1","pad":"PA01","configuration":null,"definition":"","mode":"Enabled"}]},"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::SERCOM::driver_definition::UART::HAL:Driver:USART.Sync","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM1::driver_config_definition::UART::HAL:Driver:USART.Sync","module":"SERCOM1"},"clocks":{"domain_group":{"nodes":[{"name":"Slow","input":"Generic clock generator 3"},{"name":"Core","input":"Generic clock generator 0"}],"configuration":{"core_gclk_selection":"Generic clock generator 0","slow_gclk_selection":"Generic clock generator 3"}}}},{"functionality":"I2C","identifier":"I2C_0","user_label":"I2C_0","api":"HAL:Driver:I2C_Master_Sync","configuration":{"i2c_master_baud_rate":100000,"i2c_master_advanced":false,"i2c_master_arch_trise":215,"i2c_master_arch_mexttoen":false,"i2c_master_arch_sexttoen":false,"i2c_master_arch_lowtout":false,"i2c_master_arch_inactout":"Disabled","i2c_master_arch_sdahold":"300-600ns hold time","i2c_master_arch_runstdby":false,"i2c_master_arch_dbgstop":"Keep running"},"dependencies":{},"optional_signals":[],"variant":{"specification":"SDA=0, SCL=1","required_signals":[{"label":"SDA","identifier":"I2C_0:SDA","name":"SERCOM0/PAD/0","pad":"PA08","configuration":null,"definition":"","mode":"Enabled"},{"label":"SCL","identifier":"I2C_0:SCL","name":"SERCOM0/PAD/1","pad":"PA09","configuration":null,"definition":"","mode":"Enabled"}]},"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::SERCOM::driver_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync","module":"SERCOM0"},"clocks":{"domain_group":{"nodes":[{"name":"Slow","input":"Generic clock generator 3"},{"name":"Core","input":"Generic clock generator 0"}],"configuration":{"core_gclk_selection":"Generic clock generator 0","slow_gclk_selection":"Generic clock generator 3"}}}},{"functionality":"Timer","identifier":"TIMER_0","user_label":"TIMER_0","api":"HAL:Driver:Timer","configuration":{"rtc_arch_prescaler":"OFF(Peripheral clock divided by 1)","rtc_arch_comp_val":1,"rtc_event_control":false,"rtc_pereo0":false,"rtc_pereo1":false,"rtc_pereo2":false,"rtc_pereo3":false,"rtc_pereo4":false,"rtc_pereo5":false,"rtc_pereo6":false,"rtc_pereo7":false,"rtc_cmpeo0":false,"rtc_cmpeo1":false,"rtc_ovfeo":false,"rtc_tampereo":false,"rtc_tampevei":false},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::RTC::driver_definition::Timer::HAL:Driver:Timer","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::RTC::driver_config_definition::Timer::HAL:Driver:Timer","module":"RTC"},"clocks":{"domain_group":{"nodes":[{"name":"RTC","input":"RTC source"}],"configuration":{"rtc_clk_selection":"RTC source"}}}}],"pads":[{"name":"PA00","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA00","mode":"Peripheral IO","configuration":null},{"name":"PA01","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA01","mode":"Peripheral IO","configuration":null},{"name":"PA04","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA04","mode":"Digital output","configuration":null},{"name":"PA05","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA05","mode":"Digital output","configuration":null},{"name":"PA06","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA06","mode":"Digital input","configuration":null},{"name":"PA08","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA08","mode":"Peripheral IO","configuration":null},{"name":"PA09","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA09","mode":"Peripheral IO","configuration":null},{"name":"PA24","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA24","mode":"Advanced","configuration":null},{"name":"PA25","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA25","mode":"Advanced","configuration":null}]}
diff --git a/atmel-samd/tools/update_asf.py b/atmel-samd/tools/update_asf.py
new file mode 100644
index 000000000..20868532b
--- /dev/null
+++ b/atmel-samd/tools/update_asf.py
@@ -0,0 +1,54 @@
+import requests
+import zipfile
+import os.path
+import sys
+
+for chip in ["samd21", "samd51"]:
+    r = None
+    filename = chip + ".zip"
+    if not os.path.isfile(filename):
+        with open("tools/" + chip + ".json", "r") as project_json:
+            headers = {"content-type": "text/plain"}
+            r = requests.post("http://start.atmel.com/api/v1/generate/?format=atzip&compilers=[make]&file_name_base=My%20Project", headers=headers, data=project_json)
+        if not r.ok:
+            # Double check that the JSON is minified. If its not, you'll get a 404.
+            print(r.text)
+            sys.exit(1)
+        with open(filename, "wb") as out:
+            out.write(r.content)
+    z = zipfile.ZipFile(filename)
+    z.extractall("asf4/" + chip)
+    print(z)
+
+    # delete the zip on success
+    #os.remove(filename)
+
+# Remove LITTLE_ENDIAN define from ASF because it conflicts with GCC.
+for fn in os.listdir("asf4/samd51/include"):
+    contents = []
+    path = "asf4/samd51/include/" + fn
+    if not os.path.isfile(path):
+        continue
+    with open(path, "r") as f:
+        for line in f:
+            if line.startswith("#define LITTLE_ENDIAN"):
+                contents.append("//" + line)
+            else:
+                contents.append(line)
+    with open(path, "w") as f:
+        for line in contents:
+            f.write(line)
+
+# Replace ASF's assert with asf_assert so it doesn't conflict with the C macro.
+
+for chip in ["samd21", "samd51"]:
+    contents = []
+    path = "asf4/" + chip + "/hal/utils/include/utils_assert.h"
+    with open(path, "r") as f:
+        for line in f:
+            contents.append(line.replace(" assert(", " asf_assert("))
+    with open(path, "w") as f:
+        for line in contents:
+            f.write(line)
+
+# samd21/samd21a/include is copied to samd21/include to match samd51