run code formatting script

5 files changed, 103 insertions, 110 deletions

diff --git a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c
index bd471f930..251e6f9ac 100644
--- a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c
+++ b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c
@@ -12,24 +12,24 @@
 #include "boards/flash_config.h"
 #include "supervisor/linker.h"
 
-status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type *base, uint32_t baseAddr)
+status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type * base, uint32_t baseAddr)
 {
     flexspi_transfer_t flashXfer;
     status_t status;
 
     /* Write enable */
     flashXfer.deviceAddress = baseAddr;
-    flashXfer.port          = kFLEXSPI_PortA1;
-    flashXfer.cmdType       = kFLEXSPI_Command;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = ROM_INDEX_WRITEENABLE;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = ROM_INDEX_WRITEENABLE;
 
     status = FLEXSPI_TransferBlocking(base, &flashXfer);
 
     return status;
 }
 
-status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type *base)
+status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type * base)
 {
     /* Wait status ready. */
     bool isBusy;
@@ -38,57 +38,54 @@ status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type *base)
     flexspi_transfer_t flashXfer;
 
     flashXfer.deviceAddress = 0;
-    flashXfer.port          = kFLEXSPI_PortA1;
-    flashXfer.cmdType       = kFLEXSPI_Read;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = ROM_INDEX_READSTATUSREG;
-    flashXfer.data          = &readValue;
-    flashXfer.dataSize      = 1;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = ROM_INDEX_READSTATUSREG;
+    flashXfer.data = &readValue;
+    flashXfer.dataSize = 1;
 
     do
     {
         status = FLEXSPI_TransferBlocking(base, &flashXfer);
 
-        if (status != kStatus_Success)
-        {
+        if (status != kStatus_Success) {
             return status;
         }
         size_t busyBit = readValue & (1U << qspiflash_config.memConfig.busyOffset);
         isBusy = (qspiflash_config.memConfig.busyBitPolarity == 0 && busyBit != 0) ||
-                 (qspiflash_config.memConfig.busyBitPolarity == 1 && busyBit == 0);
+            (qspiflash_config.memConfig.busyBitPolarity == 1 && busyBit == 0);
     } while (isBusy);
 
     return status;
 }
 
-status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type *base, uint32_t address)
+status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type * base, uint32_t address)
 {
     status_t status;
     flexspi_transfer_t flashXfer;
 
     /* Write enable */
     flashXfer.deviceAddress = address;
-    flashXfer.port          = kFLEXSPI_PortA1;
-    flashXfer.cmdType       = kFLEXSPI_Command;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = ROM_INDEX_WRITEENABLE;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = ROM_INDEX_WRITEENABLE;
 
     status = FLEXSPI_TransferBlocking(base, &flashXfer);
 
-    if (status != kStatus_Success)
-    {
+    if (status != kStatus_Success) {
         return status;
     }
 
     flashXfer.deviceAddress = address;
-    flashXfer.port          = kFLEXSPI_PortA1;
-    flashXfer.cmdType       = kFLEXSPI_Command;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = ROM_INDEX_ERASESECTOR;
-    status                  = FLEXSPI_TransferBlocking(base, &flashXfer);
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = ROM_INDEX_ERASESECTOR;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
 
-    if (status != kStatus_Success)
-    {
+    if (status != kStatus_Success) {
         return status;
     }
 
@@ -100,7 +97,7 @@ status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type *base, uint3
     return status;
 }
 
-status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src)
+status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type * base, uint32_t dstAddr, const uint32_t *src)
 {
     status_t status;
     flexspi_transfer_t flashXfer;
@@ -108,35 +105,33 @@ status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type *base, uint3
     /* Write enable */
     status = flexspi_nor_write_enable(base, dstAddr);
 
-    if (status != kStatus_Success)
-    {
+    if (status != kStatus_Success) {
         return status;
     }
 
     /* Prepare page program command */
     flashXfer.deviceAddress = dstAddr;
-    flashXfer.port          = kFLEXSPI_PortA1;
-    flashXfer.cmdType       = kFLEXSPI_Write;
-    flashXfer.SeqNumber     = 1;
-    flashXfer.seqIndex      = ROM_INDEX_PAGEPROGRAM;
-    flashXfer.data          = (uint32_t *)src;
-    flashXfer.dataSize      = FLASH_PAGE_SIZE;
-    status                  = FLEXSPI_TransferBlocking(base, &flashXfer);
-
-    if (status != kStatus_Success)
-    {
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = ROM_INDEX_PAGEPROGRAM;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = FLASH_PAGE_SIZE;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success) {
         return status;
     }
 
     status = flexspi_nor_wait_bus_busy(base);
 
     /* Do software reset. */
-#if defined(FSL_FEATURE_SOC_OTFAD_COUNT)
+    #if defined(FSL_FEATURE_SOC_OTFAD_COUNT)
     base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK;
     base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK);
-#else
+    #else
     FLEXSPI_SoftwareReset(base);
-#endif
+    #endif
 
     return status;
 }
diff --git a/ports/mimxrt10xx/supervisor/internal_flash.c b/ports/mimxrt10xx/supervisor/internal_flash.c
index 9c0d9f895..84c478bcf 100644
--- a/ports/mimxrt10xx/supervisor/internal_flash.c
+++ b/ports/mimxrt10xx/supervisor/internal_flash.c
@@ -49,7 +49,7 @@ extern uint32_t __fatfs_flash_length[];
 #define NO_CACHE        0xffffffff
 #define SECTOR_SIZE     0x1000 /* 4K */
 
-uint8_t  _flash_cache[SECTOR_SIZE] __attribute__((aligned(4)));
+uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4)));
 uint32_t _flash_page_addr = NO_CACHE;
 
 extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address);
@@ -58,7 +58,7 @@ extern status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base);
 
 void PLACE_IN_ITCM(supervisor_flash_init)(void) {
     // Update the LUT to make sure all entries are available.
-    FLEXSPI_UpdateLUT(FLEXSPI, 0, (const uint32_t*) &qspiflash_config.memConfig.lookupTable, 64);
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, (const uint32_t *)&qspiflash_config.memConfig.lookupTable, 64);
 }
 
 static inline uint32_t lba2addr(uint32_t block) {
@@ -74,7 +74,9 @@ uint32_t supervisor_flash_get_block_count(void) {
 }
 
 void PLACE_IN_ITCM(port_internal_flash_flush)(void) {
-    if (_flash_page_addr == NO_CACHE) return;
+    if (_flash_page_addr == NO_CACHE) {
+        return;
+    }
     status_t status;
 
     // Skip if data is the same
@@ -109,13 +111,13 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n
     supervisor_flash_flush();
 
     uint32_t src = lba2addr(block);
-    memcpy(dest, (uint8_t*)src, FILESYSTEM_BLOCK_SIZE * num_blocks);
+    memcpy(dest, (uint8_t *)src, FILESYSTEM_BLOCK_SIZE * num_blocks);
     return 0; // success
 }
 
 mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32_t num_blocks) {
     while (num_blocks) {
-        uint32_t const addr      = lba2addr(lba);
+        uint32_t const addr = lba2addr(lba);
         uint32_t const page_addr = addr & ~(SECTOR_SIZE - 1);
 
         uint32_t count = 8 - (lba % 8); // up to page boundary
@@ -135,8 +137,8 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32
         memcpy(_flash_cache + (addr & (SECTOR_SIZE - 1)), src, count * FILESYSTEM_BLOCK_SIZE);
 
         // adjust for next run
-        lba        += count;
-        src        += count * FILESYSTEM_BLOCK_SIZE;
+        lba += count;
+        src += count * FILESYSTEM_BLOCK_SIZE;
         num_blocks -= count;
     }
 
diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c
index 33a85d2b7..2493252d7 100644
--- a/ports/mimxrt10xx/supervisor/port.c
+++ b/ports/mimxrt10xx/supervisor/port.c
@@ -110,8 +110,8 @@ extern void main(void);
 // This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c.
 __attribute__((used, naked)) void Reset_Handler(void) {
     __disable_irq();
-    SCB->VTOR = (uint32_t) &__isr_vector;
-    __set_MSP((uint32_t) &_ld_stack_top);
+    SCB->VTOR = (uint32_t)&__isr_vector;
+    __set_MSP((uint32_t)&_ld_stack_top);
 
     /* Disable I cache and D cache */
     SCB_DisableICache();
@@ -135,7 +135,7 @@ __attribute__((used, naked)) void Reset_Handler(void) {
     IOMUXC_GPR->GPR14 = current_gpr14;
 
     #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
-      SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  /* set CP10, CP11 Full Access */
     #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
 
     /* Disable Watchdog Power Down Counter */
@@ -147,11 +147,10 @@ __attribute__((used, naked)) void Reset_Handler(void) {
     WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
     RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
     RTWDOG->TOVAL = 0xFFFF;
-    RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
+    RTWDOG->CS = (uint32_t)((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
 
     /* Disable Systick which might be enabled by bootrom */
-    if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)
-    {
+    if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) {
         SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     }
 
@@ -160,7 +159,7 @@ __attribute__((used, naked)) void Reset_Handler(void) {
 
     // Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write
     // protect it.
-    for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_itcm_size) / 4; i++) {
         (&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i];
     }
 
@@ -226,22 +225,22 @@ __attribute__((used, naked)) void Reset_Handler(void) {
     SCB_EnableICache();
 
     // Copy all of the data to run from DTCM.
-    for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_data_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_data_size) / 4; i++) {
         (&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i];
     }
 
     // Clear DTCM bss.
-    for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_bss_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_bss_size) / 4; i++) {
         (&_ld_dtcm_bss_start)[i] = 0;
     }
 
     // Copy all of the data to run from OCRAM.
-    for (uint32_t i = 0; i < ((size_t) &_ld_ocram_data_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_ocram_data_size) / 4; i++) {
         (&_ld_ocram_data_destination)[i] = (&_ld_ocram_data_flash_copy)[i];
     }
 
     // Clear OCRAM bss.
-    for (uint32_t i = 0; i < ((size_t) &_ld_ocram_bss_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_ocram_bss_size) / 4; i++) {
         (&_ld_ocram_bss_start)[i] = 0;
     }
 
@@ -254,9 +253,9 @@ safe_mode_t port_init(void) {
 
     clocks_init();
 
-#if CIRCUITPY_RTC
+    #if CIRCUITPY_RTC
     rtc_init();
-#endif
+    #endif
 
     // Always enable the SNVS interrupt. The GPC won't wake us up unless at least one interrupt is
     // enabled. It won't occur very often so it'll be low overhead.
@@ -275,43 +274,43 @@ safe_mode_t port_init(void) {
 void reset_port(void) {
     spi_reset();
 
-#if CIRCUITPY_AUDIOIO
+    #if CIRCUITPY_AUDIOIO
     audio_dma_reset();
     audioout_reset();
-#endif
-#if CIRCUITPY_AUDIOBUSIO
+    #endif
+    #if CIRCUITPY_AUDIOBUSIO
     i2sout_reset();
-    //pdmin_reset();
-#endif
+    // pdmin_reset();
+    #endif
 
-#if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE
+    #if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE
     touchin_reset();
-#endif
+    #endif
 
 //    eic_reset();
 
-#if CIRCUITPY_PULSEIO
+    #if CIRCUITPY_PULSEIO
     pulseout_reset();
-#endif
-#if CIRCUITPY_PWMIO
+    #endif
+    #if CIRCUITPY_PWMIO
     pwmout_reset();
-#endif
+    #endif
 
-#if CIRCUITPY_RTC
+    #if CIRCUITPY_RTC
     rtc_reset();
-#endif
+    #endif
 
-#if CIRCUITPY_GAMEPAD
+    #if CIRCUITPY_GAMEPAD
     gamepad_reset();
-#endif
-#if CIRCUITPY_GAMEPADSHIFT
+    #endif
+    #if CIRCUITPY_GAMEPADSHIFT
     gamepadshift_reset();
-#endif
-#if CIRCUITPY_PEW
+    #endif
+    #if CIRCUITPY_PEW
     pew_reset();
-#endif
+    #endif
 
-    //reset_event_system();
+    // reset_event_system();
 
     reset_all_pins();
 }
@@ -356,12 +355,12 @@ uint32_t port_get_saved_word(void) {
     return SNVS->LPGPR[1];
 }
 
-uint64_t port_get_raw_ticks(uint8_t* subticks) {
+uint64_t port_get_raw_ticks(uint8_t *subticks) {
     uint64_t ticks = 0;
     uint64_t next_ticks = 1;
     while (ticks != next_ticks) {
         ticks = next_ticks;
-        next_ticks = ((uint64_t) SNVS->HPRTCMR) << 32 | SNVS->HPRTCLR;
+        next_ticks = ((uint64_t)SNVS->HPRTCMR) << 32 | SNVS->HPRTCLR;
     }
     if (subticks != NULL) {
         *subticks = ticks % 32;
@@ -397,7 +396,8 @@ void port_interrupt_after_ticks(uint32_t ticks) {
     current_ticks += ticks;
     SNVS->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK;
     // Wait for the alarm to be disabled.
-    while ((SNVS->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0) {}
+    while ((SNVS->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0) {
+    }
     SNVS->HPTAMR = current_ticks >> (32 - 5);
     SNVS->HPTALR = current_ticks << 5 | subticks;
     SNVS->HPCR |= SNVS_HPCR_HPTA_EN_MASK;
@@ -407,9 +407,9 @@ void port_idle_until_interrupt(void) {
     // App note here: https://www.nxp.com/docs/en/application-note/AN12085.pdf
 
     // Clear the FPU interrupt because it can prevent us from sleeping.
-    if (__get_FPSCR()  & ~(0x9f)) {
-        __set_FPSCR(__get_FPSCR()  & ~(0x9f));
-        (void) __get_FPSCR();
+    if (__get_FPSCR() & ~(0x9f)) {
+        __set_FPSCR(__get_FPSCR() & ~(0x9f));
+        (void)__get_FPSCR();
     }
     NVIC_ClearPendingIRQ(SNVS_HP_WRAPPER_IRQn);
     CLOCK_SetMode(kCLOCK_ModeWait);
@@ -420,43 +420,39 @@ void port_idle_until_interrupt(void) {
 /**
  * \brief Default interrupt handler for unused IRQs.
  */
-__attribute__((used)) void MemManage_Handler(void)
-{
+__attribute__((used)) void MemManage_Handler(void) {
     reset_into_safe_mode(MEM_MANAGE);
     while (true) {
-        asm("nop;");
+        asm ("nop;");
     }
 }
 
 /**
  * \brief Default interrupt handler for unused IRQs.
  */
-__attribute__((used)) void BusFault_Handler(void)
-{
+__attribute__((used)) void BusFault_Handler(void) {
     reset_into_safe_mode(MEM_MANAGE);
     while (true) {
-        asm("nop;");
+        asm ("nop;");
     }
 }
 
 /**
  * \brief Default interrupt handler for unused IRQs.
  */
-__attribute__((used)) void UsageFault_Handler(void)
-{
+__attribute__((used)) void UsageFault_Handler(void) {
     reset_into_safe_mode(MEM_MANAGE);
     while (true) {
-        asm("nop;");
+        asm ("nop;");
     }
 }
 
 /**
  * \brief Default interrupt handler for unused IRQs.
  */
-__attribute__((used)) void HardFault_Handler(void)
-{
+__attribute__((used)) void HardFault_Handler(void) {
     reset_into_safe_mode(HARD_CRASH);
     while (true) {
-        asm("nop;");
+        asm ("nop;");
     }
 }
diff --git a/ports/mimxrt10xx/supervisor/serial.c b/ports/mimxrt10xx/supervisor/serial.c
index 01656a819..ea706d8a8 100644
--- a/ports/mimxrt10xx/supervisor/serial.c
+++ b/ports/mimxrt10xx/supervisor/serial.c
@@ -35,7 +35,7 @@
 
 // static LPUART_Type *uart_instance = LPUART1; // evk
 static LPUART_Type *uart_instance = LPUART4; // feather 1011
-//static LPUART_Type *uart_instance = LPUART2; // feather 1062
+// static LPUART_Type *uart_instance = LPUART2; // feather 1062
 
 static uint32_t UartSrcFreq(void) {
     uint32_t freq;
@@ -79,8 +79,8 @@ bool serial_bytes_available(void) {
     return LPUART_GetStatusFlags(uart_instance) & kLPUART_RxDataRegFullFlag;
 }
 
-void serial_write(const char* text) {
-    LPUART_WriteBlocking(uart_instance, (uint8_t*)text, strlen(text));
+void serial_write(const char *text) {
+    LPUART_WriteBlocking(uart_instance, (uint8_t *)text, strlen(text));
 }
 
 void serial_write_substring(const char *text, uint32_t len) {
@@ -88,5 +88,5 @@ void serial_write_substring(const char *text, uint32_t len) {
         return;
     }
 
-    LPUART_WriteBlocking(uart_instance, (uint8_t*)text, len);
+    LPUART_WriteBlocking(uart_instance, (uint8_t *)text, len);
 }
diff --git a/ports/mimxrt10xx/supervisor/usb.c b/ports/mimxrt10xx/supervisor/usb.c
index 91135289c..57f038799 100644
--- a/ports/mimxrt10xx/supervisor/usb.c
+++ b/ports/mimxrt10xx/supervisor/usb.c
@@ -33,11 +33,11 @@ void init_usb_hardware(void) {
     CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
     CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
 
-#ifdef USBPHY
+    #ifdef USBPHY
     USBPHY_Type *usb_phy = USBPHY;
-#else
+    #else
     USBPHY_Type *usb_phy = USBPHY1;
-#endif
+    #endif
 
     // Enable PHY support for Low speed device + LS via FS Hub
     usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;