diff options
| author | Jeff Epler <jepler@gmail.com> | 2021-03-16 12:21:50 -0500 |
|---|---|---|
| committer | Jeff Epler <jepler@gmail.com> | 2021-03-16 12:21:50 -0500 |
| commit | 58679dc038e475d7cd00ee45256b7f906ecc2240 (patch) | |
| tree | 30cbc3f9e7e4efc81a43f364d554f33c1df34169 /ports/stm/peripherals/stm32h7/clocks.c | |
| parent | 97b6664201de2530c9b92957a5e8d2a68524fa7e (diff) | |
| parent | bc690d4070c69e21d9070badc9f56a15d62ffb5d (diff) | |
Merge remote-tracking branch 'origin/main' into bitmap-read-2
Diffstat (limited to 'ports/stm/peripherals/stm32h7/clocks.c')
| -rw-r--r-- | ports/stm/peripherals/stm32h7/clocks.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/ports/stm/peripherals/stm32h7/clocks.c b/ports/stm/peripherals/stm32h7/clocks.c index a088f78bf..5fde5af6c 100644 --- a/ports/stm/peripherals/stm32h7/clocks.c +++ b/ports/stm/peripherals/stm32h7/clocks.c @@ -41,7 +41,8 @@ void stm32_peripherals_clocks_init(void) { // Set voltage scaling in accordance with system clock speed HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) { + } // Configure LSE Drive HAL_PWR_EnableBkUpAccess(); @@ -63,7 +64,7 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/2000000; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 2000000; RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; @@ -71,16 +72,18 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { // Clock issues are too problematic to even attempt recovery. // If you end up here, check whether your LSE settings match your board. - while(1); + while (1) { + ; + } } // Configure bus clock sources and divisors - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; @@ -92,8 +95,8 @@ void stm32_peripherals_clocks_init(void) { // Set up non-bus peripherals // TODO: I2S settings go here - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART3 - |RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 + | RCC_PERIPHCLK_USB; #if (BOARD_HAS_LOW_SPEED_CRYSTAL) PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; #else |