adds support for the stm32f746g_disco board

1 files changed, 34 insertions, 5 deletions

diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c b/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c
index b3f56e851..b73a1a20d 100644
--- a/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c
+++ b/ports/stm/peripherals/stm32f7/stm32f746xx/clocks.c
@@ -28,6 +28,22 @@
 
 #include "py/mpconfig.h"
 
+#ifndef BOARD_OSC_DIV
+#define BOARD_OSC_DIV (8)
+#endif
+#ifndef BOARD_OSC_PLLN
+#define BOARD_OSC_PLLN (432)
+#endif
+#ifndef BOARD_OSC_PLLQ
+#define BOARD_OSC_PLLQ (9)
+#endif
+#ifndef BOARD_FLASH_LATENCY
+#define BOARD_FLASH_LATENCY FLASH_LATENCY_7
+#endif
+#ifndef BOARD_OSC_HSESTATE
+#define BOARD_OSC_HSESTATE RCC_HSE_BYPASS
+#endif
+
 void stm32_peripherals_clocks_init(void) {
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
@@ -42,14 +58,14 @@ void stm32_peripherals_clocks_init(void) {
 
   /* Enable HSE Oscillator and activate PLL with HSE as source */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.HSEState = BOARD_OSC_HSESTATE;
   RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
   RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV;
-  RCC_OscInitStruct.PLL.PLLN = 432;
+  RCC_OscInitStruct.PLL.PLLN = BOARD_OSC_PLLN;
   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 9;
+  RCC_OscInitStruct.PLL.PLLQ = BOARD_OSC_PLLQ;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
   /* Activate the OverDrive to reach the 216 MHz Frequency */
@@ -62,6 +78,19 @@ void stm32_peripherals_clocks_init(void) {
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, BOARD_FLASH_LATENCY);
+
+  #ifdef STM32F746G_DISCO
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
 
-}
\ No newline at end of file
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+  PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
+  PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
+  PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
+  PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
+  PeriphClkInitStruct.PLLSAIDivQ = 1;
+  PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
+  PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+  #endif
+}