run code formatting script

141 files changed, 3127 insertions, 3129 deletions

diff --git a/ports/stm/background.c b/ports/stm/background.c
index d83a0ccec..dbf5ccee2 100644
--- a/ports/stm/background.c
+++ b/ports/stm/background.c
@@ -33,6 +33,9 @@
 #include "shared-module/displayio/__init__.h"
 #endif
 
-void port_background_task(void) {}
-void port_start_background_task(void) {}
-void port_finish_background_task(void) {}
+void port_background_task(void) {
+}
+void port_start_background_task(void) {
+}
+void port_finish_background_task(void) {
+}
diff --git a/ports/stm/boards/espruino_pico/mpconfigboard.h b/ports/stm/boards/espruino_pico/mpconfigboard.h
index fe4ed6ca2..9a3f93864 100644
--- a/ports/stm/boards/espruino_pico/mpconfigboard.h
+++ b/ports/stm/boards/espruino_pico/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "Espruino Pico"
 #define MICROPY_HW_MCU_NAME         "STM32F401xD"
diff --git a/ports/stm/boards/espruino_wifi/board.c b/ports/stm/boards/espruino_wifi/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/espruino_wifi/board.c
+++ b/ports/stm/boards/espruino_wifi/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/espruino_wifi/mpconfigboard.h b/ports/stm/boards/espruino_wifi/mpconfigboard.h
index b7f38f69b..b857650d6 100644
--- a/ports/stm/boards/espruino_wifi/mpconfigboard.h
+++ b/ports/stm/boards/espruino_wifi/mpconfigboard.h
@@ -24,13 +24,13 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "Espruino Wifi"
 #define MICROPY_HW_MCU_NAME         "STM32F411xE"
 
-#define FLASH_SIZE                  (0x80000) //512K
-#define FLASH_PAGE_SIZE             (0x4000)  //16K
+#define FLASH_SIZE                  (0x80000) // 512K
+#define FLASH_PAGE_SIZE             (0x4000)  // 16K
 
 #define HSE_VALUE ((uint32_t)8000000)
 #define LSE_VALUE ((uint32_t)32768)
diff --git a/ports/stm/boards/espruino_wifi/pins.c b/ports/stm/boards/espruino_wifi/pins.c
index 8800317d5..2d36ae8b9 100644
--- a/ports/stm/boards/espruino_wifi/pins.c
+++ b/ports/stm/boards/espruino_wifi/pins.c
@@ -1,39 +1,39 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-  //P1
-  { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_B1), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_B10), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_B13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_B14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_B15), MP_ROM_PTR(&pin_PB15) },
+    // P1
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_B1), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_B10), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_B13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_B14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_B15), MP_ROM_PTR(&pin_PB15) },
 
-  { MP_ROM_QSTR(MP_QSTR_B0), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_B9), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_B8), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_B7), MP_ROM_PTR(&pin_PB07) },
-  { MP_ROM_QSTR(MP_QSTR_B6), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_B5), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_B3), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_B0), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_B9), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_B8), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_B7), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_B6), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_B5), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_B3), MP_ROM_PTR(&pin_PB03) },
 
-  { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) },
 
-  { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_BTN), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_BTN), MP_ROM_PTR(&pin_PC13) },
 
-  { MP_ROM_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_PA02) },
-  { MP_ROM_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_PA03) },
-  { MP_ROM_QSTR(MP_QSTR_ESP_GPIO0), MP_ROM_PTR(&pin_PA13) },
-  { MP_ROM_QSTR(MP_QSTR_ESP_CHPD), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_ESP_GPIO13), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_ESP_GPIO0), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_ESP_CHPD), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_ESP_GPIO13), MP_ROM_PTR(&pin_PA15) },
 };
 MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h
index e69be6cf9..8558edd8c 100644
--- a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h
+++ b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "Adafruit Feather STM32F405 Express"
 #define MICROPY_HW_MCU_NAME         "STM32F405RG"
@@ -46,7 +46,7 @@
 
 // Bootloader only
 #ifdef UF2_BOOTLOADER_ENABLED
-    #define BOARD_VTOR_DEFER (1) //Leave VTOR relocation to bootloader
+    #define BOARD_VTOR_DEFER (1) // Leave VTOR relocation to bootloader
 #endif
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PB06)
diff --git a/ports/stm/boards/meowbit_v121/board.c b/ports/stm/boards/meowbit_v121/board.c
index 4a8014a3a..44d125462 100644
--- a/ports/stm/boards/meowbit_v121/board.c
+++ b/ports/stm/boards/meowbit_v121/board.c
@@ -41,36 +41,36 @@ displayio_fourwire_obj_t board_display_obj;
 
 uint8_t display_init_sequence[] = {
     0x01, 0 | DELAY, 150, // SWRESET
-	0x11, 0 | DELAY, 255, // SLPOUT
-	0xb1, 3, 0x01, 0x2C, 0x2D, // _FRMCTR1
-	0xb2, 3, 0x01, 0x2C, 0x2D, //
-	0xb3, 6, 0x01, 0x2C, 0x2D, 0x01, 0x2C, 0x2D,
-	0xb4, 1, 0x07, // _INVCTR line inversion
-	0xc0, 3, 0xa2, 0x02, 0x84, // _PWCTR1 GVDD = 4.7V, 1.0uA
-	0xc1, 1, 0xc5, // _PWCTR2 VGH=14.7V, VGL=-7.35V
-	0xc2, 2, 0x0a, 0x00, // _PWCTR3 Opamp current small, Boost frequency
-	0xc3, 2, 0x8a, 0x2a,
-	0xc4, 2, 0x8a, 0xee,
-	0xc5, 1, 0x0e, // _VMCTR1 VCOMH = 4V, VOML = -1.1V
-	0x20, 0, // _INVOFF //MISMATCh 0x2a vs 0x20
-	0x36, 1, 0x18, // _MADCTL bottom to top refresh
-	// 1 clk cycle nonoverlap, 2 cycle gate rise, 3 sycle osc equalie,
-	// fix on VTL
-	0x3a, 1, 0x05, // COLMOD - 16bit color
-	0xe0, 0x10, 0x02, 0x1c, 0x07, 0x12,
-				0x37, 0x32, 0x29, 0x2d,
-				0x29, 0x25, 0x2B, 0x39,
-				0x00, 0x01, 0x03, 0x10, // _GMCTRP1 Gamma
-	0xe1, 0x10, 0x03, 0x1d, 0x07, 0x06,
-				0x2E, 0x2C, 0x29, 0x2D,
-				0x2E, 0x2E, 0x37, 0x3F,
-				0x00, 0x00, 0x02, 0x10, // _GMCTRN1
-	0x13, 0 | DELAY, 10, // _NORON
-	0x29, 0 | DELAY, 100, // _DISPON
+    0x11, 0 | DELAY, 255,     // SLPOUT
+    0xb1, 3, 0x01, 0x2C, 0x2D,     // _FRMCTR1
+    0xb2, 3, 0x01, 0x2C, 0x2D,     //
+    0xb3, 6, 0x01, 0x2C, 0x2D, 0x01, 0x2C, 0x2D,
+    0xb4, 1, 0x07,     // _INVCTR line inversion
+    0xc0, 3, 0xa2, 0x02, 0x84,     // _PWCTR1 GVDD = 4.7V, 1.0uA
+    0xc1, 1, 0xc5,     // _PWCTR2 VGH=14.7V, VGL=-7.35V
+    0xc2, 2, 0x0a, 0x00,     // _PWCTR3 Opamp current small, Boost frequency
+    0xc3, 2, 0x8a, 0x2a,
+    0xc4, 2, 0x8a, 0xee,
+    0xc5, 1, 0x0e,     // _VMCTR1 VCOMH = 4V, VOML = -1.1V
+    0x20, 0,     // _INVOFF //MISMATCh 0x2a vs 0x20
+    0x36, 1, 0x18,     // _MADCTL bottom to top refresh
+    // 1 clk cycle nonoverlap, 2 cycle gate rise, 3 sycle osc equalie,
+    // fix on VTL
+    0x3a, 1, 0x05,     // COLMOD - 16bit color
+    0xe0, 0x10, 0x02, 0x1c, 0x07, 0x12,
+    0x37, 0x32, 0x29, 0x2d,
+    0x29, 0x25, 0x2B, 0x39,
+    0x00, 0x01, 0x03, 0x10,                             // _GMCTRP1 Gamma
+    0xe1, 0x10, 0x03, 0x1d, 0x07, 0x06,
+    0x2E, 0x2C, 0x29, 0x2D,
+    0x2E, 0x2E, 0x37, 0x3F,
+    0x00, 0x00, 0x02, 0x10,                             // _GMCTRN1
+    0x13, 0 | DELAY, 10,     // _NORON
+    0x29, 0 | DELAY, 100,     // _DISPON
 };
 
 void board_init(void) {
-    displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus;
+    displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus;
     bus->base.type = &displayio_fourwire_type;
     busio_spi_obj_t *internal_spi = &supervisor_flash_spi_bus;
     common_hal_displayio_fourwire_construct(bus,
@@ -82,7 +82,7 @@ void board_init(void) {
         0, // Polarity
         0); // Phase
 
-    displayio_display_obj_t* display = &displays[0].display;
+    displayio_display_obj_t *display = &displays[0].display;
     display->base.type = &displayio_display_type;
     common_hal_displayio_display_construct(display,
         bus,
diff --git a/ports/stm/boards/meowbit_v121/mpconfigboard.h b/ports/stm/boards/meowbit_v121/mpconfigboard.h
index be9f2a75f..780743794 100644
--- a/ports/stm/boards/meowbit_v121/mpconfigboard.h
+++ b/ports/stm/boards/meowbit_v121/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "MEOWBIT"
 #define MICROPY_HW_MCU_NAME         "STM32F401xE"
@@ -39,7 +39,7 @@
 #define BOARD_HAS_LOW_SPEED_CRYSTAL (0)
 
 #define BOARD_NO_VBUS_SENSE (1)
-#define BOARD_VTOR_DEFER (1) //Leave VTOR relocation to bootloader
+#define BOARD_VTOR_DEFER (1) // Leave VTOR relocation to bootloader
 #define BOARD_USE_INTERNAL_SPI
 
 // On-board flash
diff --git a/ports/stm/boards/meowbit_v121/pins.c b/ports/stm/boards/meowbit_v121/pins.c
index af896fad8..d11341145 100644
--- a/ports/stm/boards/meowbit_v121/pins.c
+++ b/ports/stm/boards/meowbit_v121/pins.c
@@ -55,7 +55,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_PC06) },
     { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_PA04) },
     { MP_ROM_QSTR(MP_QSTR_P1), MP_ROM_PTR(&pin_PA01) },
-    { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_PA10) }, //in use by USB
+    { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_PA10) }, // in use by USB
     { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_PC07) },
     { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_PB05) },
     { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_PC01) },
diff --git a/ports/stm/boards/nucleo_f746zg/board.c b/ports/stm/boards/nucleo_f746zg/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/nucleo_f746zg/board.c
+++ b/ports/stm/boards/nucleo_f746zg/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/nucleo_f746zg/mpconfigboard.h b/ports/stm/boards/nucleo_f746zg/mpconfigboard.h
index e2b54335a..ef8f84ceb 100644
--- a/ports/stm/boards/nucleo_f746zg/mpconfigboard.h
+++ b/ports/stm/boards/nucleo_f746zg/mpconfigboard.h
@@ -25,7 +25,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "NUCLEO STM32F746"
 #define MICROPY_HW_MCU_NAME         "STM32F746"
diff --git a/ports/stm/boards/nucleo_f746zg/pins.c b/ports/stm/boards/nucleo_f746zg/pins.c
index 7c6a075e2..251ce4bcb 100644
--- a/ports/stm/boards/nucleo_f746zg/pins.c
+++ b/ports/stm/boards/nucleo_f746zg/pins.c
@@ -1,74 +1,74 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
-{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) },
-{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
-{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) },
-{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) },
-{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) },
-{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) },
-{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) },
-{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) },
-{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) },
-{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) },
-{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
-{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
-{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) },
-{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) },
-{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
-{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) },
-{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
-{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
-{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
-{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
-{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) },
-{ MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) },
-{ MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) },
-{ MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) },
-{ MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) },
-{ MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) },
-{ MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) },
-{ MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) },
-{ MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) },
-{ MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) },
-{ MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) },
-{ MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) },
-{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) },
-{ MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) },
-{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) },
-{ MP_ROM_QSTR(MP_QSTR_TP1), MP_ROM_PTR(&pin_PH02) },
-{ MP_ROM_QSTR(MP_QSTR_TP2), MP_ROM_PTR(&pin_PI08) },
-{ MP_ROM_QSTR(MP_QSTR_TP3), MP_ROM_PTR(&pin_PH15) },
-{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_PD06) },
-{ MP_ROM_QSTR(MP_QSTR_AUDIO_SDA), MP_ROM_PTR(&pin_PH08) },
-{ MP_ROM_QSTR(MP_QSTR_AUDIO_SCL), MP_ROM_PTR(&pin_PH07) },
-{ MP_ROM_QSTR(MP_QSTR_EXT_SDA), MP_ROM_PTR(&pin_PB09) },
-{ MP_ROM_QSTR(MP_QSTR_EXT_SCL), MP_ROM_PTR(&pin_PB08) },
-{ MP_ROM_QSTR(MP_QSTR_EXT_RST), MP_ROM_PTR(&pin_PG03) },
-{ MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PC13) },
-{ MP_ROM_QSTR(MP_QSTR_LCD_BL_CTRL), MP_ROM_PTR(&pin_PK03) },
-{ MP_ROM_QSTR(MP_QSTR_LCD_INT), MP_ROM_PTR(&pin_PI13) },
-{ MP_ROM_QSTR(MP_QSTR_LCD_SDA), MP_ROM_PTR(&pin_PH08) },
-{ MP_ROM_QSTR(MP_QSTR_LCD_SCL), MP_ROM_PTR(&pin_PH07) },
-{ MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PD05) },
-{ MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PD04) },
-{ MP_ROM_QSTR(MP_QSTR_OTG_HS_OVER_CURRENT), MP_ROM_PTR(&pin_PE03) },
-{ MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) },
-{ MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) },
-{ MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) },
-{ MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) },
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) },
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_TP1), MP_ROM_PTR(&pin_PH02) },
+    { MP_ROM_QSTR(MP_QSTR_TP2), MP_ROM_PTR(&pin_PI08) },
+    { MP_ROM_QSTR(MP_QSTR_TP3), MP_ROM_PTR(&pin_PH15) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_SDA), MP_ROM_PTR(&pin_PH08) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_SCL), MP_ROM_PTR(&pin_PH07) },
+    { MP_ROM_QSTR(MP_QSTR_EXT_SDA), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_EXT_SCL), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_EXT_RST), MP_ROM_PTR(&pin_PG03) },
+    { MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_BL_CTRL), MP_ROM_PTR(&pin_PK03) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_INT), MP_ROM_PTR(&pin_PI13) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_SDA), MP_ROM_PTR(&pin_PH08) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_SCL), MP_ROM_PTR(&pin_PH07) },
+    { MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_OTG_HS_OVER_CURRENT), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) },
 // As we use these for the debug_console, we won't enable them here.
 // { MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PD08) },
 // { MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PD09) },
-{ MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) },
-{ MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) },
-{ MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) },
-{ MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) },
-{ MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PG14) },
-{ MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PG09) },
-{ MP_ROM_QSTR(MP_QSTR_SPI_B_NSS), MP_ROM_PTR(&pin_PA04) },
-{ MP_ROM_QSTR(MP_QSTR_SPI_B_SCK), MP_ROM_PTR(&pin_PB03) },
-{ MP_ROM_QSTR(MP_QSTR_SPI_B_MOSI), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PG14) },
+    { MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PG09) },
+    { MP_ROM_QSTR(MP_QSTR_SPI_B_NSS), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_SPI_B_SCK), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_SPI_B_MOSI), MP_ROM_PTR(&pin_PB05) },
 };
 MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/stm/boards/nucleo_f767zi/board.c b/ports/stm/boards/nucleo_f767zi/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/nucleo_f767zi/board.c
+++ b/ports/stm/boards/nucleo_f767zi/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h
index 327651923..8db104e87 100644
--- a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h
+++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "NUCLEO STM32F767"
 #define MICROPY_HW_MCU_NAME         "STM32F767"
diff --git a/ports/stm/boards/nucleo_f767zi/pins.c b/ports/stm/boards/nucleo_f767zi/pins.c
index 9ecc38f01..0373fc4fb 100644
--- a/ports/stm/boards/nucleo_f767zi/pins.c
+++ b/ports/stm/boards/nucleo_f767zi/pins.c
@@ -1,142 +1,142 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
-{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) },
-{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
-{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) },
-{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) },
-{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) },
-{ MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) },
-{ MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PC02) },
-{ MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PF04) },
-{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) },
-{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) },
-{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) },
-{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) },
-{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) },
-{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
-{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
-{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) },
-{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) },
-{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
-{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) },
-{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
-{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
-{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
-{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
-{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) },
-{ MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) },
-{ MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) },
-{ MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) },
-{ MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) },
-{ MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) },
-{ MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) },
-{ MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) },
-{ MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) },
-{ MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) },
-{ MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) },
-{ MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_PB06) },
-{ MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_PB02) },
-{ MP_ROM_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_PD13) },
-{ MP_ROM_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_PD12) },
-{ MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PD11) },
-{ MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PE02) },
-{ MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA00) },
-{ MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PB00) },
-{ MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_PE00) },
-{ MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_PB11) },
-{ MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_PB10) },
-{ MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_PE15) },
-{ MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_PE14) },
-{ MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_PE12) },
-{ MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_PE10) },
-{ MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_PE07) },
-{ MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_PE08) },
-{ MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_PC08) },
-{ MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_PC09) },
-{ MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_PC10) },
-{ MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_PC11) },
-{ MP_ROM_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_PC12) },
-{ MP_ROM_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_PD02) },
-{ MP_ROM_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_PG02) },
-{ MP_ROM_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_PG03) },
-{ MP_ROM_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_PD07) },
-{ MP_ROM_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_PD06) },
-{ MP_ROM_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_PD05) },
-{ MP_ROM_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_PD04) },
-{ MP_ROM_QSTR(MP_QSTR_D55), MP_ROM_PTR(&pin_PD03) },
-{ MP_ROM_QSTR(MP_QSTR_D56), MP_ROM_PTR(&pin_PE02) },
-{ MP_ROM_QSTR(MP_QSTR_D57), MP_ROM_PTR(&pin_PE04) },
-{ MP_ROM_QSTR(MP_QSTR_D58), MP_ROM_PTR(&pin_PE05) },
-{ MP_ROM_QSTR(MP_QSTR_D59), MP_ROM_PTR(&pin_PE06) },
-{ MP_ROM_QSTR(MP_QSTR_D60), MP_ROM_PTR(&pin_PE03) },
-{ MP_ROM_QSTR(MP_QSTR_D61), MP_ROM_PTR(&pin_PF08) },
-{ MP_ROM_QSTR(MP_QSTR_D62), MP_ROM_PTR(&pin_PF07) },
-{ MP_ROM_QSTR(MP_QSTR_D63), MP_ROM_PTR(&pin_PF09) },
-{ MP_ROM_QSTR(MP_QSTR_D64), MP_ROM_PTR(&pin_PG01) },
-{ MP_ROM_QSTR(MP_QSTR_D65), MP_ROM_PTR(&pin_PG00) },
-{ MP_ROM_QSTR(MP_QSTR_D66), MP_ROM_PTR(&pin_PD01) },
-{ MP_ROM_QSTR(MP_QSTR_D67), MP_ROM_PTR(&pin_PD00) },
-{ MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) },
-{ MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) },
-{ MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) },
-{ MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PA07) },
-{ MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) },
-{ MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) },
-{ MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) },
-{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) },
-{ MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) },
-{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) },
-{ MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) },
-{ MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) },
-{ MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) },
-{ MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) },
-{ MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) },
-{ MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) },
-{ MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PG02) },
-{ MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PG06) },
-{ MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PG07) },
-{ MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) },
-{ MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) },
-{ MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) },
-{ MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) },
-{ MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) },
-{ MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) },
-{ MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) },
-{ MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) },
-{ MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PD08) },
-{ MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PD09) },
-{ MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PD08) },
-{ MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PD09) },
-{ MP_ROM_QSTR(MP_QSTR_UART5_TX), MP_ROM_PTR(&pin_PB06) },
-{ MP_ROM_QSTR(MP_QSTR_UART5_RX), MP_ROM_PTR(&pin_PB12) },
-{ MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PC06) },
-{ MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PC07) },
-{ MP_ROM_QSTR(MP_QSTR_UART7_TX), MP_ROM_PTR(&pin_PF07) },
-{ MP_ROM_QSTR(MP_QSTR_UART7_RX), MP_ROM_PTR(&pin_PF06) },
-{ MP_ROM_QSTR(MP_QSTR_UART8_TX), MP_ROM_PTR(&pin_PE01) },
-{ MP_ROM_QSTR(MP_QSTR_UART8_RX), MP_ROM_PTR(&pin_PE00) },
-{ MP_ROM_QSTR(MP_QSTR_SPI3_NSS), MP_ROM_PTR(&pin_PA04) },
-{ MP_ROM_QSTR(MP_QSTR_SPI3_SCK), MP_ROM_PTR(&pin_PB03) },
-{ MP_ROM_QSTR(MP_QSTR_SPI3_MISO), MP_ROM_PTR(&pin_PB04) },
-{ MP_ROM_QSTR(MP_QSTR_SPI3_MOSI), MP_ROM_PTR(&pin_PB05) },
-{ MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) },
-{ MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PB08) },
-{ MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PF00) },
-{ MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PF01) },
-{ MP_ROM_QSTR(MP_QSTR_I2C4_SCL), MP_ROM_PTR(&pin_PF14) },
-{ MP_ROM_QSTR(MP_QSTR_I2C4_SDA), MP_ROM_PTR(&pin_PF15) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PB13) },
-{ MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA13) },
-{ MP_ROM_QSTR(MP_QSTR_SWDCLK), MP_ROM_PTR(&pin_PA14) }
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PF04) },
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) },
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PD11) },
+    { MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_PB11) },
+    { MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_PG02) },
+    { MP_ROM_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_PG03) },
+    { MP_ROM_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_PD07) },
+    { MP_ROM_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_D55), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_D56), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_D57), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_D58), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_D59), MP_ROM_PTR(&pin_PE06) },
+    { MP_ROM_QSTR(MP_QSTR_D60), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_D61), MP_ROM_PTR(&pin_PF08) },
+    { MP_ROM_QSTR(MP_QSTR_D62), MP_ROM_PTR(&pin_PF07) },
+    { MP_ROM_QSTR(MP_QSTR_D63), MP_ROM_PTR(&pin_PF09) },
+    { MP_ROM_QSTR(MP_QSTR_D64), MP_ROM_PTR(&pin_PG01) },
+    { MP_ROM_QSTR(MP_QSTR_D65), MP_ROM_PTR(&pin_PG00) },
+    { MP_ROM_QSTR(MP_QSTR_D66), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_D67), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) },
+    { MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) },
+    { MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) },
+    { MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PG02) },
+    { MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PG06) },
+    { MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PG07) },
+    { MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_UART5_TX), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_UART5_RX), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_UART7_TX), MP_ROM_PTR(&pin_PF07) },
+    { MP_ROM_QSTR(MP_QSTR_UART7_RX), MP_ROM_PTR(&pin_PF06) },
+    { MP_ROM_QSTR(MP_QSTR_UART8_TX), MP_ROM_PTR(&pin_PE01) },
+    { MP_ROM_QSTR(MP_QSTR_UART8_RX), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_SPI3_NSS), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_SPI3_SCK), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_SPI3_MISO), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_SPI3_MOSI), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PF00) },
+    { MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PF01) },
+    { MP_ROM_QSTR(MP_QSTR_I2C4_SCL), MP_ROM_PTR(&pin_PF14) },
+    { MP_ROM_QSTR(MP_QSTR_I2C4_SDA), MP_ROM_PTR(&pin_PF15) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_SWDCLK), MP_ROM_PTR(&pin_PA14) }
 };
 MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/stm/boards/nucleo_h743zi_2/board.c b/ports/stm/boards/nucleo_h743zi_2/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/nucleo_h743zi_2/board.c
+++ b/ports/stm/boards/nucleo_h743zi_2/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h
index 2ac986701..36c55a26a 100644
--- a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h
+++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "NUCLEO STM32H743"
 #define MICROPY_HW_MCU_NAME         "STM32H743"
diff --git a/ports/stm/boards/openmv_h7/board.c b/ports/stm/boards/openmv_h7/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/openmv_h7/board.c
+++ b/ports/stm/boards/openmv_h7/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/openmv_h7/mpconfigboard.h b/ports/stm/boards/openmv_h7/mpconfigboard.h
index 77ae235ec..ffeba28f6 100644
--- a/ports/stm/boards/openmv_h7/mpconfigboard.h
+++ b/ports/stm/boards/openmv_h7/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "OPENMV-H7 R1"
 #define MICROPY_HW_MCU_NAME         "STM32H743"
diff --git a/ports/stm/boards/pyb_nano_v2/mpconfigboard.h b/ports/stm/boards/pyb_nano_v2/mpconfigboard.h
index 7c1ab31e3..0960687d1 100644
--- a/ports/stm/boards/pyb_nano_v2/mpconfigboard.h
+++ b/ports/stm/boards/pyb_nano_v2/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "PYB LR Nano V2"
 #define MICROPY_HW_MCU_NAME         "STM32F411CE"
diff --git a/ports/stm/boards/pyboard_v11/board.c b/ports/stm/boards/pyboard_v11/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/pyboard_v11/board.c
+++ b/ports/stm/boards/pyboard_v11/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/pyboard_v11/mpconfigboard.h b/ports/stm/boards/pyboard_v11/mpconfigboard.h
index 50a90c52b..1ce89a59f 100644
--- a/ports/stm/boards/pyboard_v11/mpconfigboard.h
+++ b/ports/stm/boards/pyboard_v11/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "PyboardV1_1"
 #define MICROPY_HW_MCU_NAME         "STM32F405RG"
diff --git a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h
index 435133954..400e7bb2c 100644
--- a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h
+++ b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "stm32f411ce-blackpill"
 #define MICROPY_HW_MCU_NAME         "STM32F411CE"
diff --git a/ports/stm/boards/stm32f411ce_blackpill/pins.c b/ports/stm/boards/stm32f411ce_blackpill/pins.c
index 16946b8be..7e25ad042 100644
--- a/ports/stm/boards/stm32f411ce_blackpill/pins.c
+++ b/ports/stm/boards/stm32f411ce_blackpill/pins.c
@@ -6,10 +6,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_B14), MP_ROM_PTR(&pin_PB14) },
     { MP_ROM_QSTR(MP_QSTR_B15), MP_ROM_PTR(&pin_PB15) },
     { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) },
-    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) },  //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, //USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) },  // USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, // USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, // USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, // USB (shouldn't be used)
     { MP_ROM_QSTR(MP_QSTR_A15), MP_ROM_PTR(&pin_PA15) },
     { MP_ROM_QSTR(MP_QSTR_B3), MP_ROM_PTR(&pin_PB03) },
     { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) },
diff --git a/ports/stm/boards/stm32f411ce_blackpill_with_flash/mpconfigboard.h b/ports/stm/boards/stm32f411ce_blackpill_with_flash/mpconfigboard.h
index 65e224e47..a7d56209c 100644
--- a/ports/stm/boards/stm32f411ce_blackpill_with_flash/mpconfigboard.h
+++ b/ports/stm/boards/stm32f411ce_blackpill_with_flash/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "stm32f411ce-blackpill-with-flash"
 #define MICROPY_HW_MCU_NAME         "STM32F411CE"
diff --git a/ports/stm/boards/stm32f411ce_blackpill_with_flash/pins.c b/ports/stm/boards/stm32f411ce_blackpill_with_flash/pins.c
index 16946b8be..7e25ad042 100644
--- a/ports/stm/boards/stm32f411ce_blackpill_with_flash/pins.c
+++ b/ports/stm/boards/stm32f411ce_blackpill_with_flash/pins.c
@@ -6,10 +6,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
     { MP_ROM_QSTR(MP_QSTR_B14), MP_ROM_PTR(&pin_PB14) },
     { MP_ROM_QSTR(MP_QSTR_B15), MP_ROM_PTR(&pin_PB15) },
     { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) },
-    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) },  //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, //USB (shouldn't be used)
-    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, //USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) },  // USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, // USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, // USB (shouldn't be used)
+    { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, // USB (shouldn't be used)
     { MP_ROM_QSTR(MP_QSTR_A15), MP_ROM_PTR(&pin_PA15) },
     { MP_ROM_QSTR(MP_QSTR_B3), MP_ROM_PTR(&pin_PB03) },
     { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) },
diff --git a/ports/stm/boards/stm32f411ve_discovery/board.c b/ports/stm/boards/stm32f411ve_discovery/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/stm32f411ve_discovery/board.c
+++ b/ports/stm/boards/stm32f411ve_discovery/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h
index 0be43f4fb..ec6e54833 100644
--- a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h
+++ b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h
@@ -24,13 +24,13 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "STM32F411E_DISCO"
 #define MICROPY_HW_MCU_NAME         "STM32F411xE"
 
-#define FLASH_SIZE                  (0x80000) //512K
-#define FLASH_PAGE_SIZE             (0x4000)  //16K
+#define FLASH_SIZE                  (0x80000) // 512K
+#define FLASH_PAGE_SIZE             (0x4000)  // 16K
 
 #define HSE_VALUE ((uint32_t)8000000)
 #define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal
diff --git a/ports/stm/boards/stm32f411ve_discovery/pins.c b/ports/stm/boards/stm32f411ve_discovery/pins.c
index 673c412d5..626151334 100644
--- a/ports/stm/boards/stm32f411ve_discovery/pins.c
+++ b/ports/stm/boards/stm32f411ve_discovery/pins.c
@@ -1,106 +1,106 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-  //P1
-  { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
-  { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
-  { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
-  { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
-  { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
-  { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
-  { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
-  { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
-  { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
-  { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
-  { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
-  { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
-  { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
-  { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
-  { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
-  { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
-  { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
-  //P2
-  { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) },
-  { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) },
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
-  { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
-  { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
-  { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
-  { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
-  { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
-  { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
-  { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
-  { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
-  { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
-  { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
-  { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
-  { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
-  { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
-  { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
-  { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
-  { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
-  { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
-  { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
-  { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
-  { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
-  //ST LED names
-  { MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) },
-  //more useful LED names
-  { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) },
-  //AnalogIO names
-  { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
-  { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
-  { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
-  //actual LED names
-  { MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) },
+    // P1
+    { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
+    { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
+    { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
+    // P2
+    { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) },
+    { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) },
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
+    { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
+    { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
+    { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
+    // ST LED names
+    { MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) },
+    // more useful LED names
+    { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) },
+    // AnalogIO names
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
+    // actual LED names
+    { MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) },
 };
 MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/stm/boards/stm32f412zg_discovery/board.c b/ports/stm/boards/stm32f412zg_discovery/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/stm32f412zg_discovery/board.c
+++ b/ports/stm/boards/stm32f412zg_discovery/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h
index 6b9ab6467..3ae0761c7 100644
--- a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h
+++ b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "STM32F412G_DISCO"
 #define MICROPY_HW_MCU_NAME         "STM32F412xGS"
diff --git a/ports/stm/boards/stm32f412zg_discovery/pins.c b/ports/stm/boards/stm32f412zg_discovery/pins.c
index ab90b0455..84e646ca7 100644
--- a/ports/stm/boards/stm32f412zg_discovery/pins.c
+++ b/ports/stm/boards/stm32f412zg_discovery/pins.c
@@ -1,94 +1,94 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-  { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
-  { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
-  { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
-  { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
-  { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) },
-  { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) },
-  { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) },
-  { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
-  { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
-  { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) },
-  { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) },
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
-  { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) },
-  { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
-  { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
-  { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
-  { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) },
-  { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) },
-  { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) },
-  { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) },
-  { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) },
-  { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
-  { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
-  { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PG10) },
-  { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PG11) },
-  { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PF03) },
-  { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PF10) },
-  { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG12) },
-  { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PF04) },
-  { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG13) },
-  { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, //USART6 TX
-  { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, //USART6 RX
-  { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
-  { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC05) }, //alt PB09, see F401ZG-DISCO manual
-  { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB00) }, //alt PB10, see F401ZG-DISCO manual
-  { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PE00) },
-  { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PE01) },
-  { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PE02) },
-  { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) },
+    { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) },
+    { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) },
+    { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) },
+    { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) },
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) },
+    { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) },
+    { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) },
+    { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) },
+    { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) },
+    { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) },
+    { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PG10) },
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PG11) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PF03) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PF10) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG12) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PF04) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG13) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, // USART6 TX
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, // USART6 RX
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC05) }, // alt PB09, see F401ZG-DISCO manual
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB00) }, // alt PB10, see F401ZG-DISCO manual
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PE01) },
+    { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PE03) },
 
-  { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
 };
 MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/stm/boards/stm32f4_discovery/board.c b/ports/stm/boards/stm32f4_discovery/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/stm32f4_discovery/board.c
+++ b/ports/stm/boards/stm32f4_discovery/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/stm32f4_discovery/mpconfigboard.h b/ports/stm/boards/stm32f4_discovery/mpconfigboard.h
index 44ee07378..410c21ec9 100644
--- a/ports/stm/boards/stm32f4_discovery/mpconfigboard.h
+++ b/ports/stm/boards/stm32f4_discovery/mpconfigboard.h
@@ -24,7 +24,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "STM32F4_DISCO"
 #define MICROPY_HW_MCU_NAME         "STM32F407VG"
diff --git a/ports/stm/boards/stm32f4_discovery/pins.c b/ports/stm/boards/stm32f4_discovery/pins.c
index 712932145..ee53fbd78 100644
--- a/ports/stm/boards/stm32f4_discovery/pins.c
+++ b/ports/stm/boards/stm32f4_discovery/pins.c
@@ -1,107 +1,107 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-  //P1
-  { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
-  { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
-  { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
-  { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
-  { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
-  { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
-  { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
-  { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
-  { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
-  { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
-  { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
-  { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
-  { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, // Differs from F411
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
-  { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
-  { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
-  { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
-  { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
-  { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
-  //P2
-  { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) },
-  { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) },
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
-  { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
-  { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
-  { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
-  { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
-  { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
-  { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
-  { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
-  { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
-  { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
-  { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
-  { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
-  { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
-  { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
-  { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
-  { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
-  { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
-  { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
-  { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
-  { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
-  { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
-  //ST LED names
-  { MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) },
-  //more useful LED names
-  { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) },
-  //AnalogIO names
-  { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
-  { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
-  { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
-  //actual LED names
-  { MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) },
+    // P1
+    { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, // Differs from F411
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
+    { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
+    { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
+    // P2
+    { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) },
+    { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) },
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
+    { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
+    { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
+    { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
+    // ST LED names
+    { MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) },
+    // more useful LED names
+    { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) },
+    // AnalogIO names
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) },
+    // actual LED names
+    { MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) },
 };
 MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/stm/boards/stm32f746g_discovery/board.c b/ports/stm/boards/stm32f746g_discovery/board.c
index db2c72727..68bf157b6 100644
--- a/ports/stm/boards/stm32f746g_discovery/board.c
+++ b/ports/stm/boards/stm32f746g_discovery/board.c
@@ -49,7 +49,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h
index 769990a98..afcefe0ce 100644
--- a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h
+++ b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h
@@ -25,7 +25,7 @@
  * THE SOFTWARE.
  */
 
-//Micropython setup
+// Micropython setup
 
 #define MICROPY_HW_BOARD_NAME       "ST STM32F746G Discovery"
 #define MICROPY_HW_MCU_NAME         "STM32F746"
diff --git a/ports/stm/boards/stm32f746g_discovery/pins.c b/ports/stm/boards/stm32f746g_discovery/pins.c
index a859c8d19..bd9c1dcb1 100644
--- a/ports/stm/boards/stm32f746g_discovery/pins.c
+++ b/ports/stm/boards/stm32f746g_discovery/pins.c
@@ -1,110 +1,110 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
-{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
-{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PF10) },
-{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PF09) },
-{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF08) },
-{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF07) },
-{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF06) },
-{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PC07) },
-{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PC06) },
-{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG06) },
-{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PB04) },
-{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG07) },
-{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA08) },
-{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PH06) },
-{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PI03) },
-{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PI02) },
-{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA15) },
-{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PI00) },
-{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB15) },
-{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PB14) },
-{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PI01) },
-{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
-{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) },
-{ MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PI01) },
-{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PI11) },
-{ MP_ROM_QSTR(MP_QSTR_TP1), MP_ROM_PTR(&pin_PH02) },
-{ MP_ROM_QSTR(MP_QSTR_TP2), MP_ROM_PTR(&pin_PI08) },
-{ MP_ROM_QSTR(MP_QSTR_TP3), MP_ROM_PTR(&pin_PH15) },
-{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_PD06) },
-{ MP_ROM_QSTR(MP_QSTR_AUDIO_SDA), MP_ROM_PTR(&pin_PH08) },
-{ MP_ROM_QSTR(MP_QSTR_AUDIO_SCL), MP_ROM_PTR(&pin_PH07) },
-{ MP_ROM_QSTR(MP_QSTR_EXT_SDA), MP_ROM_PTR(&pin_PB09) },
-{ MP_ROM_QSTR(MP_QSTR_EXT_SCL), MP_ROM_PTR(&pin_PB08) },
-{ MP_ROM_QSTR(MP_QSTR_EXT_RST), MP_ROM_PTR(&pin_PG03) },
-{ MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) },
-{ MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) },
-{ MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) },
-{ MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) },
-{ MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) },
-{ MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) },
-{ MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PC13) },
-{ MP_ROM_QSTR(MP_QSTR_LCD_BL_CTRL), MP_ROM_PTR(&pin_PK03) },
-{ MP_ROM_QSTR(MP_QSTR_LCD_INT), MP_ROM_PTR(&pin_PI13) },
-{ MP_ROM_QSTR(MP_QSTR_LCD_SDA), MP_ROM_PTR(&pin_PH08) },
-{ MP_ROM_QSTR(MP_QSTR_LCD_SCL), MP_ROM_PTR(&pin_PH07) },
-{ MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PD05) },
-{ MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PD04) },
-{ MP_ROM_QSTR(MP_QSTR_OTG_HS_OVER_CURRENT), MP_ROM_PTR(&pin_PE03) },
-{ MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PJ12) },
-{ MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) },
-{ MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) },
-{ MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) },
-{ MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PA09) },
-{ MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PB07) },
-{ MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_PB13) },
-{ MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_PB12) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXER), MP_ROM_PTR(&pin_PG02) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) },
-{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PG14) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDCKE0), MP_ROM_PTR(&pin_PC03) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDNE0), MP_ROM_PTR(&pin_PH03) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDCLK), MP_ROM_PTR(&pin_PG08) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDNCAS), MP_ROM_PTR(&pin_PG15) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDNRAS), MP_ROM_PTR(&pin_PF11) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDNWE), MP_ROM_PTR(&pin_PH05) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_BA0), MP_ROM_PTR(&pin_PG04) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_BA1), MP_ROM_PTR(&pin_PG05) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_NBL0), MP_ROM_PTR(&pin_PE00) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_NBL1), MP_ROM_PTR(&pin_PE01) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A0), MP_ROM_PTR(&pin_PF00) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A1), MP_ROM_PTR(&pin_PF01) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A2), MP_ROM_PTR(&pin_PF02) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A3), MP_ROM_PTR(&pin_PF03) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A4), MP_ROM_PTR(&pin_PF04) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A5), MP_ROM_PTR(&pin_PF05) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A6), MP_ROM_PTR(&pin_PF12) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A7), MP_ROM_PTR(&pin_PF13) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A8), MP_ROM_PTR(&pin_PF14) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A9), MP_ROM_PTR(&pin_PF15) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A10), MP_ROM_PTR(&pin_PG00) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_A11), MP_ROM_PTR(&pin_PG01) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D0), MP_ROM_PTR(&pin_PD14) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D1), MP_ROM_PTR(&pin_PD15) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D2), MP_ROM_PTR(&pin_PD00) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D3), MP_ROM_PTR(&pin_PD01) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D4), MP_ROM_PTR(&pin_PE07) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D5), MP_ROM_PTR(&pin_PE08) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D6), MP_ROM_PTR(&pin_PE09) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D7), MP_ROM_PTR(&pin_PE10) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D8), MP_ROM_PTR(&pin_PE11) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D9), MP_ROM_PTR(&pin_PE12) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D10), MP_ROM_PTR(&pin_PE13) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D11), MP_ROM_PTR(&pin_PE14) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D12), MP_ROM_PTR(&pin_PE15) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D13), MP_ROM_PTR(&pin_PD08) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D14), MP_ROM_PTR(&pin_PD09) },
-{ MP_ROM_QSTR(MP_QSTR_SDRAM_D15), MP_ROM_PTR(&pin_PD10) },
-{ MP_ROM_QSTR(MP_QSTR_I2C3_SDA), MP_ROM_PTR(&pin_PH08) },
-{ MP_ROM_QSTR(MP_QSTR_I2C3_SCL), MP_ROM_PTR(&pin_PH07) },
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PF10) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PF09) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF08) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF07) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF06) },
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG06) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG07) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PH06) },
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PI03) },
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PI02) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PI00) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PI01) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PI01) },
+    { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PI11) },
+    { MP_ROM_QSTR(MP_QSTR_TP1), MP_ROM_PTR(&pin_PH02) },
+    { MP_ROM_QSTR(MP_QSTR_TP2), MP_ROM_PTR(&pin_PI08) },
+    { MP_ROM_QSTR(MP_QSTR_TP3), MP_ROM_PTR(&pin_PH15) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_SDA), MP_ROM_PTR(&pin_PH08) },
+    { MP_ROM_QSTR(MP_QSTR_AUDIO_SCL), MP_ROM_PTR(&pin_PH07) },
+    { MP_ROM_QSTR(MP_QSTR_EXT_SDA), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_EXT_SCL), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_EXT_RST), MP_ROM_PTR(&pin_PG03) },
+    { MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_BL_CTRL), MP_ROM_PTR(&pin_PK03) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_INT), MP_ROM_PTR(&pin_PI13) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_SDA), MP_ROM_PTR(&pin_PH08) },
+    { MP_ROM_QSTR(MP_QSTR_LCD_SCL), MP_ROM_PTR(&pin_PH07) },
+    { MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_OTG_HS_OVER_CURRENT), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PJ12) },
+    { MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXER), MP_ROM_PTR(&pin_PG02) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) },
+    { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PG14) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_SDCKE0), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_SDNE0), MP_ROM_PTR(&pin_PH03) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_SDCLK), MP_ROM_PTR(&pin_PG08) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_SDNCAS), MP_ROM_PTR(&pin_PG15) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_SDNRAS), MP_ROM_PTR(&pin_PF11) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_SDNWE), MP_ROM_PTR(&pin_PH05) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_BA0), MP_ROM_PTR(&pin_PG04) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_BA1), MP_ROM_PTR(&pin_PG05) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_NBL0), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_NBL1), MP_ROM_PTR(&pin_PE01) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A0), MP_ROM_PTR(&pin_PF00) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A1), MP_ROM_PTR(&pin_PF01) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A2), MP_ROM_PTR(&pin_PF02) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A3), MP_ROM_PTR(&pin_PF03) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A4), MP_ROM_PTR(&pin_PF04) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A5), MP_ROM_PTR(&pin_PF05) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A6), MP_ROM_PTR(&pin_PF12) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A7), MP_ROM_PTR(&pin_PF13) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A8), MP_ROM_PTR(&pin_PF14) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A9), MP_ROM_PTR(&pin_PF15) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A10), MP_ROM_PTR(&pin_PG00) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_A11), MP_ROM_PTR(&pin_PG01) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D0), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D1), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D2), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D3), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D4), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D5), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D6), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D7), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D8), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D9), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D10), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D11), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D12), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D13), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D14), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_SDRAM_D15), MP_ROM_PTR(&pin_PD10) },
+    { MP_ROM_QSTR(MP_QSTR_I2C3_SDA), MP_ROM_PTR(&pin_PH08) },
+    { MP_ROM_QSTR(MP_QSTR_I2C3_SCL), MP_ROM_PTR(&pin_PH07) },
 };
 MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/stm/boards/system_stm32f4xx.c b/ports/stm/boards/system_stm32f4xx.c
index d8c745dbb..39dc72705 100644
--- a/ports/stm/boards/system_stm32f4xx.c
+++ b/ports/stm/boards/system_stm32f4xx.c
@@ -89,11 +89,11 @@
 #include "stm32f4xx.h"
 #include "py/mpconfig.h"
 
-#if !defined  (HSE_VALUE)
+#if !defined(HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
-#if !defined  (HSI_VALUE)
+#if !defined(HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
@@ -115,15 +115,15 @@
 
 /************************* Miscellaneous Configuration ************************/
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
- || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) \
+    || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \
+    || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
           STM32F412Zx || STM32F412Vx */
 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \
+    || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /* #define DATA_IN_ExtSDRAM */
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
           STM32F479xx */
@@ -150,7 +150,7 @@
 /** @addtogroup STM32F4xx_System_Private_Variables
   * @{
   */
-  /* This variable is updated in three ways:
+/* This variable is updated in three ways:
       1) by calling CMSIS function SystemCoreClockUpdate()
       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
@@ -160,7 +160,7 @@
   */
 uint32_t SystemCoreClock = 16000000;
 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
 /**
   * @}
   */
@@ -169,8 +169,8 @@ const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
   * @{
   */
 
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void);
+#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
+static void SystemInit_ExtMemCtl(void);
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
 /**
@@ -188,43 +188,42 @@ const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
   * @param  None
   * @retval None
   */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
+void SystemInit(void) {
+    /* FPU settings ------------------------------------------------------------*/
+    #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  /* set CP10 and CP11 Full Access */
+    #endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
 
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
 
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
 
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x24003010;
 
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
 
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
 
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+    #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
+    SystemInit_ExtMemCtl();
+    #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
-  /* Configure the Vector Table location add offset address ------------------*/
-#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already
-  #ifdef VECT_TAB_SRAM
+    /* Configure the Vector Table location add offset address ------------------*/
+    #if !(BOARD_VTOR_DEFER) // only set VTOR if the bootloader hasn't already
+    #ifdef VECT_TAB_SRAM
     SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-  #else
+    #else
     SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-  #endif
-#endif
+    #endif
+    #endif
 }
 
 /**
@@ -263,57 +262,53 @@ void SystemInit(void)
   * @param  None
   * @retval None
   */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
+void SystemCoreClockUpdate(void) {
+    uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+    /* Get SYSCLK source -------------------------------------------------------*/
+    tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+    switch (tmp)
+    {
+        case 0x00: /* HSI used as system clock source */
+            SystemCoreClock = HSI_VALUE;
+            break;
+        case 0x04: /* HSE used as system clock source */
+            SystemCoreClock = HSE_VALUE;
+            break;
+        case 0x08: /* PLL used as system clock source */
+
+            /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+               SYSCLK = PLL_VCO / PLL_P
+               */
+            pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+            pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+            if (pllsource != 0) {
+                /* HSE used as PLL clock source */
+                pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+            } else {
+                /* HSI used as PLL clock source */
+                pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+            }
+
+            pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
+            SystemCoreClock = pllvco / pllp;
+            break;
+        default:
+            SystemCoreClock = HSI_VALUE;
+            break;
+    }
+    /* Compute HCLK frequency --------------------------------------------------*/
+    /* Get HCLK prescaler */
+    tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+    /* HCLK frequency */
+    SystemCoreClock >>= tmp;
 }
 
-#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \
+    || defined(STM32F469xx) || defined(STM32F479xx)
 /**
   * @brief  Setup the external memory controller.
   *         Called in startup_stm32f4xx.s before jump to main.
@@ -322,161 +317,157 @@ void SystemCoreClockUpdate(void)
   * @param  None
   * @retval None
   */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0x00;
-
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register __IO uint32_t index;
-
-  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
-  RCC->AHB1ENR |= 0x000001F8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0xCCCCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PFx pins in Alternate function mode */
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0xCCCCCCCC;
-  GPIOG->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PGx pins in Alternate function mode */
-  GPIOG->MODER   = 0xAAAAAAAA;
-  /* Configure PGx pins speed to 50 MHz */
-  GPIOG->OSPEEDR = 0xAAAAAAAA;
-  /* Configure PGx pins Output type to push-pull */
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
-  GPIOG->PUPDR   = 0x00000000;
-
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */
-  GPIOH->PUPDR   = 0x00000000;
-
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */
-  GPIOI->PUPDR   = 0x00000000;
+void SystemInit_ExtMemCtl(void) {
+    __IO uint32_t tmp = 0x00;
+
+    register uint32_t tmpreg = 0, timeout = 0xFFFF;
+    register __IO uint32_t index;
+
+    /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+    RCC->AHB1ENR |= 0x000001F8;
+
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+    /* Connect PDx pins to FMC Alternate function */
+    GPIOD->AFR[0] = 0x00CCC0CC;
+    GPIOD->AFR[1] = 0xCCCCCCCC;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOD->MODER = 0xAAAA0A8A;
+    /* Configure PDx pins speed to 100 MHz */
+    GPIOD->OSPEEDR = 0xFFFF0FCF;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOD->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOD->PUPDR = 0x00000000;
+
+    /* Connect PEx pins to FMC Alternate function */
+    GPIOE->AFR[0] = 0xC00CC0CC;
+    GPIOE->AFR[1] = 0xCCCCCCCC;
+    /* Configure PEx pins in Alternate function mode */
+    GPIOE->MODER = 0xAAAA828A;
+    /* Configure PEx pins speed to 100 MHz */
+    GPIOE->OSPEEDR = 0xFFFFC3CF;
+    /* Configure PEx pins Output type to push-pull */
+    GPIOE->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PEx pins */
+    GPIOE->PUPDR = 0x00000000;
+
+    /* Connect PFx pins to FMC Alternate function */
+    GPIOF->AFR[0] = 0xCCCCCCCC;
+    GPIOF->AFR[1] = 0xCCCCCCCC;
+    /* Configure PFx pins in Alternate function mode */
+    GPIOF->MODER = 0xAA800AAA;
+    /* Configure PFx pins speed to 50 MHz */
+    GPIOF->OSPEEDR = 0xAA800AAA;
+    /* Configure PFx pins Output type to push-pull */
+    GPIOF->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PFx pins */
+    GPIOF->PUPDR = 0x00000000;
+
+    /* Connect PGx pins to FMC Alternate function */
+    GPIOG->AFR[0] = 0xCCCCCCCC;
+    GPIOG->AFR[1] = 0xCCCCCCCC;
+    /* Configure PGx pins in Alternate function mode */
+    GPIOG->MODER = 0xAAAAAAAA;
+    /* Configure PGx pins speed to 50 MHz */
+    GPIOG->OSPEEDR = 0xAAAAAAAA;
+    /* Configure PGx pins Output type to push-pull */
+    GPIOG->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PGx pins */
+    GPIOG->PUPDR = 0x00000000;
+
+    /* Connect PHx pins to FMC Alternate function */
+    GPIOH->AFR[0] = 0x00C0CC00;
+    GPIOH->AFR[1] = 0xCCCCCCCC;
+    /* Configure PHx pins in Alternate function mode */
+    GPIOH->MODER = 0xAAAA08A0;
+    /* Configure PHx pins speed to 50 MHz */
+    GPIOH->OSPEEDR = 0xAAAA08A0;
+    /* Configure PHx pins Output type to push-pull */
+    GPIOH->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PHx pins */
+    GPIOH->PUPDR = 0x00000000;
+
+    /* Connect PIx pins to FMC Alternate function */
+    GPIOI->AFR[0] = 0xCCCCCCCC;
+    GPIOI->AFR[1] = 0x00000CC0;
+    /* Configure PIx pins in Alternate function mode */
+    GPIOI->MODER = 0x0028AAAA;
+    /* Configure PIx pins speed to 50 MHz */
+    GPIOI->OSPEEDR = 0x0028AAAA;
+    /* Configure PIx pins Output type to push-pull */
+    GPIOI->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PIx pins */
+    GPIOI->PUPDR = 0x00000000;
 
 /*-- FMC Configuration -------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  FMC_Bank5_6->SDCR[0] = 0x000019E4;
-  FMC_Bank5_6->SDTR[0] = 0x01115351;
-
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011;
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
+    /* Enable the FMC interface clock */
+    RCC->AHB3ENR |= 0x00000001;
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
 
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x00000073;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
+    FMC_Bank5_6->SDCR[0] = 0x000019E4;
+    FMC_Bank5_6->SDTR[0] = 0x01115351;
 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
+    /* SDRAM initialization sequence */
+    /* Clock enable command */
+    FMC_Bank5_6->SDCMR = 0x00000011;
     tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0];
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[2]  = 0x00001011;
-  FMC_Bank1->BTCR[3]  = 0x00000201;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-#if defined(STM32F469xx) || defined(STM32F479xx)
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[2]  = 0x00001091;
-  FMC_Bank1->BTCR[3]  = 0x00110212;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F469xx || STM32F479xx */
-
-  (void)(tmp);
+    while ((tmpreg != 0) && (timeout-- > 0)) {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Delay */
+    for (index = 0; index < 1000; index++) {;
+    }
+
+    /* PALL command */
+    FMC_Bank5_6->SDCMR = 0x00000012;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0)) {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Auto refresh command */
+    FMC_Bank5_6->SDCMR = 0x00000073;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0)) {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* MRD register program */
+    FMC_Bank5_6->SDCMR = 0x00046014;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0)) {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Set refresh count */
+    tmpreg = FMC_Bank5_6->SDRTR;
+    FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C << 1));
+
+    /* Disable write protection */
+    tmpreg = FMC_Bank5_6->SDCR[0];
+    FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+    #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+    /* Configure and enable Bank1_SRAM2 */
+    FMC_Bank1->BTCR[2] = 0x00001011;
+    FMC_Bank1->BTCR[3] = 0x00000201;
+    FMC_Bank1E->BWTR[2] = 0x0fffffff;
+    #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+    #if defined(STM32F469xx) || defined(STM32F479xx)
+    /* Configure and enable Bank1_SRAM2 */
+    FMC_Bank1->BTCR[2] = 0x00001091;
+    FMC_Bank1->BTCR[3] = 0x00110212;
+    FMC_Bank1E->BWTR[2] = 0x0fffffff;
+    #endif /* STM32F469xx || STM32F479xx */
+
+    (void)(tmp);
 }
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+#elif defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
 /**
   * @brief  Setup the external memory controller.
   *         Called in startup_stm32f4xx.s before jump to main.
@@ -485,293 +476,289 @@ void SystemInit_ExtMemCtl(void)
   * @param  None
   * @retval None
   */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0x00;
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#if defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register __IO uint32_t index;
-
-#if defined(STM32F446xx)
-  /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
-      clock */
-  RCC->AHB1ENR |= 0x0000007D;
-#else
-  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-#endif /* STM32F446xx */
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
-#if defined(STM32F446xx)
-  /* Connect PAx pins to FMC Alternate function */
-  GPIOA->AFR[0]  |= 0xC0000000;
-  GPIOA->AFR[1]  |= 0x00000000;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOA->MODER   |= 0x00008000;
-  /* Configure PDx pins speed to 50 MHz */
-  GPIOA->OSPEEDR |= 0x00008000;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOA->OTYPER  |= 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOA->PUPDR   |= 0x00000000;
-
-  /* Connect PCx pins to FMC Alternate function */
-  GPIOC->AFR[0]  |= 0x00CC0000;
-  GPIOC->AFR[1]  |= 0x00000000;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOC->MODER   |= 0x00000A00;
-  /* Configure PDx pins speed to 50 MHz */
-  GPIOC->OSPEEDR |= 0x00000A00;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOC->OTYPER  |= 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOC->PUPDR   |= 0x00000000;
-#endif /* STM32F446xx */
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */
-  GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0xCCCCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PFx pins in Alternate function mode */
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0xCCCCCCCC;
-  GPIOG->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PGx pins in Alternate function mode */
-  GPIOG->MODER   = 0xAAAAAAAA;
-  /* Configure PGx pins speed to 50 MHz */
-  GPIOG->OSPEEDR = 0xAAAAAAAA;
-  /* Configure PGx pins Output type to push-pull */
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
-  GPIOG->PUPDR   = 0x00000000;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */
-  GPIOH->PUPDR   = 0x00000000;
-
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */
-  GPIOI->PUPDR   = 0x00000000;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+void SystemInit_ExtMemCtl(void) {
+    __IO uint32_t tmp = 0x00;
+    #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \
+    || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    #if defined(DATA_IN_ExtSDRAM)
+    register uint32_t tmpreg = 0, timeout = 0xFFFF;
+    register __IO uint32_t index;
+
+    #if defined(STM32F446xx)
+    /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+        clock */
+    RCC->AHB1ENR |= 0x0000007D;
+    #else
+    /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+        clock */
+    RCC->AHB1ENR |= 0x000001F8;
+    #endif /* STM32F446xx */
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+    #if defined(STM32F446xx)
+    /* Connect PAx pins to FMC Alternate function */
+    GPIOA->AFR[0] |= 0xC0000000;
+    GPIOA->AFR[1] |= 0x00000000;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOA->MODER |= 0x00008000;
+    /* Configure PDx pins speed to 50 MHz */
+    GPIOA->OSPEEDR |= 0x00008000;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOA->OTYPER |= 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOA->PUPDR |= 0x00000000;
+
+    /* Connect PCx pins to FMC Alternate function */
+    GPIOC->AFR[0] |= 0x00CC0000;
+    GPIOC->AFR[1] |= 0x00000000;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOC->MODER |= 0x00000A00;
+    /* Configure PDx pins speed to 50 MHz */
+    GPIOC->OSPEEDR |= 0x00000A00;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOC->OTYPER |= 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOC->PUPDR |= 0x00000000;
+    #endif /* STM32F446xx */
+
+    /* Connect PDx pins to FMC Alternate function */
+    GPIOD->AFR[0] = 0x000000CC;
+    GPIOD->AFR[1] = 0xCC000CCC;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOD->MODER = 0xA02A000A;
+    /* Configure PDx pins speed to 50 MHz */
+    GPIOD->OSPEEDR = 0xA02A000A;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOD->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOD->PUPDR = 0x00000000;
+
+    /* Connect PEx pins to FMC Alternate function */
+    GPIOE->AFR[0] = 0xC00000CC;
+    GPIOE->AFR[1] = 0xCCCCCCCC;
+    /* Configure PEx pins in Alternate function mode */
+    GPIOE->MODER = 0xAAAA800A;
+    /* Configure PEx pins speed to 50 MHz */
+    GPIOE->OSPEEDR = 0xAAAA800A;
+    /* Configure PEx pins Output type to push-pull */
+    GPIOE->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PEx pins */
+    GPIOE->PUPDR = 0x00000000;
+
+    /* Connect PFx pins to FMC Alternate function */
+    GPIOF->AFR[0] = 0xCCCCCCCC;
+    GPIOF->AFR[1] = 0xCCCCCCCC;
+    /* Configure PFx pins in Alternate function mode */
+    GPIOF->MODER = 0xAA800AAA;
+    /* Configure PFx pins speed to 50 MHz */
+    GPIOF->OSPEEDR = 0xAA800AAA;
+    /* Configure PFx pins Output type to push-pull */
+    GPIOF->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PFx pins */
+    GPIOF->PUPDR = 0x00000000;
+
+    /* Connect PGx pins to FMC Alternate function */
+    GPIOG->AFR[0] = 0xCCCCCCCC;
+    GPIOG->AFR[1] = 0xCCCCCCCC;
+    /* Configure PGx pins in Alternate function mode */
+    GPIOG->MODER = 0xAAAAAAAA;
+    /* Configure PGx pins speed to 50 MHz */
+    GPIOG->OSPEEDR = 0xAAAAAAAA;
+    /* Configure PGx pins Output type to push-pull */
+    GPIOG->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PGx pins */
+    GPIOG->PUPDR = 0x00000000;
+
+    #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \
+    || defined(STM32F469xx) || defined(STM32F479xx)
+    /* Connect PHx pins to FMC Alternate function */
+    GPIOH->AFR[0] = 0x00C0CC00;
+    GPIOH->AFR[1] = 0xCCCCCCCC;
+    /* Configure PHx pins in Alternate function mode */
+    GPIOH->MODER = 0xAAAA08A0;
+    /* Configure PHx pins speed to 50 MHz */
+    GPIOH->OSPEEDR = 0xAAAA08A0;
+    /* Configure PHx pins Output type to push-pull */
+    GPIOH->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PHx pins */
+    GPIOH->PUPDR = 0x00000000;
+
+    /* Connect PIx pins to FMC Alternate function */
+    GPIOI->AFR[0] = 0xCCCCCCCC;
+    GPIOI->AFR[1] = 0x00000CC0;
+    /* Configure PIx pins in Alternate function mode */
+    GPIOI->MODER = 0x0028AAAA;
+    /* Configure PIx pins speed to 50 MHz */
+    GPIOI->OSPEEDR = 0x0028AAAA;
+    /* Configure PIx pins Output type to push-pull */
+    GPIOI->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PIx pins */
+    GPIOI->PUPDR = 0x00000000;
+    #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 
 /*-- FMC Configuration -------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable SDRAM bank1 */
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCR[0] = 0x00001954;
-#else
-  FMC_Bank5_6->SDCR[0] = 0x000019E4;
-#endif /* STM32F446xx */
-  FMC_Bank5_6->SDTR[0] = 0x01115351;
-
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011;
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Auto refresh command */
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-#else
-  FMC_Bank5_6->SDCMR = 0x00000073;
-#endif /* STM32F446xx */
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* MRD register program */
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCMR = 0x00044014;
-#else
-  FMC_Bank5_6->SDCMR = 0x00046014;
-#endif /* STM32F446xx */
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
+    /* Enable the FMC interface clock */
+    RCC->AHB3ENR |= 0x00000001;
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+    /* Configure and enable SDRAM bank1 */
+    #if defined(STM32F446xx)
+    FMC_Bank5_6->SDCR[0] = 0x00001954;
+    #else
+    FMC_Bank5_6->SDCR[0] = 0x000019E4;
+    #endif /* STM32F446xx */
+    FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+    /* SDRAM initialization sequence */
+    /* Clock enable command */
+    FMC_Bank5_6->SDCMR = 0x00000011;
     tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
-#else
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-#endif /* STM32F446xx */
-
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0];
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-#endif /* DATA_IN_ExtSDRAM */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
- || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
-
-#if defined(DATA_IN_ExtSRAM)
+    while ((tmpreg != 0) && (timeout-- > 0)) {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Delay */
+    for (index = 0; index < 1000; index++) {;
+    }
+
+    /* PALL command */
+    FMC_Bank5_6->SDCMR = 0x00000012;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0)) {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Auto refresh command */
+    #if defined(STM32F446xx)
+    FMC_Bank5_6->SDCMR = 0x000000F3;
+    #else
+    FMC_Bank5_6->SDCMR = 0x00000073;
+    #endif /* STM32F446xx */
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0)) {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* MRD register program */
+    #if defined(STM32F446xx)
+    FMC_Bank5_6->SDCMR = 0x00044014;
+    #else
+    FMC_Bank5_6->SDCMR = 0x00046014;
+    #endif /* STM32F446xx */
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0)) {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Set refresh count */
+    tmpreg = FMC_Bank5_6->SDRTR;
+    #if defined(STM32F446xx)
+    FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C << 1));
+    #else
+    FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C << 1));
+    #endif /* STM32F446xx */
+
+    /* Disable write protection */
+    tmpreg = FMC_Bank5_6->SDCR[0];
+    FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+    #endif /* DATA_IN_ExtSDRAM */
+    #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+    #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) \
+    || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \
+    || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+    #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */
-  GPIOG->MODER   = 0x00085AAA;
-  /* Configure PGx pins speed to 100 MHz */
-  GPIOG->OSPEEDR = 0x000CAFFF;
-  /* Configure PGx pins Output type to push-pull */
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
-  GPIOG->PUPDR   = 0x00000000;
+    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+    RCC->AHB1ENR |= 0x00000078;
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+
+    /* Connect PDx pins to FMC Alternate function */
+    GPIOD->AFR[0] = 0x00CCC0CC;
+    GPIOD->AFR[1] = 0xCCCCCCCC;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOD->MODER = 0xAAAA0A8A;
+    /* Configure PDx pins speed to 100 MHz */
+    GPIOD->OSPEEDR = 0xFFFF0FCF;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOD->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOD->PUPDR = 0x00000000;
+
+    /* Connect PEx pins to FMC Alternate function */
+    GPIOE->AFR[0] = 0xC00CC0CC;
+    GPIOE->AFR[1] = 0xCCCCCCCC;
+    /* Configure PEx pins in Alternate function mode */
+    GPIOE->MODER = 0xAAAA828A;
+    /* Configure PEx pins speed to 100 MHz */
+    GPIOE->OSPEEDR = 0xFFFFC3CF;
+    /* Configure PEx pins Output type to push-pull */
+    GPIOE->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PEx pins */
+    GPIOE->PUPDR = 0x00000000;
+
+    /* Connect PFx pins to FMC Alternate function */
+    GPIOF->AFR[0] = 0x00CCCCCC;
+    GPIOF->AFR[1] = 0xCCCC0000;
+    /* Configure PFx pins in Alternate function mode */
+    GPIOF->MODER = 0xAA000AAA;
+    /* Configure PFx pins speed to 100 MHz */
+    GPIOF->OSPEEDR = 0xFF000FFF;
+    /* Configure PFx pins Output type to push-pull */
+    GPIOF->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PFx pins */
+    GPIOF->PUPDR = 0x00000000;
+
+    /* Connect PGx pins to FMC Alternate function */
+    GPIOG->AFR[0] = 0x00CCCCCC;
+    GPIOG->AFR[1] = 0x000000C0;
+    /* Configure PGx pins in Alternate function mode */
+    GPIOG->MODER = 0x00085AAA;
+    /* Configure PGx pins speed to 100 MHz */
+    GPIOG->OSPEEDR = 0x000CAFFF;
+    /* Configure PGx pins Output type to push-pull */
+    GPIOG->OTYPER = 0x00000000;
+    /* No pull-up, pull-down for PGx pins */
+    GPIOG->PUPDR = 0x00000000;
 
 /*-- FMC/FSMC Configuration --------------------------------------------------*/
-  /* Enable the FMC/FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[2]  = 0x00001011;
-  FMC_Bank1->BTCR[3]  = 0x00000201;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-#if defined(STM32F469xx) || defined(STM32F479xx)
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[2]  = 0x00001091;
-  FMC_Bank1->BTCR[3]  = 0x00110212;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
-   || defined(STM32F412Zx) || defined(STM32F412Vx)
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
-  /* Configure and enable Bank1_SRAM2 */
-  FSMC_Bank1->BTCR[2]  = 0x00001011;
-  FSMC_Bank1->BTCR[3]  = 0x00000201;
-  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
-
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+    /* Enable the FMC/FSMC interface clock */
+    RCC->AHB3ENR |= 0x00000001;
+
+    #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+    /* Configure and enable Bank1_SRAM2 */
+    FMC_Bank1->BTCR[2] = 0x00001011;
+    FMC_Bank1->BTCR[3] = 0x00000201;
+    FMC_Bank1E->BWTR[2] = 0x0fffffff;
+    #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+    #if defined(STM32F469xx) || defined(STM32F479xx)
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+    /* Configure and enable Bank1_SRAM2 */
+    FMC_Bank1->BTCR[2] = 0x00001091;
+    FMC_Bank1->BTCR[3] = 0x00110212;
+    FMC_Bank1E->BWTR[2] = 0x0fffffff;
+    #endif /* STM32F469xx || STM32F479xx */
+    #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) \
+    || defined(STM32F412Zx) || defined(STM32F412Vx)
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+    /* Configure and enable Bank1_SRAM2 */
+    FSMC_Bank1->BTCR[2] = 0x00001011;
+    FSMC_Bank1->BTCR[3] = 0x00000201;
+    FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+    #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+    #endif /* DATA_IN_ExtSRAM */
+    #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
           STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */
-  (void)(tmp);
+    (void)(tmp);
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
 /**
diff --git a/ports/stm/boards/system_stm32f7xx.c b/ports/stm/boards/system_stm32f7xx.c
index 4aebc3d35..450283ae5 100644
--- a/ports/stm/boards/system_stm32f7xx.c
+++ b/ports/stm/boards/system_stm32f7xx.c
@@ -47,11 +47,11 @@
 
 #include "stm32f7xx.h"
 
-#if !defined  (HSE_VALUE)
+#if !defined(HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
-#if !defined  (HSI_VALUE)
+#if !defined(HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
@@ -96,7 +96,7 @@
   * @{
   */
 
-  /* This variable is updated in three ways:
+/* This variable is updated in three ways:
       1) by calling CMSIS function SystemCoreClockUpdate()
       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
@@ -104,9 +104,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 16000000;
-  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
 
 /**
   * @}
@@ -131,21 +131,20 @@
   * @param  None
   * @retval None
   */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-#endif
+void SystemInit(void) {
+    /* FPU settings ------------------------------------------------------------*/
+    #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+    #endif
 
-  /* Configure the Vector Table location add offset address ------------------*/
-#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already
+    /* Configure the Vector Table location add offset address ------------------*/
+    #if !(BOARD_VTOR_DEFER) // only set VTOR if the bootloader hasn't already
     #ifdef VECT_TAB_SRAM
-      SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+    SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET;   /* Vector Table Relocation in Internal SRAM */
     #else
-      SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;   /* Vector Table Relocation in Internal FLASH */
+    #endif
     #endif
-#endif
 
 }
 
@@ -185,52 +184,48 @@ void SystemInit(void)
   * @param  None
   * @retval None
   */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
+void SystemCoreClockUpdate(void) {
+    uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+    /* Get SYSCLK source -------------------------------------------------------*/
+    tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+    switch (tmp)
+    {
+        case 0x00: /* HSI used as system clock source */
+            SystemCoreClock = HSI_VALUE;
+            break;
+        case 0x04: /* HSE used as system clock source */
+            SystemCoreClock = HSE_VALUE;
+            break;
+        case 0x08: /* PLL used as system clock source */
+
+            /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+               SYSCLK = PLL_VCO / PLL_P
+               */
+            pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+            pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+            if (pllsource != 0) {
+                /* HSE used as PLL clock source */
+                pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+            } else {
+                /* HSI used as PLL clock source */
+                pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+            }
+
+            pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
+            SystemCoreClock = pllvco / pllp;
+            break;
+        default:
+            SystemCoreClock = HSI_VALUE;
+            break;
+    }
+    /* Compute HCLK frequency --------------------------------------------------*/
+    /* Get HCLK prescaler */
+    tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+    /* HCLK frequency */
+    SystemCoreClock >>= tmp;
 }
 
 /**
diff --git a/ports/stm/boards/system_stm32h7xx.c b/ports/stm/boards/system_stm32h7xx.c
index bbb0f821f..8b782e496 100644
--- a/ports/stm/boards/system_stm32h7xx.c
+++ b/ports/stm/boards/system_stm32h7xx.c
@@ -71,15 +71,15 @@
 
 #include "stm32h7xx.h"
 #include <math.h>
-#if !defined  (HSE_VALUE)
+#if !defined(HSE_VALUE)
 #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
-#if !defined  (CSI_VALUE)
+#if !defined(CSI_VALUE)
   #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* CSI_VALUE */
 
-#if !defined  (HSI_VALUE)
+#if !defined(HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
@@ -126,7 +126,7 @@
 /** @addtogroup STM32H7xx_System_Private_Variables
   * @{
   */
-  /* This variable is updated in three ways:
+/* This variable is updated in three ways:
       1) by calling CMSIS function SystemCoreClockUpdate()
       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
@@ -134,9 +134,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 64000000;
-  uint32_t SystemD2Clock = 64000000;
-  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+uint32_t SystemCoreClock = 64000000;
+uint32_t SystemD2Clock = 64000000;
+const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}
@@ -161,117 +161,115 @@
   * @param  None
   * @retval None
   */
-void SystemInit (void)
-{
-#if defined (DATA_IN_D2_SRAM)
- __IO uint32_t tmpreg;
-#endif /* DATA_IN_D2_SRAM */
-
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= RCC_CR_HSION;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
-  RCC->CR &= 0xEAF6ED7FU;
-
-#if defined(D3_SRAM_BASE)
-  /* Reset D1CFGR register */
-  RCC->D1CFGR = 0x00000000;
-
-  /* Reset D2CFGR register */
-  RCC->D2CFGR = 0x00000000;
-
-  /* Reset D3CFGR register */
-  RCC->D3CFGR = 0x00000000;
-#else
-  /* Reset CDCFGR1 register */
-  RCC->CDCFGR1 = 0x00000000;
-
-  /* Reset CDCFGR2 register */
-  RCC->CDCFGR2 = 0x00000000;
-
-  /* Reset SRDCFGR register */
-  RCC->SRDCFGR = 0x00000000;
-#endif
-  /* Reset PLLCKSELR register */
-  RCC->PLLCKSELR = 0x00000000;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x00000000;
-  /* Reset PLL1DIVR register */
-  RCC->PLL1DIVR = 0x00000000;
-  /* Reset PLL1FRACR register */
-  RCC->PLL1FRACR = 0x00000000;
-
-  /* Reset PLL2DIVR register */
-  RCC->PLL2DIVR = 0x00000000;
-
-  /* Reset PLL2FRACR register */
-
-  RCC->PLL2FRACR = 0x00000000;
-  /* Reset PLL3DIVR register */
-  RCC->PLL3DIVR = 0x00000000;
-
-  /* Reset PLL3FRACR register */
-  RCC->PLL3FRACR = 0x00000000;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
-
-#if (STM32H7_DEV_ID == 0x450UL)
-  /* dual core CM7 or single core line */
-  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
-  {
-    /* if stm32h7 revY*/
-    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
-    *((__IO uint32_t*)0x51008108) = 0x000000001U;
-  }
-#endif
-
-#if defined (DATA_IN_D2_SRAM)
-  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
-#if defined(RCC_AHB2ENR_D2SRAM3EN)
-  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
-#elif defined(RCC_AHB2ENR_D2SRAM2EN)
-  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
-#else
-  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
-#endif /* RCC_AHB2ENR_D2SRAM3EN */
-
-  tmpreg = RCC->AHB2ENR;
-  (void) tmpreg;
-#endif /* DATA_IN_D2_SRAM */
-
-#if defined(DUAL_CORE) && defined(CORE_CM4)
-  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif /* VECT_TAB_SRAM */
-
-#else
-
-  /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
-#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already
+void SystemInit(void) {
+    #if defined(DATA_IN_D2_SRAM)
+    __IO uint32_t tmpreg;
+    #endif /* DATA_IN_D2_SRAM */
+
+    /* FPU settings ------------------------------------------------------------*/
+    #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2)));  /* set CP10 and CP11 Full Access */
+    #endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= RCC_CR_HSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
+    RCC->CR &= 0xEAF6ED7FU;
+
+    #if defined(D3_SRAM_BASE)
+    /* Reset D1CFGR register */
+    RCC->D1CFGR = 0x00000000;
+
+    /* Reset D2CFGR register */
+    RCC->D2CFGR = 0x00000000;
+
+    /* Reset D3CFGR register */
+    RCC->D3CFGR = 0x00000000;
+    #else
+    /* Reset CDCFGR1 register */
+    RCC->CDCFGR1 = 0x00000000;
+
+    /* Reset CDCFGR2 register */
+    RCC->CDCFGR2 = 0x00000000;
+
+    /* Reset SRDCFGR register */
+    RCC->SRDCFGR = 0x00000000;
+    #endif
+    /* Reset PLLCKSELR register */
+    RCC->PLLCKSELR = 0x00000000;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00000000;
+    /* Reset PLL1DIVR register */
+    RCC->PLL1DIVR = 0x00000000;
+    /* Reset PLL1FRACR register */
+    RCC->PLL1FRACR = 0x00000000;
+
+    /* Reset PLL2DIVR register */
+    RCC->PLL2DIVR = 0x00000000;
+
+    /* Reset PLL2FRACR register */
+
+    RCC->PLL2FRACR = 0x00000000;
+    /* Reset PLL3DIVR register */
+    RCC->PLL3DIVR = 0x00000000;
+
+    /* Reset PLL3FRACR register */
+    RCC->PLL3FRACR = 0x00000000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    #if (STM32H7_DEV_ID == 0x450UL)
+    /* dual core CM7 or single core line */
+    if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) {
+        /* if stm32h7 revY*/
+        /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+        *((__IO uint32_t *)0x51008108) = 0x000000001U;
+    }
+    #endif
+
+    #if defined(DATA_IN_D2_SRAM)
+    /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+    #if defined(RCC_AHB2ENR_D2SRAM3EN)
+    RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+    #elif defined(RCC_AHB2ENR_D2SRAM2EN)
+    RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+    #else
+    RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+    #endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+    tmpreg = RCC->AHB2ENR;
+    (void)tmpreg;
+    #endif /* DATA_IN_D2_SRAM */
+
+    #if defined(DUAL_CORE) && defined(CORE_CM4)
+    /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+    #ifdef VECT_TAB_SRAM
+    SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+    #else
+    SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+    #endif /* VECT_TAB_SRAM */
+
+    #else
+
+    /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
+    #if !(BOARD_VTOR_DEFER) // only set VTOR if the bootloader hasn't already
     #ifdef VECT_TAB_SRAM
-      SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
+    SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET;    /* Vector Table Relocation in Internal AXI-RAM */
     #else
-      SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+    SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET;   /* Vector Table Relocation in Internal FLASH */
+    #endif
     #endif
-#endif
 
-#endif /*DUAL_CORE && CORE_CM4*/
+    #endif /*DUAL_CORE && CORE_CM4*/
 
 }
 
@@ -312,102 +310,98 @@ void SystemInit (void)
   * @param  None
   * @retval None
   */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
-  uint32_t common_system_clock;
-  float_t fracn1, pllvco;
-
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
-    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
-    break;
-
-  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
-    common_system_clock = CSI_VALUE;
-    break;
-
-  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
-    common_system_clock = HSE_VALUE;
-    break;
+void SystemCoreClockUpdate(void) {
+    uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+    uint32_t common_system_clock;
+    float_t fracn1, pllvco;
 
-  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
 
-    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
-    SYSCLK = PLL_VCO / PLLR
-    */
-    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
-    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
-    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
-    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+    /* Get SYSCLK source -------------------------------------------------------*/
 
-    if (pllm != 0U)
+    switch (RCC->CFGR & RCC_CFGR_SWS)
     {
-      switch (pllsource)
-      {
-        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
-
-        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
-        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-
-        break;
-
-        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
-          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-        break;
-
-        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
-          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-        break;
-
-      default:
-          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-        break;
-      }
-      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
-      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+        case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+            common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
+            break;
+
+        case RCC_CFGR_SWS_CSI: /* CSI used as system clock  source */
+            common_system_clock = CSI_VALUE;
+            break;
+
+        case RCC_CFGR_SWS_HSE: /* HSE used as system clock  source */
+            common_system_clock = HSE_VALUE;
+            break;
+
+        case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock  source */
+
+            /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+            SYSCLK = PLL_VCO / PLLR
+            */
+            pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+            pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
+            pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
+            fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
+
+            if (pllm != 0U) {
+                switch (pllsource)
+                {
+                    case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+                        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
+                        pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+
+                        break;
+
+                    case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+                        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+                        break;
+
+                    case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+                        pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+                        break;
+
+                    default:
+                        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+                        break;
+                }
+                pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U);
+                common_system_clock = (uint32_t)(float_t)(pllvco / (float_t)pllp);
+            } else {
+                common_system_clock = 0U;
+            }
+            break;
+
+        default:
+            common_system_clock = CSI_VALUE;
+            break;
     }
-    else
-    {
-      common_system_clock = 0U;
-    }
-    break;
-
-  default:
-    common_system_clock = CSI_VALUE;
-    break;
-  }
 
-  /* Compute SystemClock frequency --------------------------------------------------*/
-#if defined (RCC_D1CFGR_D1CPRE)
-  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+    /* Compute SystemClock frequency --------------------------------------------------*/
+    #if defined(RCC_D1CFGR_D1CPRE)
+    tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos];
 
-  /* common_system_clock frequency : CM7 CPU frequency  */
-  common_system_clock >>= tmp;
+    /* common_system_clock frequency : CM7 CPU frequency  */
+    common_system_clock >>= tmp;
 
-  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+    /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
+    SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 
-#else
-  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+    #else
+    tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos];
 
-  /* common_system_clock frequency : CM7 CPU frequency  */
-  common_system_clock >>= tmp;
+    /* common_system_clock frequency : CM7 CPU frequency  */
+    common_system_clock >>= tmp;
 
-  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+    /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+    SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
 
-#endif
+    #endif
 
-#if defined(DUAL_CORE) && defined(CORE_CM4)
-  SystemCoreClock = SystemD2Clock;
-#else
-  SystemCoreClock = common_system_clock;
-#endif /* DUAL_CORE && CORE_CM4 */
+    #if defined(DUAL_CORE) && defined(CORE_CM4)
+    SystemCoreClock = SystemD2Clock;
+    #else
+    SystemCoreClock = common_system_clock;
+    #endif /* DUAL_CORE && CORE_CM4 */
 }
 
 
diff --git a/ports/stm/boards/thunderpack_v11/board.c b/ports/stm/boards/thunderpack_v11/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/thunderpack_v11/board.c
+++ b/ports/stm/boards/thunderpack_v11/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/thunderpack_v11/mpconfigboard.h b/ports/stm/boards/thunderpack_v11/mpconfigboard.h
index 7d4a8dff3..9c3c116e5 100644
--- a/ports/stm/boards/thunderpack_v11/mpconfigboard.h
+++ b/ports/stm/boards/thunderpack_v11/mpconfigboard.h
@@ -38,7 +38,7 @@
 // Flash config
 #define FLASH_SIZE                  (0x80000)
 #define FLASH_PAGE_SIZE             (0x4000)
-#define BOARD_FLASH_SIZE            (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000)
+#define BOARD_FLASH_SIZE            (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE - 0x2000 - 0xC000)
 
 #define HSE_VALUE                   ((uint32_t)24000000U)
 #define BOARD_OVERWRITE_SWD         (1)
diff --git a/ports/stm/boards/thunderpack_v12/board.c b/ports/stm/boards/thunderpack_v12/board.c
index 781793328..688cfb4de 100644
--- a/ports/stm/boards/thunderpack_v12/board.c
+++ b/ports/stm/boards/thunderpack_v12/board.c
@@ -30,7 +30,7 @@ void board_init(void) {
 }
 
 bool board_requests_safe_mode(void) {
-  return false;
+    return false;
 }
 
 void reset_board(void) {
diff --git a/ports/stm/boards/thunderpack_v12/mpconfigboard.h b/ports/stm/boards/thunderpack_v12/mpconfigboard.h
index fb5f389a3..34a5795ff 100644
--- a/ports/stm/boards/thunderpack_v12/mpconfigboard.h
+++ b/ports/stm/boards/thunderpack_v12/mpconfigboard.h
@@ -35,7 +35,7 @@
 // Flash config
 #define FLASH_SIZE                           (0x80000)
 #define FLASH_PAGE_SIZE                      (0x4000)
-#define BOARD_FLASH_SIZE                     (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000)
+#define BOARD_FLASH_SIZE                     (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE - 0x2000 - 0xC000)
 #define INTERNAL_FLASH_FILESYSTEM_SIZE       0x8000
 
 // On-board flash
diff --git a/ports/stm/common-hal/analogio/AnalogIn.c b/ports/stm/common-hal/analogio/AnalogIn.c
index 588d687ee..35010ac7c 100644
--- a/ports/stm/common-hal/analogio/AnalogIn.c
+++ b/ports/stm/common-hal/analogio/AnalogIn.c
@@ -36,8 +36,8 @@
 #include "stm32f4xx_ll_adc.h"
 #include "stm32f4xx_ll_bus.h"
 
-void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self,
-        const mcu_pin_obj_t *pin) {
+void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self,
+    const mcu_pin_obj_t *pin) {
 
     // No ADC function on pin
     if (pin->adc_unit == 0x00) {
@@ -76,9 +76,9 @@ void common_hal_analogio_analogin_deinit(analogio_analogin_obj_t *self) {
 uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) {
     // Something else might have used the ADC in a different way,
     // so we completely re-initialize it.
-    ADC_TypeDef * ADCx;
+    ADC_TypeDef *ADCx;
 
-    if(self->pin->adc_unit & 0x01) {
+    if (self->pin->adc_unit & 0x01) {
         ADCx = ADC1;
     } else if (self->pin->adc_unit == 0x04) {
         #ifdef ADC3
@@ -89,9 +89,9 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) {
     }
 
     LL_GPIO_SetPinMode(pin_port(self->pin->port), (uint32_t)pin_mask(self->pin->number), LL_GPIO_MODE_ANALOG);
-    //LL_GPIO_PIN_0
+    // LL_GPIO_PIN_0
 
-    //HAL Implementation
+    // HAL Implementation
     ADC_HandleTypeDef AdcHandle;
     ADC_ChannelConfTypeDef sConfig;
 
@@ -110,9 +110,9 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) {
     AdcHandle.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
     HAL_ADC_Init(&AdcHandle);
 
-    sConfig.Channel = (uint32_t)self->pin->adc_channel; //ADC_CHANNEL_0 <-normal iteration, not mask
+    sConfig.Channel = (uint32_t)self->pin->adc_channel; // ADC_CHANNEL_0 <-normal iteration, not mask
     sConfig.Rank = 1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES; //Taken from micropython
+    sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES; // Taken from micropython
     HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
 
     HAL_ADC_Start(&AdcHandle);
diff --git a/ports/stm/common-hal/analogio/AnalogIn.h b/ports/stm/common-hal/analogio/AnalogIn.h
index 910092897..c8e3e0868 100644
--- a/ports/stm/common-hal/analogio/AnalogIn.h
+++ b/ports/stm/common-hal/analogio/AnalogIn.h
@@ -34,7 +34,7 @@
 
 typedef struct {
     mp_obj_base_t base;
-    const mcu_pin_obj_t * pin;
+    const mcu_pin_obj_t *pin;
 } analogio_analogin_obj_t;
 
 static inline uint8_t stm32_adc_units(uint8_t adc_packed) {
diff --git a/ports/stm/common-hal/analogio/AnalogOut.c b/ports/stm/common-hal/analogio/AnalogOut.c
index 69c1f3e04..1a3817a35 100644
--- a/ports/stm/common-hal/analogio/AnalogOut.c
+++ b/ports/stm/common-hal/analogio/AnalogOut.c
@@ -39,15 +39,15 @@
 
 #include "stm32f4xx_hal.h"
 
-//DAC is shared between both channels.
+// DAC is shared between both channels.
 #if HAS_DAC
 DAC_HandleTypeDef handle;
 #endif
 
 STATIC bool dac_on[2];
 
-void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self,
-        const mcu_pin_obj_t *pin) {
+void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self,
+    const mcu_pin_obj_t *pin) {
     #if !(HAS_DAC)
     mp_raise_ValueError(translate("No DAC on chip"));
     #else
@@ -61,17 +61,16 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self,
         mp_raise_ValueError(translate("Invalid DAC pin supplied"));
     }
 
-    //Only init if the shared DAC is empty or reset
+    // Only init if the shared DAC is empty or reset
     if (handle.Instance == NULL || handle.State == HAL_DAC_STATE_RESET) {
         __HAL_RCC_DAC_CLK_ENABLE();
         handle.Instance = DAC;
-        if (HAL_DAC_Init(&handle) != HAL_OK)
-        {
+        if (HAL_DAC_Init(&handle) != HAL_OK) {
             mp_raise_ValueError(translate("DAC Device Init Error"));
         }
     }
 
-    //init channel specific pin
+    // init channel specific pin
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     GPIO_InitStruct.Pin = pin_mask(pin->number);
     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
@@ -100,8 +99,8 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) {
     self->pin = NULL;
     dac_on[self->dac_index] = false;
 
-    //turn off the DAC if both channels are off
-    if(dac_on[0] == false && dac_on[1] == false) {
+    // turn off the DAC if both channels are off
+    if (dac_on[0] == false && dac_on[1] == false) {
         __HAL_RCC_DAC_CLK_DISABLE();
         HAL_DAC_DeInit(&handle);
     }
@@ -109,7 +108,7 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) {
 }
 
 void common_hal_analogio_analogout_set_value(analogio_analogout_obj_t *self,
-        uint16_t value) {
+    uint16_t value) {
     #if HAS_DAC
     HAL_DAC_SetValue(&handle, self->channel, DAC_ALIGN_12B_R, value >> 4);
     HAL_DAC_Start(&handle, self->channel);
diff --git a/ports/stm/common-hal/analogio/AnalogOut.h b/ports/stm/common-hal/analogio/AnalogOut.h
index 46312b460..3c208a611 100644
--- a/ports/stm/common-hal/analogio/AnalogOut.h
+++ b/ports/stm/common-hal/analogio/AnalogOut.h
@@ -36,12 +36,12 @@
 
 typedef struct {
     mp_obj_base_t base;
-#if HAS_DAC
+    #if HAS_DAC
     DAC_ChannelConfTypeDef ch_handle;
-#endif
-    const mcu_pin_obj_t * pin;
+    #endif
+    const mcu_pin_obj_t *pin;
     uint8_t channel;
-    uint8_t dac_index:1;
+    uint8_t dac_index : 1;
 } analogio_analogout_obj_t;
 
 void analogout_reset(void);
diff --git a/ports/stm/common-hal/busio/I2C.c b/ports/stm/common-hal/busio/I2C.c
index 7726b5e87..db6d86c34 100644
--- a/ports/stm/common-hal/busio/I2C.c
+++ b/ports/stm/common-hal/busio/I2C.c
@@ -61,11 +61,11 @@ STATIC bool never_reset_i2c[MAX_I2C];
 #define ALL_CLOCKS 0xFF
 STATIC void i2c_clock_enable(uint8_t mask);
 STATIC void i2c_clock_disable(uint8_t mask);
-STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef * I2Cx);
+STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef *I2Cx);
 
 void i2c_reset(void) {
     uint16_t never_reset_mask = 0x00;
-    for(int i = 0; i < MAX_I2C; i++) {
+    for (int i = 0; i < MAX_I2C; i++) {
         if (!never_reset_i2c[i]) {
             reserved_i2c[i] = false;
         } else {
@@ -76,10 +76,10 @@ void i2c_reset(void) {
 }
 
 void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
-        const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda, uint32_t frequency, uint32_t timeout) {
+    const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) {
 
     // Match pins to I2C objects
-    I2C_TypeDef * I2Cx;
+    I2C_TypeDef *I2Cx;
     uint8_t sda_len = MP_ARRAY_SIZE(mcu_i2c_sda_list);
     uint8_t scl_len = MP_ARRAY_SIZE(mcu_i2c_scl_list);
     bool i2c_taken = false;
@@ -107,7 +107,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
     }
 
     // Handle typedef selection, errors
-    if (self->sda != NULL && self->scl != NULL ) {
+    if (self->sda != NULL && self->scl != NULL) {
         I2Cx = mcu_i2c_banks[self->sda->periph_index - 1];
     } else {
         if (i2c_taken) {
@@ -171,8 +171,8 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
 
     self->frame_in_prog = false;
 
-    //start the receive interrupt chain
-    HAL_NVIC_DisableIRQ(self->irq); //prevent handle lock contention
+    // start the receive interrupt chain
+    HAL_NVIC_DisableIRQ(self->irq); // prevent handle lock contention
     HAL_NVIC_SetPriority(self->irq, 1, 0);
     HAL_NVIC_EnableIRQ(self->irq);
 }
@@ -215,15 +215,15 @@ bool common_hal_busio_i2c_probe(busio_i2c_obj_t *self, uint8_t addr) {
 bool common_hal_busio_i2c_try_lock(busio_i2c_obj_t *self) {
     bool grabbed_lock = false;
 
-    //Critical section code that may be required at some point.
+    // Critical section code that may be required at some point.
     // uint32_t store_primask = __get_PRIMASK();
     // __disable_irq();
     // __DMB();
 
-        if (!self->has_lock) {
-            grabbed_lock = true;
-            self->has_lock = true;
-        }
+    if (!self->has_lock) {
+        grabbed_lock = true;
+        self->has_lock = true;
+    }
 
     // __DMB();
     // __set_PRIMASK(store_primask);
@@ -240,7 +240,7 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) {
 }
 
 uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr,
-                                   const uint8_t *data, size_t len, bool transmit_stop_bit) {
+    const uint8_t *data, size_t len, bool transmit_stop_bit) {
     HAL_StatusTypeDef result;
     if (!transmit_stop_bit) {
         uint32_t xfer_opt;
@@ -251,31 +251,29 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr,
             xfer_opt = I2C_NEXT_FRAME;
         }
         result = HAL_I2C_Master_Seq_Transmit_IT(&(self->handle),
-                                    (uint16_t)(addr << 1), (uint8_t *)data,
-                                    (uint16_t)len, xfer_opt);
-        while (HAL_I2C_GetState(&(self->handle)) != HAL_I2C_STATE_READY)
-        {
+            (uint16_t)(addr << 1), (uint8_t *)data,
+            (uint16_t)len, xfer_opt);
+        while (HAL_I2C_GetState(&(self->handle)) != HAL_I2C_STATE_READY) {
             RUN_BACKGROUND_TASKS;
         }
         self->frame_in_prog = true;
     } else {
         result = HAL_I2C_Master_Transmit(&(self->handle), (uint16_t)(addr << 1),
-                                                        (uint8_t *)data, (uint16_t)len, 500);
+            (uint8_t *)data, (uint16_t)len, 500);
     }
     return result == HAL_OK ? 0 : MP_EIO;
 }
 
 uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr,
-        uint8_t *data, size_t len) {
+    uint8_t *data, size_t len) {
     if (!self->frame_in_prog) {
-        return HAL_I2C_Master_Receive(&(self->handle), (uint16_t)(addr<<1), data, (uint16_t)len, 500)
-                                    == HAL_OK ? 0 : MP_EIO;
+        return HAL_I2C_Master_Receive(&(self->handle), (uint16_t)(addr << 1), data, (uint16_t)len, 500)
+               == HAL_OK ? 0 : MP_EIO;
     } else {
         HAL_StatusTypeDef result = HAL_I2C_Master_Seq_Receive_IT(&(self->handle),
-                                    (uint16_t)(addr << 1), (uint8_t *)data,
-                                    (uint16_t)len, I2C_LAST_FRAME);
-        while (HAL_I2C_GetState(&(self->handle)) != HAL_I2C_STATE_READY)
-        {
+            (uint16_t)(addr << 1), (uint8_t *)data,
+            (uint16_t)len, I2C_LAST_FRAME);
+        while (HAL_I2C_GetState(&(self->handle)) != HAL_I2C_STATE_READY) {
             RUN_BACKGROUND_TASKS;
         }
         self->frame_in_prog = false;
@@ -338,7 +336,7 @@ STATIC void i2c_clock_disable(uint8_t mask) {
     #endif
 }
 
-STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef * I2Cx) {
+STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef *I2Cx) {
     #ifdef I2C1
     if (I2Cx == I2C1) {
         self->irq = I2C1_EV_IRQn;
@@ -362,8 +360,8 @@ STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef * I2Cx) {
 }
 
 STATIC void call_hal_irq(int i2c_num) {
-    //Create casted context pointer
-    busio_i2c_obj_t * context = (busio_i2c_obj_t*)MP_STATE_PORT(cpy_i2c_obj_all)[i2c_num - 1];
+    // Create casted context pointer
+    busio_i2c_obj_t *context = (busio_i2c_obj_t *)MP_STATE_PORT(cpy_i2c_obj_all)[i2c_num - 1];
     if (context != NULL) {
         HAL_NVIC_ClearPendingIRQ(context->irq);
         HAL_I2C_EV_IRQHandler(&context->handle);
diff --git a/ports/stm/common-hal/busio/SPI.c b/ports/stm/common-hal/busio/SPI.c
index 20ee0f6e1..2f26a01cb 100644
--- a/ports/stm/common-hal/busio/SPI.c
+++ b/ports/stm/common-hal/busio/SPI.c
@@ -39,7 +39,7 @@
 // Note that any bugs introduced in this file can cause crashes at startup
 // for chips using external SPI flash.
 
-//arrays use 0 based numbering: SPI1 is stored at index 0
+// arrays use 0 based numbering: SPI1 is stored at index 0
 #define MAX_SPI 6
 
 STATIC bool reserved_spi[MAX_SPI];
@@ -49,28 +49,32 @@ STATIC bool never_reset_spi[MAX_SPI];
 STATIC void spi_clock_enable(uint8_t mask);
 STATIC void spi_clock_disable(uint8_t mask);
 
-STATIC uint32_t get_busclock(SPI_TypeDef * instance) {
+STATIC uint32_t get_busclock(SPI_TypeDef *instance) {
     #if (CPY_STM32H7)
-        if (instance == SPI1 || instance == SPI2 || instance == SPI3) {
-            return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
-        } else if (instance == SPI4 || instance == SPI5) {
-            return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI45);
-        } else {
-            return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
-        }
+    if (instance == SPI1 || instance == SPI2 || instance == SPI3) {
+        return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
+    } else if (instance == SPI4 || instance == SPI5) {
+        return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI45);
+    } else {
+        return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
+    }
     #elif (CPY_STM32F4 || CPY_STM32F7)
-        //SPI2 and 3 are on PCLK1, if they exist.
-        #ifdef SPI2
-            if (instance == SPI2) return HAL_RCC_GetPCLK1Freq();
-        #endif
-        #ifdef SPI3
-            if (instance == SPI3) return HAL_RCC_GetPCLK1Freq();
-        #endif
-        return HAL_RCC_GetPCLK2Freq();
+    // SPI2 and 3 are on PCLK1, if they exist.
+    #ifdef SPI2
+    if (instance == SPI2) {
+        return HAL_RCC_GetPCLK1Freq();
+    }
+    #endif
+    #ifdef SPI3
+    if (instance == SPI3) {
+        return HAL_RCC_GetPCLK1Freq();
+    }
+    #endif
+    return HAL_RCC_GetPCLK2Freq();
     #endif
 }
 
-STATIC uint32_t stm32_baud_to_spi_div(uint32_t baudrate, uint16_t * prescaler, uint32_t busclock) {
+STATIC uint32_t stm32_baud_to_spi_div(uint32_t baudrate, uint16_t *prescaler, uint32_t busclock) {
     static const uint32_t baud_map[8][2] = {
         {2,SPI_BAUDRATEPRESCALER_2},
         {4,SPI_BAUDRATEPRESCALER_4},
@@ -85,13 +89,13 @@ STATIC uint32_t stm32_baud_to_spi_div(uint32_t baudrate, uint16_t * prescaler, u
     uint16_t divisor;
     do {
         divisor = baud_map[i][0];
-        if (baudrate >= (busclock/divisor)) {
+        if (baudrate >= (busclock / divisor)) {
             *prescaler = divisor;
             return baud_map[i][1];
         }
         i++;
     } while (divisor != 256);
-    //only gets here if requested baud is lower than minimum
+    // only gets here if requested baud is lower than minimum
     *prescaler = 256;
     return SPI_BAUDRATEPRESCALER_256;
 }
@@ -109,18 +113,18 @@ void spi_reset(void) {
 }
 
 STATIC const mcu_periph_obj_t *find_pin_function(const mcu_periph_obj_t *table, size_t sz, const mcu_pin_obj_t *pin, int periph_index) {
-    for(size_t i = 0; i<sz; i++, table++) {
-        if(periph_index == table->periph_index && pin == table->pin ) {
+    for (size_t i = 0; i < sz; i++, table++) {
+        if (periph_index == table->periph_index && pin == table->pin) {
             return table;
         }
     }
     return NULL;
 }
 
-//match pins to SPI objects
+// match pins to SPI objects
 STATIC int check_pins(busio_spi_obj_t *self,
-         const mcu_pin_obj_t * sck, const mcu_pin_obj_t * mosi,
-         const mcu_pin_obj_t * miso) {
+    const mcu_pin_obj_t *sck, const mcu_pin_obj_t *mosi,
+    const mcu_pin_obj_t *miso) {
     bool spi_taken = false;
 
     uint8_t sck_len = MP_ARRAY_SIZE(mcu_spi_sck_list);
@@ -146,7 +150,7 @@ STATIC int check_pins(busio_spi_obj_t *self,
             continue;
         }
 
-        if (reserved_spi[periph_index-1]) {
+        if (reserved_spi[periph_index - 1]) {
             spi_taken = true;
             continue;
         }
@@ -166,13 +170,13 @@ STATIC int check_pins(busio_spi_obj_t *self,
 }
 
 void common_hal_busio_spi_construct(busio_spi_obj_t *self,
-         const mcu_pin_obj_t * sck, const mcu_pin_obj_t * mosi,
-         const mcu_pin_obj_t * miso) {
+    const mcu_pin_obj_t *sck, const mcu_pin_obj_t *mosi,
+    const mcu_pin_obj_t *miso) {
 
     int periph_index = check_pins(self, sck, mosi, miso);
-    SPI_TypeDef * SPIx = mcu_spi_banks[periph_index - 1];
+    SPI_TypeDef *SPIx = mcu_spi_banks[periph_index - 1];
 
-    //Start GPIO for each pin
+    // Start GPIO for each pin
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     GPIO_InitStruct.Pin = pin_mask(sck->number);
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -215,8 +219,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
     self->handle.Init.TIMode = SPI_TIMODE_DISABLE;
     self->handle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
     self->handle.Init.CRCPolynomial = 10;
-    if (HAL_SPI_Init(&self->handle) != HAL_OK)
-    {
+    if (HAL_SPI_Init(&self->handle) != HAL_OK) {
         mp_raise_ValueError(translate("SPI Init Error"));
     }
     self->baudrate = (get_busclock(SPIx) / 16);
@@ -254,7 +257,7 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
     if (common_hal_busio_spi_deinited(self)) {
         return;
     }
-    spi_clock_disable(1<<(self->sck->periph_index - 1));
+    spi_clock_disable(1 << (self->sck->periph_index - 1));
     reserved_spi[self->sck->periph_index - 1] = false;
     never_reset_spi[self->sck->periph_index - 1] = false;
 
@@ -271,14 +274,14 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
 }
 
 bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
-        uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
-    //This resets the SPI, so check before updating it redundantly
-    if (baudrate == self->baudrate && polarity== self->polarity
+    uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
+    // This resets the SPI, so check before updating it redundantly
+    if (baudrate == self->baudrate && polarity == self->polarity
         && phase == self->phase && bits == self->bits) {
         return true;
     }
 
-    //Deinit SPI
+    // Deinit SPI
     HAL_SPI_DeInit(&self->handle);
 
     self->handle.Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
@@ -286,10 +289,9 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
     self->handle.Init.CLKPhase = (phase) ? SPI_PHASE_2EDGE : SPI_PHASE_1EDGE;
 
     self->handle.Init.BaudRatePrescaler = stm32_baud_to_spi_div(baudrate, &self->prescaler,
-                                            get_busclock(self->handle.Instance));
+        get_busclock(self->handle.Instance));
 
-    if (HAL_SPI_Init(&self->handle) != HAL_OK)
-    {
+    if (HAL_SPI_Init(&self->handle) != HAL_OK) {
         mp_raise_ValueError(translate("SPI Re-initialization error"));
     }
 
@@ -303,7 +305,7 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
 bool common_hal_busio_spi_try_lock(busio_spi_obj_t *self) {
     bool grabbed_lock = false;
 
-    //Critical section code that may be required at some point.
+    // Critical section code that may be required at some point.
     // uint32_t store_primask = __get_PRIMASK();
     // __disable_irq();
     // __DMB();
@@ -328,7 +330,7 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
 }
 
 bool common_hal_busio_spi_write(busio_spi_obj_t *self,
-        const uint8_t *data, size_t len) {
+    const uint8_t *data, size_t len) {
     if (self->mosi == NULL) {
         mp_raise_ValueError(translate("No MOSI Pin"));
     }
@@ -337,7 +339,7 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self,
 }
 
 bool common_hal_busio_spi_read(busio_spi_obj_t *self,
-        uint8_t *data, size_t len, uint8_t write_value) {
+    uint8_t *data, size_t len, uint8_t write_value) {
     if (self->miso == NULL) {
         mp_raise_ValueError(translate("No MISO Pin"));
     }
@@ -352,26 +354,26 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self,
 }
 
 bool common_hal_busio_spi_transfer(busio_spi_obj_t *self,
-        const uint8_t *data_out, uint8_t *data_in, size_t len) {
+    const uint8_t *data_out, uint8_t *data_in, size_t len) {
     if (self->miso == NULL || self->mosi == NULL) {
         mp_raise_ValueError(translate("Missing MISO or MOSI Pin"));
     }
     HAL_StatusTypeDef result = HAL_SPI_TransmitReceive(&self->handle,
-        (uint8_t *) data_out, data_in, (uint16_t)len,HAL_MAX_DELAY);
+        (uint8_t *)data_out, data_in, (uint16_t)len,HAL_MAX_DELAY);
     return result == HAL_OK;
 }
 
-uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) {
-    //returns actual frequency
-    uint32_t result = HAL_RCC_GetPCLK2Freq()/self->prescaler;
+uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) {
+    // returns actual frequency
+    uint32_t result = HAL_RCC_GetPCLK2Freq() / self->prescaler;
     return result;
 }
 
-uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) {
+uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) {
     return self->phase;
 }
 
-uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) {
+uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) {
     return self->polarity;
 }
 
diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c
index b4794a31b..ecaee84d3 100644
--- a/ports/stm/common-hal/busio/UART.c
+++ b/ports/stm/common-hal/busio/UART.c
@@ -39,19 +39,19 @@
 
 #define ALL_UARTS 0xFFFF
 
-//arrays use 0 based numbering: UART1 is stored at index 0
+// arrays use 0 based numbering: UART1 is stored at index 0
 STATIC bool reserved_uart[MAX_UART];
 STATIC bool never_reset_uart[MAX_UART];
-int errflag; //Used to restart read halts
+int errflag; // Used to restart read halts
 
 STATIC void uart_clock_enable(uint16_t mask);
 STATIC void uart_clock_disable(uint16_t mask);
-STATIC void uart_assign_irq(busio_uart_obj_t* self, USART_TypeDef* USARTx);
+STATIC void uart_assign_irq(busio_uart_obj_t *self, USART_TypeDef *USARTx);
 
-STATIC USART_TypeDef * assign_uart_or_throw(busio_uart_obj_t* self, bool pin_eval,
-                                            int periph_index, bool uart_taken) {
+STATIC USART_TypeDef *assign_uart_or_throw(busio_uart_obj_t *self, bool pin_eval,
+    int periph_index, bool uart_taken) {
     if (pin_eval) {
-        //assign a root pointer pointer for IRQ
+        // assign a root pointer pointer for IRQ
         MP_STATE_PORT(cpy_uart_obj_all)[periph_index] = self;
         return mcu_uart_banks[periph_index];
     } else {
@@ -77,40 +77,40 @@ void uart_reset(void) {
 }
 
 void common_hal_busio_uart_construct(busio_uart_obj_t *self,
-    const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx,
-    const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts,
-    const mcu_pin_obj_t * rs485_dir, bool rs485_invert,
+    const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx,
+    const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts,
+    const mcu_pin_obj_t *rs485_dir, bool rs485_invert,
     uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop,
-    mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer,
+    mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer,
     bool sigint_enabled) {
 
-    //match pins to UART objects
-    USART_TypeDef * USARTx;
+    // match pins to UART objects
+    USART_TypeDef *USARTx;
 
     uint8_t tx_len = MP_ARRAY_SIZE(mcu_uart_tx_list);
     uint8_t rx_len = MP_ARRAY_SIZE(mcu_uart_rx_list);
     bool uart_taken = false;
-    uint8_t periph_index = 0; //origin 0 corrected
+    uint8_t periph_index = 0; // origin 0 corrected
 
     if ((rts != NULL) || (cts != NULL) || (rs485_dir != NULL) || (rs485_invert == true)) {
         mp_raise_ValueError(translate("RTS/CTS/RS485 Not yet supported on this device"));
     }
 
-    //Can have both pins, or either
+    // Can have both pins, or either
     if ((tx != NULL) && (rx != NULL)) {
-        //normal find loop if both pins exist
+        // normal find loop if both pins exist
         for (uint i = 0; i < tx_len; i++) {
             if (mcu_uart_tx_list[i].pin == tx) {
-                //rx
+                // rx
                 for (uint j = 0; j < rx_len; j++) {
                     if (mcu_uart_rx_list[j].pin == rx
                         && mcu_uart_rx_list[j].periph_index == mcu_uart_tx_list[i].periph_index) {
-                        //keep looking if the UART is taken, edge case
+                        // keep looking if the UART is taken, edge case
                         if (reserved_uart[mcu_uart_tx_list[i].periph_index - 1]) {
                             uart_taken = true;
                             continue;
                         }
-                        //store pins if not
+                        // store pins if not
                         self->tx = &mcu_uart_tx_list[i];
                         self->rx = &mcu_uart_rx_list[j];
                         break;
@@ -125,15 +125,15 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
         USARTx = assign_uart_or_throw(self, (self->tx != NULL && self->rx != NULL),
             periph_index, uart_taken);
     } else if (tx == NULL) {
-        //If there is no tx, run only rx
+        // If there is no tx, run only rx
         for (uint i = 0; i < rx_len; i++) {
             if (mcu_uart_rx_list[i].pin == rx) {
-                //keep looking if the UART is taken, edge case
+                // keep looking if the UART is taken, edge case
                 if (reserved_uart[mcu_uart_rx_list[i].periph_index - 1]) {
                     uart_taken = true;
                     continue;
                 }
-                //store pins if not
+                // store pins if not
                 self->rx = &mcu_uart_rx_list[i];
                 break;
             }
@@ -142,15 +142,15 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
         USARTx = assign_uart_or_throw(self, (self->rx != NULL),
             periph_index, uart_taken);
     } else if (rx == NULL) {
-        //If there is no rx, run only tx
+        // If there is no rx, run only tx
         for (uint i = 0; i < tx_len; i++) {
             if (mcu_uart_tx_list[i].pin == tx) {
-                //keep looking if the UART is taken, edge case
+                // keep looking if the UART is taken, edge case
                 if (reserved_uart[mcu_uart_tx_list[i].periph_index - 1]) {
                     uart_taken = true;
                     continue;
                 }
-                //store pins if not
+                // store pins if not
                 self->tx = &mcu_uart_tx_list[i];
                 break;
             }
@@ -159,22 +159,22 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
         USARTx = assign_uart_or_throw(self, (self->tx != NULL),
             periph_index, uart_taken);
     } else {
-        //both pins cannot be empty
+        // both pins cannot be empty
         mp_raise_ValueError(translate("Supply at least one UART pin"));
     }
 
-    //Other errors
-    if ( receiver_buffer_size == 0 ) {
+    // Other errors
+    if (receiver_buffer_size == 0) {
         mp_raise_ValueError(translate("Invalid buffer size"));
     }
-    if ( bits != 8 && bits != 9 ) {
+    if (bits != 8 && bits != 9) {
         mp_raise_ValueError(translate("Invalid word/bit length"));
     }
-    if ( USARTx == NULL) { //this can only be hit if the periph file is wrong
+    if (USARTx == NULL) {  // this can only be hit if the periph file is wrong
         mp_raise_ValueError(translate("Internal define error"));
     }
 
-    //GPIO Init
+    // GPIO Init
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     if (self->tx != NULL) {
         GPIO_InitStruct.Pin = pin_mask(tx->number);
@@ -193,7 +193,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
         HAL_GPIO_Init(pin_port(rx->port), &GPIO_InitStruct);
     }
 
-    //reserve uart and enable the peripheral
+    // reserve uart and enable the peripheral
     reserved_uart[periph_index] = true;
     uart_clock_enable(1 << (periph_index));
     uart_assign_irq(self, USARTx);
@@ -203,15 +203,14 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
     self->handle.Init.WordLength = (bits == 9) ? UART_WORDLENGTH_9B : UART_WORDLENGTH_8B;
     self->handle.Init.StopBits = (stop > 1) ? UART_STOPBITS_2 : UART_STOPBITS_1;
     self->handle.Init.Parity = (parity == BUSIO_UART_PARITY_ODD) ? UART_PARITY_ODD :
-                               (parity == BUSIO_UART_PARITY_EVEN) ? UART_PARITY_EVEN :
-                               UART_PARITY_NONE;
+        (parity == BUSIO_UART_PARITY_EVEN) ? UART_PARITY_EVEN :
+        UART_PARITY_NONE;
     self->handle.Init.Mode = (self->tx != NULL && self->rx != NULL) ? UART_MODE_TX_RX :
-                             (self->tx != NULL) ? UART_MODE_TX :
-                             UART_MODE_RX;
+        (self->tx != NULL) ? UART_MODE_TX :
+        UART_MODE_RX;
     self->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
     self->handle.Init.OverSampling = UART_OVERSAMPLING_16;
-    if (HAL_UART_Init(&self->handle) != HAL_OK)
-    {
+    if (HAL_UART_Init(&self->handle) != HAL_OK) {
         mp_raise_ValueError(translate("UART Init Error"));
 
     }
@@ -219,7 +218,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
     // Init buffer for rx and claim pins
     if (self->rx != NULL) {
         if (receiver_buffer != NULL) {
-            self->ringbuf = (ringbuf_t){ receiver_buffer, receiver_buffer_size };
+            self->ringbuf = (ringbuf_t) { receiver_buffer, receiver_buffer_size };
         } else {
             if (!ringbuf_alloc(&self->ringbuf, receiver_buffer_size, true)) {
                 mp_raise_ValueError(translate("UART Buffer allocation error"));
@@ -234,13 +233,13 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
     self->timeout_ms = timeout * 1000;
     self->sigint_enabled = sigint_enabled;
 
-    //start the interrupt series
+    // start the interrupt series
     if ((HAL_UART_GetState(&self->handle) & HAL_UART_STATE_BUSY_RX) == HAL_UART_STATE_BUSY_RX) {
         mp_raise_ValueError(translate("Could not start interrupt, RX busy"));
     }
 
-    //start the receive interrupt chain
-    HAL_NVIC_DisableIRQ(self->irq); //prevent handle lock contention
+    // start the receive interrupt chain
+    HAL_NVIC_DisableIRQ(self->irq); // prevent handle lock contention
     HAL_UART_Receive_IT(&self->handle, &self->rx_char, 1);
     HAL_NVIC_SetPriority(self->irq, UART_IRQPRI, UART_IRQSUB_PRI);
     HAL_NVIC_EnableIRQ(self->irq);
@@ -260,11 +259,13 @@ void common_hal_busio_uart_never_reset(busio_uart_obj_t *self) {
 }
 
 bool common_hal_busio_uart_deinited(busio_uart_obj_t *self) {
-    return (self->tx->pin == NULL && self->rx->pin == NULL);
+    return self->tx->pin == NULL && self->rx->pin == NULL;
 }
 
 void common_hal_busio_uart_deinit(busio_uart_obj_t *self) {
-    if (common_hal_busio_uart_deinited(self)) return;
+    if (common_hal_busio_uart_deinited(self)) {
+        return;
+    }
 
     for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_uart_banks); i++) {
         if (mcu_uart_banks[i] == self->handle.Instance) {
@@ -294,14 +295,14 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t
     uint64_t start_ticks = supervisor_ticks_ms64();
 
     // Wait for all bytes received or timeout, same as nrf
-    while ( (ringbuf_num_filled(&self->ringbuf) < len) && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms) ) {
+    while ((ringbuf_num_filled(&self->ringbuf) < len) && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms)) {
         RUN_BACKGROUND_TASKS;
-        //restart if it failed in the callback
+        // restart if it failed in the callback
         if (errflag != HAL_OK) {
             errflag = HAL_UART_Receive_IT(&self->handle, &self->rx_char, 1);
         }
         // Allow user to break out of a timeout with a KeyboardInterrupt.
-        if ( mp_hal_is_interrupted() ) {
+        if (mp_hal_is_interrupted()) {
             return 0;
         }
     }
@@ -324,10 +325,10 @@ size_t common_hal_busio_uart_write(busio_uart_obj_t *self, const uint8_t *data,
     if (self->tx == NULL) {
         mp_raise_ValueError(translate("No TX pin"));
     }
-    bool write_err = false; //write error shouldn't disable interrupts
+    bool write_err = false; // write error shouldn't disable interrupts
 
     HAL_NVIC_DisableIRQ(self->irq);
-    HAL_StatusTypeDef ret = HAL_UART_Transmit(&self->handle, (uint8_t*)data, len, HAL_MAX_DELAY);
+    HAL_StatusTypeDef ret = HAL_UART_Transmit(&self->handle, (uint8_t *)data, len, HAL_MAX_DELAY);
     if (ret != HAL_OK) {
         write_err = true;
     }
@@ -340,13 +341,12 @@ size_t common_hal_busio_uart_write(busio_uart_obj_t *self, const uint8_t *data,
     return len;
 }
 
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *handle)
-{
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *handle) {
     for (int i = 0; i < 7; i++) {
-        //get context pointer and cast it as struct pointer
-        busio_uart_obj_t * context = (busio_uart_obj_t*)MP_STATE_PORT(cpy_uart_obj_all)[i];
+        // get context pointer and cast it as struct pointer
+        busio_uart_obj_t *context = (busio_uart_obj_t *)MP_STATE_PORT(cpy_uart_obj_all)[i];
         if (handle == &context->handle) {
-            //check if transaction is ongoing
+            // check if transaction is ongoing
             if ((HAL_UART_GetState(handle) & HAL_UART_STATE_BUSY_RX) == HAL_UART_STATE_BUSY_RX) {
                 return;
             }
@@ -364,8 +364,7 @@ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *handle)
     }
 }
 
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle)
-{
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle) {
     if (__HAL_UART_GET_FLAG(UartHandle, UART_FLAG_PE) != RESET) {
         __HAL_UART_CLEAR_PEFLAG(UartHandle);
     } else if (__HAL_UART_GET_FLAG(UartHandle, UART_FLAG_FE) != RESET) {
@@ -375,9 +374,9 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle)
     } else if (__HAL_UART_GET_FLAG(UartHandle, UART_FLAG_ORE) != RESET) {
         __HAL_UART_CLEAR_OREFLAG(UartHandle);
     }
-    //restart serial read after an error
+    // restart serial read after an error
     for (int i = 0; i < 7; i++) {
-        busio_uart_obj_t * context = (busio_uart_obj_t *)MP_STATE_PORT(cpy_uart_obj_all)[i];
+        busio_uart_obj_t *context = (busio_uart_obj_t *)MP_STATE_PORT(cpy_uart_obj_all)[i];
         if (UartHandle == &context->handle) {
             HAL_UART_Receive_IT(UartHandle, &context->rx_char, 1);
             return;
@@ -391,10 +390,12 @@ uint32_t common_hal_busio_uart_get_baudrate(busio_uart_obj_t *self) {
 }
 
 void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrate) {
-    //Don't reset if it's the same value
-    if (baudrate == self->baudrate) return;
+    // Don't reset if it's the same value
+    if (baudrate == self->baudrate) {
+        return;
+    }
 
-    //Otherwise de-init and set new rate
+    // Otherwise de-init and set new rate
     if (HAL_UART_DeInit(&self->handle) != HAL_OK) {
         mp_raise_ValueError(translate("UART De-init error"));
     }
@@ -407,7 +408,7 @@ void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrat
 }
 
 mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) {
-    return (mp_float_t) (self->timeout_ms / 1000.0f);
+    return (mp_float_t)(self->timeout_ms / 1000.0f);
 }
 
 void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) {
@@ -430,8 +431,8 @@ bool common_hal_busio_uart_ready_to_tx(busio_uart_obj_t *self) {
 }
 
 STATIC void call_hal_irq(int uart_num) {
-    //Create casted context pointer
-    busio_uart_obj_t * context = (busio_uart_obj_t*)MP_STATE_PORT(cpy_uart_obj_all)[uart_num - 1];
+    // Create casted context pointer
+    busio_uart_obj_t *context = (busio_uart_obj_t *)MP_STATE_PORT(cpy_uart_obj_all)[uart_num - 1];
     if (context != NULL) {
         HAL_NVIC_ClearPendingIRQ(context->irq);
         HAL_UART_IRQHandler(&context->handle);
@@ -609,7 +610,7 @@ STATIC void uart_clock_disable(uint16_t mask) {
     #endif
 }
 
-STATIC void uart_assign_irq(busio_uart_obj_t *self, USART_TypeDef * USARTx) {
+STATIC void uart_assign_irq(busio_uart_obj_t *self, USART_TypeDef *USARTx) {
     #ifdef USART1
     if (USARTx == USART1) {
         self->irq = USART1_IRQn;
diff --git a/ports/stm/common-hal/canio/CAN.c b/ports/stm/common-hal/canio/CAN.c
index 52d5cad1f..091421fd1 100644
--- a/ports/stm/common-hal/canio/CAN.c
+++ b/ports/stm/common-hal/canio/CAN.c
@@ -38,7 +38,7 @@
 STATIC bool reserved_can[MP_ARRAY_SIZE(mcu_can_banks)];
 
 STATIC const mcu_periph_obj_t *find_pin_function(const mcu_periph_obj_t *table, size_t sz, const mcu_pin_obj_t *pin, int periph_index) {
-    for(size_t i = 0; i<sz; i++, table++) {
+    for (size_t i = 0; i < sz; i++, table++) {
         if (periph_index != -1 && periph_index != table->periph_index) {
             continue;
         }
@@ -50,9 +50,8 @@ STATIC const mcu_periph_obj_t *find_pin_function(const mcu_periph_obj_t *table,
 }
 
 
-void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent)
-{
-#define DIV_ROUND(a, b) (((a) + (b)/2) / (b))
+void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent) {
+#define DIV_ROUND(a, b) (((a) + (b) / 2) / (b))
 #define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
 
     const uint8_t can_tx_len = MP_ARRAY_SIZE(mcu_can_tx_list);
@@ -110,7 +109,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
 
     __HAL_RCC_CAN1_CLK_ENABLE();
 
-    if(hw == CAN2) {
+    if (hw == CAN2) {
         __HAL_RCC_CAN2_CLK_ENABLE();
         self->start_filter_bank = 14;
         self->end_filter_bank = 28;
@@ -126,9 +125,9 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
         .AutoBusOff = ENABLE,
         .Prescaler = divisor,
         .Mode = (loopback ? CAN_MODE_LOOPBACK : 0) | (silent ? CAN_MODE_SILENT_LOOPBACK : 0),
-        .SyncJumpWidth = (sjw-1) << CAN_BTR_SJW_Pos,
-        .TimeSeg1 = (tq_to_sample-2) << CAN_BTR_TS1_Pos,
-        .TimeSeg2 = (tq_after_sample-1) << CAN_BTR_TS2_Pos,
+        .SyncJumpWidth = (sjw - 1) << CAN_BTR_SJW_Pos,
+            .TimeSeg1 = (tq_to_sample - 2) << CAN_BTR_TS1_Pos,
+            .TimeSeg2 = (tq_after_sample - 1) << CAN_BTR_TS2_Pos,
     };
 
     self->periph_index = periph_index;
@@ -149,7 +148,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
 
     // Clear every filter enable bit for this can HW
     uint32_t fa1r = self->filter_hw->FA1R;
-    for (int i = self->start_filter_bank; i<self->end_filter_bank; i++) {
+    for (int i = self->start_filter_bank; i < self->end_filter_bank; i++) {
         fa1r &= ~(1 << i);
     }
     self->filter_hw->FA1R = fa1r;
@@ -160,23 +159,19 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
     reserved_can[periph_index] = true;
 }
 
-bool common_hal_canio_can_loopback_get(canio_can_obj_t *self)
-{
+bool common_hal_canio_can_loopback_get(canio_can_obj_t *self) {
     return self->loopback;
 }
 
-int common_hal_canio_can_baudrate_get(canio_can_obj_t *self)
-{
+int common_hal_canio_can_baudrate_get(canio_can_obj_t *self) {
     return self->baudrate;
 }
 
-int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self)
-{
+int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self) {
     return (self->handle.Instance->ESR & CAN_ESR_TEC) >> CAN_ESR_TEC_Pos;
 }
 
-int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self)
-{
+int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self) {
     return (self->handle.Instance->ESR & CAN_ESR_REC) >> CAN_ESR_REC_Pos;
 }
 
@@ -213,15 +208,14 @@ bool common_hal_canio_can_auto_restart_get(canio_can_obj_t *self) {
 }
 
 void common_hal_canio_can_auto_restart_set(canio_can_obj_t *self, bool value) {
-    if(value) {
+    if (value) {
         SET_BIT(self->handle.Instance->MCR, CAN_MCR_ABOM);
     } else {
         CLEAR_BIT(self->handle.Instance->MCR, CAN_MCR_ABOM);
     }
 }
 
-void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in)
-{
+void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in) {
     canio_message_obj_t *message = message_in;
     uint32_t mailbox;
     bool rtr = message->base.type == &canio_remote_transmission_request_type;
@@ -278,8 +272,7 @@ void common_hal_canio_can_check_for_deinit(canio_can_obj_t *self) {
     }
 }
 
-void common_hal_canio_can_deinit(canio_can_obj_t *self)
-{
+void common_hal_canio_can_deinit(canio_can_obj_t *self) {
     if (self->handle.Instance) {
         SET_BIT(self->handle.Instance->MCR, CAN_MCR_RESET);
         while (READ_BIT(self->handle.Instance->MCR, CAN_MCR_RESET)) {
@@ -290,7 +283,7 @@ void common_hal_canio_can_deinit(canio_can_obj_t *self)
 }
 
 void common_hal_canio_reset(void) {
-    for (size_t i=0; i<MP_ARRAY_SIZE(mcu_can_banks); i++) {
+    for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_can_banks); i++) {
         SET_BIT(mcu_can_banks[i]->MCR, CAN_MCR_RESET);
         reserved_can[i] = 0;
     }
diff --git a/ports/stm/common-hal/canio/CAN.h b/ports/stm/common-hal/canio/CAN.h
index 3157d0a03..16bb8fd1e 100644
--- a/ports/stm/common-hal/canio/CAN.h
+++ b/ports/stm/common-hal/canio/CAN.h
@@ -45,12 +45,12 @@ typedef struct canio_can_obj {
     int baudrate;
     const mcu_pin_obj_t *rx_pin;
     const mcu_pin_obj_t *tx_pin;
-    bool loopback:1;
-    bool silent:1;
-    bool auto_restart:1;
-    bool fifo0_in_use:1;
-    bool fifo1_in_use:1;
-    uint8_t periph_index:2;
+    bool loopback : 1;
+    bool silent : 1;
+    bool auto_restart : 1;
+    bool fifo0_in_use : 1;
+    bool fifo1_in_use : 1;
+    uint8_t periph_index : 2;
     uint8_t cancel_mailbox;
     uint8_t start_filter_bank;
     uint8_t end_filter_bank;
diff --git a/ports/stm/common-hal/canio/Listener.c b/ports/stm/common-hal/canio/Listener.c
index 09456d39d..23634eba6 100644
--- a/ports/stm/common-hal/canio/Listener.c
+++ b/ports/stm/common-hal/canio/Listener.c
@@ -46,7 +46,7 @@ STATIC void prevent_filter_change(canio_can_obj_t *can) {
 }
 
 STATIC bool filter_in_use(canio_can_obj_t *can, int idx) {
-    return can->filter_hw->FA1R & (1<<idx);
+    return can->filter_hw->FA1R & (1 << idx);
 }
 
 // One filter bank can hold:
@@ -62,19 +62,19 @@ STATIC size_t num_filters_needed(size_t nmatch, canio_match_obj_t **matches) {
     }
     size_t num_extended_mask = 0;
     size_t num_standard_mask = 1;
-    for(size_t i=0; i<nmatch; i++) {
+    for (size_t i = 0; i < nmatch; i++) {
         if (matches[i]->extended) {
             num_extended_mask += 1;
         } else {
             num_standard_mask += 1;
         }
     }
-    return num_extended_mask + num_standard_mask/2;
+    return num_extended_mask + num_standard_mask / 2;
 }
 
 STATIC size_t num_filters_available(canio_can_obj_t *can) {
     size_t available = 0;
-    for(size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) {
+    for (size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) {
         if (!filter_in_use(can, i)) {
             available++;
         }
@@ -87,9 +87,9 @@ STATIC void clear_filters(canio_listener_obj_t *self) {
 
     allow_filter_change(can);
     uint32_t fa1r = can->filter_hw->FA1R;
-    for(size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) {
+    for (size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) {
         if (((can->filter_hw->FFA1R >> i) & 1) == self->fifo_idx) {
-            fa1r &= ~(1<<i);
+            fa1r &= ~(1 << i);
         }
     }
     can->filter_hw->FA1R = fa1r;
@@ -98,8 +98,8 @@ STATIC void clear_filters(canio_listener_obj_t *self) {
 
 STATIC int next_filter(canio_can_obj_t *can) {
     uint32_t fa1r = can->filter_hw->FA1R;
-    for(size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) {
-        if (!(fa1r & (1<<i))) {
+    for (size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) {
+        if (!(fa1r & (1 << i))) {
             return i;
         }
     }
@@ -109,8 +109,8 @@ STATIC int next_filter(canio_can_obj_t *can) {
 
 // IDE = "extended ID" flag of packet header.  We always add this bit to the
 // mask because a match is always for just one kind of address length
-#define FILTER16_IDE (1<<3)
-#define FILTER32_IDE (1<<2)
+#define FILTER16_IDE (1 << 3)
+#define FILTER32_IDE (1 << 2)
 
 STATIC void install_standard_filter(canio_listener_obj_t *self, canio_match_obj_t *match1, canio_match_obj_t *match2) {
     int bank = next_filter(self->can);
@@ -201,8 +201,8 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **
         install_all_match_filter(self);
     } else {
         canio_match_obj_t *first_match = NULL;
-        for(size_t i = 0; i<nmatch; i++) {
-            if(matches[i]->extended) {
+        for (size_t i = 0; i < nmatch; i++) {
+            if (matches[i]->extended) {
                 install_extended_filter(self, matches[i]);
             } else {
                 if (first_match) {
diff --git a/ports/stm/common-hal/digitalio/DigitalInOut.c b/ports/stm/common-hal/digitalio/DigitalInOut.c
index a676aeb15..fbefdb79a 100644
--- a/ports/stm/common-hal/digitalio/DigitalInOut.c
+++ b/ports/stm/common-hal/digitalio/DigitalInOut.c
@@ -40,12 +40,12 @@
 #endif
 
 void common_hal_digitalio_digitalinout_never_reset(
-        digitalio_digitalinout_obj_t *self) {
+    digitalio_digitalinout_obj_t *self) {
     never_reset_pin_number(self->pin->port, self->pin->number);
 }
 
 digitalinout_result_t common_hal_digitalio_digitalinout_construct(
-        digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) {
+    digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) {
 
     common_hal_mcu_pin_claim(pin);
     self->pin = pin;
@@ -74,7 +74,7 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self
 }
 
 void common_hal_digitalio_digitalinout_switch_to_input(
-        digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) {
+    digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) {
 
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     GPIO_InitStruct.Pin = pin_mask(self->pin->number);
@@ -87,8 +87,8 @@ void common_hal_digitalio_digitalinout_switch_to_input(
 }
 
 digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output(
-        digitalio_digitalinout_obj_t *self, bool value,
-        digitalio_drive_mode_t drive_mode) {
+    digitalio_digitalinout_obj_t *self, bool value,
+    digitalio_drive_mode_t drive_mode) {
 
     common_hal_digitalio_digitalinout_set_drive_mode(self, drive_mode);
     common_hal_digitalio_digitalinout_set_value(self, value);
@@ -96,27 +96,27 @@ digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output(
 }
 
 digitalio_direction_t common_hal_digitalio_digitalinout_get_direction(
-        digitalio_digitalinout_obj_t *self) {
+    digitalio_digitalinout_obj_t *self) {
 
     return (LL_GPIO_GetPinMode(pin_port(self->pin->port), pin_mask(self->pin->number))
         == LL_GPIO_MODE_INPUT) ? DIRECTION_INPUT : DIRECTION_OUTPUT;
 }
 
 void common_hal_digitalio_digitalinout_set_value(
-        digitalio_digitalinout_obj_t *self, bool value) {
+    digitalio_digitalinout_obj_t *self, bool value) {
     HAL_GPIO_WritePin(pin_port(self->pin->port), pin_mask(self->pin->number), value);
 }
 
 bool common_hal_digitalio_digitalinout_get_value(
-        digitalio_digitalinout_obj_t *self) {
+    digitalio_digitalinout_obj_t *self) {
     return (LL_GPIO_GetPinMode(pin_port(self->pin->port), pin_mask(self->pin->number)) == LL_GPIO_MODE_INPUT)
         ? HAL_GPIO_ReadPin(pin_port(self->pin->port), pin_mask(self->pin->number))
         : LL_GPIO_IsOutputPinSet(pin_port(self->pin->port), pin_mask(self->pin->number));
 }
 
 digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode(
-        digitalio_digitalinout_obj_t *self,
-        digitalio_drive_mode_t drive_mode) {
+    digitalio_digitalinout_obj_t *self,
+    digitalio_drive_mode_t drive_mode) {
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     GPIO_InitStruct.Pin = pin_mask(self->pin->number);
     GPIO_InitStruct.Mode = (drive_mode == DRIVE_MODE_OPEN_DRAIN ?
@@ -128,14 +128,14 @@ digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode(
 }
 
 digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode(
-        digitalio_digitalinout_obj_t *self) {
+    digitalio_digitalinout_obj_t *self) {
 
     return LL_GPIO_GetPinOutputType(pin_port(self->pin->port), pin_mask(self->pin->number))
-        == LL_GPIO_OUTPUT_OPENDRAIN ? DRIVE_MODE_OPEN_DRAIN : DRIVE_MODE_PUSH_PULL;
+           == LL_GPIO_OUTPUT_OPENDRAIN ? DRIVE_MODE_OPEN_DRAIN : DRIVE_MODE_PUSH_PULL;
 }
 
 void common_hal_digitalio_digitalinout_set_pull(
-        digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) {
+    digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) {
 
     switch (pull) {
         case PULL_UP:
@@ -153,7 +153,7 @@ void common_hal_digitalio_digitalinout_set_pull(
 }
 
 digitalio_pull_t common_hal_digitalio_digitalinout_get_pull(
-        digitalio_digitalinout_obj_t *self) {
+    digitalio_digitalinout_obj_t *self) {
 
     switch (LL_GPIO_GetPinPull(pin_port(self->pin->port), pin_mask(self->pin->number))) {
         case LL_GPIO_PULL_UP:
diff --git a/ports/stm/common-hal/displayio/ParallelBus.c b/ports/stm/common-hal/displayio/ParallelBus.c
index fd07d38af..4788deb9b 100644
--- a/ports/stm/common-hal/displayio/ParallelBus.c
+++ b/ports/stm/common-hal/displayio/ParallelBus.c
@@ -33,19 +33,19 @@
 #include "shared-bindings/digitalio/DigitalInOut.h"
 #include "shared-bindings/microcontroller/__init__.h"
 
-void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* self,
-    const mcu_pin_obj_t* data0, const mcu_pin_obj_t* command, const mcu_pin_obj_t* chip_select,
-    const mcu_pin_obj_t* write, const mcu_pin_obj_t* read, const mcu_pin_obj_t* reset) {
+void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t *self,
+    const mcu_pin_obj_t *data0, const mcu_pin_obj_t *command, const mcu_pin_obj_t *chip_select,
+    const mcu_pin_obj_t *write, const mcu_pin_obj_t *read, const mcu_pin_obj_t *reset) {
 
     mp_raise_NotImplementedError(translate("ParallelBus not yet supported"));
 }
 
-void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) {
+void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t *self) {
 
 }
 
 bool common_hal_displayio_parallelbus_reset(mp_obj_t obj) {
-	return false;
+    return false;
 }
 
 bool common_hal_displayio_parallelbus_bus_free(mp_obj_t obj) {
diff --git a/ports/stm/common-hal/microcontroller/Pin.c b/ports/stm/common-hal/microcontroller/Pin.c
index 37c202d86..80cb9defc 100644
--- a/ports/stm/common-hal/microcontroller/Pin.c
+++ b/ports/stm/common-hal/microcontroller/Pin.c
@@ -41,15 +41,15 @@ bool apa102_mosi_in_use;
 #endif
 
 #if defined(TFBGA216)
-    GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK};
+GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK};
 #elif defined(LQFP144)
-    GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG};
+GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG};
 #elif defined(LQFP100_f4) || (LQFP100_x7)
-    GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE};
+GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE};
 #elif defined(LQFP64)
-    GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC, GPIOD};
+GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD};
 #elif defined(UFQFPN48)
-    GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC};
+GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC};
 #endif
 
 
@@ -78,7 +78,7 @@ void reset_all_pins(void) {
 
 // Mark pin as free and return it to a quiescent state.
 void reset_pin_number(uint8_t pin_port, uint8_t pin_number) {
-    if ( pin_number == NO_PIN ) {
+    if (pin_number == NO_PIN) {
         return;
     }
 
@@ -86,9 +86,9 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number) {
         return;
     }
     // Clear claimed bit & reset
-    claimed_pins[pin_port] &= ~(1<<pin_number);
-    never_reset_pins[pin_port] &= ~(1<<pin_number);
-    HAL_GPIO_DeInit(ports[pin_port], 1<<pin_number);
+    claimed_pins[pin_port] &= ~(1 << pin_number);
+    never_reset_pins[pin_port] &= ~(1 << pin_number);
+    HAL_GPIO_DeInit(ports[pin_port], 1 << pin_number);
 
     #ifdef MICROPY_HW_NEOPIXEL
     if (pin_port == MICROPY_HW_NEOPIXEL->port && pin_number == MICROPY_HW_NEOPIXEL->number) {
@@ -101,8 +101,7 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number) {
     if (
         (pin_port == MICROPY_HW_APA102_MOSI->port && pin_number == MICROPY_HW_APA102_MOSI->number)
         || (pin_port == MICROPY_HW_APA102_SCK->port && pin_number == MICROPY_HW_APA102_MOSI->number)
-    )
-    {
+        ) {
         apa102_mosi_in_use = false;
         apa102_sck_in_use = false;
         rgb_led_status_init();
@@ -112,19 +111,19 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number) {
 }
 
 void never_reset_pin_number(uint8_t pin_port, uint8_t pin_number) {
-    if ( pin_number == NO_PIN ) {
+    if (pin_number == NO_PIN) {
         return;
     }
-    never_reset_pins[pin_port] |= 1<<pin_number;
+    never_reset_pins[pin_port] |= 1 << pin_number;
     // Make sure never reset pins are also always claimed
-    claimed_pins[pin_port] |= 1<<pin_number;
+    claimed_pins[pin_port] |= 1 << pin_number;
 }
 
-void common_hal_never_reset_pin(const mcu_pin_obj_t* pin) {
+void common_hal_never_reset_pin(const mcu_pin_obj_t *pin) {
     never_reset_pin_number(pin->port, pin->number);
 }
 
-void common_hal_reset_pin(const mcu_pin_obj_t* pin) {
+void common_hal_reset_pin(const mcu_pin_obj_t *pin) {
     if (pin == NULL) {
         return;
     }
@@ -133,11 +132,11 @@ void common_hal_reset_pin(const mcu_pin_obj_t* pin) {
 
 void claim_pin(uint8_t pin_port, uint8_t pin_number) {
     // Set bit in claimed_pins bitmask.
-    claimed_pins[pin_port] |= 1<<pin_number;
+    claimed_pins[pin_port] |= 1 << pin_number;
 }
 
 bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number) {
-    return !(claimed_pins[pin_port] & 1<<pin_number);
+    return !(claimed_pins[pin_port] & 1 << pin_number);
 }
 
 bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) {
@@ -147,12 +146,10 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) {
     }
     #endif
     #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)
-    if (pin == MICROPY_HW_APA102_MOSI)
-    {
+    if (pin == MICROPY_HW_APA102_MOSI) {
         return !apa102_mosi_in_use;
     }
-    if (pin == MICROPY_HW_APA102_SCK)
-    {
+    if (pin == MICROPY_HW_APA102_SCK) {
         return !apa102_sck_in_use;
     }
     #endif
@@ -160,19 +157,19 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) {
     return pin_number_is_free(pin->port, pin->number);
 }
 
-GPIO_TypeDef * pin_port(uint8_t pin_port) {
+GPIO_TypeDef *pin_port(uint8_t pin_port) {
     return ports[pin_port];
 }
 
 uint16_t pin_mask(uint8_t pin_number) {
-    return 1<<pin_number;
+    return 1 << pin_number;
 }
 
-uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t* pin) {
+uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t *pin) {
     return pin->port * 16 + pin->number;
 }
 
-void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) {
+void common_hal_mcu_pin_claim(const mcu_pin_obj_t *pin) {
     claim_pin(pin->port, pin->number);
     #ifdef MICROPY_HW_NEOPIXEL
     if (pin == MICROPY_HW_NEOPIXEL) {
@@ -180,12 +177,10 @@ void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) {
     }
     #endif
     #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)
-    if (pin == MICROPY_HW_APA102_MOSI)
-    {
+    if (pin == MICROPY_HW_APA102_MOSI) {
         apa102_mosi_in_use = true;
     }
-    if (pin == MICROPY_HW_APA102_SCK)
-    {
+    if (pin == MICROPY_HW_APA102_SCK) {
         apa102_sck_in_use = true;
     }
     #endif
diff --git a/ports/stm/common-hal/microcontroller/Pin.h b/ports/stm/common-hal/microcontroller/Pin.h
index f461d3813..4a3397942 100644
--- a/ports/stm/common-hal/microcontroller/Pin.h
+++ b/ports/stm/common-hal/microcontroller/Pin.h
@@ -46,7 +46,7 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number);
 void claim_pin(uint8_t pin_port, uint8_t pin_number);
 bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number);
 void never_reset_pin_number(uint8_t pin_port, uint8_t pin_number);
-GPIO_TypeDef * pin_port(uint8_t pin_port);
+GPIO_TypeDef *pin_port(uint8_t pin_port);
 uint16_t pin_mask(uint8_t pin_number);
 
 #endif // MICROPY_INCLUDED_STM32_COMMON_HAL_MICROCONTROLLER_PIN_H
diff --git a/ports/stm/common-hal/microcontroller/Processor.c b/ports/stm/common-hal/microcontroller/Processor.c
index dd04c56dc..b33d96e73 100644
--- a/ports/stm/common-hal/microcontroller/Processor.c
+++ b/ports/stm/common-hal/microcontroller/Processor.c
@@ -37,10 +37,10 @@
 
 #define STM32_UUID ((uint32_t *)0x1FFF7A10)
 
-//Factory calibration locations
+// Factory calibration locations
 #define ADC_CAL_ADDRESS         (0x1fff7a2a)
-#define ADC_CAL1                ((uint16_t*)(ADC_CAL_ADDRESS + 2))
-#define ADC_CAL2                ((uint16_t*)(ADC_CAL_ADDRESS + 4))
+#define ADC_CAL1                ((uint16_t *)(ADC_CAL_ADDRESS + 2))
+#define ADC_CAL2                ((uint16_t *)(ADC_CAL_ADDRESS + 4))
 #define VREFIN_CAL ((uint16_t *)ADC_CAL_ADDRESS)
 
 // correction factor for reference value
@@ -68,7 +68,7 @@ float common_hal_mcu_processor_get_temperature(void) {
     #if CPY_STM32F4
     __HAL_RCC_ADC1_CLK_ENABLE();
 
-    //HAL Implementation
+    // HAL Implementation
     ADC_HandleTypeDef AdcHandle;
     ADC_ChannelConfTypeDef sConfig;
     set_adc_params(&AdcHandle);
@@ -77,7 +77,7 @@ float common_hal_mcu_processor_get_temperature(void) {
     ADC->CCR |= ADC_CCR_TSVREFE;
     ADC->CCR &= ~ADC_CCR_VBATE; // If this somehow got turned on, it'll return bad values.
 
-    sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; //either 16 or 18, depending on chip
+    sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; // either 16 or 18, depending on chip
     sConfig.Rank = 1;
     sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; // Temp sensor likes 10us minimum
     HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
@@ -89,7 +89,7 @@ float common_hal_mcu_processor_get_temperature(void) {
     uint32_t value = (uint32_t)HAL_ADC_GetValue(&AdcHandle);
     HAL_ADC_Stop(&AdcHandle);
 
-    //There's no F4 specific appnote for this but it works the same as the L1 in AN3964
+    // There's no F4 specific appnote for this but it works the same as the L1 in AN3964
     float core_temp_avg_slope = (*ADC_CAL2 - *ADC_CAL1) / 80.0;
     return (((float)value * adc_refcor - *ADC_CAL1) / core_temp_avg_slope) + 30.0f;
     #else
@@ -101,7 +101,7 @@ float common_hal_mcu_processor_get_voltage(void) {
     #if CPY_STM32F4
     __HAL_RCC_ADC1_CLK_ENABLE();
 
-    //HAL Implementation
+    // HAL Implementation
     ADC_HandleTypeDef AdcHandle;
     ADC_ChannelConfTypeDef sConfig;
     set_adc_params(&AdcHandle);
@@ -121,7 +121,7 @@ float common_hal_mcu_processor_get_voltage(void) {
     uint32_t value = (uint32_t)HAL_ADC_GetValue(&AdcHandle);
     HAL_ADC_Stop(&AdcHandle);
 
-    //This value could be used to actively correct ADC values.
+    // This value could be used to actively correct ADC values.
     adc_refcor = ((float)(*VREFIN_CAL)) / ((float)value);
 
     return adc_refcor * 3.3f;
@@ -136,8 +136,8 @@ uint32_t common_hal_mcu_processor_get_frequency(void) {
 
 void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) {
     #if CPY_STM32F4
-    for (int i=0; i<3; i++) {
-        ((uint32_t*) raw_id)[i] = STM32_UUID[i];
+    for (int i = 0; i < 3; i++) {
+        ((uint32_t *)raw_id)[i] = STM32_UUID[i];
     }
     #endif
 }
diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c
index a827399cc..28e06c913 100644
--- a/ports/stm/common-hal/microcontroller/__init__.c
+++ b/ports/stm/common-hal/microcontroller/__init__.c
@@ -41,11 +41,12 @@
 #include "supervisor/shared/safe_mode.h"
 
 void common_hal_mcu_delay_us(uint32_t delay) {
-    uint32_t ticks_per_us = HAL_RCC_GetSysClockFreq()/1000000;
+    uint32_t ticks_per_us = HAL_RCC_GetSysClockFreq() / 1000000;
     delay *= ticks_per_us;
     SysTick->LOAD = delay;
     SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-    while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {}
+    while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {
+    }
     SysTick->CTRL = 0;
 }
 
@@ -61,7 +62,7 @@ void common_hal_mcu_enable_interrupts(void) {
     if (nesting_count == 0) {
         // This is very very bad because it means there was mismatched disable/enables so we
         // "HardFault".
-        asm("bkpt");
+        asm ("bkpt");
     }
     nesting_count--;
     if (nesting_count > 0) {
@@ -72,12 +73,13 @@ void common_hal_mcu_enable_interrupts(void) {
 }
 
 void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) {
-  if(runmode == RUNMODE_SAFE_MODE)
-    safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE);
+    if (runmode == RUNMODE_SAFE_MODE) {
+        safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE);
+    }
 }
 
 void common_hal_mcu_reset(void) {
-    filesystem_flush(); //TODO: implement as part of flash improvements
+    filesystem_flush(); // TODO: implement as part of flash improvements
     NVIC_SystemReset();
 }
 
@@ -96,6 +98,6 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = {
         .type = &nvm_bytearray_type,
     },
     .len = NVM_BYTEARRAY_BUFFER_SIZE,
-    .start_address = (uint8_t*) (CIRCUITPY_INTERNAL_NVM_START_ADDR)
+    .start_address = (uint8_t *)(CIRCUITPY_INTERNAL_NVM_START_ADDR)
 };
 #endif
diff --git a/ports/stm/common-hal/neopixel_write/__init__.c b/ports/stm/common-hal/neopixel_write/__init__.c
index c8852403b..f5dabe7f9 100644
--- a/ports/stm/common-hal/neopixel_write/__init__.c
+++ b/ports/stm/common-hal/neopixel_write/__init__.c
@@ -36,7 +36,7 @@
 
 uint64_t next_start_raw_ticks = 0;
 
-//sysclock divisors
+// sysclock divisors
 #define MAGIC_800_INT  900000  // ~1.11 us  -> 1.2  field
 #define MAGIC_800_T0H  2800000  // ~0.36 us -> 0.44 field
 #define MAGIC_800_T1H  1350000  // ~0.74 us -> 0.84 field
@@ -44,25 +44,26 @@ uint64_t next_start_raw_ticks = 0;
 #pragma GCC push_options
 #pragma GCC optimize ("Os")
 
-void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels,
-                                uint32_t numBytes) {
+void common_hal_neopixel_write(const digitalio_digitalinout_obj_t *digitalinout, uint8_t *pixels,
+    uint32_t numBytes) {
     uint8_t *p = pixels, *end = p + numBytes, pix = *p++, mask = 0x80;
     uint32_t start = 0;
     uint32_t cyc = 0;
 
-    //assumes 800_000Hz frequency
-    //Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us
-    //TODO: try to get dynamic weighting working again
+    // assumes 800_000Hz frequency
+    // Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us
+    // TODO: try to get dynamic weighting working again
     uint32_t sys_freq = HAL_RCC_GetSysClockFreq();
-    uint32_t interval = sys_freq/MAGIC_800_INT;
-    uint32_t t0 = (sys_freq/MAGIC_800_T0H);
-    uint32_t t1 = (sys_freq/MAGIC_800_T1H);
+    uint32_t interval = sys_freq / MAGIC_800_INT;
+    uint32_t t0 = (sys_freq / MAGIC_800_T0H);
+    uint32_t t1 = (sys_freq / MAGIC_800_T1H);
 
     // Wait to make sure we don't append onto the last transmission. This should only be a tick or
     // two.
-    while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {}
+    while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {
+    }
 
-    GPIO_TypeDef * p_port = pin_port(digitalinout->pin->port);
+    GPIO_TypeDef *p_port = pin_port(digitalinout->pin->port);
     uint32_t p_mask = pin_mask(digitalinout->pin->number);
 
     __disable_irq();
@@ -71,16 +72,22 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout
     DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
     DWT->CYCCNT = 0;
 
-    for(;;) {
+    for (;;) {
         cyc = (pix & mask) ? t1 : t0;
         start = DWT->CYCCNT;
         LL_GPIO_SetOutputPin(p_port, p_mask);
-        while((DWT->CYCCNT - start) < cyc);
+        while ((DWT->CYCCNT - start) < cyc) {
+            ;
+        }
         LL_GPIO_ResetOutputPin(p_port, p_mask);
-        while((DWT->CYCCNT - start) < interval);
-        if(!(mask >>= 1)) {
-            if(p >= end) break;
-            pix       = *p++;
+        while ((DWT->CYCCNT - start) < interval) {
+            ;
+        }
+        if (!(mask >>= 1)) {
+            if (p >= end) {
+                break;
+            }
+            pix = *p++;
             mask = 0x80;
         }
     }
diff --git a/ports/stm/common-hal/nvm/ByteArray.c b/ports/stm/common-hal/nvm/ByteArray.c
index b7a1ff035..6ef2eb392 100644
--- a/ports/stm/common-hal/nvm/ByteArray.c
+++ b/ports/stm/common-hal/nvm/ByteArray.c
@@ -38,7 +38,7 @@ uint32_t common_hal_nvm_bytearray_get_length(nvm_bytearray_obj_t *self) {
 }
 
 bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self,
-        uint32_t start_index, uint8_t* values, uint32_t len) {
+    uint32_t start_index, uint8_t *values, uint32_t len) {
     // Copy flash to buffer
     uint8_t buffer[self->len];
     memcpy(buffer, self->start_address, self->len);
@@ -48,7 +48,7 @@ bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self,
 
     // Erase flash sector
     HAL_FLASH_Unlock();
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR );
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
     FLASH_Erase_Sector(CIRCUITPY_INTERNAL_NVM_SECTOR, VOLTAGE_RANGE_3);
 
     // Write bytes to flash
@@ -68,6 +68,6 @@ bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self,
 
 // NVM memory is memory mapped so reading it is easy.
 void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t *self,
-    uint32_t start_index, uint32_t len, uint8_t* values) {
+    uint32_t start_index, uint32_t len, uint8_t *values) {
     memcpy(values, self->start_address + start_index, len);
 }
diff --git a/ports/stm/common-hal/nvm/ByteArray.h b/ports/stm/common-hal/nvm/ByteArray.h
index b6ea36de3..b88d91976 100644
--- a/ports/stm/common-hal/nvm/ByteArray.h
+++ b/ports/stm/common-hal/nvm/ByteArray.h
@@ -38,7 +38,7 @@
 
 typedef struct {
     mp_obj_base_t base;
-    uint8_t* start_address;
+    uint8_t *start_address;
     uint32_t len;
 } nvm_bytearray_obj_t;
 
diff --git a/ports/stm/common-hal/os/__init__.c b/ports/stm/common-hal/os/__init__.c
index 8da7243a3..66dfd9f76 100644
--- a/ports/stm/common-hal/os/__init__.c
+++ b/ports/stm/common-hal/os/__init__.c
@@ -55,7 +55,7 @@ STATIC MP_DEFINE_ATTRTUPLE(
     (mp_obj_t)&os_uname_info_release_obj,
     (mp_obj_t)&os_uname_info_version_obj,
     (mp_obj_t)&os_uname_info_machine_obj
-);
+    );
 
 mp_obj_t common_hal_os_uname(void) {
     return (mp_obj_t)&os_uname_info_obj;
@@ -65,19 +65,23 @@ mp_obj_t common_hal_os_uname(void) {
 
 bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) {
     #if (HAS_TRNG)
-    //init the RNG
+    // init the RNG
     __HAL_RCC_RNG_CLK_ENABLE();
     RNG_HandleTypeDef handle;
     handle.Instance = RNG;
-    if (HAL_RNG_Init(&handle) != HAL_OK) mp_raise_ValueError(translate("RNG Init Error"));
+    if (HAL_RNG_Init(&handle) != HAL_OK) {
+        mp_raise_ValueError(translate("RNG Init Error"));
+    }
 
-    //Assign bytes
+    // Assign bytes
     uint32_t i = 0;
     while (i < length) {
         uint32_t new_random;
         uint32_t start = HAL_GetTick();
-        //the HAL function has a timeout, but it isn't long enough, and isn't adjustable
-        while(!(__HAL_RNG_GET_FLAG(&handle,RNG_FLAG_DRDY)) && ((HAL_GetTick() - start) < RNG_TIMEOUT));
+        // the HAL function has a timeout, but it isn't long enough, and isn't adjustable
+        while (!(__HAL_RNG_GET_FLAG(&handle,RNG_FLAG_DRDY)) && ((HAL_GetTick() - start) < RNG_TIMEOUT)) {
+            ;
+        }
         if (HAL_RNG_GenerateRandomNumber(&handle, &new_random) != HAL_OK) {
             mp_raise_ValueError(translate("Random number generation error"));
         }
@@ -88,8 +92,10 @@ bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) {
         }
     }
 
-    //shut down the peripheral
-    if (HAL_RNG_DeInit(&handle) != HAL_OK) mp_raise_ValueError(translate("RNG DeInit Error"));
+    // shut down the peripheral
+    if (HAL_RNG_DeInit(&handle) != HAL_OK) {
+        mp_raise_ValueError(translate("RNG DeInit Error"));
+    }
     __HAL_RCC_RNG_CLK_DISABLE();
 
     return true;
diff --git a/ports/stm/common-hal/pulseio/PulseIn.c b/ports/stm/common-hal/pulseio/PulseIn.c
index 015ee8536..ece02f66a 100644
--- a/ports/stm/common-hal/pulseio/PulseIn.c
+++ b/ports/stm/common-hal/pulseio/PulseIn.c
@@ -38,21 +38,18 @@
 #include STM32_HAL_H
 
 #define STM32_GPIO_PORT_SIZE 16
-static pulseio_pulsein_obj_t* _objs[STM32_GPIO_PORT_SIZE];
+static pulseio_pulsein_obj_t *_objs[STM32_GPIO_PORT_SIZE];
 
 STATIC TIM_HandleTypeDef tim_handle;
 static uint32_t overflow_count = 0;
 STATIC uint8_t refcount = 0;
 
-static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t* self, uint8_t num);
+static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t *self, uint8_t num);
 
-void pulsein_timer_event_handler(void)
-{
+void pulsein_timer_event_handler(void) {
     // Detect TIM Update event
-    if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET)
-    {
-        if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET)
-        {
+    if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET) {
+        if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET) {
             __HAL_TIM_CLEAR_IT(&tim_handle, TIM_IT_UPDATE);
             overflow_count++;
         }
@@ -67,13 +64,15 @@ static void pulsein_exti_event_handler(uint8_t num) {
     // Interrupt register must be cleared manually
     EXTI->PR = 1 << num;
 
-    pulseio_pulsein_obj_t* self = _objs[num];
-    if ( !self ) return;
+    pulseio_pulsein_obj_t *self = _objs[num];
+    if (!self) {
+        return;
+    }
 
     if (self->first_edge) {
         // first pulse is opposite state from idle
         bool state = HAL_GPIO_ReadPin(pin_port(self->pin->port), pin_mask(self->pin->number));
-        if ( self->idle_state != state ) {
+        if (self->idle_state != state) {
             self->first_edge = false;
         }
     } else {
@@ -109,20 +108,20 @@ void pulsein_reset(void) {
     refcount = 0;
 }
 
-void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu_pin_obj_t* pin,
-                                             uint16_t maxlen, bool idle_state) {
+void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t *self, const mcu_pin_obj_t *pin,
+    uint16_t maxlen, bool idle_state) {
     // STM32 has one shared EXTI for each pin number, 0-15
     uint8_t p_num = pin->number;
-    if(_objs[p_num]) {
+    if (_objs[p_num]) {
         mp_raise_ValueError(translate("Pin number already reserved by EXTI"));
     }
     _objs[p_num] = self;
 
     // Allocate pulse buffer
-    self->buffer = (uint16_t *) m_malloc(maxlen * sizeof(uint16_t), false);
+    self->buffer = (uint16_t *)m_malloc(maxlen * sizeof(uint16_t), false);
     if (self->buffer == NULL) {
         mp_raise_msg_varg(&mp_type_MemoryError, translate("Failed to allocate RX buffer of %d bytes"),
-                          maxlen * sizeof(uint16_t));
+            maxlen * sizeof(uint16_t));
     }
 
     // Set internal variables
@@ -138,12 +137,12 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu
 
     if (HAL_TIM_Base_GetState(&tim_handle) == HAL_TIM_STATE_RESET) {
         // Find a suitable timer
-        TIM_TypeDef * tim_instance = stm_peripherals_find_timer();
+        TIM_TypeDef *tim_instance = stm_peripherals_find_timer();
         stm_peripherals_timer_reserve(tim_instance);
 
         // Set ticks to 1us
         uint32_t source = stm_peripherals_timer_get_source_freq(tim_instance);
-        uint32_t prescaler = source/1000000;
+        uint32_t prescaler = source / 1000000;
 
         // Enable clocks and IRQ, set callback
         stm_peripherals_timer_preinit(tim_instance, 4, pulsein_timer_event_handler);
@@ -151,7 +150,7 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu
         // Set the new period
         tim_handle.Instance = tim_instance;
         tim_handle.Init.Prescaler = prescaler - 1;
-        tim_handle.Init.Period = 0x10000 - 1; //65 ms period (maximum)
+        tim_handle.Init.Period = 0x10000 - 1; // 65 ms period (maximum)
         HAL_TIM_Base_Init(&tim_handle);
 
         // Set registers manually
@@ -178,15 +177,15 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu
     common_hal_mcu_pin_claim(pin);
 }
 
-bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t* self) {
-    return (self->pin == NULL);
+bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t *self) {
+    return self->pin == NULL;
 }
 
-void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) {
+void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t *self) {
     if (common_hal_pulseio_pulsein_deinited(self)) {
         return;
     }
-    //Remove pulsein slot from shared array
+    // Remove pulsein slot from shared array
     _objs[self->pin->number] = NULL;
     reset_pin_number(self->pin->port, self->pin->number);
     self->pin = NULL;
@@ -197,14 +196,14 @@ void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) {
     }
 }
 
-void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t* self) {
+void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t *self) {
     HAL_NVIC_DisableIRQ(self->irq);
     self->paused = true;
 }
 
-void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, uint16_t trigger_duration) {
+void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t *self, uint16_t trigger_duration) {
     // Make sure we're paused.
-    if ( !self->paused ) {
+    if (!self->paused) {
         common_hal_pulseio_pulsein_pause(self);
     }
 
@@ -235,14 +234,14 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, uint16_t tri
     HAL_NVIC_EnableIRQ(self->irq);
 }
 
-void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t* self) {
+void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t *self) {
     HAL_NVIC_DisableIRQ(self->irq);
     self->start = 0;
     self->len = 0;
     HAL_NVIC_EnableIRQ(self->irq);
 }
 
-uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, int16_t index) {
+uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t *self, int16_t index) {
     HAL_NVIC_DisableIRQ(self->irq);
     if (index < 0) {
         index += self->len;
@@ -256,7 +255,7 @@ uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, int16_
     return value;
 }
 
-uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) {
+uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t *self) {
     if (self->len == 0) {
         mp_raise_IndexError_varg(translate("pop from empty %q"), MP_QSTR_PulseIn);
     }
@@ -269,19 +268,19 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) {
     return value;
 }
 
-uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t* self) {
+uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t *self) {
     return self->maxlen;
 }
 
-bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t* self) {
+bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t *self) {
     return self->paused;
 }
 
-uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t* self) {
+uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t *self) {
     return self->len;
 }
 
-static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t* self, uint8_t num) {
+static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t *self, uint8_t num) {
     if (num == 0) {
         self->irq = EXTI0_IRQn;
     } else if (num == 1) {
@@ -292,49 +291,42 @@ static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t* self, uint8_t num) {
         self->irq = EXTI3_IRQn;
     } else if (num == 4) {
         self->irq = EXTI4_IRQn;
-    } else if (num >= 5 && num <= 9 ) {
+    } else if (num >= 5 && num <= 9) {
         self->irq = EXTI9_5_IRQn;
     } else if (num >= 10 && num <= 15) {
         self->irq = EXTI15_10_IRQn;
     }
 }
 
-void EXTI0_IRQHandler(void)
-{
+void EXTI0_IRQHandler(void) {
     pulsein_exti_event_handler(0);
 }
-void EXTI1_IRQHandler(void)
-{
+void EXTI1_IRQHandler(void) {
     pulsein_exti_event_handler(1);
 }
-void EXTI2_IRQHandler(void)
-{
+void EXTI2_IRQHandler(void) {
     pulsein_exti_event_handler(2);
 }
-void EXTI3_IRQHandler(void)
-{
+void EXTI3_IRQHandler(void) {
     pulsein_exti_event_handler(3);
 }
-void EXTI4_IRQHandler(void)
-{
+void EXTI4_IRQHandler(void) {
     pulsein_exti_event_handler(4);
 }
 
-void EXTI9_5_IRQHandler(void)
-{
+void EXTI9_5_IRQHandler(void) {
     uint32_t pending = EXTI->PR;
     for (uint i = 5; i <= 9; i++) {
-        if(pending & (1 << i)) {
+        if (pending & (1 << i)) {
             pulsein_exti_event_handler(i);
         }
     }
 }
 
-void EXTI15_10_IRQHandler(void)
-{
+void EXTI15_10_IRQHandler(void) {
     uint32_t pending = EXTI->PR;
     for (uint i = 10; i <= 15; i++) {
-        if(pending & (1 << i)) {
+        if (pending & (1 << i)) {
             pulsein_exti_event_handler(i);
         }
     }
diff --git a/ports/stm/common-hal/pulseio/PulseIn.h b/ports/stm/common-hal/pulseio/PulseIn.h
index 34d0cc731..8de60b9cd 100644
--- a/ports/stm/common-hal/pulseio/PulseIn.h
+++ b/ports/stm/common-hal/pulseio/PulseIn.h
@@ -34,13 +34,13 @@
 typedef struct {
     mp_obj_base_t base;
 
-    const mcu_pin_obj_t* pin;
+    const mcu_pin_obj_t *pin;
     IRQn_Type irq;
     bool idle_state;
     bool paused;
     volatile bool first_edge;
 
-    uint16_t* buffer;
+    uint16_t *buffer;
     uint16_t maxlen;
 
     volatile uint16_t start;
diff --git a/ports/stm/common-hal/pulseio/PulseOut.c b/ports/stm/common-hal/pulseio/PulseOut.c
index 38027606f..9e28002a6 100644
--- a/ports/stm/common-hal/pulseio/PulseOut.c
+++ b/ports/stm/common-hal/pulseio/PulseOut.c
@@ -45,7 +45,7 @@ STATIC uint8_t refcount = 0;
 STATIC uint16_t *pulse_array = NULL;
 STATIC volatile uint16_t pulse_array_index = 0;
 STATIC uint16_t pulse_array_length;
-//Timer is shared, must be accessible by interrupt
+// Timer is shared, must be accessible by interrupt
 STATIC TIM_HandleTypeDef tim_handle;
 STATIC pulseio_pulseout_obj_t *curr_pulseout = NULL;
 
@@ -60,7 +60,7 @@ STATIC void turn_off(pulseio_pulseout_obj_t *pulseout) {
     HAL_TIM_PWM_Stop(&(pulseout->pwmout->handle), pulseout->pwmout->channel);
     // Make sure pin is low.
     HAL_GPIO_WritePin(pin_port(pulseout->pwmout->tim->pin->port),
-                      pin_mask(pulseout->pwmout->tim->pin->number), 0);
+        pin_mask(pulseout->pwmout->tim->pin->number), 0);
 }
 
 STATIC void start_timer(void) {
@@ -77,13 +77,11 @@ STATIC void start_timer(void) {
 
 STATIC void pulseout_event_handler(void) {
     // Detect TIM Update event
-    if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET)
-    {
-        if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET)
-        {
+    if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET) {
+        if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET) {
             __HAL_TIM_CLEAR_IT(&tim_handle, TIM_IT_UPDATE);
             if (curr_pulseout->pwmout == NULL) {
-                return; //invalid interrupt
+                return; // invalid interrupt
             }
 
             pulse_array_index++;
@@ -112,27 +110,27 @@ void pulseout_reset() {
     refcount = 0;
 }
 
-void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self,
-                                            const pwmio_pwmout_obj_t* carrier,
-                                            const mcu_pin_obj_t* pin,
-                                            uint32_t frequency,
-                                            uint16_t duty_cycle) {
+void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self,
+    const pwmio_pwmout_obj_t *carrier,
+    const mcu_pin_obj_t *pin,
+    uint32_t frequency,
+    uint16_t duty_cycle) {
     if (!carrier || pin || frequency) {
         mp_raise_NotImplementedError(translate("Port does not accept pins or frequency. Construct and pass a PWMOut Carrier instead"));
     }
 
     // Add to active PulseOuts
     refcount++;
-    TIM_TypeDef * tim_instance = stm_peripherals_find_timer();
+    TIM_TypeDef *tim_instance = stm_peripherals_find_timer();
     stm_peripherals_timer_reserve(tim_instance);
 
-    //calculate a 1ms period
+    // calculate a 1ms period
     uint32_t source = stm_peripherals_timer_get_source_freq(tim_instance);
-    uint32_t prescaler = source/1000000; //1us intervals
+    uint32_t prescaler = source / 1000000; // 1us intervals
 
     stm_peripherals_timer_preinit(tim_instance, 4, pulseout_event_handler);
     tim_handle.Instance = tim_instance;
-    tim_handle.Init.Period = 100; //immediately replaced.
+    tim_handle.Init.Period = 100; // immediately replaced.
     tim_handle.Init.Prescaler = prescaler - 1;
     tim_handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
     tim_handle.Init.CounterMode = TIM_COUNTERMODE_UP;
@@ -142,15 +140,15 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self,
     tim_handle.Instance->SR = 0;
 
     // The HAL can't work with const, recast required.
-    self->pwmout = (pwmio_pwmout_obj_t*)carrier;
+    self->pwmout = (pwmio_pwmout_obj_t *)carrier;
     turn_off(self);
 }
 
-bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t* self) {
+bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t *self) {
     return self->pwmout == NULL;
 }
 
-void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) {
+void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t *self) {
     if (common_hal_pulseio_pulseout_deinited(self)) {
         return;
     }
@@ -163,7 +161,7 @@ void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) {
     }
 }
 
-void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pulses, uint16_t length) {
+void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pulses, uint16_t length) {
     pulse_array = pulses;
     pulse_array_index = 0;
     pulse_array_length = length;
@@ -177,7 +175,7 @@ void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pu
     // Use when debugging, or issues are irrecoverable
     // uint32_t starttime = supervisor_ticks_ms64();
     // uint32_t timeout = 10000;
-    while(pulse_array_index < length) {
+    while (pulse_array_index < length) {
         // Do other things while we wait. The interrupts will handle sending the
         // signal.
         RUN_BACKGROUND_TASKS;
@@ -187,6 +185,6 @@ void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pu
         //    mp_raise_RuntimeError(translate("Error: Send Timeout"));
         // }
     }
-    //turn off timer counter.
+    // turn off timer counter.
     tim_handle.Instance->CR1 &= ~TIM_CR1_CEN;
 }
diff --git a/ports/stm/common-hal/pwmio/PWMOut.c b/ports/stm/common-hal/pwmio/PWMOut.c
index 85427185e..c463cac43 100644
--- a/ports/stm/common-hal/pwmio/PWMOut.c
+++ b/ports/stm/common-hal/pwmio/PWMOut.c
@@ -44,13 +44,13 @@ STATIC uint32_t tim_frequencies[TIM_BANK_ARRAY_LEN];
 STATIC bool never_reset_tim[TIM_BANK_ARRAY_LEN];
 
 STATIC uint32_t timer_get_internal_duty(uint16_t duty, uint32_t period) {
-    //duty cycle is duty/0xFFFF fraction x (number of pulses per period)
-    return (duty*period) / ((1 << 16) - 1);
+    // duty cycle is duty/0xFFFF fraction x (number of pulses per period)
+    return (duty * period) / ((1 << 16) - 1);
 }
 
-STATIC void timer_get_optimal_divisors(uint32_t*period, uint32_t*prescaler,
-                                       uint32_t frequency, uint32_t source_freq) {
-    //Find the largest possible period supported by this frequency
+STATIC void timer_get_optimal_divisors(uint32_t *period, uint32_t *prescaler,
+    uint32_t frequency, uint32_t source_freq) {
+    // Find the largest possible period supported by this frequency
     for (int i = 0; i < (1 << 16); i++) {
         *period = source_freq / (i * frequency);
         if (*period < (1 << 16) && *period >= 2) {
@@ -75,12 +75,12 @@ void pwmout_reset(void) {
     }
 }
 
-pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
-                                                    const mcu_pin_obj_t* pin,
-                                                    uint16_t duty,
-                                                    uint32_t frequency,
-                                                    bool variable_frequency) {
-    TIM_TypeDef * TIMx;
+pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self,
+    const mcu_pin_obj_t *pin,
+    uint16_t duty,
+    uint32_t frequency,
+    bool variable_frequency) {
+    TIM_TypeDef *TIMx;
     uint8_t tim_num = MP_ARRAY_SIZE(mcu_tim_pin_list);
     bool tim_taken_internal = false;
     bool tim_chan_taken = false;
@@ -89,47 +89,47 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
     bool first_time_setup = true;
 
     for (uint i = 0; i < tim_num; i++) {
-        const mcu_tim_pin_obj_t * l_tim = &mcu_tim_pin_list[i];
+        const mcu_tim_pin_obj_t *l_tim = &mcu_tim_pin_list[i];
         uint8_t l_tim_index = l_tim->tim_index - 1;
         uint8_t l_tim_channel = l_tim->channel_index - 1;
 
-        //if pin is same
+        // if pin is same
         if (l_tim->pin == pin) {
-            //check if the timer has a channel active, or is reserved by main timer system
+            // check if the timer has a channel active, or is reserved by main timer system
             if (l_tim_index < TIM_BANK_ARRAY_LEN && reserved_tim[l_tim_index] != 0) {
                 // Timer has already been reserved by an internal module
                 if (stm_peripherals_timer_is_reserved(mcu_tim_banks[l_tim_index])) {
                     tim_taken_internal = true;
-                    continue; //keep looking
+                    continue; // keep looking
                 }
-                //is it the same channel? (or all channels reserved by a var-freq)
+                // is it the same channel? (or all channels reserved by a var-freq)
                 if (reserved_tim[l_tim_index] & 1 << (l_tim_channel)) {
                     tim_chan_taken = true;
-                    continue; //keep looking, might be another viable option
+                    continue; // keep looking, might be another viable option
                 }
-                //If the frequencies are the same it's ok
+                // If the frequencies are the same it's ok
                 if (tim_frequencies[l_tim_index] != frequency) {
                     tim_taken_f_mismatch = true;
-                    continue; //keep looking
+                    continue; // keep looking
                 }
-                //you can't put a variable frequency on a partially reserved timer
+                // you can't put a variable frequency on a partially reserved timer
                 if (variable_frequency) {
                     var_freq_mismatch = true;
-                    continue; //keep looking
+                    continue; // keep looking
                 }
-                first_time_setup = false; //skip setting up the timer
+                first_time_setup = false; // skip setting up the timer
             }
-            //No problems taken, so set it up
+            // No problems taken, so set it up
             self->tim = l_tim;
             break;
         }
     }
 
-    //handle valid/invalid timer instance
+    // handle valid/invalid timer instance
     if (self->tim != NULL) {
-        //create instance
+        // create instance
         TIMx = mcu_tim_banks[self->tim->tim_index - 1];
-        //reserve timer/channel
+        // reserve timer/channel
         if (variable_frequency) {
             reserved_tim[self->tim->tim_index - 1] = 0x0F;
         } else {
@@ -137,7 +137,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
         }
         tim_frequencies[self->tim->tim_index - 1] = frequency;
         stm_peripherals_timer_reserve(TIMx);
-    } else { //no match found
+    } else { // no match found
         if (tim_chan_taken) {
             mp_raise_ValueError(translate("No more timers available on this pin."));
         } else if (tim_taken_internal) {
@@ -161,15 +161,15 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
 
     tim_clock_enable(1 << (self->tim->tim_index - 1));
 
-    //translate channel into handle value
+    // translate channel into handle value
     self->channel = 4 * (self->tim->channel_index - 1);
 
-    uint32_t prescaler = 0; //prescaler is 15 bit
-    uint32_t period = 0; //period is 16 bit
+    uint32_t prescaler = 0; // prescaler is 15 bit
+    uint32_t period = 0; // period is 16 bit
     uint32_t source_freq = stm_peripherals_timer_get_source_freq(TIMx);
     timer_get_optimal_divisors(&period, &prescaler, frequency, source_freq);
 
-    //Timer init
+    // Timer init
     self->handle.Instance = TIMx;
     self->handle.Init.Period = period - 1;
     self->handle.Init.Prescaler = prescaler - 1;
@@ -177,14 +177,14 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
     self->handle.Init.CounterMode = TIM_COUNTERMODE_UP;
     self->handle.Init.RepetitionCounter = 0;
 
-    //only run init if this is the first instance of this timer
+    // only run init if this is the first instance of this timer
     if (first_time_setup) {
         if (HAL_TIM_PWM_Init(&self->handle) != HAL_OK) {
             mp_raise_ValueError(translate("Could not initialize timer"));
         }
     }
 
-    //Channel/PWM init
+    // Channel/PWM init
     self->chan_handle.OCMode = TIM_OCMODE_PWM1;
     self->chan_handle.Pulse = timer_get_internal_duty(duty, period);
     self->chan_handle.OCPolarity = TIM_OCPOLARITY_HIGH;
@@ -215,7 +215,7 @@ void common_hal_pwmio_pwmout_never_reset(pwmio_pwmout_obj_t *self) {
 }
 
 void common_hal_pwmio_pwmout_reset_ok(pwmio_pwmout_obj_t *self) {
-    for(size_t i = 0; i < TIM_BANK_ARRAY_LEN; i++) {
+    for (size_t i = 0; i < TIM_BANK_ARRAY_LEN; i++) {
         if (mcu_tim_banks[i] == self->handle.Instance) {
             never_reset_tim[i] = false;
             break;
@@ -223,15 +223,15 @@ void common_hal_pwmio_pwmout_reset_ok(pwmio_pwmout_obj_t *self) {
     }
 }
 
-bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t* self) {
+bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) {
     return self->tim == NULL;
 }
 
-void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) {
+void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) {
     if (common_hal_pwmio_pwmout_deinited(self)) {
         return;
     }
-    //var freq shuts down entire timer, others just their channel
+    // var freq shuts down entire timer, others just their channel
     if (self->variable_frequency) {
         reserved_tim[self->tim->tim_index - 1] = 0x00;
     } else {
@@ -240,7 +240,7 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) {
     }
     reset_pin_number(self->tim->pin->port,self->tim->pin->number);
 
-    //if reserved timer has no active channels, we can disable it
+    // if reserved timer has no active channels, we can disable it
     if (!reserved_tim[self->tim->tim_index - 1]) {
         tim_frequencies[self->tim->tim_index - 1] = 0x00;
         stm_peripherals_timer_free(self->handle.Instance);
@@ -249,18 +249,18 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) {
     self->tim = NULL;
 }
 
-void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t* self, uint16_t duty) {
+void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t duty) {
     uint32_t internal_duty_cycle = timer_get_internal_duty(duty, self->period);
     __HAL_TIM_SET_COMPARE(&self->handle, self->channel, internal_duty_cycle);
     self->duty_cycle = duty;
 }
 
-uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) {
+uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) {
     return self->duty_cycle;
 }
 
-void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t frequency) {
-    //don't halt setup for the same frequency
+void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self, uint32_t frequency) {
+    // don't halt setup for the same frequency
     if (frequency == self->frequency) {
         return;
     }
@@ -270,14 +270,14 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t fr
     uint32_t source_freq = stm_peripherals_timer_get_source_freq(self->handle.Instance);
     timer_get_optimal_divisors(&period, &prescaler, frequency, source_freq);
 
-    //shut down
+    // shut down
     HAL_TIM_PWM_Stop(&self->handle, self->channel);
 
-    //Only change altered values
+    // Only change altered values
     self->handle.Init.Period = period - 1;
     self->handle.Init.Prescaler = prescaler - 1;
 
-    //restart everything, adjusting for new speed
+    // restart everything, adjusting for new speed
     if (HAL_TIM_PWM_Init(&self->handle) != HAL_OK) {
         mp_raise_ValueError(translate("Could not re-init timer"));
     }
@@ -296,10 +296,10 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t fr
     self->period = period;
 }
 
-uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) {
+uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) {
     return self->frequency;
 }
 
-bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t* self) {
+bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) {
     return self->variable_frequency;
 }
diff --git a/ports/stm/common-hal/pwmio/PWMOut.h b/ports/stm/common-hal/pwmio/PWMOut.h
index 5d8001202..4cf2b1c67 100644
--- a/ports/stm/common-hal/pwmio/PWMOut.h
+++ b/ports/stm/common-hal/pwmio/PWMOut.h
@@ -39,8 +39,8 @@ typedef struct {
     TIM_HandleTypeDef handle;
     TIM_OC_InitTypeDef chan_handle;
     const mcu_tim_pin_obj_t *tim;
-    uint8_t channel: 7;
-    bool variable_frequency: 1;
+    uint8_t channel : 7;
+    bool variable_frequency : 1;
     uint16_t duty_cycle;
     uint32_t frequency;
     uint32_t period;
diff --git a/ports/stm/common-hal/rgbmatrix/RGBMatrix.c b/ports/stm/common-hal/rgbmatrix/RGBMatrix.c
index 36ed6d018..4c0ad94b0 100644
--- a/ports/stm/common-hal/rgbmatrix/RGBMatrix.c
+++ b/ports/stm/common-hal/rgbmatrix/RGBMatrix.c
@@ -34,24 +34,24 @@
 extern void _PM_IRQ_HANDLER(void);
 
 void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self) {
-    TIM_TypeDef * timer = stm_peripherals_find_timer();
+    TIM_TypeDef *timer = stm_peripherals_find_timer();
     stm_peripherals_timer_reserve(timer);
     stm_peripherals_timer_never_reset(timer);
     return timer;
 }
 
-void common_hal_rgbmatrix_timer_enable(void* ptr) {
-    TIM_TypeDef *tim = (TIM_TypeDef*)ptr;
+void common_hal_rgbmatrix_timer_enable(void *ptr) {
+    TIM_TypeDef *tim = (TIM_TypeDef *)ptr;
     HAL_NVIC_EnableIRQ(stm_peripherals_timer_get_irqnum(tim));
 }
 
-void common_hal_rgbmatrix_timer_disable(void* ptr) {
-    TIM_TypeDef *tim = (TIM_TypeDef*)ptr;
+void common_hal_rgbmatrix_timer_disable(void *ptr) {
+    TIM_TypeDef *tim = (TIM_TypeDef *)ptr;
     tim->DIER &= ~TIM_DIER_UIE;
 }
 
-void common_hal_rgbmatrix_timer_free(void* ptr) {
-    TIM_TypeDef *tim = (TIM_TypeDef*)ptr;
+void common_hal_rgbmatrix_timer_free(void *ptr) {
+    TIM_TypeDef *tim = (TIM_TypeDef *)ptr;
     stm_peripherals_timer_free(tim);
     common_hal_rgbmatrix_timer_disable(ptr);
 }
diff --git a/ports/stm/common-hal/rgbmatrix/RGBMatrix.h b/ports/stm/common-hal/rgbmatrix/RGBMatrix.h
index 2debb6a76..cc4b82da0 100644
--- a/ports/stm/common-hal/rgbmatrix/RGBMatrix.h
+++ b/ports/stm/common-hal/rgbmatrix/RGBMatrix.h
@@ -30,8 +30,8 @@
 #include "shared-module/rgbmatrix/RGBMatrix.h"
 
 void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self);
-void common_hal_rgbmatrix_timer_enable(void*);
-void common_hal_rgbmatrix_timer_disable(void*);
-void common_hal_rgbmatrix_timer_free(void*);
+void common_hal_rgbmatrix_timer_enable(void *);
+void common_hal_rgbmatrix_timer_disable(void *);
+void common_hal_rgbmatrix_timer_free(void *);
 
 #endif
diff --git a/ports/stm/common-hal/sdioio/SDCard.c b/ports/stm/common-hal/sdioio/SDCard.c
index de0e8d111..e09e2e1b3 100644
--- a/ports/stm/common-hal/sdioio/SDCard.c
+++ b/ports/stm/common-hal/sdioio/SDCard.c
@@ -40,18 +40,18 @@ STATIC bool reserved_sdio[MP_ARRAY_SIZE(mcu_sdio_banks)];
 STATIC bool never_reset_sdio[MP_ARRAY_SIZE(mcu_sdio_banks)];
 
 STATIC const mcu_periph_obj_t *find_pin_function(const mcu_periph_obj_t *table, size_t sz, const mcu_pin_obj_t *pin, int periph_index) {
-    for(size_t i = 0; i<sz; i++, table++) {
-        if(periph_index == table->periph_index && pin == table->pin ) {
+    for (size_t i = 0; i < sz; i++, table++) {
+        if (periph_index == table->periph_index && pin == table->pin) {
             return table;
         }
     }
     return NULL;
 }
 
-//match pins to SDIO objects
+// match pins to SDIO objects
 STATIC int check_pins(sdioio_sdcard_obj_t *self,
-         const mcu_pin_obj_t * clock, const mcu_pin_obj_t * command,
-         uint8_t num_data, mcu_pin_obj_t ** data) {
+    const mcu_pin_obj_t *clock, const mcu_pin_obj_t *command,
+    uint8_t num_data, mcu_pin_obj_t **data) {
     bool sdio_taken = false;
 
     const uint8_t sdio_clock_len = MP_ARRAY_SIZE(mcu_sdio_clock_list);
@@ -78,26 +78,26 @@ STATIC int check_pins(sdioio_sdcard_obj_t *self,
         }
 
         const mcu_periph_obj_t *mcu_sdio_data0 = NULL;
-        if(!(mcu_sdio_data0 = find_pin_function(mcu_sdio_data0_list, sdio_data0_len, data[0], periph_index))) {
+        if (!(mcu_sdio_data0 = find_pin_function(mcu_sdio_data0_list, sdio_data0_len, data[0], periph_index))) {
             continue;
         }
 
         const mcu_periph_obj_t *mcu_sdio_data1 = NULL;
-        if(num_data > 1 && !(mcu_sdio_data1 = find_pin_function(mcu_sdio_data1_list, sdio_data1_len, data[1], periph_index))) {
+        if (num_data > 1 && !(mcu_sdio_data1 = find_pin_function(mcu_sdio_data1_list, sdio_data1_len, data[1], periph_index))) {
             continue;
         }
 
         const mcu_periph_obj_t *mcu_sdio_data2 = NULL;
-        if(num_data > 2 && !(mcu_sdio_data2 = find_pin_function(mcu_sdio_data2_list, sdio_data2_len, data[2], periph_index))) {
+        if (num_data > 2 && !(mcu_sdio_data2 = find_pin_function(mcu_sdio_data2_list, sdio_data2_len, data[2], periph_index))) {
             continue;
         }
 
         const mcu_periph_obj_t *mcu_sdio_data3 = NULL;
-        if(num_data > 3 && !(mcu_sdio_data3 = find_pin_function(mcu_sdio_data3_list, sdio_data3_len, data[3], periph_index))) {
+        if (num_data > 3 && !(mcu_sdio_data3 = find_pin_function(mcu_sdio_data3_list, sdio_data3_len, data[3], periph_index))) {
             continue;
         }
 
-        if (reserved_sdio[periph_index-1]) {
+        if (reserved_sdio[periph_index - 1]) {
             sdio_taken = true;
             continue;
         }
@@ -121,16 +121,16 @@ STATIC int check_pins(sdioio_sdcard_obj_t *self,
 
 
 void common_hal_sdioio_sdcard_construct(sdioio_sdcard_obj_t *self,
-        const mcu_pin_obj_t * clock, const mcu_pin_obj_t * command,
-        uint8_t num_data, mcu_pin_obj_t ** data, uint32_t frequency) {
+    const mcu_pin_obj_t *clock, const mcu_pin_obj_t *command,
+    uint8_t num_data, mcu_pin_obj_t **data, uint32_t frequency) {
 
     int periph_index = check_pins(self, clock, command, num_data, data);
-    SDIO_TypeDef * SDIOx = mcu_sdio_banks[periph_index - 1];
+    SDIO_TypeDef *SDIOx = mcu_sdio_banks[periph_index - 1];
 
     GPIO_InitTypeDef GPIO_InitStruct = {0};
 
     /* Configure data pins */
-    for (int i=0; i<num_data; i++) {
+    for (int i = 0; i < num_data; i++) {
         GPIO_InitStruct.Pin = pin_mask(data[i]->number);
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -186,7 +186,7 @@ void common_hal_sdioio_sdcard_construct(sdioio_sdcard_obj_t *self,
 
     common_hal_mcu_pin_claim(clock);
     common_hal_mcu_pin_claim(command);
-    for (int i=0; i<num_data; i++) {
+    for (int i = 0; i < num_data; i++) {
         common_hal_mcu_pin_claim(data[i]);
     }
 
@@ -217,7 +217,7 @@ STATIC void wait_write_complete(sdioio_sdcard_obj_t *self) {
         // This waits up to 60s for programming to complete.  This seems like
         // an extremely long time, but this is the timeout that micropython's
         // implementation uses
-        for (int i=0; i < 60000 && st == HAL_SD_CARD_PROGRAMMING; i++) {
+        for (int i = 0; i < 60000 && st == HAL_SD_CARD_PROGRAMMING; i++) {
             st = HAL_SD_GetCardState(&self->handle);
             HAL_Delay(1);
         };
@@ -293,7 +293,7 @@ void common_hal_sdioio_sdcard_deinit(sdioio_sdcard_obj_t *self) {
     reset_mcu_periph(self->clock);
     self->command = NULL;
 
-    for (size_t i=0; i<MP_ARRAY_SIZE(self->data); i++) {
+    for (size_t i = 0; i < MP_ARRAY_SIZE(self->data); i++) {
         reset_mcu_periph(self->data[i]);
         self->data[i] = NULL;
     }
@@ -313,13 +313,13 @@ void common_hal_sdioio_sdcard_never_reset(sdioio_sdcard_obj_t *self) {
     never_reset_mcu_periph(self->command);
     never_reset_mcu_periph(self->clock);
 
-    for (size_t i=0; i<MP_ARRAY_SIZE(self->data); i++) {
+    for (size_t i = 0; i < MP_ARRAY_SIZE(self->data); i++) {
         never_reset_mcu_periph(self->data[i]);
     }
 }
 
 void sdioio_reset() {
-    for (size_t i=0; i<MP_ARRAY_SIZE(reserved_sdio); i++) {
+    for (size_t i = 0; i < MP_ARRAY_SIZE(reserved_sdio); i++) {
         if (!never_reset_sdio[i]) {
             reserved_sdio[i] = false;
         }
diff --git a/ports/stm/common-hal/sdioio/SDCard.h b/ports/stm/common-hal/sdioio/SDCard.h
index b737b6939..845a5aa5f 100644
--- a/ports/stm/common-hal/sdioio/SDCard.h
+++ b/ports/stm/common-hal/sdioio/SDCard.h
@@ -36,7 +36,7 @@
 typedef struct {
     mp_obj_base_t base;
     SD_HandleTypeDef handle;
-    uint8_t num_data:3, state_programming:1;
+    uint8_t num_data : 3, state_programming : 1;
     bool has_lock;
     const mcu_periph_obj_t *command;
     const mcu_periph_obj_t *clock;
diff --git a/ports/stm/common-hal/supervisor/Runtime.c b/ports/stm/common-hal/supervisor/Runtime.c
index 974f26cec..f82765178 100755..100644
--- a/ports/stm/common-hal/supervisor/Runtime.c
+++ b/ports/stm/common-hal/supervisor/Runtime.c
@@ -29,9 +29,9 @@
 #include "supervisor/serial.h"
 
 bool common_hal_supervisor_runtime_get_serial_connected(void) {
-    return (bool) serial_connected();
+    return (bool)serial_connected();
 }
 
 bool common_hal_supervisor_runtime_get_serial_bytes_available(void) {
-    return (bool) serial_bytes_available();
+    return (bool)serial_bytes_available();
 }
diff --git a/ports/stm/hal_conf/stm32f4xx_hal_conf.h b/ports/stm/hal_conf/stm32f4xx_hal_conf.h
index ad8939052..7fb3b77e5 100644
--- a/ports/stm/hal_conf/stm32f4xx_hal_conf.h
+++ b/ports/stm/hal_conf/stm32f4xx_hal_conf.h
@@ -26,7 +26,7 @@
 #define __STM32F4xx_HAL_CONF_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Exported types ------------------------------------------------------------*/
@@ -38,11 +38,11 @@
   *        This value is used by the RCC HAL module to compute the system frequency
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE)
+#if !defined(HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
-#if !defined  (HSE_STARTUP_TIMEOUT)
+#if !defined(HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
@@ -51,14 +51,14 @@
   *        This value is used by the RCC HAL module to compute the system frequency
   *        (when HSI is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSI_VALUE)
+#if !defined(HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE)
+#if !defined(LSI_VALUE)
  #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -66,11 +66,11 @@
 /**
   * @brief External Low Speed oscillator (LSE) value.
   */
-#if !defined  (LSE_VALUE)
+#if !defined(LSE_VALUE)
  #define LSE_VALUE  32768    /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 
-#if !defined  (LSE_STARTUP_TIMEOUT)
+#if !defined(LSE_STARTUP_TIMEOUT)
   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
@@ -80,7 +80,7 @@
   *        This value is used by the I2S HAL module to compute the I2S clock source
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
+#if !defined(EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
 #endif /* EXTERNAL_CLOCK_VALUE */
 
@@ -371,7 +371,7 @@
   */
   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */
diff --git a/ports/stm/hal_conf/stm32f7xx_hal_conf.h b/ports/stm/hal_conf/stm32f7xx_hal_conf.h
index 3dd368e85..72cb60e44 100644
--- a/ports/stm/hal_conf/stm32f7xx_hal_conf.h
+++ b/ports/stm/hal_conf/stm32f7xx_hal_conf.h
@@ -26,7 +26,7 @@
 #define __STM32F7xx_HAL_CONF_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Exported types ------------------------------------------------------------*/
@@ -38,11 +38,11 @@
   *        This value is used by the RCC HAL module to compute the system frequency
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE)
+#if !defined(HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
-#if !defined  (HSE_STARTUP_TIMEOUT)
+#if !defined(HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
@@ -51,14 +51,14 @@
   *        This value is used by the RCC HAL module to compute the system frequency
   *        (when HSI is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSI_VALUE)
+#if !defined(HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE)
+#if !defined(LSI_VALUE)
  #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -66,11 +66,11 @@
 /**
   * @brief External Low Speed oscillator (LSE) value.
   */
-#if !defined  (LSE_VALUE)
+#if !defined(LSE_VALUE)
  #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 
-#if !defined  (LSE_STARTUP_TIMEOUT)
+#if !defined(LSE_STARTUP_TIMEOUT)
   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
@@ -79,7 +79,7 @@
   *        This value is used by the I2S HAL module to compute the I2S clock source
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
+#if !defined(EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* EXTERNAL_CLOCK_VALUE */
 
@@ -376,7 +376,7 @@
   */
   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */
diff --git a/ports/stm/hal_conf/stm32h7xx_hal_conf.h b/ports/stm/hal_conf/stm32h7xx_hal_conf.h
index a0328610c..630e63b8f 100644
--- a/ports/stm/hal_conf/stm32h7xx_hal_conf.h
+++ b/ports/stm/hal_conf/stm32h7xx_hal_conf.h
@@ -24,7 +24,7 @@
 #define __STM32H7xx_HAL_CONF_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Exported types ------------------------------------------------------------*/
@@ -36,11 +36,11 @@
   *        This value is used by the RCC HAL module to compute the system frequency
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE)
+#if !defined(HSE_VALUE)
 #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
 #endif /* HSE_VALUE */
 
-#if !defined  (HSE_STARTUP_TIMEOUT)
+#if !defined(HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
@@ -48,7 +48,7 @@
   * @brief Internal  oscillator (CSI) default value.
   *        This value is the default CSI value after Reset.
   */
-#if !defined  (CSI_VALUE)
+#if !defined(CSI_VALUE)
   #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* CSI_VALUE */
 
@@ -57,14 +57,14 @@
   *        This value is used by the RCC HAL module to compute the system frequency
   *        (when HSI is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSI_VALUE)
+#if !defined(HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE)
+#if !defined(LSI_VALUE)
  #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -74,11 +74,11 @@
   * @brief External Low Speed oscillator (LSE) value.
   *        This value is used by the UART, RTC HAL module to compute the system frequency
   */
-#if !defined  (LSE_VALUE)
+#if !defined(LSE_VALUE)
   #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
 #endif /* LSE_VALUE */
 
-#if !defined  (LSE_STARTUP_TIMEOUT)
+#if !defined(LSE_STARTUP_TIMEOUT)
   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
@@ -87,7 +87,7 @@
   *        This value is used by the I2S HAL module to compute the I2S clock source
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
+#if !defined(EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
 #endif /* EXTERNAL_CLOCK_VALUE */
 
@@ -421,7 +421,7 @@
   */
   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */
diff --git a/ports/stm/mpconfigport.h b/ports/stm/mpconfigport.h
index 3f64e6565..4ac8c20ea 100644
--- a/ports/stm/mpconfigport.h
+++ b/ports/stm/mpconfigport.h
@@ -37,7 +37,7 @@ extern uint8_t _ld_default_stack_size;
 
 // 24kiB stack
 // #define CIRCUITPY_DEFAULT_STACK_SIZE            0x6000
-#define CIRCUITPY_DEFAULT_STACK_SIZE            ((uint32_t) &_ld_default_stack_size)
+#define CIRCUITPY_DEFAULT_STACK_SIZE            ((uint32_t)&_ld_default_stack_size)
 
 #include "py/circuitpy_mpconfig.h"
 
@@ -60,6 +60,6 @@ extern uint8_t _ld_default_stack_size;
 #define MICROPY_PORT_ROOT_POINTERS \
     void *cpy_uart_obj_all[MAX_UART]; \
     void *cpy_i2c_obj_all[MAX_I2C]; \
-	CIRCUITPY_COMMON_ROOT_POINTERS
+    CIRCUITPY_COMMON_ROOT_POINTERS
 
 #endif  // __INCLUDED_MPCONFIGPORT_H
diff --git a/ports/stm/mphalport.h b/ports/stm/mphalport.h
index 2c4caf3b2..cf175b526 100644
--- a/ports/stm/mphalport.h
+++ b/ports/stm/mphalport.h
@@ -35,7 +35,7 @@
 
 // Global millisecond tick count (driven by SysTick interrupt).
 static inline mp_uint_t mp_hal_ticks_ms(void) {
-  return supervisor_ticks_ms32();
+    return supervisor_ticks_ms32();
 }
 // Number of bytes in receive buffer
 extern volatile uint8_t usb_rx_count;
diff --git a/ports/stm/packages/LQFP100_f4.c b/ports/stm/packages/LQFP100_f4.c
index 9136b9495..f1c3cc367 100644
--- a/ports/stm/packages/LQFP100_f4.c
+++ b/ports/stm/packages/LQFP100_f4.c
@@ -4,114 +4,114 @@
 
 STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = {
 // Pins 1-25
-  { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
-  { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
-  { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
-  { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
-  { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
-  /* VBAT -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  // PC14 OSC32_IN ----------------------------------*/
-  // PC15 OSC32_OUT ---------------------------------*/
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  // PH0 OSC_IN -------------------------------------*/
-  // PH1 OSC_OUT ------------------------------------*/
-  // NRST -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
-  { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
-  { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
-  // VDD --------------------------------------------*/
-  // VSSA -------------------------------------------*/
-  // VREF+ ------------------------------------------*/
-  // VDDA -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
+    /* VBAT -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    // PC14 OSC32_IN ----------------------------------*/
+    // PC15 OSC32_OUT ---------------------------------*/
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    // PH0 OSC_IN -------------------------------------*/
+    // PH1 OSC_OUT ------------------------------------*/
+    // NRST -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
+    // VDD --------------------------------------------*/
+    // VSSA -------------------------------------------*/
+    // VREF+ ------------------------------------------*/
+    // VDDA -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
 
 // Pins 26-50
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
-  { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
-  { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
-  { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
-  { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
-  { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
-  { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
-  { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
-  { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-#if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx)
-  { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
-#endif //or VCAP1 -----------------------------------*/
-  // VCAP1 or VSS -----------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    #if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx)
+    { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
+    #endif // or VCAP1 -----------------------------------*/
+    // VCAP1 or VSS -----------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 51-75
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
-  { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
-  { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
-  { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
-  { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
-  { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
-  { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
-  { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
-  { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
-  { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
-  { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
-  { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
-  // VCAP2 ------------------------------------------*/
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
+    { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
+    { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    // VCAP2 ------------------------------------------*/
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 76-100
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
-  { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
-  { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
-  { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
-  { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
-  { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
-  { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
-  { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
-  { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
-  { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
-  { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  // BOOT0 ------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
-  { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    // BOOT0 ------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 };
 MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
diff --git a/ports/stm/packages/LQFP100_x7.c b/ports/stm/packages/LQFP100_x7.c
index 4d3d5f45a..77a887b0d 100644
--- a/ports/stm/packages/LQFP100_x7.c
+++ b/ports/stm/packages/LQFP100_x7.c
@@ -4,112 +4,112 @@
 
 STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = {
 // Pins 1-25
-  { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
-  { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
-  { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
-  { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
-  { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
-  /* VBAT -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  // PC14 OSC32_IN ----------------------------------*/
-  // PC15 OSC32_OUT ---------------------------------*/
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  // PH0 OSC_IN -------------------------------------*/
-  // PH1 OSC_OUT ------------------------------------*/
-  // NRST -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
-  { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
-  { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
-  // VSSA -------------------------------------------*/
-  // VREF+ ------------------------------------------*/
-  // VDDA -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
+    /* VBAT -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    // PC14 OSC32_IN ----------------------------------*/
+    // PC15 OSC32_OUT ---------------------------------*/
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    // PH0 OSC_IN -------------------------------------*/
+    // PH1 OSC_OUT ------------------------------------*/
+    // NRST -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
+    // VSSA -------------------------------------------*/
+    // VREF+ ------------------------------------------*/
+    // VDDA -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
 
 // Pins 26-50
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
-  { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
-  { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
-  { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
-  { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
-  { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
-  { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
-  { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
-  { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
-  // VCAP1 ------------------------------------------*/
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
+    // VCAP1 ------------------------------------------*/
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 51-75
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
-  { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
-  { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
-  { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
-  { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
-  { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
-  { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
-  { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
-  { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
-  { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
-  { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
-  { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
-  // VCAP2 ------------------------------------------*/
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
+    { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
+    { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    // VCAP2 ------------------------------------------*/
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 76-100
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
-  { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
-  { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
-  { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
-  { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
-  { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
-  { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
-  { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
-  { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
-  { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
-  { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  // BOOT0 ------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
-  { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    // BOOT0 ------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 };
 MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
diff --git a/ports/stm/packages/LQFP144.c b/ports/stm/packages/LQFP144.c
index 5e0d743d7..a08d16086 100644
--- a/ports/stm/packages/LQFP144.c
+++ b/ports/stm/packages/LQFP144.c
@@ -4,156 +4,156 @@
 
 STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = {
 // Pins 1-36
-  { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
-  { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
-  { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
-  { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
-  { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
-  /* VBAT -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  // PC14 OSC32_IN ----------------------------------*/
-  // PC15 OSC32_OUT ---------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) },
-  { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) },
-  { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) },
-  { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) },
-  { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) },
-  { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) },
-  { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) },
-  { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) },
-  { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) },
-  { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) },
-  // PH0 OSC_IN -------------------------------------*/
-  // PH1 OSC_OUT ------------------------------------*/
-  // NRST -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
-  { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
-  { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
-  // VDD --------------------------------------------*/
-  // VSSA -------------------------------------------*/
-  // VREF+ ------------------------------------------*/
-  // VDDA -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
+    /* VBAT -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    // PC14 OSC32_IN ----------------------------------*/
+    // PC15 OSC32_OUT ---------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) },
+    { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) },
+    { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) },
+    { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) },
+    { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) },
+    { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) },
+    { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) },
+    { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) },
+    { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) },
+    { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) },
+    // PH0 OSC_IN -------------------------------------*/
+    // PH1 OSC_OUT ------------------------------------*/
+    // NRST -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
+    // VDD --------------------------------------------*/
+    // VSSA -------------------------------------------*/
+    // VREF+ ------------------------------------------*/
+    // VDDA -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
 
 // Pins 37-72
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) },
-  { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) },
-  { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) },
-  { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) },
-  { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) },
-  { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) },
-  { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
-  { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
-  { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
-  { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
-  { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
-  { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
-  { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
-  { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
-  // VCAP1 ------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) },
+    { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) },
+    { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) },
+    { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) },
+    { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) },
+    { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) },
+    { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
+    // VCAP1 ------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 73-108
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
-  { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
-  { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
-  { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
-  { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
-  { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
-  { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) },
-  { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) },
-  { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) },
-  { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) },
-  { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) },
-  { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) },
-  { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) },
-  // VSS --------------------------------------------*/
-  // VDD or VDD_USB (F412, F446) --------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
-  { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
-  { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
-  { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
-  { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
-  { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
-  // VCAP2 ------------------------------------------*/
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
+    { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
+    { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) },
+    { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) },
+    { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) },
+    { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) },
+    { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) },
+    { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) },
+    { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) },
+    // VSS --------------------------------------------*/
+    // VDD or VDD_USB (F412, F446) --------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    // VCAP2 ------------------------------------------*/
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 109-144
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
-  { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
-  { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
-  { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
-  { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
-  { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
-  { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
-  { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
-  { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
-  { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
-  { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) },
-  { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) },
-  { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) },
-  { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) },
-  { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) },
-  { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  // BOOT0 ------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
-  { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
-  // PDR_ON -----------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
+    { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) },
+    { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) },
+    { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) },
+    { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) },
+    { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) },
+    { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    // BOOT0 ------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
+    // PDR_ON -----------------------------------------*/
+    // VDD --------------------------------------------*/
 
 };
 MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
diff --git a/ports/stm/packages/LQFP64.c b/ports/stm/packages/LQFP64.c
index 52ca27cd9..71e8be978 100644
--- a/ports/stm/packages/LQFP64.c
+++ b/ports/stm/packages/LQFP64.c
@@ -4,78 +4,78 @@
 
 STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = {
 // Pins 1-16
-  /* VBAT -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  // PC14 OSC32_IN ----------------------------------*/
-  // PC15 OSC32_OUT ---------------------------------*/
-  // PH0 OSC_IN -------------------------------------*/
-  // PH1 OSC_OUT ------------------------------------*/
-  // NRST -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
-  { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
-  { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
-  // VSSA -------------------------------------------*/
-  // VDDA -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    /* VBAT -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    // PC14 OSC32_IN ----------------------------------*/
+    // PC15 OSC32_OUT ---------------------------------*/
+    // PH0 OSC_IN -------------------------------------*/
+    // PH1 OSC_OUT ------------------------------------*/
+    // NRST -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
+    // VSSA -------------------------------------------*/
+    // VDDA -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
 
 // Pins 17-32
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-#if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx)
-  { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
-#endif //or VCAP1 -----------------------------------*/
-  // VCAP1 or VSS -----------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    #if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx)
+    { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
+    #endif // or VCAP1 -----------------------------------*/
+    // VCAP1 or VSS -----------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 33-48
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
-  { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
-  { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
-  { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
-  { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
-  { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
-  { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
-  // VSS or VCAP (F405) -----------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    // VSS or VCAP (F405) -----------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 49-64
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
-  { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
-  { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
-  { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  // BOOT0 ------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    // BOOT0 ------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 };
 MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
diff --git a/ports/stm/packages/TFBGA216.c b/ports/stm/packages/TFBGA216.c
index af91e70ae..ebcae5f2d 100644
--- a/ports/stm/packages/TFBGA216.c
+++ b/ports/stm/packages/TFBGA216.c
@@ -31,201 +31,201 @@
 
 STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = {
 // Row A
-  { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
-  { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
-  { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
-  { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) },
-  { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
-  { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
-  { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) },
+    { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
+    { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
+    { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
 
 // Row B
-  { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
-  { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
-  { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) },
-  { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) },
-  { MP_ROM_QSTR(MP_QSTR_PJ13), MP_ROM_PTR(&pin_PJ13) },
-  { MP_ROM_QSTR(MP_QSTR_PJ12), MP_ROM_PTR(&pin_PJ12) },
-  { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
-  { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
-  { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
-  { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
-  { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
+    { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) },
+    { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) },
+    { MP_ROM_QSTR(MP_QSTR_PJ13), MP_ROM_PTR(&pin_PJ13) },
+    { MP_ROM_QSTR(MP_QSTR_PJ12), MP_ROM_PTR(&pin_PJ12) },
+    { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
 
 // Row C
-  { MP_ROM_QSTR(MP_QSTR_PI08), MP_ROM_PTR(&pin_PI08) },
-  { MP_ROM_QSTR(MP_QSTR_PI04), MP_ROM_PTR(&pin_PI04) },
-  { MP_ROM_QSTR(MP_QSTR_PK07), MP_ROM_PTR(&pin_PK07) },
-  { MP_ROM_QSTR(MP_QSTR_PK06), MP_ROM_PTR(&pin_PK06) },
-  { MP_ROM_QSTR(MP_QSTR_PK05), MP_ROM_PTR(&pin_PK05) },
-  { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) },
-  { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) },
-  { MP_ROM_QSTR(MP_QSTR_PJ14), MP_ROM_PTR(&pin_PJ14) },
-  { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
-  { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
-  { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
-  { MP_ROM_QSTR(MP_QSTR_PI03), MP_ROM_PTR(&pin_PI03) },
-  { MP_ROM_QSTR(MP_QSTR_PI02), MP_ROM_PTR(&pin_PI02) },
-  { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_PI08), MP_ROM_PTR(&pin_PI08) },
+    { MP_ROM_QSTR(MP_QSTR_PI04), MP_ROM_PTR(&pin_PI04) },
+    { MP_ROM_QSTR(MP_QSTR_PK07), MP_ROM_PTR(&pin_PK07) },
+    { MP_ROM_QSTR(MP_QSTR_PK06), MP_ROM_PTR(&pin_PK06) },
+    { MP_ROM_QSTR(MP_QSTR_PK05), MP_ROM_PTR(&pin_PK05) },
+    { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) },
+    { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) },
+    { MP_ROM_QSTR(MP_QSTR_PJ14), MP_ROM_PTR(&pin_PJ14) },
+    { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_PI03), MP_ROM_PTR(&pin_PI03) },
+    { MP_ROM_QSTR(MP_QSTR_PI02), MP_ROM_PTR(&pin_PI02) },
+    { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
 
 // Row D
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) },
-  { MP_ROM_QSTR(MP_QSTR_PI05), MP_ROM_PTR(&pin_PI05) },
-  { MP_ROM_QSTR(MP_QSTR_PI07), MP_ROM_PTR(&pin_PI07) },
-  { MP_ROM_QSTR(MP_QSTR_PI10), MP_ROM_PTR(&pin_PI10) },
-  { MP_ROM_QSTR(MP_QSTR_PI06), MP_ROM_PTR(&pin_PI06) },
-  { MP_ROM_QSTR(MP_QSTR_PK04), MP_ROM_PTR(&pin_PK04) },
-  { MP_ROM_QSTR(MP_QSTR_PK03), MP_ROM_PTR(&pin_PK03) },
-  { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) },
-  { MP_ROM_QSTR(MP_QSTR_PJ15), MP_ROM_PTR(&pin_PJ15) },
-  { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
-  { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
-  { MP_ROM_QSTR(MP_QSTR_PH15), MP_ROM_PTR(&pin_PH15) },
-  { MP_ROM_QSTR(MP_QSTR_PI01), MP_ROM_PTR(&pin_PI01) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) },
+    { MP_ROM_QSTR(MP_QSTR_PI05), MP_ROM_PTR(&pin_PI05) },
+    { MP_ROM_QSTR(MP_QSTR_PI07), MP_ROM_PTR(&pin_PI07) },
+    { MP_ROM_QSTR(MP_QSTR_PI10), MP_ROM_PTR(&pin_PI10) },
+    { MP_ROM_QSTR(MP_QSTR_PI06), MP_ROM_PTR(&pin_PI06) },
+    { MP_ROM_QSTR(MP_QSTR_PK04), MP_ROM_PTR(&pin_PK04) },
+    { MP_ROM_QSTR(MP_QSTR_PK03), MP_ROM_PTR(&pin_PK03) },
+    { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) },
+    { MP_ROM_QSTR(MP_QSTR_PJ15), MP_ROM_PTR(&pin_PJ15) },
+    { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_PH15), MP_ROM_PTR(&pin_PH15) },
+    { MP_ROM_QSTR(MP_QSTR_PI01), MP_ROM_PTR(&pin_PI01) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
 
 // Row E
-  // { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) }, // OSC32_IN
-  { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) },
-  { MP_ROM_QSTR(MP_QSTR_PI12), MP_ROM_PTR(&pin_PI12) },
-  { MP_ROM_QSTR(MP_QSTR_PI09), MP_ROM_PTR(&pin_PI09) },
-  { MP_ROM_QSTR(MP_QSTR_PH13), MP_ROM_PTR(&pin_PH13) },
-  { MP_ROM_QSTR(MP_QSTR_PH14), MP_ROM_PTR(&pin_PH14) },
-  { MP_ROM_QSTR(MP_QSTR_PI00), MP_ROM_PTR(&pin_PI00) },
-  { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
+    // { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) }, // OSC32_IN
+    { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) },
+    { MP_ROM_QSTR(MP_QSTR_PI12), MP_ROM_PTR(&pin_PI12) },
+    { MP_ROM_QSTR(MP_QSTR_PI09), MP_ROM_PTR(&pin_PI09) },
+    { MP_ROM_QSTR(MP_QSTR_PH13), MP_ROM_PTR(&pin_PH13) },
+    { MP_ROM_QSTR(MP_QSTR_PH14), MP_ROM_PTR(&pin_PH14) },
+    { MP_ROM_QSTR(MP_QSTR_PI00), MP_ROM_PTR(&pin_PI00) },
+    { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
 
 // Row F
-  // { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) }, // OSC32_OUT
-  { MP_ROM_QSTR(MP_QSTR_PK01), MP_ROM_PTR(&pin_PK01) },
-  { MP_ROM_QSTR(MP_QSTR_PK02), MP_ROM_PTR(&pin_PK02) },
-  { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    // { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) }, // OSC32_OUT
+    { MP_ROM_QSTR(MP_QSTR_PK01), MP_ROM_PTR(&pin_PK01) },
+    { MP_ROM_QSTR(MP_QSTR_PK02), MP_ROM_PTR(&pin_PK02) },
+    { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
 
 // Row G
-  // { MP_ROM_QSTR(MP_QSTR_PH00), MP_ROM_PTR(&pin_PH00) }, // OSC_IN
-  { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) },
-  { MP_ROM_QSTR(MP_QSTR_PI13), MP_ROM_PTR(&pin_PI13) },
-  { MP_ROM_QSTR(MP_QSTR_PI15), MP_ROM_PTR(&pin_PI15) },
-  { MP_ROM_QSTR(MP_QSTR_PJ11), MP_ROM_PTR(&pin_PJ11) },
-  { MP_ROM_QSTR(MP_QSTR_PK00), MP_ROM_PTR(&pin_PK00) },
-  { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
-  { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
+    // { MP_ROM_QSTR(MP_QSTR_PH00), MP_ROM_PTR(&pin_PH00) }, // OSC_IN
+    { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) },
+    { MP_ROM_QSTR(MP_QSTR_PI13), MP_ROM_PTR(&pin_PI13) },
+    { MP_ROM_QSTR(MP_QSTR_PI15), MP_ROM_PTR(&pin_PI15) },
+    { MP_ROM_QSTR(MP_QSTR_PJ11), MP_ROM_PTR(&pin_PJ11) },
+    { MP_ROM_QSTR(MP_QSTR_PK00), MP_ROM_PTR(&pin_PK00) },
+    { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
 
 // Row H
-  // { MP_ROM_QSTR(MP_QSTR_PH01), MP_ROM_PTR(&pin_PH01) }, // OSC_OUT
-  { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) },
-  { MP_ROM_QSTR(MP_QSTR_PI14), MP_ROM_PTR(&pin_PI14) },
-  { MP_ROM_QSTR(MP_QSTR_PH04), MP_ROM_PTR(&pin_PH04) },
-  { MP_ROM_QSTR(MP_QSTR_PJ08), MP_ROM_PTR(&pin_PJ08) },
-  { MP_ROM_QSTR(MP_QSTR_PJ10), MP_ROM_PTR(&pin_PJ10) },
-  { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) },
-  { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
+    // { MP_ROM_QSTR(MP_QSTR_PH01), MP_ROM_PTR(&pin_PH01) }, // OSC_OUT
+    { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) },
+    { MP_ROM_QSTR(MP_QSTR_PI14), MP_ROM_PTR(&pin_PI14) },
+    { MP_ROM_QSTR(MP_QSTR_PH04), MP_ROM_PTR(&pin_PH04) },
+    { MP_ROM_QSTR(MP_QSTR_PJ08), MP_ROM_PTR(&pin_PJ08) },
+    { MP_ROM_QSTR(MP_QSTR_PJ10), MP_ROM_PTR(&pin_PJ10) },
+    { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) },
+    { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
 
 // Row J
-  { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) },
-  { MP_ROM_QSTR(MP_QSTR_PH05), MP_ROM_PTR(&pin_PH05) },
-  { MP_ROM_QSTR(MP_QSTR_PH03), MP_ROM_PTR(&pin_PH03) },
-  { MP_ROM_QSTR(MP_QSTR_PJ07), MP_ROM_PTR(&pin_PJ07) },
-  { MP_ROM_QSTR(MP_QSTR_PJ09), MP_ROM_PTR(&pin_PJ09) },
-  { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) },
-  { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) },
+    { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) },
+    { MP_ROM_QSTR(MP_QSTR_PH05), MP_ROM_PTR(&pin_PH05) },
+    { MP_ROM_QSTR(MP_QSTR_PH03), MP_ROM_PTR(&pin_PH03) },
+    { MP_ROM_QSTR(MP_QSTR_PJ07), MP_ROM_PTR(&pin_PJ07) },
+    { MP_ROM_QSTR(MP_QSTR_PJ09), MP_ROM_PTR(&pin_PJ09) },
+    { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) },
+    { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) },
 
 // Row K
-  { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) },
-  { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) },
-  { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) },
-  { MP_ROM_QSTR(MP_QSTR_PH02), MP_ROM_PTR(&pin_PH02) },
-  { MP_ROM_QSTR(MP_QSTR_PJ06), MP_ROM_PTR(&pin_PJ06) },
-  { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
+    { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) },
+    { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) },
+    { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) },
+    { MP_ROM_QSTR(MP_QSTR_PH02), MP_ROM_PTR(&pin_PH02) },
+    { MP_ROM_QSTR(MP_QSTR_PJ06), MP_ROM_PTR(&pin_PJ06) },
+    { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
 
 // Row L
-  { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) },
-  { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) },
-  { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) },
-  { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
-  { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
-  { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
+    { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) },
+    { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) },
+    { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) },
+    { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
+    { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
 
 // Row M
-  { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
-  { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
-  { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
-  { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) },
-  { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) },
-  { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) },
-  { MP_ROM_QSTR(MP_QSTR_PJ04), MP_ROM_PTR(&pin_PJ04) },
-  { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
-  { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
-  { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) },
-  { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) },
-  { MP_ROM_QSTR(MP_QSTR_PJ05), MP_ROM_PTR(&pin_PJ05) },
-  { MP_ROM_QSTR(MP_QSTR_PH12), MP_ROM_PTR(&pin_PH12) },
+    { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
+    { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) },
+    { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) },
+    { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) },
+    { MP_ROM_QSTR(MP_QSTR_PJ04), MP_ROM_PTR(&pin_PJ04) },
+    { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) },
+    { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) },
+    { MP_ROM_QSTR(MP_QSTR_PJ05), MP_ROM_PTR(&pin_PJ05) },
+    { MP_ROM_QSTR(MP_QSTR_PH12), MP_ROM_PTR(&pin_PH12) },
 
 // Row N
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
-  { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) },
-  { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) },
-  { MP_ROM_QSTR(MP_QSTR_PJ03), MP_ROM_PTR(&pin_PJ03) },
-  { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
-  { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
-  { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) },
-  { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) },
-  { MP_ROM_QSTR(MP_QSTR_PH07), MP_ROM_PTR(&pin_PH07) },
-  { MP_ROM_QSTR(MP_QSTR_PH09), MP_ROM_PTR(&pin_PH09) },
-  { MP_ROM_QSTR(MP_QSTR_PH11), MP_ROM_PTR(&pin_PH11) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
+    { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) },
+    { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) },
+    { MP_ROM_QSTR(MP_QSTR_PJ03), MP_ROM_PTR(&pin_PJ03) },
+    { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
+    { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) },
+    { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) },
+    { MP_ROM_QSTR(MP_QSTR_PH07), MP_ROM_PTR(&pin_PH07) },
+    { MP_ROM_QSTR(MP_QSTR_PH09), MP_ROM_PTR(&pin_PH09) },
+    { MP_ROM_QSTR(MP_QSTR_PH11), MP_ROM_PTR(&pin_PH11) },
 
 // Row P
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
-  { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) },
-  { MP_ROM_QSTR(MP_QSTR_PJ02), MP_ROM_PTR(&pin_PJ02) },
-  { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) },
-  { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
-  { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
-  { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-  { MP_ROM_QSTR(MP_QSTR_PH06), MP_ROM_PTR(&pin_PH06) },
-  { MP_ROM_QSTR(MP_QSTR_PH08), MP_ROM_PTR(&pin_PH08) },
-  { MP_ROM_QSTR(MP_QSTR_PH10), MP_ROM_PTR(&pin_PH10) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) },
+    { MP_ROM_QSTR(MP_QSTR_PJ02), MP_ROM_PTR(&pin_PJ02) },
+    { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) },
+    { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_PH06), MP_ROM_PTR(&pin_PH06) },
+    { MP_ROM_QSTR(MP_QSTR_PH08), MP_ROM_PTR(&pin_PH08) },
+    { MP_ROM_QSTR(MP_QSTR_PH10), MP_ROM_PTR(&pin_PH10) },
 
 // Row R
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PJ00), MP_ROM_PTR(&pin_PJ00) },
-  { MP_ROM_QSTR(MP_QSTR_PJ01), MP_ROM_PTR(&pin_PJ01) },
-  { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
-  { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
-  { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
-  { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
-  { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
-  { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PJ00), MP_ROM_PTR(&pin_PJ00) },
+    { MP_ROM_QSTR(MP_QSTR_PJ01), MP_ROM_PTR(&pin_PJ01) },
+    { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
 
 };
 MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
diff --git a/ports/stm/packages/UFQFPN48.c b/ports/stm/packages/UFQFPN48.c
index 5304482ec..b45fc9c98 100644
--- a/ports/stm/packages/UFQFPN48.c
+++ b/ports/stm/packages/UFQFPN48.c
@@ -4,60 +4,60 @@
 
 STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = {
 // Pins 1-12
-  /* VBAT -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
-  // PC14 OSC32_IN ----------------------------------*/
-  // PC15 OSC32_OUT ---------------------------------*/
-  // PH0 OSC_IN -------------------------------------*/
-  // PH1 OSC_OUT ------------------------------------*/
-  // NRST -------------------------------------------*/
-  // VSSA -------------------------------------------*/
-  // VDDA -------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
-  { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
-  { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
+    /* VBAT -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
+    // PC14 OSC32_IN ----------------------------------*/
+    // PC15 OSC32_OUT ---------------------------------*/
+    // PH0 OSC_IN -------------------------------------*/
+    // PH1 OSC_OUT ------------------------------------*/
+    // NRST -------------------------------------------*/
+    // VSSA -------------------------------------------*/
+    // VDDA -------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
+    { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
 
 // Pins 13-24
-  { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
-  { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
-  { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
-  { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
-  { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
-  { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
-  { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
-  { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
-  { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
-  // VCAP1 ------------------------------------------*/
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
+    // VCAP1 ------------------------------------------*/
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 25-36
-  { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
-  { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
-  { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
-  { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
-  { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
-  { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
-  { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
-  { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
-  { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
-  { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 // Pins 37-48
-  { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
-  { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
-  { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
-  { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
-  { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
-  { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
-  { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
-  // BOOT0 ------------------------------------------*/
-  { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
-  { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
-  // VSS --------------------------------------------*/
-  // VDD --------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
+    // BOOT0 ------------------------------------------*/
+    { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
+    // VSS --------------------------------------------*/
+    // VDD --------------------------------------------*/
 
 };
 MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);
diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h
index 34089c849..488541d09 100644
--- a/ports/stm/peripherals/periph.h
+++ b/ports/stm/peripherals/periph.h
@@ -36,34 +36,34 @@
 // Comm Peripherals
 
 typedef struct {
-    uint8_t periph_index:4;     // Index of the peripheral instance
-    uint8_t altfn_index:4;      // Index of the altfn for this pin (0 to 15)
-    const mcu_pin_obj_t * pin;  // Pin Object
+    uint8_t periph_index : 4;     // Index of the peripheral instance
+    uint8_t altfn_index : 4;      // Index of the altfn for this pin (0 to 15)
+    const mcu_pin_obj_t *pin;   // Pin Object
 } mcu_periph_obj_t;
 
 #define PERIPH(index, alt, p_pin)       \
-{ \
-    .periph_index = index, \
-    .altfn_index = alt, \
-    .pin = p_pin, \
-}
+    { \
+        .periph_index = index, \
+        .altfn_index = alt, \
+        .pin = p_pin, \
+    }
 
 // Timer Peripheral
 
 typedef struct {
-    uint8_t tim_index:4;
-    uint8_t altfn_index:4;
-    uint8_t channel_index:4;
-    const mcu_pin_obj_t * pin;
+    uint8_t tim_index : 4;
+    uint8_t altfn_index : 4;
+    uint8_t channel_index : 4;
+    const mcu_pin_obj_t *pin;
 } mcu_tim_pin_obj_t;
 
 #define TIM(index, alt, channel, tim_pin)       \
-{ \
-    .tim_index = index, \
-    .altfn_index = alt, \
-    .channel_index = channel, \
-    .pin = tim_pin, \
-}
+    { \
+        .tim_index = index, \
+        .altfn_index = alt, \
+        .channel_index = channel, \
+        .pin = tim_pin, \
+    }
 
 // F4 Series
 // Access Lines
diff --git a/ports/stm/peripherals/pins.h b/ports/stm/peripherals/pins.h
index 358313f56..4a516864b 100644
--- a/ports/stm/peripherals/pins.h
+++ b/ports/stm/peripherals/pins.h
@@ -37,21 +37,21 @@
 
 typedef struct {
     mp_obj_base_t base;
-    uint8_t port:4;
-    uint8_t number:4;
-    uint8_t adc_unit:3;
-    uint8_t adc_channel:5;
+    uint8_t port : 4;
+    uint8_t number : 4;
+    uint8_t adc_unit : 3;
+    uint8_t adc_channel : 5;
 } mcu_pin_obj_t;
 
-//Standard stm32 adc unit combinations
+// Standard stm32 adc unit combinations
 #define ADC_1   1
 #define ADC_12  3
 #define ADC_123 7
 #define ADC_3   4
 
-//STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin,
-//but all 3 ADCs will share the same input number per pin.
-//F4 family has 3 ADC max, 24 channels max.
+// STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin,
+// but all 3 ADCs will share the same input number per pin.
+// F4 family has 3 ADC max, 24 channels max.
 #define ADC_INPUT(mask, number) \
     .adc_unit = mask, \
     .adc_channel = number,
@@ -65,12 +65,12 @@ extern const mp_obj_type_t mcu_pin_type;
 // STM32 can have up to 9 ports, each restricted to 16 pins
 // We split the pin/port evenly, in contrast to nrf.
 #define PIN(p_port, p_number, p_adc)       \
-{ \
-    { &mcu_pin_type }, \
-    .port = p_port, \
-    .number = p_number, \
-    p_adc \
-}
+    { \
+        { &mcu_pin_type }, \
+        .port = p_port, \
+        .number = p_number, \
+        p_adc \
+    }
 
 // Use illegal pin value to mark unassigned pins.
 #define NO_PIN 0xff
diff --git a/ports/stm/peripherals/stm32f4/clocks.c b/ports/stm/peripherals/stm32f4/clocks.c
index c2d0a452a..a98b38946 100644
--- a/ports/stm/peripherals/stm32f4/clocks.c
+++ b/ports/stm/peripherals/stm32f4/clocks.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the Micro Python project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -66,7 +66,7 @@ void stm32_peripherals_clocks_init(void) {
     RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE;
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-    RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
+    RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000;
     RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN;
     RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP;
     RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ;
@@ -74,10 +74,12 @@ void stm32_peripherals_clocks_init(void) {
     RCC_OscInitStruct.PLL.PLLR = 2; // Unused but required by HAL
     #endif
 
-    if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         // Clock issues are too problematic to even attempt recovery.
         // If you end up here, check whether your LSE settings match your board.
-        while(1);
+        while (1) {
+            ;
+        }
     }
 
     // Configure bus clock sources and divisors
@@ -98,7 +100,7 @@ void stm32_peripherals_clocks_init(void) {
     #endif
     #if (CPY_CLK_USB_USES_AUDIOPLL)
     // Not supported by all lines. Should always result in 48M.
-    PeriphClkInitStruct.PLLI2S.PLLI2SM = HSE_VALUE/1000000;
+    PeriphClkInitStruct.PLLI2S.PLLI2SM = HSE_VALUE / 1000000;
     PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
     PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
     PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_CK48;
diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h
index d157d944a..72efe82eb 100644
--- a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h
+++ b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the Micro Python project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c b/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c
index d10fcbb6f..86634cf6c 100644
--- a/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c
@@ -36,9 +36,9 @@ void stm32_peripherals_gpio_init(void) {
     __HAL_RCC_GPIOE_CLK_ENABLE();
     __HAL_RCC_GPIOH_CLK_ENABLE();
 
-    //Never reset pins
-    never_reset_pin_number(2,14); //PC14 OSC32_IN
-    never_reset_pin_number(2,15); //PC15 OSC32_OUT
-    never_reset_pin_number(0,13); //PA13 SWDIO
-    never_reset_pin_number(0,14); //PA14 SWCLK
+    // Never reset pins
+    never_reset_pin_number(2,14); // PC14 OSC32_IN
+    never_reset_pin_number(2,15); // PC15 OSC32_OUT
+    never_reset_pin_number(0,13); // PA13 SWDIO
+    never_reset_pin_number(0,14); // PA14 SWCLK
 }
diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c
index 868945ecc..23664999b 100644
--- a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c
+++ b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -31,7 +31,7 @@
 
 // I2C
 
-I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3};
+I2C_TypeDef *mcu_i2c_banks[3] = {I2C1, I2C2, I2C3};
 
 const mcu_periph_obj_t mcu_i2c_sda_list[5] = {
     PERIPH(1, 4, &pin_PB07),
@@ -50,7 +50,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[4] = {
 
 // SPI
 
-SPI_TypeDef * mcu_spi_banks[4] = {SPI1, SPI2, SPI3, SPI4};
+SPI_TypeDef *mcu_spi_banks[4] = {SPI1, SPI2, SPI3, SPI4};
 
 const mcu_periph_obj_t mcu_spi_sck_list[9] = {
     PERIPH(1, 5, &pin_PA05),
@@ -99,7 +99,7 @@ const mcu_periph_obj_t mcu_spi_nss_list[9] = {
     PERIPH(4, 5, &pin_PE11),
 };
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6};
+USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6};
 bool mcu_uart_has_usart[MAX_UART] = {true, true, false, false, false, true};
 
 const mcu_periph_obj_t mcu_uart_tx_list[6] = {
@@ -120,12 +120,12 @@ const mcu_periph_obj_t mcu_uart_rx_list[6] = {
     PERIPH(2, 7, &pin_PD06),
 };
 
-//Timers
-//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, TIM10,
-                                    TIM11, NULL, NULL, NULL};
+// Timers
+// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
+TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, TIM10,
+                                  TIM11, NULL, NULL, NULL};
 
-//#define TIM(index, alt, channel, tim_pin)
+// #define TIM(index, alt, channel, tim_pin)
 const mcu_tim_pin_obj_t mcu_tim_pin_list[44] = {
     TIM(2,1,1,&pin_PA00),
     TIM(5,2,1,&pin_PA00),
diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h
index c38e9ea98..9bc47b8bf 100644
--- a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h
+++ b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h
@@ -27,31 +27,31 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H
 
-//I2C
-extern I2C_TypeDef * mcu_i2c_banks[3];
+// I2C
+extern I2C_TypeDef *mcu_i2c_banks[3];
 
 extern const mcu_periph_obj_t mcu_i2c_sda_list[5];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[4];
 
-//SPI
-extern SPI_TypeDef * mcu_spi_banks[4];
+// SPI
+extern SPI_TypeDef *mcu_spi_banks[4];
 
 extern const mcu_periph_obj_t mcu_spi_sck_list[9];
 extern const mcu_periph_obj_t mcu_spi_mosi_list[9];
 extern const mcu_periph_obj_t mcu_spi_miso_list[8];
 extern const mcu_periph_obj_t mcu_spi_nss_list[9];
 
-//UART
-extern USART_TypeDef * mcu_uart_banks[MAX_UART];
+// UART
+extern USART_TypeDef *mcu_uart_banks[MAX_UART];
 extern bool mcu_uart_has_usart[MAX_UART];
 
 extern const mcu_periph_obj_t mcu_uart_tx_list[6];
 extern const mcu_periph_obj_t mcu_uart_rx_list[6];
 
-//Timers
+// Timers
 #define TIM_BANK_ARRAY_LEN 14
 #define TIM_PIN_ARRAY_LEN 44
-extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
+extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN];
 extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN];
 
 #endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H
diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c
index ed89f0de6..a155970bb 100644
--- a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c
+++ b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -34,9 +34,9 @@ const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC);
 const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC);
 const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC);
 
-const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp
-const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN
-const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT
+const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); // anti-tamp
+const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); // OSC32_IN
+const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); // OSC32_OUT
 
 const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10));
 const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11));
@@ -94,9 +94,9 @@ const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC);
 const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC);
 const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC);
 const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC);
-const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); //SWDIO
-const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); //SWCLK
-const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); //JTDI
+const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); // SWDIO
+const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); // SWCLK
+const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); // JTDI
 
 const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC);
 const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC);
diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h
index c836df69a..ef804ba09 100644
--- a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h
+++ b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h
@@ -27,13 +27,13 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PINS_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PINS_H
 
-//Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only
-//pg 38
+// Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only
+// pg 38
 extern const mcu_pin_obj_t pin_PE02;
 extern const mcu_pin_obj_t pin_PE03;
 extern const mcu_pin_obj_t pin_PE04;
 extern const mcu_pin_obj_t pin_PE05;
-//pg 39
+// pg 39
 extern const mcu_pin_obj_t pin_PE06;
 extern const mcu_pin_obj_t pin_PC13;
 extern const mcu_pin_obj_t pin_PC14;
@@ -42,7 +42,7 @@ extern const mcu_pin_obj_t pin_PC00;
 extern const mcu_pin_obj_t pin_PC01;
 extern const mcu_pin_obj_t pin_PC02;
 extern const mcu_pin_obj_t pin_PC03;
-//pg 40
+// pg 40
 extern const mcu_pin_obj_t pin_PA00;
 extern const mcu_pin_obj_t pin_PA01;
 extern const mcu_pin_obj_t pin_PA02;
@@ -51,7 +51,7 @@ extern const mcu_pin_obj_t pin_PA04;
 extern const mcu_pin_obj_t pin_PA05;
 extern const mcu_pin_obj_t pin_PA06;
 extern const mcu_pin_obj_t pin_PA07;
-//pg 41
+// pg 41
 extern const mcu_pin_obj_t pin_PC04;
 extern const mcu_pin_obj_t pin_PC05;
 extern const mcu_pin_obj_t pin_PB00;
@@ -66,7 +66,7 @@ extern const mcu_pin_obj_t pin_PE12;
 extern const mcu_pin_obj_t pin_PE13;
 extern const mcu_pin_obj_t pin_PE14;
 extern const mcu_pin_obj_t pin_PE15;
-//pg 42
+// pg 42
 extern const mcu_pin_obj_t pin_PB10;
 extern const mcu_pin_obj_t pin_PB12;
 extern const mcu_pin_obj_t pin_PB13;
@@ -77,7 +77,7 @@ extern const mcu_pin_obj_t pin_PD09;
 extern const mcu_pin_obj_t pin_PD10;
 extern const mcu_pin_obj_t pin_PD11;
 extern const mcu_pin_obj_t pin_PD12;
-//pg 43
+// pg 43
 extern const mcu_pin_obj_t pin_PD13;
 extern const mcu_pin_obj_t pin_PD14;
 extern const mcu_pin_obj_t pin_PD15;
@@ -87,7 +87,7 @@ extern const mcu_pin_obj_t pin_PC08;
 extern const mcu_pin_obj_t pin_PC09;
 extern const mcu_pin_obj_t pin_PA08;
 extern const mcu_pin_obj_t pin_PA09;
-//pg 44
+// pg 44
 extern const mcu_pin_obj_t pin_PA10;
 extern const mcu_pin_obj_t pin_PA11;
 extern const mcu_pin_obj_t pin_PA12;
@@ -97,7 +97,7 @@ extern const mcu_pin_obj_t pin_PA15;
 extern const mcu_pin_obj_t pin_PC10;
 extern const mcu_pin_obj_t pin_PC11;
 extern const mcu_pin_obj_t pin_PC12;
-//pg 45
+// pg 45
 extern const mcu_pin_obj_t pin_PD00;
 extern const mcu_pin_obj_t pin_PD01;
 extern const mcu_pin_obj_t pin_PD02;
@@ -110,7 +110,7 @@ extern const mcu_pin_obj_t pin_PB03;
 extern const mcu_pin_obj_t pin_PB04;
 extern const mcu_pin_obj_t pin_PB05;
 extern const mcu_pin_obj_t pin_PB06;
-//pg 46
+// pg 46
 extern const mcu_pin_obj_t pin_PB07;
 extern const mcu_pin_obj_t pin_PB08;
 extern const mcu_pin_obj_t pin_PB09;
diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h
index 87faec035..4239e3318 100644
--- a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h
+++ b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the Micro Python project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c
index 03fba6289..385766623 100644
--- a/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c
@@ -28,7 +28,7 @@
 #include "common-hal/microcontroller/Pin.h"
 
 void stm32_peripherals_gpio_init(void) {
-    //Enable all GPIO for now
+    // Enable all GPIO for now
     __HAL_RCC_GPIOA_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
     __HAL_RCC_GPIOC_CLK_ENABLE();
@@ -37,12 +37,12 @@ void stm32_peripherals_gpio_init(void) {
     __HAL_RCC_GPIOF_CLK_ENABLE();
     __HAL_RCC_GPIOG_CLK_ENABLE();
 
-    //Never reset pins
-    never_reset_pin_number(2,13); //PC13 anti tamp
-    never_reset_pin_number(2,14); //PC14 OSC32_IN
-    never_reset_pin_number(2,15); //PC15 OSC32_OUT
-    never_reset_pin_number(0,13); //PA13 SWDIO
-    never_reset_pin_number(0,14); //PA14 SWCLK
+    // Never reset pins
+    never_reset_pin_number(2,13); // PC13 anti tamp
+    never_reset_pin_number(2,14); // PC14 OSC32_IN
+    never_reset_pin_number(2,15); // PC15 OSC32_OUT
+    never_reset_pin_number(0,13); // PA13 SWDIO
+    never_reset_pin_number(0,14); // PA14 SWCLK
     // never_reset_pin_number(0,15); //PA15 JTDI
     // never_reset_pin_number(1,3); //PB3 JTDO
     // never_reset_pin_number(1,4); //PB4 JTRST
diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c
index 2f9accbf1..451e4220c 100644
--- a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c
+++ b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -29,7 +29,7 @@
 #include "peripherals/pins.h"
 #include "peripherals/periph.h"
 
-I2C_TypeDef * mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3};
+I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3};
 
 const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN] = {
     PERIPH(1, 4, &pin_PB07),
@@ -50,7 +50,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN] = {
     PERIPH(3, 4, &pin_PH07),
 };
 
-SPI_TypeDef * mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3};
+SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3};
 
 const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN] = {
     PERIPH(1, 5, &pin_PA05),
@@ -88,7 +88,7 @@ const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN] = {
     PERIPH(3, 6, &pin_PA15),
 };
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6};
+USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6};
 bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true};
 
 const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN] = {
@@ -120,10 +120,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN] = {
     PERIPH(6, 8, &pin_PG09),
 };
 
-//Timers
-//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
-                                    TIM11, TIM12, TIM13, TIM14};
+// Timers
+// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
+TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
+                                                  TIM11, TIM12, TIM13, TIM14};
 
 const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = {
     TIM(2, 1, 1, &pin_PA00),
@@ -195,8 +195,8 @@ const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = {
     TIM(8, 3, 3, &pin_PI07),
 };
 
-//SDIO
-SDIO_TypeDef * mcu_sdio_banks[1] = {SDIO};
+// SDIO
+SDIO_TypeDef *mcu_sdio_banks[1] = {SDIO};
 
 const mcu_periph_obj_t mcu_sdio_clock_list[1] = {
     PERIPH(1, 12, &pin_PC12),
@@ -217,8 +217,8 @@ const mcu_periph_obj_t mcu_sdio_data3_list[1] = {
     PERIPH(1, 12, &pin_PC11),
 };
 
-//CAN
-CAN_TypeDef * mcu_can_banks[2] = {CAN1, CAN2};
+// CAN
+CAN_TypeDef *mcu_can_banks[2] = {CAN1, CAN2};
 
 const mcu_periph_obj_t mcu_can_tx_list[6] = {
     PERIPH(1, 9, &pin_PA11),
diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h
index 03198af55..d5433f995 100644
--- a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h
+++ b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h
@@ -27,42 +27,42 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H
 
-//I2C
+// I2C
 #define I2C_BANK_ARRAY_LEN 3
 #define I2C_SDA_ARRAY_LEN 7
 #define I2C_SCL_ARRAY_LEN 7
-extern I2C_TypeDef * mcu_i2c_banks[I2C_BANK_ARRAY_LEN];
+extern I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN];
 
-//SPI
+// SPI
 #define SPI_BANK_ARRAY_LEN 3
 #define SPI_SCK_ARRAY_LEN 7
 #define SPI_MOSI_ARRAY_LEN 7
 #define SPI_MISO_ARRAY_LEN 7
 #define SPI_NSS_ARRAY_LEN 6
-extern SPI_TypeDef * mcu_spi_banks[SPI_BANK_ARRAY_LEN];
+extern SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_spi_mosi_list[SPI_MOSI_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_spi_miso_list[SPI_MISO_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN];
 
-//UART
+// UART
 #define UART_TX_ARRAY_LEN 12
 #define UART_RX_ARRAY_LEN 12
-extern USART_TypeDef * mcu_uart_banks[MAX_UART];
+extern USART_TypeDef *mcu_uart_banks[MAX_UART];
 extern bool mcu_uart_has_usart[MAX_UART];
 extern const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN];
 
-//Timers
+// Timers
 #define TIM_BANK_ARRAY_LEN 14
 #define TIM_PIN_ARRAY_LEN 67
-extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
+extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN];
 extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN];
 
-//SDIO
-extern SDIO_TypeDef * mcu_sdio_banks[1];
+// SDIO
+extern SDIO_TypeDef *mcu_sdio_banks[1];
 
 extern const mcu_periph_obj_t mcu_sdio_clock_list[1];
 extern const mcu_periph_obj_t mcu_sdio_command_list[1];
@@ -72,7 +72,7 @@ extern const mcu_periph_obj_t mcu_sdio_data2_list[1];
 extern const mcu_periph_obj_t mcu_sdio_data3_list[1];
 
 // CAN
-extern CAN_TypeDef * mcu_can_banks[2];
+extern CAN_TypeDef *mcu_can_banks[2];
 
 extern const mcu_periph_obj_t mcu_can_tx_list[6];
 extern const mcu_periph_obj_t mcu_can_rx_list[6];
diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c
index 62acb1955..9fef433ea 100644
--- a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c
+++ b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h
index 5894b4ae8..28d48e5c1 100644
--- a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h
+++ b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the Micro Python project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c
index 03fba6289..385766623 100644
--- a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c
@@ -28,7 +28,7 @@
 #include "common-hal/microcontroller/Pin.h"
 
 void stm32_peripherals_gpio_init(void) {
-    //Enable all GPIO for now
+    // Enable all GPIO for now
     __HAL_RCC_GPIOA_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
     __HAL_RCC_GPIOC_CLK_ENABLE();
@@ -37,12 +37,12 @@ void stm32_peripherals_gpio_init(void) {
     __HAL_RCC_GPIOF_CLK_ENABLE();
     __HAL_RCC_GPIOG_CLK_ENABLE();
 
-    //Never reset pins
-    never_reset_pin_number(2,13); //PC13 anti tamp
-    never_reset_pin_number(2,14); //PC14 OSC32_IN
-    never_reset_pin_number(2,15); //PC15 OSC32_OUT
-    never_reset_pin_number(0,13); //PA13 SWDIO
-    never_reset_pin_number(0,14); //PA14 SWCLK
+    // Never reset pins
+    never_reset_pin_number(2,13); // PC13 anti tamp
+    never_reset_pin_number(2,14); // PC14 OSC32_IN
+    never_reset_pin_number(2,15); // PC15 OSC32_OUT
+    never_reset_pin_number(0,13); // PA13 SWDIO
+    never_reset_pin_number(0,14); // PA14 SWCLK
     // never_reset_pin_number(0,15); //PA15 JTDI
     // never_reset_pin_number(1,3); //PB3 JTDO
     // never_reset_pin_number(1,4); //PB4 JTRST
diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c
index 2f9accbf1..451e4220c 100644
--- a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c
+++ b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -29,7 +29,7 @@
 #include "peripherals/pins.h"
 #include "peripherals/periph.h"
 
-I2C_TypeDef * mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3};
+I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3};
 
 const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN] = {
     PERIPH(1, 4, &pin_PB07),
@@ -50,7 +50,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN] = {
     PERIPH(3, 4, &pin_PH07),
 };
 
-SPI_TypeDef * mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3};
+SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3};
 
 const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN] = {
     PERIPH(1, 5, &pin_PA05),
@@ -88,7 +88,7 @@ const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN] = {
     PERIPH(3, 6, &pin_PA15),
 };
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6};
+USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6};
 bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true};
 
 const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN] = {
@@ -120,10 +120,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN] = {
     PERIPH(6, 8, &pin_PG09),
 };
 
-//Timers
-//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
-                                    TIM11, TIM12, TIM13, TIM14};
+// Timers
+// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
+TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
+                                                  TIM11, TIM12, TIM13, TIM14};
 
 const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = {
     TIM(2, 1, 1, &pin_PA00),
@@ -195,8 +195,8 @@ const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = {
     TIM(8, 3, 3, &pin_PI07),
 };
 
-//SDIO
-SDIO_TypeDef * mcu_sdio_banks[1] = {SDIO};
+// SDIO
+SDIO_TypeDef *mcu_sdio_banks[1] = {SDIO};
 
 const mcu_periph_obj_t mcu_sdio_clock_list[1] = {
     PERIPH(1, 12, &pin_PC12),
@@ -217,8 +217,8 @@ const mcu_periph_obj_t mcu_sdio_data3_list[1] = {
     PERIPH(1, 12, &pin_PC11),
 };
 
-//CAN
-CAN_TypeDef * mcu_can_banks[2] = {CAN1, CAN2};
+// CAN
+CAN_TypeDef *mcu_can_banks[2] = {CAN1, CAN2};
 
 const mcu_periph_obj_t mcu_can_tx_list[6] = {
     PERIPH(1, 9, &pin_PA11),
diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h
index e6d4526b6..481a8376d 100644
--- a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h
+++ b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h
@@ -27,42 +27,42 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H
 
-//I2C
+// I2C
 #define I2C_BANK_ARRAY_LEN 3
 #define I2C_SDA_ARRAY_LEN 7
 #define I2C_SCL_ARRAY_LEN 7
-extern I2C_TypeDef * mcu_i2c_banks[I2C_BANK_ARRAY_LEN];
+extern I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN];
 
-//SPI
+// SPI
 #define SPI_BANK_ARRAY_LEN 3
 #define SPI_SCK_ARRAY_LEN 7
 #define SPI_MOSI_ARRAY_LEN 7
 #define SPI_MISO_ARRAY_LEN 7
 #define SPI_NSS_ARRAY_LEN 6
-extern SPI_TypeDef * mcu_spi_banks[SPI_BANK_ARRAY_LEN];
+extern SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_spi_mosi_list[SPI_MOSI_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_spi_miso_list[SPI_MISO_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN];
 
-//UART
+// UART
 #define UART_TX_ARRAY_LEN 12
 #define UART_RX_ARRAY_LEN 12
-extern USART_TypeDef * mcu_uart_banks[MAX_UART];
+extern USART_TypeDef *mcu_uart_banks[MAX_UART];
 extern bool mcu_uart_has_usart[MAX_UART];
 extern const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN];
 extern const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN];
 
-//Timers
+// Timers
 #define TIM_BANK_ARRAY_LEN 14
 #define TIM_PIN_ARRAY_LEN 67
-extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
+extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN];
 extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN];
 
-//SDIO
-extern SDIO_TypeDef * mcu_sdio_banks[1];
+// SDIO
+extern SDIO_TypeDef *mcu_sdio_banks[1];
 
 extern const mcu_periph_obj_t mcu_sdio_clock_list[1];
 extern const mcu_periph_obj_t mcu_sdio_command_list[1];
@@ -72,7 +72,7 @@ extern const mcu_periph_obj_t mcu_sdio_data2_list[1];
 extern const mcu_periph_obj_t mcu_sdio_data3_list[1];
 
 // CAN
-extern CAN_TypeDef * mcu_can_banks[2];
+extern CAN_TypeDef *mcu_can_banks[2];
 
 extern const mcu_periph_obj_t mcu_can_tx_list[6];
 extern const mcu_periph_obj_t mcu_can_rx_list[6];
diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c
index 62acb1955..9fef433ea 100644
--- a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c
+++ b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h
index a2fb7bd54..0b38d610c 100644
--- a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h
+++ b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the Micro Python project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c b/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c
index 08c6b55cd..351607a70 100644
--- a/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c
@@ -29,7 +29,7 @@
 #include "common-hal/microcontroller/Pin.h"
 
 void stm32_peripherals_gpio_init(void) {
-    //* GPIO Ports Clock Enable */
+    // * GPIO Ports Clock Enable */
     __HAL_RCC_GPIOE_CLK_ENABLE();
     __HAL_RCC_GPIOC_CLK_ENABLE();
     __HAL_RCC_GPIOH_CLK_ENABLE();
@@ -37,15 +37,15 @@ void stm32_peripherals_gpio_init(void) {
     __HAL_RCC_GPIOB_CLK_ENABLE();
     __HAL_RCC_GPIOD_CLK_ENABLE();
 
-    //Never reset pins
+    // Never reset pins
     // TODO: Move this out of peripherals. These helpers shouldn't reference anything CircuitPython
     // specific.
-    never_reset_pin_number(2,14); //PC14 OSC32_IN
-    never_reset_pin_number(2,15); //PC15 OSC32_OUT
+    never_reset_pin_number(2,14); // PC14 OSC32_IN
+    never_reset_pin_number(2,15); // PC15 OSC32_OUT
 
     #if !(BOARD_OVERWRITE_SWD)
-    never_reset_pin_number(0,13); //PA13 SWDIO
-    never_reset_pin_number(0,14); //PA14 SWCLK
+    never_reset_pin_number(0,13); // PA13 SWDIO
+    never_reset_pin_number(0,14); // PA14 SWCLK
     #endif
 
     // Port H is not included in GPIO port array
@@ -53,6 +53,6 @@ void stm32_peripherals_gpio_init(void) {
     // never_reset_pin_number(5,1); //PH1 JTRST
 }
 
-//LEDs are inverted on F411 DISCO
+// LEDs are inverted on F411 DISCO
 void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) {
 }
diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c
index 085663749..dd9cb3d84 100644
--- a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c
+++ b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -31,7 +31,7 @@
 
 // I2C
 
-I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3};
+I2C_TypeDef *mcu_i2c_banks[3] = {I2C1, I2C2, I2C3};
 
 const mcu_periph_obj_t mcu_i2c_sda_list[7] = {
     PERIPH(1, 4, &pin_PB07),
@@ -52,7 +52,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[4] = {
 
 // SPI
 
-SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5};
+SPI_TypeDef *mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5};
 
 const mcu_periph_obj_t mcu_spi_sck_list[15] = {
     PERIPH(1, 5, &pin_PA05),
@@ -119,7 +119,7 @@ const mcu_periph_obj_t mcu_spi_nss_list[12] = {
     PERIPH(5, 6, &pin_PE11)
 };
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6};
+USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6};
 bool mcu_uart_has_usart[MAX_UART] = {true, true, false, false, false, true};
 
 const mcu_periph_obj_t mcu_uart_tx_list[7] = {
@@ -142,10 +142,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[7] = {
     PERIPH(2, 7, &pin_PD06),
 };
 
-//Timers
-//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, TIM10,
-                                    TIM11, NULL, NULL, NULL};
+// Timers
+// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
+TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, TIM10,
+                                  TIM11, NULL, NULL, NULL};
 
 const mcu_tim_pin_obj_t mcu_tim_pin_list[44] = {
     TIM(2,1,1,&pin_PA00),
diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h
index f78cb57a7..52fc1961a 100644
--- a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h
+++ b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h
@@ -27,31 +27,31 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H
 
-//I2C
-extern I2C_TypeDef * mcu_i2c_banks[3];
+// I2C
+extern I2C_TypeDef *mcu_i2c_banks[3];
 
 extern const mcu_periph_obj_t mcu_i2c_sda_list[7];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[4];
 
-//SPI
-extern SPI_TypeDef * mcu_spi_banks[5];
+// SPI
+extern SPI_TypeDef *mcu_spi_banks[5];
 
 extern const mcu_periph_obj_t mcu_spi_sck_list[15];
 extern const mcu_periph_obj_t mcu_spi_mosi_list[14];
 extern const mcu_periph_obj_t mcu_spi_miso_list[12];
 extern const mcu_periph_obj_t mcu_spi_nss_list[12];
 
-//UART
-extern USART_TypeDef * mcu_uart_banks[MAX_UART];
+// UART
+extern USART_TypeDef *mcu_uart_banks[MAX_UART];
 extern bool mcu_uart_has_usart[MAX_UART];
 
 extern const mcu_periph_obj_t mcu_uart_tx_list[7];
 extern const mcu_periph_obj_t mcu_uart_rx_list[7];
 
-//Timers
+// Timers
 #define TIM_BANK_ARRAY_LEN 14
 #define TIM_PIN_ARRAY_LEN 44
-extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
+extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN];
 extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN];
 
 #endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H
diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c
index ed89f0de6..a155970bb 100644
--- a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c
+++ b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -34,9 +34,9 @@ const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC);
 const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC);
 const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC);
 
-const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp
-const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN
-const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT
+const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); // anti-tamp
+const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); // OSC32_IN
+const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); // OSC32_OUT
 
 const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10));
 const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11));
@@ -94,9 +94,9 @@ const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC);
 const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC);
 const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC);
 const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC);
-const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); //SWDIO
-const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); //SWCLK
-const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); //JTDI
+const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); // SWDIO
+const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); // SWCLK
+const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); // JTDI
 
 const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC);
 const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC);
diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h
index b6c18b02e..00e7cf1b4 100644
--- a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h
+++ b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h
@@ -27,13 +27,13 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PINS_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PINS_H
 
-//Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only
-//pg 38
+// Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only
+// pg 38
 extern const mcu_pin_obj_t pin_PE02;
 extern const mcu_pin_obj_t pin_PE03;
 extern const mcu_pin_obj_t pin_PE04;
 extern const mcu_pin_obj_t pin_PE05;
-//pg 39
+// pg 39
 extern const mcu_pin_obj_t pin_PE06;
 extern const mcu_pin_obj_t pin_PC13;
 extern const mcu_pin_obj_t pin_PC14;
@@ -42,7 +42,7 @@ extern const mcu_pin_obj_t pin_PC00;
 extern const mcu_pin_obj_t pin_PC01;
 extern const mcu_pin_obj_t pin_PC02;
 extern const mcu_pin_obj_t pin_PC03;
-//pg 40
+// pg 40
 extern const mcu_pin_obj_t pin_PA00;
 extern const mcu_pin_obj_t pin_PA01;
 extern const mcu_pin_obj_t pin_PA02;
@@ -51,7 +51,7 @@ extern const mcu_pin_obj_t pin_PA04;
 extern const mcu_pin_obj_t pin_PA05;
 extern const mcu_pin_obj_t pin_PA06;
 extern const mcu_pin_obj_t pin_PA07;
-//pg 41
+// pg 41
 extern const mcu_pin_obj_t pin_PC04;
 extern const mcu_pin_obj_t pin_PC05;
 extern const mcu_pin_obj_t pin_PB00;
@@ -66,7 +66,7 @@ extern const mcu_pin_obj_t pin_PE12;
 extern const mcu_pin_obj_t pin_PE13;
 extern const mcu_pin_obj_t pin_PE14;
 extern const mcu_pin_obj_t pin_PE15;
-//pg 42
+// pg 42
 extern const mcu_pin_obj_t pin_PB10;
 extern const mcu_pin_obj_t pin_PB12;
 extern const mcu_pin_obj_t pin_PB13;
@@ -77,7 +77,7 @@ extern const mcu_pin_obj_t pin_PD09;
 extern const mcu_pin_obj_t pin_PD10;
 extern const mcu_pin_obj_t pin_PD11;
 extern const mcu_pin_obj_t pin_PD12;
-//pg 43
+// pg 43
 extern const mcu_pin_obj_t pin_PD13;
 extern const mcu_pin_obj_t pin_PD14;
 extern const mcu_pin_obj_t pin_PD15;
@@ -87,7 +87,7 @@ extern const mcu_pin_obj_t pin_PC08;
 extern const mcu_pin_obj_t pin_PC09;
 extern const mcu_pin_obj_t pin_PA08;
 extern const mcu_pin_obj_t pin_PA09;
-//pg 44
+// pg 44
 extern const mcu_pin_obj_t pin_PA10;
 extern const mcu_pin_obj_t pin_PA11;
 extern const mcu_pin_obj_t pin_PA12;
@@ -97,7 +97,7 @@ extern const mcu_pin_obj_t pin_PA15;
 extern const mcu_pin_obj_t pin_PC10;
 extern const mcu_pin_obj_t pin_PC11;
 extern const mcu_pin_obj_t pin_PC12;
-//pg 45
+// pg 45
 extern const mcu_pin_obj_t pin_PD00;
 extern const mcu_pin_obj_t pin_PD01;
 extern const mcu_pin_obj_t pin_PD02;
@@ -110,7 +110,7 @@ extern const mcu_pin_obj_t pin_PB03;
 extern const mcu_pin_obj_t pin_PB04;
 extern const mcu_pin_obj_t pin_PB05;
 extern const mcu_pin_obj_t pin_PB06;
-//pg 46
+// pg 46
 extern const mcu_pin_obj_t pin_PB07;
 extern const mcu_pin_obj_t pin_PB08;
 extern const mcu_pin_obj_t pin_PB09;
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h
index e1355c8f3..acd353793 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the Micro Python project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
index 5ca4667a4..6fe7bbb9c 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c
@@ -38,15 +38,15 @@ void stm32_peripherals_gpio_init(void) {
     __HAL_RCC_GPIOG_CLK_ENABLE();
     __HAL_RCC_GPIOD_CLK_ENABLE();
 
-    //Never reset pins
-    never_reset_pin_number(2,13); //PC13 anti tamp
-    never_reset_pin_number(2,14); //PC14 OSC32_IN
-    never_reset_pin_number(2,15); //PC15 OSC32_OUT
-    never_reset_pin_number(0,13); //PA13 SWDIO
-    never_reset_pin_number(0,14); //PA14 SWCLK
-    //never_reset_pin_number(0,15); //PA15 JTDI
-    //never_reset_pin_number(1,3); //PB3 JTDO
-    //never_reset_pin_number(1,4); //PB4 JTRST
+    // Never reset pins
+    never_reset_pin_number(2,13); // PC13 anti tamp
+    never_reset_pin_number(2,14); // PC14 OSC32_IN
+    never_reset_pin_number(2,15); // PC15 OSC32_OUT
+    never_reset_pin_number(0,13); // PA13 SWDIO
+    never_reset_pin_number(0,14); // PA14 SWCLK
+    // never_reset_pin_number(0,15); //PA15 JTDI
+    // never_reset_pin_number(1,3); //PB3 JTDO
+    // never_reset_pin_number(1,4); //PB4 JTRST
 
     // Port H is not included in GPIO port array
     // never_reset_pin_number(5,0); //PH0 JTDO
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c
index e92c88ce5..8cd61fd49 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -31,12 +31,12 @@
 
 // I2C
 
-I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3};
+I2C_TypeDef *mcu_i2c_banks[3] = {I2C1, I2C2, I2C3};
 
 const mcu_periph_obj_t mcu_i2c_sda_list[8] = {
     PERIPH(1, 4, &pin_PB07),
     PERIPH(1, 4, &pin_PB09),
-    PERIPH(2, 4, &pin_PB11), //not on LQFP100
+    PERIPH(2, 4, &pin_PB11), // not on LQFP100
     PERIPH(2, 9, &pin_PB09),
     PERIPH(2, 9, &pin_PB03),
     PERIPH(3, 4, &pin_PC09),
@@ -53,7 +53,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[4] = {
 
 // SPI
 
-SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5};
+SPI_TypeDef *mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5};
 
 const mcu_periph_obj_t mcu_spi_sck_list[15] = {
     PERIPH(1, 5, &pin_PA05),
@@ -120,9 +120,9 @@ const mcu_periph_obj_t mcu_spi_nss_list[12] = {
     PERIPH(5, 6, &pin_PE11)
 };
 
-//UART
+// UART
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, NULL, NULL, USART6};
+USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, NULL, NULL, USART6};
 bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true};
 
 const mcu_periph_obj_t mcu_uart_tx_list[11] = {
@@ -154,10 +154,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[12] = {
     PERIPH(6, 8, &pin_PG09),
 };
 
-//Timers
-//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
-                                    TIM11, TIM12, TIM13, TIM14};
+// Timers
+// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
+TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
+                                  TIM11, TIM12, TIM13, TIM14};
 
 const mcu_tim_pin_obj_t mcu_tim_pin_list[60] = {
     TIM(2,1,1,&pin_PA00),
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h
index 40afd27f4..4e861da5d 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h
@@ -27,32 +27,32 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H
 
-//I2C
-extern I2C_TypeDef * mcu_i2c_banks[3];
+// I2C
+extern I2C_TypeDef *mcu_i2c_banks[3];
 
 extern const mcu_periph_obj_t mcu_i2c_sda_list[8];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[4];
 
 
-//SPI
-extern SPI_TypeDef * mcu_spi_banks[5];
+// SPI
+extern SPI_TypeDef *mcu_spi_banks[5];
 
 extern const mcu_periph_obj_t mcu_spi_sck_list[15];
 extern const mcu_periph_obj_t mcu_spi_mosi_list[14];
 extern const mcu_periph_obj_t mcu_spi_miso_list[12];
 extern const mcu_periph_obj_t mcu_spi_nss_list[12];
 
-//UART
-extern USART_TypeDef * mcu_uart_banks[MAX_UART];
+// UART
+extern USART_TypeDef *mcu_uart_banks[MAX_UART];
 extern bool mcu_uart_has_usart[MAX_UART];
 
 extern const mcu_periph_obj_t mcu_uart_tx_list[11];
 extern const mcu_periph_obj_t mcu_uart_rx_list[12];
 
-//Timers
+// Timers
 #define TIM_BANK_ARRAY_LEN 14
 #define TIM_PIN_ARRAY_LEN 60
-extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
+extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN];
 extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN];
 
 #endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c
index c1b624f4d..4fa70b5bd 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -34,9 +34,9 @@ const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC);
 const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC);
 const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC);
 
-const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp
-const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN
-const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT
+const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); // anti-tamp
+const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); // OSC32_IN
+const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); // OSC32_OUT
 
 const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC);   // 144 only
 const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC);   // 144 only
diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h
index 8914530d2..18e25f3f5 100644
--- a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h
+++ b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h
@@ -27,7 +27,7 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PINS_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PINS_H
 
-//pg 50
+// pg 50
 extern const mcu_pin_obj_t pin_PE02;
 extern const mcu_pin_obj_t pin_PE03;
 extern const mcu_pin_obj_t pin_PE04;
@@ -35,7 +35,7 @@ extern const mcu_pin_obj_t pin_PE05;
 extern const mcu_pin_obj_t pin_PE06;
 extern const mcu_pin_obj_t pin_PC13;
 extern const mcu_pin_obj_t pin_PC14;
-//pg 51
+// pg 51
 extern const mcu_pin_obj_t pin_PC15;
 extern const mcu_pin_obj_t pin_PF00;  // 144 only
 extern const mcu_pin_obj_t pin_PF01;  // 144 only
@@ -48,7 +48,7 @@ extern const mcu_pin_obj_t pin_PF07;  // 144 only
 extern const mcu_pin_obj_t pin_PF08;  // 144 only
 extern const mcu_pin_obj_t pin_PF09;  // 144 only
 extern const mcu_pin_obj_t pin_PF10; // 144 only
-//pg 52
+// pg 52
 extern const mcu_pin_obj_t pin_PC00;
 extern const mcu_pin_obj_t pin_PC01;
 extern const mcu_pin_obj_t pin_PC02;
@@ -56,14 +56,14 @@ extern const mcu_pin_obj_t pin_PC03;
 extern const mcu_pin_obj_t pin_PA00;
 extern const mcu_pin_obj_t pin_PA01;
 extern const mcu_pin_obj_t pin_PA02;
-//pg 53
+// pg 53
 extern const mcu_pin_obj_t pin_PA03;
 extern const mcu_pin_obj_t pin_PA04;
 extern const mcu_pin_obj_t pin_PA05;
 extern const mcu_pin_obj_t pin_PA06;
 extern const mcu_pin_obj_t pin_PA07;
 extern const mcu_pin_obj_t pin_PC04;
-//pg 54
+// pg 54
 extern const mcu_pin_obj_t pin_PC05;
 extern const mcu_pin_obj_t pin_PB00;
 extern const mcu_pin_obj_t pin_PB01;
@@ -75,7 +75,7 @@ extern const mcu_pin_obj_t pin_PF14; // 144 only
 extern const mcu_pin_obj_t pin_PF15; // 144 only
 extern const mcu_pin_obj_t pin_PG00;  // 144 only
 extern const mcu_pin_obj_t pin_PG01;  // 144 only
-//pg 55
+// pg 55
 extern const mcu_pin_obj_t pin_PE07;
 extern const mcu_pin_obj_t pin_PE08;
 extern const mcu_pin_obj_t pin_PE09;
@@ -84,13 +84,13 @@ extern const mcu_pin_obj_t pin_PE11;
 extern const mcu_pin_obj_t pin_PE12;
 extern const mcu_pin_obj_t pin_PE13;
 extern const mcu_pin_obj_t pin_PE14;
-//pg 56
+// pg 56
 extern const mcu_pin_obj_t pin_PE15;
 extern const mcu_pin_obj_t pin_PB10;
 extern const mcu_pin_obj_t pin_PB11; // 144 only
 extern const mcu_pin_obj_t pin_PB12;
 extern const mcu_pin_obj_t pin_PB13;
-//pg 57
+// pg 57
 extern const mcu_pin_obj_t pin_PB14;
 extern const mcu_pin_obj_t pin_PB15;
 extern const mcu_pin_obj_t pin_PD08;
@@ -98,7 +98,7 @@ extern const mcu_pin_obj_t pin_PD09;
 extern const mcu_pin_obj_t pin_PD10;
 extern const mcu_pin_obj_t pin_PD11;
 extern const mcu_pin_obj_t pin_PD12;
-//pg 58
+// pg 58
 extern const mcu_pin_obj_t pin_PD13;
 extern const mcu_pin_obj_t pin_PD14;
 extern const mcu_pin_obj_t pin_PD15;
@@ -109,7 +109,7 @@ extern const mcu_pin_obj_t pin_PG05;  // 144 only
 extern const mcu_pin_obj_t pin_PG06;  // 144 only
 extern const mcu_pin_obj_t pin_PG07;  // 144 only
 extern const mcu_pin_obj_t pin_PG08;  // 144 only
-//pg 59
+// pg 59
 extern const mcu_pin_obj_t pin_PC06;
 extern const mcu_pin_obj_t pin_PC07;
 extern const mcu_pin_obj_t pin_PC08;
@@ -117,7 +117,7 @@ extern const mcu_pin_obj_t pin_PC09;
 extern const mcu_pin_obj_t pin_PA08;
 extern const mcu_pin_obj_t pin_PA09;
 extern const mcu_pin_obj_t pin_PA10;
-//pg 60
+// pg 60
 extern const mcu_pin_obj_t pin_PA11;
 extern const mcu_pin_obj_t pin_PA12;
 extern const mcu_pin_obj_t pin_PA13;
@@ -125,7 +125,7 @@ extern const mcu_pin_obj_t pin_PA14;
 extern const mcu_pin_obj_t pin_PA15;
 extern const mcu_pin_obj_t pin_PC10;
 extern const mcu_pin_obj_t pin_PC11;
-//pg 61
+// pg 61
 extern const mcu_pin_obj_t pin_PC12;
 extern const mcu_pin_obj_t pin_PD00;
 extern const mcu_pin_obj_t pin_PD01;
@@ -135,7 +135,7 @@ extern const mcu_pin_obj_t pin_PD04;
 extern const mcu_pin_obj_t pin_PD05;
 extern const mcu_pin_obj_t pin_PD06;
 extern const mcu_pin_obj_t pin_PD07;
-//pg 62
+// pg 62
 extern const mcu_pin_obj_t pin_PG09;  // 144 only
 extern const mcu_pin_obj_t pin_PG10; // 144 only
 extern const mcu_pin_obj_t pin_PG11; // 144 only
@@ -145,7 +145,7 @@ extern const mcu_pin_obj_t pin_PG14; // 144 only
 extern const mcu_pin_obj_t pin_PG15; // 144 only
 extern const mcu_pin_obj_t pin_PB03;
 extern const mcu_pin_obj_t pin_PB04;
-//pg 63
+// pg 63
 extern const mcu_pin_obj_t pin_PB05;
 extern const mcu_pin_obj_t pin_PB06;
 extern const mcu_pin_obj_t pin_PB07;
diff --git a/ports/stm/peripherals/stm32f7/clocks.c b/ports/stm/peripherals/stm32f7/clocks.c
index f13088782..3767d223c 100644
--- a/ports/stm/peripherals/stm32f7/clocks.c
+++ b/ports/stm/peripherals/stm32f7/clocks.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the Micro Python project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -61,15 +61,17 @@ void stm32_peripherals_clocks_init(void) {
     RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE;
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-    RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
+    RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000;
     RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN;
     RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP;
     RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ;
 
-    if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         // Clock issues are too problematic to even attempt recovery.
         // If you end up here, check whether your LSE settings match your board.
-        while(1);
+        while (1) {
+            ;
+        }
     }
 
     /* Activate the OverDrive to reach the 216 MHz Frequency */
diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c b/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c
index ca64428eb..b7cc0aad6 100644
--- a/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c
+++ b/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c
@@ -29,7 +29,7 @@
 #include "common-hal/microcontroller/Pin.h"
 
 void stm32_peripherals_gpio_init(void) {
-    //Enable all GPIO for now
+    // Enable all GPIO for now
     __HAL_RCC_GPIOA_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
     __HAL_RCC_GPIOC_CLK_ENABLE();
@@ -42,11 +42,11 @@ void stm32_peripherals_gpio_init(void) {
     __HAL_RCC_GPIOJ_CLK_ENABLE();
     __HAL_RCC_GPIOK_CLK_ENABLE();
 
-    //Never reset pins
-    never_reset_pin_number(2,14); //PC14 OSC32_IN
-    never_reset_pin_number(2,15); //PC15 OSC32_OUT
-    never_reset_pin_number(0,13); //PA13 SWDIO
-    never_reset_pin_number(0,14); //PA14 SWCLK
-    never_reset_pin_number(7,0); //PH0 OSC_IN
-    never_reset_pin_number(7,1); //PH1 OSC_OUT
+    // Never reset pins
+    never_reset_pin_number(2,14); // PC14 OSC32_IN
+    never_reset_pin_number(2,15); // PC15 OSC32_OUT
+    never_reset_pin_number(0,13); // PA13 SWDIO
+    never_reset_pin_number(0,14); // PA14 SWCLK
+    never_reset_pin_number(7,0); // PH0 OSC_IN
+    never_reset_pin_number(7,1); // PH1 OSC_OUT
 }
diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/periph.c b/ports/stm/peripherals/stm32f7/stm32f746xx/periph.c
index 0c3391239..89cd7e27e 100644
--- a/ports/stm/peripherals/stm32f7/stm32f746xx/periph.c
+++ b/ports/stm/peripherals/stm32f7/stm32f746xx/periph.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -32,7 +32,7 @@
 
 // I2C
 
-I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4};
+I2C_TypeDef *mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4};
 
 const mcu_periph_obj_t mcu_i2c_sda_list[10] = {
     PERIPH(1, 4, &pin_PB07),
@@ -59,9 +59,9 @@ const mcu_periph_obj_t mcu_i2c_scl_list[10] = {
     PERIPH(4, 4, &pin_PH11),
 };
 
-//SPI
+// SPI
 
-SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6};
+SPI_TypeDef *mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6};
 
 const mcu_periph_obj_t mcu_spi_sck_list[14] = {
     PERIPH(1, 5, &pin_PA05),
@@ -111,9 +111,9 @@ const mcu_periph_obj_t mcu_spi_miso_list[12] = {
     PERIPH(2, 5, &pin_PI02),
 };
 
-//UART
+// UART
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8};
+USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8};
 bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true};
 
 const mcu_periph_obj_t mcu_uart_tx_list[15] = {
@@ -151,10 +151,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[15] = {
     PERIPH(6, 8, &pin_PG09),
 };
 
-//Timers
-//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
-                                    TIM11, TIM12, TIM13, TIM14};
+// Timers
+// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
+TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10,
+                                  TIM11, TIM12, TIM13, TIM14};
 
 const mcu_tim_pin_obj_t mcu_tim_pin_list[55] = {
     TIM(2, 1, 1, &pin_PA00),
diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/periph.h b/ports/stm/peripherals/stm32f7/stm32f746xx/periph.h
index f20896e22..425221f64 100644
--- a/ports/stm/peripherals/stm32f7/stm32f746xx/periph.h
+++ b/ports/stm/peripherals/stm32f7/stm32f746xx/periph.h
@@ -28,30 +28,30 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F746XX_PERIPH_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F746XX_PERIPH_H
 
-//I2C
-extern I2C_TypeDef * mcu_i2c_banks[4];
+// I2C
+extern I2C_TypeDef *mcu_i2c_banks[4];
 
 extern const mcu_periph_obj_t mcu_i2c_sda_list[10];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[10];
 
-//SPI
-extern SPI_TypeDef * mcu_spi_banks[6];
+// SPI
+extern SPI_TypeDef *mcu_spi_banks[6];
 
 extern const mcu_periph_obj_t mcu_spi_sck_list[14];
 extern const mcu_periph_obj_t mcu_spi_mosi_list[15];
 extern const mcu_periph_obj_t mcu_spi_miso_list[12];
 
-//UART
-extern USART_TypeDef * mcu_uart_banks[MAX_UART];
+// UART
+extern USART_TypeDef *mcu_uart_banks[MAX_UART];
 extern bool mcu_uart_has_usart[MAX_UART];
 
 extern const mcu_periph_obj_t mcu_uart_tx_list[15];
 extern const mcu_periph_obj_t mcu_uart_rx_list[15];
 
-//Timers
+// Timers
 #define TIM_BANK_ARRAY_LEN 14
 #define TIM_PIN_ARRAY_LEN 55
-extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
+extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN];
 
 extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN];
 
diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c b/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c
index ae940c1a0..0a2682528 100644
--- a/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c
+++ b/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c b/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c
index 1189948c7..f89af2714 100644
--- a/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c
+++ b/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c
@@ -28,7 +28,7 @@
 #include "common-hal/microcontroller/Pin.h"
 
 void stm32_peripherals_gpio_init(void) {
-    //Enable all GPIO for now
+    // Enable all GPIO for now
     __HAL_RCC_GPIOE_CLK_ENABLE();
     __HAL_RCC_GPIOC_CLK_ENABLE();
     __HAL_RCC_GPIOF_CLK_ENABLE();
@@ -38,9 +38,9 @@ void stm32_peripherals_gpio_init(void) {
     __HAL_RCC_GPIOG_CLK_ENABLE();
     __HAL_RCC_GPIOD_CLK_ENABLE();
 
-    //Never reset pins
-    never_reset_pin_number(2,14); //PC14 OSC32_IN
-    never_reset_pin_number(2,15); //PC15 OSC32_OUT
-    never_reset_pin_number(0,13); //PA13 SWDIO
-    never_reset_pin_number(0,14); //PA14 SWCLK
+    // Never reset pins
+    never_reset_pin_number(2,14); // PC14 OSC32_IN
+    never_reset_pin_number(2,15); // PC15 OSC32_OUT
+    never_reset_pin_number(0,13); // PA13 SWDIO
+    never_reset_pin_number(0,14); // PA14 SWCLK
 }
diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c
index 07d226db3..b1ac71248 100644
--- a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c
+++ b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -31,7 +31,7 @@
 
 // I2C
 
-I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4};
+I2C_TypeDef *mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4};
 
 const mcu_periph_obj_t mcu_i2c_sda_list[12] = {
     PERIPH(1, 4, &pin_PB07),
@@ -62,9 +62,9 @@ const mcu_periph_obj_t mcu_i2c_scl_list[12] = {
     PERIPH(4, 4, &pin_PH11),
 };
 
-//SPI
+// SPI
 
-SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6};
+SPI_TypeDef *mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6};
 
 const mcu_periph_obj_t mcu_spi_sck_list[18] = {
     PERIPH(1, 5, &pin_PA05),
@@ -124,9 +124,9 @@ const mcu_periph_obj_t mcu_spi_miso_list[15] = {
     PERIPH(2, 5, &pin_PI02),
 };
 
-//UART
+// UART
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8};
+USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8};
 bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true};
 
 const mcu_periph_obj_t mcu_uart_tx_list[24] = {
@@ -183,11 +183,11 @@ const mcu_periph_obj_t mcu_uart_rx_list[25] = {
     PERIPH(4, 8, &pin_PI09),
 };
 
-//Timers
-//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-//TODO: H7 has more timers than this, but are they tied to pins?
-TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL,
-                                    NULL, TIM12, TIM13, TIM14};
+// Timers
+// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
+// TODO: H7 has more timers than this, but are they tied to pins?
+TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL,
+                                  NULL, TIM12, TIM13, TIM14};
 
 const mcu_tim_pin_obj_t mcu_tim_pin_list[55] = {
     TIM(2, 1, 1, &pin_PA00),
diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h
index 70f03f258..ea4797634 100644
--- a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h
+++ b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h
@@ -27,30 +27,30 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H
 
-//I2C
-extern I2C_TypeDef * mcu_i2c_banks[4];
+// I2C
+extern I2C_TypeDef *mcu_i2c_banks[4];
 
 extern const mcu_periph_obj_t mcu_i2c_sda_list[12];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[12];
 
-//SPI
-extern SPI_TypeDef * mcu_spi_banks[6];
+// SPI
+extern SPI_TypeDef *mcu_spi_banks[6];
 
 extern const mcu_periph_obj_t mcu_spi_sck_list[18];
 extern const mcu_periph_obj_t mcu_spi_mosi_list[18];
 extern const mcu_periph_obj_t mcu_spi_miso_list[15];
 
-//UART
-extern USART_TypeDef * mcu_uart_banks[MAX_UART];
+// UART
+extern USART_TypeDef *mcu_uart_banks[MAX_UART];
 extern bool mcu_uart_has_usart[MAX_UART];
 
 extern const mcu_periph_obj_t mcu_uart_tx_list[24];
 extern const mcu_periph_obj_t mcu_uart_rx_list[25];
 
-//Timers
+// Timers
 #define TIM_BANK_ARRAY_LEN 14
 #define TIM_PIN_ARRAY_LEN 55
-extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
+extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN];
 
 extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN];
 
diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c
index 5c9daea98..67814c6b7 100644
--- a/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c
+++ b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/stm32h7/clocks.c b/ports/stm/peripherals/stm32h7/clocks.c
index a088f78bf..5fde5af6c 100644
--- a/ports/stm/peripherals/stm32h7/clocks.c
+++ b/ports/stm/peripherals/stm32h7/clocks.c
@@ -41,7 +41,8 @@ void stm32_peripherals_clocks_init(void) {
     // Set voltage scaling in accordance with system clock speed
     HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
     __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE);
-    while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+    while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
+    }
 
     // Configure LSE Drive
     HAL_PWR_EnableBkUpAccess();
@@ -63,7 +64,7 @@ void stm32_peripherals_clocks_init(void) {
     RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE;
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-    RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/2000000;
+    RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 2000000;
     RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN;
     RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP;
     RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ;
@@ -71,16 +72,18 @@ void stm32_peripherals_clocks_init(void) {
     RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
     RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
     RCC_OscInitStruct.PLL.PLLFRACN = 0;
-    if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         // Clock issues are too problematic to even attempt recovery.
         // If you end up here, check whether your LSE settings match your board.
-        while(1);
+        while (1) {
+            ;
+        }
     }
 
     // Configure bus clock sources and divisors
-    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
-                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+        | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+        | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
     RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
     RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV;
@@ -92,8 +95,8 @@ void stm32_peripherals_clocks_init(void) {
 
     // Set up non-bus peripherals
     // TODO: I2S settings go here
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART3
-                              |RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
+        | RCC_PERIPHCLK_USB;
     #if (BOARD_HAS_LOW_SPEED_CRYSTAL)
     PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
     #else
diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c b/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c
index 1189948c7..f89af2714 100644
--- a/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c
+++ b/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c
@@ -28,7 +28,7 @@
 #include "common-hal/microcontroller/Pin.h"
 
 void stm32_peripherals_gpio_init(void) {
-    //Enable all GPIO for now
+    // Enable all GPIO for now
     __HAL_RCC_GPIOE_CLK_ENABLE();
     __HAL_RCC_GPIOC_CLK_ENABLE();
     __HAL_RCC_GPIOF_CLK_ENABLE();
@@ -38,9 +38,9 @@ void stm32_peripherals_gpio_init(void) {
     __HAL_RCC_GPIOG_CLK_ENABLE();
     __HAL_RCC_GPIOD_CLK_ENABLE();
 
-    //Never reset pins
-    never_reset_pin_number(2,14); //PC14 OSC32_IN
-    never_reset_pin_number(2,15); //PC15 OSC32_OUT
-    never_reset_pin_number(0,13); //PA13 SWDIO
-    never_reset_pin_number(0,14); //PA14 SWCLK
+    // Never reset pins
+    never_reset_pin_number(2,14); // PC14 OSC32_IN
+    never_reset_pin_number(2,15); // PC15 OSC32_OUT
+    never_reset_pin_number(0,13); // PA13 SWDIO
+    never_reset_pin_number(0,14); // PA14 SWCLK
 }
diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c
index 892164600..bf8248f76 100644
--- a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c
+++ b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
@@ -31,7 +31,7 @@
 
 // I2C
 
-I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4};
+I2C_TypeDef *mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4};
 
 const mcu_periph_obj_t mcu_i2c_sda_list[12] = {
     PERIPH(1, 4, &pin_PB07),
@@ -65,7 +65,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[12] = {
 
 // SPI
 
-SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6};
+SPI_TypeDef *mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6};
 
 const mcu_periph_obj_t mcu_spi_sck_list[19] = {
     PERIPH(1, 5, &pin_PA05),
@@ -130,9 +130,9 @@ const mcu_periph_obj_t mcu_spi_miso_list[16] = {
     PERIPH(5, 5, &pin_PJ11),
 };
 
-//UART
+// UART
 
-USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8};
+USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8};
 bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true};
 
 const mcu_periph_obj_t mcu_uart_tx_list[25] = {
@@ -192,11 +192,11 @@ const mcu_periph_obj_t mcu_uart_rx_list[26] = {
     PERIPH(8, 8, &pin_PJ09),
 };
 
-//Timers
-//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
-//TODO: H7 has more timers than this, but are they tied to pins?
-TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL,
-                                    NULL, TIM12, TIM13, TIM14};
+// Timers
+// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins
+// TODO: H7 has more timers than this, but are they tied to pins?
+TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL,
+                                  NULL, TIM12, TIM13, TIM14};
 
 const mcu_tim_pin_obj_t mcu_tim_pin_list[58] = {
     TIM(2, 1, 1, &pin_PA00),
diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h
index e3902e7c7..3716a0f82 100644
--- a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h
+++ b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h
@@ -27,29 +27,29 @@
 #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H
 #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H
 
-//I2C
-extern I2C_TypeDef * mcu_i2c_banks[4];
+// I2C
+extern I2C_TypeDef *mcu_i2c_banks[4];
 
 extern const mcu_periph_obj_t mcu_i2c_sda_list[12];
 extern const mcu_periph_obj_t mcu_i2c_scl_list[12];
 
-//SPI
-extern SPI_TypeDef * mcu_spi_banks[6];
+// SPI
+extern SPI_TypeDef *mcu_spi_banks[6];
 
 extern const mcu_periph_obj_t mcu_spi_sck_list[19];
 extern const mcu_periph_obj_t mcu_spi_mosi_list[19];
 extern const mcu_periph_obj_t mcu_spi_miso_list[16];
 
-//UART
-extern USART_TypeDef * mcu_uart_banks[MAX_UART];
+// UART
+extern USART_TypeDef *mcu_uart_banks[MAX_UART];
 extern bool mcu_uart_has_usart[MAX_UART];
 
 extern const mcu_periph_obj_t mcu_uart_tx_list[25];
 extern const mcu_periph_obj_t mcu_uart_rx_list[26];
 
-//Timers
+// Timers
 #define TIM_BANK_ARRAY_LEN 14
 #define TIM_PIN_ARRAY_LEN 58
-extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN];
+extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN];
 
 #endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H
diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c
index 7484781c2..baad62274 100644
--- a/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c
+++ b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c
@@ -1,4 +1,4 @@
- /*
+/*
  * This file is part of the MicroPython project, http://micropython.org/
  *
  * The MIT License (MIT)
diff --git a/ports/stm/peripherals/timers.c b/ports/stm/peripherals/timers.c
index 7bc5ea495..6121deab1 100644
--- a/ports/stm/peripherals/timers.c
+++ b/ports/stm/peripherals/timers.c
@@ -41,8 +41,8 @@
 
 static bool stm_timer_reserved[MP_ARRAY_SIZE(mcu_tim_banks)];
 static bool stm_timer_never_reset[MP_ARRAY_SIZE(mcu_tim_banks)];
-static void (*stm_timer_callback[MP_ARRAY_SIZE(mcu_tim_banks)])(void);
-static size_t irq_map[] = {
+static void (*stm_timer_callback[MP_ARRAY_SIZE (mcu_tim_banks)])(void);
+    static size_t irq_map[] = {
     #ifdef TIM1
     TIM1_CC_IRQn,
     #else
@@ -69,11 +69,11 @@ static size_t irq_map[] = {
     NULL_IRQ,
     #endif
     #ifdef TIM6
-        #if !defined(DAC_BASE) && !defined(DAC1_BASE)
-        TIM6_IRQn,
-        #else
-        TIM6_DAC_IRQn,
-        #endif
+    #if !defined(DAC_BASE) && !defined(DAC1_BASE)
+    TIM6_IRQn,
+    #else
+    TIM6_DAC_IRQn,
+    #endif
     #else
     NULL_IRQ,
     #endif
@@ -139,7 +139,7 @@ static size_t irq_map[] = {
 // If the APB prescaler is 1, then the timer clock is equal to its respective
 // APB clock.  Otherwise (APB prescaler > 1) the timer clock is twice its
 // respective APB clock.  See DM00031020 Rev 4, page 115.
-uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef * timer) {
+    uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef *timer) {
     size_t tim_id = stm_peripherals_timer_get_index(timer);
     uint32_t source, clk_div;
     if (tim_id == 1 || (8 <= tim_id && tim_id <= 11)) {
@@ -158,12 +158,12 @@ uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef * timer) {
     return source;
 }
 
-size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef * instance) {
+    size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef *instance) {
     size_t tim_id = stm_peripherals_timer_get_index(instance);
     return irq_map[tim_id];
 }
 
-void timers_reset(void) {
+    void timers_reset(void) {
     uint16_t never_reset_mask = 0x00;
     for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) {
         if (!stm_timer_never_reset[i]) {
@@ -175,18 +175,18 @@ void timers_reset(void) {
     tim_clock_disable(ALL_CLOCKS & ~(never_reset_mask));
 }
 
-TIM_TypeDef * stm_peripherals_find_timer(void) {
+    TIM_TypeDef *stm_peripherals_find_timer(void) {
     // Check for timers on pins outside the package size
     for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) {
         bool timer_in_package = false;
         // Find each timer instance on the given bank
         for (size_t j = 0; j < MP_ARRAY_SIZE(mcu_tim_pin_list); j++) {
             // If a pin is claimed, we skip it
-            if ( (mcu_tim_pin_list[j].tim_index == i + 1)
-                && (common_hal_mcu_pin_is_free(mcu_tim_pin_list[j].pin) == true) ) {
+            if ((mcu_tim_pin_list[j].tim_index == i + 1)
+                && (common_hal_mcu_pin_is_free(mcu_tim_pin_list[j].pin) == true)) {
                 // Search whether any pins in the package array match it
                 for (size_t k = 0; k < mcu_pin_globals.map.alloc; k++) {
-                    if ( (mcu_tim_pin_list[j].pin == (mcu_pin_obj_t*)(mcu_pin_globals.map.table[k].value)) ) {
+                    if ((mcu_tim_pin_list[j].pin == (mcu_pin_obj_t *)(mcu_pin_globals.map.table[k].value))) {
                         timer_in_package = true;
                     }
                 }
@@ -198,7 +198,7 @@ TIM_TypeDef * stm_peripherals_find_timer(void) {
             return mcu_tim_banks[i];
         }
     }
-    //TODO: secondary search for timers outside the pins in the board profile
+    // TODO: secondary search for timers outside the pins in the board profile
 
     // Work backwards - higher index timers have fewer pin allocations
     for (size_t i = (MP_ARRAY_SIZE(mcu_tim_banks) - 1); i >= 0; i--) {
@@ -210,7 +210,7 @@ TIM_TypeDef * stm_peripherals_find_timer(void) {
     return NULL;
 }
 
-void stm_peripherals_timer_preinit(TIM_TypeDef * instance, uint8_t prio, void (*callback)(void)) {
+    void stm_peripherals_timer_preinit(TIM_TypeDef *instance, uint8_t prio, void (*callback)(void)) {
     size_t tim_idx = stm_peripherals_timer_get_index(instance);
     stm_timer_callback[tim_idx] = callback;
     tim_clock_enable(1 << tim_idx);
@@ -218,16 +218,16 @@ void stm_peripherals_timer_preinit(TIM_TypeDef * instance, uint8_t prio, void (*
     HAL_NVIC_EnableIRQ(irq_map[tim_idx]);
 }
 
-void stm_peripherals_timer_reserve(TIM_TypeDef * instance) {
+    void stm_peripherals_timer_reserve(TIM_TypeDef *instance) {
     size_t tim_idx = stm_peripherals_timer_get_index(instance);
     stm_timer_reserved[tim_idx] = true;
 }
 
-void stm_peripherals_timer_set_callback(void(*callback)(void), TIM_TypeDef * timer) {
+    void stm_peripherals_timer_set_callback(void (*callback)(void), TIM_TypeDef *timer) {
     stm_timer_callback[stm_peripherals_timer_get_index(timer)] = callback;
 }
 
-void stm_peripherals_timer_free(TIM_TypeDef * instance) {
+    void stm_peripherals_timer_free(TIM_TypeDef *instance) {
     size_t tim_idx = stm_peripherals_timer_get_index(instance);
     HAL_NVIC_DisableIRQ(irq_map[tim_idx]);
     stm_timer_callback[tim_idx] = NULL;
@@ -236,24 +236,24 @@ void stm_peripherals_timer_free(TIM_TypeDef * instance) {
     stm_timer_never_reset[tim_idx] = false;
 }
 
-void stm_peripherals_timer_never_reset(TIM_TypeDef * instance) {
+    void stm_peripherals_timer_never_reset(TIM_TypeDef *instance) {
     size_t tim_idx = stm_peripherals_timer_get_index(instance);
     stm_timer_never_reset[tim_idx] = true;
 }
-void stm_peripherals_timer_reset_ok(TIM_TypeDef * instance) {
+    void stm_peripherals_timer_reset_ok(TIM_TypeDef *instance) {
     size_t tim_idx = stm_peripherals_timer_get_index(instance);
     stm_timer_never_reset[tim_idx] = false;
 }
-bool stm_peripherals_timer_is_never_reset(TIM_TypeDef * instance){
+    bool stm_peripherals_timer_is_never_reset(TIM_TypeDef *instance) {
     size_t tim_idx = stm_peripherals_timer_get_index(instance);
     return stm_timer_never_reset[tim_idx];
 }
-bool stm_peripherals_timer_is_reserved(TIM_TypeDef * instance) {
+    bool stm_peripherals_timer_is_reserved(TIM_TypeDef *instance) {
     size_t tim_idx = stm_peripherals_timer_get_index(instance);
     return stm_timer_reserved[tim_idx];
 }
 
-size_t stm_peripherals_timer_get_index(TIM_TypeDef * instance) {
+    size_t stm_peripherals_timer_get_index(TIM_TypeDef *instance) {
     for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) {
         if (instance == mcu_tim_banks[i]) {
             return i;
@@ -262,7 +262,7 @@ size_t stm_peripherals_timer_get_index(TIM_TypeDef * instance) {
     return ~(size_t)0;
 }
 
-void tim_clock_enable(uint16_t mask) {
+    void tim_clock_enable(uint16_t mask) {
     #ifdef TIM1
     if (mask & (1 << 0)) {
         __HAL_RCC_TIM1_CLK_ENABLE();
@@ -288,7 +288,7 @@ void tim_clock_enable(uint16_t mask) {
         __HAL_RCC_TIM5_CLK_ENABLE();
     }
     #endif
-    //6 and 7 are reserved ADC timers
+    // 6 and 7 are reserved ADC timers
     #ifdef TIM8
     if (mask & (1 << 7)) {
         __HAL_RCC_TIM8_CLK_ENABLE();
@@ -326,7 +326,7 @@ void tim_clock_enable(uint16_t mask) {
     #endif
 }
 
-void tim_clock_disable(uint16_t mask) {
+    void tim_clock_disable(uint16_t mask) {
     #ifdef TIM1
     if (mask & (1 << 0)) {
         __HAL_RCC_TIM1_CLK_DISABLE();
@@ -352,7 +352,7 @@ void tim_clock_disable(uint16_t mask) {
         __HAL_RCC_TIM5_CLK_DISABLE();
     }
     #endif
-    //6 and 7 are reserved ADC timers
+    // 6 and 7 are reserved ADC timers
     #ifdef TIM8
     if (mask & (1 << 7)) {
         __HAL_RCC_TIM8_CLK_DISABLE();
@@ -390,65 +390,65 @@ void tim_clock_disable(uint16_t mask) {
     #endif
 }
 
-STATIC void callback_router(size_t index) {
+    STATIC void callback_router(size_t index) {
     if (stm_timer_callback[index - 1]) {
         (*stm_timer_callback[index - 1])();
     }
 }
 
-void TIM1_CC_IRQHandler(void) {     // Advanced timer
+    void TIM1_CC_IRQHandler(void) { // Advanced timer
     callback_router(1);
 }
-void TIM2_IRQHandler(void) {
+    void TIM2_IRQHandler(void) {
     callback_router(2);
 }
-void TIM3_IRQHandler(void) {
+    void TIM3_IRQHandler(void) {
     callback_router(3);
 }
-void TIM4_IRQHandler(void) {
+    void TIM4_IRQHandler(void) {
     callback_router(4);
 }
-void TIM5_IRQHandler(void) {
+    void TIM5_IRQHandler(void) {
     callback_router(5);
 }
-void TIM6_DAC_IRQHandler(void) {    // Basic timer (DAC)
+    void TIM6_DAC_IRQHandler(void) { // Basic timer (DAC)
     callback_router(6);
 }
-void TIM7_IRQHandler(void) {        // Basic timer
+    void TIM7_IRQHandler(void) {    // Basic timer
     callback_router(7);
 }
-void TIM8_CC_IRQHandler(void) {     // Advanced timer
+    void TIM8_CC_IRQHandler(void) { // Advanced timer
     callback_router(8);
 }
 
 // Advanced timer interrupts are currently unused.
-void TIM1_BRK_TIM9_IRQHandler(void) {
+    void TIM1_BRK_TIM9_IRQHandler(void) {
     callback_router(9);
 }
-void TIM1_UP_TIM10_IRQHandler(void) {
+    void TIM1_UP_TIM10_IRQHandler(void) {
     callback_router(10);
 }
-void TIM1_TRG_COM_TIM11_IRQHandler(void) {
+    void TIM1_TRG_COM_TIM11_IRQHandler(void) {
     callback_router(11);
 }
-void TIM8_BRK_TIM12_IRQHandler(void) {
+    void TIM8_BRK_TIM12_IRQHandler(void) {
     callback_router(12);
 }
-void TIM8_UP_TIM13_IRQHandler(void) {
+    void TIM8_UP_TIM13_IRQHandler(void) {
     callback_router(13);
 }
-void TIM8_TRG_COM_TIM14_IRQHandler(void) {
+    void TIM8_TRG_COM_TIM14_IRQHandler(void) {
     callback_router(14);
 }
 
 #if (CPY_STM32H7)
-void TIM15_IRQHandler(void) {
+    void TIM15_IRQHandler(void) {
     callback_router(15);
 }
-void TIM16_IRQHandler(void) {
+    void TIM16_IRQHandler(void) {
     callback_router(16);
 }
-void TIM17_IRQHandler(void) {
+    void TIM17_IRQHandler(void) {
     callback_router(17);
 }
 #endif
diff --git a/ports/stm/peripherals/timers.h b/ports/stm/peripherals/timers.h
index c4b6c6367..26cba88a0 100644
--- a/ports/stm/peripherals/timers.h
+++ b/ports/stm/peripherals/timers.h
@@ -32,15 +32,15 @@
 
 void tim_clock_enable(uint16_t mask);
 void tim_clock_disable(uint16_t mask);
-uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef * timer);
-size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef * instance);
+uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef *timer);
+size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef *instance);
 void timers_reset(void);
-TIM_TypeDef * stm_peripherals_find_timer(void);
-void stm_peripherals_timer_preinit(TIM_TypeDef * instance, uint8_t prio, void (*callback)(void));
-void stm_peripherals_timer_reserve(TIM_TypeDef * instance);
-void stm_peripherals_timer_free(TIM_TypeDef * instance);
-void stm_peripherals_timer_never_reset(TIM_TypeDef * instance);
-void stm_peripherals_timer_reset_ok(TIM_TypeDef * instance);
-bool stm_peripherals_timer_is_never_reset(TIM_TypeDef * instance);
-bool stm_peripherals_timer_is_reserved(TIM_TypeDef * instance);
-size_t stm_peripherals_timer_get_index(TIM_TypeDef * instance);
+TIM_TypeDef *stm_peripherals_find_timer(void);
+void stm_peripherals_timer_preinit(TIM_TypeDef *instance, uint8_t prio, void (*callback)(void));
+void stm_peripherals_timer_reserve(TIM_TypeDef *instance);
+void stm_peripherals_timer_free(TIM_TypeDef *instance);
+void stm_peripherals_timer_never_reset(TIM_TypeDef *instance);
+void stm_peripherals_timer_reset_ok(TIM_TypeDef *instance);
+bool stm_peripherals_timer_is_never_reset(TIM_TypeDef *instance);
+bool stm_peripherals_timer_is_reserved(TIM_TypeDef *instance);
+size_t stm_peripherals_timer_get_index(TIM_TypeDef *instance);
diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c
index 78ee4f3e6..560081013 100644
--- a/ports/stm/supervisor/internal_flash.c
+++ b/ports/stm/supervisor/internal_flash.c
@@ -52,47 +52,47 @@ typedef struct {
 
 #if defined(STM32F4)
 
-    STATIC const flash_layout_t flash_layout[] = {
-        { 0x08000000, 0x04000, 4 },
-        { 0x08010000, 0x10000, 1 },
-        { 0x08020000, 0x20000, 3 },
-        #if defined(FLASH_SECTOR_8)
-        { 0x08080000, 0x20000, 4 },
-        #endif
-        #if defined(FLASH_SECTOR_12)
-        { 0x08100000, 0x04000, 4 },
-        { 0x08110000, 0x10000, 1 },
-        { 0x08120000, 0x20000, 7 },
-        #endif
-    };
-    STATIC uint8_t  _flash_cache[0x4000] __attribute__((aligned(4)));
+STATIC const flash_layout_t flash_layout[] = {
+    { 0x08000000, 0x04000, 4 },
+    { 0x08010000, 0x10000, 1 },
+    { 0x08020000, 0x20000, 3 },
+    #if defined(FLASH_SECTOR_8)
+    { 0x08080000, 0x20000, 4 },
+    #endif
+    #if defined(FLASH_SECTOR_12)
+    { 0x08100000, 0x04000, 4 },
+    { 0x08110000, 0x10000, 1 },
+    { 0x08120000, 0x20000, 7 },
+    #endif
+};
+STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4)));
 
 #elif defined(STM32F7)
 
-    // FLASH_FLAG_PGSERR (Programming Sequence Error) was renamed to
-    // FLASH_FLAG_ERSERR (Erasing Sequence Error) in STM32F7
+// FLASH_FLAG_PGSERR (Programming Sequence Error) was renamed to
+// FLASH_FLAG_ERSERR (Erasing Sequence Error) in STM32F7
     #define FLASH_FLAG_PGSERR FLASH_FLAG_ERSERR
     #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx)
-    static const flash_layout_t flash_layout[] = {
-        { 0x08000000, 0x04000, 4 },
-        { 0x08010000, 0x10000, 1 },
-        { 0x08020000, 0x20000, 3 },
-    };
-    STATIC uint8_t  _flash_cache[0x4000] __attribute__((aligned(4)));
+static const flash_layout_t flash_layout[] = {
+    { 0x08000000, 0x04000, 4 },
+    { 0x08010000, 0x10000, 1 },
+    { 0x08020000, 0x20000, 3 },
+};
+STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4)));
     #else
-    static const flash_layout_t flash_layout[] = {
-        { 0x08000000, 0x08000, 4 },
-        { 0x08020000, 0x20000, 1 },
-        { 0x08040000, 0x40000, 3 },
-    };
-    STATIC uint8_t  _flash_cache[0x8000] __attribute__((aligned(4)));
+static const flash_layout_t flash_layout[] = {
+    { 0x08000000, 0x08000, 4 },
+    { 0x08020000, 0x20000, 1 },
+    { 0x08040000, 0x40000, 3 },
+};
+STATIC uint8_t _flash_cache[0x8000] __attribute__((aligned(4)));
     #endif
 #elif defined(STM32H7)
 
-    STATIC const flash_layout_t flash_layout[] = {
-        { 0x08000000, 0x20000, 16 },
-    };
-    STATIC uint8_t  _flash_cache[0x20000] __attribute__((aligned(4)));
+STATIC const flash_layout_t flash_layout[] = {
+    { 0x08000000, 0x20000, 16 },
+};
+STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4)));
 
 #else
     #error Unsupported processor
@@ -125,7 +125,7 @@ STATIC uint32_t get_bank(uint32_t addr) {
 }
 #endif
 
-//Return the sector of a given flash address.
+// Return the sector of a given flash address.
 uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) {
     if (addr >= flash_layout[0].base_address) {
         uint32_t sector_index = 0;
@@ -162,13 +162,15 @@ uint32_t supervisor_flash_get_block_count(void) {
 }
 
 void port_internal_flash_flush(void) {
-    if (_cache_flash_addr == NO_CACHE) return;
+    if (_cache_flash_addr == NO_CACHE) {
+        return;
+    }
 
     #if defined(STM32H7)
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK2);
     #else
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |
-                           FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
+        FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
     #endif
 
     // set up for erase
@@ -200,13 +202,13 @@ void port_internal_flash_flush(void) {
             reset_into_safe_mode(FLASH_WRITE_FAIL);
         }
 
-        uint32_t * cache_addr = (uint32_t*)_flash_cache;
+        uint32_t *cache_addr = (uint32_t *)_flash_cache;
 
         #if defined(STM32H7)
         for (uint32_t i = 0; i < (sector_size / 32); i++) {
             // Note that the STM32H7 HAL interface differs by taking an address, not 64 bit data
             if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, sector_start_addr,
-                                  (uint32_t)cache_addr) != HAL_OK) {
+                (uint32_t)cache_addr) != HAL_OK) {
                 // error occurred during flash write
                 HAL_FLASH_Lock(); // lock the flash
                 reset_into_safe_mode(FLASH_WRITE_FAIL);
@@ -220,7 +222,7 @@ void port_internal_flash_flush(void) {
         // program the flash word by word
         for (uint32_t i = 0; i < sector_size / 4; i++) {
             if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, sector_start_addr,
-                                  (uint64_t)*cache_addr) != HAL_OK) {
+                (uint64_t)*cache_addr) != HAL_OK) {
                 // error occurred during flash write
                 HAL_FLASH_Lock(); // lock the flash
                 reset_into_safe_mode(FLASH_WRITE_FAIL);
@@ -257,17 +259,17 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n
     uint32_t sector_start_addr;
     flash_get_sector_info(src, &sector_start_addr, &sector_size);
     // Count how many blocks are left in the sector
-    uint32_t count = (sector_size - (src - sector_start_addr))/FILESYSTEM_BLOCK_SIZE;
+    uint32_t count = (sector_size - (src - sector_start_addr)) / FILESYSTEM_BLOCK_SIZE;
     count = MIN(num_blocks, count);
 
     if (count < num_blocks && _cache_flash_addr == sector_start_addr) {
         // Read is contained in the cache, so just read cache
-        memcpy(dest, (_flash_cache + (src-sector_start_addr)), FILESYSTEM_BLOCK_SIZE*num_blocks);
+        memcpy(dest, (_flash_cache + (src - sector_start_addr)), FILESYSTEM_BLOCK_SIZE * num_blocks);
     } else {
         // The read spans multiple sectors or is in another sector
         // Must write out anything in cache before trying to read.
         supervisor_flash_flush();
-        memcpy(dest, (uint8_t*) src, FILESYSTEM_BLOCK_SIZE*num_blocks);
+        memcpy(dest, (uint8_t *)src, FILESYSTEM_BLOCK_SIZE * num_blocks);
     }
 
     return 0; // success
@@ -294,7 +296,7 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num,
         }
 
         // Find how many blocks are left in the sector
-        uint32_t count = (sector_size - (dest - sector_start_addr))/FILESYSTEM_BLOCK_SIZE;
+        uint32_t count = (sector_size - (dest - sector_start_addr)) / FILESYSTEM_BLOCK_SIZE;
         count = MIN(num_blocks, count);
 
         if (_cache_flash_addr != sector_start_addr) {
@@ -308,11 +310,11 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num,
         }
 
         // Overwrite part or all of the sector cache with the src data.
-        memcpy(_flash_cache + (dest-sector_start_addr), src, count * FILESYSTEM_BLOCK_SIZE);
+        memcpy(_flash_cache + (dest - sector_start_addr), src, count * FILESYSTEM_BLOCK_SIZE);
 
         // adjust for next run
-        block_num  += count;
-        src        += count * FILESYSTEM_BLOCK_SIZE;
+        block_num += count;
+        src += count * FILESYSTEM_BLOCK_SIZE;
         num_blocks -= count;
     }
 
diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h
index 19ae03e0b..106ff6c54 100644
--- a/ports/stm/supervisor/internal_flash.h
+++ b/ports/stm/supervisor/internal_flash.h
@@ -34,15 +34,15 @@
 #include "py/mpconfig.h"
 
 #ifdef STM32F401xE
-#define STM32_FLASH_SIZE 0x80000 //512KiB
-#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
+#define STM32_FLASH_SIZE 0x80000 // 512KiB
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB
 #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
 #endif
 
 #ifdef STM32F411xE
-#define STM32_FLASH_SIZE 0x80000 //512KiB
+#define STM32_FLASH_SIZE 0x80000 // 512KiB
 #ifndef INTERNAL_FLASH_FILESYSTEM_SIZE
-  #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
+  #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB
 #endif
 #ifndef INTERNAL_FLASH_FILESYSTEM_START_ADDR
   #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
@@ -50,45 +50,45 @@
 #endif
 
 #ifdef STM32F412Zx
-#define STM32_FLASH_SIZE 0x100000 //1MB
-#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
+#define STM32_FLASH_SIZE 0x100000 // 1MB
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB
 #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
 #endif
 
 #ifdef STM32F405xx
-#define STM32_FLASH_SIZE 0x100000 //1MB
-#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
+#define STM32_FLASH_SIZE 0x100000 // 1MB
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB
 #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
 #endif
 
 #ifdef STM32F407xx
-#define STM32_FLASH_SIZE 0x100000 //1MB
-#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB
+#define STM32_FLASH_SIZE 0x100000 // 1MB
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB
 #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000
 #endif
 
 /* Note this applies to STM32F769xG only, STM32F746xE has 512KB */
 #ifdef STM32F746xx
-#define STM32_FLASH_SIZE 0x100000 //1MB
-#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 //96KiB
+#define STM32_FLASH_SIZE 0x100000 // 1MB
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 // 96KiB
 #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08008000
 #endif
 
 #ifdef STM32F767xx
-#define STM32_FLASH_SIZE 0x200000 //2MB
-#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 //96KiB
+#define STM32_FLASH_SIZE 0x200000 // 2MB
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 // 96KiB
 #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08008000
 #endif
 
 #ifdef STM32H743xx
-#define STM32_FLASH_SIZE 0x200000 //2MB
-#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x60000 //384KiB
+#define STM32_FLASH_SIZE 0x200000 // 2MB
+#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x60000 // 384KiB
 #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08020000
 #endif
 
 #define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)
 
-#define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location
+#define STM32_FLASH_OFFSET 0x8000000 // All STM32 chips map to this flash location
 
 #define INTERNAL_FLASH_SYSTICK_MASK     (0x1ff) // 512ms
 #define INTERNAL_FLASH_IDLE_TICK(tick)  (((tick) & INTERNAL_FLASH_SYSTICK_MASK) == 2)
diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c
index 3103a0716..4a7583eb2 100644
--- a/ports/stm/supervisor/port.c
+++ b/ports/stm/supervisor/port.c
@@ -98,14 +98,14 @@ extern void SystemInit(void);
 // This replaces the Reset_Handler in gcc/startup_*.s, calls SystemInit from system_*.c
 __attribute__((used, naked)) void Reset_Handler(void) {
     __disable_irq();
-    __set_MSP((uint32_t) &_ld_stack_top);
+    __set_MSP((uint32_t)&_ld_stack_top);
 
     /* Disable MPU */
     ARM_MPU_Disable();
 
     // Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write
     // protect it.
-    for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_itcm_size) / 4; i++) {
         (&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i];
     }
 
@@ -133,22 +133,22 @@ __attribute__((used, naked)) void Reset_Handler(void) {
     ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
 
     // Copy all of the data to run from DTCM.
-    for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_data_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_data_size) / 4; i++) {
         (&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i];
     }
 
     // Clear DTCM bss.
-    for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_bss_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_bss_size) / 4; i++) {
         (&_ld_dtcm_bss_start)[i] = 0;
     }
 
     // Copy all of the data to run from D1 RAM.
-    for (uint32_t i = 0; i < ((size_t) &_ld_d1_ram_data_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_d1_ram_data_size) / 4; i++) {
         (&_ld_d1_ram_data_destination)[i] = (&_ld_d1_ram_data_flash_copy)[i];
     }
 
     // Clear D1 RAM bss.
-    for (uint32_t i = 0; i < ((size_t) &_ld_d1_ram_bss_size) / 4; i++) {
+    for (uint32_t i = 0; i < ((size_t)&_ld_d1_ram_bss_size) / 4; i++) {
         (&_ld_d1_ram_bss_start)[i] = 0;
     }
 
@@ -156,7 +156,7 @@ __attribute__((used, naked)) void Reset_Handler(void) {
     __enable_irq();
     main();
 }
-#endif //end H7 specific code
+#endif // end H7 specific code
 
 // Low power clock variables
 static volatile uint32_t systick_ms;
@@ -173,7 +173,7 @@ safe_mode_t port_init(void) {
     __HAL_RCC_SYSCFG_CLK_ENABLE();
 
     #if (CPY_STM32F4)
-        __HAL_RCC_PWR_CLK_ENABLE();
+    __HAL_RCC_PWR_CLK_ENABLE();
     #endif
 
     stm32_peripherals_clocks_init();
@@ -229,24 +229,24 @@ void SysTick_Handler(void) {
 
 void reset_port(void) {
     reset_all_pins();
-#if CIRCUITPY_BUSIO
+    #if CIRCUITPY_BUSIO
     i2c_reset();
     spi_reset();
     uart_reset();
-#endif
-#if CIRCUITPY_SDIOIO
+    #endif
+    #if CIRCUITPY_SDIOIO
     sdioio_reset();
-#endif
-#if CIRCUITPY_PULSEIO || CIRCUITPY_PWMIO
+    #endif
+    #if CIRCUITPY_PULSEIO || CIRCUITPY_PWMIO
     timers_reset();
-#endif
-#if CIRCUITPY_PULSEIO
+    #endif
+    #if CIRCUITPY_PULSEIO
     pulseout_reset();
     pulsein_reset();
-#endif
-#if CIRCUITPY_PWMIO
+    #endif
+    #if CIRCUITPY_PWMIO
     pwmout_reset();
-#endif
+    #endif
 }
 
 void reset_to_bootloader(void) {
@@ -290,35 +290,31 @@ uint32_t port_get_saved_word(void) {
     return _ebss;
 }
 
-__attribute__((used)) void MemManage_Handler(void)
-{
+__attribute__((used)) void MemManage_Handler(void) {
     reset_into_safe_mode(MEM_MANAGE);
     while (true) {
-        asm("nop;");
+        asm ("nop;");
     }
 }
 
-__attribute__((used)) void BusFault_Handler(void)
-{
+__attribute__((used)) void BusFault_Handler(void) {
     reset_into_safe_mode(MEM_MANAGE);
     while (true) {
-        asm("nop;");
+        asm ("nop;");
     }
 }
 
-__attribute__((used)) void UsageFault_Handler(void)
-{
+__attribute__((used)) void UsageFault_Handler(void) {
     reset_into_safe_mode(MEM_MANAGE);
     while (true) {
-        asm("nop;");
+        asm ("nop;");
     }
 }
 
-__attribute__((used)) void HardFault_Handler(void)
-{
+__attribute__((used)) void HardFault_Handler(void) {
     reset_into_safe_mode(HARD_CRASH);
     while (true) {
-        asm("nop;");
+        asm ("nop;");
     }
 }
 
@@ -328,7 +324,7 @@ volatile uint32_t seconds_to_date = 0;
 volatile uint32_t cached_date = 0;
 volatile uint32_t seconds_to_minute = 0;
 volatile uint32_t cached_hours_minutes = 0;
-uint64_t port_get_raw_ticks(uint8_t* subticks) {
+uint64_t port_get_raw_ticks(uint8_t *subticks) {
     // Disable IRQs to ensure we read all of the RTC registers as close in time as possible. Read
     // SSR twice to make sure we didn't read across a tick.
     __disable_irq();
@@ -372,7 +368,7 @@ uint64_t port_get_raw_ticks(uint8_t* subticks) {
         *subticks = subseconds % 32;
     }
 
-    uint64_t raw_ticks = ((uint64_t) 1024) * (seconds_to_date + seconds_to_minute + seconds) + subseconds / 32;
+    uint64_t raw_ticks = ((uint64_t)1024) * (seconds_to_date + seconds_to_minute + seconds) + subseconds / 32;
     return raw_ticks;
 }
 
@@ -424,7 +420,7 @@ void port_interrupt_after_ticks(uint32_t ticks) {
     }
 
     alarm.AlarmTime.SubSeconds = rtc_clock_frequency - 1 -
-                                 ((raw_ticks % 1024) * 32);
+        ((raw_ticks % 1024) * 32);
     alarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
     alarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_SET;
     // Masking here means that the bits are ignored so we set none of them.
@@ -438,9 +434,9 @@ void port_interrupt_after_ticks(uint32_t ticks) {
 
 void port_idle_until_interrupt(void) {
     // Clear the FPU interrupt because it can prevent us from sleeping.
-    if (__get_FPSCR()  & ~(0x9f)) {
-        __set_FPSCR(__get_FPSCR()  & ~(0x9f));
-        (void) __get_FPSCR();
+    if (__get_FPSCR() & ~(0x9f)) {
+        __set_FPSCR(__get_FPSCR() & ~(0x9f));
+        (void)__get_FPSCR();
     }
     if (alarmed_already) {
         return;
@@ -450,7 +446,6 @@ void port_idle_until_interrupt(void) {
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }
diff --git a/ports/stm/supervisor/qspi_flash.c b/ports/stm/supervisor/qspi_flash.c
index f3915273b..330e27dbd 100644
--- a/ports/stm/supervisor/qspi_flash.c
+++ b/ports/stm/supervisor/qspi_flash.c
@@ -31,9 +31,9 @@
 #include <string.h>
 
 #include "py/mpconfig.h" // for EXTERNAL_FLASH_QSPI_DUAL
-//#include "nrfx_qspi.h"
+// #include "nrfx_qspi.h"
 
-//#include "shared-bindings/microcontroller/__init__.h"
+// #include "shared-bindings/microcontroller/__init__.h"
 
 #include "supervisor/shared/external_flash/common_commands.h"
 #include "supervisor/shared/external_flash/qspi_flash.h"
@@ -47,10 +47,10 @@ bool spi_flash_command(uint8_t command) {
     //     .wipwait = false,
     //     .wren = false
     // };
-    return false; //nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL) == NRFX_SUCCESS;
+    return false; // nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL) == NRFX_SUCCESS;
 }
 
-bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length) {
+bool spi_flash_read_command(uint8_t command, uint8_t *response, uint32_t length) {
     // nrf_qspi_cinstr_conf_t cinstr_cfg = {
     //     .opcode = command,
     //     .length = length + 1,
@@ -64,7 +64,7 @@ bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length)
 
 }
 
-bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
+bool spi_flash_write_command(uint8_t command, uint8_t *data, uint32_t length) {
     // nrf_qspi_cinstr_conf_t cinstr_cfg = {
     //     .opcode = command,
     //     .length = length + 1,
@@ -85,12 +85,12 @@ bool spi_flash_sector_command(uint8_t command, uint32_t address) {
     return false;
 }
 
-bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) {
+bool spi_flash_write_data(uint32_t address, uint8_t *data, uint32_t length) {
     // return nrfx_qspi_write(data, length, address) == NRFX_SUCCESS;
     return false;
 }
 
-bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
+bool spi_flash_read_data(uint32_t address, uint8_t *data, uint32_t length) {
     // return nrfx_qspi_read(data, length, address) == NRFX_SUCCESS;
     return false;
 }
@@ -139,7 +139,7 @@ void spi_flash_init(void) {
 //     nrfx_qspi_init(&qspi_cfg, NULL, NULL);
 }
 
-void spi_flash_init_device(const external_flash_device* device) {
+void spi_flash_init_device(const external_flash_device *device) {
     // check_quad_enable(device);
 
     // // Switch to single output line if the device doesn't support quad programs.
diff --git a/ports/stm/supervisor/serial.c b/ports/stm/supervisor/serial.c
index 3a058ed2e..ac6f69bbb 100644
--- a/ports/stm/supervisor/serial.c
+++ b/ports/stm/supervisor/serial.c
@@ -42,8 +42,7 @@ void serial_init(void) {
     huart2.Init.Mode = UART_MODE_TX_RX;
     huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
     huart2.Init.OverSampling = UART_OVERSAMPLING_16;
-    if (HAL_UART_Init(&huart2) == HAL_OK)
-    {
+    if (HAL_UART_Init(&huart2) == HAL_OK) {
         stm32f4_peripherals_status_led(1,1);
     }
 }
@@ -62,7 +61,7 @@ bool serial_bytes_available(void) {
     return __HAL_UART_GET_FLAG(&huart2, UART_FLAG_RXNE);
 }
 
-void serial_write(const char* text) {
+void serial_write(const char *text) {
     serial_write_substring(text, strlen(text));
 }
 
@@ -70,5 +69,5 @@ void serial_write_substring(const char *text, uint32_t len) {
     if (len == 0) {
         return;
     }
-    HAL_UART_Transmit(&huart2, (uint8_t*)text, len, 5000);
+    HAL_UART_Transmit(&huart2, (uint8_t *)text, len, 5000);
 }
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
index c0e012cc6..906d07f73 100644
--- a/ports/stm/supervisor/usb.c
+++ b/ports/stm/supervisor/usb.c
@@ -37,33 +37,33 @@
 
 STATIC void init_usb_vbus_sense(void) {
 
-#if (BOARD_NO_VBUS_SENSE)
+    #if (BOARD_NO_VBUS_SENSE)
     // Disable VBUS sensing
     #ifdef USB_OTG_GCCFG_VBDEN
-        // Deactivate VBUS Sensing B
-        USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+    // Deactivate VBUS Sensing B
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 
-        // B-peripheral session valid override enable
-        USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-        USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+    // B-peripheral session valid override enable
+    USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+    USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
     #else
-        USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-        USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-        USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
     #endif
-#else
+    #else
     // Enable VBUS hardware sensing
     #ifdef USB_OTG_GCCFG_VBDEN
-        USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
     #else
-        USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-        USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // B Device sense
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;     // B Device sense
+    #endif
     #endif
-#endif
 }
 
 void init_usb_hardware(void) {
-    //TODO: if future chips overload this with options, move to peripherals management.
+    // TODO: if future chips overload this with options, move to peripherals management.
 
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     /**USB_OTG_FS GPIO Configuration
@@ -73,7 +73,7 @@ void init_usb_hardware(void) {
     */
     __HAL_RCC_GPIOA_CLK_ENABLE();
 
-      /* Configure DM DP Pins */
+    /* Configure DM DP Pins */
     GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
     GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -135,5 +135,5 @@ void init_usb_hardware(void) {
 }
 
 void OTG_FS_IRQHandler(void) {
-  usb_irq_handler();
+    usb_irq_handler();
 }
diff --git a/ports/stm/tools/parse_af_csv.py b/ports/stm/tools/parse_af_csv.py
index 06af3bf1e..38608b5da 100644
--- a/ports/stm/tools/parse_af_csv.py
+++ b/ports/stm/tools/parse_af_csv.py
@@ -36,40 +36,43 @@ import sys
 def evaluate_periph(inper, inlist, periph, subtype, altfn, pin):
     # ex) SPI1_SCK,SPI3_SCK/I2S3_CK
     # Clean anything after a '\' due to SPI/I2S mixing
-    if not inper.find('/') == -1:
-        inper = inper[:inper.find('/')]
+    if not inper.find("/") == -1:
+        inper = inper[: inper.find("/")]
+
+    if inper[: len(periph)] == periph and inper[-len(subtype) :] == subtype:
+        inlist.append([inper[len(periph) : len(periph) + 1], altfn, pin])
 
-    if inper[:len(periph)] == periph and inper[-len(subtype):] == subtype:
-        inlist.append([inper[len(periph):len(periph)+1], altfn, pin])
 
 # Timers (TIM) are a special case with 4 values
 # timer index, alt function, channel, pin string
 def evaluate_tim(inper, inlist, altfn, pin):
     # ex) TIM2_CH1/TIM2_ETR,  TIM5_CH1
     # Clean anything after a '\' to filter ETR
-    if not inper.find('/') == -1:
-        inper = inper[:inper.find('/')]
+    if not inper.find("/") == -1:
+        inper = inper[: inper.find("/")]
+
+    if inper[:3] == "TIM" and inper[5:7] == "CH" and inper[-1:] != "N":
+        inlist.append([inper[3:4], altfn, inper[-1:], pin])
+    elif inper[:3] == "TIM" and inper[6:8] == "CH" and inper[-1:] != "N":
+        inlist.append([inper[3:5], altfn, inper[-1:], pin])
 
-    if inper[:3] == "TIM" and inper[5:7] == "CH" and inper[-1:] != 'N':
-        inlist.append([inper[3:4],altfn,inper[-1:],pin])
-    elif inper[:3] == "TIM" and inper[6:8] == "CH" and inper[-1:] != 'N':
-        inlist.append([inper[3:5],altfn,inper[-1:],pin])
 
 # Open target file
 with open(sys.argv[1]) as csv_file:
-    csv_reader = csv.reader(csv_file, delimiter=',')
+    csv_reader = csv.reader(csv_file, delimiter=",")
     line_count = 0
 
     if sys.argv[2] != "-pins-only":
         # List of peripheral pin types to read
         todo = [
-            ["I2C","SDA"],
-            ["I2C","SCL"],
-            ["SPI","SCK"],
-            ["SPI","MOSI"],
-            ["SPI","MISO"],
-            ["UART","TX"],
-            ["UART","RX"]]
+            ["I2C", "SDA"],
+            ["I2C", "SCL"],
+            ["SPI", "SCK"],
+            ["SPI", "MOSI"],
+            ["SPI", "MISO"],
+            ["UART", "TX"],
+            ["UART", "RX"],
+        ]
 
         # Make a list of empty lists to populate
         outlist = []
@@ -85,7 +88,7 @@ with open(sys.argv[1]) as csv_file:
             altfn = 0
             pin = row[1]
             if len(pin) < 4:
-                pin = pin[:2] + '0' + pin[2:]
+                pin = pin[:2] + "0" + pin[2:]
             for col in row:
                 array_index = 0
                 # Evaluate the string for every possible todo entry
@@ -93,7 +96,9 @@ with open(sys.argv[1]) as csv_file:
                     evaluate_periph(col, outlist[array_index], item[0], item[1], altfn - 2, pin)
                     # UART special case, run again for USART variant
                     if item[0] == "UART":
-                        evaluate_periph(col, outlist[array_index], "USART", item[1], altfn - 2, pin)
+                        evaluate_periph(
+                            col, outlist[array_index], "USART", item[1], altfn - 2, pin
+                        )
                     array_index += 1
                 # TIM special case
                 evaluate_tim(col, outlist[-1], altfn - 2, pin)
@@ -102,7 +107,7 @@ with open(sys.argv[1]) as csv_file:
 
         # Print formatted output
         for i in range(len(todo)):
-            ins = (todo[i][0]).lower() + '_' + (todo[i][1]).lower() + '_'
+            ins = (todo[i][0]).lower() + "_" + (todo[i][1]).lower() + "_"
             #      const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4] = {
             print("const mcu_periph_obj_t mcu_" + ins + "list[" + str(len(outlist[i])) + "] = {")
             for row in outlist[i]:
@@ -112,7 +117,17 @@ with open(sys.argv[1]) as csv_file:
         # Timer special case:
         print("const mcu_tim_pin_obj_t mcu_tim_pin_list[" + str(len(outlist[-1])) + "] = {")
         for row in outlist[-1]:
-            print("    TIM(" + row[0] + ", " + str(row[1]) + ", " + str(row[2]) + ", &pin_" + row[3] + "),")
+            print(
+                "    TIM("
+                + row[0]
+                + ", "
+                + str(row[1])
+                + ", "
+                + str(row[2])
+                + ", &pin_"
+                + row[3]
+                + "),"
+            )
         print("};")
 
     else:
@@ -126,14 +141,22 @@ with open(sys.argv[1]) as csv_file:
             altfn = 0
             pin = row[1]
             if len(pin) < 4:
-                pin = pin[:2] + '0' + pin[2:]
+                pin = pin[:2] + "0" + pin[2:]
             outlist.append([pin, str(ord(row[1][1:2]) - 65), row[1][2:4]])
             line_count += 1
 
         for line in outlist:
-            print("const mcu_pin_obj_t pin_" + line[0] + " = PIN(" + line[1] + ", " + line[2] + ", NO_ADC);")
+            print(
+                "const mcu_pin_obj_t pin_"
+                + line[0]
+                + " = PIN("
+                + line[1]
+                + ", "
+                + line[2]
+                + ", NO_ADC);"
+            )
 
         for line in outlist:
             print("extern const mcu_pin_obj_t pin_" + line[0] + ";")
 
-    print(f'Processed {line_count} lines.')
+    print(f"Processed {line_count} lines.")
diff --git a/ports/stm/tools/parse_pins_csv.py b/ports/stm/tools/parse_pins_csv.py
index 68f6db586..972c6b6a8 100644
--- a/ports/stm/tools/parse_pins_csv.py
+++ b/ports/stm/tools/parse_pins_csv.py
@@ -33,7 +33,7 @@ import sys
 
 # Open target file
 with open(sys.argv[1]) as csv_file:
-    csv_reader = csv.reader(csv_file, delimiter=',')
+    csv_reader = csv.reader(csv_file, delimiter=",")
     line_count = 0
 
     print("STATIC const mp_rom_map_elem_t board_module_globals_table[] = {")
@@ -42,8 +42,8 @@ with open(sys.argv[1]) as csv_file:
         label = row[0]
         pin = row[1]
         if len(pin) < 4:
-            pin = pin[:2] + '0' + pin[2:]
+            pin = pin[:2] + "0" + pin[2:]
         print("{ MP_ROM_QSTR(MP_QSTR_" + label + "), MP_ROM_PTR(&pin_" + pin + ") },")
         line_count += 1
 
-    print(f'Processed {line_count} lines.')
+    print(f"Processed {line_count} lines.")