Merge pull request #443 from dhalbert/3.0_spi3.0.0-alpha.1

non-DMA SPI working; adding this now for testing; will continue with DMA

16 files changed, 1532 insertions, 1854 deletions

diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile
index 916bc559f..3ac4cde9a 100644
--- a/ports/atmel-samd/Makefile
+++ b/ports/atmel-samd/Makefile
@@ -172,6 +172,7 @@ SRC_ASF := \
 	hal/src/hal_i2c_m_sync.c \
 	hal/src/hal_io.c \
 	hal/src/hal_sleep.c \
+	hal/src/hal_spi_m_sync.c \
 	hal/src/hal_timer.c \
 	hal/src/hal_usb_device.c \
 	hpl/core/hpl_init.c \
@@ -251,6 +252,7 @@ SRC_COMMON_HAL = \
 	board/__init__.c \
 	busio/__init__.c \
 	busio/I2C.c \
+	busio/SPI.c \
 	digitalio/__init__.c \
 	digitalio/DigitalInOut.c \
 	microcontroller/__init__.c \
@@ -266,7 +268,6 @@ SRC_COMMON_HAL = \
 	audiobusio/PDMIn.c \
 	audioio/__init__.c \
 	audioio/AudioOut.c \
-	busio/SPI.c \
 	busio/UART.c \
 	neopixel_write/__init__.c \
 	nvm/__init__.c \
diff --git a/ports/atmel-samd/asf4 b/ports/atmel-samd/asf4
-Subproject 7ffa51e117eb6d6b6679febfc77e50d03731b46
+Subproject 72f76894ba08c9de2ec3ae231fb71daaf3eafb1
diff --git a/ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h
index 4a3daaae6..91141bcfc 100644
--- a/ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h
+++ b/ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h
@@ -1,3 +1,17 @@
+// For CircuitPython, use SERCOM settings as prototypes to set
+// the default settings. This file defines these SERCOMs
+//
+// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous
+// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous
+// SERCOM2: USART with hal_usart_sync.c driver: usart synchronous
+
+#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0
+#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY
+
+#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1
+#define PROTOTYPE_SERCOM_USART_SYNC SERCOM2
+
+
 /* Auto-generated config file hpl_sercom_config.h */
 #ifndef HPL_SERCOM_CONFIG_H
 #define HPL_SERCOM_CONFIG_H
@@ -6,138 +20,164 @@
 
 #include <peripheral_clk_config.h>
 
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+// Enable configuration of module
+#ifndef CONF_SERCOM_0_SPI_ENABLE
+#define CONF_SERCOM_0_SPI_ENABLE 1
 #endif
 
-#ifndef CONF_SERCOM_0_I2CM_ENABLE
-#define CONF_SERCOM_0_I2CM_ENABLE 1
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_0_SPI_MODE
+#define CONF_SERCOM_0_SPI_MODE 0x03
 #endif
 
-// <h> Basic
+// <h> Basic Configuration
 
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_0_I2CM_BAUD
-#define CONF_SERCOM_0_I2CM_BAUD 100000
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_0_SPI_RXEN
+#define CONF_SERCOM_0_SPI_RXEN 0x1
 #endif
 
-// </h>
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_0_SPI_CHSIZE
+#define CONF_SERCOM_0_SPI_CHSIZE 0x0
+#endif
 
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 0
+// <o> Baud rate <1-12000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_0_SPI_BAUD
+#define CONF_SERCOM_0_SPI_BAUD 50000
 #endif
 
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
+// </h>
 
-#ifndef CONF_SERCOM_0_I2CM_TRISE
-#define CONF_SERCOM_0_I2CM_TRISE 215
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_0_SPI_ADVANCED
+#define CONF_SERCOM_0_SPI_ADVANCED 0
 #endif
 
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN
-#define CONF_SERCOM_0_I2CM_MEXTTOEN 0
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE
+#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff
 #endif
 
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN
-#define CONF_SERCOM_0_I2CM_SEXTTOEN 0
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_0_SPI_DORD
+#define CONF_SERCOM_0_SPI_DORD 0x0
 #endif
 
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_0_I2CM_LOWTOUT
-#define CONF_SERCOM_0_I2CM_LOWTOUT 0
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_0_SPI_CPOL
+#define CONF_SERCOM_0_SPI_CPOL 0x0
 #endif
 
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_0_I2CM_INACTOUT
-#define CONF_SERCOM_0_I2CM_INACTOUT 0x0
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_0_SPI_CPHA
+#define CONF_SERCOM_0_SPI_CPHA 0x0
 #endif
 
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_0_I2CM_SDAHOLD
-#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_0_SPI_IBON
+#define CONF_SERCOM_0_SPI_IBON 0x0
 #endif
 
 // <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY
-#define CONF_SERCOM_0_I2CM_RUNSTDBY 0
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_0_SPI_RUNSTDBY
+#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0
 #endif
 
 // <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
 // <0=>Keep running
 // <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_0_SPI_DBGSTOP
+#define CONF_SERCOM_0_SPI_DBGSTOP 0
 #endif
 
 // </e>
 
-#ifndef CONF_SERCOM_0_I2CM_SPEED
-#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_0_SPI_AMODE_EN
+#define CONF_SERCOM_0_SPI_AMODE_EN 0
 #endif
-#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300
-#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_0_I2CM_TRISE
-#define CONF_SERCOM_0_I2CM_TRISE 215
+
+#ifndef CONF_SERCOM_0_SPI_AMODE
+#define CONF_SERCOM_0_SPI_AMODE 0
 #endif
 
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_0_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE
-#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-//#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1
-//#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_0_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_0_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2))
+#ifndef CONF_SERCOM_0_SPI_ADDR
+#define CONF_SERCOM_0_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_ADDRMASK
+#define CONF_SERCOM_0_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_SSDE
+#define CONF_SERCOM_0_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_MSSEN
+#define CONF_SERCOM_0_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_PLOADEN
+#define CONF_SERCOM_0_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_0_SPI_RXPO
+#define CONF_SERCOM_0_SPI_RXPO 2
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_0_SPI_TXPO
+#define CONF_SERCOM_0_SPI_TXPO 0
 #endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_0_SPI_BAUD_RATE
+#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1
 #endif
+
 #include <peripheral_clk_config.h>
 
 #ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
@@ -241,7 +281,7 @@
 #define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
 #endif
 #if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
-//#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
 #undef CONF_SERCOM_1_I2CM_TRISE
 #define CONF_SERCOM_1_I2CM_TRISE 215
 #endif
@@ -260,10 +300,10 @@
 	 / (CONF_SERCOM_1_I2CM_BAUD * 10))
 #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
 #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-//#warning Requested I2C baudrate too low, please check
+#warning Requested I2C baudrate too low, please check
 #define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
 #elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
-//#warning Requested I2C baudrate too high, please check
+#warning Requested I2C baudrate too high, please check
 #define CONF_SERCOM_1_I2CM_BAUD_RATE 1
 #else
 #define CONF_SERCOM_1_I2CM_BAUD_RATE                                                                                   \
@@ -275,541 +315,231 @@
 
 #include <peripheral_clk_config.h>
 
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
-#endif
-
-#ifndef CONF_SERCOM_2_I2CM_ENABLE
-#define CONF_SERCOM_2_I2CM_ENABLE 1
-#endif
-
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_2_I2CM_BAUD
-#define CONF_SERCOM_2_I2CM_BAUD 100000
-#endif
-
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_2_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_2_I2CM_ADVANCED_CONFIG 0
-#endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_2_I2CM_TRISE
-#define CONF_SERCOM_2_I2CM_TRISE 215
+#ifndef CONF_SERCOM_2_USART_ENABLE
+#define CONF_SERCOM_2_USART_ENABLE 1
 #endif
 
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_2_I2CM_MEXTTOEN
-#define CONF_SERCOM_2_I2CM_MEXTTOEN 0
-#endif
+// <h> Basic Configuration
 
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_2_I2CM_SEXTTOEN
-#define CONF_SERCOM_2_I2CM_SEXTTOEN 0
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_2_USART_RXEN
+#define CONF_SERCOM_2_USART_RXEN 1
 #endif
 
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_2_I2CM_LOWTOUT
-#define CONF_SERCOM_2_I2CM_LOWTOUT 0
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_2_USART_TXEN
+#define CONF_SERCOM_2_USART_TXEN 1
 #endif
 
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_2_I2CM_INACTOUT
-#define CONF_SERCOM_2_I2CM_INACTOUT 0x0
+// <o> Frame parity
+// <0x0=>No parity
+// <0x1=>Even parity
+// <0x2=>Odd parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_2_USART_PARITY
+#define CONF_SERCOM_2_USART_PARITY 0x0
 #endif
 
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_2_I2CM_SDAHOLD
-#define CONF_SERCOM_2_I2CM_SDAHOLD 0x2
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_2_USART_CHSIZE
+#define CONF_SERCOM_2_USART_CHSIZE 0x0
 #endif
 
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_2_I2CM_RUNSTDBY
-#define CONF_SERCOM_2_I2CM_RUNSTDBY 0
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_2_USART_SBMODE
+#define CONF_SERCOM_2_USART_SBMODE 0
 #endif
 
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE 0
-#endif
-
-// </e>
-
-#ifndef CONF_SERCOM_2_I2CM_SPEED
-#define CONF_SERCOM_2_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_2_I2CM_TRISE < 215 || CONF_SERCOM_2_I2CM_TRISE > 300
-//#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_2_I2CM_TRISE
-#define CONF_SERCOM_2_I2CM_TRISE 215
-#endif
-
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_2_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM2_CORE_FREQUENCY - (CONF_SERCOM_2_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_2_I2CM_TRISE * (CONF_SERCOM_2_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM2_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_2_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_2_I2CM_BAUD_RATE
-#if CONF_SERCOM_2_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-//#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_2_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_2_I2CM_BAUD_BAUDLOW <= 1
-//#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_2_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_2_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2))
-#endif
-#endif
-
-#include <peripheral_clk_config.h>
-
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
-#endif
-
-#ifndef CONF_SERCOM_3_I2CM_ENABLE
-#define CONF_SERCOM_3_I2CM_ENABLE 1
-#endif
-
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_3_I2CM_BAUD
-#define CONF_SERCOM_3_I2CM_BAUD 100000
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_2_USART_BAUD
+#define CONF_SERCOM_2_USART_BAUD 9600
 #endif
 
 // </h>
 
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0
-#endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_3_I2CM_TRISE
-#define CONF_SERCOM_3_I2CM_TRISE 215
-#endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN
-#define CONF_SERCOM_3_I2CM_MEXTTOEN 0
-#endif
-
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN
-#define CONF_SERCOM_3_I2CM_SEXTTOEN 0
-#endif
-
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_3_I2CM_LOWTOUT
-#define CONF_SERCOM_3_I2CM_LOWTOUT 0
-#endif
-
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_3_I2CM_INACTOUT
-#define CONF_SERCOM_3_I2CM_INACTOUT 0x0
-#endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_3_I2CM_SDAHOLD
-#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
 #endif
 
 // <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY
-#define CONF_SERCOM_3_I2CM_RUNSTDBY 0
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_2_USART_RUNSTDBY
+#define CONF_SERCOM_2_USART_RUNSTDBY 0
 #endif
 
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_2_USART_IBON
+#define CONF_SERCOM_2_USART_IBON 0
 #endif
 
-// </e>
-
-#ifndef CONF_SERCOM_3_I2CM_SPEED
-#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300
-//#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_3_I2CM_TRISE
-#define CONF_SERCOM_3_I2CM_TRISE 215
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_2_USART_SFDE
+#define CONF_SERCOM_2_USART_SFDE 0
 #endif
 
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_3_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE
-#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-//#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1
-//#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_3_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_3_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2))
-#endif
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_2_USART_CLODEN
+#define CONF_SERCOM_2_USART_CLODEN 0
 #endif
 
-#include <peripheral_clk_config.h>
-
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+// <o> Operating Mode
+// <0x0=>USART with external clock
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_2_USART_MODE
+#define CONF_SERCOM_2_USART_MODE 0x1
 #endif
 
-#ifndef CONF_SERCOM_4_I2CM_ENABLE
-#define CONF_SERCOM_4_I2CM_ENABLE 1
+// <o> Sample Rate
+// <0x0=>16x arithmetic
+// <0x1=>16x fractional
+// <0x2=>8x arithmetic
+// <0x3=>8x fractional
+// <0x3=>3x
+// <i> How many over-sampling bits used when samling data state
+// <id> usart_arch_sampr
+#ifndef CONF_SERCOM_2_USART_SAMPR
+#define CONF_SERCOM_2_USART_SAMPR 0x0
 #endif
 
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_4_I2CM_BAUD
-#define CONF_SERCOM_4_I2CM_BAUD 100000
-#endif
-
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_4_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_4_I2CM_ADVANCED_CONFIG 0
-#endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_4_I2CM_TRISE
-#define CONF_SERCOM_4_I2CM_TRISE 215
-#endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_4_I2CM_MEXTTOEN
-#define CONF_SERCOM_4_I2CM_MEXTTOEN 0
+// <o> Sample Adjustment
+// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
+// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
+// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
+// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
+// <i> Adjust which samples to use for data sampling in asynchronous mode
+// <id> usart_arch_sampa
+#ifndef CONF_SERCOM_2_USART_SAMPA
+#define CONF_SERCOM_2_USART_SAMPA 0x0
 #endif
 
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_4_I2CM_SEXTTOEN
-#define CONF_SERCOM_4_I2CM_SEXTTOEN 0
+// <o> Fractional Part <0-7>
+// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
+// <id> usart_arch_fractional
+#ifndef CONF_SERCOM_2_USART_FRACTIONAL
+#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
 #endif
 
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_4_I2CM_LOWTOUT
-#define CONF_SERCOM_4_I2CM_LOWTOUT 0
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_2_USART_DORD
+#define CONF_SERCOM_2_USART_DORD 1
 #endif
 
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_4_I2CM_INACTOUT
-#define CONF_SERCOM_4_I2CM_INACTOUT 0x0
-#endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_4_I2CM_SDAHOLD
-#define CONF_SERCOM_4_I2CM_SDAHOLD 0x2
-#endif
+// Does not do anything in UART mode
+#define CONF_SERCOM_2_USART_CPOL 0
 
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_4_I2CM_RUNSTDBY
-#define CONF_SERCOM_4_I2CM_RUNSTDBY 0
+// <o> Encoding Format
+// <0=>No encoding
+// <1=>IrDA encoded
+// <id> usart_arch_enc
+#ifndef CONF_SERCOM_2_USART_ENC
+#define CONF_SERCOM_2_USART_ENC 0
 #endif
 
 // <o> Debug Stop Mode
 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
 // <0=>Keep running
 // <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_4_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_4_I2CM_DEBUG_STOP_MODE 0
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
 #endif
 
 // </e>
 
-#ifndef CONF_SERCOM_4_I2CM_SPEED
-#define CONF_SERCOM_4_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_4_I2CM_TRISE < 215 || CONF_SERCOM_4_I2CM_TRISE > 300
-//#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_4_I2CM_TRISE
-#define CONF_SERCOM_4_I2CM_TRISE 215
+#ifndef CONF_SERCOM_2_USART_CMODE
+#define CONF_SERCOM_2_USART_CMODE 0
 #endif
 
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_4_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM4_CORE_FREQUENCY - (CONF_SERCOM_4_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_4_I2CM_TRISE * (CONF_SERCOM_4_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM4_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_4_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_4_I2CM_BAUD_RATE
-#if CONF_SERCOM_4_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-//#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_4_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_4_I2CM_BAUD_BAUDLOW <= 1
-//#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_4_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_4_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_4_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_4_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_4_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_4_I2CM_BAUD_BAUDLOW / 2))
+#ifndef CONF_SERCOM_2_USART_RXPO
+#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA09 */
 #endif
-#endif
-
-#include <peripheral_clk_config.h>
 
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#ifndef CONF_SERCOM_2_USART_TXPO
+#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA08 */
 #endif
 
-#ifndef CONF_SERCOM_5_I2CM_ENABLE
-#define CONF_SERCOM_5_I2CM_ENABLE 1
+/* Set correct parity settings in register interface based on PARITY setting */
+#if CONF_SERCOM_2_USART_PARITY == 0
+#define CONF_SERCOM_2_USART_PMODE 0
+#define CONF_SERCOM_2_USART_FORM 0
+#else
+#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
+#define CONF_SERCOM_2_USART_FORM 1
 #endif
 
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_5_I2CM_BAUD
-#define CONF_SERCOM_5_I2CM_BAUD 100000
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_2_USART_SAMPR == 0
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
 #endif
-
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_5_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_5_I2CM_ADVANCED_CONFIG 0
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_5_I2CM_TRISE
-#define CONF_SERCOM_5_I2CM_TRISE 215
+#elif CONF_SERCOM_2_USART_SAMPR == 1
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
 #endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_5_I2CM_MEXTTOEN
-#define CONF_SERCOM_5_I2CM_MEXTTOEN 0
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
-
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_5_I2CM_SEXTTOEN
-#define CONF_SERCOM_5_I2CM_SEXTTOEN 0
+#elif CONF_SERCOM_2_USART_SAMPR == 2
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
 #endif
-
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_5_I2CM_LOWTOUT
-#define CONF_SERCOM_5_I2CM_LOWTOUT 0
-#endif
-
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_5_I2CM_INACTOUT
-#define CONF_SERCOM_5_I2CM_INACTOUT 0x0
-#endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_5_I2CM_SDAHOLD
-#define CONF_SERCOM_5_I2CM_SDAHOLD 0x2
-#endif
-
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_5_I2CM_RUNSTDBY
-#define CONF_SERCOM_5_I2CM_RUNSTDBY 0
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
-
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_5_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_5_I2CM_DEBUG_STOP_MODE 0
+#elif CONF_SERCOM_2_USART_SAMPR == 3
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
 #endif
-
-// </e>
-
-#ifndef CONF_SERCOM_5_I2CM_SPEED
-#define CONF_SERCOM_5_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
-#if CONF_SERCOM_5_I2CM_TRISE < 215 || CONF_SERCOM_5_I2CM_TRISE > 300
-//#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_5_I2CM_TRISE
-#define CONF_SERCOM_5_I2CM_TRISE 215
+#elif CONF_SERCOM_2_USART_SAMPR == 4
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
 #endif
-
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_5_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM5_CORE_FREQUENCY - (CONF_SERCOM_5_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_5_I2CM_TRISE * (CONF_SERCOM_5_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM5_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_5_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_5_I2CM_BAUD_RATE
-#if CONF_SERCOM_5_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-//#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_5_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_5_I2CM_BAUD_BAUDLOW <= 1
-//#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_5_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_5_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_5_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_5_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_5_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_5_I2CM_BAUD_BAUDLOW / 2))
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
 #endif
 
diff --git a/ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h
index 804f6f9d0..b8080d059 100644
--- a/ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h
+++ b/ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h
@@ -1,7 +1,3 @@
-// Derived from:
-// Create START project with using six I2C, then six ...
-// then merge all.
-
 /* Auto-generated config file peripheral_clk_config.h */
 #ifndef PERIPHERAL_CLK_CONFIG_H
 #define PERIPHERAL_CLK_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h
index 14327a960..1830c5490 100644
--- a/ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h
+++ b/ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h
@@ -1,3 +1,16 @@
+// For CircuitPython, use SERCOM settings as prototypes to set
+// the default settings. This file defines these SERCOMs
+//
+// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous
+// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous
+// SERCOM2: USART with hal_usart_sync.c driver: usart synchronous
+
+#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0
+#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY
+
+#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1
+#define PROTOTYPE_SERCOM_USART_SYNC SERCOM2
+
 /* Auto-generated config file hpl_sercom_config.h */
 #ifndef HPL_SERCOM_CONFIG_H
 #define HPL_SERCOM_CONFIG_H
@@ -166,390 +179,6 @@
 
 #include <peripheral_clk_config.h>
 
-#ifndef CONF_SERCOM_1_USART_ENABLE
-#define CONF_SERCOM_1_USART_ENABLE 1
-#endif
-
-// <h> Basic Configuration
-
-// <q> Receive buffer enable
-// <i> Enable input buffer in SERCOM module
-// <id> usart_rx_enable
-#ifndef CONF_SERCOM_1_USART_RXEN
-#define CONF_SERCOM_1_USART_RXEN 1
-#endif
-
-// <q> Transmitt buffer enable
-// <i> Enable output buffer in SERCOM module
-// <id> usart_tx_enable
-#ifndef CONF_SERCOM_1_USART_TXEN
-#define CONF_SERCOM_1_USART_TXEN 1
-#endif
-
-// <o> Frame parity
-// <0x0=>No parity
-// <0x1=>Even parity
-// <0x2=>Odd parity
-// <i> Parity bit mode for USART frame
-// <id> usart_parity
-#ifndef CONF_SERCOM_1_USART_PARITY
-#define CONF_SERCOM_1_USART_PARITY 0x0
-#endif
-
-// <o> Character Size
-// <0x0=>8 bits
-// <0x1=>9 bits
-// <0x5=>5 bits
-// <0x6=>6 bits
-// <0x7=>7 bits
-// <i> Data character size in USART frame
-// <id> usart_character_size
-#ifndef CONF_SERCOM_1_USART_CHSIZE
-#define CONF_SERCOM_1_USART_CHSIZE 0x0
-#endif
-
-// <o> Stop Bit
-// <0=>One stop bit
-// <1=>Two stop bits
-// <i> Number of stop bits in USART frame
-// <id> usart_stop_bit
-#ifndef CONF_SERCOM_1_USART_SBMODE
-#define CONF_SERCOM_1_USART_SBMODE 0
-#endif
-
-// <o> Baud rate <1-3000000>
-// <i> USART baud rate setting
-// <id> usart_baud_rate
-#ifndef CONF_SERCOM_1_USART_BAUD
-#define CONF_SERCOM_1_USART_BAUD 9600
-#endif
-
-// </h>
-
-// <e> Advanced configuration
-// <id> usart_advanced
-#ifndef CONF_SERCOM_1_USART_ADVANCED_CONFIG
-#define CONF_SERCOM_1_USART_ADVANCED_CONFIG 0
-#endif
-
-// <q> Run in stand-by
-// <i> Keep the module running in standby sleep mode
-// <id> usart_arch_runstdby
-#ifndef CONF_SERCOM_1_USART_RUNSTDBY
-#define CONF_SERCOM_1_USART_RUNSTDBY 0
-#endif
-
-// <q> Immediate Buffer Overflow Notification
-// <i> Controls when the BUFOVF status bit is asserted
-// <id> usart_arch_ibon
-#ifndef CONF_SERCOM_1_USART_IBON
-#define CONF_SERCOM_1_USART_IBON 0
-#endif
-
-// <q> Start of Frame Detection Enable
-// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
-// <id> usart_arch_sfde
-#ifndef CONF_SERCOM_1_USART_SFDE
-#define CONF_SERCOM_1_USART_SFDE 0
-#endif
-
-// <q> Collision Detection Enable
-// <i> Collision detection enable
-// <id> usart_arch_cloden
-#ifndef CONF_SERCOM_1_USART_CLODEN
-#define CONF_SERCOM_1_USART_CLODEN 0
-#endif
-
-// <o> Operating Mode
-// <0x0=>USART with external clock
-// <0x1=>USART with internal clock
-// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
-// <id> usart_arch_clock_mode
-#ifndef CONF_SERCOM_1_USART_MODE
-#define CONF_SERCOM_1_USART_MODE 0x1
-#endif
-
-// <o> Sample Rate
-// <0x0=>16x arithmetic
-// <0x1=>16x fractional
-// <0x2=>8x arithmetic
-// <0x3=>8x fractional
-// <0x3=>3x
-// <i> How many over-sampling bits used when samling data state
-// <id> usart_arch_sampr
-#ifndef CONF_SERCOM_1_USART_SAMPR
-#define CONF_SERCOM_1_USART_SAMPR 0x0
-#endif
-
-// <o> Sample Adjustment
-// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
-// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
-// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
-// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
-// <i> Adjust which samples to use for data sampling in asynchronous mode
-// <id> usart_arch_sampa
-#ifndef CONF_SERCOM_1_USART_SAMPA
-#define CONF_SERCOM_1_USART_SAMPA 0x0
-#endif
-
-// <o> Fractional Part <0-7>
-// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
-// <id> usart_arch_fractional
-#ifndef CONF_SERCOM_1_USART_FRACTIONAL
-#define CONF_SERCOM_1_USART_FRACTIONAL 0x0
-#endif
-
-// <o> Data Order
-// <0=>MSB is transmitted first
-// <1=>LSB is transmitted first
-// <i> Data order of the data bits in the frame
-// <id> usart_arch_dord
-#ifndef CONF_SERCOM_1_USART_DORD
-#define CONF_SERCOM_1_USART_DORD 1
-#endif
-
-// Does not do anything in UART mode
-#define CONF_SERCOM_1_USART_CPOL 0
-
-// <o> Encoding Format
-// <0=>No encoding
-// <1=>IrDA encoded
-// <id> usart_arch_enc
-#ifndef CONF_SERCOM_1_USART_ENC
-#define CONF_SERCOM_1_USART_ENC 0
-#endif
-
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> usart_arch_dbgstop
-#ifndef CONF_SERCOM_1_USART_DEBUG_STOP_MODE
-#define CONF_SERCOM_1_USART_DEBUG_STOP_MODE 0
-#endif
-
-// </e>
-
-#ifndef CONF_SERCOM_1_USART_INACK
-#define CONF_SERCOM_1_USART_INACK 0x0
-#endif
-
-#ifndef CONF_SERCOM_1_USART_DSNACK
-#define CONF_SERCOM_1_USART_DSNACK 0x0
-#endif
-
-#ifndef CONF_SERCOM_1_USART_MAXITER
-#define CONF_SERCOM_1_USART_MAXITER 0x7
-#endif
-
-#ifndef CONF_SERCOM_1_USART_GTIME
-#define CONF_SERCOM_1_USART_GTIME 0x2
-#endif
-
-#define CONF_SERCOM_1_USART_RXINV 0x0
-#define CONF_SERCOM_1_USART_TXINV 0x0
-
-#ifndef CONF_SERCOM_1_USART_CMODE
-#define CONF_SERCOM_1_USART_CMODE 0
-#endif
-
-#ifndef CONF_SERCOM_1_USART_RXPO
-#define CONF_SERCOM_1_USART_RXPO 1 /* RX is on PIN_PA01 */
-#endif
-
-#ifndef CONF_SERCOM_1_USART_TXPO
-#define CONF_SERCOM_1_USART_TXPO 0 /* TX is on PIN_PA00 */
-#endif
-
-/* Set correct parity settings in register interface based on PARITY setting */
-#if CONF_SERCOM_1_USART_PARITY == 0
-#define CONF_SERCOM_1_USART_PMODE 0
-#define CONF_SERCOM_1_USART_FORM 0
-#else
-#define CONF_SERCOM_1_USART_PMODE CONF_SERCOM_1_USART_PARITY - 1
-#define CONF_SERCOM_1_USART_FORM 1
-#endif
-
-// Calculate BAUD register value in UART mode
-#if CONF_SERCOM_1_USART_SAMPR == 0
-#ifndef CONF_SERCOM_1_USART_BAUD_RATE
-#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
-	65536 - ((65536 * 16.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)
-#endif
-#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
-#endif
-#elif CONF_SERCOM_1_USART_SAMPR == 1
-#ifndef CONF_SERCOM_1_USART_BAUD_RATE
-#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
-	((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 16)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8)
-#endif
-#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
-#endif
-#elif CONF_SERCOM_1_USART_SAMPR == 2
-#ifndef CONF_SERCOM_1_USART_BAUD_RATE
-#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
-	65536 - ((65536 * 8.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)
-#endif
-#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
-#endif
-#elif CONF_SERCOM_1_USART_SAMPR == 3
-#ifndef CONF_SERCOM_1_USART_BAUD_RATE
-#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
-	((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 8)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8)
-#endif
-#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
-#endif
-#elif CONF_SERCOM_1_USART_SAMPR == 4
-#ifndef CONF_SERCOM_1_USART_BAUD_RATE
-#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
-	65536 - ((65536 * 3.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)
-#endif
-#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
-#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
-#endif
-#endif
-
-#include <peripheral_clk_config.h>
-
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
-#endif
-
-#ifndef CONF_SERCOM_0_I2CM_ENABLE
-#define CONF_SERCOM_0_I2CM_ENABLE 1
-#endif
-
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_0_I2CM_BAUD
-#define CONF_SERCOM_0_I2CM_BAUD 100000
-#endif
-
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 0
-#endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_0_I2CM_TRISE
-#define CONF_SERCOM_0_I2CM_TRISE 215
-#endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN
-#define CONF_SERCOM_0_I2CM_MEXTTOEN 0
-#endif
-
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN
-#define CONF_SERCOM_0_I2CM_SEXTTOEN 0
-#endif
-
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_0_I2CM_LOWTOUT
-#define CONF_SERCOM_0_I2CM_LOWTOUT 0
-#endif
-
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_0_I2CM_INACTOUT
-#define CONF_SERCOM_0_I2CM_INACTOUT 0x0
-#endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_0_I2CM_SDAHOLD
-#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2
-#endif
-
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY
-#define CONF_SERCOM_0_I2CM_RUNSTDBY 0
-#endif
-
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0
-#endif
-
-// </e>
-
-#ifndef CONF_SERCOM_0_I2CM_SPEED
-#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300
-#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_0_I2CM_TRISE
-#define CONF_SERCOM_0_I2CM_TRISE 215
-#endif
-
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_0_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE
-#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1
-#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_0_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_0_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2))
-#endif
-#endif
-
-#include <peripheral_clk_config.h>
-
 #ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
 #endif
@@ -685,811 +314,250 @@
 
 #include <peripheral_clk_config.h>
 
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
-#endif
-
-#ifndef CONF_SERCOM_2_I2CM_ENABLE
-#define CONF_SERCOM_2_I2CM_ENABLE 1
-#endif
-
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_2_I2CM_BAUD
-#define CONF_SERCOM_2_I2CM_BAUD 100000
-#endif
-
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_2_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_2_I2CM_ADVANCED_CONFIG 0
-#endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_2_I2CM_TRISE
-#define CONF_SERCOM_2_I2CM_TRISE 215
-#endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_2_I2CM_MEXTTOEN
-#define CONF_SERCOM_2_I2CM_MEXTTOEN 0
-#endif
-
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_2_I2CM_SEXTTOEN
-#define CONF_SERCOM_2_I2CM_SEXTTOEN 0
-#endif
-
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_2_I2CM_LOWTOUT
-#define CONF_SERCOM_2_I2CM_LOWTOUT 0
-#endif
-
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_2_I2CM_INACTOUT
-#define CONF_SERCOM_2_I2CM_INACTOUT 0x0
-#endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_2_I2CM_SDAHOLD
-#define CONF_SERCOM_2_I2CM_SDAHOLD 0x2
-#endif
-
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_2_I2CM_RUNSTDBY
-#define CONF_SERCOM_2_I2CM_RUNSTDBY 0
-#endif
-
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE 0
-#endif
-
-// </e>
-
-#ifndef CONF_SERCOM_2_I2CM_SPEED
-#define CONF_SERCOM_2_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_2_I2CM_TRISE < 215 || CONF_SERCOM_2_I2CM_TRISE > 300
-#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_2_I2CM_TRISE
-#define CONF_SERCOM_2_I2CM_TRISE 215
-#endif
-
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_2_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM2_CORE_FREQUENCY - (CONF_SERCOM_2_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_2_I2CM_TRISE * (CONF_SERCOM_2_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM2_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_2_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_2_I2CM_BAUD_RATE
-#if CONF_SERCOM_2_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_2_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_2_I2CM_BAUD_BAUDLOW <= 1
-#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_2_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_2_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2))
-#endif
-#endif
-
-#include <peripheral_clk_config.h>
-
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#ifndef CONF_SERCOM_2_USART_ENABLE
+#define CONF_SERCOM_2_USART_ENABLE 1
 #endif
 
-#ifndef CONF_SERCOM_3_I2CM_ENABLE
-#define CONF_SERCOM_3_I2CM_ENABLE 1
-#endif
-
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_3_I2CM_BAUD
-#define CONF_SERCOM_3_I2CM_BAUD 100000
-#endif
-
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0
-#endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_3_I2CM_TRISE
-#define CONF_SERCOM_3_I2CM_TRISE 215
-#endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN
-#define CONF_SERCOM_3_I2CM_MEXTTOEN 0
-#endif
-
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN
-#define CONF_SERCOM_3_I2CM_SEXTTOEN 0
-#endif
-
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_3_I2CM_LOWTOUT
-#define CONF_SERCOM_3_I2CM_LOWTOUT 0
-#endif
-
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_3_I2CM_INACTOUT
-#define CONF_SERCOM_3_I2CM_INACTOUT 0x0
-#endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_3_I2CM_SDAHOLD
-#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2
-#endif
-
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY
-#define CONF_SERCOM_3_I2CM_RUNSTDBY 0
-#endif
+// <h> Basic Configuration
 
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_2_USART_RXEN
+#define CONF_SERCOM_2_USART_RXEN 1
 #endif
 
-// </e>
-
-#ifndef CONF_SERCOM_3_I2CM_SPEED
-#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300
-#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_3_I2CM_TRISE
-#define CONF_SERCOM_3_I2CM_TRISE 215
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_2_USART_TXEN
+#define CONF_SERCOM_2_USART_TXEN 1
 #endif
 
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_3_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE
-#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1
-#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_3_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_3_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2))
-#endif
+// <o> Frame parity
+// <0x0=>No parity
+// <0x1=>Even parity
+// <0x2=>Odd parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_2_USART_PARITY
+#define CONF_SERCOM_2_USART_PARITY 0x0
 #endif
 
-#include <peripheral_clk_config.h>
-
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_2_USART_CHSIZE
+#define CONF_SERCOM_2_USART_CHSIZE 0x0
 #endif
 
-#ifndef CONF_SERCOM_4_I2CM_ENABLE
-#define CONF_SERCOM_4_I2CM_ENABLE 1
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_2_USART_SBMODE
+#define CONF_SERCOM_2_USART_SBMODE 0
 #endif
 
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_4_I2CM_BAUD
-#define CONF_SERCOM_4_I2CM_BAUD 100000
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_2_USART_BAUD
+#define CONF_SERCOM_2_USART_BAUD 9600
 #endif
 
 // </h>
 
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_4_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_4_I2CM_ADVANCED_CONFIG 0
-#endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_4_I2CM_TRISE
-#define CONF_SERCOM_4_I2CM_TRISE 215
-#endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_4_I2CM_MEXTTOEN
-#define CONF_SERCOM_4_I2CM_MEXTTOEN 0
-#endif
-
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_4_I2CM_SEXTTOEN
-#define CONF_SERCOM_4_I2CM_SEXTTOEN 0
-#endif
-
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_4_I2CM_LOWTOUT
-#define CONF_SERCOM_4_I2CM_LOWTOUT 0
-#endif
-
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_4_I2CM_INACTOUT
-#define CONF_SERCOM_4_I2CM_INACTOUT 0x0
-#endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_4_I2CM_SDAHOLD
-#define CONF_SERCOM_4_I2CM_SDAHOLD 0x2
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
 #endif
 
 // <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_4_I2CM_RUNSTDBY
-#define CONF_SERCOM_4_I2CM_RUNSTDBY 0
-#endif
-
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_4_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_4_I2CM_DEBUG_STOP_MODE 0
-#endif
-
-// </e>
-
-#ifndef CONF_SERCOM_4_I2CM_SPEED
-#define CONF_SERCOM_4_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_4_I2CM_TRISE < 215 || CONF_SERCOM_4_I2CM_TRISE > 300
-#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_4_I2CM_TRISE
-#define CONF_SERCOM_4_I2CM_TRISE 215
-#endif
-
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_4_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM4_CORE_FREQUENCY - (CONF_SERCOM_4_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_4_I2CM_TRISE * (CONF_SERCOM_4_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM4_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_4_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_4_I2CM_BAUD_RATE
-#if CONF_SERCOM_4_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_4_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_4_I2CM_BAUD_BAUDLOW <= 1
-#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_4_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_4_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_4_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_4_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_4_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_4_I2CM_BAUD_BAUDLOW / 2))
-#endif
-#endif
-
-#include <peripheral_clk_config.h>
-
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_2_USART_RUNSTDBY
+#define CONF_SERCOM_2_USART_RUNSTDBY 0
 #endif
 
-#ifndef CONF_SERCOM_5_I2CM_ENABLE
-#define CONF_SERCOM_5_I2CM_ENABLE 1
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_2_USART_IBON
+#define CONF_SERCOM_2_USART_IBON 0
 #endif
 
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_5_I2CM_BAUD
-#define CONF_SERCOM_5_I2CM_BAUD 100000
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_2_USART_SFDE
+#define CONF_SERCOM_2_USART_SFDE 0
 #endif
 
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_5_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_5_I2CM_ADVANCED_CONFIG 0
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_2_USART_CLODEN
+#define CONF_SERCOM_2_USART_CLODEN 0
 #endif
 
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_5_I2CM_TRISE
-#define CONF_SERCOM_5_I2CM_TRISE 215
+// <o> Operating Mode
+// <0x0=>USART with external clock
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_2_USART_MODE
+#define CONF_SERCOM_2_USART_MODE 0x1
 #endif
 
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_5_I2CM_MEXTTOEN
-#define CONF_SERCOM_5_I2CM_MEXTTOEN 0
+// <o> Sample Rate
+// <0x0=>16x arithmetic
+// <0x1=>16x fractional
+// <0x2=>8x arithmetic
+// <0x3=>8x fractional
+// <0x3=>3x
+// <i> How many over-sampling bits used when samling data state
+// <id> usart_arch_sampr
+#ifndef CONF_SERCOM_2_USART_SAMPR
+#define CONF_SERCOM_2_USART_SAMPR 0x0
 #endif
 
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_5_I2CM_SEXTTOEN
-#define CONF_SERCOM_5_I2CM_SEXTTOEN 0
+// <o> Sample Adjustment
+// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
+// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
+// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
+// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
+// <i> Adjust which samples to use for data sampling in asynchronous mode
+// <id> usart_arch_sampa
+#ifndef CONF_SERCOM_2_USART_SAMPA
+#define CONF_SERCOM_2_USART_SAMPA 0x0
 #endif
 
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_5_I2CM_LOWTOUT
-#define CONF_SERCOM_5_I2CM_LOWTOUT 0
+// <o> Fractional Part <0-7>
+// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
+// <id> usart_arch_fractional
+#ifndef CONF_SERCOM_2_USART_FRACTIONAL
+#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
 #endif
 
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_5_I2CM_INACTOUT
-#define CONF_SERCOM_5_I2CM_INACTOUT 0x0
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_2_USART_DORD
+#define CONF_SERCOM_2_USART_DORD 1
 #endif
 
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_5_I2CM_SDAHOLD
-#define CONF_SERCOM_5_I2CM_SDAHOLD 0x2
-#endif
+// Does not do anything in UART mode
+#define CONF_SERCOM_2_USART_CPOL 0
 
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_5_I2CM_RUNSTDBY
-#define CONF_SERCOM_5_I2CM_RUNSTDBY 0
+// <o> Encoding Format
+// <0=>No encoding
+// <1=>IrDA encoded
+// <id> usart_arch_enc
+#ifndef CONF_SERCOM_2_USART_ENC
+#define CONF_SERCOM_2_USART_ENC 0
 #endif
 
 // <o> Debug Stop Mode
 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
 // <0=>Keep running
 // <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_5_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_5_I2CM_DEBUG_STOP_MODE 0
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
 #endif
 
 // </e>
 
-#ifndef CONF_SERCOM_5_I2CM_SPEED
-#define CONF_SERCOM_5_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_5_I2CM_TRISE < 215 || CONF_SERCOM_5_I2CM_TRISE > 300
-#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_5_I2CM_TRISE
-#define CONF_SERCOM_5_I2CM_TRISE 215
+#ifndef CONF_SERCOM_2_USART_INACK
+#define CONF_SERCOM_2_USART_INACK 0x0
 #endif
 
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_5_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM5_CORE_FREQUENCY - (CONF_SERCOM_5_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_5_I2CM_TRISE * (CONF_SERCOM_5_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM5_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_5_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_5_I2CM_BAUD_RATE
-#if CONF_SERCOM_5_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_5_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_5_I2CM_BAUD_BAUDLOW <= 1
-#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_5_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_5_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_5_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_5_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_5_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_5_I2CM_BAUD_BAUDLOW / 2))
+#ifndef CONF_SERCOM_2_USART_DSNACK
+#define CONF_SERCOM_2_USART_DSNACK 0x0
 #endif
-#endif
-
-#include <peripheral_clk_config.h>
 
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#ifndef CONF_SERCOM_2_USART_MAXITER
+#define CONF_SERCOM_2_USART_MAXITER 0x7
 #endif
 
-#ifndef CONF_SERCOM_6_I2CM_ENABLE
-#define CONF_SERCOM_6_I2CM_ENABLE 1
+#ifndef CONF_SERCOM_2_USART_GTIME
+#define CONF_SERCOM_2_USART_GTIME 0x2
 #endif
 
-// <h> Basic
+#define CONF_SERCOM_2_USART_RXINV 0x0
+#define CONF_SERCOM_2_USART_TXINV 0x0
 
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_6_I2CM_BAUD
-#define CONF_SERCOM_6_I2CM_BAUD 100000
+#ifndef CONF_SERCOM_2_USART_CMODE
+#define CONF_SERCOM_2_USART_CMODE 0
 #endif
 
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_6_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_6_I2CM_ADVANCED_CONFIG 0
-#endif
-
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_6_I2CM_TRISE
-#define CONF_SERCOM_6_I2CM_TRISE 215
-#endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_6_I2CM_MEXTTOEN
-#define CONF_SERCOM_6_I2CM_MEXTTOEN 0
-#endif
-
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_6_I2CM_SEXTTOEN
-#define CONF_SERCOM_6_I2CM_SEXTTOEN 0
-#endif
-
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_6_I2CM_LOWTOUT
-#define CONF_SERCOM_6_I2CM_LOWTOUT 0
-#endif
-
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_6_I2CM_INACTOUT
-#define CONF_SERCOM_6_I2CM_INACTOUT 0x0
-#endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_6_I2CM_SDAHOLD
-#define CONF_SERCOM_6_I2CM_SDAHOLD 0x2
-#endif
-
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_6_I2CM_RUNSTDBY
-#define CONF_SERCOM_6_I2CM_RUNSTDBY 0
-#endif
-
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_6_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_6_I2CM_DEBUG_STOP_MODE 0
+#ifndef CONF_SERCOM_2_USART_RXPO
+#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA08 */
 #endif
 
-// </e>
-
-#ifndef CONF_SERCOM_6_I2CM_SPEED
-#define CONF_SERCOM_6_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
-#endif
-#if CONF_SERCOM_6_I2CM_TRISE < 215 || CONF_SERCOM_6_I2CM_TRISE > 300
-#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_6_I2CM_TRISE
-#define CONF_SERCOM_6_I2CM_TRISE 215
+#ifndef CONF_SERCOM_2_USART_TXPO
+#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA09 */
 #endif
 
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_6_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM6_CORE_FREQUENCY - (CONF_SERCOM_6_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_6_I2CM_TRISE * (CONF_SERCOM_6_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM6_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_6_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_6_I2CM_BAUD_RATE
-#if CONF_SERCOM_6_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_6_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_6_I2CM_BAUD_BAUDLOW <= 1
-#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_6_I2CM_BAUD_RATE 1
+/* Set correct parity settings in register interface based on PARITY setting */
+#if CONF_SERCOM_2_USART_PARITY == 0
+#define CONF_SERCOM_2_USART_PMODE 0
+#define CONF_SERCOM_2_USART_FORM 0
 #else
-#define CONF_SERCOM_6_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_6_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_6_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_6_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_6_I2CM_BAUD_BAUDLOW / 2))
-#endif
-#endif
-
-#include <peripheral_clk_config.h>
-
-#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
-#endif
-
-#ifndef CONF_SERCOM_7_I2CM_ENABLE
-#define CONF_SERCOM_7_I2CM_ENABLE 1
-#endif
-
-// <h> Basic
-
-// <o> I2C Bus clock speed (Hz) <1-400000>
-// <i> I2C Bus clock (SCL) speed measured in Hz
-// <id> i2c_master_baud_rate
-#ifndef CONF_SERCOM_7_I2CM_BAUD
-#define CONF_SERCOM_7_I2CM_BAUD 100000
-#endif
-
-// </h>
-
-// <e> Advanced
-// <id> i2c_master_advanced
-#ifndef CONF_SERCOM_7_I2CM_ADVANCED_CONFIG
-#define CONF_SERCOM_7_I2CM_ADVANCED_CONFIG 0
+#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
+#define CONF_SERCOM_2_USART_FORM 1
 #endif
 
-// <o> TRise (ns) <0-300>
-// <i> Determined by the bus impedance, check electric characteristics in the datasheet
-// <i> Standard Fast Mode: typical 215ns, max 300ns
-// <i> Fast Mode +: typical 60ns, max 100ns
-// <i> High Speed Mode: typical 20ns, max 40ns
-// <id> i2c_master_arch_trise
-
-#ifndef CONF_SERCOM_7_I2CM_TRISE
-#define CONF_SERCOM_7_I2CM_TRISE 215
-#endif
-
-// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
-// <i> This enables the master SCL low extend time-out
-// <id> i2c_master_arch_mexttoen
-#ifndef CONF_SERCOM_7_I2CM_MEXTTOEN
-#define CONF_SERCOM_7_I2CM_MEXTTOEN 0
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_2_USART_SAMPR == 0
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
 #endif
-
-// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
-// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
-// <id> i2c_master_arch_sexttoen
-#ifndef CONF_SERCOM_7_I2CM_SEXTTOEN
-#define CONF_SERCOM_7_I2CM_SEXTTOEN 0
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
-
-// <q> SCL Low Time-Out (LOWTOUT)
-// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
-// <id> i2c_master_arch_lowtout
-#ifndef CONF_SERCOM_7_I2CM_LOWTOUT
-#define CONF_SERCOM_7_I2CM_LOWTOUT 0
+#elif CONF_SERCOM_2_USART_SAMPR == 1
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
 #endif
-
-// <o> Inactive Time-Out (INACTOUT)
-// <0x0=>Disabled
-// <0x1=>5-6 SCL cycle time-out(50-60us)
-// <0x2=>10-11 SCL cycle time-out(100-110us)
-// <0x3=>20-21 SCL cycle time-out(200-210us)
-// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
-// <id> i2c_master_arch_inactout
-#ifndef CONF_SERCOM_7_I2CM_INACTOUT
-#define CONF_SERCOM_7_I2CM_INACTOUT 0x0
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
-
-// <o> SDA Hold Time (SDAHOLD)
-// <0=>Disabled
-// <1=>50-100ns hold time
-// <2=>300-600ns hold time
-// <3=>400-800ns hold time
-// <i> Defines the SDA hold time with respect to the negative edge of SCL
-// <id> i2c_master_arch_sdahold
-#ifndef CONF_SERCOM_7_I2CM_SDAHOLD
-#define CONF_SERCOM_7_I2CM_SDAHOLD 0x2
+#elif CONF_SERCOM_2_USART_SAMPR == 2
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
 #endif
-
-// <q> Run in stand-by
-// <i> Determine if the module shall run in standby sleep mode
-// <id> i2c_master_arch_runstdby
-#ifndef CONF_SERCOM_7_I2CM_RUNSTDBY
-#define CONF_SERCOM_7_I2CM_RUNSTDBY 0
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
-
-// <o> Debug Stop Mode
-// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
-// <0=>Keep running
-// <1=>Halt
-// <id> i2c_master_arch_dbgstop
-#ifndef CONF_SERCOM_7_I2CM_DEBUG_STOP_MODE
-#define CONF_SERCOM_7_I2CM_DEBUG_STOP_MODE 0
+#elif CONF_SERCOM_2_USART_SAMPR == 3
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
 #endif
-
-// </e>
-
-#ifndef CONF_SERCOM_7_I2CM_SPEED
-#define CONF_SERCOM_7_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
-#if CONF_SERCOM_7_I2CM_TRISE < 215 || CONF_SERCOM_7_I2CM_TRISE > 300
-#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
-#undef CONF_SERCOM_7_I2CM_TRISE
-#define CONF_SERCOM_7_I2CM_TRISE 215
+#elif CONF_SERCOM_2_USART_SAMPR == 4
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
 #endif
-
-//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
-// BAUD + BAUDLOW = --------------------------------------------------------------------
-//                  i2c_scl_freq
-// BAUD:    register value low  [7:0]
-// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
-#define CONF_SERCOM_7_I2CM_BAUD_BAUDLOW                                                                                \
-	(((CONF_GCLK_SERCOM7_CORE_FREQUENCY - (CONF_SERCOM_7_I2CM_BAUD * 10)                                               \
-	   - (CONF_SERCOM_7_I2CM_TRISE * (CONF_SERCOM_7_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM7_CORE_FREQUENCY / 10000)      \
-	      / 1000))                                                                                                     \
-	      * 10                                                                                                         \
-	  + 5)                                                                                                             \
-	 / (CONF_SERCOM_7_I2CM_BAUD * 10))
-#ifndef CONF_SERCOM_7_I2CM_BAUD_RATE
-#if CONF_SERCOM_7_I2CM_BAUD_BAUDLOW > (0xFF * 2)
-#warning Requested I2C baudrate too low, please check
-#define CONF_SERCOM_7_I2CM_BAUD_RATE 0xFF
-#elif CONF_SERCOM_7_I2CM_BAUD_BAUDLOW <= 1
-#warning Requested I2C baudrate too high, please check
-#define CONF_SERCOM_7_I2CM_BAUD_RATE 1
-#else
-#define CONF_SERCOM_7_I2CM_BAUD_RATE                                                                                   \
-	((CONF_SERCOM_7_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
-	     ? (CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
-	     : (CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2))
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
 #endif
 #endif
 
diff --git a/ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
index d7786a7a2..09744f279 100644
--- a/ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
+++ b/ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
@@ -1,113 +1,926 @@
-// Derived from: Auto-generated config file peripheral_clk_config.h
-// Boilerplate removed.
-
+/* Auto-generated config file peripheral_clk_config.h */
 #ifndef PERIPHERAL_CLK_CONFIG_H
 #define PERIPHERAL_CLK_CONFIG_H
 
-// ADC
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <y> ADC Clock Source
+// <id> adc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC0_SRC
 #define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_ADC0_FREQUENCY 120000000
+#endif
+
+/**
+ * \def CONF_GCLK_ADC0_FREQUENCY
+ * \brief ADC0's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC0_FREQUENCY
+#define CONF_GCLK_ADC0_FREQUENCY 12000000
+#endif
+
+// <y> DAC Clock Source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
 
-// DAC
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <id> dac_gclk_selection
+// <i> Select the clock source for DAC.
+#ifndef CONF_GCLK_DAC_SRC
 #define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_DAC_FREQUENCY 120000000
+#endif
+
+/**
+ * \def CONF_GCLK_DAC_FREQUENCY
+ * \brief DAC's Clock frequency
+ */
+#ifndef CONF_GCLK_DAC_FREQUENCY
+#define CONF_GCLK_DAC_FREQUENCY 12000000
+#endif
+
+// <y> EVSYS Channel 0 Clock Source
+// <id> evsys_clk_selection_0
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
 
-// EVSYS
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 0.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 1 Clock Source
+// <id> evsys_clk_selection_1
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
 
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 1.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 2 Clock Source
+// <id> evsys_clk_selection_2
 
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 2.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 3 Clock Source
+// <id> evsys_clk_selection_3
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
 
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 3.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 4 Clock Source
+// <id> evsys_clk_selection_4
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
 
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 4.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 5 Clock Source
+// <id> evsys_clk_selection_5
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
 
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 5.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 6 Clock Source
+// <id> evsys_clk_selection_6
 
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 6.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 7 Clock Source
+// <id> evsys_clk_selection_7
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
 
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 7.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 8 Clock Source
+// <id> evsys_clk_selection_8
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
 
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 8.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 9 Clock Source
+// <id> evsys_clk_selection_9
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
 
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 9.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 10 Clock Source
+// <id> evsys_clk_selection_10
 
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 10.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000.0
+#endif
+
+// <y> EVSYS Channel 11 Clock Source
+// <id> evsys_clk_selection_11
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
 
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 11.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC
 #define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
-#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000.0
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
 
-// CPU: 120 MHz
-#define CONF_CPU_FREQUENCY 120000000
+#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000.0
+#endif
 
-// RTC
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 12000000
+#endif
+
+// <y> RTC Clock Source
+// <id> rtc_clk_selection
+// <RTC_CLOCK_SOURCE"> RTC source
+// <i> Select the clock source for RTC.
+#ifndef CONF_GCLK_RTC_SRC
 #define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_RTC_FREQUENCY
+ * \brief RTC's Clock frequency
+ */
+#ifndef CONF_GCLK_RTC_FREQUENCY
 #define CONF_GCLK_RTC_FREQUENCY 1024
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
 
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
 
-// SERCOM
-// Use 48 MHz clock for CORE, and 32kHz clock for SLOW.
-// 120 MHz is too fast for CORE.
-// Slow is only needed for SMBus, it appears.
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
 
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM0_CORE_SRC
 #define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
 #define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
+ * \brief SERCOM0's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
 #define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+ * \brief SERCOM0's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
 #define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
 
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM1_CORE_SRC
 #define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
 #define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
+ * \brief SERCOM1's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
 #define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+ * \brief SERCOM1's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
 #define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
 
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM2_CORE_SRC
 #define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
 #define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
+ * \brief SERCOM2's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
 #define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+ * \brief SERCOM2's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
 #define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
 
-#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
-#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
-#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000
-#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
 
-#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
-#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 48000000
-#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
 
-#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
-#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 48000000
-#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
 
-#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
-#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
-#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 48000000
-#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
 
-#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
-#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
-#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 48000000
-#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 32768
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
 
-// TC
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC0_SRC
 #define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC0_FREQUENCY
+ * \brief TC0's Clock frequency
+ */
+#ifndef CONF_GCLK_TC0_FREQUENCY
 #define CONF_GCLK_TC0_FREQUENCY 12000000
+#endif
+
+// <y> USB Clock Source
+// <id> usb_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
 
-// USB
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for USB.
+#ifndef CONF_GCLK_USB_SRC
 #define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+
+#endif
+
+/**
+ * \def CONF_GCLK_USB_FREQUENCY
+ * \brief USB's Clock frequency
+ */
+#ifndef CONF_GCLK_USB_FREQUENCY
 #define CONF_GCLK_USB_FREQUENCY 48000000
+#endif
+
+// <<< end of configuration section >>>
 
 #endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
index a2cd84417..6e975fdc1 100644
--- a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
@@ -13,7 +13,7 @@ CHIP_FAMILY = samd21
 # Include these Python libraries in firmware.
 ### TODO(halbert): disable some of these frozen modules; they don't fit in 3.0.0 build while internalfs
 ### is in use
-FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_BusDevice
-FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_LIS3DH
-FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel
+###FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_BusDevice
+###FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_LIS3DH
+###FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel
 ###FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Thermistor
diff --git a/ports/atmel-samd/boards/metro_m4_express/pins.c b/ports/atmel-samd/boards/metro_m4_express/pins.c
index ea6bab9c1..f6ad05f2d 100644
--- a/ports/atmel-samd/boards/metro_m4_express/pins.c
+++ b/ports/atmel-samd/boards/metro_m4_express/pins.c
@@ -7,9 +7,9 @@ STATIC const mp_map_elem_t board_global_dict_table[] = {
     { MP_OBJ_NEW_QSTR(MP_QSTR_A0),  (mp_obj_t)&pin_PA02 },
     { MP_OBJ_NEW_QSTR(MP_QSTR_A1),  (mp_obj_t)&pin_PA05 },
     { MP_OBJ_NEW_QSTR(MP_QSTR_A2),  (mp_obj_t)&pin_PA06 },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_A3),  (mp_obj_t)&pin_PA07 },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A3),  (mp_obj_t)&pin_PA04 },
     { MP_OBJ_NEW_QSTR(MP_QSTR_A4),  (mp_obj_t)&pin_PA11 },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_A5),  (mp_obj_t)&pin_PA04 },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A5),  (mp_obj_t)&pin_PA07 },
 
 
     { MP_OBJ_NEW_QSTR(MP_QSTR_D0),  (mp_obj_t)&pin_PA23 },
@@ -32,8 +32,8 @@ STATIC const mp_map_elem_t board_global_dict_table[] = {
 
     { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), (mp_obj_t)&pin_PB17 },
 
-    { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), (mp_obj_t)&pin_PA12 },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), (mp_obj_t)&pin_PA13 },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), (mp_obj_t)&pin_PA13 },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), (mp_obj_t)&pin_PA12 },
     { MP_OBJ_NEW_QSTR(MP_QSTR_MISO), (mp_obj_t)&pin_PA15 },
 
     { MP_OBJ_NEW_QSTR(MP_QSTR_LED_RX), (mp_obj_t)&pin_PB06 },
diff --git a/ports/atmel-samd/common-hal/busio/I2C.c b/ports/atmel-samd/common-hal/busio/I2C.c
index e8c90c924..31b5767e7 100644
--- a/ports/atmel-samd/common-hal/busio/I2C.c
+++ b/ports/atmel-samd/common-hal/busio/I2C.c
@@ -72,7 +72,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
 
 
     // Set up I2C clocks on sercom.
-    sercom_clock_init(sercom, sercom_index);
+    samd_peripheral_sercom_clock_init(sercom, sercom_index);
 
     if (i2c_m_sync_init(&self->i2c_desc, sercom) != ERR_NONE) {
             mp_raise_OSError(MP_EIO);
diff --git a/ports/atmel-samd/common-hal/busio/SPI.c b/ports/atmel-samd/common-hal/busio/SPI.c
index c1b13cec8..21fed5d12 100644
--- a/ports/atmel-samd/common-hal/busio/SPI.c
+++ b/ports/atmel-samd/common-hal/busio/SPI.c
@@ -25,25 +25,35 @@
  */
 
 #include "shared-bindings/busio/SPI.h"
-#include "py/nlr.h"
+#include "py/mperrno.h"
 #include "py/runtime.h"
-#include "rgb_led_status.h"
-#include "samd21_pins.h"
-#include "shared_dma.h"
 
-// We use ENABLE registers below we don't want to treat as a macro.
-#undef ENABLE
+#include "hpl_sercom_config.h"
+#include "peripheral_clk_config.h"
+
+#include "hal/include/hal_gpio.h"
+#include "hal/include/hal_spi_m_sync.h"
+#include "hal/include/hpl_spi_m_sync.h"
+
+#include "peripherals.h"
+#include "pins.h"
+#include "shared_dma.h"
 
-// Number of times to try to send packet if failed.
-#define TIMEOUT 1
+// Convert frequency to clock-speed-dependent value. Return 0 if out of range.
+static uint8_t baudrate_to_baud_reg_value(const uint32_t baudrate) {
+    uint32_t baud_reg_value = (uint32_t) (((float) PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY /
+                                           (2 * baudrate)) + 0.5f);
+    if (baud_reg_value > 0xff) {
+        return 0;
+    }
+    return (uint8_t) baud_reg_value;
+}
 
 void common_hal_busio_spi_construct(busio_spi_obj_t *self,
         const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi,
         const mcu_pin_obj_t * miso) {
-    struct spi_config config_spi_master;
-    spi_get_config_defaults(&config_spi_master);
-
     Sercom* sercom = NULL;
+    uint8_t sercom_index;
     uint32_t clock_pinmux = 0;
     bool mosi_none = mosi == mp_const_none;
     bool miso_none = miso == mp_const_none;
@@ -52,8 +62,10 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
     uint8_t clock_pad = 0;
     uint8_t mosi_pad = 0;
     uint8_t miso_pad = 0;
+    uint8_t dopo = 255;
     for (int i = 0; i < NUM_SERCOMS_PER_PIN; i++) {
         Sercom* potential_sercom = clock->sercom[i].sercom;
+        sercom_index = clock->sercom[i].index; // 2 for SERCOM2, etc.
         if (potential_sercom == NULL ||
         #if defined(MICROPY_HW_APA102_SCK) && defined(MICROPY_HW_APA102_MOSI) && !defined(CIRCUITPY_BITBANG_APA102)
             (potential_sercom->SPI.CTRLA.bit.ENABLE != 0 &&
@@ -66,11 +78,18 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
         }
         clock_pinmux = PINMUX(clock->pin, (i == 0) ? MUX_C : MUX_D);
         clock_pad = clock->sercom[i].pad;
+        if (!samd_peripheral_valid_spi_clock_pad(clock_pad)) {
+            continue;
+        }
         for (int j = 0; j < NUM_SERCOMS_PER_PIN; j++) {
             if (!mosi_none) {
                 if(potential_sercom == mosi->sercom[j].sercom) {
                     mosi_pinmux = PINMUX(mosi->pin, (j == 0) ? MUX_C : MUX_D);
                     mosi_pad = mosi->sercom[j].pad;
+                    dopo = samd_peripheral_get_spi_dopo(clock_pad, mosi_pad);
+                    if (dopo > 0x3) {
+                        continue;  // pad combination not possible
+                    }
                     if (miso_none) {
                         sercom = potential_sercom;
                         break;
@@ -101,62 +120,52 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
         mp_raise_ValueError("Invalid pins");
     }
 
-    // Depends on where MOSI and CLK are.
-    uint8_t dopo = 8;
-    if (clock_pad == 1) {
-        if (mosi_pad == 0) {
-            dopo = 0;
-        } else if (mosi_pad == 3) {
-            dopo = 2;
-        }
-    } else if (clock_pad == 3) {
-        if (mosi_pad == 0) {
-            dopo = 3;
-        } else if (mosi_pad == 2) {
-            dopo = 1;
-        }
-    }
-    if (dopo == 8) {
-        mp_raise_ValueError("MOSI and clock pins incompatible");
+    // Set up SPI clocks on SERCOM.
+    samd_peripheral_sercom_clock_init(sercom, sercom_index);
+    
+    if (spi_m_sync_init(&self->spi_desc, sercom) != ERR_NONE) {
+        mp_raise_OSError(MP_EIO);
     }
+    
+    hri_sercomspi_write_CTRLA_DOPO_bf(sercom, dopo);
+    hri_sercomspi_write_CTRLA_DIPO_bf(sercom, miso_pad);
 
-    config_spi_master.mux_setting = (dopo << SERCOM_SPI_CTRLA_DOPO_Pos) |
-        (miso_pad << SERCOM_SPI_CTRLA_DIPO_Pos);
-
-    // Map pad to pinmux through a short array.
-    uint32_t *pinmuxes[4] = {&config_spi_master.pinmux_pad0,
-                             &config_spi_master.pinmux_pad1,
-                             &config_spi_master.pinmux_pad2,
-                             &config_spi_master.pinmux_pad3};
-    // Set other pinmuxes to unused so we don't accidentally change other pin
-    // state.
-    for (uint8_t i = 0; i < 4; i++) {
-        *pinmuxes[i] = PINMUX_UNUSED;
+    // Always start at 250khz which is what SD cards need. They are sensitive to
+    // SPI bus noise before they are put into SPI mode.
+    uint8_t baud_value = baudrate_to_baud_reg_value(250000);
+    if (baud_value == 0) {
+        mp_raise_RuntimeError("SPI initial baudrate out of range.");
     }
-    *pinmuxes[clock_pad] = clock_pinmux;
-    self->clock_pin = clock->pin;
+    if (spi_m_sync_set_baudrate(&self->spi_desc, baud_value) != ERR_NONE) {
+        // spi_m_sync_set_baudrate does not check for validity, just whether the device is
+        // busy or not
+        mp_raise_OSError(MP_EIO);
+    }
+        
+    gpio_set_pin_pull_mode(clock->pin, GPIO_PULL_OFF);
+    gpio_set_pin_function(clock->pin, clock_pinmux);
     claim_pin(clock);
-    self->MOSI_pin = NO_PIN;
-    if (!mosi_none) {
-        *pinmuxes[mosi_pad] = mosi_pinmux;
+    self->clock_pin = clock->pin;
+
+    if (mosi_none) {
+        self->MOSI_pin = NO_PIN;
+    } else {
+        gpio_set_pin_pull_mode(mosi->pin, GPIO_PULL_OFF);
+        gpio_set_pin_function(mosi->pin, mosi_pinmux);
         self->MOSI_pin = mosi->pin;
         claim_pin(mosi);
     }
-    self->MISO_pin = NO_PIN;
-    if (!miso_none) {
-        *pinmuxes[miso_pad] = miso_pinmux;
+
+    if (miso_none) {
+        self->MISO_pin = NO_PIN;
+    } else {
+        gpio_set_pin_pull_mode(miso->pin, GPIO_PULL_OFF);
+        gpio_set_pin_function(miso->pin, miso_pinmux);
         self->MISO_pin = miso->pin;
         claim_pin(miso);
     }
 
-    // Always start at 250khz which is what SD cards need. They are sensitive to
-    // SPI bus noise before they are put into SPI mode.
-    self->current_baudrate = 250000;
-    config_spi_master.mode_specific.master.baudrate = self->current_baudrate;
-
-    spi_init(&self->spi_master_instance, sercom, &config_spi_master);
-
-    spi_enable(&self->spi_master_instance);
+    spi_m_sync_enable(&self->spi_desc);
 }
 
 bool common_hal_busio_spi_deinited(busio_spi_obj_t *self) {
@@ -167,7 +176,8 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
     if (common_hal_busio_spi_deinited(self)) {
         return;
     }
-    spi_disable(&self->spi_master_instance);
+    spi_m_sync_disable(&self->spi_desc);
+    spi_m_sync_deinit(&self->spi_desc);
     reset_pin(self->clock_pin);
     reset_pin(self->MOSI_pin);
     reset_pin(self->MISO_pin);
@@ -176,49 +186,45 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
 
 bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
         uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
-    // TODO(tannewt): Check baudrate first before changing it.
-    if (baudrate != self->current_baudrate) {
-        enum status_code status = spi_set_baudrate(&self->spi_master_instance, baudrate);
-        if (status != STATUS_OK) {
-            return false;
-        }
-        self->current_baudrate = baudrate;
+    uint8_t baud_reg_value = baudrate_to_baud_reg_value(baudrate);
+    if (baud_reg_value == 0) {
+        mp_raise_ValueError("baudrate out of range");
     }
 
-    SercomSpi *const spi_module = &(self->spi_master_instance.hw->SPI);
+    void * hw = self->spi_desc.dev.prvt;
     // If the settings are already what we want then don't reset them.
-    if (spi_module->CTRLA.bit.CPHA == phase &&
-        spi_module->CTRLA.bit.CPOL == polarity &&
-        spi_module->CTRLB.bit.CHSIZE == (bits - 8)) {
+    if (hri_sercomspi_get_CTRLA_CPHA_bit(hw) == phase &&
+        hri_sercomspi_get_CTRLA_CPOL_bit(hw) == polarity &&
+        hri_sercomspi_read_CTRLB_CHSIZE_bf(hw) == ((uint32_t)bits - 8) &&
+        hri_sercomspi_read_BAUD_BAUD_bf(hw) == baud_reg_value) {
         return true;
     }
 
-    spi_disable(&self->spi_master_instance);
-    while (spi_is_syncing(&self->spi_master_instance)) {
-        /* Wait until the synchronization is complete */
-    }
-
-    spi_module->CTRLA.bit.CPHA = phase;
-    spi_module->CTRLA.bit.CPOL = polarity;
-    spi_module->CTRLB.bit.CHSIZE = bits - 8;
-
-    while (spi_is_syncing(&self->spi_master_instance)) {
-        /* Wait until the synchronization is complete */
-    }
+    // Disable, set values (most or all are enable-protected), and re-enable. 
+    spi_m_sync_disable(&self->spi_desc);
+    hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
 
-    /* Enable the module */
-    spi_enable(&self->spi_master_instance);
+    hri_sercomspi_write_CTRLA_CPHA_bit(hw, phase);
+    hri_sercomspi_write_CTRLA_CPOL_bit(hw, polarity);
+    hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, bits - 8);
+    hri_sercomspi_write_BAUD_BAUD_bf(hw, baud_reg_value);
+    hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
 
-    while (spi_is_syncing(&self->spi_master_instance)) {
-        /* Wait until the synchronization is complete */
-    }
+    spi_m_sync_enable(&self->spi_desc);
+    hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
 
     return true;
 }
 
 bool common_hal_busio_spi_try_lock(busio_spi_obj_t *self) {
-    self->has_lock = spi_lock(&self->spi_master_instance) == STATUS_OK;
-    return self->has_lock;
+    bool grabbed_lock = false;
+    CRITICAL_SECTION_ENTER()
+        if (!self->has_lock) {
+            grabbed_lock = true;
+            self->has_lock = true;
+        }
+    CRITICAL_SECTION_LEAVE();
+    return grabbed_lock;
 }
 
 bool common_hal_busio_spi_has_lock(busio_spi_obj_t *self) {
@@ -227,7 +233,6 @@ bool common_hal_busio_spi_has_lock(busio_spi_obj_t *self) {
 
 void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
     self->has_lock = false;
-    spi_unlock(&self->spi_master_instance);
 }
 
 bool common_hal_busio_spi_write(busio_spi_obj_t *self,
@@ -235,13 +240,15 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self,
     if (len == 0) {
         return true;
     }
-    enum status_code status;
-    if (len >= 16) {
-        status = shared_dma_write(self->spi_master_instance.hw, data, len);
-    } else {
-        status = spi_write_buffer_wait(&self->spi_master_instance, data, len);
-    }
-    return status == STATUS_OK;
+    int32_t status;
+//    if (len >= 16) {
+//        status = shared_dma_write(self->spi_desc.dev.prvt, data, len);
+//    } else {
+        struct io_descriptor *spi_io;
+        spi_m_sync_get_io_descriptor(&self->spi_desc, &spi_io);
+        status = spi_io->write(spi_io, data, len);
+//    }
+        return status > 0; // Status is number of chars read or an error code < 0.
 }
 
 bool common_hal_busio_spi_read(busio_spi_obj_t *self,
@@ -249,11 +256,16 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self,
     if (len == 0) {
         return true;
     }
-    enum status_code status;
-    if (len >= 16) {
-        status = shared_dma_read(self->spi_master_instance.hw, data, len, write_value);
-    } else {
-        status = spi_read_buffer_wait(&self->spi_master_instance, data, len, write_value);
-    }
-    return status == STATUS_OK;
+    int32_t status;
+//    if (len >= 16) {
+//        status = shared_dma_read(self->spi_desc.dev.prvt, data, len, write_value);
+//    } else {
+        self->spi_desc.dev.dummy_byte = write_value;
+
+        struct io_descriptor *spi_io;
+        spi_m_sync_get_io_descriptor(&self->spi_desc, &spi_io);
+
+        status = spi_io->read(spi_io, data, len);
+//    }
+        return status > 0; // Status is number of chars read or an error code < 0.
 }
diff --git a/ports/atmel-samd/common-hal/busio/SPI.h b/ports/atmel-samd/common-hal/busio/SPI.h
index 2644c876f..2fced6d64 100644
--- a/ports/atmel-samd/common-hal/busio/SPI.h
+++ b/ports/atmel-samd/common-hal/busio/SPI.h
@@ -29,17 +29,17 @@
 
 #include "common-hal/microcontroller/Pin.h"
 
-#include "asf/sam0/drivers/sercom/spi/spi.h"
+#include "hal/include/hal_spi_m_sync.h"
+
 #include "py/obj.h"
 
 typedef struct {
     mp_obj_base_t base;
-    struct spi_module spi_master_instance;
+    struct spi_m_sync_descriptor spi_desc;
     bool has_lock;
     uint8_t clock_pin;
     uint8_t MOSI_pin;
     uint8_t MISO_pin;
-    uint32_t current_baudrate;
 } busio_spi_obj_t;
 
 #endif // MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_BUSIO_SPI_H
diff --git a/ports/atmel-samd/samd21_peripherals.c b/ports/atmel-samd/samd21_peripherals.c
index d94ba0fa4..0ddc3be52 100644
--- a/ports/atmel-samd/samd21_peripherals.c
+++ b/ports/atmel-samd/samd21_peripherals.c
@@ -58,8 +58,35 @@ static const uint8_t SERCOMx_GCLK_ID_SLOW[] = {
 
     
 // Clock initialization as done in Atmel START.
-void sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
+void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
     _pm_enable_bus_clock(PM_BUS_APBC, sercom);
     _gclk_enable_channel(SERCOMx_GCLK_ID_CORE[sercom_index], GCLK_CLKCTRL_GEN_GCLK0_Val);
     _gclk_enable_channel(SERCOMx_GCLK_ID_SLOW[sercom_index], GCLK_CLKCTRL_GEN_GCLK3_Val);
 }
+
+// Figure out the DOPO value given the chosen clock pad and mosi pad.
+// Return an out-of-range value (255) if the combination is not permitted.
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad) {
+    if (clock_pad == 1) {
+        if (mosi_pad == 0) {
+            return 0;
+        } else if (mosi_pad == 3) {
+            return 2;
+        }
+    } else if (clock_pad == 3) {
+        if (mosi_pad == 0) {
+            return 3;
+        } else if (mosi_pad == 2) {
+            return 1;
+        }
+    }
+    return 255;
+}
+
+bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad) {
+    return clock_pad == 1 || clock_pad == 3;
+}
diff --git a/ports/atmel-samd/samd21_peripherals.h b/ports/atmel-samd/samd21_peripherals.h
index f7fbbd1bd..a317d3ddc 100644
--- a/ports/atmel-samd/samd21_peripherals.h
+++ b/ports/atmel-samd/samd21_peripherals.h
@@ -29,6 +29,8 @@
 
 #include "include/sam.h"
 
-void sercom_clock_init(Sercom* sercom, uint8_t sercom_index);
+void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index);
+uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad);
+bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad);
 
 #endif  // MICROPY_INCLUDED_ATMEL_SAMD_SAMD21_PERIPHERALS_H
diff --git a/ports/atmel-samd/samd51_peripherals.c b/ports/atmel-samd/samd51_peripherals.c
index 3323df116..f1528f3c1 100644
--- a/ports/atmel-samd/samd51_peripherals.c
+++ b/ports/atmel-samd/samd51_peripherals.c
@@ -62,7 +62,7 @@ static const uint8_t SERCOMx_GCLK_ID_SLOW[] = {
 
     
 // Clock initialization as done in Atmel START.
-void sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
+void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
 	hri_gclk_write_PCHCTRL_reg(GCLK,
                                    SERCOMx_GCLK_ID_CORE[sercom_index],
                                    GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos));
@@ -102,3 +102,30 @@ void sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
 #endif
         }
 }
+
+
+// Figure out the DOPO value given the chosen clock pad and mosi pad.
+// Return an out-of-range value (255) if the combination is not permitted
+// The ASF4 config files list this, but the SAMD51 datasheet
+// says 0x1 and 0x3 are reserved, so don't allow pad 3 SCK.
+// Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK [RESERVED]
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK [RESERVED]
+uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad) {
+    if (clock_pad != 1) {
+        return 255;
+    }
+    if (mosi_pad == 0) {
+        return 0x1;
+    }
+    if (mosi_pad == 3) {
+        return 0x2;
+    }
+    return 255;
+}
+
+bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad) {
+    return clock_pad == 1;
+}
diff --git a/ports/atmel-samd/samd51_peripherals.h b/ports/atmel-samd/samd51_peripherals.h
index fe693a24d..3e8097c87 100644
--- a/ports/atmel-samd/samd51_peripherals.h
+++ b/ports/atmel-samd/samd51_peripherals.h
@@ -29,7 +29,9 @@
 
 #include "sam.h"
 
-void sercom_clock_init(Sercom* sercom, uint8_t sercom_index);
+void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index);
+uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad);
+bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad);
 
 #endif  // MICROPY_INCLUDED_ATMEL_SAMD_SAMD51_PERIPHERALS_H
 
diff --git a/ports/atmel-samd/shared_dma.c b/ports/atmel-samd/shared_dma.c
index 5dc8cde43..a2914c3cf 100644
--- a/ports/atmel-samd/shared_dma.c
+++ b/ports/atmel-samd/shared_dma.c
@@ -95,7 +95,7 @@ static void dma_configure(uint8_t channel, uint8_t trigsrc, bool output_event) {
     system_interrupt_leave_critical_section();
 }
 
-enum status_code shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_t length) {
+int32_t shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_t length) {
     if (general_dma_tx.job_status != STATUS_OK) {
         return general_dma_tx.job_status;
     }
@@ -113,7 +113,7 @@ enum status_code shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_
 
     dma_descriptor_create(general_dma_tx.descriptor, &descriptor_config);
     enum status_code status = dma_start_transfer_job(&general_dma_tx);
-    if (status != STATUS_OK) {
+    if (status != ERR_NONE) {
         return status;
     }
 
@@ -134,8 +134,8 @@ enum status_code shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_
     return general_dma_tx.job_status;
 }
 
-enum status_code shared_dma_read(Sercom* sercom, uint8_t* buffer, uint32_t length, uint8_t tx) {
-    if (general_dma_tx.job_status != STATUS_OK) {
+int32_t shared_dma_read(Sercom* sercom, uint8_t* buffer, uint32_t length, uint8_t tx) {
+    if (general_dma_tx.job_status != ERR_NONE) {
         return general_dma_tx.job_status;
     }