diff options
Diffstat (limited to 'ports/mimxrt10xx')
60 files changed, 1705 insertions, 1701 deletions
diff --git a/ports/mimxrt10xx/background.c b/ports/mimxrt10xx/background.c index a8a613d41..9e531cea2 100644 --- a/ports/mimxrt10xx/background.c +++ b/ports/mimxrt10xx/background.c @@ -32,5 +32,7 @@ void port_background_task(void) { audio_dma_background(); #endif } -void port_start_background_task(void) {} -void port_finish_background_task(void) {} +void port_start_background_task(void) { +} +void port_finish_background_task(void) { +} diff --git a/ports/mimxrt10xx/boards/feather_m7_1011/board.c b/ports/mimxrt10xx/boards/feather_m7_1011/board.c index 1db1dd686..5e20e5e3c 100644 --- a/ports/mimxrt10xx/boards/feather_m7_1011/board.c +++ b/ports/mimxrt10xx/boards/feather_m7_1011/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_13);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_12);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_13);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); diff --git a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c index 9ba3e168f..5871dda96 100644 --- a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c @@ -14,14 +14,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -29,141 +29,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q32JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, // Bit pattern for setting Quad Enable. + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, // Bit pattern for setting Quad Enable. - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status -2 - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01 /* number of bytes to write */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status -2 + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01 /* number of bytes to write */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/board.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/board.c index 1db1dd686..5e20e5e3c 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1011/board.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_13);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_12);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_13);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c index eafc9ac3a..7460615c4 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c @@ -14,14 +14,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -29,141 +29,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/pins.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/pins.c index 4e5de8de2..b752b8ed3 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1011/pins.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/pins.c @@ -41,7 +41,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RESET), MP_ROM_PTR(&pin_GPIO_AD_00) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_GPIO_12) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_GPIO_11) }, - //{ MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RTS), MP_ROM_PTR(&pin_) }, + // { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RTS), MP_ROM_PTR(&pin_) }, { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO_SD_05) }, diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/board.c b/ports/mimxrt10xx/boards/feather_mimxrt1062/board.c index 26f55f96e..3782d3f2d 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1062/board.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_06); diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c index fef1c11e3..d6cfc07e6 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h b/ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h index 4c3953187..7b335d896 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h +++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h @@ -1,10 +1,10 @@ #define MICROPY_HW_BOARD_NAME "Feather MIMXRT1062" #define MICROPY_HW_MCU_NAME "IMXRT1062DVJ6A" -//TODO -//#define MICROPY_HW_LED_STATUS (&pin_PA27) +// TODO +// #define MICROPY_HW_LED_STATUS (&pin_PA27) -//#define MICROPY_HW_NEOPIXEL (&pin_PB22) +// #define MICROPY_HW_NEOPIXEL (&pin_PB22) // If you change this, then make sure to update the linker scripts as well to // make sure you don't overwrite code diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board.c b/ports/mimxrt10xx/boards/imxrt1010_evk/board.c index 8519893a5..9f7a22a86 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_13); //SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_12); //SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_13); // SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12); // SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); common_hal_never_reset_pin(&pin_GPIO_SD_11); diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c index 00ee47c98..9c88f689d 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for AT25SF128A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board.c b/ports/mimxrt10xx/boards/imxrt1020_evk/board.c index 531c0c6f6..4ae1e19b0 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_B0_00);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_B0_01);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_B0_00);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_B0_01);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_06); diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c index 4c3ba4717..6589ad9c4 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for IS25LP064A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_30MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_30MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - // RADDR_SDR, FLEXSPI_4PAD, 24 bits to transmit ), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - // READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + // RADDR_SDR, FLEXSPI_4PAD, 24 bits to transmit ), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + // READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/board.c b/ports/mimxrt10xx/boards/imxrt1060_evk/board.c index e7d74ab49..c4a2867ab 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_00); diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c index 502e21a3b..40db33444 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for IS25WP064A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board.c b/ports/mimxrt10xx/boards/metro_m7_1011/board.c index 1db1dd686..5e20e5e3c 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/board.c +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_13);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_12);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_13);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c index 991bc43e4..3f4ab0271 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c +++ b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,151 +30,151 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q16JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { + .seqId = 2u, + .seqNum = 1u, + }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x0200, - .configCmdEnable = 1u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .configCmdSeqs[0] = { - .seqId = 2u, - .seqNum = 1u, - }, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, - DUMMY_SDR, FLEXSPI_1PAD, 8), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, + DUMMY_SDR, FLEXSPI_1PAD, 8), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/teensy40/flash_config.c b/ports/mimxrt10xx/boards/teensy40/flash_config.c index 991bc43e4..3f4ab0271 100644 --- a/ports/mimxrt10xx/boards/teensy40/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy40/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,151 +30,151 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q16JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { + .seqId = 2u, + .seqNum = 1u, + }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x0200, - .configCmdEnable = 1u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .configCmdSeqs[0] = { - .seqId = 2u, - .seqNum = 1u, - }, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, - DUMMY_SDR, FLEXSPI_1PAD, 8), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, + DUMMY_SDR, FLEXSPI_1PAD, 8), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/teensy41/flash_config.c b/ports/mimxrt10xx/boards/teensy41/flash_config.c index c0e0c86f9..09886dece 100644 --- a/ports/mimxrt10xx/boards/teensy41/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy41/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c b/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c index 9587eba63..5e7bb82c7 100644 --- a/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c +++ b/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c @@ -36,8 +36,8 @@ #define ADC_CHANNEL_GROUP 0 -void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self, + const mcu_pin_obj_t *pin) { adc_config_t config = {0}; if (pin->adc == NULL) { diff --git a/ports/mimxrt10xx/common-hal/analogio/AnalogOut.c b/ports/mimxrt10xx/common-hal/analogio/AnalogOut.c index 6bdbeff7c..bf21e30df 100644 --- a/ports/mimxrt10xx/common-hal/analogio/AnalogOut.c +++ b/ports/mimxrt10xx/common-hal/analogio/AnalogOut.c @@ -31,7 +31,7 @@ #include "shared-bindings/microcontroller/Pin.h" #include "supervisor/shared/translate.h" -void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self, const mcu_pin_obj_t *pin) { mp_raise_NotImplementedError(translate("AnalogOut functionality not supported")); } diff --git a/ports/mimxrt10xx/common-hal/busio/I2C.c b/ports/mimxrt10xx/common-hal/busio/I2C.c index c8daddc4b..74639d0ef 100644 --- a/ports/mimxrt10xx/common-hal/busio/I2C.c +++ b/ports/mimxrt10xx/common-hal/busio/I2C.c @@ -37,16 +37,16 @@ #include "fsl_lpi2c.h" #include "fsl_gpio.h" -#define I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (1+CLOCK_GetDiv(kCLOCK_Lpi2cDiv))) +#define I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (1 + CLOCK_GetDiv(kCLOCK_Lpi2cDiv))) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5 5U -//arrays use 0 based numbering: I2C1 is stored at index 0 +// arrays use 0 based numbering: I2C1 is stored at index 0 #define MAX_I2C 4 STATIC bool reserved_i2c[MAX_I2C]; STATIC bool never_reset_i2c[MAX_I2C]; void i2c_reset(void) { - for(uint i = 0; i < MP_ARRAY_SIZE(mcu_i2c_banks); i++) { + for (uint i = 0; i < MP_ARRAY_SIZE(mcu_i2c_banks); i++) { if (!never_reset_i2c[i]) { reserved_i2c[i] = false; LPI2C_MasterDeinit(mcu_i2c_banks[i]); @@ -64,30 +64,29 @@ static void config_periph_pin(const mcu_periph_obj_t *periph) { IOMUXC_SetPinConfig(0, 0, 0, 0, periph->pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(0) - | IOMUXC_SW_PAD_CTL_PAD_PUS(3) - | IOMUXC_SW_PAD_CTL_PAD_PUE(0) - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(1) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) - | IOMUXC_SW_PAD_CTL_PAD_DSE(4) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS(3) + | IOMUXC_SW_PAD_CTL_PAD_PUE(0) + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(1) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(4) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } -static void i2c_check_pin_config(const mcu_pin_obj_t *pin, uint32_t pull) -{ +static void i2c_check_pin_config(const mcu_pin_obj_t *pin, uint32_t pull) { IOMUXC_SetPinConfig(0, 0, 0, 0, pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(1) - | IOMUXC_SW_PAD_CTL_PAD_PUS(0) // Pulldown - | IOMUXC_SW_PAD_CTL_PAD_PUE(pull) // 0=nopull (keeper), 1=pull - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(0) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) - | IOMUXC_SW_PAD_CTL_PAD_DSE(1) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS(0) // Pulldown + | IOMUXC_SW_PAD_CTL_PAD_PUE(pull) // 0=nopull (keeper), 1=pull + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(0) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(1) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, - const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) { + const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) { #if CIRCUITPY_REQUIRE_I2C_PULLUPS // Test that the pins are in a high state. (Hopefully indicating they are pulled up.) @@ -107,7 +106,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, // We must pull up within 3us to achieve 400khz. common_hal_mcu_delay_us(3); - if( !GPIO_PinRead(sda->gpio, sda->number) || !GPIO_PinRead(scl->gpio, scl->number)) { + if (!GPIO_PinRead(sda->gpio, sda->number) || !GPIO_PinRead(scl->gpio, scl->number)) { common_hal_reset_pin(sda); common_hal_reset_pin(scl); mp_raise_RuntimeError(translate("No pull up found on SDA or SCL; check your wiring")); @@ -118,15 +117,18 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const uint32_t scl_count = MP_ARRAY_SIZE(mcu_i2c_scl_list); for (uint32_t i = 0; i < sda_count; ++i) { - if (mcu_i2c_sda_list[i].pin != sda) + if (mcu_i2c_sda_list[i].pin != sda) { continue; + } for (uint32_t j = 0; j < scl_count; ++j) { - if (mcu_i2c_scl_list[j].pin != scl) + if (mcu_i2c_scl_list[j].pin != scl) { continue; + } - if (mcu_i2c_scl_list[j].bank_idx != mcu_i2c_sda_list[i].bank_idx) + if (mcu_i2c_scl_list[j].bank_idx != mcu_i2c_sda_list[i].bank_idx) { continue; + } self->sda = &mcu_i2c_sda_list[i]; self->scl = &mcu_i2c_scl_list[j]; @@ -135,7 +137,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, } } - if(self->sda == NULL || self->scl == NULL) { + if (self->sda == NULL || self->scl == NULL) { mp_raise_ValueError(translate("Invalid pins")); } else { self->i2c = mcu_i2c_banks[self->sda->bank_idx - 1]; @@ -209,23 +211,24 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) { } uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, - const uint8_t *data, size_t len, bool transmit_stop_bit) { + const uint8_t *data, size_t len, bool transmit_stop_bit) { lpi2c_master_transfer_t xfer = { 0 }; xfer.flags = transmit_stop_bit ? kLPI2C_TransferDefaultFlag : kLPI2C_TransferNoStopFlag; xfer.slaveAddress = addr; - xfer.data = (uint8_t*)data; + xfer.data = (uint8_t *)data; xfer.dataSize = len; const status_t status = LPI2C_MasterTransferBlocking(self->i2c, &xfer); - if (status == kStatus_Success) + if (status == kStatus_Success) { return 0; + } return MP_EIO; } uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, - uint8_t *data, size_t len) { + uint8_t *data, size_t len) { lpi2c_master_transfer_t xfer = { 0 }; xfer.direction = kLPI2C_Read; @@ -234,8 +237,9 @@ uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, xfer.dataSize = len; const status_t status = LPI2C_MasterTransferBlocking(self->i2c, &xfer); - if (status == kStatus_Success) + if (status == kStatus_Success) { return 0; + } return MP_EIO; } diff --git a/ports/mimxrt10xx/common-hal/busio/SPI.c b/ports/mimxrt10xx/common-hal/busio/SPI.c index 00d8d9867..3488ac0fb 100644 --- a/ports/mimxrt10xx/common-hal/busio/SPI.c +++ b/ports/mimxrt10xx/common-hal/busio/SPI.c @@ -40,7 +40,7 @@ #define MAX_SPI_BUSY_RETRIES 100 -//arrays use 0 based numbering: SPI1 is stored at index 0 +// arrays use 0 based numbering: SPI1 is stored at index 0 #define MAX_SPI 4 STATIC bool reserved_spi[MAX_SPI]; STATIC bool never_reset_spi[MAX_SPI]; @@ -55,13 +55,13 @@ STATIC void config_periph_pin(const mcu_periph_obj_t *periph) { IOMUXC_SetPinConfig(0, 0, 0, 0, periph->pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(0) - | IOMUXC_SW_PAD_CTL_PAD_PUS(0) - | IOMUXC_SW_PAD_CTL_PAD_PUE(0) - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(0) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) - | IOMUXC_SW_PAD_CTL_PAD_DSE(4) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS(0) + | IOMUXC_SW_PAD_CTL_PAD_PUE(0) + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(0) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(4) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } void spi_reset(void) { @@ -74,8 +74,8 @@ void spi_reset(void) { } void common_hal_busio_spi_construct(busio_spi_obj_t *self, - const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, - const mcu_pin_obj_t *miso) { + const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, + const mcu_pin_obj_t *miso) { const uint32_t sck_count = MP_ARRAY_SIZE(mcu_spi_sck_list); const uint32_t miso_count = MP_ARRAY_SIZE(mcu_spi_miso_list); @@ -86,15 +86,15 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, if (mcu_spi_sck_list[i].pin != clock) { continue; } - //if both MOSI and MISO exist, loop search normally + // if both MOSI and MISO exist, loop search normally if ((mosi != NULL) && (miso != NULL)) { for (uint j = 0; j < mosi_count; j++) { if ((mcu_spi_mosi_list[i].pin != mosi) - || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)){ + || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)) { continue; } for (uint k = 0; k < miso_count; k++) { - if ((mcu_spi_miso_list[k].pin != miso) //everything needs the same index + if ((mcu_spi_miso_list[k].pin != miso) // everything needs the same index || (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[k].bank_idx)) { continue; } @@ -103,7 +103,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, spi_taken = true; break; } - //store pins if not + // store pins if not self->clock = &mcu_spi_sck_list[i]; self->mosi = &mcu_spi_mosi_list[j]; self->miso = &mcu_spi_miso_list[k]; @@ -116,10 +116,10 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, if (self->clock != NULL || spi_taken) { break; } - // if just MISO, reduce search + // if just MISO, reduce search } else if (miso != NULL) { for (uint j = 0; j < miso_count; j++) { - if ((mcu_spi_miso_list[j].pin != miso) //only SCK and MISO need the same index + if ((mcu_spi_miso_list[j].pin != miso) // only SCK and MISO need the same index || (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[j].bank_idx)) { continue; } @@ -134,10 +134,10 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, if (self->clock != NULL || spi_taken) { break; } - // if just MOSI, reduce search + // if just MOSI, reduce search } else if (mosi != NULL) { for (uint j = 0; j < mosi_count; j++) { - if ((mcu_spi_mosi_list[j].pin != mosi) //only SCK and MOSI need the same index + if ((mcu_spi_mosi_list[j].pin != mosi) // only SCK and MOSI need the same index || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)) { continue; } @@ -153,7 +153,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, break; } } else { - //throw an error immediately + // throw an error immediately mp_raise_ValueError(translate("Must provide MISO or MOSI pin")); } } @@ -231,7 +231,7 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { } bool common_hal_busio_spi_configure(busio_spi_obj_t *self, - uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { + uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { LPSPI_Enable(self->spi, false); uint32_t tcrPrescaleValue; @@ -278,7 +278,7 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) { } bool common_hal_busio_spi_write(busio_spi_obj_t *self, - const uint8_t *data, size_t len) { + const uint8_t *data, size_t len) { if (len == 0) { return true; } @@ -287,7 +287,7 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, } lpspi_transfer_t xfer = { 0 }; - xfer.txData = (uint8_t*)data; + xfer.txData = (uint8_t *)data; xfer.dataSize = len; xfer.configFlags = kLPSPI_MasterPcs0; @@ -297,14 +297,15 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, status = LPSPI_MasterTransferBlocking(self->spi, &xfer); } while (status == kStatus_LPSPI_Busy && --retries > 0); - if (status != kStatus_Success) + if (status != kStatus_Success) { printf("%s: status %ld\r\n", __func__, status); + } - return (status == kStatus_Success); + return status == kStatus_Success; } bool common_hal_busio_spi_read(busio_spi_obj_t *self, - uint8_t *data, size_t len, uint8_t write_value) { + uint8_t *data, size_t len, uint8_t write_value) { if (len == 0) { return true; } @@ -324,10 +325,11 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self, status = LPSPI_MasterTransferBlocking(self->spi, &xfer); } while (status == kStatus_LPSPI_Busy && --retries > 0); - if (status != kStatus_Success) + if (status != kStatus_Success) { printf("%s: status %ld\r\n", __func__, status); + } - return (status == kStatus_Success); + return status == kStatus_Success; } bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_out, uint8_t *data_in, size_t len) { @@ -351,20 +353,21 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou status = LPSPI_MasterTransferBlocking(self->spi, &xfer); } while (status == kStatus_LPSPI_Busy && --retries > 0); - if (status != kStatus_Success) + if (status != kStatus_Success) { printf("%s: status %ld\r\n", __func__, status); + } - return (status == kStatus_Success); + return status == kStatus_Success; } -uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) { +uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) { return self->baudrate; } -uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) { - return ((self->spi->TCR & LPSPI_TCR_CPHA_MASK) == LPSPI_TCR_CPHA_MASK); +uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) { + return (self->spi->TCR & LPSPI_TCR_CPHA_MASK) == LPSPI_TCR_CPHA_MASK; } -uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) { - return ((self->spi->TCR & LPSPI_TCR_CPOL_MASK) == LPSPI_TCR_CPOL_MASK); +uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) { + return (self->spi->TCR & LPSPI_TCR_CPOL_MASK) == LPSPI_TCR_CPOL_MASK; } diff --git a/ports/mimxrt10xx/common-hal/busio/UART.c b/ports/mimxrt10xx/common-hal/busio/UART.c index 503da14c2..29f9ea0b2 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.c +++ b/ports/mimxrt10xx/common-hal/busio/UART.c @@ -40,7 +40,7 @@ #include "fsl_lpuart.h" -//arrays use 0 based numbering: UART1 is stored at index 0 +// arrays use 0 based numbering: UART1 is stored at index 0 #define MAX_UART 8 STATIC bool reserved_uart[MAX_UART]; @@ -56,18 +56,17 @@ static void config_periph_pin(const mcu_periph_obj_t *periph) { IOMUXC_SetPinConfig(0, 0, 0, 0, periph->pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(0) - | IOMUXC_SW_PAD_CTL_PAD_PUS(1) - | IOMUXC_SW_PAD_CTL_PAD_PUE(1) - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(0) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(1) - | IOMUXC_SW_PAD_CTL_PAD_DSE(6) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS(1) + | IOMUXC_SW_PAD_CTL_PAD_PUE(1) + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(0) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(1) + | IOMUXC_SW_PAD_CTL_PAD_DSE(6) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } -void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *user_data) -{ - busio_uart_obj_t *self = (busio_uart_obj_t*)user_data; +void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *user_data) { + busio_uart_obj_t *self = (busio_uart_obj_t *)user_data; if (status == kStatus_LPUART_RxIdle) { self->rx_ongoing = false; @@ -75,19 +74,19 @@ void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t st } void uart_reset(void) { - for(uint i = 0; i < MP_ARRAY_SIZE(mcu_uart_banks); i++) { + for (uint i = 0; i < MP_ARRAY_SIZE(mcu_uart_banks); i++) { reserved_uart[i] = false; LPUART_Deinit(mcu_uart_banks[i]); } } void common_hal_busio_uart_construct(busio_uart_obj_t *self, - const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx, - const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts, - const mcu_pin_obj_t * rs485_dir, bool rs485_invert, - uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, - mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer, - bool sigint_enabled) { + const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx, + const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts, + const mcu_pin_obj_t *rs485_dir, bool rs485_invert, + uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, + mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer, + bool sigint_enabled) { self->baudrate = baudrate; self->character_bits = bits; @@ -169,8 +168,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } // For IMXRT the RTS pin is used for RS485 direction rts = rs485_dir; - } - else { + } else { if (rs485_invert) { mp_raise_ValueError(translate("RS485 inversion specified when not in RS485 mode")); } @@ -181,7 +179,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, const uint32_t cts_count = MP_ARRAY_SIZE(mcu_uart_cts_list); if (rts != NULL) { - for (uint32_t i=0; i < rts_count; ++i) { + for (uint32_t i = 0; i < rts_count; ++i) { if (mcu_uart_rts_list[i].bank_idx == self->rx->bank_idx) { if (mcu_uart_rts_list[i].pin == rts) { self->rts = &mcu_uart_rts_list[i]; @@ -189,13 +187,13 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } } } - if (self->rts == NULL){ + if (self->rts == NULL) { mp_raise_ValueError(translate("Selected RTS pin not valid")); } } if (cts != NULL) { - for (uint32_t i=0; i < cts_count; ++i) { + for (uint32_t i = 0; i < cts_count; ++i) { if (mcu_uart_cts_list[i].bank_idx == self->rx->bank_idx) { if (mcu_uart_cts_list[i].pin == cts) { self->cts = &mcu_uart_cts_list[i]; @@ -203,7 +201,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } } } - if (self->cts == NULL){ + if (self->cts == NULL) { mp_raise_ValueError(translate("Selected CTS pin not valid")); } } @@ -326,7 +324,7 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t uint64_t start_ticks = supervisor_ticks_ms64(); // Wait for all bytes received or timeout - while (self->rx_ongoing && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms) ) { + while (self->rx_ongoing && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms)) { RUN_BACKGROUND_TASKS; // Allow user to break out of a timeout with a KeyboardInterrupt. @@ -372,7 +370,7 @@ void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrat } mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) { - return (mp_float_t) (self->timeout_ms / 1000.0f); + return (mp_float_t)(self->timeout_ms / 1000.0f); } void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) { diff --git a/ports/mimxrt10xx/common-hal/busio/UART.h b/ports/mimxrt10xx/common-hal/busio/UART.h index 94a5fb02c..604fef2cf 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.h +++ b/ports/mimxrt10xx/common-hal/busio/UART.h @@ -40,7 +40,7 @@ typedef struct { mp_obj_base_t base; LPUART_Type *uart; lpuart_handle_t handle; - uint8_t* ringbuf; + uint8_t *ringbuf; bool rx_ongoing; uint32_t baudrate; uint8_t character_bits; diff --git a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c index e4eda9f4f..445ffa91c 100644 --- a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c +++ b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c @@ -40,21 +40,20 @@ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5 5U -void pin_config(const mcu_pin_obj_t *pin, bool open_drain, digitalio_pull_t pull) -{ +void pin_config(const mcu_pin_obj_t *pin, bool open_drain, digitalio_pull_t pull) { IOMUXC_SetPinConfig(0, 0, 0, 0, pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(1) - | IOMUXC_SW_PAD_CTL_PAD_PUS((pull == PULL_UP) ? 2 : 0) - | IOMUXC_SW_PAD_CTL_PAD_PUE(pull != PULL_NONE) - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(open_drain) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) - | IOMUXC_SW_PAD_CTL_PAD_DSE(1) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS((pull == PULL_UP) ? 2 : 0) + | IOMUXC_SW_PAD_CTL_PAD_PUE(pull != PULL_NONE) + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(open_drain) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(1) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } digitalinout_result_t common_hal_digitalio_digitalinout_construct( - digitalio_digitalinout_obj_t* self, const mcu_pin_obj_t* pin) { + digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { claim_pin(pin); self->pin = pin; self->output = false; @@ -73,15 +72,15 @@ digitalinout_result_t common_hal_digitalio_digitalinout_construct( } void common_hal_digitalio_digitalinout_never_reset( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { common_hal_never_reset_pin(self->pin); } -bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t* self) { +bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t *self) { return self->pin == NULL; } -void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t* self) { +void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self) { if (common_hal_digitalio_digitalinout_deinited(self)) { return; } @@ -90,7 +89,7 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t* self } void common_hal_digitalio_digitalinout_switch_to_input( - digitalio_digitalinout_obj_t* self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { self->output = false; // This also sets direction to input. @@ -98,8 +97,8 @@ void common_hal_digitalio_digitalinout_switch_to_input( } digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( - digitalio_digitalinout_obj_t* self, bool value, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, bool value, + digitalio_drive_mode_t drive_mode) { self->output = true; self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN; self->pull = PULL_NONE; @@ -112,23 +111,23 @@ digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { return self->output ? DIRECTION_OUTPUT : DIRECTION_INPUT; } void common_hal_digitalio_digitalinout_set_value( - digitalio_digitalinout_obj_t* self, bool value) { + digitalio_digitalinout_obj_t *self, bool value) { GPIO_PinWrite(self->pin->gpio, self->pin->number, value); } bool common_hal_digitalio_digitalinout_get_value( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { return GPIO_PinRead(self->pin->gpio, self->pin->number); } digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( - digitalio_digitalinout_obj_t* self, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, + digitalio_drive_mode_t drive_mode) { bool value = common_hal_digitalio_digitalinout_get_value(self); self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN; @@ -143,7 +142,7 @@ digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { if (self->open_drain) { return DRIVE_MODE_OPEN_DRAIN; } else { @@ -152,7 +151,7 @@ digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( } void common_hal_digitalio_digitalinout_set_pull( - digitalio_digitalinout_obj_t* self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { self->pull = pull; pin_config(self->pin, self->open_drain, self->pull); @@ -162,7 +161,7 @@ void common_hal_digitalio_digitalinout_set_pull( } digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { if (self->output) { mp_raise_AttributeError(translate("Cannot get pull while in output mode")); return PULL_NONE; diff --git a/ports/mimxrt10xx/common-hal/displayio/ParallelBus.c b/ports/mimxrt10xx/common-hal/displayio/ParallelBus.c index 0fdf4413b..6a5a978cf 100644 --- a/ports/mimxrt10xx/common-hal/displayio/ParallelBus.c +++ b/ports/mimxrt10xx/common-hal/displayio/ParallelBus.c @@ -33,19 +33,19 @@ #include "shared-bindings/digitalio/DigitalInOut.h" #include "shared-bindings/microcontroller/__init__.h" -void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* self, - const mcu_pin_obj_t* data0, const mcu_pin_obj_t* command, const mcu_pin_obj_t* chip_select, - const mcu_pin_obj_t* write, const mcu_pin_obj_t* read, const mcu_pin_obj_t* reset) { +void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t *self, + const mcu_pin_obj_t *data0, const mcu_pin_obj_t *command, const mcu_pin_obj_t *chip_select, + const mcu_pin_obj_t *write, const mcu_pin_obj_t *read, const mcu_pin_obj_t *reset) { mp_raise_NotImplementedError(translate("ParallelBus not yet supported")); } -void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) { +void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t *self) { } bool common_hal_displayio_parallelbus_reset(mp_obj_t obj) { - return false; + return false; } bool common_hal_displayio_parallelbus_bus_free(mp_obj_t obj) { diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Pin.c b/ports/mimxrt10xx/common-hal/microcontroller/Pin.c index 50970f8e2..b55ab6e86 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Pin.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/Pin.c @@ -49,9 +49,9 @@ void reset_all_pins(void) { claimed_pins[i] = never_reset_pins[i]; } for (uint8_t i = 0; i < IOMUXC_SW_PAD_CTL_PAD_COUNT; i++) { - if(!never_reset_pins[i]) { - IOMUXC->SW_MUX_CTL_PAD[i] = ((mcu_pin_obj_t*)(mcu_pin_globals.map.table[i].value))->mux_reset; - IOMUXC->SW_PAD_CTL_PAD[i] = ((mcu_pin_obj_t*)(mcu_pin_globals.map.table[i].value))->pad_reset; + if (!never_reset_pins[i]) { + IOMUXC->SW_MUX_CTL_PAD[i] = ((mcu_pin_obj_t *)(mcu_pin_globals.map.table[i].value))->mux_reset; + IOMUXC->SW_PAD_CTL_PAD[i] = ((mcu_pin_obj_t *)(mcu_pin_globals.map.table[i].value))->pad_reset; } } @@ -66,14 +66,14 @@ void reset_all_pins(void) { // Since i.MX pins need extra register and reset information to reset properly, // resetting pins by number alone has been removed. -void common_hal_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_reset_pin(const mcu_pin_obj_t *pin) { if (pin == NULL) { return; } never_reset_pins[pin->mux_idx] = false; claimed_pins[pin->mux_idx] = false; - *(uint32_t*)pin->mux_reg = pin->mux_reset; - *(uint32_t*)pin->cfg_reg = pin->pad_reset; + *(uint32_t *)pin->mux_reg = pin->mux_reset; + *(uint32_t *)pin->cfg_reg = pin->pad_reset; #ifdef MICROPY_HW_NEOPIXEL if (pin == MICROPY_HW_NEOPIXEL) { @@ -95,11 +95,11 @@ void common_hal_reset_pin(const mcu_pin_obj_t* pin) { #endif } -void common_hal_never_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_never_reset_pin(const mcu_pin_obj_t *pin) { never_reset_pins[pin->mux_idx] = true; } -bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t* pin) { +bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { #ifdef MICROPY_HW_NEOPIXEL if (pin == MICROPY_HW_NEOPIXEL) { return !neopixel_in_use; @@ -117,11 +117,11 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t* pin) { return !claimed_pins[pin->mux_idx]; } -uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t* pin) { +uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t *pin) { return pin->mux_idx; // returns IOMUXC to align with pin table } -void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { +void common_hal_mcu_pin_claim(const mcu_pin_obj_t *pin) { claimed_pins[pin->mux_idx] = true; #ifdef MICROPY_HW_NEOPIXEL @@ -139,10 +139,10 @@ void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { #endif } -void claim_pin(const mcu_pin_obj_t* pin) { +void claim_pin(const mcu_pin_obj_t *pin) { common_hal_mcu_pin_claim(pin); } void common_hal_mcu_pin_reset_number(uint8_t pin_no) { - common_hal_reset_pin((mcu_pin_obj_t*)(mcu_pin_globals.map.table[pin_no].value)); + common_hal_reset_pin((mcu_pin_obj_t *)(mcu_pin_globals.map.table[pin_no].value)); } diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Pin.h b/ports/mimxrt10xx/common-hal/microcontroller/Pin.h index 2f1aaa895..fde7fc8b8 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Pin.h +++ b/ports/mimxrt10xx/common-hal/microcontroller/Pin.h @@ -41,6 +41,6 @@ extern bool apa102_mosi_in_use; #endif void reset_all_pins(void); -void claim_pin(const mcu_pin_obj_t* pin); +void claim_pin(const mcu_pin_obj_t *pin); #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_MICROCONTROLLER_PIN_H diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c index efbde35d2..b097133d5 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c @@ -65,7 +65,7 @@ void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { for (int i = 0; i < 4; ++i) { uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1); for (int j = 0; j < 4; j++) { - raw_id[i*4+j] = wr & 0xff; + raw_id[i * 4 + j] = wr & 0xff; wr >>= 8; } } diff --git a/ports/mimxrt10xx/common-hal/microcontroller/__init__.c b/ports/mimxrt10xx/common-hal/microcontroller/__init__.c index 6a8537e2d..2daf108af 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/__init__.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/__init__.c @@ -24,7 +24,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -//TODO +// TODO #include "py/mphal.h" #include "py/obj.h" #include "py/runtime.h" @@ -102,14 +102,14 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .type = &nvm_bytearray_type, }, .len = CIRCUITPY_INTERNAL_NVM_SIZE, - .start_address = (uint8_t*) (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE) + .start_address = (uint8_t *)(FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE) }; #endif // This maps MCU pin names to pin objects. // NOTE: for all i.MX chips, order MUST match _iomuxc_sw_mux_ctl_pad enum STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = { -#ifdef MIMXRT1011_SERIES + #ifdef MIMXRT1011_SERIES { MP_ROM_QSTR(MP_QSTR_GPIO_AD_14), MP_ROM_PTR(&pin_GPIO_AD_14) }, { MP_ROM_QSTR(MP_QSTR_GPIO_AD_13), MP_ROM_PTR(&pin_GPIO_AD_13) }, { MP_ROM_QSTR(MP_QSTR_GPIO_AD_12), MP_ROM_PTR(&pin_GPIO_AD_12) }, @@ -125,7 +125,7 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_GPIO_AD_02), MP_ROM_PTR(&pin_GPIO_AD_02) }, { MP_ROM_QSTR(MP_QSTR_GPIO_AD_01), MP_ROM_PTR(&pin_GPIO_AD_01) }, { MP_ROM_QSTR(MP_QSTR_GPIO_AD_00), MP_ROM_PTR(&pin_GPIO_AD_00) }, - { MP_ROM_QSTR(MP_QSTR_GPIO_SD_14), MP_ROM_PTR(&pin_GPIO_SD_14) }, //spooky ghost pin + { MP_ROM_QSTR(MP_QSTR_GPIO_SD_14), MP_ROM_PTR(&pin_GPIO_SD_14) }, // spooky ghost pin { MP_ROM_QSTR(MP_QSTR_GPIO_SD_13), MP_ROM_PTR(&pin_GPIO_SD_13) }, { MP_ROM_QSTR(MP_QSTR_GPIO_SD_12), MP_ROM_PTR(&pin_GPIO_SD_12) }, { MP_ROM_QSTR(MP_QSTR_GPIO_SD_11), MP_ROM_PTR(&pin_GPIO_SD_11) }, @@ -154,7 +154,7 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_GPIO_02), MP_ROM_PTR(&pin_GPIO_02) }, { MP_ROM_QSTR(MP_QSTR_GPIO_01), MP_ROM_PTR(&pin_GPIO_01) }, { MP_ROM_QSTR(MP_QSTR_GPIO_00), MP_ROM_PTR(&pin_GPIO_00) }, -#else + #else { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_00), MP_ROM_PTR(&pin_GPIO_EMC_00) }, { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_01), MP_ROM_PTR(&pin_GPIO_EMC_01) }, { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_02), MP_ROM_PTR(&pin_GPIO_EMC_02) }, @@ -284,6 +284,6 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_09), MP_ROM_PTR(&pin_GPIO_SD_B1_09) }, { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_10), MP_ROM_PTR(&pin_GPIO_SD_B1_10) }, { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_11), MP_ROM_PTR(&pin_GPIO_SD_B1_11) }, -#endif + #endif }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_global_dict_table); diff --git a/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c b/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c index b86077015..88d045306 100644 --- a/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c +++ b/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c @@ -33,7 +33,7 @@ uint64_t next_start_raw_ticks = 0; -//sysclock divisors +// sysclock divisors #define MAGIC_800_INT 900000 // ~1.11 us -> 1.2 field #define MAGIC_800_T0H 2800000 // ~0.36 us -> 0.44 field #define MAGIC_800_T1H 1350000 // ~0.74 us -> 0.84 field @@ -41,15 +41,15 @@ uint64_t next_start_raw_ticks = 0; #pragma GCC push_options #pragma GCC optimize ("Os") -void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, - uint32_t numBytes) { +void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t * digitalinout, uint8_t *pixels, + uint32_t numBytes) { uint8_t *p = pixels, *end = p + numBytes, pix = *p++, mask = 0x80; uint32_t start = 0; uint32_t cyc = 0; - //assumes 800_000Hz frequency - //Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us - //TODO: try to get dynamic weighting working again + // assumes 800_000Hz frequency + // Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us + // TODO: try to get dynamic weighting working again const uint32_t sys_freq = SystemCoreClock; const uint32_t interval = (sys_freq / MAGIC_800_INT); const uint32_t t0 = (sys_freq / MAGIC_800_T0H); @@ -57,7 +57,8 @@ void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t // Wait to make sure we don't append onto the last transmission. This should only be a tick or // two. - while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {} + while (port_get_raw_ticks(NULL) < next_start_raw_ticks) { + } GPIO_Type *gpio = digitalinout->pin->gpio; const uint32_t pin = digitalinout->pin->number; @@ -68,16 +69,22 @@ void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; DWT->CYCCNT = 0; - for(;;) { + for (;;) { cyc = (pix & mask) ? t1 : t0; start = DWT->CYCCNT; gpio->DR |= (1U << pin); - while((DWT->CYCCNT - start) < cyc); + while ((DWT->CYCCNT - start) < cyc) { + ; + } gpio->DR &= ~(1U << pin); - while((DWT->CYCCNT - start) < interval); - if(!(mask >>= 1)) { - if(p >= end) break; - pix = *p++; + while ((DWT->CYCCNT - start) < interval) { + ; + } + if (!(mask >>= 1)) { + if (p >= end) { + break; + } + pix = *p++; mask = 0x80; } } diff --git a/ports/mimxrt10xx/common-hal/os/__init__.c b/ports/mimxrt10xx/common-hal/os/__init__.c index e84beb526..dd1d186f1 100644 --- a/ports/mimxrt10xx/common-hal/os/__init__.c +++ b/ports/mimxrt10xx/common-hal/os/__init__.c @@ -52,13 +52,13 @@ STATIC MP_DEFINE_ATTRTUPLE( (mp_obj_t)&os_uname_info_release_obj, (mp_obj_t)&os_uname_info_version_obj, (mp_obj_t)&os_uname_info_machine_obj -); + ); mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; } -bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) { +bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { trng_config_t trngConfig; TRNG_GetDefaultConfig(&trngConfig); diff --git a/ports/mimxrt10xx/common-hal/pulseio/PulseIn.c b/ports/mimxrt10xx/common-hal/pulseio/PulseIn.c index cea11a4b9..c1f7ce20b 100644 --- a/ports/mimxrt10xx/common-hal/pulseio/PulseIn.c +++ b/ports/mimxrt10xx/common-hal/pulseio/PulseIn.c @@ -39,7 +39,7 @@ #include "supervisor/shared/translate.h" // TODO -//static void pulsein_set_config(pulseio_pulsein_obj_t* self, bool first_edge) { +// static void pulsein_set_config(pulseio_pulsein_obj_t* self, bool first_edge) { // uint32_t sense_setting; // if (!first_edge) { // sense_setting = EIC_CONFIG_SENSE0_BOTH_Val; @@ -52,9 +52,9 @@ // } // set_eic_handler(self->channel, EIC_HANDLER_PULSEIN); // turn_on_eic_channel(self->channel, sense_setting); -//} +// } -//void pulsein_interrupt_handler(uint8_t channel) { +// void pulsein_interrupt_handler(uint8_t channel) { // // Grab the current time first. // uint32_t current_us; // uint64_t current_ms; @@ -99,10 +99,10 @@ // } // self->last_ms = current_ms; // self->last_us = current_us; -//} +// } -void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, - const mcu_pin_obj_t* pin, uint16_t maxlen, bool idle_state) { +void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t *self, + const mcu_pin_obj_t *pin, uint16_t maxlen, bool idle_state) { // if (!pin->has_extint) { // mp_raise_RuntimeError(translate("No hardware support on pin")); // } @@ -142,12 +142,12 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, // pulsein_set_config(self, true); } -bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t *self) { // return self->pin == NO_PIN; return true; } -void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t *self) { // if (common_hal_pulseio_pulsein_deinited(self)) { // return; // } @@ -157,13 +157,13 @@ void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { // self->pin = NO_PIN; } -void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t *self) { // uint32_t mask = 1 << self->channel; // EIC->INTENCLR.reg = mask << EIC_INTENSET_EXTINT_Pos; } -void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, - uint16_t trigger_duration) { +void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t *self, + uint16_t trigger_duration) { // // Make sure we're paused. // common_hal_pulseio_pulsein_pause(self); // @@ -192,14 +192,14 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, // pulsein_set_config(self, true); } -void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t *self) { // common_hal_mcu_disable_interrupts(); // self->start = 0; // self->len = 0; // common_hal_mcu_enable_interrupts(); } -uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t *self) { // if (self->len == 0) { // mp_raise_IndexError_varg(translate("pop from empty %q"), MP_QSTR_PulseIn); // } @@ -213,24 +213,24 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { return 0; } -uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t *self) { // return self->maxlen; return 0; } -uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t *self) { // return self->len; return 0; } -bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t *self) { // uint32_t mask = 1 << self->channel; // return (EIC->INTENSET.reg & (mask << EIC_INTENSET_EXTINT_Pos)) == 0; return true; } -uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, - int16_t index) { +uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t *self, + int16_t index) { // common_hal_mcu_disable_interrupts(); // if (index < 0) { // index += self->len; diff --git a/ports/mimxrt10xx/common-hal/pulseio/PulseIn.h b/ports/mimxrt10xx/common-hal/pulseio/PulseIn.h index af742f319..cce4f58ca 100644 --- a/ports/mimxrt10xx/common-hal/pulseio/PulseIn.h +++ b/ports/mimxrt10xx/common-hal/pulseio/PulseIn.h @@ -48,8 +48,8 @@ typedef struct { // volatile bool errored_too_fast; } pulseio_pulsein_obj_t; -//void pulsein_reset(void); +// void pulsein_reset(void); // -//void pulsein_interrupt_handler(uint8_t channel); +// void pulsein_interrupt_handler(uint8_t channel); #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_PULSEIO_PULSEIN_H diff --git a/ports/mimxrt10xx/common-hal/pulseio/PulseOut.c b/ports/mimxrt10xx/common-hal/pulseio/PulseOut.c index d3a1a897f..b38f6f093 100644 --- a/ports/mimxrt10xx/common-hal/pulseio/PulseOut.c +++ b/ports/mimxrt10xx/common-hal/pulseio/PulseOut.c @@ -39,25 +39,25 @@ // This timer is shared amongst all PulseOut objects under the assumption that // the code is single threaded. -//static uint8_t refcount = 0; +// static uint8_t refcount = 0; // -//static uint8_t pulseout_tc_index = 0xff; +// static uint8_t pulseout_tc_index = 0xff; // -//static __IO PORT_PINCFG_Type *active_pincfg = NULL; -//static uint16_t *pulse_buffer = NULL; -//static volatile uint16_t pulse_index = 0; -//static uint16_t pulse_length; -//static volatile uint32_t current_compare = 0; +// static __IO PORT_PINCFG_Type *active_pincfg = NULL; +// static uint16_t *pulse_buffer = NULL; +// static volatile uint16_t pulse_index = 0; +// static uint16_t pulse_length; +// static volatile uint32_t current_compare = 0; // -//static void turn_on(__IO PORT_PINCFG_Type * pincfg) { +// static void turn_on(__IO PORT_PINCFG_Type * pincfg) { // pincfg->reg = PORT_PINCFG_PMUXEN; -//} +// } // -//static void turn_off(__IO PORT_PINCFG_Type * pincfg) { +// static void turn_off(__IO PORT_PINCFG_Type * pincfg) { // pincfg->reg = PORT_PINCFG_RESETVALUE; -//} +// } // -//void pulse_finish(void) { +// void pulse_finish(void) { // pulse_index++; // // if (active_pincfg == NULL) { @@ -74,7 +74,7 @@ // if (pulse_index % 2 == 0) { // turn_on(active_pincfg); // } -//} +// } void pulseout_interrupt_handler(uint8_t index) { // if (index != pulseout_tc_index) return; @@ -93,11 +93,11 @@ void pulseout_reset() { // active_pincfg = NULL; } -void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, - const pwmio_pwmout_obj_t* carrier, - const mcu_pin_obj_t* pin, - uint32_t frequency, - uint16_t duty_cycle) { +void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self, + const pwmio_pwmout_obj_t *carrier, + const mcu_pin_obj_t *pin, + uint32_t frequency, + uint16_t duty_cycle) { // if (refcount == 0) { // // Find a spare timer. // Tc *tc = NULL; @@ -155,12 +155,12 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, // turn_off(self->pincfg); } -bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t* self) { +bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t *self) { // return self->pin == NO_PIN; return false; } -void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { +void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t *self) { // if (common_hal_pulseio_pulseout_deinited(self)) { // return; // } @@ -177,7 +177,7 @@ void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { // self->pin = NO_PIN; } -void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pulses, uint16_t length) { +void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pulses, uint16_t length) { // if (active_pincfg != NULL) { // mp_raise_RuntimeError(translate("Another send is already active")); // } diff --git a/ports/mimxrt10xx/common-hal/pulseio/PulseOut.h b/ports/mimxrt10xx/common-hal/pulseio/PulseOut.h index ee70ac17e..da022b738 100644 --- a/ports/mimxrt10xx/common-hal/pulseio/PulseOut.h +++ b/ports/mimxrt10xx/common-hal/pulseio/PulseOut.h @@ -40,6 +40,6 @@ typedef struct { } pulseio_pulseout_obj_t; void pulseout_reset(void); -//void pulseout_interrupt_handler(uint8_t index); +// void pulseout_interrupt_handler(uint8_t index); #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_PULSEIO_PULSEOUT_H diff --git a/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c b/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c index dd464ef84..28ea81fa2 100644 --- a/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c +++ b/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c @@ -41,28 +41,28 @@ #include <stdio.h> // TODO -//#include "samd/pins.h" +// #include "samd/pins.h" -//#undef ENABLE +// #undef ENABLE // -//# define _TCC_SIZE(unused, n) TCC ## n ## _SIZE, -//# define TCC_SIZES { REPEAT_MACRO(_TCC_SIZE, 0, TCC_INST_NUM) } +// # define _TCC_SIZE(unused, n) TCC ## n ## _SIZE, +// # define TCC_SIZES { REPEAT_MACRO(_TCC_SIZE, 0, TCC_INST_NUM) } // -//static uint32_t tcc_periods[TCC_INST_NUM]; -//static uint32_t tc_periods[TC_INST_NUM]; +// static uint32_t tcc_periods[TCC_INST_NUM]; +// static uint32_t tc_periods[TC_INST_NUM]; // -//uint32_t target_tcc_frequencies[TCC_INST_NUM]; -//uint8_t tcc_refcount[TCC_INST_NUM]; +// uint32_t target_tcc_frequencies[TCC_INST_NUM]; +// uint8_t tcc_refcount[TCC_INST_NUM]; // //// This bitmask keeps track of which channels of a TCC are currently claimed. -//#ifdef SAMD21 -//uint8_t tcc_channels[3]; // Set by pwmout_reset() to {0xf0, 0xfc, 0xfc} initially. -//#endif -//#ifdef SAMD51 -//uint8_t tcc_channels[5]; // Set by pwmout_reset() to {0xc0, 0xf0, 0xf8, 0xfc, 0xfc} initially. -//#endif +// #ifdef SAMD21 +// uint8_t tcc_channels[3]; // Set by pwmout_reset() to {0xf0, 0xfc, 0xfc} initially. +// #endif +// #ifdef SAMD51 +// uint8_t tcc_channels[5]; // Set by pwmout_reset() to {0xc0, 0xf0, 0xf8, 0xfc, 0xfc} initially. +// #endif // -//static uint8_t never_reset_tc_or_tcc[TC_INST_NUM + TCC_INST_NUM]; +// static uint8_t never_reset_tc_or_tcc[TC_INST_NUM + TCC_INST_NUM]; void common_hal_pwmio_pwmout_never_reset(pwmio_pwmout_obj_t *self) { // if (self->timer->is_tc) { @@ -119,33 +119,34 @@ void pwmout_reset(void) { // } } -//static uint8_t tcc_channel(const pin_timer_t* t) { +// static uint8_t tcc_channel(const pin_timer_t* t) { // // For the SAMD51 this hardcodes the use of OTMX == 0x0, the output matrix mapping, which uses // // SAMD21-style modulo mapping. // return t->wave_output % tcc_cc_num[t->index]; -//} +// } -//bool channel_ok(const pin_timer_t* t) { +// bool channel_ok(const pin_timer_t* t) { // uint8_t channel_bit = 1 << tcc_channel(t); // return (!t->is_tc && ((tcc_channels[t->index] & channel_bit) == 0)) || // t->is_tc; -//} +// } #define PWM_SRC_CLK_FREQ CLOCK_GetFreq(kCLOCK_IpgClk) pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, - const mcu_pin_obj_t *pin, - uint16_t duty, - uint32_t frequency, - bool variable_frequency) { + const mcu_pin_obj_t *pin, + uint16_t duty, + uint32_t frequency, + bool variable_frequency) { self->pin = pin; self->variable_frequency = variable_frequency; const uint32_t pwm_count = sizeof(mcu_pwm_list) / sizeof(mcu_pwm_obj_t); for (uint32_t i = 0; i < pwm_count; ++i) { - if (mcu_pwm_list[i].pin != pin) + if (mcu_pwm_list[i].pin != pin) { continue; + } printf("pwm: 0x%p, sum %d, chan %d, mux %d\r\n", mcu_pwm_list[i].pwm, mcu_pwm_list[i].submodule, mcu_pwm_list[i].channel, mcu_pwm_list[i].mux_mode); @@ -161,7 +162,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, CLOCK_SetDiv(kCLOCK_AhbDiv, 0x2); /* Set AHB PODF to 2, divide by 3 */ CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ -//TODO re-enable +// TODO re-enable // IOMUXC_SetPinMux( // IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A, /* GPIO_02 is configured as FLEXPWM1_PWM0_A */ // 0U); /* Software Input On Field: Input Path is determined by functionality */ @@ -195,7 +196,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, */ PWM_GetDefaultConfig(&pwmConfig); - //pwmConfig.reloadLogic = kPWM_ReloadPwmFullCycle; + // pwmConfig.reloadLogic = kPWM_ReloadPwmFullCycle; pwmConfig.enableDebugMode = true; if (PWM_Init(PWM1, self->pwm->submodule, &pwmConfig) == kStatus_Fail) { @@ -208,10 +209,10 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, /* Set deadtime count, we set this to about 650ns */ uint16_t deadTimeVal = ((uint64_t)PWM_SRC_CLK_FREQ * 650) / 1000000000; - pwmSignal.pwmChannel = self->pwm->channel; - pwmSignal.level = kPWM_HighTrue; + pwmSignal.pwmChannel = self->pwm->channel; + pwmSignal.level = kPWM_HighTrue; pwmSignal.dutyCyclePercent = frequency / 2; /* 1 percent dutycycle */ - pwmSignal.deadtimeValue = deadTimeVal; + pwmSignal.deadtimeValue = deadTimeVal; PWM_SetupPwm(PWM1, self->pwm->submodule, &pwmSignal, 1, kPWM_SignedCenterAligned, frequency, PWM_SRC_CLK_FREQ); @@ -364,11 +365,11 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, return PWMOUT_OK; } -bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) { return self->pin == NULL; } -void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { +void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) { if (common_hal_pwmio_pwmout_deinited(self)) { return; } @@ -433,7 +434,7 @@ void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t d // } } -uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) { +uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) { return 0; // const pin_timer_t* t = self->timer; // if (t->is_tc) { @@ -471,8 +472,8 @@ uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) { // } } -void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, - uint32_t frequency) { +void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self, + uint32_t frequency) { // if (frequency == 0 || frequency > 6000000) { // mp_raise_ValueError(translate("Invalid PWM frequency")); // } @@ -530,7 +531,7 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, // common_hal_pwmio_pwmout_set_duty_cycle(self, old_duty); } -uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) { +uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) { // uint32_t system_clock = common_hal_mcu_processor_get_frequency(); // const pin_timer_t* t = self->timer; // uint8_t divisor; @@ -546,6 +547,6 @@ uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) { return 0; } -bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) { return self->variable_frequency; } diff --git a/ports/mimxrt10xx/common-hal/rtc/RTC.c b/ports/mimxrt10xx/common-hal/rtc/RTC.c index 6940a1817..aabe2b09f 100644 --- a/ports/mimxrt10xx/common-hal/rtc/RTC.c +++ b/ports/mimxrt10xx/common-hal/rtc/RTC.c @@ -48,19 +48,19 @@ void common_hal_rtc_get_time(timeutils_struct_time_t *tm) { SNVS_HP_RTC_GetDatetime(SNVS, &rtcDate); tm->tm_year = rtcDate.year; - tm->tm_mon = rtcDate.month; + tm->tm_mon = rtcDate.month; tm->tm_mday = rtcDate.day; tm->tm_hour = rtcDate.hour; - tm->tm_min = rtcDate.minute; - tm->tm_sec = rtcDate.second; + tm->tm_min = rtcDate.minute; + tm->tm_sec = rtcDate.second; } void common_hal_rtc_set_time(timeutils_struct_time_t *tm) { snvs_hp_rtc_datetime_t rtcDate; - rtcDate.year = tm->tm_year; - rtcDate.month = tm->tm_mon; - rtcDate.day = tm->tm_mday; - rtcDate.hour = tm->tm_hour; + rtcDate.year = tm->tm_year; + rtcDate.month = tm->tm_mon; + rtcDate.day = tm->tm_mday; + rtcDate.hour = tm->tm_hour; rtcDate.minute = tm->tm_min; rtcDate.second = tm->tm_sec; diff --git a/ports/mimxrt10xx/common-hal/supervisor/Runtime.c b/ports/mimxrt10xx/common-hal/supervisor/Runtime.c index 974f26cec..f82765178 100755..100644 --- a/ports/mimxrt10xx/common-hal/supervisor/Runtime.c +++ b/ports/mimxrt10xx/common-hal/supervisor/Runtime.c @@ -29,9 +29,9 @@ #include "supervisor/serial.h" bool common_hal_supervisor_runtime_get_serial_connected(void) { - return (bool) serial_connected(); + return (bool)serial_connected(); } bool common_hal_supervisor_runtime_get_serial_bytes_available(void) { - return (bool) serial_bytes_available(); + return (bool)serial_bytes_available(); } diff --git a/ports/mimxrt10xx/fatfs_port.c b/ports/mimxrt10xx/fatfs_port.c index c65a73a42..e6eee2049 100644 --- a/ports/mimxrt10xx/fatfs_port.c +++ b/ports/mimxrt10xx/fatfs_port.c @@ -35,14 +35,14 @@ #endif DWORD get_fattime(void) { -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC timeutils_struct_time_t tm; common_hal_rtc_get_time(&tm); return ((tm.tm_year - 1980) << 25) | (tm.tm_mon << 21) | (tm.tm_mday << 16) | - (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); -#else + (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); + #else return ((2016 - 1980) << 25) | ((9) << 21) | ((1) << 16) | ((16) << 11) | ((43) << 5) | (35 / 2); -#endif + #endif } diff --git a/ports/mimxrt10xx/mpconfigport.h b/ports/mimxrt10xx/mpconfigport.h index 51e0ef9ff..16cc63bc2 100644 --- a/ports/mimxrt10xx/mpconfigport.h +++ b/ports/mimxrt10xx/mpconfigport.h @@ -38,14 +38,14 @@ extern uint8_t _ld_filesystem_end; extern uint8_t _ld_default_stack_size; // 20kiB stack -#define CIRCUITPY_DEFAULT_STACK_SIZE ((uint32_t) &_ld_default_stack_size) +#define CIRCUITPY_DEFAULT_STACK_SIZE ((uint32_t)&_ld_default_stack_size) #define MICROPY_PY_BUILTINS_NOTIMPLEMENTED (0) #define MICROPY_PY_FUNCTION_ATTRS (0) #define MICROPY_PY_REVERSE_SPECIAL_METHODS (1) -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR ((uint32_t) &_ld_filesystem_start) -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE ((uint32_t) (&_ld_filesystem_end - &_ld_filesystem_start)) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR ((uint32_t)&_ld_filesystem_start) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE ((uint32_t)(&_ld_filesystem_end - &_ld_filesystem_start)) #include "py/circuitpy_mpconfig.h" diff --git a/ports/mimxrt10xx/mphalport.c b/ports/mimxrt10xx/mphalport.c index 111e97011..ff7a880ab 100644 --- a/ports/mimxrt10xx/mphalport.c +++ b/ports/mimxrt10xx/mphalport.c @@ -34,11 +34,11 @@ #include "fsl_common.h" void mp_hal_delay_us(mp_uint_t delay) { -#if defined(MIMXRT1011_SERIES) || defined(MIMXRT1021_SERIES) + #if defined(MIMXRT1011_SERIES) || defined(MIMXRT1021_SERIES) SDK_DelayAtLeastUs(delay, SystemCoreClock); -#else + #else SDK_DelayAtLeastUs(delay); -#endif + #endif } void mp_hal_disable_all_interrupts(void) { diff --git a/ports/mimxrt10xx/mphalport.h b/ports/mimxrt10xx/mphalport.h index 4ba3a2476..a67e58e33 100644 --- a/ports/mimxrt10xx/mphalport.h +++ b/ports/mimxrt10xx/mphalport.h @@ -36,7 +36,7 @@ // Global millisecond tick count (driven by SysTick interrupt). static inline mp_uint_t mp_hal_ticks_ms(void) { - return supervisor_ticks_ms32(); + return supervisor_ticks_ms32(); } // Number of bytes in receive buffer extern volatile uint8_t usb_rx_count; diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c index 61888fcaa..e6354386a 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c @@ -74,17 +74,17 @@ const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; // Based on the hello_world example in the SDK @@ -111,8 +111,7 @@ void clocks_init(void) { /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c index a994e154d..66dc56e4e 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c index cfab35cea..492d1c6f0 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c index cb9dd34c9..fb4d04b99 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c @@ -87,20 +87,20 @@ const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ + .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; // Based on the hello_world example in the SDK @@ -127,8 +127,7 @@ void clocks_init(void) { /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); @@ -167,7 +166,7 @@ void clocks_init(void) { * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as * well.*/ -#ifndef SKIP_SYSCLK_INIT + #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ @@ -176,7 +175,7 @@ void clocks_init(void) { CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif + #endif /* Disable LPSPI clock gate. */ CLOCK_DisableClock(kCLOCK_Lpspi1); CLOCK_DisableClock(kCLOCK_Lpspi2); @@ -268,10 +267,10 @@ void clocks_init(void) { * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as * well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #ifndef SKIP_SYSCLK_INIT + #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif + #endif /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -282,7 +281,7 @@ void clocks_init(void) { CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); /* Init System pfd3. */ CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); -#endif + #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); /* Bypass Audio PLL. */ diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c index 3d043a14e..754ef01c3 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c index a25937cab..fe39f7e19 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c index 7b9af3a6a..1d67956f8 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c @@ -40,22 +40,22 @@ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; +{ + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; +{ + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; +{ + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; // Based on the hello_world example in the SDK void clocks_init(void) { @@ -81,8 +81,7 @@ void clocks_init(void) { /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); @@ -120,7 +119,7 @@ void clocks_init(void) { /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT + #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ @@ -129,7 +128,7 @@ void clocks_init(void) { CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif + #endif /* Disable LPSPI clock gate. */ CLOCK_DisableClock(kCLOCK_Lpspi1); CLOCK_DisableClock(kCLOCK_Lpspi2); @@ -232,7 +231,7 @@ void clocks_init(void) { /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT + #ifndef SKIP_SYSCLK_INIT /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -243,7 +242,7 @@ void clocks_init(void) { CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Init System pfd3. */ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif + #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); /* Bypass Audio PLL. */ @@ -320,11 +319,11 @@ void clocks_init(void) { /* Set ENET1 Tx clock source. */ IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); /* Set ENET2 Tx clock source. */ -#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) + #if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); -#else + #else IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); -#endif + #endif /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c index fd1e4ddb8..e1c6968fc 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c index ce098ea2b..0e440b6b6 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h index 9b9713bb4..ab0ebf045 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h @@ -31,38 +31,38 @@ #include "pins.h" typedef struct { - uint8_t bank_idx:4; - uint8_t mux_mode:4; + uint8_t bank_idx : 4; + uint8_t mux_mode : 4; uint32_t input_reg; uint8_t input_idx; const mcu_pin_obj_t *pin; } mcu_periph_obj_t; #define PERIPH_PIN(p_bank_idx, p_mux_mode, p_input_reg, p_input_idx, p_pin) \ -{ \ - .bank_idx = p_bank_idx, \ - .mux_mode = p_mux_mode, \ - .input_reg = p_input_reg == 0 ? 0 : (uint32_t)&(IOMUXC->SELECT_INPUT[p_input_reg]), \ - .input_idx = p_input_idx, \ - .pin = p_pin, \ -} + { \ + .bank_idx = p_bank_idx, \ + .mux_mode = p_mux_mode, \ + .input_reg = p_input_reg == 0 ? 0 : (uint32_t)&(IOMUXC->SELECT_INPUT[p_input_reg]), \ + .input_idx = p_input_idx, \ + .pin = p_pin, \ + } typedef struct { PWM_Type *pwm; - pwm_submodule_t submodule:4; - pwm_channels_t channel:4; + pwm_submodule_t submodule : 4; + pwm_channels_t channel : 4; uint8_t mux_mode; const mcu_pin_obj_t *pin; } mcu_pwm_obj_t; #define PWM_PIN(p_pwm, p_submodule, p_channel, p_mux_mode, p_pin) \ -{ \ - .pwm = p_pwm, \ - .submodule = p_submodule, \ - .channel = p_channel, \ - .mux_mode = p_mux_mode, \ - .pin = p_pin, \ -} + { \ + .pwm = p_pwm, \ + .submodule = p_submodule, \ + .channel = p_channel, \ + .mux_mode = p_mux_mode, \ + .pin = p_pin, \ + } extern LPI2C_Type *mcu_i2c_banks[]; extern LPSPI_Type *mcu_spi_banks[]; diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h index 7168854a5..d6d12771c 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h @@ -59,18 +59,18 @@ typedef struct { } mcu_pin_obj_t; #define PIN(p_gpio, p_number, p_enum, p_adc, p_adc_channel, p_mux_reset, p_pad_reset) \ -{ \ - { &mcu_pin_type }, \ - .gpio = p_gpio, \ - .number = p_number, \ - .mux_idx = kIOMUXC_SW_MUX_CTL_PAD_ ## p_enum, \ - .mux_reg = (uint32_t)&(IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_ ## p_enum]), \ - .cfg_reg = (uint32_t)&(IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_PAD_CTL_PAD_ ## p_enum]), \ - .adc = p_adc, \ - .adc_channel = p_adc_channel, \ - .mux_reset = p_mux_reset, \ - .pad_reset = p_pad_reset, \ -} + { \ + { &mcu_pin_type }, \ + .gpio = p_gpio, \ + .number = p_number, \ + .mux_idx = kIOMUXC_SW_MUX_CTL_PAD_##p_enum, \ + .mux_reg = (uint32_t)&(IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_##p_enum]), \ + .cfg_reg = (uint32_t)&(IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_PAD_CTL_PAD_##p_enum]), \ + .adc = p_adc, \ + .adc_channel = p_adc_channel, \ + .mux_reset = p_mux_reset, \ + .pad_reset = p_pad_reset, \ + } #ifdef MIMXRT1011_SERIES #include "MIMXRT1011/pins.h" diff --git a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c index bd471f930..251e6f9ac 100644 --- a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c +++ b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c @@ -12,24 +12,24 @@ #include "boards/flash_config.h" #include "supervisor/linker.h" -status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type *base, uint32_t baseAddr) +status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type * base, uint32_t baseAddr) { flexspi_transfer_t flashXfer; status_t status; /* Write enable */ flashXfer.deviceAddress = baseAddr; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; status = FLEXSPI_TransferBlocking(base, &flashXfer); return status; } -status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type *base) +status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type * base) { /* Wait status ready. */ bool isBusy; @@ -38,57 +38,54 @@ status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type *base) flexspi_transfer_t flashXfer; flashXfer.deviceAddress = 0; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Read; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_READSTATUSREG; - flashXfer.data = &readValue; - flashXfer.dataSize = 1; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_READSTATUSREG; + flashXfer.data = &readValue; + flashXfer.dataSize = 1; do { status = FLEXSPI_TransferBlocking(base, &flashXfer); - if (status != kStatus_Success) - { + if (status != kStatus_Success) { return status; } size_t busyBit = readValue & (1U << qspiflash_config.memConfig.busyOffset); isBusy = (qspiflash_config.memConfig.busyBitPolarity == 0 && busyBit != 0) || - (qspiflash_config.memConfig.busyBitPolarity == 1 && busyBit == 0); + (qspiflash_config.memConfig.busyBitPolarity == 1 && busyBit == 0); } while (isBusy); return status; } -status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type *base, uint32_t address) +status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type * base, uint32_t address) { status_t status; flexspi_transfer_t flashXfer; /* Write enable */ flashXfer.deviceAddress = address; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; status = FLEXSPI_TransferBlocking(base, &flashXfer); - if (status != kStatus_Success) - { + if (status != kStatus_Success) { return status; } flashXfer.deviceAddress = address; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_ERASESECTOR; - status = FLEXSPI_TransferBlocking(base, &flashXfer); + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(base, &flashXfer); - if (status != kStatus_Success) - { + if (status != kStatus_Success) { return status; } @@ -100,7 +97,7 @@ status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type *base, uint3 return status; } -status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src) +status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type * base, uint32_t dstAddr, const uint32_t *src) { status_t status; flexspi_transfer_t flashXfer; @@ -108,35 +105,33 @@ status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type *base, uint3 /* Write enable */ status = flexspi_nor_write_enable(base, dstAddr); - if (status != kStatus_Success) - { + if (status != kStatus_Success) { return status; } /* Prepare page program command */ flashXfer.deviceAddress = dstAddr; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_PAGEPROGRAM; - flashXfer.data = (uint32_t *)src; - flashXfer.dataSize = FLASH_PAGE_SIZE; - status = FLEXSPI_TransferBlocking(base, &flashXfer); - - if (status != kStatus_Success) - { + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_PAGEPROGRAM; + flashXfer.data = (uint32_t *)src; + flashXfer.dataSize = FLASH_PAGE_SIZE; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) { return status; } status = flexspi_nor_wait_bus_busy(base); /* Do software reset. */ -#if defined(FSL_FEATURE_SOC_OTFAD_COUNT) + #if defined(FSL_FEATURE_SOC_OTFAD_COUNT) base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK; base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK); -#else + #else FLEXSPI_SoftwareReset(base); -#endif + #endif return status; } diff --git a/ports/mimxrt10xx/supervisor/internal_flash.c b/ports/mimxrt10xx/supervisor/internal_flash.c index 9c0d9f895..84c478bcf 100644 --- a/ports/mimxrt10xx/supervisor/internal_flash.c +++ b/ports/mimxrt10xx/supervisor/internal_flash.c @@ -49,7 +49,7 @@ extern uint32_t __fatfs_flash_length[]; #define NO_CACHE 0xffffffff #define SECTOR_SIZE 0x1000 /* 4K */ -uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4))); +uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4))); uint32_t _flash_page_addr = NO_CACHE; extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); @@ -58,7 +58,7 @@ extern status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base); void PLACE_IN_ITCM(supervisor_flash_init)(void) { // Update the LUT to make sure all entries are available. - FLEXSPI_UpdateLUT(FLEXSPI, 0, (const uint32_t*) &qspiflash_config.memConfig.lookupTable, 64); + FLEXSPI_UpdateLUT(FLEXSPI, 0, (const uint32_t *)&qspiflash_config.memConfig.lookupTable, 64); } static inline uint32_t lba2addr(uint32_t block) { @@ -74,7 +74,9 @@ uint32_t supervisor_flash_get_block_count(void) { } void PLACE_IN_ITCM(port_internal_flash_flush)(void) { - if (_flash_page_addr == NO_CACHE) return; + if (_flash_page_addr == NO_CACHE) { + return; + } status_t status; // Skip if data is the same @@ -109,13 +111,13 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n supervisor_flash_flush(); uint32_t src = lba2addr(block); - memcpy(dest, (uint8_t*)src, FILESYSTEM_BLOCK_SIZE * num_blocks); + memcpy(dest, (uint8_t *)src, FILESYSTEM_BLOCK_SIZE * num_blocks); return 0; // success } mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32_t num_blocks) { while (num_blocks) { - uint32_t const addr = lba2addr(lba); + uint32_t const addr = lba2addr(lba); uint32_t const page_addr = addr & ~(SECTOR_SIZE - 1); uint32_t count = 8 - (lba % 8); // up to page boundary @@ -135,8 +137,8 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 memcpy(_flash_cache + (addr & (SECTOR_SIZE - 1)), src, count * FILESYSTEM_BLOCK_SIZE); // adjust for next run - lba += count; - src += count * FILESYSTEM_BLOCK_SIZE; + lba += count; + src += count * FILESYSTEM_BLOCK_SIZE; num_blocks -= count; } diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c index 33a85d2b7..2493252d7 100644 --- a/ports/mimxrt10xx/supervisor/port.c +++ b/ports/mimxrt10xx/supervisor/port.c @@ -110,8 +110,8 @@ extern void main(void); // This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c. __attribute__((used, naked)) void Reset_Handler(void) { __disable_irq(); - SCB->VTOR = (uint32_t) &__isr_vector; - __set_MSP((uint32_t) &_ld_stack_top); + SCB->VTOR = (uint32_t)&__isr_vector; + __set_MSP((uint32_t)&_ld_stack_top); /* Disable I cache and D cache */ SCB_DisableICache(); @@ -135,7 +135,7 @@ __attribute__((used, naked)) void Reset_Handler(void) { IOMUXC_GPR->GPR14 = current_gpr14; #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ /* Disable Watchdog Power Down Counter */ @@ -147,11 +147,10 @@ __attribute__((used, naked)) void Reset_Handler(void) { WDOG2->WCR &= ~WDOG_WCR_WDE_MASK; RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ RTWDOG->TOVAL = 0xFFFF; - RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; + RTWDOG->CS = (uint32_t)((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; /* Disable Systick which might be enabled by bootrom */ - if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) - { + if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) { SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; } @@ -160,7 +159,7 @@ __attribute__((used, naked)) void Reset_Handler(void) { // Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write // protect it. - for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_itcm_size) / 4; i++) { (&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i]; } @@ -226,22 +225,22 @@ __attribute__((used, naked)) void Reset_Handler(void) { SCB_EnableICache(); // Copy all of the data to run from DTCM. - for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_data_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_data_size) / 4; i++) { (&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i]; } // Clear DTCM bss. - for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_bss_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_bss_size) / 4; i++) { (&_ld_dtcm_bss_start)[i] = 0; } // Copy all of the data to run from OCRAM. - for (uint32_t i = 0; i < ((size_t) &_ld_ocram_data_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_ocram_data_size) / 4; i++) { (&_ld_ocram_data_destination)[i] = (&_ld_ocram_data_flash_copy)[i]; } // Clear OCRAM bss. - for (uint32_t i = 0; i < ((size_t) &_ld_ocram_bss_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_ocram_bss_size) / 4; i++) { (&_ld_ocram_bss_start)[i] = 0; } @@ -254,9 +253,9 @@ safe_mode_t port_init(void) { clocks_init(); -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC rtc_init(); -#endif + #endif // Always enable the SNVS interrupt. The GPC won't wake us up unless at least one interrupt is // enabled. It won't occur very often so it'll be low overhead. @@ -275,43 +274,43 @@ safe_mode_t port_init(void) { void reset_port(void) { spi_reset(); -#if CIRCUITPY_AUDIOIO + #if CIRCUITPY_AUDIOIO audio_dma_reset(); audioout_reset(); -#endif -#if CIRCUITPY_AUDIOBUSIO + #endif + #if CIRCUITPY_AUDIOBUSIO i2sout_reset(); - //pdmin_reset(); -#endif + // pdmin_reset(); + #endif -#if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE + #if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE touchin_reset(); -#endif + #endif // eic_reset(); -#if CIRCUITPY_PULSEIO + #if CIRCUITPY_PULSEIO pulseout_reset(); -#endif -#if CIRCUITPY_PWMIO + #endif + #if CIRCUITPY_PWMIO pwmout_reset(); -#endif + #endif -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC rtc_reset(); -#endif + #endif -#if CIRCUITPY_GAMEPAD + #if CIRCUITPY_GAMEPAD gamepad_reset(); -#endif -#if CIRCUITPY_GAMEPADSHIFT + #endif + #if CIRCUITPY_GAMEPADSHIFT gamepadshift_reset(); -#endif -#if CIRCUITPY_PEW + #endif + #if CIRCUITPY_PEW pew_reset(); -#endif + #endif - //reset_event_system(); + // reset_event_system(); reset_all_pins(); } @@ -356,12 +355,12 @@ uint32_t port_get_saved_word(void) { return SNVS->LPGPR[1]; } -uint64_t port_get_raw_ticks(uint8_t* subticks) { +uint64_t port_get_raw_ticks(uint8_t *subticks) { uint64_t ticks = 0; uint64_t next_ticks = 1; while (ticks != next_ticks) { ticks = next_ticks; - next_ticks = ((uint64_t) SNVS->HPRTCMR) << 32 | SNVS->HPRTCLR; + next_ticks = ((uint64_t)SNVS->HPRTCMR) << 32 | SNVS->HPRTCLR; } if (subticks != NULL) { *subticks = ticks % 32; @@ -397,7 +396,8 @@ void port_interrupt_after_ticks(uint32_t ticks) { current_ticks += ticks; SNVS->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK; // Wait for the alarm to be disabled. - while ((SNVS->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0) {} + while ((SNVS->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0) { + } SNVS->HPTAMR = current_ticks >> (32 - 5); SNVS->HPTALR = current_ticks << 5 | subticks; SNVS->HPCR |= SNVS_HPCR_HPTA_EN_MASK; @@ -407,9 +407,9 @@ void port_idle_until_interrupt(void) { // App note here: https://www.nxp.com/docs/en/application-note/AN12085.pdf // Clear the FPU interrupt because it can prevent us from sleeping. - if (__get_FPSCR() & ~(0x9f)) { - __set_FPSCR(__get_FPSCR() & ~(0x9f)); - (void) __get_FPSCR(); + if (__get_FPSCR() & ~(0x9f)) { + __set_FPSCR(__get_FPSCR() & ~(0x9f)); + (void)__get_FPSCR(); } NVIC_ClearPendingIRQ(SNVS_HP_WRAPPER_IRQn); CLOCK_SetMode(kCLOCK_ModeWait); @@ -420,43 +420,39 @@ void port_idle_until_interrupt(void) { /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void MemManage_Handler(void) -{ +__attribute__((used)) void MemManage_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void BusFault_Handler(void) -{ +__attribute__((used)) void BusFault_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void UsageFault_Handler(void) -{ +__attribute__((used)) void UsageFault_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void HardFault_Handler(void) -{ +__attribute__((used)) void HardFault_Handler(void) { reset_into_safe_mode(HARD_CRASH); while (true) { - asm("nop;"); + asm ("nop;"); } } diff --git a/ports/mimxrt10xx/supervisor/serial.c b/ports/mimxrt10xx/supervisor/serial.c index 01656a819..ea706d8a8 100644 --- a/ports/mimxrt10xx/supervisor/serial.c +++ b/ports/mimxrt10xx/supervisor/serial.c @@ -35,7 +35,7 @@ // static LPUART_Type *uart_instance = LPUART1; // evk static LPUART_Type *uart_instance = LPUART4; // feather 1011 -//static LPUART_Type *uart_instance = LPUART2; // feather 1062 +// static LPUART_Type *uart_instance = LPUART2; // feather 1062 static uint32_t UartSrcFreq(void) { uint32_t freq; @@ -79,8 +79,8 @@ bool serial_bytes_available(void) { return LPUART_GetStatusFlags(uart_instance) & kLPUART_RxDataRegFullFlag; } -void serial_write(const char* text) { - LPUART_WriteBlocking(uart_instance, (uint8_t*)text, strlen(text)); +void serial_write(const char *text) { + LPUART_WriteBlocking(uart_instance, (uint8_t *)text, strlen(text)); } void serial_write_substring(const char *text, uint32_t len) { @@ -88,5 +88,5 @@ void serial_write_substring(const char *text, uint32_t len) { return; } - LPUART_WriteBlocking(uart_instance, (uint8_t*)text, len); + LPUART_WriteBlocking(uart_instance, (uint8_t *)text, len); } diff --git a/ports/mimxrt10xx/supervisor/usb.c b/ports/mimxrt10xx/supervisor/usb.c index 91135289c..57f038799 100644 --- a/ports/mimxrt10xx/supervisor/usb.c +++ b/ports/mimxrt10xx/supervisor/usb.c @@ -33,11 +33,11 @@ void init_usb_hardware(void) { CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); -#ifdef USBPHY + #ifdef USBPHY USBPHY_Type *usb_phy = USBPHY; -#else + #else USBPHY_Type *usb_phy = USBPHY1; -#endif + #endif // Enable PHY support for Low speed device + LS via FS Hub usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; 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