diff options
Diffstat (limited to 'ports')
84 files changed, 2265 insertions, 1055 deletions
diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/board.c b/ports/atmel-samd/boards/bdmicro_vina_d51/board.c new file mode 100644 index 000000000..bd63baa6f --- /dev/null +++ b/ports/atmel-samd/boards/bdmicro_vina_d51/board.c @@ -0,0 +1,48 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "mpconfigboard.h" + +void board_init(void) +{ + // struct port_config pin_conf; + // port_get_config_defaults(&pin_conf); + // + // pin_conf.direction = PORT_PIN_DIR_OUTPUT; + // port_pin_set_config(MICROPY_HW_LED_TX, &pin_conf); + // port_pin_set_output_level(MICROPY_HW_LED_TX, true); + // + // port_pin_set_config(MICROPY_HW_LED_RX, &pin_conf); + // port_pin_set_output_level(MICROPY_HW_LED_RX, true); +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.h b/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.h new file mode 100644 index 000000000..6bc9bb706 --- /dev/null +++ b/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.h @@ -0,0 +1,28 @@ +#define MICROPY_HW_BOARD_NAME "BDMICRO VINA-D51" +#define MICROPY_HW_MCU_NAME "samd51n20" + +#define CIRCUITPY_MCU_FAMILY samd51 + +// These are pins not to reset. +// Don't reset QSPI data pins +#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) +#define MICROPY_PORT_B (PORT_PB10 | PORT_PB11) +#define MICROPY_PORT_C (0) +#define MICROPY_PORT_D (0) + +#define BOARD_HAS_CRYSTAL 1 + +#define DEFAULT_I2C_BUS_SDA (&pin_PB02) +#define DEFAULT_I2C_BUS_SCL (&pin_PB03) +#define DEFAULT_SPI_BUS_MISO (&pin_PB23) +#define DEFAULT_UART_BUS_TX (&pin_PB24) +#define DEFAULT_UART_BUS_RX (&pin_PB25) +#define DEFAULT_SPI_BUS_MOSI (&pin_PC27) +#define DEFAULT_SPI_BUS_SCK (&pin_PC28) +#define MICROPY_HW_LED_STATUS (&pin_PA15) +#define MICROPY_HW_LED_RX (&pin_PC05) +#define MICROPY_HW_LED_TX (&pin_PC06) + +// USB is always used internally so skip the pin objects for it. +#define IGNORE_PIN_PA24 1 +#define IGNORE_PIN_PA25 1 diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.mk b/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.mk new file mode 100644 index 000000000..f1b2f4c1d --- /dev/null +++ b/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.mk @@ -0,0 +1,12 @@ +USB_VID = 0x31e2 +USB_PID = 0x2011 +USB_PRODUCT = "VINA-D51" +USB_MANUFACTURER = "BDMICRO LLC" + +CHIP_VARIANT = SAMD51N20A +CHIP_FAMILY = samd51 + +QSPI_FLASH_FILESYSTEM = 1 +EXTERNAL_FLASH_DEVICE_COUNT = 2 +EXTERNAL_FLASH_DEVICES = "MX25L51245G","GD25S512MD" +LONGINT_IMPL = MPZ diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/pins.c b/ports/atmel-samd/boards/bdmicro_vina_d51/pins.c new file mode 100644 index 000000000..931e0328f --- /dev/null +++ b/ports/atmel-samd/boards/bdmicro_vina_d51/pins.c @@ -0,0 +1,82 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PC20) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PC21) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PB31) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA17) }, + { MP_ROM_QSTR(MP_QSTR_DAC0), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_ESP01_EN), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_ESP01_GPIO0), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_UART3_RTS), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_ESP01_GPIO2), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_UART3_CTS), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_ESP01_RESET), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_ESP01_RX), MP_ROM_PTR(&pin_PB21) }, + { MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PB21) }, + { MP_ROM_QSTR(MP_QSTR_ESP01_TX), MP_ROM_PTR(&pin_PB20) }, + { MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PB20) }, + { MP_ROM_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_I2S_FS_0), MP_ROM_PTR(&pin_PA20) }, + { MP_ROM_QSTR(MP_QSTR_I2S_FS_1), MP_ROM_PTR(&pin_PA23) }, + { MP_ROM_QSTR(MP_QSTR_I2S_MCK_0), MP_ROM_PTR(&pin_PB17) }, + { MP_ROM_QSTR(MP_QSTR_I2S_MCK_1), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_I2S_SCK_0), MP_ROM_PTR(&pin_PB16) }, + { MP_ROM_QSTR(MP_QSTR_I2S_SCK_1), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_I2S_SDI), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_I2S_SDO), MP_ROM_PTR(&pin_PA21) }, + { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_LED_STATUS), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_PB18) }, + { MP_ROM_QSTR(MP_QSTR_LED_R), MP_ROM_PTR(&pin_PB19) }, + { MP_ROM_QSTR(MP_QSTR_LED_RX), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_LED_TX), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_RS485_RE), MP_ROM_PTR(&pin_PC15) }, + { MP_ROM_QSTR(MP_QSTR_RS485_RX), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_RS485_TE), MP_ROM_PTR(&pin_PC14) }, + { MP_ROM_QSTR(MP_QSTR_RS485_TX), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_SPI_MISO), MP_ROM_PTR(&pin_PB23) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB23) }, + { MP_ROM_QSTR(MP_QSTR_SPI_MOSI), MP_ROM_PTR(&pin_PC27) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PC27) }, + { MP_ROM_QSTR(MP_QSTR_SPI_SCK), MP_ROM_PTR(&pin_PC28) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PC28) }, + { MP_ROM_QSTR(MP_QSTR_SPI_SS), MP_ROM_PTR(&pin_PB22) }, + { MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PB22) }, + { MP_ROM_QSTR(MP_QSTR_UART1_CTS), MP_ROM_PTR(&pin_PC19) }, + { MP_ROM_QSTR(MP_QSTR_UART1_RTS), MP_ROM_PTR(&pin_PC18) }, + { MP_ROM_QSTR(MP_QSTR_UART1_RX), MP_ROM_PTR(&pin_PC17) }, + { MP_ROM_QSTR(MP_QSTR_UART1_TX), MP_ROM_PTR(&pin_PC16) }, + { MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PB25) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB25) }, + { MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PB24) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB24) }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk b/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk index 5656d4cb8..178258b6c 100755 --- a/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk +++ b/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk @@ -16,6 +16,7 @@ CIRCUITPY_COUNTIO = 0 CIRCUITPY_FREQUENCYIO = 0 CIRCUITPY_I2CPERIPHERAL = 0 CIRCUITPY_VECTORIO = 0 +MICROPY_PY_ASYNC_AWAIT = 0 SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk index 81391b953..13ec9e861 100644 --- a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk +++ b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk @@ -15,6 +15,7 @@ LONGINT_IMPL = MPZ CIRCUITPY_DISPLAYIO = 0 CIRCUITPY_FREQUENCYIO = 0 CIRCUITPY_I2CPERIPHERAL = 0 +MICROPY_PY_ASYNC_AWAIT = 0 SUPEROPT_GC = 0 CFLAGS_INLINE_LIMIT = 55 diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/board.c b/ports/atmel-samd/boards/dynossat_edu_eps/board.c new file mode 100644 index 000000000..c8e20206a --- /dev/null +++ b/ports/atmel-samd/boards/dynossat_edu_eps/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" + +void board_init(void) +{ +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h new file mode 100644 index 000000000..ef4fa8f99 --- /dev/null +++ b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h @@ -0,0 +1,40 @@ +#define MICROPY_HW_BOARD_NAME "DynOSSAT-EDU-EPS" +#define MICROPY_HW_MCU_NAME "samd21g18" + +#define MICROPY_HW_NEOPIXEL (&pin_PA06) + +#define SPI_FLASH_MOSI_PIN &pin_PA22 +#define SPI_FLASH_MISO_PIN &pin_PA21 +#define SPI_FLASH_SCK_PIN &pin_PA23 +#define SPI_FLASH_CS_PIN &pin_PA20 + +// These are pins not to reset. +#define MICROPY_PORT_A ( 0 ) +#define MICROPY_PORT_B ( 0 ) +#define MICROPY_PORT_C ( 0 ) + +#define BOARD_HAS_CRYSTAL 1 + +#define DEFAULT_I2C_BUS_SCL (&pin_PA09) +#define DEFAULT_I2C_BUS_SDA (&pin_PA08) + +#define DEFAULT_SPI_BUS_SCK (&pin_PB11) +#define DEFAULT_SPI_BUS_MOSI (&pin_PA12) +#define DEFAULT_SPI_BUS_MISO (&pin_PB10) + +#define DEFAULT_UART_BUS_RX (&pin_PA17) +#define DEFAULT_UART_BUS_TX (&pin_PA16) + +// USB is always used internally so skip the pin objects for it. +#define IGNORE_PIN_PA24 1 +#define IGNORE_PIN_PA25 1 +#define IGNORE_PIN_PA03 1 +#define IGNORE_PIN_PA13 1 +#define IGNORE_PIN_PA14 1 +#define IGNORE_PIN_PA15 1 +#define IGNORE_PIN_PA18 1 +#define IGNORE_PIN_PA27 1 +#define IGNORE_PIN_PA28 1 +#define IGNORE_PIN_PB08 1 +#define IGNORE_PIN_PB22 1 +#define IGNORE_PIN_PB23 1 diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.mk b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.mk new file mode 100644 index 000000000..3c0cc07be --- /dev/null +++ b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.mk @@ -0,0 +1,23 @@ +USB_VID = 0x04D8 +USB_PID = 0xEAD1 + +USB_PRODUCT = "DynOSSAT-EDU-EPS-v1.0" +USB_MANUFACTURER = "BH Dynamics" + +CHIP_VARIANT = SAMD21G18A +CHIP_FAMILY = samd21 + +SPI_FLASH_FILESYSTEM = 1 +EXTERNAL_FLASH_DEVICE_COUNT = 1 +EXTERNAL_FLASH_DEVICES = "GD25Q32C" +LONGINT_IMPL = MPZ + +CIRCUITPY_BITBANGIO = 0 +CIRCUITPY_FREQUENCYIO = 0 +CIRCUITPY_COUNTIO = 0 +CIRCUITPY_I2CPERIPHERAL = 0 +CIRCUITPY_VECTORIO = 0 + +CFLAGS_INLINE_LIMIT = 60 + +SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/pins.c b/ports/atmel-samd/boards/dynossat_edu_eps/pins.c new file mode 100644 index 000000000..a910311d4 --- /dev/null +++ b/ports/atmel-samd/boards/dynossat_edu_eps/pins.c @@ -0,0 +1,32 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PA30) }, + { MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PA31) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA17) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_OVTEMP), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_SAT_RESET), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_SAT_PWR_ENABLE), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_INT_IMU_OBC), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PWRMON_SDA), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PWRMON_SCL), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PWRMON_ALERT), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_I2C_MONITOR), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/board.c b/ports/atmel-samd/boards/dynossat_edu_obc/board.c new file mode 100644 index 000000000..c8e20206a --- /dev/null +++ b/ports/atmel-samd/boards/dynossat_edu_obc/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" + +void board_init(void) +{ +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h new file mode 100644 index 000000000..d7df8db74 --- /dev/null +++ b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h @@ -0,0 +1,44 @@ +#define MICROPY_HW_BOARD_NAME "DynOSSAT-EDU-OBC" +#define MICROPY_HW_MCU_NAME "samd51j20" + +#define MICROPY_HW_NEOPIXEL (&pin_PA08) + +#define SPI_FLASH_MOSI_PIN &pin_PA16 +#define SPI_FLASH_MISO_PIN &pin_PA18 +#define SPI_FLASH_SCK_PIN &pin_PA17 +#define SPI_FLASH_CS_PIN &pin_PA19 + +// These are pins not to reset. +#define MICROPY_PORT_A ( PORT_PA16 | PORT_PA17 | PORT_PA18 | PORT_PA19 ) +#define MICROPY_PORT_B ( 0 ) +#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_D ( 0 ) + +#define BOARD_HAS_CRYSTAL 1 + +#define DEFAULT_I2C_BUS_SCL (&pin_PB13) +#define DEFAULT_I2C_BUS_SDA (&pin_PB12) + +#define DEFAULT_SPI_BUS_SCK (&pin_PB03) +#define DEFAULT_SPI_BUS_MOSI (&pin_PB02) +#define DEFAULT_SPI_BUS_MISO (&pin_PB01) + +#define DEFAULT_UART_BUS_RX (&pin_PA23) +#define DEFAULT_UART_BUS_TX (&pin_PA22) + +// USB is always used internally so skip the pin objects for it. +#define IGNORE_PIN_PA24 1 +#define IGNORE_PIN_PA25 1 +#define IGNORE_PIN_PA02 1 +#define IGNORE_PIN_PA13 1 +#define IGNORE_PIN_PA14 1 +#define IGNORE_PIN_PA20 1 +#define IGNORE_PIN_PA21 1 +#define IGNORE_PIN_PA27 1 +#define IGNORE_PIN_PB00 1 +#define IGNORE_PIN_PB04 1 +#define IGNORE_PIN_PB05 1 +#define IGNORE_PIN_PB16 1 +#define IGNORE_PIN_PB17 1 +#define IGNORE_PIN_PB23 1 +#define IGNORE_PIN_PB31 1 diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.mk b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.mk new file mode 100644 index 000000000..360940cf1 --- /dev/null +++ b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.mk @@ -0,0 +1,16 @@ +USB_VID = 0x04D8 +USB_PID = 0xEAD2 + +USB_PRODUCT = "DynOSSAT-EDU-OBC-v1.0" +USB_MANUFACTURER = "BH Dynamics" + +CHIP_VARIANT = SAMD51J20A +CHIP_FAMILY = samd51 + +SPI_FLASH_FILESYSTEM = 1 +EXTERNAL_FLASH_DEVICE_COUNT = 1 +EXTERNAL_FLASH_DEVICES = "GD25Q32C" +LONGINT_IMPL = MPZ + +CFLAGS_INLINE_LIMIT = 60 +SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/pins.c b/ports/atmel-samd/boards/dynossat_edu_obc/pins.c new file mode 100644 index 000000000..a560360f7 --- /dev/null +++ b/ports/atmel-samd/boards/dynossat_edu_obc/pins.c @@ -0,0 +1,40 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PA23) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA23) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB30) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA30) }, + { MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PA31) }, + { MP_ROM_QSTR(MP_QSTR_SD_CS), MP_ROM_PTR(&pin_PB22) }, + { MP_ROM_QSTR(MP_QSTR_INT_IMU), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_SAT_POWER), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk index 1ad429295..c33ab0740 100644 --- a/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk @@ -22,6 +22,7 @@ CIRCUITPY_USB_MIDI = 0 CIRCUITPY_USB_HID = 0 CIRCUITPY_TOUCHIO = 0 CFLAGS_INLINE_LIMIT = 35 + # Make more room. SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk index 44606e340..49b0ef5e3 100644 --- a/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk +++ b/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk @@ -22,6 +22,7 @@ CIRCUITPY_SAMD = 0 CIRCUITPY_USB_MIDI = 0 CIRCUITPY_USB_HID = 0 CIRCUITPY_TOUCHIO = 0 + CFLAGS_INLINE_LIMIT = 35 # Make more room. SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk b/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk index 18cef738e..249265151 100644 --- a/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk +++ b/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk @@ -11,12 +11,12 @@ LONGINT_IMPL = MPZ # Not needed. CIRCUITPY_AUDIOBUSIO = 0 -CIRCUITPY_FRAMEBUFFERIO = 0 +CIRCUITPY_AUDIOMP3 = 0 +CIRCUITPY_BLEIO_HCI = 0 CIRCUITPY_DISPLAYIO = 0 -CIRCUITPY_RGBMATRIX = 0 +CIRCUITPY_FRAMEBUFFERIO = 0 CIRCUITPY_PS2IO = 0 -CIRCUITPY_AUDIOMP3 = 0 - +CIRCUITPY_RGBMATRIX = 0 CIRCUITPY_ULAB = 0 # Override optimization to keep binary small diff --git a/ports/atmel-samd/boards/matrixportal_m4/mpconfigboard.h b/ports/atmel-samd/boards/matrixportal_m4/mpconfigboard.h index 0368d577b..cbca94e03 100644 --- a/ports/atmel-samd/boards/matrixportal_m4/mpconfigboard.h +++ b/ports/atmel-samd/boards/matrixportal_m4/mpconfigboard.h @@ -15,8 +15,8 @@ #define MICROPY_PORT_C (0) #define MICROPY_PORT_D (0) -#define DEFAULT_I2C_BUS_SCL (&pin_PB03) -#define DEFAULT_I2C_BUS_SDA (&pin_PB02) +#define DEFAULT_I2C_BUS_SCL (&pin_PB30) +#define DEFAULT_I2C_BUS_SDA (&pin_PB31) #define DEFAULT_SPI_BUS_SCK (&pin_PA16) #define DEFAULT_SPI_BUS_MOSI (&pin_PA19) diff --git a/ports/atmel-samd/boards/metro_m4_airlift_lite/mpconfigboard.mk b/ports/atmel-samd/boards/metro_m4_airlift_lite/mpconfigboard.mk index e999629c3..4895cda77 100644 --- a/ports/atmel-samd/boards/metro_m4_airlift_lite/mpconfigboard.mk +++ b/ports/atmel-samd/boards/metro_m4_airlift_lite/mpconfigboard.mk @@ -6,10 +6,6 @@ USB_MANUFACTURER = "Adafruit Industries LLC" CHIP_VARIANT = SAMD51J19A CHIP_FAMILY = samd51 -# Support _bleio via the on-board ESP32 module. -CIRCUITPY_BLEIO = 1 -CIRCUITPY_BLEIO_HCI = 1 - QSPI_FLASH_FILESYSTEM = 1 EXTERNAL_FLASH_DEVICE_COUNT = 3 EXTERNAL_FLASH_DEVICES = "S25FL116K, S25FL216K, GD25Q16C" diff --git a/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk b/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk index 402db7ebc..7eda151f3 100644 --- a/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk +++ b/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk @@ -17,6 +17,7 @@ CIRCUITPY_COUNTIO = 0 CIRCUITPY_RTC = 0 CIRCUITPY_FREQUENCYIO = 0 CIRCUITPY_I2CPERIPHERAL = 0 +MICROPY_PY_ASYNC_AWAIT = 0 SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/winterbloom_sol/mpconfigboard.mk b/ports/atmel-samd/boards/winterbloom_sol/mpconfigboard.mk index 9217cdf23..fcefaee9b 100644 --- a/ports/atmel-samd/boards/winterbloom_sol/mpconfigboard.mk +++ b/ports/atmel-samd/boards/winterbloom_sol/mpconfigboard.mk @@ -18,7 +18,7 @@ LONGINT_IMPL = MPZ # Disable modules that are unusable on this special-purpose board. CIRCUITPY_AUDIOBUSIO = 0 CIRCUITPY_AUDIOIO = 0 -CIRCUITPY_BLEIO = 0 +CIRCUITPY_BLEIO_HCI = 0 CIRCUITPY_DISPLAYIO = 0 CIRCUITPY_FRAMEBUFFERIO = 0 CIRCUITPY_GAMEPAD = 0 diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.h b/ports/atmel-samd/common-hal/pulseio/PulseIn.h index 99358178f..b91bbd703 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.h +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.h @@ -51,7 +51,6 @@ void pulsein_reset(void); void pulsein_interrupt_handler(uint8_t channel); void pulsein_timer_interrupt_handler(uint8_t index); #ifdef SAMD21 -void rtc_set_continuous(void); void rtc_start_pulsein(void); void rtc_end_pulsein(void); #endif diff --git a/ports/atmel-samd/mpconfigport.mk b/ports/atmel-samd/mpconfigport.mk index a16daf4b0..1929e146d 100644 --- a/ports/atmel-samd/mpconfigport.mk +++ b/ports/atmel-samd/mpconfigport.mk @@ -37,6 +37,9 @@ ifndef CIRCUITPY_TOUCHIO_USE_NATIVE CIRCUITPY_TOUCHIO_USE_NATIVE = 1 endif +# No room for HCI _bleio on SAMD21. +CIRCUITPY_BLEIO_HCI = 0 + CIRCUITPY_SDCARDIO ?= 0 # Not enough RAM for framebuffers diff --git a/ports/atmel-samd/peripherals b/ports/atmel-samd/peripherals -Subproject 2ff4ab05101ce7d3e105009cc6612df6e992123 +Subproject a7e39c4d01aa5916015beecb021777617e77b0a diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 8d52c30c5..d65d09825 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -96,19 +96,20 @@ #endif volatile bool hold_interrupt = false; #ifdef SAMD21 +static void rtc_set_continuous(bool continuous) { + while (RTC->MODE0.STATUS.bit.SYNCBUSY); + RTC->MODE0.READREQ.reg = (continuous ? RTC_READREQ_RCONT : 0) | 0x0010; + while (RTC->MODE0.STATUS.bit.SYNCBUSY); +} + void rtc_start_pulsein(void) { - rtc_set_continuous(); + rtc_set_continuous(true); hold_interrupt = true; } void rtc_end_pulsein(void) { hold_interrupt = false; -} - -void rtc_set_continuous(void) { - while (RTC->MODE0.STATUS.bit.SYNCBUSY); - RTC->MODE0.READREQ.reg = RTC_READREQ_RREQ | RTC_READREQ_RCONT | 0x0010; - while (RTC->MODE0.STATUS.bit.SYNCBUSY); + rtc_set_continuous(false); } #endif @@ -430,6 +431,42 @@ uint32_t port_get_saved_word(void) { static volatile uint64_t overflowed_ticks = 0; static volatile bool _ticks_enabled = false; +static uint32_t _get_count(uint32_t* overflow_count) { + #ifdef SAM_D5X_E5X + while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) {} + #endif + #ifdef SAMD21 + // Request a read so we don't stall the bus later. See section 14.3.1.5 Read Request + RTC->MODE0.READREQ.reg = RTC_READREQ_RREQ | 0x0010; + while (RTC->MODE0.STATUS.bit.SYNCBUSY != 0) {} + #endif + // Disable interrupts so we can grab the count and the overflow. + common_hal_mcu_disable_interrupts(); + uint32_t count = RTC->MODE0.COUNT.reg; + if (overflow_count != NULL) { + *overflow_count = overflowed_ticks; + } + common_hal_mcu_enable_interrupts(); + + return count; +} + +static void _port_interrupt_after_ticks(uint32_t ticks) { + uint32_t current_ticks = _get_count(NULL); + if (ticks > 1 << 28) { + // We'll interrupt sooner with an overflow. + return; + } +#ifdef SAMD21 + if (hold_interrupt) { + return; + } +#endif + RTC->MODE0.COMP[0].reg = current_ticks + (ticks << 4); + RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; + RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + void RTC_Handler(void) { uint32_t intflag = RTC->MODE0.INTFLAG.reg; if (intflag & RTC_MODE0_INTFLAG_OVF) { @@ -452,7 +489,7 @@ void RTC_Handler(void) { supervisor_tick(); // Check _ticks_enabled again because a tick handler may have turned it off. if (_ticks_enabled) { - port_interrupt_after_ticks(1); + _port_interrupt_after_ticks(1); } } #endif @@ -462,24 +499,14 @@ void RTC_Handler(void) { } } -static uint32_t _get_count(void) { - #ifdef SAM_D5X_E5X - while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) {} - #endif - #ifdef SAMD21 - while (RTC->MODE0.STATUS.bit.SYNCBUSY != 0) {} - #endif - - return RTC->MODE0.COUNT.reg; -} - uint64_t port_get_raw_ticks(uint8_t* subticks) { - uint32_t current_ticks = _get_count(); + uint32_t overflow_count; + uint32_t current_ticks = _get_count(&overflow_count); if (subticks != NULL) { *subticks = (current_ticks % 16) * 2; } - return overflowed_ticks + current_ticks / 16; + return overflow_count + current_ticks / 16; } // Enable 1/1024 second tick. @@ -489,8 +516,9 @@ void port_enable_tick(void) { RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; #endif #ifdef SAMD21 + // TODO: Switch to using the PER *event* from the RTC to generate an interrupt via EVSYS. _ticks_enabled = true; - port_interrupt_after_ticks(1); + _port_interrupt_after_ticks(1); #endif } @@ -505,20 +533,14 @@ void port_disable_tick(void) { #endif } +// This is called by sleep, we ignore it when our ticks are enabled because +// they'll wake us up earlier. If we don't, we'll mess up ticks by overwriting +// the next RTC wake up time. void port_interrupt_after_ticks(uint32_t ticks) { - uint32_t current_ticks = _get_count(); - if (ticks > 1 << 28) { - // We'll interrupt sooner with an overflow. + if (_ticks_enabled) { return; } -#ifdef SAMD21 - if (hold_interrupt) { - return; - } -#endif - RTC->MODE0.COMP[0].reg = current_ticks + (ticks << 4); - RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; - RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + _port_interrupt_after_ticks(ticks); } void port_sleep_until_interrupt(void) { diff --git a/ports/cxd56/Makefile b/ports/cxd56/Makefile index 7e145f5e2..5201f0db5 100644 --- a/ports/cxd56/Makefile +++ b/ports/cxd56/Makefile @@ -162,7 +162,7 @@ SRC_SHARED_MODULE_EXPANDED = $(addprefix shared-bindings/, $(SRC_SHARED_MODULE)) SRC_S = supervisor/cpu.s -SRC_C = \ +SRC_C += \ background.c \ fatfs_port.c \ mphalport.c \ diff --git a/ports/esp32s2/CMakeLists.txt b/ports/esp32s2/CMakeLists.txt index 0d7f48995..6ad33282f 100644 --- a/ports/esp32s2/CMakeLists.txt +++ b/ports/esp32s2/CMakeLists.txt @@ -6,7 +6,7 @@ set(ENV{IDF_PATH} ${CMAKE_SOURCE_DIR}/esp-idf) # The component list here determines what options we get in menuconfig and what the ninja file # can build. -set(COMPONENTS esptool_py soc driver log main esp-tls mbedtls esp_event esp_netif esp_wifi lwip wpa_supplicant freertos) +set(COMPONENTS esptool_py soc driver log main esp-tls mbedtls esp_event esp_adc_cal esp_netif esp_wifi lwip wpa_supplicant freertos) include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(circuitpython) diff --git a/ports/esp32s2/Makefile b/ports/esp32s2/Makefile index f8818eca0..8d891edd0 100644 --- a/ports/esp32s2/Makefile +++ b/ports/esp32s2/Makefile @@ -97,6 +97,7 @@ INC += -isystem esp-idf/components/lwip/include/apps/sntp INC += -isystem esp-idf/components/hal/include INC += -isystem esp-idf/components/hal/esp32s2/include INC += -isystem esp-idf/components/log/include/ +INC += -isystem esp-idf/components/driver/esp32s2/include INC += -isystem esp-idf/components/soc/include INC += -isystem esp-idf/components/soc/src/esp32s2/include INC += -isystem esp-idf/components/soc/soc/include @@ -268,14 +269,13 @@ menuconfig: $(BUILD)/esp-idf/config $(Q)grep -Fvxf $(DEBUG_SDKCONFIG) -f $(FLASH_SDKCONFIG) $(BUILD)/sdkconfig.diff > boards/$(BOARD)/sdkconfig # qstr builds include headers so we need to make sure they are up to date -$(HEADER_BUILD)/qstr.i.last: | $(BUILD)/esp-idf/config/sdkconfig.h +$(HEADER_BUILD)/qstr.split: | $(BUILD)/esp-idf/config/sdkconfig.h -# Order here matters -ESP_IDF_COMPONENTS_LINK = freertos log esp_system esp32s2 bootloader_support pthread esp_timer vfs spi_flash app_update esp_common esp32s2 heap newlib driver xtensa soc esp_ringbuf esp_wifi esp_event wpa_supplicant mbedtls efuse nvs_flash esp_netif lwip esp_rom esp-tls +ESP_IDF_COMPONENTS_LINK = freertos log hal esp_system esp_adc_cal esp32s2 bootloader_support pthread esp_timer vfs spi_flash app_update esp_common esp32s2 heap newlib driver xtensa soc esp_ringbuf esp_wifi esp_event wpa_supplicant mbedtls efuse nvs_flash esp_netif lwip esp_rom esp-tls ESP_IDF_COMPONENTS_INCLUDE = driver freertos log soc -INC += $(foreach component, $(ESP_IDF_COMPONENTS_INCLUDE), -Iesp-idf/components/$(component)/include) +INC += $(foreach component, $(ESP_IDF_COMPONENTS_INCLUDE), -isystem esp-idf/components/$(component)/include) ESP_IDF_COMPONENTS_EXPANDED = $(foreach component, $(ESP_IDF_COMPONENTS_LINK), $(BUILD)/esp-idf/esp-idf/$(component)/lib$(component).a) ESP_IDF_WIFI_COMPONENTS_EXPANDED = $(foreach component, $(ESP_IDF_WIFI_COMPONENTS_LINK), $(BUILD)/esp-idf/esp-idf/$(component)/lib$(component).a) @@ -283,11 +283,11 @@ ESP_IDF_WIFI_COMPONENTS_EXPANDED = $(foreach component, $(ESP_IDF_WIFI_COMPONENT MBEDTLS_COMPONENTS_LINK = crypto tls x509 MBEDTLS_COMPONENTS_LINK_EXPANDED = $(foreach component, $(MBEDTLS_COMPONENTS_LINK), $(BUILD)/esp-idf/esp-idf/mbedtls/mbedtls/library/libmbed$(component).a) -BINARY_BLOBS = esp-idf/components/xtensa/esp32s2/libhal.a +BINARY_BLOBS = esp-idf/components/xtensa/esp32s2/libxt_hal.a BINARY_WIFI_BLOBS = libcoexist.a libcore.a libespnow.a libmesh.a libnet80211.a libpp.a librtc.a libsmartconfig.a libphy.a BINARY_BLOBS += $(addprefix esp-idf/components/esp_wifi/lib/esp32s2/, $(BINARY_WIFI_BLOBS)) -ESP_IDF_COMPONENTS_EXPANDED += $(BUILD)/esp-idf/esp-idf/soc/soc/esp32s2/libsoc_esp32s2.a esp-idf/components/xtensa/esp32s2/libhal.a +ESP_IDF_COMPONENTS_EXPANDED += $(BUILD)/esp-idf/esp-idf/soc/soc/esp32s2/libsoc_esp32s2.a esp-idf/components/xtensa/esp32s2/libxt_hal.a ESP_AUTOGEN_LD = $(BUILD)/esp-idf/esp-idf/esp32s2/esp32s2_out.ld $(BUILD)/esp-idf/esp-idf/esp32s2/ld/esp32s2.project.ld FLASH_FLAGS = --flash_mode $(CIRCUITPY_ESP_FLASH_MODE) --flash_freq $(CIRCUITPY_ESP_FLASH_FREQ) --flash_size $(CIRCUITPY_ESP_FLASH_SIZE) diff --git a/ports/esp32s2/boards/adafruit_metro_esp32s2/sdkconfig b/ports/esp32s2/boards/adafruit_metro_esp32s2/sdkconfig index 9d8bbde96..80b9a2cf8 100644 --- a/ports/esp32s2/boards/adafruit_metro_esp32s2/sdkconfig +++ b/ports/esp32s2/boards/adafruit_metro_esp32s2/sdkconfig @@ -31,3 +31,9 @@ CONFIG_SPIRAM_USE_MEMMAP=y CONFIG_SPIRAM_MEMTEST=y # CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set # end of SPI RAM config + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="Metro-ESP32S2" +# end of LWIP diff --git a/ports/esp32s2/boards/microdev_micro_s2/sdkconfig b/ports/esp32s2/boards/microdev_micro_s2/sdkconfig index 67ac6d2f3..4b8cc5cc3 100644 --- a/ports/esp32s2/boards/microdev_micro_s2/sdkconfig +++ b/ports/esp32s2/boards/microdev_micro_s2/sdkconfig @@ -32,3 +32,8 @@ CONFIG_SPIRAM_MEMTEST=y # CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set # end of SPI RAM config +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="microS2" +# end of LWIP diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2/sdkconfig b/ports/esp32s2/boards/unexpectedmaker_feathers2/sdkconfig index 67ac6d2f3..c9d44460c 100644 --- a/ports/esp32s2/boards/unexpectedmaker_feathers2/sdkconfig +++ b/ports/esp32s2/boards/unexpectedmaker_feathers2/sdkconfig @@ -32,3 +32,8 @@ CONFIG_SPIRAM_MEMTEST=y # CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set # end of SPI RAM config +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="UMFeatherS2" +# end of LWIP diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h index 90a368006..93d901bec 100644 --- a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h +++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h @@ -26,7 +26,7 @@ //Micropython setup -#define MICROPY_HW_BOARD_NAME "FeatherS2" +#define MICROPY_HW_BOARD_NAME "FeatherS2 PreRelease" #define MICROPY_HW_MCU_NAME "ESP32S2" #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0) diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/sdkconfig b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/sdkconfig index b73c4a8c2..00e0bb256 100644 --- a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/sdkconfig +++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/sdkconfig @@ -33,3 +33,9 @@ CONFIG_SPIRAM_USE_MEMMAP=y CONFIG_SPIRAM_MEMTEST=y # CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set # end of SPI RAM config + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="UMFeatherS2" +# end of LWIP diff --git a/ports/esp32s2/common-hal/analogio/AnalogIn.c b/ports/esp32s2/common-hal/analogio/AnalogIn.c new file mode 100644 index 000000000..bab1721ea --- /dev/null +++ b/ports/esp32s2/common-hal/analogio/AnalogIn.c @@ -0,0 +1,98 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "common-hal/analogio/AnalogIn.h" +#include "py/mperrno.h" +#include "py/runtime.h" +#include "supervisor/shared/translate.h" + +#include "components/driver/include/driver/adc_common.h" +#include "components/esp_adc_cal/include/esp_adc_cal.h" + +#include "shared-bindings/microcontroller/Pin.h" + +#define DEFAULT_VREF 1100 +#define NO_OF_SAMPLES 64 +#define ATTENUATION ADC_ATTEN_DB_11 +#define DATA_WIDTH ADC_WIDTH_BIT_13 + +void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self, + const mcu_pin_obj_t *pin) { + if (pin->adc_index == 0 || pin->adc_channel == ADC_CHANNEL_MAX) { + mp_raise_ValueError(translate("Pin does not have ADC capabilities")); + } + common_hal_mcu_pin_claim(pin); + self->pin = pin; +} + +bool common_hal_analogio_analogin_deinited(analogio_analogin_obj_t *self) { + return self->pin == NULL; +} + +void common_hal_analogio_analogin_deinit(analogio_analogin_obj_t *self) { + if (common_hal_analogio_analogin_deinited(self)) { + return; + } + reset_pin_number(self->pin->number); + self->pin = NULL; +} + +uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { + if (self->pin->adc_index == ADC_UNIT_1) { + adc1_config_width(DATA_WIDTH); + adc1_config_channel_atten((adc1_channel_t)self->pin->adc_channel, ATTENUATION); + } else if (self->pin->adc_index == ADC_UNIT_2) { + adc2_config_channel_atten((adc2_channel_t)self->pin->adc_channel, ATTENUATION); + } + + // Automatically select calibration process depending on status of efuse + esp_adc_cal_characteristics_t *adc_chars = calloc(1, sizeof(esp_adc_cal_characteristics_t)); + esp_adc_cal_characterize(self->pin->adc_index, ATTENUATION, DATA_WIDTH, DEFAULT_VREF, adc_chars); + + uint32_t adc_reading = 0; + //Multisampling + for (int i = 0; i < NO_OF_SAMPLES; i++) { + if (self->pin->adc_index == ADC_UNIT_1) { + adc_reading += adc1_get_raw((adc1_channel_t)self->pin->adc_channel); + } else { + int raw; + esp_err_t r = adc2_get_raw((adc2_channel_t)self->pin->adc_channel, DATA_WIDTH, &raw); + if ( r != ESP_OK ) { + mp_raise_ValueError(translate("ADC2 is being used by WiFi")); + } + adc_reading += raw; + } + } + adc_reading /= NO_OF_SAMPLES; + + // This corrects non-linear regions of the ADC range with a LUT, so it's a better reading than raw + uint32_t voltage = esp_adc_cal_raw_to_voltage(adc_reading, adc_chars); + return voltage * ((1 << 16) - 1)/3300; +} + +float common_hal_analogio_analogin_get_reference_voltage(analogio_analogin_obj_t *self) { + return 3.3f; +} diff --git a/ports/esp32s2/common-hal/analogio/AnalogIn.h b/ports/esp32s2/common-hal/analogio/AnalogIn.h new file mode 100644 index 000000000..fed4d0217 --- /dev/null +++ b/ports/esp32s2/common-hal/analogio/AnalogIn.h @@ -0,0 +1,42 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_ESP32S2_COMMON_HAL_ANALOGIO_ANALOGIN_H +#define MICROPY_INCLUDED_ESP32S2_COMMON_HAL_ANALOGIO_ANALOGIN_H + +#include "common-hal/microcontroller/Pin.h" + +#include "components/hal/include/hal/adc_types.h" +#include "FreeRTOS.h" +#include "freertos/semphr.h" +#include "py/obj.h" + +typedef struct { + mp_obj_base_t base; + const mcu_pin_obj_t * pin; +} analogio_analogin_obj_t; + +#endif // MICROPY_INCLUDED_ESP32S2_COMMON_HAL_ANALOGIO_ANALOGIN_H diff --git a/ports/esp32s2/common-hal/analogio/AnalogOut.c b/ports/esp32s2/common-hal/analogio/AnalogOut.c new file mode 100644 index 000000000..080a01b04 --- /dev/null +++ b/ports/esp32s2/common-hal/analogio/AnalogOut.c @@ -0,0 +1,73 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * SPDX-FileCopyrightText: Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2019, Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdint.h> +#include <string.h> + +#include "py/mperrno.h" +#include "py/runtime.h" + +#include "shared-bindings/analogio/AnalogOut.h" +#include "shared-bindings/microcontroller/Pin.h" +#include "supervisor/shared/translate.h" + +#include "components/driver/include/driver/dac_common.h" + +#include "common-hal/microcontroller/Pin.h" + +void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, + const mcu_pin_obj_t *pin) { + if (pin == &pin_GPIO17) { + self->channel = DAC_CHANNEL_1; + } else if (pin == &pin_GPIO18) { + self->channel = DAC_CHANNEL_2; + } else { + mp_raise_ValueError(translate("Invalid DAC pin supplied")); + } + dac_output_enable(self->channel); +} + +bool common_hal_analogio_analogout_deinited(analogio_analogout_obj_t *self) { + return (self->channel == DAC_CHANNEL_MAX); +} + +void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) { + dac_output_disable(self->channel); + self->channel = DAC_CHANNEL_MAX; +} + +void common_hal_analogio_analogout_set_value(analogio_analogout_obj_t *self, + uint16_t value) { + uint8_t dac_value = (value * 255) / 65535; + dac_output_enable(self->channel); + dac_output_voltage(self->channel, dac_value); +} + +void analogout_reset(void) { + dac_output_disable(DAC_CHANNEL_1); + dac_output_disable(DAC_CHANNEL_2); +} diff --git a/ports/esp32s2/common-hal/analogio/AnalogOut.h b/ports/esp32s2/common-hal/analogio/AnalogOut.h new file mode 100644 index 000000000..6285151ba --- /dev/null +++ b/ports/esp32s2/common-hal/analogio/AnalogOut.h @@ -0,0 +1,43 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Scott Shawcroft + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_ESP32S2_COMMON_HAL_ANALOGIO_ANALOGOUT_H +#define MICROPY_INCLUDED_ESP32S2_COMMON_HAL_ANALOGIO_ANALOGOUT_H + +#include "common-hal/microcontroller/Pin.h" + +#include "py/obj.h" + +typedef struct { + mp_obj_base_t base; + const mcu_pin_obj_t * pin; + uint8_t channel; +} analogio_analogout_obj_t; + +void analogout_reset(void); + +#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_ANALOGIO_ANALOGOUT_H diff --git a/ports/esp32s2/common-hal/analogio/__init__.c b/ports/esp32s2/common-hal/analogio/__init__.c new file mode 100644 index 000000000..eea58c77d --- /dev/null +++ b/ports/esp32s2/common-hal/analogio/__init__.c @@ -0,0 +1 @@ +// No analogio module functions. diff --git a/ports/esp32s2/common-hal/busio/I2C.h b/ports/esp32s2/common-hal/busio/I2C.h index 1a989e30a..c39d6d744 100644 --- a/ports/esp32s2/common-hal/busio/I2C.h +++ b/ports/esp32s2/common-hal/busio/I2C.h @@ -29,7 +29,7 @@ #include "common-hal/microcontroller/Pin.h" -#include "components/soc/include/hal/i2c_types.h" +#include "components/hal/include/hal/i2c_types.h" #include "FreeRTOS.h" #include "freertos/semphr.h" #include "py/obj.h" diff --git a/ports/esp32s2/common-hal/busio/SPI.h b/ports/esp32s2/common-hal/busio/SPI.h index d6203feae..f6c1c344a 100644 --- a/ports/esp32s2/common-hal/busio/SPI.h +++ b/ports/esp32s2/common-hal/busio/SPI.h @@ -30,8 +30,8 @@ #include "common-hal/microcontroller/Pin.h" #include "components/driver/include/driver/spi_common_internal.h" -#include "components/soc/include/hal/spi_hal.h" -#include "components/soc/include/hal/spi_types.h" +#include "components/hal/include/hal/spi_hal.h" +#include "components/hal/include/hal/spi_types.h" #include "py/obj.h" typedef struct { diff --git a/ports/esp32s2/common-hal/busio/UART.h b/ports/esp32s2/common-hal/busio/UART.h index 751fb2e00..1d7f13511 100644 --- a/ports/esp32s2/common-hal/busio/UART.h +++ b/ports/esp32s2/common-hal/busio/UART.h @@ -29,7 +29,7 @@ #include "common-hal/microcontroller/Pin.h" -#include "components/soc/include/hal/uart_types.h" +#include "components/hal/include/hal/uart_types.h" #include "py/obj.h" typedef struct { diff --git a/ports/esp32s2/common-hal/digitalio/DigitalInOut.c b/ports/esp32s2/common-hal/digitalio/DigitalInOut.c index a2a0209f9..152db1e71 100644 --- a/ports/esp32s2/common-hal/digitalio/DigitalInOut.c +++ b/ports/esp32s2/common-hal/digitalio/DigitalInOut.c @@ -30,7 +30,7 @@ #include "components/driver/include/driver/gpio.h" -#include "components/soc/include/hal/gpio_hal.h" +#include "components/hal/include/hal/gpio_hal.h" void common_hal_digitalio_digitalinout_never_reset( digitalio_digitalinout_obj_t *self) { diff --git a/ports/esp32s2/common-hal/microcontroller/Pin.c b/ports/esp32s2/common-hal/microcontroller/Pin.c index 0f4669fe0..3c2611efe 100644 --- a/ports/esp32s2/common-hal/microcontroller/Pin.c +++ b/ports/esp32s2/common-hal/microcontroller/Pin.c @@ -32,7 +32,7 @@ #include "py/mphal.h" #include "components/driver/include/driver/gpio.h" -#include "components/soc/include/hal/gpio_hal.h" +#include "components/hal/include/hal/gpio_hal.h" #ifdef MICROPY_HW_NEOPIXEL bool neopixel_in_use; diff --git a/ports/esp32s2/common-hal/socketpool/Socket.h b/ports/esp32s2/common-hal/socketpool/Socket.h index de63c8ab2..62b5ded58 100644 --- a/ports/esp32s2/common-hal/socketpool/Socket.h +++ b/ports/esp32s2/common-hal/socketpool/Socket.h @@ -33,7 +33,6 @@ #include "common-hal/ssl/SSLContext.h" #include "components/esp-tls/esp_tls.h" -#include "components/log/include/esp_log.h" typedef struct { mp_obj_base_t base; diff --git a/ports/esp32s2/common-hal/wifi/Radio.c b/ports/esp32s2/common-hal/wifi/Radio.c index b62ad611b..5e349c09d 100644 --- a/ports/esp32s2/common-hal/wifi/Radio.c +++ b/ports/esp32s2/common-hal/wifi/Radio.c @@ -104,6 +104,19 @@ void common_hal_wifi_radio_stop_scanning_networks(wifi_radio_obj_t *self) { self->current_scan = NULL; } +mp_obj_t common_hal_wifi_radio_get_hostname(wifi_radio_obj_t *self) { + const char *hostname = NULL; + esp_netif_get_hostname(self->netif, &hostname); + if (hostname == NULL) { + return mp_const_none; + } + return mp_obj_new_str(hostname, strlen(hostname)); +} + +void common_hal_wifi_radio_set_hostname(wifi_radio_obj_t *self, const char *hostname) { + esp_netif_set_hostname(self->netif, hostname); +} + wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t* ssid, size_t ssid_len, uint8_t* password, size_t password_len, uint8_t channel, mp_float_t timeout, uint8_t* bssid, size_t bssid_len) { // check enabled start_station(self); diff --git a/ports/esp32s2/common-hal/wifi/ScannedNetworks.h b/ports/esp32s2/common-hal/wifi/ScannedNetworks.h index db0c2a148..36da387f2 100644 --- a/ports/esp32s2/common-hal/wifi/ScannedNetworks.h +++ b/ports/esp32s2/common-hal/wifi/ScannedNetworks.h @@ -36,7 +36,6 @@ #include "freertos/event_groups.h" #include "components/esp_wifi/include/esp_wifi_types.h" -#include "components/log/include/esp_log.h" typedef struct { mp_obj_base_t base; diff --git a/ports/esp32s2/esp-idf b/ports/esp32s2/esp-idf -Subproject a7f77798816661f7c4ae198f3878bc92a9274f8 +Subproject 8bc19ba893e5544d571a753d82b44a84799b94b diff --git a/ports/esp32s2/mpconfigport.h b/ports/esp32s2/mpconfigport.h index c06e63439..cec8dd35d 100644 --- a/ports/esp32s2/mpconfigport.h +++ b/ports/esp32s2/mpconfigport.h @@ -31,8 +31,8 @@ #define CIRCUITPY_INTERNAL_NVM_SIZE (0) #define MICROPY_NLR_THUMB (0) -#define MICROPY_PY_UJSON (1) -#define MICROPY_USE_INTERNAL_PRINTF (0) +#define MICROPY_PY_UJSON (1) +#define MICROPY_USE_INTERNAL_PRINTF (0) #include "py/circuitpy_mpconfig.h" diff --git a/ports/esp32s2/mpconfigport.mk b/ports/esp32s2/mpconfigport.mk index bbaabb1c3..4e8a7bdef 100644 --- a/ports/esp32s2/mpconfigport.mk +++ b/ports/esp32s2/mpconfigport.mk @@ -14,7 +14,6 @@ LONGINT_IMPL = MPZ # These modules are implemented in ports/<port>/common-hal: CIRCUITPY_FULL_BUILD = 1 -CIRCUITPY_ANALOGIO = 0 CIRCUITPY_AUDIOBUSIO = 0 CIRCUITPY_AUDIOIO = 0 CIRCUITPY_COUNTIO = 0 diff --git a/ports/esp32s2/peripherals/pins.c b/ports/esp32s2/peripherals/pins.c index 34fd6483e..2c8b61c62 100755 --- a/ports/esp32s2/peripherals/pins.c +++ b/ports/esp32s2/peripherals/pins.c @@ -26,56 +26,58 @@ #include "peripherals/pins.h" -#define NO_ADC 0xff +#define NO_ADC 0 +#define NO_ADC_CHANNEL ADC_CHANNEL_MAX // This macro is used to simplify pin definition in boards/<board>/pins.c -#define PIN(p_name, p_number) \ +#define PIN(p_name, p_number, p_adc_index, p_adc_channel) \ const mcu_pin_obj_t pin_## p_name = { \ PIN_PREFIX_VALUES \ .number = p_number, \ + .adc_index = p_adc_index, \ + .adc_channel = p_adc_channel, \ } -PIN(GPIO0, 0); -PIN(GPIO1, 1); -PIN(GPIO2, 2); -PIN(GPIO3, 3); -PIN(GPIO4, 4); -PIN(GPIO5, 5); -PIN(GPIO6, 6); -PIN(GPIO7, 7); -PIN(GPIO8, 8); -PIN(GPIO9, 9); -PIN(GPIO10, 10); -PIN(GPIO11, 11); -PIN(GPIO12, 12); -PIN(GPIO13, 13); -PIN(GPIO14, 14); -PIN(GPIO15, 15); -PIN(GPIO16, 16); -PIN(GPIO17, 17); -PIN(GPIO18, 18); - -PIN(GPIO19, 19); -PIN(GPIO20, 20); -PIN(GPIO21, 21); -PIN(GPIO26, 26); -PIN(GPIO27, 27); -PIN(GPIO28, 28); -PIN(GPIO29, 29); -PIN(GPIO30, 30); -PIN(GPIO31, 31); -PIN(GPIO32, 32); -PIN(GPIO33, 33); -PIN(GPIO34, 34); -PIN(GPIO35, 35); -PIN(GPIO36, 36); -PIN(GPIO37, 37); -PIN(GPIO38, 38); -PIN(GPIO39, 39); -PIN(GPIO40, 40); -PIN(GPIO41, 41); -PIN(GPIO42, 42); -PIN(GPIO43, 43); -PIN(GPIO44, 44); -PIN(GPIO45, 45); -PIN(GPIO46, 46); +PIN(GPIO0, 0, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO1, 1, ADC_UNIT_1, ADC_CHANNEL_0); +PIN(GPIO2, 2, ADC_UNIT_1, ADC_CHANNEL_1); +PIN(GPIO3, 3, ADC_UNIT_1, ADC_CHANNEL_2); +PIN(GPIO4, 4, ADC_UNIT_1, ADC_CHANNEL_3); +PIN(GPIO5, 5, ADC_UNIT_1, ADC_CHANNEL_4); +PIN(GPIO6, 6, ADC_UNIT_1, ADC_CHANNEL_5); +PIN(GPIO7, 7, ADC_UNIT_1, ADC_CHANNEL_6); +PIN(GPIO8, 8, ADC_UNIT_1, ADC_CHANNEL_7); +PIN(GPIO9, 9, ADC_UNIT_1, ADC_CHANNEL_8); +PIN(GPIO10, 10, ADC_UNIT_1, ADC_CHANNEL_9); +PIN(GPIO11, 11, ADC_UNIT_2, ADC_CHANNEL_0); +PIN(GPIO12, 12, ADC_UNIT_2, ADC_CHANNEL_1); +PIN(GPIO13, 13, ADC_UNIT_2, ADC_CHANNEL_2); +PIN(GPIO14, 14, ADC_UNIT_2, ADC_CHANNEL_3); +PIN(GPIO15, 15, ADC_UNIT_2, ADC_CHANNEL_4); +PIN(GPIO16, 16, ADC_UNIT_2, ADC_CHANNEL_5); +PIN(GPIO17, 17, ADC_UNIT_2, ADC_CHANNEL_6); +PIN(GPIO18, 18, ADC_UNIT_2, ADC_CHANNEL_7); +PIN(GPIO19, 19, ADC_UNIT_2, ADC_CHANNEL_8); +PIN(GPIO20, 20, ADC_UNIT_2, ADC_CHANNEL_9); +PIN(GPIO21, 21, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO26, 26, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO27, 27, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO28, 28, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO29, 29, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO30, 30, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO31, 31, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO32, 32, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO33, 33, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO34, 34, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO35, 35, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO36, 36, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO37, 37, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO38, 38, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO39, 39, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO40, 40, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO41, 41, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO42, 42, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO43, 43, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO44, 44, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO45, 45, NO_ADC, NO_ADC_CHANNEL); +PIN(GPIO46, 46, NO_ADC, NO_ADC_CHANNEL); diff --git a/ports/esp32s2/peripherals/pins.h b/ports/esp32s2/peripherals/pins.h index 0cf63a029..84123a80e 100644 --- a/ports/esp32s2/peripherals/pins.h +++ b/ports/esp32s2/peripherals/pins.h @@ -34,11 +34,15 @@ #include "esp32s2_peripherals_config.h" #include "esp-idf/config/sdkconfig.h" -#include "components/soc/include/hal/gpio_types.h" + +#include "components/hal/include/hal/gpio_types.h" +#include "components/hal/include/hal/adc_types.h" typedef struct { PIN_PREFIX_FIELDS gpio_num_t number; + uint8_t adc_index:2; + uint8_t adc_channel:6; } mcu_pin_obj_t; extern const mcu_pin_obj_t pin_GPIO0; diff --git a/ports/esp32s2/supervisor/port.c b/ports/esp32s2/supervisor/port.c index 4290b9bb4..0b9c03f74 100644 --- a/ports/esp32s2/supervisor/port.c +++ b/ports/esp32s2/supervisor/port.c @@ -35,6 +35,7 @@ #include "freertos/task.h" #include "common-hal/microcontroller/Pin.h" +#include "common-hal/analogio/AnalogOut.h" #include "common-hal/busio/I2C.h" #include "common-hal/busio/SPI.h" #include "common-hal/busio/UART.h" @@ -95,6 +96,10 @@ void reset_port(void) { // A larger delay so the idle task can run and do any IDF cleanup needed. vTaskDelay(4); +#if CIRCUITPY_ANALOGIO + analogout_reset(); +#endif + #if CIRCUITPY_PULSEIO esp32s2_peripherals_rmt_reset(); pulsein_reset(); diff --git a/ports/esp32s2/supervisor/usb.c b/ports/esp32s2/supervisor/usb.c index c91c2ec4b..1ad6af047 100644 --- a/ports/esp32s2/supervisor/usb.c +++ b/ports/esp32s2/supervisor/usb.c @@ -33,6 +33,8 @@ #include "components/driver/include/driver/periph_ctrl.h" #include "components/driver/include/driver/gpio.h" #include "components/esp_rom/include/esp32s2/rom/gpio.h" +#include "components/esp_rom/include/esp_rom_gpio.h" +#include "components/hal/esp32s2/include/hal/gpio_ll.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -68,6 +70,33 @@ void usb_device_task(void* param) } } +static void configure_pins (usb_hal_context_t *usb) +{ + /* usb_periph_iopins currently configures USB_OTG as USB Device. + * Introduce additional parameters in usb_hal_context_t when adding support + * for USB Host. + */ + for ( const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin ) { + if ( (usb->use_external_phy) || (iopin->ext_phy_only == 0) ) { + esp_rom_gpio_pad_select_gpio(iopin->pin); + if ( iopin->is_output ) { + esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false); + } + else { + esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false); + if ( (iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH) ) { + gpio_ll_input_enable(&GPIO, iopin->pin); + } + } + esp_rom_gpio_pad_unhold(iopin->pin); + } + } + if ( !usb->use_external_phy ) { + gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3); + gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); + } +} + void init_usb_hardware(void) { periph_module_reset(PERIPH_USB_MODULE); periph_module_enable(PERIPH_USB_MODULE); @@ -75,10 +104,7 @@ void init_usb_hardware(void) { .use_external_phy = false // use built-in PHY }; usb_hal_init(&hal); - - // Initialize the pin drive strength. - gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3); - gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); + configure_pins(&hal); (void) xTaskCreateStatic(usb_device_task, "usbd", diff --git a/ports/litex/mpconfigport.mk b/ports/litex/mpconfigport.mk index 427e9ea84..485a75fde 100644 --- a/ports/litex/mpconfigport.mk +++ b/ports/litex/mpconfigport.mk @@ -16,6 +16,7 @@ CIRCUITPY_ANALOGIO = 0 CIRCUITPY_AUDIOBUSIO = 0 CIRCUITPY_AUDIOIO = 0 CIRCUITPY_BITBANGIO = 0 +CIRCUITPY_BLEIO_HCI = 0 CIRCUITPY_BOARD = 0 CIRCUITPY_BUSIO = 0 CIRCUITPY_COUNTIO = 0 diff --git a/ports/litex/supervisor/port.c b/ports/litex/supervisor/port.c index e55eb49f0..02617b9af 100644 --- a/ports/litex/supervisor/port.c +++ b/ports/litex/supervisor/port.c @@ -128,7 +128,11 @@ uint32_t port_get_saved_word(void) { } uint64_t port_get_raw_ticks(uint8_t* subticks) { - return raw_ticks; + // Reading 64 bits may take two loads, so turn of interrupts while we do it. + irq_setie(false); + uint64_t raw_tick_snapshot = raw_ticks; + irq_setie(true); + return raw_tick_snapshot; } // Enable 1/1024 second tick. diff --git a/ports/mimxrt10xx/Makefile b/ports/mimxrt10xx/Makefile index 248798f63..a17e5f703 100644 --- a/ports/mimxrt10xx/Makefile +++ b/ports/mimxrt10xx/Makefile @@ -75,7 +75,7 @@ INC += \ # NDEBUG disables assert() statements. This reduces code size pretty dramatically, per tannewt. -CFLAGS += -Os -DNDEBUG +CFLAGS += -Os -DNDEBUG -ffreestanding # TinyUSB defines CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX -DCFG_TUD_MIDI_RX_BUFSIZE=512 -DCFG_TUD_CDC_RX_BUFSIZE=512 -DCFG_TUD_MIDI_TX_BUFSIZE=512 -DCFG_TUD_CDC_TX_BUFSIZE=512 -DCFG_TUD_MSC_BUFSIZE=1024 @@ -147,7 +147,7 @@ SRC_SDK := \ SRC_SDK := $(addprefix sdk/devices/$(CHIP_FAMILY)/, $(SRC_SDK)) -SRC_C = \ +SRC_C += \ background.c \ boards/$(BOARD)/board.c \ boards/$(BOARD)/flash_config.c \ diff --git a/ports/mimxrt10xx/boards/board.h b/ports/mimxrt10xx/boards/board.h index 92d02d900..678c223ae 100644 --- a/ports/mimxrt10xx/boards/board.h +++ b/ports/mimxrt10xx/boards/board.h @@ -33,6 +33,7 @@ #include "py/mpconfig.h" #include "fsl_common.h" +#include "fsl_flexspi_nor_config.h" // Initializes board related state once on start up. void board_init(void); @@ -45,4 +46,11 @@ bool board_requests_safe_mode(void); // Reset the state of off MCU components such as neopixels. void reset_board(void); +#define SEQUENCE(first, second, third, fourth) first, second, third, fourth +#define TWO_EMPTY_STEPS 0x00000000 +#define EMPTY_SEQUENCE SEQUENCE(TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS) + +// FlexSPI configuration that stores command info. +extern const flexspi_nor_config_t qspiflash_config; + #endif // MICROPY_INCLUDED_MIMXRT10XX_BOARDS_BOARD_H diff --git a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c index b74c0b151..282464c75 100644 --- a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c @@ -6,7 +6,7 @@ */ #include "fsl_flexspi_nor_boot.h" -#include "fsl_flexspi_nor_config.h" +#include "boards/board.h" __attribute__((section(".boot_hdr.ivt"))) @@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = { 0xFFFFFFFF /* empty - extra data word */ }; +// Config for W25Q32JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 1u, - .csSetupTime = 2u, - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, // Bit pattern for setting Quad Enable. .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 + .serialClkFreq = kFlexSpiSerialClk_133MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - 0, - 0, - - 0x24040405, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000406, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x08180420, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x081804D8, - 0, - 0, - 0, - - 0x08180402, - 0x00002004, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000460, + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status -2 + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01 /* number of bytes to write */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, }; diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c index b74c0b151..51cc0f164 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c @@ -6,7 +6,7 @@ */ #include "fsl_flexspi_nor_boot.h" -#include "fsl_flexspi_nor_config.h" +#include "boards/board.h" __attribute__((section(".boot_hdr.ivt"))) @@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = { 0xFFFFFFFF /* empty - extra data word */ }; +// Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 1u, - .csSetupTime = 2u, - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 + .serialClkFreq = kFlexSpiSerialClk_133MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - 0, - 0, - - 0x24040405, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000406, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x08180420, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x081804D8, - 0, - 0, - 0, - - 0x08180402, - 0x00002004, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000460, + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, }; diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c index b74c0b151..51cc0f164 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c @@ -6,7 +6,7 @@ */ #include "fsl_flexspi_nor_boot.h" -#include "fsl_flexspi_nor_config.h" +#include "boards/board.h" __attribute__((section(".boot_hdr.ivt"))) @@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = { 0xFFFFFFFF /* empty - extra data word */ }; +// Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 1u, - .csSetupTime = 2u, - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 + .serialClkFreq = kFlexSpiSerialClk_133MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - 0, - 0, - - 0x24040405, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000406, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x08180420, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x081804D8, - 0, - 0, - 0, - - 0x08180402, - 0x00002004, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000460, + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, }; diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c index 7e8fb75b2..19573bd99 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c @@ -6,7 +6,8 @@ */ #include "fsl_flexspi_nor_boot.h" -#include "fsl_flexspi_nor_config.h" +#include "boards/board.h" + __attribute__((section(".boot_hdr.ivt"))) /************************************* @@ -34,88 +35,135 @@ const BOOT_DATA_T boot_data = { 0xFFFFFFFF /* empty - extra data word */ }; +// Config for AT25SF128A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 1u, - .csSetupTime = 2u, - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 + .serialClkFreq = kFlexSpiSerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - 0, - 0, - - 0x24040405, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000406, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x08180420, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x081804D8, - 0, - 0, - 0, - - 0x08180402, - 0x00002004, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000460, + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, }; diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c index 43ffe0dd1..40b566618 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c @@ -6,7 +6,7 @@ */ #include "fsl_flexspi_nor_boot.h" -#include "fsl_flexspi_nor_config.h" +#include "boards/board.h" __attribute__((section(".boot_hdr.ivt"))) @@ -35,92 +35,135 @@ const BOOT_DATA_T boot_data = { 0xFFFFFFFF /* empty - extra data word */ }; +// Config for IS25LP064A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, -#ifdef BOARD_USING_SECONDARY_QSPI_PINMUX - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromInternally, -#else .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, -#endif - .csHoldTime = 1u, - .csSetupTime = 2u, - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x40, .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 + .serialClkFreq = kFlexSpiSerialClk_30MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - 0, - 0, - - 0x24040405, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000406, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x08180420, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x081804D8, - 0, - 0, - 0, - - 0x08180402, - 0x00002004, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000460, + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + // RADDR_SDR, FLEXSPI_4PAD, 24 bits to transmit ), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + // READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, }; diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c index 7e046d494..d79a8d0f9 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c @@ -6,10 +6,10 @@ */ #include "fsl_flexspi_nor_boot.h" -#include "fsl_flexspi_nor_config.h" +#include "boards/board.h" -__attribute__((section(".boot_hdr.ivt"))) +__attribute__((section(".boot_hdr.ivt"))) /************************************* * IVT Data *************************************/ @@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = { 0xFFFFFFFF /* empty - extra data word */ }; +// Config for IS25WP064A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 1u, - .csSetupTime = 2u, - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x40, .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 + .serialClkFreq = kFlexSpiSerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - 0, - 0, - - 0x24040405, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000406, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x08180420, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x081804D8, - 0, - 0, - 0, - - 0x08180402, - 0x00002004, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000460, + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, }; diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board.c b/ports/mimxrt10xx/boards/metro_m7_1011/board.c new file mode 100644 index 000000000..ed543e1b0 --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board.c @@ -0,0 +1,52 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2019 Artur Pacholec + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "mpconfigboard.h" +#include "shared-bindings/microcontroller/Pin.h" + +void board_init(void) { + // SWD Pins + common_hal_never_reset_pin(&pin_GPIO_AD_13);//SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12);//SWCLK + + // FLEX flash + common_hal_never_reset_pin(&pin_GPIO_SD_12); + common_hal_never_reset_pin(&pin_GPIO_SD_11); + common_hal_never_reset_pin(&pin_GPIO_SD_10); + common_hal_never_reset_pin(&pin_GPIO_SD_09); + common_hal_never_reset_pin(&pin_GPIO_SD_08); + common_hal_never_reset_pin(&pin_GPIO_SD_07); + common_hal_never_reset_pin(&pin_GPIO_SD_06); +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c new file mode 100644 index 000000000..30ce67523 --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c @@ -0,0 +1,179 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi_nor_boot.h" +#include "boards/board.h" + + +__attribute__((section(".boot_hdr.ivt"))) +/************************************* + * IVT Data + *************************************/ +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +__attribute__((section(".boot_hdr.boot_data"))) +/************************************* + * Boot Data + *************************************/ +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +// Config for W25Q16JV with QSPI routed. +__attribute__((section(".boot_hdr.conf"))) +const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { + .seqId = 2u, + .seqNum = 1u, + }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + { + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, + DUMMY_SDR, FLEXSPI_1PAD, 8), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE + }, + }, +}; diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.h b/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.h new file mode 100644 index 000000000..b11edb18b --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.h @@ -0,0 +1,20 @@ +#define MICROPY_HW_BOARD_NAME "Metro MIMXRT1011" +#define MICROPY_HW_MCU_NAME "IMXRT1011DAE5A" + +#define MICROPY_HW_NEOPIXEL (&pin_GPIO_00) + +// If you change this, then make sure to update the linker scripts as well to +// make sure you don't overwrite code +#define CIRCUITPY_INTERNAL_NVM_SIZE 0 + +#define BOARD_FLASH_SIZE (2 * 1024 * 1024) + +#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_02) +#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_01) + +#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_AD_06) +#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_AD_04) +#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_AD_03) + +#define DEFAULT_UART_BUS_RX (&pin_GPIO_09) +#define DEFAULT_UART_BUS_TX (&pin_GPIO_10) diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.mk b/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.mk new file mode 100644 index 000000000..1a3f7e766 --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.mk @@ -0,0 +1,12 @@ +USB_VID = 0x239A +USB_PID = 0x80E2 +USB_PRODUCT = "Metro M7 1011" +USB_MANUFACTURER = "Adafruit" + +CHIP_VARIANT = MIMXRT1011DAE5A +CHIP_FAMILY = MIMXRT1011 +FLASH = W25Q16JV + +# Include these Python libraries in the firmware +FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_ESP32SPI +FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Requests diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/pins.c b/ports/mimxrt10xx/boards/metro_m7_1011/pins.c new file mode 100644 index 000000000..e88493413 --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011/pins.c @@ -0,0 +1,59 @@ +#include "shared-bindings/board/__init__.h" + +#include "boards/board.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + // Analog + { MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_00) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_05) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_10) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_08) }, + + // Digital + { MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_09) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_10) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_13) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_12) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_SD_00) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_SD_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_SD_02) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_11) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_08) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_07) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_06) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_05) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_04) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D13),MP_ROM_PTR(&pin_GPIO_03) }, + + // ESP control + { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_CS), MP_ROM_PTR(&pin_GPIO_AD_14) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_GPIO0), MP_ROM_PTR(&pin_GPIO_SD_05) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_BUSY), MP_ROM_PTR(&pin_GPIO_AD_11) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RESET), MP_ROM_PTR(&pin_GPIO_AD_07) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_GPIO_09) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_GPIO_10) }, + + // SPI + { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO_AD_06) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO_AD_03) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO_AD_04) }, + + // UART + { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) }, + + // I2C + { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_01) }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_02) }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO_00) }, + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/mimxrt10xx/boards/teensy40/flash_config.c b/ports/mimxrt10xx/boards/teensy40/flash_config.c index 426deb884..30ce67523 100644 --- a/ports/mimxrt10xx/boards/teensy40/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy40/flash_config.c @@ -6,12 +6,8 @@ */ #include "fsl_flexspi_nor_boot.h" -#include "fsl_flexspi_nor_config.h" +#include "boards/board.h" -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_device" -#endif __attribute__((section(".boot_hdr.ivt"))) /************************************* @@ -39,88 +35,145 @@ const BOOT_DATA_T boot_data = { 0xFFFFFFFF /* empty - extra data word */ }; +// Config for W25Q16JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 1u, - .csSetupTime = 2u, - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { + .seqId = 2u, + .seqNum = 1u, + }, .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 + .serialClkFreq = kFlexSpiSerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - 0, - 0, - - 0x24040405, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000406, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x08180420, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x081804D8, - 0, - 0, - 0, - - 0x08180402, - 0x00002004, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000460, + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, + DUMMY_SDR, FLEXSPI_1PAD, 8), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, }; diff --git a/ports/mimxrt10xx/boards/teensy41/flash_config.c b/ports/mimxrt10xx/boards/teensy41/flash_config.c index 426deb884..7b2bfb768 100644 --- a/ports/mimxrt10xx/boards/teensy41/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy41/flash_config.c @@ -6,12 +6,8 @@ */ #include "fsl_flexspi_nor_boot.h" -#include "fsl_flexspi_nor_config.h" +#include "boards/board.h" -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_device" -#endif __attribute__((section(".boot_hdr.ivt"))) /************************************* @@ -39,88 +35,135 @@ const BOOT_DATA_T boot_data = { 0xFFFFFFFF /* empty - extra data word */ }; +// Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 const flexspi_nor_config_t qspiflash_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 1u, - .csSetupTime = 2u, - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, .deviceType = kFlexSpiDeviceType_SerialNOR, .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 + .serialClkFreq = kFlexSpiSerialClk_60MHz, .sflashA1Size = FLASH_SIZE, .lookupTable = { // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - 0, - 0, - - 0x24040405, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000406, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x08180420, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x081804D8, - 0, - 0, - 0, - - 0x08180402, - 0x00002004, - 0, - 0, - - 0, - 0, - 0, - 0, - - 0x00000460, + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, }; diff --git a/ports/mimxrt10xx/linking/common.ld b/ports/mimxrt10xx/linking/common.ld index 90fc78093..720361aa0 100644 --- a/ports/mimxrt10xx/linking/common.ld +++ b/ports/mimxrt10xx/linking/common.ld @@ -62,7 +62,6 @@ SECTIONS KEEP(*(.isr_vector)) /* Startup code */ *(EXCLUDE_FILE( - *flexspi_nor_flash_ops.o *fsl_flexspi.o ) .text*) /* .text* sections (code) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ @@ -84,7 +83,6 @@ SECTIONS { . = ALIGN(4); *(.data*) /* .data* sections */ - *flexspi_nor_flash_ops.o(.text*) *fsl_flexspi.o(.text*) . = ALIGN(4); } > OCRAM AT> FLASH_FIRMWARE @@ -110,7 +108,6 @@ SECTIONS .itcm : { . = ALIGN(4); - *(.itcm.*) . = ALIGN(4); diff --git a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c index 28d5115ac..353ba3176 100644 --- a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c +++ b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c @@ -9,23 +9,10 @@ #include "fsl_flexspi.h" #include "internal_flash.h" +#include "boards/board.h" +#include "supervisor/linker.h" -#define FLASH_QUAD_ENABLE 0x02 -#define FLASH_BUSY_STATUS_POL 1 -#define FLASH_BUSY_STATUS_OFFSET 0 - -static inline void flexspi_clock_init(void) -{ - /* Switch to PLL2 for XIP to avoid hardfault during re-initialize clock. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Set PLL2 PFD2 clock 396MHZ. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0x2); /* Choose PLL2 PFD2 clock as flexspi source clock. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 133M. */ -} - -extern flexspi_device_config_t deviceconfig; -extern const uint32_t customLUT[CUSTOM_LUT_LENGTH]; - -status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) +status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type *base, uint32_t baseAddr) { flexspi_transfer_t flashXfer; status_t status; @@ -35,14 +22,14 @@ status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) flashXfer.port = kFLEXSPI_PortA1; flashXfer.cmdType = kFLEXSPI_Command; flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; status = FLEXSPI_TransferBlocking(base, &flashXfer); return status; } -status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) +status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type *base) { /* Wait status ready. */ bool isBusy; @@ -54,7 +41,7 @@ status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) flashXfer.port = kFLEXSPI_PortA1; flashXfer.cmdType = kFLEXSPI_Read; flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + flashXfer.seqIndex = ROM_INDEX_READSTATUSREG; flashXfer.data = &readValue; flashXfer.dataSize = 1; @@ -66,72 +53,15 @@ status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) { return status; } - if (FLASH_BUSY_STATUS_POL) - { - if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) - { - isBusy = true; - } - else - { - isBusy = false; - } - } - else - { - if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) - { - isBusy = false; - } - else - { - isBusy = true; - } - } - + size_t busyBit = readValue & (1U << qspiflash_config.memConfig.busyOffset); + isBusy = (qspiflash_config.memConfig.busyBitPolarity == 0 && busyBit != 0) || + (qspiflash_config.memConfig.busyBitPolarity == 1 && busyBit == 0); } while (isBusy); return status; } -status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base) -{ - flexspi_transfer_t flashXfer; - status_t status; - uint32_t writeValue = FLASH_QUAD_ENABLE; - - /* Write enable */ - status = flexspi_nor_write_enable(base, 0); - - if (status != kStatus_Success) - { - return status; - } - - /* Enable quad mode. */ - flashXfer.deviceAddress = 0; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG; - flashXfer.data = &writeValue; - flashXfer.dataSize = 1; - - status = FLEXSPI_TransferBlocking(base, &flashXfer); - if (status != kStatus_Success) - { - return status; - } - - status = flexspi_nor_wait_bus_busy(base); - - /* Do software reset. */ - FLEXSPI_SoftwareReset(base); - - return status; -} - -status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) +status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type *base, uint32_t address) { status_t status; flexspi_transfer_t flashXfer; @@ -141,7 +71,7 @@ status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) flashXfer.port = kFLEXSPI_PortA1; flashXfer.cmdType = kFLEXSPI_Command; flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; status = FLEXSPI_TransferBlocking(base, &flashXfer); @@ -154,7 +84,7 @@ status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) flashXfer.port = kFLEXSPI_PortA1; flashXfer.cmdType = kFLEXSPI_Command; flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + flashXfer.seqIndex = ROM_INDEX_ERASESECTOR; status = FLEXSPI_TransferBlocking(base, &flashXfer); if (status != kStatus_Success) @@ -170,7 +100,7 @@ status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) return status; } -status_t flexspi_nor_flash_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src, uint32_t length) +status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src) { status_t status; flexspi_transfer_t flashXfer; @@ -188,48 +118,7 @@ status_t flexspi_nor_flash_program(FLEXSPI_Type *base, uint32_t dstAddr, const u flashXfer.port = kFLEXSPI_PortA1; flashXfer.cmdType = kFLEXSPI_Write; flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; - flashXfer.data = (uint32_t *)src; - flashXfer.dataSize = length; - status = FLEXSPI_TransferBlocking(base, &flashXfer); - - if (status != kStatus_Success) - { - return status; - } - - status = flexspi_nor_wait_bus_busy(base); - - /* Do software reset. */ -#if defined(FSL_FEATURE_SOC_OTFAD_COUNT) - base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK; - base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK); -#else - FLEXSPI_SoftwareReset(base); -#endif - - return status; -} - -status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src) -{ - status_t status; - flexspi_transfer_t flashXfer; - - /* Write enable */ - status = flexspi_nor_write_enable(base, dstAddr); - - if (status != kStatus_Success) - { - return status; - } - - /* Prepare page program command */ - flashXfer.deviceAddress = dstAddr; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; + flashXfer.seqIndex = ROM_INDEX_PAGEPROGRAM; flashXfer.data = (uint32_t *)src; flashXfer.dataSize = FLASH_PAGE_SIZE; status = FLEXSPI_TransferBlocking(base, &flashXfer); @@ -251,92 +140,3 @@ status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, co return status; } - -status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId) -{ - uint32_t temp; - flexspi_transfer_t flashXfer; - flashXfer.deviceAddress = 0; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Read; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID; - flashXfer.data = &temp; - flashXfer.dataSize = 1; - - status_t status = FLEXSPI_TransferBlocking(base, &flashXfer); - - *vendorId = temp; - - /* Do software reset. */ -#if defined(FSL_FEATURE_SOC_OTFAD_COUNT) - base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK; - base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK); -#else - FLEXSPI_SoftwareReset(base); -#endif - - return status; -} - -status_t flexspi_nor_erase_chip(FLEXSPI_Type *base) -{ - status_t status; - flexspi_transfer_t flashXfer; - - /* Write enable */ - status = flexspi_nor_write_enable(base, 0); - - if (status != kStatus_Success) - { - return status; - } - - flashXfer.deviceAddress = 0; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASECHIP; - - status = FLEXSPI_TransferBlocking(base, &flashXfer); - - if (status != kStatus_Success) - { - return status; - } - - status = flexspi_nor_wait_bus_busy(base); - - return status; -} - -void flexspi_nor_flash_init(FLEXSPI_Type *base) -{ - flexspi_config_t config; - - flexspi_clock_init(); - - /*Get FLEXSPI default settings and configure the flexspi. */ - FLEXSPI_GetDefaultConfig(&config); - - /*Set AHB buffer size for reading data through AHB bus. */ - config.ahbConfig.enableAHBPrefetch = true; - config.ahbConfig.enableAHBBufferable = true; - config.ahbConfig.enableReadAddressOpt = true; - config.ahbConfig.enableAHBCachable = true; -#ifdef BOARD_USING_SECONDARY_QSPI_PINMUX - config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; -#else - config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad; -#endif - FLEXSPI_Init(base, &config); - - /* Configure flash settings according to serial flash feature. */ - FLEXSPI_SetFlashConfig(base, &deviceconfig, kFLEXSPI_PortA1); - - /* Update LUT table. */ - FLEXSPI_UpdateLUT(base, 0, customLUT, CUSTOM_LUT_LENGTH); - - /* Do software reset. */ - FLEXSPI_SoftwareReset(base); -} diff --git a/ports/mimxrt10xx/supervisor/internal_flash.c b/ports/mimxrt10xx/supervisor/internal_flash.c index 09f44cced..e194cbed9 100644 --- a/ports/mimxrt10xx/supervisor/internal_flash.c +++ b/ports/mimxrt10xx/supervisor/internal_flash.c @@ -30,6 +30,7 @@ #include <string.h> #include <stdio.h> +#include "boards/board.h" #include "extmod/vfs.h" #include "extmod/vfs_fat.h" #include "py/mphal.h" @@ -50,125 +51,14 @@ extern uint32_t __fatfs_flash_length[]; uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4))); uint32_t _flash_page_addr = NO_CACHE; -static bool init_done = false; - -flexspi_device_config_t deviceconfig = { - .flexspiRootClk = 133000000, - .flashSize = (BOARD_FLASH_SIZE / 1024), - .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, - .CSInterval = 2, - .CSHoldTime = 3, - .CSSetupTime = 3, - .dataValidTime = 0, - .columnspace = 0, - .enableWordAddress = 0, - .AWRSeqIndex = 0, - .AWRSeqNumber = 0, - .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD, - .ARDSeqNumber = 1, - .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, - .AHBWriteWaitInterval = 0, -}; - -const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { - /* Normal read mode -SDR */ - /* Normal read mode -SDR */ - [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Fast read mode - SDR */ - [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), - - /* Fast read quad mode - SDR */ - [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), - - /* Read extend parameters */ - [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), - - /* Write Enable */ - [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Erase Sector */ - [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - - /* Page Program - single mode */ - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Page Program - quad mode */ - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Read ID */ - [4 * NOR_CMD_LUT_SEQ_IDX_READID] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), - - /* Enable Quad mode */ - [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x31, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04), - - /* Read status register */ - [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), - - /* Erase whole chip */ - [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), -}; extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src); -extern status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId); extern status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base); -extern status_t flexspi_nor_erase_chip(FLEXSPI_Type *base); -extern void flexspi_nor_flash_init(FLEXSPI_Type *base); - -void supervisor_flash_init(void) { - if (init_done) - return; - - SCB_DisableDCache(); - - status_t status; - uint8_t vendorID = 0; - - flexspi_nor_flash_init(FLEXSPI); - - /* Get vendor ID. */ - status = flexspi_nor_get_vendor_id(FLEXSPI, &vendorID); - if (status != kStatus_Success) { - printf("flexspi_nor_get_vendor_id fail %ld\r\n", status); - return; - } - - /* Enter quad mode. */ - __disable_irq(); - status = flexspi_nor_enable_quad_mode(FLEXSPI); - if (status != kStatus_Success) - { - printf("flexspi_nor_enable_quad_mode fail %ld\r\n", status); - return; - } - __enable_irq(); - - SCB_EnableDCache(); - init_done = true; +void PLACE_IN_ITCM(supervisor_flash_init)(void) { + // Update the LUT to make sure all entries are available. + FLEXSPI_UpdateLUT(FLEXSPI, 0, (const uint32_t*) &qspiflash_config.memConfig.lookupTable, 64); } static inline uint32_t lba2addr(uint32_t block) { @@ -183,7 +73,7 @@ uint32_t supervisor_flash_get_block_count(void) { return CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE; } -void port_internal_flash_flush(void) { +void PLACE_IN_ITCM(port_internal_flash_flush)(void) { if (_flash_page_addr == NO_CACHE) return; status_t status; @@ -211,6 +101,7 @@ void port_internal_flash_flush(void) { DCACHE_CleanInvalidateByRange(_flash_page_addr, SECTOR_SIZE); } + _flash_page_addr = NO_CACHE; } mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) { diff --git a/ports/mimxrt10xx/supervisor/internal_flash.h b/ports/mimxrt10xx/supervisor/internal_flash.h index daee66620..ae33fd134 100644 --- a/ports/mimxrt10xx/supervisor/internal_flash.h +++ b/ports/mimxrt10xx/supervisor/internal_flash.h @@ -34,20 +34,11 @@ #define INTERNAL_FLASH_SYSTICK_MASK (0x1ff) // 512ms #define INTERNAL_FLASH_IDLE_TICK(tick) (((tick) & INTERNAL_FLASH_SYSTICK_MASK) == 2) -#define CUSTOM_LUT_LENGTH 60 #define FLASH_PAGE_SIZE 256 -#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7 -#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13 -#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0 -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1 -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2 -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3 -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6 -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4 -#define NOR_CMD_LUT_SEQ_IDX_READID 8 -#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9 -#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12 -#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5 +#define ROM_INDEX_WRITEENABLE 3 +#define ROM_INDEX_ERASESECTOR 5 +#define ROM_INDEX_PAGEPROGRAM 9 +#define ROM_INDEX_READSTATUSREG 1 #endif // MICROPY_INCLUDED_MIMXRT10XX_INTERNAL_FLASH_H diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c index 38cf16a49..e3fef373f 100644 --- a/ports/mimxrt10xx/supervisor/port.c +++ b/ports/mimxrt10xx/supervisor/port.c @@ -72,7 +72,8 @@ #define NO_EXECUTION 1 #define EXECUTION 0 -// Shareable if the memory system manages coherency. +// Shareable if the memory system manages coherency. This means shared between memory bus masters, +// not just CPUs. #define NOT_SHAREABLE 0 #define SHAREABLE 1 @@ -207,9 +208,11 @@ __attribute__((used, naked)) void Reset_Handler(void) { MPU->RBAR = ARM_MPU_RBAR(13, 0x20000000U); MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_32KB); - // This is OCRAM. + // This is OCRAM. We mark it as shareable so that it isn't cached. This makes USB work at the + // cost of 1/4 speed OCRAM accesses. It will leave more room for caching data from the flash + // too which might be a net win. MPU->RBAR = ARM_MPU_RBAR(14, 0x20200000U); - MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB); + MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB); // We steal 64k from FlexRAM for ITCM and DTCM so disable those memory regions here. MPU->RBAR = ARM_MPU_RBAR(15, 0x20280000U); @@ -322,19 +325,22 @@ void reset_cpu(void) { reset(); } -supervisor_allocation* port_fixed_stack(void) { - return NULL; -} - extern uint32_t _ld_heap_start, _ld_heap_end, _ld_stack_top, _ld_stack_bottom; uint32_t *port_stack_get_limit(void) { - return &_ld_heap_start; + return &_ld_stack_bottom; } uint32_t *port_stack_get_top(void) { return &_ld_stack_top; } +supervisor_allocation _fixed_stack; +supervisor_allocation* port_fixed_stack(void) { + _fixed_stack.ptr = port_stack_get_limit(); + _fixed_stack.length = (port_stack_get_top() - port_stack_get_limit()) * sizeof(uint32_t); + return &_fixed_stack; +} + uint32_t *port_heap_get_bottom(void) { return &_ld_heap_start; } diff --git a/ports/mimxrt10xx/supervisor/usb.c b/ports/mimxrt10xx/supervisor/usb.c index af259405a..91135289c 100644 --- a/ports/mimxrt10xx/supervisor/usb.c +++ b/ports/mimxrt10xx/supervisor/usb.c @@ -50,10 +50,6 @@ void init_usb_hardware(void) { phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK); phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06); usb_phy->TX = phytx; - - // Temporarily disable the data cache until we can sort out all of the spots in TinyUSB that - // need the cache invalidated or cleaned. - SCB_DisableDCache(); } void USB_OTG1_IRQHandler(void) { diff --git a/ports/nrf/boards/pca10100/mpconfigboard.mk b/ports/nrf/boards/pca10100/mpconfigboard.mk index f952983f5..86ba65454 100644 --- a/ports/nrf/boards/pca10100/mpconfigboard.mk +++ b/ports/nrf/boards/pca10100/mpconfigboard.mk @@ -24,6 +24,7 @@ CIRCUITPY_RTC = 1 CIRCUITPY_SDCARDIO = 0 CIRCUITPY_TOUCHIO = 0 CIRCUITPY_ULAB = 0 +MICROPY_PY_ASYNC_AWAIT = 0 SUPEROPT_GC = 0 diff --git a/ports/nrf/boards/sparkfun_nrf52840_mini/mpconfigboard.mk b/ports/nrf/boards/sparkfun_nrf52840_mini/mpconfigboard.mk index f66b2eaf7..eb28ef5ea 100644 --- a/ports/nrf/boards/sparkfun_nrf52840_mini/mpconfigboard.mk +++ b/ports/nrf/boards/sparkfun_nrf52840_mini/mpconfigboard.mk @@ -6,3 +6,5 @@ USB_MANUFACTURER = "SparkFun Electronics" MCU_CHIP = nrf52840 INTERNAL_FLASH_FILESYSTEM = 1 + +MICROPY_PY_ASYNC_AWAIT = 0 diff --git a/ports/nrf/common-hal/_bleio/__init__.c b/ports/nrf/common-hal/_bleio/__init__.c index 496c9429f..5293f7ad1 100644 --- a/ports/nrf/common-hal/_bleio/__init__.c +++ b/ports/nrf/common-hal/_bleio/__init__.c @@ -50,7 +50,7 @@ void check_nrf_error(uint32_t err_code) { mp_raise_msg(&mp_type_TimeoutError, NULL); return; case BLE_ERROR_INVALID_CONN_HANDLE: - mp_raise_bleio_ConnectionError(translate("Not connected")); + mp_raise_ConnectionError(translate("Not connected")); return; default: mp_raise_bleio_BluetoothError(translate("Unknown soft device error: %04x"), err_code); @@ -115,7 +115,7 @@ bleio_adapter_obj_t common_hal_bleio_adapter_obj = { void common_hal_bleio_check_connected(uint16_t conn_handle) { if (conn_handle == BLE_CONN_HANDLE_INVALID) { - mp_raise_bleio_ConnectionError(translate("Not connected")); + mp_raise_ConnectionError(translate("Not connected")); } } diff --git a/ports/nrf/mpconfigport.mk b/ports/nrf/mpconfigport.mk index ed689545d..9560064fb 100644 --- a/ports/nrf/mpconfigport.mk +++ b/ports/nrf/mpconfigport.mk @@ -23,6 +23,9 @@ CIRCUITPY_AUDIOCORE ?= 1 CIRCUITPY_AUDIOMIXER ?= 1 CIRCUITPY_AUDIOPWMIO ?= 1 +# Native BLEIO is not compatible with HCI _bleio. +CIRCUITPY_BLEIO_HCI = 0 + CIRCUITPY_BLEIO ?= 1 # No I2CPeripheral implementation diff --git a/ports/nrf/supervisor/port.c b/ports/nrf/supervisor/port.c index bc8b47be7..493de43e0 100644 --- a/ports/nrf/supervisor/port.c +++ b/ports/nrf/supervisor/port.c @@ -274,11 +274,15 @@ uint32_t port_get_saved_word(void) { } uint64_t port_get_raw_ticks(uint8_t* subticks) { + common_hal_mcu_disable_interrupts(); uint32_t rtc = nrfx_rtc_counter_get(&rtc_instance); + uint32_t overflow_count = overflow_tracker.overflowed_ticks; + common_hal_mcu_enable_interrupts(); + if (subticks != NULL) { *subticks = (rtc % 32); } - return overflow_tracker.overflowed_ticks + rtc / 32; + return overflow_count + rtc / 32; } // Enable 1/1024 second tick. diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index bb50f8710..d303582e0 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -7,6 +7,7 @@ INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = NONE CIRCUITPY_NVM = 1 +CIRCUITPY_BLEIO_HCI = 0 MCU_SERIES = F4 MCU_VARIANT = STM32F411xE diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index bb304a317..a8aab00ff 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -190,6 +190,7 @@ safe_mode_t port_init(void) { _hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; HAL_RTC_Init(&_hrtc); + HAL_RTCEx_EnableBypassShadow(&_hrtc); HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); // Turn off SysTick @@ -328,9 +329,23 @@ volatile uint32_t cached_date = 0; volatile uint32_t seconds_to_minute = 0; volatile uint32_t cached_hours_minutes = 0; uint64_t port_get_raw_ticks(uint8_t* subticks) { - uint32_t subseconds = rtc_clock_frequency - (uint32_t)(RTC->SSR); + // Disable IRQs to ensure we read all of the RTC registers as close in time as possible. Read + // SSR twice to make sure we didn't read across a tick. + __disable_irq(); + uint32_t first_ssr = (uint32_t)(RTC->SSR); uint32_t time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); uint32_t date = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); + uint32_t ssr = (uint32_t)(RTC->SSR); + while (ssr != first_ssr) { + first_ssr = ssr; + time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); + date = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); + ssr = (uint32_t)(RTC->SSR); + } + __enable_irq(); + + uint32_t subseconds = rtc_clock_frequency - 1 - ssr; + if (date != cached_date) { uint32_t year = (uint8_t)((date & (RTC_DR_YT | RTC_DR_YU)) >> 16U); uint8_t month = (uint8_t)((date & (RTC_DR_MT | RTC_DR_MU)) >> 8U); @@ -349,6 +364,7 @@ uint64_t port_get_raw_ticks(uint8_t* subticks) { hours = (uint8_t)RTC_Bcd2ToByte(hours); minutes = (uint8_t)RTC_Bcd2ToByte(minutes); seconds_to_minute = 60 * (60 * hours + minutes); + cached_hours_minutes = hours_minutes; } uint8_t seconds = (uint8_t)(time & (RTC_TR_ST | RTC_TR_SU)); seconds = (uint8_t)RTC_Bcd2ToByte(seconds); @@ -407,7 +423,7 @@ void port_interrupt_after_ticks(uint32_t ticks) { alarm.AlarmMask = RTC_ALARMMASK_ALL; } - alarm.AlarmTime.SubSeconds = rtc_clock_frequency - + alarm.AlarmTime.SubSeconds = rtc_clock_frequency - 1 - ((raw_ticks % 1024) * 32); alarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; alarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_SET; diff --git a/ports/unix/Makefile b/ports/unix/Makefile index 5d4b168fe..4bfb13c6a 100644 --- a/ports/unix/Makefile +++ b/ports/unix/Makefile @@ -134,7 +134,7 @@ SRC_MOD += modjni.c endif # source files -SRC_C = \ +SRC_C += \ main.c \ gccollect.c \ unix_mphal.c \ |