diff options
Diffstat (limited to 'ports')
732 files changed, 13276 insertions, 12828 deletions
diff --git a/ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h index b97131f0b..a3d67d8b3 100644 --- a/ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h +++ b/ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h @@ -93,8 +93,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 0 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 0 division <0x0000-0xFFFF> // <i> // <id> gclk_gen_0_div #ifndef CONF_GCLK_GEN_0_DIV @@ -177,8 +177,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 1 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 1 division <0x0000-0xFFFF> // <i> // <id> gclk_gen_1_div #ifndef CONF_GCLK_GEN_1_DIV @@ -263,8 +263,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 2 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 2 division <0x0000-0xFFFF> // <i> // <id> gclk_gen_2_div #ifndef CONF_GCLK_GEN_2_DIV @@ -349,8 +349,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 3 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 3 division <0x0000-0xFFFF> // <i> // <id> gclk_gen_3_div #ifndef CONF_GCLK_GEN_3_DIV @@ -435,8 +435,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 4 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 4 division <0x0000-0xFFFF> // <i> // <id> gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV @@ -521,8 +521,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 5 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 5 division <0x0000-0xFFFF> // <i> // <id> gclk_gen_5_div #ifndef CONF_GCLK_GEN_5_DIV @@ -607,8 +607,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 6 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 6 division <0x0000-0xFFFF> // <i> // <id> gclk_gen_6_div #ifndef CONF_GCLK_GEN_6_DIV @@ -693,8 +693,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 7 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 7 division <0x0000-0xFFFF> // <i> // <id> gclk_gen_7_div #ifndef CONF_GCLK_GEN_7_DIV diff --git a/ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h index 85d05fc50..007a72d06 100644 --- a/ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h @@ -294,12 +294,12 @@ // BAUD: register value low [7:0] // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW #define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ - / 1000)) \ - * 10 \ - + 5) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10)) + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10)) #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) #warning Requested I2C baudrate too low, please check @@ -309,9 +309,9 @@ #define CONF_SERCOM_1_I2CM_BAUD_RATE 1 #else #define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) #endif #endif @@ -506,7 +506,7 @@ #if CONF_SERCOM_2_USART_SAMPR == 0 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -514,7 +514,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 1 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -522,7 +522,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 2 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -530,7 +530,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 3 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -538,7 +538,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 4 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -552,9 +552,9 @@ #define CONF_SERCOM_3_SPI_ENABLE 1 #endif -//<o> SPI DMA TX Channel <0-32> -//<i> This defines DMA channel to be used -//<id> spi_master_dma_tx_channel +// <o> SPI DMA TX Channel <0-32> +// <i> This defines DMA channel to be used +// <id> spi_master_dma_tx_channel #ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL #define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0 #endif @@ -565,9 +565,9 @@ #define CONF_SERCOM_3_SPI_RX_CHANNEL 1 #endif -//<o> DMA Channel <0-32> -//<i> This defines DMA channel to be used -//<id> spi_master_dma_rx_channel +// <o> DMA Channel <0-32> +// <i> This defines DMA channel to be used +// <id> spi_master_dma_rx_channel #ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL #define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1 #endif diff --git a/ports/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h index 74ec2bee9..193298ed9 100644 --- a/ports/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h +++ b/ports/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h @@ -95,7 +95,7 @@ #endif // <o>Osc Calibration Value <0-65535> -// <i> Set the Oscillator Calibration Value +// <i> Set the Oscillator Calibration Value // <i> Default: 1 // <id> osc8m_arch_calib #ifndef CONF_OSC8M_CALIB @@ -183,7 +183,7 @@ #endif // <o>Osc Calibration Value <0-65535> -// <i> Set the Oscillator Calibration Value +// <i> Set the Oscillator Calibration Value // <i> Default: 0 // <id> osc32k_arch_calib #ifndef CONF_OSC32K_CALIB @@ -396,7 +396,7 @@ #endif // <o>Osc Calibration Value <0-255> -// <i> Set the Oscillator Calibration Value +// <i> Set the Oscillator Calibration Value // <i> Default: 0 // <id> osculp32k_arch_calib #ifndef CONF_OSCULP32K_CALIB @@ -536,7 +536,7 @@ #endif // <o>DFLL Multiply Factor<0-65535> -// <i> Set the DFLL Multiply Factor +// <i> Set the DFLL Multiply Factor // <i> Default: 0 // <id> dfll48m_mul #ifndef CONF_DFLL_MUL @@ -564,17 +564,17 @@ #if CONF_DFLL_OVERWRITE_CALIBRATION == 0 #define CONF_DEFAULT_CORASE \ - ((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos) + ((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos) #define CONF_DFLLVAL \ - SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \ - | SYSCTRL_DFLLVAL_FINE(512) + SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \ + | SYSCTRL_DFLLVAL_FINE(512) #else #define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE) #endif -//</e> +// </e> // </h> // </e> diff --git a/ports/atmel-samd/asf4_conf/samd21/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_tc_config.h index 90e9b0735..d651ca33a 100644 --- a/ports/atmel-samd/asf4_conf/samd21/hpl_tc_config.h +++ b/ports/atmel-samd/asf4_conf/samd21/hpl_tc_config.h @@ -27,7 +27,7 @@ #define CONF_TC3_PRESCALER TC_CTRLA_PRESCALER_DIV8_Val #endif -//<o> Period Value <0x00000000-0xFFFFFFFF> +// <o> Period Value <0x00000000-0xFFFFFFFF> // <id> tc_per #ifndef CONF_TC3_PER #define CONF_TC3_PER 0x32 @@ -52,7 +52,7 @@ /* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ #if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val #define CONF_TC3_CC0 \ - ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1)) + ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1)) #define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) #elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val @@ -83,7 +83,7 @@ // <h> Advanced settings /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val +// #define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val // <q> Run in standby // <i> Indicates whether the will continue running in standby sleep mode or not @@ -103,14 +103,14 @@ #endif /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC3_DIR 0 -//#define CONF_TC3_ONESHOT 0 +// #define CONF_TC3_DIR 0 +// #define CONF_TC3_ONESHOT 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC3_INVEN0 0 -//#define CONF_TC3_INVEN1 0 -//#define CONF_TC3_CPTEN0 0 -//#define CONF_TC3_CPTEN1 0 +// #define CONF_TC3_INVEN0 0 +// #define CONF_TC3_INVEN1 0 +// #define CONF_TC3_CPTEN0 0 +// #define CONF_TC3_CPTEN1 0 // <q> Debug Running Mode // <i> Indicates whether the Debug Running Mode is enabled or not diff --git a/ports/atmel-samd/asf4_conf/samd21/usbd_config.h b/ports/atmel-samd/asf4_conf/samd21/usbd_config.h index df6dac3f7..b0f570b5e 100644 --- a/ports/atmel-samd/asf4_conf/samd21/usbd_config.h +++ b/ports/atmel-samd/asf4_conf/samd21/usbd_config.h @@ -101,7 +101,7 @@ #ifndef CONF_USB_COMPOSITE_IPRODUCT #define CONF_USB_COMPOSITE_IPRODUCT \ - (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) + (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) #endif // <s> Unicode string of iProduct @@ -124,8 +124,8 @@ #ifndef CONF_USB_COMPOSITE_ISERIALNUM #define CONF_USB_COMPOSITE_ISERIALNUM \ - (CONF_USB_COMPOSITE_ISERIALNUM_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) + (CONF_USB_COMPOSITE_ISERIALNUM_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) #endif // <s> Unicode string of iSerialNum @@ -162,9 +162,9 @@ #ifndef CONF_USB_COMPOSITE_ICONFIG #define CONF_USB_COMPOSITE_ICONFIG \ - (CONF_USB_COMPOSITE_ICONFIG_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ - + CONF_USB_COMPOSITE_ICONFIG_EN)) + (CONF_USB_COMPOSITE_ICONFIG_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ + + CONF_USB_COMPOSITE_ICONFIG_EN)) #endif // <s> Unicode string of iConfig @@ -453,9 +453,9 @@ #ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT #define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ - 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ - 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ - 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 #endif // <o> HID Generic INTERRUPT IN Endpoint Address @@ -650,7 +650,7 @@ #ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) #endif // </e> @@ -713,7 +713,7 @@ #ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) #endif // </e> @@ -775,7 +775,7 @@ #ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) #endif // </e> @@ -837,7 +837,7 @@ #ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) #endif // </e> diff --git a/ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h index 6f4f01a7e..1dda85a69 100644 --- a/ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h +++ b/ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h @@ -11,7 +11,7 @@ // Used in hpl/core/hpl_init.c to define which clocks should be initialized first. // Not clear why all these need to be specified, but it doesn't work properly otherwise. -//#define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5) +// #define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5) #define CIRCUITPY_GCLK_INIT_1ST 0xffff /* Auto-generated config file hpl_gclk_config.h */ @@ -52,7 +52,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_0_div_sel +// <id> gclk_gen_0_div_sel #ifndef CONF_GCLK_GEN_0_DIVSEL #define CONF_GCLK_GEN_0_DIVSEL 0 #endif @@ -86,8 +86,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 0 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 0 division <0x0000-0xFFFF> // <id> gclk_gen_0_div #ifndef CONF_GCLK_GEN_0_DIV #define CONF_GCLK_GEN_0_DIV 1 @@ -126,7 +126,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_1_div_sel +// <id> gclk_gen_1_div_sel #ifndef CONF_GCLK_GEN_1_DIVSEL #define CONF_GCLK_GEN_1_DIVSEL 0 #endif @@ -160,8 +160,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 1 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 1 division <0x0000-0xFFFF> // <id> gclk_gen_1_div #ifndef CONF_GCLK_GEN_1_DIV #define CONF_GCLK_GEN_1_DIV 1 @@ -201,7 +201,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_2_div_sel +// <id> gclk_gen_2_div_sel #ifndef CONF_GCLK_GEN_2_DIVSEL #define CONF_GCLK_GEN_2_DIVSEL 1 #endif @@ -235,8 +235,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 2 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 2 division <0x0000-0xFFFF> // <id> gclk_gen_2_div #ifndef CONF_GCLK_GEN_2_DIV #define CONF_GCLK_GEN_2_DIV 4 @@ -276,7 +276,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_3_div_sel +// <id> gclk_gen_3_div_sel #ifndef CONF_GCLK_GEN_3_DIVSEL #define CONF_GCLK_GEN_3_DIVSEL 0 #endif @@ -310,8 +310,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 3 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 3 division <0x0000-0xFFFF> // <id> gclk_gen_3_div #ifndef CONF_GCLK_GEN_3_DIV #define CONF_GCLK_GEN_3_DIV 1 @@ -351,7 +351,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_4_div_sel +// <id> gclk_gen_4_div_sel #ifndef CONF_GCLK_GEN_4_DIVSEL #define CONF_GCLK_GEN_4_DIVSEL 0 #endif @@ -385,8 +385,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 4 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 4 division <0x0000-0xFFFF> // <id> gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV #define CONF_GCLK_GEN_4_DIV 1 @@ -426,7 +426,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_5_div_sel +// <id> gclk_gen_5_div_sel #ifndef CONF_GCLK_GEN_5_DIVSEL #define CONF_GCLK_GEN_5_DIVSEL 0 #endif @@ -460,8 +460,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 5 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 5 division <0x0000-0xFFFF> // <id> gclk_gen_5_div #ifndef CONF_GCLK_GEN_5_DIV #define CONF_GCLK_GEN_5_DIV 24 @@ -501,7 +501,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_6_div_sel +// <id> gclk_gen_6_div_sel #ifndef CONF_GCLK_GEN_6_DIVSEL #define CONF_GCLK_GEN_6_DIVSEL 0 #endif @@ -535,8 +535,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 6 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 6 division <0x0000-0xFFFF> // <id> gclk_gen_6_div #ifndef CONF_GCLK_GEN_6_DIV #define CONF_GCLK_GEN_6_DIV 4 @@ -576,7 +576,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_7_div_sel +// <id> gclk_gen_7_div_sel #ifndef CONF_GCLK_GEN_7_DIVSEL #define CONF_GCLK_GEN_7_DIVSEL 0 #endif @@ -610,8 +610,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 7 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 7 division <0x0000-0xFFFF> // <id> gclk_gen_7_div #ifndef CONF_GCLK_GEN_7_DIV #define CONF_GCLK_GEN_7_DIV 1 @@ -651,7 +651,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_8_div_sel +// <id> gclk_gen_8_div_sel #ifndef CONF_GCLK_GEN_8_DIVSEL #define CONF_GCLK_GEN_8_DIVSEL 0 #endif @@ -685,8 +685,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 8 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 8 division <0x0000-0xFFFF> // <id> gclk_gen_8_div #ifndef CONF_GCLK_GEN_8_DIV #define CONF_GCLK_GEN_8_DIV 1 @@ -726,7 +726,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_9_div_sel +// <id> gclk_gen_9_div_sel #ifndef CONF_GCLK_GEN_9_DIVSEL #define CONF_GCLK_GEN_9_DIVSEL 0 #endif @@ -760,8 +760,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 9 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 9 division <0x0000-0xFFFF> // <id> gclk_gen_9_div #ifndef CONF_GCLK_GEN_9_DIV #define CONF_GCLK_GEN_9_DIV 1 @@ -801,7 +801,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_10_div_sel +// <id> gclk_gen_10_div_sel #ifndef CONF_GCLK_GEN_10_DIVSEL #define CONF_GCLK_GEN_10_DIVSEL 0 #endif @@ -835,8 +835,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 10 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 10 division <0x0000-0xFFFF> // <id> gclk_gen_10_div #ifndef CONF_GCLK_GEN_10_DIV #define CONF_GCLK_GEN_10_DIV 1 @@ -876,7 +876,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_11_div_sel +// <id> gclk_gen_11_div_sel #ifndef CONF_GCLK_GEN_11_DIVSEL #define CONF_GCLK_GEN_11_DIVSEL 0 #endif @@ -910,8 +910,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 11 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 11 division <0x0000-0xFFFF> // <id> gclk_gen_11_div #ifndef CONF_GCLK_GEN_11_DIV #define CONF_GCLK_GEN_11_DIV 1 diff --git a/ports/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h index cd1186605..f7f79fada 100644 --- a/ports/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h +++ b/ports/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h @@ -96,8 +96,8 @@ #ifndef CONF_XOSC0_XTALEN #define CONF_XOSC0_XTALEN 0 #endif -//</h> -//</e> +// </h> +// </e> #if CONF_XOSC0_FREQUENCY >= 32000000 #define CONF_XOSC0_CFDPRESC 0x0 @@ -209,8 +209,8 @@ #ifndef CONF_XOSC1_XTALEN #define CONF_XOSC1_XTALEN 0 #endif -//</h> -//</e> +// </h> +// </e> #if CONF_XOSC1_FREQUENCY >= 32000000 #define CONF_XOSC1_CFDPRESC 0x0 @@ -372,11 +372,11 @@ #define CONF_DFLL_FINE (0x80) #endif -//</e> +// </e> -//</h> +// </h> -//</e> +// </e> // <e> FDPLL0 Configuration // <i> Indicates whether configuration for FDPLL0 is enabled or not @@ -501,8 +501,8 @@ #define CONF_FDPLL0_FILTER 0x0 #endif -//</h> -//</e> +// </h> +// </e> // <e> FDPLL1 Configuration // <i> Indicates whether configuration for FDPLL1 is enabled or not // <id> enable_fdpll1 @@ -626,8 +626,8 @@ #define CONF_FDPLL1_FILTER 0x0 #endif -//</h> -//</e> +// </h> +// </e> // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h index cd411154c..b43861977 100644 --- a/ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h @@ -294,12 +294,12 @@ // BAUD: register value low [7:0] // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW #define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ - / 1000)) \ - * 10 \ - + 5) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10)) + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10)) #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) #warning Requested I2C baudrate too low, please check @@ -309,9 +309,9 @@ #define CONF_SERCOM_1_I2CM_BAUD_RATE 1 #else #define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) #endif #endif @@ -525,7 +525,7 @@ #if CONF_SERCOM_2_USART_SAMPR == 0 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -533,7 +533,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 1 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -541,7 +541,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 2 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -549,7 +549,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 3 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -557,7 +557,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 4 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -571,9 +571,9 @@ #define CONF_SERCOM_3_SPI_ENABLE 1 #endif -//<o> SPI DMA TX Channel <0-32> -//<i> This defines DMA channel to be used -//<id> spi_master_dma_tx_channel +// <o> SPI DMA TX Channel <0-32> +// <i> This defines DMA channel to be used +// <id> spi_master_dma_tx_channel #ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL #define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0 #endif @@ -584,9 +584,9 @@ #define CONF_SERCOM_3_SPI_RX_CHANNEL 1 #endif -//<o> DMA Channel <0-32> -//<i> This defines DMA channel to be used -//<id> spi_master_dma_rx_channel +// <o> DMA Channel <0-32> +// <i> This defines DMA channel to be used +// <id> spi_master_dma_rx_channel #ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL #define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1 #endif diff --git a/ports/atmel-samd/asf4_conf/samd51/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_tc_config.h index 38d48e9b6..3bc688295 100644 --- a/ports/atmel-samd/asf4_conf/samd51/hpl_tc_config.h +++ b/ports/atmel-samd/asf4_conf/samd51/hpl_tc_config.h @@ -45,7 +45,7 @@ /* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ #if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val #define CONF_TC0_CC0 \ - ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) #define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) #elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val @@ -114,15 +114,15 @@ #endif /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CAPTEN0 0 -//#define CONF_TC0_CAPTEN1 0 -//#define CONF_TC0_COPEN0 0 -//#define CONF_TC0_COPEN1 0 +// #define CONF_TC0_CAPTEN0 0 +// #define CONF_TC0_CAPTEN1 0 +// #define CONF_TC0_COPEN0 0 +// #define CONF_TC0_COPEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_DIR 0 -//#define CONF_TC0_ONESHOT 0 -//#define CONF_TC0_LUPD 0 +// #define CONF_TC0_DIR 0 +// #define CONF_TC0_ONESHOT 0 +// #define CONF_TC0_LUPD 0 // <q> Debug Running Mode // <i> Indicates whether the Debug Running Mode is enabled or not @@ -182,25 +182,25 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // <i> Event which will be performed on an event -//<id> tc_arch_evact +// <id> tc_arch_evact #ifndef CONF_TC0_EVACT #define CONF_TC0_EVACT 0 #endif // </e> /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val +// #define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_INVEN0 0 -//#define CONF_TC0_INVEN1 0 +// #define CONF_TC0_INVEN0 0 +// #define CONF_TC0_INVEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_PERBUF 0 +// #define CONF_TC0_PERBUF 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CCBUF0 0 -//#define CONF_TC0_CCBUF1 0 +// #define CONF_TC0_CCBUF0 0 +// #define CONF_TC0_CCBUF1 0 // </h> diff --git a/ports/atmel-samd/asf4_conf/samd51/usbd_config.h b/ports/atmel-samd/asf4_conf/samd51/usbd_config.h index be1fa3c9e..b2629e123 100644 --- a/ports/atmel-samd/asf4_conf/samd51/usbd_config.h +++ b/ports/atmel-samd/asf4_conf/samd51/usbd_config.h @@ -101,7 +101,7 @@ #ifndef CONF_USB_COMPOSITE_IPRODUCT #define CONF_USB_COMPOSITE_IPRODUCT \ - (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) + (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) #endif // <s> Unicode string of iProduct @@ -124,8 +124,8 @@ #ifndef CONF_USB_COMPOSITE_ISERIALNUM #define CONF_USB_COMPOSITE_ISERIALNUM \ - (CONF_USB_COMPOSITE_ISERIALNUM_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) + (CONF_USB_COMPOSITE_ISERIALNUM_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) #endif // <s> Unicode string of iSerialNum @@ -162,9 +162,9 @@ #ifndef CONF_USB_COMPOSITE_ICONFIG #define CONF_USB_COMPOSITE_ICONFIG \ - (CONF_USB_COMPOSITE_ICONFIG_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ - + CONF_USB_COMPOSITE_ICONFIG_EN)) + (CONF_USB_COMPOSITE_ICONFIG_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ + + CONF_USB_COMPOSITE_ICONFIG_EN)) #endif // <s> Unicode string of iConfig @@ -453,9 +453,9 @@ #ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT #define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ - 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ - 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ - 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 #endif // <o> HID Generic INTERRUPT IN Endpoint Address @@ -650,7 +650,7 @@ #ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) #endif // </e> @@ -713,7 +713,7 @@ #ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) #endif // </e> @@ -775,7 +775,7 @@ #ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) #endif // </e> @@ -837,7 +837,7 @@ #ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) #endif // </e> diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h index 6f4f01a7e..1dda85a69 100644 --- a/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h +++ b/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h @@ -11,7 +11,7 @@ // Used in hpl/core/hpl_init.c to define which clocks should be initialized first. // Not clear why all these need to be specified, but it doesn't work properly otherwise. -//#define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5) +// #define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5) #define CIRCUITPY_GCLK_INIT_1ST 0xffff /* Auto-generated config file hpl_gclk_config.h */ @@ -52,7 +52,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_0_div_sel +// <id> gclk_gen_0_div_sel #ifndef CONF_GCLK_GEN_0_DIVSEL #define CONF_GCLK_GEN_0_DIVSEL 0 #endif @@ -86,8 +86,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 0 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 0 division <0x0000-0xFFFF> // <id> gclk_gen_0_div #ifndef CONF_GCLK_GEN_0_DIV #define CONF_GCLK_GEN_0_DIV 1 @@ -126,7 +126,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_1_div_sel +// <id> gclk_gen_1_div_sel #ifndef CONF_GCLK_GEN_1_DIVSEL #define CONF_GCLK_GEN_1_DIVSEL 0 #endif @@ -160,8 +160,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 1 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 1 division <0x0000-0xFFFF> // <id> gclk_gen_1_div #ifndef CONF_GCLK_GEN_1_DIV #define CONF_GCLK_GEN_1_DIV 1 @@ -201,7 +201,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_2_div_sel +// <id> gclk_gen_2_div_sel #ifndef CONF_GCLK_GEN_2_DIVSEL #define CONF_GCLK_GEN_2_DIVSEL 1 #endif @@ -235,8 +235,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 2 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 2 division <0x0000-0xFFFF> // <id> gclk_gen_2_div #ifndef CONF_GCLK_GEN_2_DIV #define CONF_GCLK_GEN_2_DIV 4 @@ -276,7 +276,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_3_div_sel +// <id> gclk_gen_3_div_sel #ifndef CONF_GCLK_GEN_3_DIVSEL #define CONF_GCLK_GEN_3_DIVSEL 0 #endif @@ -310,8 +310,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 3 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 3 division <0x0000-0xFFFF> // <id> gclk_gen_3_div #ifndef CONF_GCLK_GEN_3_DIV #define CONF_GCLK_GEN_3_DIV 1 @@ -351,7 +351,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_4_div_sel +// <id> gclk_gen_4_div_sel #ifndef CONF_GCLK_GEN_4_DIVSEL #define CONF_GCLK_GEN_4_DIVSEL 0 #endif @@ -385,8 +385,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 4 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 4 division <0x0000-0xFFFF> // <id> gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV #define CONF_GCLK_GEN_4_DIV 1 @@ -426,7 +426,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_5_div_sel +// <id> gclk_gen_5_div_sel #ifndef CONF_GCLK_GEN_5_DIVSEL #define CONF_GCLK_GEN_5_DIVSEL 0 #endif @@ -460,8 +460,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 5 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 5 division <0x0000-0xFFFF> // <id> gclk_gen_5_div #ifndef CONF_GCLK_GEN_5_DIV #define CONF_GCLK_GEN_5_DIV 24 @@ -501,7 +501,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_6_div_sel +// <id> gclk_gen_6_div_sel #ifndef CONF_GCLK_GEN_6_DIVSEL #define CONF_GCLK_GEN_6_DIVSEL 0 #endif @@ -535,8 +535,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 6 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 6 division <0x0000-0xFFFF> // <id> gclk_gen_6_div #ifndef CONF_GCLK_GEN_6_DIV #define CONF_GCLK_GEN_6_DIV 4 @@ -576,7 +576,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_7_div_sel +// <id> gclk_gen_7_div_sel #ifndef CONF_GCLK_GEN_7_DIVSEL #define CONF_GCLK_GEN_7_DIVSEL 0 #endif @@ -610,8 +610,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 7 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 7 division <0x0000-0xFFFF> // <id> gclk_gen_7_div #ifndef CONF_GCLK_GEN_7_DIV #define CONF_GCLK_GEN_7_DIV 1 @@ -651,7 +651,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_8_div_sel +// <id> gclk_gen_8_div_sel #ifndef CONF_GCLK_GEN_8_DIVSEL #define CONF_GCLK_GEN_8_DIVSEL 0 #endif @@ -685,8 +685,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 8 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 8 division <0x0000-0xFFFF> // <id> gclk_gen_8_div #ifndef CONF_GCLK_GEN_8_DIV #define CONF_GCLK_GEN_8_DIV 1 @@ -726,7 +726,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_9_div_sel +// <id> gclk_gen_9_div_sel #ifndef CONF_GCLK_GEN_9_DIVSEL #define CONF_GCLK_GEN_9_DIVSEL 0 #endif @@ -760,8 +760,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 9 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 9 division <0x0000-0xFFFF> // <id> gclk_gen_9_div #ifndef CONF_GCLK_GEN_9_DIV #define CONF_GCLK_GEN_9_DIV 1 @@ -801,7 +801,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_10_div_sel +// <id> gclk_gen_10_div_sel #ifndef CONF_GCLK_GEN_10_DIVSEL #define CONF_GCLK_GEN_10_DIVSEL 0 #endif @@ -835,8 +835,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 10 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 10 division <0x0000-0xFFFF> // <id> gclk_gen_10_div #ifndef CONF_GCLK_GEN_10_DIV #define CONF_GCLK_GEN_10_DIV 1 @@ -876,7 +876,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_11_div_sel +// <id> gclk_gen_11_div_sel #ifndef CONF_GCLK_GEN_11_DIVSEL #define CONF_GCLK_GEN_11_DIVSEL 0 #endif @@ -910,8 +910,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 11 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 11 division <0x0000-0xFFFF> // <id> gclk_gen_11_div #ifndef CONF_GCLK_GEN_11_DIV #define CONF_GCLK_GEN_11_DIV 1 diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h index cd1186605..f7f79fada 100644 --- a/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h +++ b/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h @@ -96,8 +96,8 @@ #ifndef CONF_XOSC0_XTALEN #define CONF_XOSC0_XTALEN 0 #endif -//</h> -//</e> +// </h> +// </e> #if CONF_XOSC0_FREQUENCY >= 32000000 #define CONF_XOSC0_CFDPRESC 0x0 @@ -209,8 +209,8 @@ #ifndef CONF_XOSC1_XTALEN #define CONF_XOSC1_XTALEN 0 #endif -//</h> -//</e> +// </h> +// </e> #if CONF_XOSC1_FREQUENCY >= 32000000 #define CONF_XOSC1_CFDPRESC 0x0 @@ -372,11 +372,11 @@ #define CONF_DFLL_FINE (0x80) #endif -//</e> +// </e> -//</h> +// </h> -//</e> +// </e> // <e> FDPLL0 Configuration // <i> Indicates whether configuration for FDPLL0 is enabled or not @@ -501,8 +501,8 @@ #define CONF_FDPLL0_FILTER 0x0 #endif -//</h> -//</e> +// </h> +// </e> // <e> FDPLL1 Configuration // <i> Indicates whether configuration for FDPLL1 is enabled or not // <id> enable_fdpll1 @@ -626,8 +626,8 @@ #define CONF_FDPLL1_FILTER 0x0 #endif -//</h> -//</e> +// </h> +// </e> // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h index cd411154c..b43861977 100644 --- a/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h @@ -294,12 +294,12 @@ // BAUD: register value low [7:0] // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW #define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ - / 1000)) \ - * 10 \ - + 5) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10)) + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10)) #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) #warning Requested I2C baudrate too low, please check @@ -309,9 +309,9 @@ #define CONF_SERCOM_1_I2CM_BAUD_RATE 1 #else #define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) #endif #endif @@ -525,7 +525,7 @@ #if CONF_SERCOM_2_USART_SAMPR == 0 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -533,7 +533,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 1 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -541,7 +541,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 2 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -549,7 +549,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 3 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -557,7 +557,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 4 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -571,9 +571,9 @@ #define CONF_SERCOM_3_SPI_ENABLE 1 #endif -//<o> SPI DMA TX Channel <0-32> -//<i> This defines DMA channel to be used -//<id> spi_master_dma_tx_channel +// <o> SPI DMA TX Channel <0-32> +// <i> This defines DMA channel to be used +// <id> spi_master_dma_tx_channel #ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL #define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0 #endif @@ -584,9 +584,9 @@ #define CONF_SERCOM_3_SPI_RX_CHANNEL 1 #endif -//<o> DMA Channel <0-32> -//<i> This defines DMA channel to be used -//<id> spi_master_dma_rx_channel +// <o> DMA Channel <0-32> +// <i> This defines DMA channel to be used +// <id> spi_master_dma_rx_channel #ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL #define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1 #endif diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h index 38d48e9b6..3bc688295 100644 --- a/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h +++ b/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h @@ -45,7 +45,7 @@ /* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ #if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val #define CONF_TC0_CC0 \ - ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) #define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) #elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val @@ -114,15 +114,15 @@ #endif /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CAPTEN0 0 -//#define CONF_TC0_CAPTEN1 0 -//#define CONF_TC0_COPEN0 0 -//#define CONF_TC0_COPEN1 0 +// #define CONF_TC0_CAPTEN0 0 +// #define CONF_TC0_CAPTEN1 0 +// #define CONF_TC0_COPEN0 0 +// #define CONF_TC0_COPEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_DIR 0 -//#define CONF_TC0_ONESHOT 0 -//#define CONF_TC0_LUPD 0 +// #define CONF_TC0_DIR 0 +// #define CONF_TC0_ONESHOT 0 +// #define CONF_TC0_LUPD 0 // <q> Debug Running Mode // <i> Indicates whether the Debug Running Mode is enabled or not @@ -182,25 +182,25 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // <i> Event which will be performed on an event -//<id> tc_arch_evact +// <id> tc_arch_evact #ifndef CONF_TC0_EVACT #define CONF_TC0_EVACT 0 #endif // </e> /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val +// #define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_INVEN0 0 -//#define CONF_TC0_INVEN1 0 +// #define CONF_TC0_INVEN0 0 +// #define CONF_TC0_INVEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_PERBUF 0 +// #define CONF_TC0_PERBUF 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CCBUF0 0 -//#define CONF_TC0_CCBUF1 0 +// #define CONF_TC0_CCBUF0 0 +// #define CONF_TC0_CCBUF1 0 // </h> diff --git a/ports/atmel-samd/asf4_conf/same51/usbd_config.h b/ports/atmel-samd/asf4_conf/same51/usbd_config.h index be1fa3c9e..b2629e123 100644 --- a/ports/atmel-samd/asf4_conf/same51/usbd_config.h +++ b/ports/atmel-samd/asf4_conf/same51/usbd_config.h @@ -101,7 +101,7 @@ #ifndef CONF_USB_COMPOSITE_IPRODUCT #define CONF_USB_COMPOSITE_IPRODUCT \ - (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) + (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) #endif // <s> Unicode string of iProduct @@ -124,8 +124,8 @@ #ifndef CONF_USB_COMPOSITE_ISERIALNUM #define CONF_USB_COMPOSITE_ISERIALNUM \ - (CONF_USB_COMPOSITE_ISERIALNUM_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) + (CONF_USB_COMPOSITE_ISERIALNUM_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) #endif // <s> Unicode string of iSerialNum @@ -162,9 +162,9 @@ #ifndef CONF_USB_COMPOSITE_ICONFIG #define CONF_USB_COMPOSITE_ICONFIG \ - (CONF_USB_COMPOSITE_ICONFIG_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ - + CONF_USB_COMPOSITE_ICONFIG_EN)) + (CONF_USB_COMPOSITE_ICONFIG_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ + + CONF_USB_COMPOSITE_ICONFIG_EN)) #endif // <s> Unicode string of iConfig @@ -453,9 +453,9 @@ #ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT #define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ - 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ - 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ - 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 #endif // <o> HID Generic INTERRUPT IN Endpoint Address @@ -650,7 +650,7 @@ #ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) #endif // </e> @@ -713,7 +713,7 @@ #ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) #endif // </e> @@ -775,7 +775,7 @@ #ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) #endif // </e> @@ -837,7 +837,7 @@ #ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) #endif // </e> diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h index 6f4f01a7e..1dda85a69 100644 --- a/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h +++ b/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h @@ -11,7 +11,7 @@ // Used in hpl/core/hpl_init.c to define which clocks should be initialized first. // Not clear why all these need to be specified, but it doesn't work properly otherwise. -//#define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5) +// #define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5) #define CIRCUITPY_GCLK_INIT_1ST 0xffff /* Auto-generated config file hpl_gclk_config.h */ @@ -52,7 +52,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_0_div_sel +// <id> gclk_gen_0_div_sel #ifndef CONF_GCLK_GEN_0_DIVSEL #define CONF_GCLK_GEN_0_DIVSEL 0 #endif @@ -86,8 +86,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 0 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 0 division <0x0000-0xFFFF> // <id> gclk_gen_0_div #ifndef CONF_GCLK_GEN_0_DIV #define CONF_GCLK_GEN_0_DIV 1 @@ -126,7 +126,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_1_div_sel +// <id> gclk_gen_1_div_sel #ifndef CONF_GCLK_GEN_1_DIVSEL #define CONF_GCLK_GEN_1_DIVSEL 0 #endif @@ -160,8 +160,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 1 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 1 division <0x0000-0xFFFF> // <id> gclk_gen_1_div #ifndef CONF_GCLK_GEN_1_DIV #define CONF_GCLK_GEN_1_DIV 1 @@ -201,7 +201,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_2_div_sel +// <id> gclk_gen_2_div_sel #ifndef CONF_GCLK_GEN_2_DIVSEL #define CONF_GCLK_GEN_2_DIVSEL 1 #endif @@ -235,8 +235,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 2 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 2 division <0x0000-0xFFFF> // <id> gclk_gen_2_div #ifndef CONF_GCLK_GEN_2_DIV #define CONF_GCLK_GEN_2_DIV 4 @@ -276,7 +276,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_3_div_sel +// <id> gclk_gen_3_div_sel #ifndef CONF_GCLK_GEN_3_DIVSEL #define CONF_GCLK_GEN_3_DIVSEL 0 #endif @@ -310,8 +310,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 3 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 3 division <0x0000-0xFFFF> // <id> gclk_gen_3_div #ifndef CONF_GCLK_GEN_3_DIV #define CONF_GCLK_GEN_3_DIV 1 @@ -351,7 +351,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_4_div_sel +// <id> gclk_gen_4_div_sel #ifndef CONF_GCLK_GEN_4_DIVSEL #define CONF_GCLK_GEN_4_DIVSEL 0 #endif @@ -385,8 +385,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 4 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 4 division <0x0000-0xFFFF> // <id> gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV #define CONF_GCLK_GEN_4_DIV 1 @@ -426,7 +426,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_5_div_sel +// <id> gclk_gen_5_div_sel #ifndef CONF_GCLK_GEN_5_DIVSEL #define CONF_GCLK_GEN_5_DIVSEL 0 #endif @@ -460,8 +460,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 5 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 5 division <0x0000-0xFFFF> // <id> gclk_gen_5_div #ifndef CONF_GCLK_GEN_5_DIV #define CONF_GCLK_GEN_5_DIV 24 @@ -501,7 +501,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_6_div_sel +// <id> gclk_gen_6_div_sel #ifndef CONF_GCLK_GEN_6_DIVSEL #define CONF_GCLK_GEN_6_DIVSEL 0 #endif @@ -535,8 +535,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 6 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 6 division <0x0000-0xFFFF> // <id> gclk_gen_6_div #ifndef CONF_GCLK_GEN_6_DIV #define CONF_GCLK_GEN_6_DIV 4 @@ -576,7 +576,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_7_div_sel +// <id> gclk_gen_7_div_sel #ifndef CONF_GCLK_GEN_7_DIVSEL #define CONF_GCLK_GEN_7_DIVSEL 0 #endif @@ -610,8 +610,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 7 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 7 division <0x0000-0xFFFF> // <id> gclk_gen_7_div #ifndef CONF_GCLK_GEN_7_DIV #define CONF_GCLK_GEN_7_DIV 1 @@ -651,7 +651,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_8_div_sel +// <id> gclk_gen_8_div_sel #ifndef CONF_GCLK_GEN_8_DIVSEL #define CONF_GCLK_GEN_8_DIVSEL 0 #endif @@ -685,8 +685,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 8 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 8 division <0x0000-0xFFFF> // <id> gclk_gen_8_div #ifndef CONF_GCLK_GEN_8_DIV #define CONF_GCLK_GEN_8_DIV 1 @@ -726,7 +726,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_9_div_sel +// <id> gclk_gen_9_div_sel #ifndef CONF_GCLK_GEN_9_DIVSEL #define CONF_GCLK_GEN_9_DIVSEL 0 #endif @@ -760,8 +760,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 9 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 9 division <0x0000-0xFFFF> // <id> gclk_gen_9_div #ifndef CONF_GCLK_GEN_9_DIV #define CONF_GCLK_GEN_9_DIV 1 @@ -801,7 +801,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_10_div_sel +// <id> gclk_gen_10_div_sel #ifndef CONF_GCLK_GEN_10_DIVSEL #define CONF_GCLK_GEN_10_DIVSEL 0 #endif @@ -835,8 +835,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 10 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 10 division <0x0000-0xFFFF> // <id> gclk_gen_10_div #ifndef CONF_GCLK_GEN_10_DIV #define CONF_GCLK_GEN_10_DIV 1 @@ -876,7 +876,7 @@ // <q> Divide Selection // <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_11_div_sel +// <id> gclk_gen_11_div_sel #ifndef CONF_GCLK_GEN_11_DIVSEL #define CONF_GCLK_GEN_11_DIVSEL 0 #endif @@ -910,8 +910,8 @@ #endif // </h> -//<h> Generic Clock Generator Division -//<o> Generic clock generator 11 division <0x0000-0xFFFF> +// <h> Generic Clock Generator Division +// <o> Generic clock generator 11 division <0x0000-0xFFFF> // <id> gclk_gen_11_div #ifndef CONF_GCLK_GEN_11_DIV #define CONF_GCLK_GEN_11_DIV 1 diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_oscctrl_config.h index cd1186605..f7f79fada 100644 --- a/ports/atmel-samd/asf4_conf/same54/hpl_oscctrl_config.h +++ b/ports/atmel-samd/asf4_conf/same54/hpl_oscctrl_config.h @@ -96,8 +96,8 @@ #ifndef CONF_XOSC0_XTALEN #define CONF_XOSC0_XTALEN 0 #endif -//</h> -//</e> +// </h> +// </e> #if CONF_XOSC0_FREQUENCY >= 32000000 #define CONF_XOSC0_CFDPRESC 0x0 @@ -209,8 +209,8 @@ #ifndef CONF_XOSC1_XTALEN #define CONF_XOSC1_XTALEN 0 #endif -//</h> -//</e> +// </h> +// </e> #if CONF_XOSC1_FREQUENCY >= 32000000 #define CONF_XOSC1_CFDPRESC 0x0 @@ -372,11 +372,11 @@ #define CONF_DFLL_FINE (0x80) #endif -//</e> +// </e> -//</h> +// </h> -//</e> +// </e> // <e> FDPLL0 Configuration // <i> Indicates whether configuration for FDPLL0 is enabled or not @@ -501,8 +501,8 @@ #define CONF_FDPLL0_FILTER 0x0 #endif -//</h> -//</e> +// </h> +// </e> // <e> FDPLL1 Configuration // <i> Indicates whether configuration for FDPLL1 is enabled or not // <id> enable_fdpll1 @@ -626,8 +626,8 @@ #define CONF_FDPLL1_FILTER 0x0 #endif -//</h> -//</e> +// </h> +// </e> // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_sercom_config.h index cd411154c..b43861977 100644 --- a/ports/atmel-samd/asf4_conf/same54/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/same54/hpl_sercom_config.h @@ -294,12 +294,12 @@ // BAUD: register value low [7:0] // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW #define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ - / 1000)) \ - * 10 \ - + 5) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10)) + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10)) #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) #warning Requested I2C baudrate too low, please check @@ -309,9 +309,9 @@ #define CONF_SERCOM_1_I2CM_BAUD_RATE 1 #else #define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) #endif #endif @@ -525,7 +525,7 @@ #if CONF_SERCOM_2_USART_SAMPR == 0 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -533,7 +533,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 1 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -541,7 +541,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 2 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -549,7 +549,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 3 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -557,7 +557,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 4 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -571,9 +571,9 @@ #define CONF_SERCOM_3_SPI_ENABLE 1 #endif -//<o> SPI DMA TX Channel <0-32> -//<i> This defines DMA channel to be used -//<id> spi_master_dma_tx_channel +// <o> SPI DMA TX Channel <0-32> +// <i> This defines DMA channel to be used +// <id> spi_master_dma_tx_channel #ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL #define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0 #endif @@ -584,9 +584,9 @@ #define CONF_SERCOM_3_SPI_RX_CHANNEL 1 #endif -//<o> DMA Channel <0-32> -//<i> This defines DMA channel to be used -//<id> spi_master_dma_rx_channel +// <o> DMA Channel <0-32> +// <i> This defines DMA channel to be used +// <id> spi_master_dma_rx_channel #ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL #define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1 #endif diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_tc_config.h index 38d48e9b6..3bc688295 100644 --- a/ports/atmel-samd/asf4_conf/same54/hpl_tc_config.h +++ b/ports/atmel-samd/asf4_conf/same54/hpl_tc_config.h @@ -45,7 +45,7 @@ /* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ #if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val #define CONF_TC0_CC0 \ - ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) #define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) #elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val @@ -114,15 +114,15 @@ #endif /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CAPTEN0 0 -//#define CONF_TC0_CAPTEN1 0 -//#define CONF_TC0_COPEN0 0 -//#define CONF_TC0_COPEN1 0 +// #define CONF_TC0_CAPTEN0 0 +// #define CONF_TC0_CAPTEN1 0 +// #define CONF_TC0_COPEN0 0 +// #define CONF_TC0_COPEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_DIR 0 -//#define CONF_TC0_ONESHOT 0 -//#define CONF_TC0_LUPD 0 +// #define CONF_TC0_DIR 0 +// #define CONF_TC0_ONESHOT 0 +// #define CONF_TC0_LUPD 0 // <q> Debug Running Mode // <i> Indicates whether the Debug Running Mode is enabled or not @@ -182,25 +182,25 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // <i> Event which will be performed on an event -//<id> tc_arch_evact +// <id> tc_arch_evact #ifndef CONF_TC0_EVACT #define CONF_TC0_EVACT 0 #endif // </e> /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val +// #define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_INVEN0 0 -//#define CONF_TC0_INVEN1 0 +// #define CONF_TC0_INVEN0 0 +// #define CONF_TC0_INVEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_PERBUF 0 +// #define CONF_TC0_PERBUF 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CCBUF0 0 -//#define CONF_TC0_CCBUF1 0 +// #define CONF_TC0_CCBUF0 0 +// #define CONF_TC0_CCBUF1 0 // </h> diff --git a/ports/atmel-samd/asf4_conf/same54/usbd_config.h b/ports/atmel-samd/asf4_conf/same54/usbd_config.h index be1fa3c9e..b2629e123 100644 --- a/ports/atmel-samd/asf4_conf/same54/usbd_config.h +++ b/ports/atmel-samd/asf4_conf/same54/usbd_config.h @@ -101,7 +101,7 @@ #ifndef CONF_USB_COMPOSITE_IPRODUCT #define CONF_USB_COMPOSITE_IPRODUCT \ - (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) + (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) #endif // <s> Unicode string of iProduct @@ -124,8 +124,8 @@ #ifndef CONF_USB_COMPOSITE_ISERIALNUM #define CONF_USB_COMPOSITE_ISERIALNUM \ - (CONF_USB_COMPOSITE_ISERIALNUM_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) + (CONF_USB_COMPOSITE_ISERIALNUM_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) #endif // <s> Unicode string of iSerialNum @@ -162,9 +162,9 @@ #ifndef CONF_USB_COMPOSITE_ICONFIG #define CONF_USB_COMPOSITE_ICONFIG \ - (CONF_USB_COMPOSITE_ICONFIG_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ - + CONF_USB_COMPOSITE_ICONFIG_EN)) + (CONF_USB_COMPOSITE_ICONFIG_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ + + CONF_USB_COMPOSITE_ICONFIG_EN)) #endif // <s> Unicode string of iConfig @@ -453,9 +453,9 @@ #ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT #define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ - 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ - 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ - 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 #endif // <o> HID Generic INTERRUPT IN Endpoint Address @@ -650,7 +650,7 @@ #ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) #endif // </e> @@ -713,7 +713,7 @@ #ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) #endif // </e> @@ -775,7 +775,7 @@ #ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) #endif // </e> @@ -837,7 +837,7 @@ #ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) #endif // </e> diff --git a/ports/atmel-samd/audio_dma.c b/ports/atmel-samd/audio_dma.c index c6c636160..0fe71e6d5 100644 --- a/ports/atmel-samd/audio_dma.c +++ b/ports/atmel-samd/audio_dma.c @@ -38,7 +38,7 @@ #if CIRCUITPY_AUDIOIO || CIRCUITPY_AUDIOBUSIO -static audio_dma_t* audio_dma_state[AUDIO_DMA_CHANNEL_COUNT]; +static audio_dma_t *audio_dma_state[AUDIO_DMA_CHANNEL_COUNT]; // This cannot be in audio_dma_state because it's volatile. static volatile bool audio_dma_pending[AUDIO_DMA_CHANNEL_COUNT]; @@ -64,20 +64,22 @@ void audio_dma_free_channel(uint8_t channel) { } void audio_dma_disable_channel(uint8_t channel) { - if (channel >= AUDIO_DMA_CHANNEL_COUNT) + if (channel >= AUDIO_DMA_CHANNEL_COUNT) { return; + } dma_disable_channel(channel); } void audio_dma_enable_channel(uint8_t channel) { - if (channel >= AUDIO_DMA_CHANNEL_COUNT) + if (channel >= AUDIO_DMA_CHANNEL_COUNT) { return; + } dma_enable_channel(channel); } -void audio_dma_convert_signed(audio_dma_t* dma, uint8_t* buffer, uint32_t buffer_length, - uint8_t** output_buffer, uint32_t* output_buffer_length, - uint8_t* output_spacing) { +void audio_dma_convert_signed(audio_dma_t *dma, uint8_t *buffer, uint32_t buffer_length, + uint8_t **output_buffer, uint32_t *output_buffer_length, + uint8_t *output_spacing) { if (dma->first_buffer_free) { *output_buffer = dma->first_buffer; } else { @@ -92,18 +94,18 @@ void audio_dma_convert_signed(audio_dma_t* dma, uint8_t* buffer, uint32_t buffer if (dma->bytes_per_sample == 1) { for (uint32_t i = 0; i < buffer_length; i += dma->spacing) { if (dma->signed_to_unsigned) { - ((uint8_t*) *output_buffer)[out_i] = ((int8_t*) buffer)[i] + 0x80; + ((uint8_t *)*output_buffer)[out_i] = ((int8_t *)buffer)[i] + 0x80; } else { - ((int8_t*) *output_buffer)[out_i] = ((uint8_t*) buffer)[i] - 0x80; + ((int8_t *)*output_buffer)[out_i] = ((uint8_t *)buffer)[i] - 0x80; } out_i += 1; } } else if (dma->bytes_per_sample == 2) { for (uint32_t i = 0; i < buffer_length / 2; i += dma->spacing) { if (dma->signed_to_unsigned) { - ((uint16_t*) *output_buffer)[out_i] = ((int16_t*) buffer)[i] + 0x8000; + ((uint16_t *)*output_buffer)[out_i] = ((int16_t *)buffer)[i] + 0x8000; } else { - ((int16_t*) *output_buffer)[out_i] = ((uint16_t*) buffer)[i] - 0x8000; + ((int16_t *)*output_buffer)[out_i] = ((uint16_t *)buffer)[i] - 0x8000; } out_i += 1; } @@ -117,14 +119,14 @@ void audio_dma_convert_signed(audio_dma_t* dma, uint8_t* buffer, uint32_t buffer dma->first_buffer_free = !dma->first_buffer_free; } -void audio_dma_load_next_block(audio_dma_t* dma) { - uint8_t* buffer; +void audio_dma_load_next_block(audio_dma_t *dma) { + uint8_t *buffer; uint32_t buffer_length; audioio_get_buffer_result_t get_buffer_result = audiosample_get_buffer(dma->sample, dma->single_channel, dma->audio_channel, - &buffer, &buffer_length); + &buffer, &buffer_length); - DmacDescriptor* descriptor = dma->second_descriptor; + DmacDescriptor *descriptor = dma->second_descriptor; if (dma->first_descriptor_free) { descriptor = dma_descriptor(dma->dma_channel); } @@ -135,14 +137,14 @@ void audio_dma_load_next_block(audio_dma_t* dma) { return; } - uint8_t* output_buffer; + uint8_t *output_buffer; uint32_t output_buffer_length; uint8_t output_spacing; audio_dma_convert_signed(dma, buffer, buffer_length, &output_buffer, &output_buffer_length, &output_spacing); descriptor->BTCNT.reg = output_buffer_length / dma->beat_size / output_spacing; - descriptor->SRCADDR.reg = ((uint32_t) output_buffer) + output_buffer_length; + descriptor->SRCADDR.reg = ((uint32_t)output_buffer) + output_buffer_length; if (get_buffer_result == GET_BUFFER_DONE) { if (dma->loop) { audiosample_reset_buffer(dma->sample, dma->single_channel, dma->audio_channel); @@ -153,8 +155,8 @@ void audio_dma_load_next_block(audio_dma_t* dma) { descriptor->BTCTRL.bit.VALID = true; } -static void setup_audio_descriptor(DmacDescriptor* descriptor, uint8_t beat_size, - uint8_t spacing, uint32_t output_register_address) { +static void setup_audio_descriptor(DmacDescriptor *descriptor, uint8_t beat_size, + uint8_t spacing, uint32_t output_register_address) { uint32_t beat_size_reg = DMAC_BTCTRL_BEATSIZE_BYTE; if (beat_size == 2) { beat_size_reg = DMAC_BTCTRL_BEATSIZE_HWORD; @@ -162,22 +164,22 @@ static void setup_audio_descriptor(DmacDescriptor* descriptor, uint8_t beat_size beat_size_reg = DMAC_BTCTRL_BEATSIZE_WORD; } descriptor->BTCTRL.reg = beat_size_reg | - DMAC_BTCTRL_SRCINC | - DMAC_BTCTRL_EVOSEL_BLOCK | - DMAC_BTCTRL_STEPSIZE(spacing - 1) | - DMAC_BTCTRL_STEPSEL_SRC; + DMAC_BTCTRL_SRCINC | + DMAC_BTCTRL_EVOSEL_BLOCK | + DMAC_BTCTRL_STEPSIZE(spacing - 1) | + DMAC_BTCTRL_STEPSEL_SRC; descriptor->DSTADDR.reg = output_register_address; } // Playback should be shutdown before calling this. -audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, - mp_obj_t sample, - bool loop, - bool single_channel, - uint8_t audio_channel, - bool output_signed, - uint32_t output_register_address, - uint8_t dma_trigger_source) { +audio_dma_result audio_dma_setup_playback(audio_dma_t *dma, + mp_obj_t sample, + bool loop, + bool single_channel, + uint8_t audio_channel, + bool output_signed, + uint32_t output_register_address, + uint8_t dma_trigger_source) { uint8_t dma_channel = audio_dma_allocate_channel(); if (dma_channel >= AUDIO_DMA_CHANNEL_COUNT) { return AUDIO_DMA_DMA_BUSY; @@ -199,18 +201,18 @@ audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, bool samples_signed; uint32_t max_buffer_length; audiosample_get_buffer_structure(sample, single_channel, &single_buffer, &samples_signed, - &max_buffer_length, &dma->spacing); + &max_buffer_length, &dma->spacing); uint8_t output_spacing = dma->spacing; if (output_signed != samples_signed) { output_spacing = 1; max_buffer_length /= dma->spacing; - dma->first_buffer = (uint8_t*) m_realloc(dma->first_buffer, max_buffer_length); + dma->first_buffer = (uint8_t *)m_realloc(dma->first_buffer, max_buffer_length); if (dma->first_buffer == NULL) { return AUDIO_DMA_MEMORY_ERROR; } dma->first_buffer_free = true; if (!single_buffer) { - dma->second_buffer = (uint8_t*) m_realloc(dma->second_buffer, max_buffer_length); + dma->second_buffer = (uint8_t *)m_realloc(dma->second_buffer, max_buffer_length); if (dma->second_buffer == NULL) { return AUDIO_DMA_MEMORY_ERROR; } @@ -221,7 +223,7 @@ audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, dma->event_channel = 0xff; if (!single_buffer) { - dma->second_descriptor = (DmacDescriptor*) m_malloc(sizeof(DmacDescriptor), false); + dma->second_descriptor = (DmacDescriptor *)m_malloc(sizeof(DmacDescriptor), false); if (dma->second_descriptor == NULL) { return AUDIO_DMA_MEMORY_ERROR; } @@ -257,26 +259,26 @@ audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, dma->beat_size *= 2; } -#ifdef SAM_D5X_E5X + #ifdef SAM_D5X_E5X int irq = dma->event_channel < 4 ? EVSYS_0_IRQn + dma->event_channel : EVSYS_4_IRQn; -#else + #else int irq = EVSYS_IRQn; -#endif + #endif NVIC_DisableIRQ(irq); NVIC_ClearPendingIRQ(irq); - DmacDescriptor* first_descriptor = dma_descriptor(dma_channel); + DmacDescriptor *first_descriptor = dma_descriptor(dma_channel); setup_audio_descriptor(first_descriptor, dma->beat_size, output_spacing, output_register_address); if (single_buffer) { first_descriptor->DESCADDR.reg = 0; if (dma->loop) { - first_descriptor->DESCADDR.reg = (uint32_t) first_descriptor; + first_descriptor->DESCADDR.reg = (uint32_t)first_descriptor; } } else { - first_descriptor->DESCADDR.reg = (uint32_t) dma->second_descriptor; + first_descriptor->DESCADDR.reg = (uint32_t)dma->second_descriptor; setup_audio_descriptor(dma->second_descriptor, dma->beat_size, output_spacing, output_register_address); - dma->second_descriptor->DESCADDR.reg = (uint32_t) first_descriptor; + dma->second_descriptor->DESCADDR.reg = (uint32_t)first_descriptor; } // Load the first two blocks up front. @@ -293,7 +295,7 @@ audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, return AUDIO_DMA_OK; } -void audio_dma_stop(audio_dma_t* dma) { +void audio_dma_stop(audio_dma_t *dma) { uint8_t channel = dma->dma_channel; if (channel < AUDIO_DMA_CHANNEL_COUNT) { audio_dma_disable_channel(channel); @@ -305,15 +307,15 @@ void audio_dma_stop(audio_dma_t* dma) { dma->dma_channel = AUDIO_DMA_CHANNEL_COUNT; } -void audio_dma_pause(audio_dma_t* dma) { +void audio_dma_pause(audio_dma_t *dma) { dma_suspend_channel(dma->dma_channel); } -void audio_dma_resume(audio_dma_t* dma) { +void audio_dma_resume(audio_dma_t *dma) { dma_resume_channel(dma->dma_channel); } -bool audio_dma_get_paused(audio_dma_t* dma) { +bool audio_dma_get_paused(audio_dma_t *dma) { if (dma->dma_channel >= AUDIO_DMA_CHANNEL_COUNT) { return false; } @@ -322,7 +324,7 @@ bool audio_dma_get_paused(audio_dma_t* dma) { return (status & DMAC_CHINTFLAG_SUSP) != 0; } -void audio_dma_init(audio_dma_t* dma) { +void audio_dma_init(audio_dma_t *dma) { dma->dma_channel = AUDIO_DMA_CHANNEL_COUNT; } @@ -337,7 +339,7 @@ void audio_dma_reset(void) { } } -bool audio_dma_get_playing(audio_dma_t* dma) { +bool audio_dma_get_playing(audio_dma_t *dma) { if (dma->dma_channel >= AUDIO_DMA_CHANNEL_COUNT) { return false; } @@ -352,7 +354,7 @@ bool audio_dma_get_playing(audio_dma_t* dma) { // WARN(tannewt): DO NOT print from here, or anything it calls. Printing calls // background tasks such as this and causes a stack overflow. STATIC void dma_callback_fun(void *arg) { - audio_dma_t* dma = arg; + audio_dma_t *dma = arg; if (dma == NULL) { return; } @@ -362,7 +364,7 @@ STATIC void dma_callback_fun(void *arg) { void evsyshandler_common(void) { for (uint8_t i = 0; i < AUDIO_DMA_CHANNEL_COUNT; i++) { - audio_dma_t* dma = audio_dma_state[i]; + audio_dma_t *dma = audio_dma_state[i]; if (dma == NULL) { continue; } @@ -370,18 +372,30 @@ void evsyshandler_common(void) { if (!block_done) { continue; } - background_callback_add(&dma->callback, dma_callback_fun, (void*)dma); + background_callback_add(&dma->callback, dma_callback_fun, (void *)dma); } } #ifdef SAM_D5X_E5X -void EVSYS_0_Handler(void) { evsyshandler_common(); } -void EVSYS_1_Handler(void) { evsyshandler_common(); } -void EVSYS_2_Handler(void) { evsyshandler_common(); } -void EVSYS_3_Handler(void) { evsyshandler_common(); } -void EVSYS_4_Handler(void) { evsyshandler_common(); } +void EVSYS_0_Handler(void) { + evsyshandler_common(); +} +void EVSYS_1_Handler(void) { + evsyshandler_common(); +} +void EVSYS_2_Handler(void) { + evsyshandler_common(); +} +void EVSYS_3_Handler(void) { + evsyshandler_common(); +} +void EVSYS_4_Handler(void) { + evsyshandler_common(); +} #else -void EVSYS_Handler(void) { evsyshandler_common(); } +void EVSYS_Handler(void) { + evsyshandler_common(); +} #endif #endif diff --git a/ports/atmel-samd/audio_dma.h b/ports/atmel-samd/audio_dma.h index 4fffd06b8..5506cff62 100644 --- a/ports/atmel-samd/audio_dma.h +++ b/ports/atmel-samd/audio_dma.h @@ -46,10 +46,10 @@ typedef struct { bool signed_to_unsigned; bool unsigned_to_signed; bool first_buffer_free; - uint8_t* first_buffer; - uint8_t* second_buffer; + uint8_t *first_buffer; + uint8_t *second_buffer; bool first_descriptor_free; - DmacDescriptor* second_descriptor; + DmacDescriptor *second_descriptor; background_callback_t callback; } audio_dma_t; @@ -63,7 +63,7 @@ uint32_t audiosample_sample_rate(mp_obj_t sample_obj); uint8_t audiosample_bits_per_sample(mp_obj_t sample_obj); uint8_t audiosample_channel_count(mp_obj_t sample_obj); -void audio_dma_init(audio_dma_t* dma); +void audio_dma_init(audio_dma_t *dma); void audio_dma_reset(void); uint8_t audio_dma_allocate_channel(void); @@ -78,22 +78,22 @@ void audio_dma_free_channel(uint8_t channel); // output_signed is true if the dma'd data should be signed. False and it will be unsigned. // output_register_address is the address to copy data to. // dma_trigger_source is the DMA trigger source which cause another copy -audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, - mp_obj_t sample, - bool loop, - bool single_channel, - uint8_t audio_channel, - bool output_signed, - uint32_t output_register_address, - uint8_t dma_trigger_source); +audio_dma_result audio_dma_setup_playback(audio_dma_t *dma, + mp_obj_t sample, + bool loop, + bool single_channel, + uint8_t audio_channel, + bool output_signed, + uint32_t output_register_address, + uint8_t dma_trigger_source); void audio_dma_disable_channel(uint8_t channel); void audio_dma_enable_channel(uint8_t channel); -void audio_dma_stop(audio_dma_t* dma); -bool audio_dma_get_playing(audio_dma_t* dma); -void audio_dma_pause(audio_dma_t* dma); -void audio_dma_resume(audio_dma_t* dma); -bool audio_dma_get_paused(audio_dma_t* dma); +void audio_dma_stop(audio_dma_t *dma); +bool audio_dma_get_playing(audio_dma_t *dma); +void audio_dma_pause(audio_dma_t *dma); +void audio_dma_resume(audio_dma_t *dma); +bool audio_dma_get_paused(audio_dma_t *dma); void audio_dma_background(void); diff --git a/ports/atmel-samd/background.c b/ports/atmel-samd/background.c index 62c233a3f..237395b6b 100644 --- a/ports/atmel-samd/background.c +++ b/ports/atmel-samd/background.c @@ -44,16 +44,19 @@ // so you can't use this code AND an i2c peripheral // at the same time unless you change this void port_start_background_task(void) { - REG_PORT_DIRSET1 = (1<<3); - REG_PORT_OUTSET1 = (1<<3); + REG_PORT_DIRSET1 = (1 << 3); + REG_PORT_OUTSET1 = (1 << 3); } void port_finish_background_task(void) { - REG_PORT_OUTCLR1 = (1<<3); + REG_PORT_OUTCLR1 = (1 << 3); } #else -void port_start_background_task(void) {} -void port_finish_background_task(void) {} +void port_start_background_task(void) { +} +void port_finish_background_task(void) { +} #endif -void port_background_task(void) {} +void port_background_task(void) { +} diff --git a/ports/atmel-samd/bindings/samd/Clock.c b/ports/atmel-samd/bindings/samd/Clock.c index 478a10fcd..9375a7a84 100644 --- a/ports/atmel-samd/bindings/samd/Clock.c +++ b/ports/atmel-samd/bindings/samd/Clock.c @@ -57,8 +57,7 @@ const mp_obj_property_t samd_clock_enabled_obj = { .base.type = &mp_type_property, .proxy = {(mp_obj_t)&samd_clock_get_enabled_obj, (mp_obj_t)&mp_const_none_obj, - (mp_obj_t)&mp_const_none_obj, - }, + (mp_obj_t)&mp_const_none_obj,}, }; //| parent: Union[Clock, None] @@ -67,14 +66,16 @@ const mp_obj_property_t samd_clock_enabled_obj = { STATIC mp_obj_t samd_clock_get_parent(mp_obj_t self_in) { samd_clock_obj_t *self = MP_OBJ_TO_PTR(self_in); uint8_t p_type, p_index; - if (!clock_get_parent(self->type, self->index, &p_type, &p_index)) + if (!clock_get_parent(self->type, self->index, &p_type, &p_index)) { return mp_const_none; + } - const mp_map_t* samd_map = &samd_clock_globals.map; + const mp_map_t *samd_map = &samd_clock_globals.map; for (uint8_t i = 0; i < samd_map->alloc; i++) { samd_clock_obj_t *iter = samd_map->table[i].value; - if (iter->type == p_type && iter->index == p_index) + if (iter->type == p_type && iter->index == p_index) { return iter; + } } return mp_const_none; } @@ -85,8 +86,7 @@ const mp_obj_property_t samd_clock_parent_obj = { .base.type = &mp_type_property, .proxy = {(mp_obj_t)&samd_clock_get_parent_obj, (mp_obj_t)&mp_const_none_obj, - (mp_obj_t)&mp_const_none_obj, - }, + (mp_obj_t)&mp_const_none_obj,}, }; //| frequency: int @@ -103,8 +103,7 @@ const mp_obj_property_t samd_clock_frequency_obj = { .base.type = &mp_type_property, .proxy = {(mp_obj_t)&samd_clock_get_frequency_obj, (mp_obj_t)&mp_const_none_obj, - (mp_obj_t)&mp_const_none_obj, - }, + (mp_obj_t)&mp_const_none_obj,}, }; //| calibration: int @@ -120,10 +119,12 @@ MP_DEFINE_CONST_FUN_OBJ_1(samd_clock_get_calibration_obj, samd_clock_get_calibra STATIC mp_obj_t samd_clock_set_calibration(mp_obj_t self_in, mp_obj_t calibration) { samd_clock_obj_t *self = MP_OBJ_TO_PTR(self_in); int ret = clock_set_calibration(self->type, self->index, mp_obj_get_int(calibration)); - if (ret == -2) + if (ret == -2) { mp_raise_AttributeError(translate("calibration is read only")); - if (ret == -1) + } + if (ret == -1) { mp_raise_ValueError(translate("calibration is out of range")); + } return mp_const_none; } @@ -133,8 +134,7 @@ const mp_obj_property_t samd_clock_calibration_obj = { .base.type = &mp_type_property, .proxy = {(mp_obj_t)&samd_clock_get_calibration_obj, (mp_obj_t)&samd_clock_set_calibration_obj, - (mp_obj_t)&mp_const_none_obj, - }, + (mp_obj_t)&mp_const_none_obj,}, }; STATIC const mp_rom_map_elem_t samd_clock_locals_dict_table[] = { @@ -212,15 +212,15 @@ CLOCK(SYSTICK, 2, 0); #endif STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = { -#ifdef SAMD21_EXPOSE_ALL_CLOCKS + #ifdef SAMD21_EXPOSE_ALL_CLOCKS CLOCK_ENTRY(XOSC), CLOCK_ENTRY(GCLKIN), CLOCK_ENTRY(GCLKGEN1), CLOCK_ENTRY(OSCULP32K), -#endif + #endif CLOCK_ENTRY(OSC32K), CLOCK_ENTRY(XOSC32K), -#ifdef SAMD21_EXPOSE_ALL_CLOCKS + #ifdef SAMD21_EXPOSE_ALL_CLOCKS CLOCK_ENTRY(OSC8M), CLOCK_ENTRY(DFLL48M), CLOCK_ENTRY(DPLL96M), @@ -228,9 +228,9 @@ STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = { CLOCK_ENTRY_(SYSCTRL, FDPLL), CLOCK_ENTRY_(SYSCTRL, FDPLL32K), CLOCK_ENTRY(WDT), -#endif + #endif CLOCK_ENTRY(RTC), -#ifdef SAMD21_EXPOSE_ALL_CLOCKS + #ifdef SAMD21_EXPOSE_ALL_CLOCKS CLOCK_ENTRY(EIC), CLOCK_ENTRY(USB), CLOCK_ENTRY_(EVSYS, 0), @@ -265,7 +265,7 @@ STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = { CLOCK_ENTRY_(I2S, 1), CLOCK_ENTRY(SYSTICK), -#endif + #endif }; MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table); diff --git a/ports/atmel-samd/bindings/samd/Clock.h b/ports/atmel-samd/bindings/samd/Clock.h index ccc8f10d1..a4c11556b 100644 --- a/ports/atmel-samd/bindings/samd/Clock.h +++ b/ports/atmel-samd/bindings/samd/Clock.h @@ -37,39 +37,39 @@ typedef struct { } samd_clock_obj_t; #define CLOCK(_name, _type, _index) \ -const samd_clock_obj_t clock_ ## _name = { \ - { &samd_clock_type }, \ - .name = MP_QSTR_ ## _name, \ - .type = _type, \ - .index = _index, \ -} + const samd_clock_obj_t clock_##_name = { \ + { &samd_clock_type }, \ + .name = MP_QSTR_##_name, \ + .type = _type, \ + .index = _index, \ + } #define CLOCK_SOURCE(_name) \ -const samd_clock_obj_t clock_ ## _name = { \ - { &samd_clock_type }, \ - .name = MP_QSTR_ ## _name, \ - .type = 0, \ - .index = GCLK_SOURCE_ ## _name, \ -} + const samd_clock_obj_t clock_##_name = { \ + { &samd_clock_type }, \ + .name = MP_QSTR_##_name, \ + .type = 0, \ + .index = GCLK_SOURCE_##_name, \ + } #define CLOCK_GCLK(_name) \ -const samd_clock_obj_t clock_ ## _name = { \ - { &samd_clock_type }, \ - .name = MP_QSTR_ ## _name, \ - .type = 1, \ - .index = _name ## _GCLK_ID, \ -} + const samd_clock_obj_t clock_##_name = { \ + { &samd_clock_type }, \ + .name = MP_QSTR_##_name, \ + .type = 1, \ + .index = _name##_GCLK_ID, \ + } #define CLOCK_GCLK_(_name, _extra) \ -const samd_clock_obj_t clock_ ## _name ## _ ## _extra = { \ - { &samd_clock_type }, \ - .name = MP_QSTR_ ## _name ## _ ## _extra, \ - .type = 1, \ - .index = _name ## _GCLK_ID_ ## _extra, \ -} + const samd_clock_obj_t clock_##_name##_##_extra = { \ + { &samd_clock_type }, \ + .name = MP_QSTR_##_name##_##_extra, \ + .type = 1, \ + .index = _name##_GCLK_ID_##_extra, \ + } -#define CLOCK_ENTRY(_name) { MP_ROM_QSTR(MP_QSTR_ ## _name), MP_ROM_PTR(&clock_ ## _name) } -#define CLOCK_ENTRY_(_name, _extra) { MP_ROM_QSTR(MP_QSTR_ ## _name ## _ ## _extra), MP_ROM_PTR(&clock_ ## _name ## _ ## _extra) } +#define CLOCK_ENTRY(_name) { MP_ROM_QSTR(MP_QSTR_##_name), MP_ROM_PTR(&clock_##_name) } +#define CLOCK_ENTRY_(_name, _extra) { MP_ROM_QSTR(MP_QSTR_##_name##_##_extra), MP_ROM_PTR(&clock_##_name##_##_extra) } extern const mp_obj_type_t samd_clock_type; extern const mp_obj_dict_t samd_clock_globals; diff --git a/ports/atmel-samd/bindings/samd/__init__.c b/ports/atmel-samd/bindings/samd/__init__.c index 6e9b68ccc..207a6d52e 100644 --- a/ports/atmel-samd/bindings/samd/__init__.c +++ b/ports/atmel-samd/bindings/samd/__init__.c @@ -43,7 +43,7 @@ //| const mp_obj_module_t samd_clock_module = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&samd_clock_globals, + .globals = (mp_obj_dict_t *)&samd_clock_globals, }; STATIC const mp_rom_map_elem_t samd_module_globals_table[] = { @@ -55,5 +55,5 @@ STATIC MP_DEFINE_CONST_DICT(samd_module_globals, samd_module_globals_table); const mp_obj_module_t samd_module = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&samd_module_globals, + .globals = (mp_obj_dict_t *)&samd_module_globals, }; diff --git a/ports/atmel-samd/boards/8086_commander/mpconfigboard.h b/ports/atmel-samd/boards/8086_commander/mpconfigboard.h index 9e3be4e6a..0b5d3a267 100644 --- a/ports/atmel-samd/boards/8086_commander/mpconfigboard.h +++ b/ports/atmel-samd/boards/8086_commander/mpconfigboard.h @@ -6,9 +6,9 @@ #define MICROPY_HW_LED_STATUS (&pin_PA06) -#define MICROPY_PORT_A (0) -#define MICROPY_PORT_B (0) -#define MICROPY_PORT_C (0) +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) // USB is always used internally so skip the pin objects for it. #define IGNORE_PIN_PA24 1 diff --git a/ports/atmel-samd/boards/aloriumtech_evo_m51/board.c b/ports/atmel-samd/boards/aloriumtech_evo_m51/board.c index 5973eeec1..c67701512 100644 --- a/ports/atmel-samd/boards/aloriumtech_evo_m51/board.c +++ b/ports/atmel-samd/boards/aloriumtech_evo_m51/board.c @@ -32,21 +32,20 @@ #include "mpconfigboard.h" void board_init(void) { - REG_PORT_DIRSET1 = PORT_PB20; // PB20 as output - REG_PORT_OUTCLR1 = PORT_PB20; // PB20 cleared - PORT->Group[1].PINCFG[20].reg |= PORT_PINCFG_PMUXEN; // Mux enabled on PB20 - PORT->Group[1].PMUX[10].reg = 0x0C; // PB20 as mux function "M" - // Gclk[6] is on PB20 - GCLK->GENCTRL[6].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL0) | - GCLK_GENCTRL_IDC | - GCLK_GENCTRL_DIV(10) | - //GCLK_GENCTRL_DIVSEL | - GCLK_GENCTRL_OE | - GCLK_GENCTRL_GENEN; - while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) - { - // Wait for synchronization - } + REG_PORT_DIRSET1 = PORT_PB20; // PB20 as output + REG_PORT_OUTCLR1 = PORT_PB20; // PB20 cleared + PORT->Group[1].PINCFG[20].reg |= PORT_PINCFG_PMUXEN; // Mux enabled on PB20 + PORT->Group[1].PMUX[10].reg = 0x0C; // PB20 as mux function "M" + // Gclk[6] is on PB20 + GCLK->GENCTRL[6].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL0) | + GCLK_GENCTRL_IDC | + GCLK_GENCTRL_DIV(10) | + // GCLK_GENCTRL_DIVSEL | + GCLK_GENCTRL_OE | + GCLK_GENCTRL_GENEN; + while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) { + // Wait for synchronization + } } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/aloriumtech_evo_m51/mpconfigboard.h b/ports/atmel-samd/boards/aloriumtech_evo_m51/mpconfigboard.h index cafc82605..3882c2b6d 100644 --- a/ports/atmel-samd/boards/aloriumtech_evo_m51/mpconfigboard.h +++ b/ports/atmel-samd/boards/aloriumtech_evo_m51/mpconfigboard.h @@ -17,21 +17,21 @@ #define MICROPY_PORT_D (0) // BC needed? -//#define AUTORESET_DELAY_MS 500 +// #define AUTORESET_DELAY_MS 500 // If you change this, then make sure to update the linker scripts as well to // make sure you don't overwrite code -//#define CIRCUITPY_INTERNAL_NVM_SIZE 8192 +// #define CIRCUITPY_INTERNAL_NVM_SIZE 8192 -//#define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000 - CIRCUITPY_INTERNAL_NVM_SIZE) +// #define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000 - CIRCUITPY_INTERNAL_NVM_SIZE) // End BC #define EXTERNAL_FLASH_QSPI_DUAL #define BOARD_HAS_CRYSTAL 1 -//#define DEFAULT_I2C_BUS_SCL (&pin_PA13) -//#define DEFAULT_I2C_BUS_SDA (&pin_PA12) +// #define DEFAULT_I2C_BUS_SCL (&pin_PA13) +// #define DEFAULT_I2C_BUS_SDA (&pin_PA12) #define DEFAULT_I2C_BUS_SCL (&pin_PA13) #define DEFAULT_I2C_BUS_SDA (&pin_PA12) diff --git a/ports/atmel-samd/boards/arduino_mkr1300/board.c b/ports/atmel-samd/boards/arduino_mkr1300/board.c index 112b173ec..7af05ba45 100644 --- a/ports/atmel-samd/boards/arduino_mkr1300/board.c +++ b/ports/atmel-samd/boards/arduino_mkr1300/board.c @@ -28,8 +28,7 @@ #include "mpconfigboard.h" #include "hal/include/hal_gpio.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/arduino_nano_33_iot/board.c b/ports/atmel-samd/boards/arduino_nano_33_iot/board.c index 112b173ec..7af05ba45 100644 --- a/ports/atmel-samd/boards/arduino_nano_33_iot/board.c +++ b/ports/atmel-samd/boards/arduino_nano_33_iot/board.c @@ -28,8 +28,7 @@ #include "mpconfigboard.h" #include "hal/include/hal_gpio.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/arduino_zero/board.c b/ports/atmel-samd/boards/arduino_zero/board.c index 112b173ec..7af05ba45 100644 --- a/ports/atmel-samd/boards/arduino_zero/board.c +++ b/ports/atmel-samd/boards/arduino_zero/board.c @@ -28,8 +28,7 @@ #include "mpconfigboard.h" #include "hal/include/hal_gpio.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/bast_pro_mini_m0/board.c b/ports/atmel-samd/boards/bast_pro_mini_m0/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/bast_pro_mini_m0/board.c +++ b/ports/atmel-samd/boards/bast_pro_mini_m0/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/bdmicro_vina_d21/board.c b/ports/atmel-samd/boards/bdmicro_vina_d21/board.c index bb1c5335c..bb6ad8bc0 100644 --- a/ports/atmel-samd/boards/bdmicro_vina_d21/board.c +++ b/ports/atmel-samd/boards/bdmicro_vina_d21/board.c @@ -27,8 +27,7 @@ #include "supervisor/board.h" #include "mpconfigboard.h" -void board_init(void) -{ +void board_init(void) { // struct port_config pin_conf; // port_get_config_defaults(&pin_conf); // diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/board.c b/ports/atmel-samd/boards/bdmicro_vina_d51/board.c index bb1c5335c..bb6ad8bc0 100644 --- a/ports/atmel-samd/boards/bdmicro_vina_d51/board.c +++ b/ports/atmel-samd/boards/bdmicro_vina_d51/board.c @@ -27,8 +27,7 @@ #include "supervisor/board.h" #include "mpconfigboard.h" -void board_init(void) -{ +void board_init(void) { // struct port_config pin_conf; // port_get_config_defaults(&pin_conf); // diff --git a/ports/atmel-samd/boards/catwan_usbstick/board.c b/ports/atmel-samd/boards/catwan_usbstick/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/catwan_usbstick/board.c +++ b/ports/atmel-samd/boards/catwan_usbstick/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/circuitbrains_basic_m0/pins.c b/ports/atmel-samd/boards/circuitbrains_basic_m0/pins.c index 5acad5e98..5acad5e98 100755..100644 --- a/ports/atmel-samd/boards/circuitbrains_basic_m0/pins.c +++ b/ports/atmel-samd/boards/circuitbrains_basic_m0/pins.c diff --git a/ports/atmel-samd/boards/circuitplayground_express/board.c b/ports/atmel-samd/boards/circuitplayground_express/board.c index f771c214b..39e39b0d4 100644 --- a/ports/atmel-samd/boards/circuitplayground_express/board.c +++ b/ports/atmel-samd/boards/circuitplayground_express/board.c @@ -31,8 +31,7 @@ #include "supervisor/shared/board.h" #include "hal/include/hal_gpio.h" -void board_init(void) -{ +void board_init(void) { } // Check the status of the two buttons on CircuitPlayground Express. If both are diff --git a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h index e46e477e4..a32133e35 100644 --- a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h +++ b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h @@ -28,7 +28,7 @@ #define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n") // Increase stack size slightly due to CPX library import nesting -#define CIRCUITPY_DEFAULT_STACK_SIZE (4248) //divisible by 8 +#define CIRCUITPY_DEFAULT_STACK_SIZE (4248) // divisible by 8 #define DEFAULT_I2C_BUS_SCL (&pin_PB03) #define DEFAULT_I2C_BUS_SDA (&pin_PB02) diff --git a/ports/atmel-samd/boards/circuitplayground_express_crickit/board.c b/ports/atmel-samd/boards/circuitplayground_express_crickit/board.c index 13fed598e..4666482e9 100644 --- a/ports/atmel-samd/boards/circuitplayground_express_crickit/board.c +++ b/ports/atmel-samd/boards/circuitplayground_express_crickit/board.c @@ -31,8 +31,7 @@ #include "hal/include/hal_gpio.h" #include "supervisor/shared/board.h" -void board_init(void) -{ +void board_init(void) { } // Check the status of the two buttons on CircuitPlayground Express. If both are diff --git a/ports/atmel-samd/boards/circuitplayground_express_displayio/board.c b/ports/atmel-samd/boards/circuitplayground_express_displayio/board.c index 13fed598e..4666482e9 100644 --- a/ports/atmel-samd/boards/circuitplayground_express_displayio/board.c +++ b/ports/atmel-samd/boards/circuitplayground_express_displayio/board.c @@ -31,8 +31,7 @@ #include "hal/include/hal_gpio.h" #include "supervisor/shared/board.h" -void board_init(void) -{ +void board_init(void) { } // Check the status of the two buttons on CircuitPlayground Express. If both are diff --git a/ports/atmel-samd/boards/cp32-m4/mpconfigboard.h b/ports/atmel-samd/boards/cp32-m4/mpconfigboard.h index 8664a6a0e..bdc44c79b 100644 --- a/ports/atmel-samd/boards/cp32-m4/mpconfigboard.h +++ b/ports/atmel-samd/boards/cp32-m4/mpconfigboard.h @@ -7,8 +7,8 @@ #define CIRCUITPY_MCU_FAMILY samd51 -#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11| PORT_PA12| PORT_PA13) -#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11) +#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 | PORT_PA12 | PORT_PA13) +#define MICROPY_PORT_B (PORT_PB10 | PORT_PB11) #define MICROPY_PORT_C (0) #define MICROPY_PORT_D (0) diff --git a/ports/atmel-samd/boards/cp_sapling_m0/mpconfigboard.h b/ports/atmel-samd/boards/cp_sapling_m0/mpconfigboard.h index c67f022eb..b04a31c46 100644 --- a/ports/atmel-samd/boards/cp_sapling_m0/mpconfigboard.h +++ b/ports/atmel-samd/boards/cp_sapling_m0/mpconfigboard.h @@ -7,15 +7,15 @@ #define MICROPY_PORT_B (0) #define MICROPY_PORT_C (0) -#define IGNORE_PIN_PA02 1 -#define IGNORE_PIN_PA03 1 -#define IGNORE_PIN_PA04 1 -#define IGNORE_PIN_PA05 1 -#define IGNORE_PIN_PA06 1 -#define IGNORE_PIN_PA07 1 +#define IGNORE_PIN_PA02 1 +#define IGNORE_PIN_PA03 1 +#define IGNORE_PIN_PA04 1 +#define IGNORE_PIN_PA05 1 +#define IGNORE_PIN_PA06 1 +#define IGNORE_PIN_PA07 1 #define IGNORE_PIN_PA12 1 #define IGNORE_PIN_PA13 1 -#define IGNORE_PIN_PA14 1 +#define IGNORE_PIN_PA14 1 #define IGNORE_PIN_PA20 1 #define IGNORE_PIN_PA21 1 // USB is always used internally so skip the pin objects for it. diff --git a/ports/atmel-samd/boards/cp_sapling_m0_spiflash/mpconfigboard.h b/ports/atmel-samd/boards/cp_sapling_m0_spiflash/mpconfigboard.h index 9c69c4802..528d989ed 100644 --- a/ports/atmel-samd/boards/cp_sapling_m0_spiflash/mpconfigboard.h +++ b/ports/atmel-samd/boards/cp_sapling_m0_spiflash/mpconfigboard.h @@ -12,15 +12,15 @@ #define SPI_FLASH_SCK_PIN &pin_PA19 #define SPI_FLASH_CS_PIN &pin_PA22 -#define IGNORE_PIN_PA02 1 -#define IGNORE_PIN_PA03 1 -#define IGNORE_PIN_PA04 1 -#define IGNORE_PIN_PA05 1 -#define IGNORE_PIN_PA06 1 -#define IGNORE_PIN_PA07 1 +#define IGNORE_PIN_PA02 1 +#define IGNORE_PIN_PA03 1 +#define IGNORE_PIN_PA04 1 +#define IGNORE_PIN_PA05 1 +#define IGNORE_PIN_PA06 1 +#define IGNORE_PIN_PA07 1 #define IGNORE_PIN_PA12 1 #define IGNORE_PIN_PA13 1 -#define IGNORE_PIN_PA14 1 +#define IGNORE_PIN_PA14 1 #define IGNORE_PIN_PA20 1 #define IGNORE_PIN_PA21 1 // USB is always used internally so skip the pin objects for it. diff --git a/ports/atmel-samd/boards/datum_distance/board.c b/ports/atmel-samd/boards/datum_distance/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/datum_distance/board.c +++ b/ports/atmel-samd/boards/datum_distance/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/datum_imu/board.c b/ports/atmel-samd/boards/datum_imu/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/datum_imu/board.c +++ b/ports/atmel-samd/boards/datum_imu/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/datum_light/board.c b/ports/atmel-samd/boards/datum_light/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/datum_light/board.c +++ b/ports/atmel-samd/boards/datum_light/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/datum_weather/board.c b/ports/atmel-samd/boards/datum_weather/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/datum_weather/board.c +++ b/ports/atmel-samd/boards/datum_weather/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/board.c b/ports/atmel-samd/boards/dynossat_edu_eps/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/dynossat_edu_eps/board.c +++ b/ports/atmel-samd/boards/dynossat_edu_eps/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h index ef4fa8f99..02707a69d 100644 --- a/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h +++ b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h @@ -9,9 +9,9 @@ #define SPI_FLASH_CS_PIN &pin_PA20 // These are pins not to reset. -#define MICROPY_PORT_A ( 0 ) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define BOARD_HAS_CRYSTAL 1 @@ -28,7 +28,7 @@ // USB is always used internally so skip the pin objects for it. #define IGNORE_PIN_PA24 1 #define IGNORE_PIN_PA25 1 -#define IGNORE_PIN_PA03 1 +#define IGNORE_PIN_PA03 1 #define IGNORE_PIN_PA13 1 #define IGNORE_PIN_PA14 1 #define IGNORE_PIN_PA15 1 diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/board.c b/ports/atmel-samd/boards/dynossat_edu_obc/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/dynossat_edu_obc/board.c +++ b/ports/atmel-samd/boards/dynossat_edu_obc/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h index d7df8db74..102a8cfb6 100644 --- a/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h +++ b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h @@ -9,10 +9,10 @@ #define SPI_FLASH_CS_PIN &pin_PA19 // These are pins not to reset. -#define MICROPY_PORT_A ( PORT_PA16 | PORT_PA17 | PORT_PA18 | PORT_PA19 ) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) -#define MICROPY_PORT_D ( 0 ) +#define MICROPY_PORT_A (PORT_PA16 | PORT_PA17 | PORT_PA18 | PORT_PA19) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) +#define MICROPY_PORT_D (0) #define BOARD_HAS_CRYSTAL 1 diff --git a/ports/atmel-samd/boards/escornabot_makech/board.c b/ports/atmel-samd/boards/escornabot_makech/board.c index 5afe2fb65..76849c53e 100644 --- a/ports/atmel-samd/boards/escornabot_makech/board.c +++ b/ports/atmel-samd/boards/escornabot_makech/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/escornabot_makech/pins.c b/ports/atmel-samd/boards/escornabot_makech/pins.c index fefee1919..86a70cb04 100644 --- a/ports/atmel-samd/boards/escornabot_makech/pins.c +++ b/ports/atmel-samd/boards/escornabot_makech/pins.c @@ -1,7 +1,7 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_global_dict_table[] = { - //LEDs + // LEDs { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) }, { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA04) }, { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA05) }, @@ -31,7 +31,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA09) }, { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA13) }, - //UART + // UART { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA01) }, { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA00) }, diff --git a/ports/atmel-samd/boards/feather_m0_adalogger/board.c b/ports/atmel-samd/boards/feather_m0_adalogger/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/feather_m0_adalogger/board.c +++ b/ports/atmel-samd/boards/feather_m0_adalogger/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/feather_m0_basic/board.c b/ports/atmel-samd/boards/feather_m0_basic/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/feather_m0_basic/board.c +++ b/ports/atmel-samd/boards/feather_m0_basic/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/feather_m0_express/board.c b/ports/atmel-samd/boards/feather_m0_express/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/feather_m0_express/board.c +++ b/ports/atmel-samd/boards/feather_m0_express/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/feather_m0_express/mpconfigboard.h b/ports/atmel-samd/boards/feather_m0_express/mpconfigboard.h index 5421dc889..27ea6c72b 100644 --- a/ports/atmel-samd/boards/feather_m0_express/mpconfigboard.h +++ b/ports/atmel-samd/boards/feather_m0_express/mpconfigboard.h @@ -12,8 +12,8 @@ // These are pins not to reset. #define MICROPY_PORT_A (PORT_PA06) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define BOARD_HAS_CRYSTAL 1 diff --git a/ports/atmel-samd/boards/feather_m0_express_crickit/board.c b/ports/atmel-samd/boards/feather_m0_express_crickit/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/feather_m0_express_crickit/board.c +++ b/ports/atmel-samd/boards/feather_m0_express_crickit/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.h b/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.h index ee61e1d87..112dd80fa 100644 --- a/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.h +++ b/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.h @@ -12,8 +12,8 @@ // These are pins not to reset. #define MICROPY_PORT_A (PORT_PA06) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define BOARD_HAS_CRYSTAL 1 diff --git a/ports/atmel-samd/boards/feather_m0_rfm69/board.c b/ports/atmel-samd/boards/feather_m0_rfm69/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/feather_m0_rfm69/board.c +++ b/ports/atmel-samd/boards/feather_m0_rfm69/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/feather_m0_rfm9x/board.c b/ports/atmel-samd/boards/feather_m0_rfm9x/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/feather_m0_rfm9x/board.c +++ b/ports/atmel-samd/boards/feather_m0_rfm9x/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/feather_m0_supersized/board.c b/ports/atmel-samd/boards/feather_m0_supersized/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/feather_m0_supersized/board.c +++ b/ports/atmel-samd/boards/feather_m0_supersized/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/feather_m0_supersized/mpconfigboard.h b/ports/atmel-samd/boards/feather_m0_supersized/mpconfigboard.h index 2d9f88e2e..9fa2ba9ce 100644 --- a/ports/atmel-samd/boards/feather_m0_supersized/mpconfigboard.h +++ b/ports/atmel-samd/boards/feather_m0_supersized/mpconfigboard.h @@ -14,8 +14,8 @@ // These are pins not to reset. #define MICROPY_PORT_A (PORT_PA06) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define DEFAULT_I2C_BUS_SCL (&pin_PA23) #define DEFAULT_I2C_BUS_SDA (&pin_PA22) diff --git a/ports/atmel-samd/boards/feather_radiofruit_zigbee/board.c b/ports/atmel-samd/boards/feather_radiofruit_zigbee/board.c index 6baa43ffa..84960e73c 100755..100644 --- a/ports/atmel-samd/boards/feather_radiofruit_zigbee/board.c +++ b/ports/atmel-samd/boards/feather_radiofruit_zigbee/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.h b/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.h index 2afe35817..b1839f2c9 100755..100644 --- a/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.h +++ b/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.h @@ -11,8 +11,8 @@ // These are pins not to reset. #define MICROPY_PORT_A (PORT_PA22) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define BOARD_HAS_CRYSTAL 1 diff --git a/ports/atmel-samd/boards/fluff_m0/board.c b/ports/atmel-samd/boards/fluff_m0/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/fluff_m0/board.c +++ b/ports/atmel-samd/boards/fluff_m0/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/gemma_m0/board.c b/ports/atmel-samd/boards/gemma_m0/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/gemma_m0/board.c +++ b/ports/atmel-samd/boards/gemma_m0/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/grandcentral_m4_express/mpconfigboard.h b/ports/atmel-samd/boards/grandcentral_m4_express/mpconfigboard.h index bab055014..f2f3d7cc4 100644 --- a/ports/atmel-samd/boards/grandcentral_m4_express/mpconfigboard.h +++ b/ports/atmel-samd/boards/grandcentral_m4_express/mpconfigboard.h @@ -14,11 +14,11 @@ // These are pins not to reset. // QSPI Data pins -#define MICROPY_PORT_A ( PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 ) +#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) // QSPI CS, and QSPI SCK -#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11 ) +#define MICROPY_PORT_B (PORT_PB10 | PORT_PB11) // NeoPixel pin, RX LED, TX LED -#define MICROPY_PORT_C ( PORT_PC24 | PORT_PC30 | PORT_PC31 ) +#define MICROPY_PORT_C (PORT_PC24 | PORT_PC30 | PORT_PC31) #define MICROPY_PORT_D (0) #define BOARD_HAS_CRYSTAL 1 diff --git a/ports/atmel-samd/boards/hallowing_m0_express/board.c b/ports/atmel-samd/boards/hallowing_m0_express/board.c index 8b922d6be..a9c11f1ba 100644 --- a/ports/atmel-samd/boards/hallowing_m0_express/board.c +++ b/ports/atmel-samd/boards/hallowing_m0_express/board.c @@ -55,13 +55,13 @@ uint8_t display_init_sequence[] = { // fix on VTL 0x3a, 1, 0x05, // COLMOD - 16bit color 0xe0, 16, 0x02, 0x1c, 0x07, 0x12, // _GMCTRP1 Gamma - 0x37, 0x32, 0x29, 0x2d, - 0x29, 0x25, 0x2B, 0x39, - 0x00, 0x01, 0x03, 0x10, + 0x37, 0x32, 0x29, 0x2d, + 0x29, 0x25, 0x2B, 0x39, + 0x00, 0x01, 0x03, 0x10, 0xe1, 16, 0x03, 0x1d, 0x07, 0x06, // _GMCTRN1 - 0x2E, 0x2C, 0x29, 0x2D, - 0x2E, 0x2E, 0x37, 0x3F, - 0x00, 0x00, 0x02, 0x10, + 0x2E, 0x2C, 0x29, 0x2D, + 0x2E, 0x2E, 0x37, 0x3F, + 0x00, 0x00, 0x02, 0x10, 0x2a, 3, 0x02, 0x00, 0x81, // _CASET XSTART = 2, XEND = 129 0x2b, 3, 0x02, 0x00, 0x81, // _RASET XSTART = 2, XEND = 129 0x13, 0 | DELAY, 10, // _NORON @@ -69,7 +69,7 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; busio_spi_obj_t *spi = common_hal_board_create_spi(); common_hal_displayio_fourwire_construct(bus, @@ -81,7 +81,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.h b/ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.h index e5ac346da..28ce10811 100644 --- a/ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.h +++ b/ports/atmel-samd/boards/hallowing_m0_express/mpconfigboard.h @@ -11,10 +11,10 @@ // These are pins not to reset. // NeoPixel and for the display: Reset, Command or data, and Chip select -#define MICROPY_PORT_A ( PORT_PA01 | PORT_PA12 | PORT_PA27 | PORT_PA28) +#define MICROPY_PORT_A (PORT_PA01 | PORT_PA12 | PORT_PA27 | PORT_PA28) // Data and Clock for the display -#define MICROPY_PORT_B ( PORT_PB22 | PORT_PB23 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (PORT_PB22 | PORT_PB23) +#define MICROPY_PORT_C (0) #define DEFAULT_I2C_BUS_SCL (&pin_PA17) #define DEFAULT_I2C_BUS_SDA (&pin_PA16) diff --git a/ports/atmel-samd/boards/hallowing_m4_express/board.c b/ports/atmel-samd/boards/hallowing_m4_express/board.c index f51d4282d..f9cdbdbaf 100644 --- a/ports/atmel-samd/boards/hallowing_m4_express/board.c +++ b/ports/atmel-samd/boards/hallowing_m4_express/board.c @@ -47,11 +47,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PA01, &pin_PA00, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -62,7 +62,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.h b/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.h index 4d911ad64..0ac595edf 100644 --- a/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.h +++ b/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.h @@ -8,7 +8,7 @@ #define MICROPY_PORT_A (PORT_PA24 | PORT_PA25) #define MICROPY_PORT_B (0) #define MICROPY_PORT_C (0) -#define MICROPY_PORT_D (0) +#define MICROPY_PORT_D (0) #define CIRCUITPY_INTERNAL_NVM_SIZE 0 diff --git a/ports/atmel-samd/boards/kicksat-sprite/pins.c b/ports/atmel-samd/boards/kicksat-sprite/pins.c index 27ee90323..711406189 100644 --- a/ports/atmel-samd/boards/kicksat-sprite/pins.c +++ b/ports/atmel-samd/boards/kicksat-sprite/pins.c @@ -8,20 +8,20 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_radioCS), MP_ROM_PTR(&pin_PA00) }, { MP_ROM_QSTR(MP_QSTR_WAKE), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_SHDWN), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_SHDWN), MP_ROM_PTR(&pin_PB10) }, { MP_ROM_QSTR(MP_QSTR_PWDWN), MP_ROM_PTR(&pin_PB11) }, { MP_ROM_QSTR(MP_QSTR_TST), MP_ROM_PTR(&pin_PA11) }, { MP_ROM_QSTR(MP_QSTR_FSYNC), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_VCLK), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_VCLK), MP_ROM_PTR(&pin_PA14) }, { MP_ROM_QSTR(MP_QSTR_FSYNC), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_MD), MP_ROM_PTR(&pin_PA18) }, - { MP_ROM_QSTR(MP_QSTR_MC), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_MD), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_MC), MP_ROM_PTR(&pin_PA19) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_DAC0), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_DAC0), MP_ROM_PTR(&pin_PA02) }, { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB09) }, { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB08) }, diff --git a/ports/atmel-samd/boards/meowmeow/board.c b/ports/atmel-samd/boards/meowmeow/board.c index 5afe2fb65..76849c53e 100644 --- a/ports/atmel-samd/boards/meowmeow/board.c +++ b/ports/atmel-samd/boards/meowmeow/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/metro_m0_express/board.c b/ports/atmel-samd/boards/metro_m0_express/board.c index bb1c5335c..bb6ad8bc0 100644 --- a/ports/atmel-samd/boards/metro_m0_express/board.c +++ b/ports/atmel-samd/boards/metro_m0_express/board.c @@ -27,8 +27,7 @@ #include "supervisor/board.h" #include "mpconfigboard.h" -void board_init(void) -{ +void board_init(void) { // struct port_config pin_conf; // port_get_config_defaults(&pin_conf); // diff --git a/ports/atmel-samd/boards/monster_m4sk/board.c b/ports/atmel-samd/boards/monster_m4sk/board.c index 2b757d091..8ef0c6ff9 100644 --- a/ports/atmel-samd/boards/monster_m4sk/board.c +++ b/ports/atmel-samd/boards/monster_m4sk/board.c @@ -48,11 +48,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PA13, &pin_PA12, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -63,7 +63,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/nfc_copy_cat/board.c b/ports/atmel-samd/boards/nfc_copy_cat/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/nfc_copy_cat/board.c +++ b/ports/atmel-samd/boards/nfc_copy_cat/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/openbook_m4/board.c b/ports/atmel-samd/boards/openbook_m4/board.c index a110779a6..d8184da73 100644 --- a/ports/atmel-samd/boards/openbook_m4/board.c +++ b/ports/atmel-samd/boards/openbook_m4/board.c @@ -53,11 +53,11 @@ uint8_t stop_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PB13, &pin_PB15, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -68,7 +68,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_epaperdisplay_obj_t* display = &displays[0].epaper_display; + displayio_epaperdisplay_obj_t *display = &displays[0].epaper_display; display->base.type = &displayio_epaperdisplay_type; common_hal_displayio_epaperdisplay_construct(display, bus, diff --git a/ports/atmel-samd/boards/pewpew_m4/board.c b/ports/atmel-samd/boards/pewpew_m4/board.c index 26bd53cad..88c5bd969 100644 --- a/ports/atmel-samd/boards/pewpew_m4/board.c +++ b/ports/atmel-samd/boards/pewpew_m4/board.c @@ -57,8 +57,9 @@ uint32_t lookupCfg(uint32_t key, uint32_t defl) { } else { ptr += 4; while (*ptr) { - if (*ptr == key) + if (*ptr == key) { return ptr[1]; + } ptr += 2; } } @@ -84,23 +85,23 @@ uint8_t display_init_sequence[] = { // fix on VTL 0x3a, 1, 0x05, // COLMOD - 16bit color 0xe0, 16, 0x02, 0x1c, 0x07, 0x12, // _GMCTRP1 Gamma - 0x37, 0x32, 0x29, 0x2d, - 0x29, 0x25, 0x2B, 0x39, - 0x00, 0x01, 0x03, 0x10, + 0x37, 0x32, 0x29, 0x2d, + 0x29, 0x25, 0x2B, 0x39, + 0x00, 0x01, 0x03, 0x10, 0xe1, 16, 0x03, 0x1d, 0x07, 0x06, // _GMCTRN1 - 0x2E, 0x2C, 0x29, 0x2D, - 0x2E, 0x2E, 0x37, 0x3F, - 0x00, 0x00, 0x02, 0x10, + 0x2E, 0x2C, 0x29, 0x2D, + 0x2E, 0x2E, 0x37, 0x3F, + 0x00, 0x00, 0x02, 0x10, 0x13, 0 | DELAY, 10, // _NORON 0x29, 0 | DELAY, 100, // _DISPON }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PA13, &pin_PA15, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -114,7 +115,7 @@ void board_init(void) { uint32_t cfg0 = lookupCfg(CFG_DISPLAY_CFG0, 0x000000); uint32_t offX = (cfg0 >> 8) & 0xff; uint32_t offY = (cfg0 >> 16) & 0xff; - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/picoplanet/mpconfigboard.h b/ports/atmel-samd/boards/picoplanet/mpconfigboard.h index 61430e06c..30a9169e0 100644 --- a/ports/atmel-samd/boards/picoplanet/mpconfigboard.h +++ b/ports/atmel-samd/boards/picoplanet/mpconfigboard.h @@ -33,10 +33,10 @@ #define DEFAULT_SPI_BUS_SCK (&pin_PA17) #define DEFAULT_SPI_BUS_MOSI (&pin_PA16) -//#define CP_RGB_STATUS_R (&pin_PA06) -//#define CP_RGB_STATUS_G (&pin_PA05) -//#define CP_RGB_STATUS_B (&pin_PA07) -//#define CP_RGB_STATUS_INVERTED_PWM -//#define CP_RGB_STATUS_LED +// #define CP_RGB_STATUS_R (&pin_PA06) +// #define CP_RGB_STATUS_G (&pin_PA05) +// #define CP_RGB_STATUS_B (&pin_PA07) +// #define CP_RGB_STATUS_INVERTED_PWM +// #define CP_RGB_STATUS_LED #define MICROPY_HW_LED_STATUS (&pin_PA06) diff --git a/ports/atmel-samd/boards/pirkey_m0/board.c b/ports/atmel-samd/boards/pirkey_m0/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/pirkey_m0/board.c +++ b/ports/atmel-samd/boards/pirkey_m0/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/pybadge/board.c b/ports/atmel-samd/boards/pybadge/board.c index 188bf7bf6..4adf10710 100644 --- a/ports/atmel-samd/boards/pybadge/board.c +++ b/ports/atmel-samd/boards/pybadge/board.c @@ -56,13 +56,13 @@ uint8_t display_init_sequence[] = { // fix on VTL 0x3a, 1, 0x05, // COLMOD - 16bit color 0xe0, 16, 0x02, 0x1c, 0x07, 0x12, // _GMCTRP1 Gamma - 0x37, 0x32, 0x29, 0x2d, - 0x29, 0x25, 0x2B, 0x39, - 0x00, 0x01, 0x03, 0x10, + 0x37, 0x32, 0x29, 0x2d, + 0x29, 0x25, 0x2B, 0x39, + 0x00, 0x01, 0x03, 0x10, 0xe1, 16, 0x03, 0x1d, 0x07, 0x06, // _GMCTRN1 - 0x2E, 0x2C, 0x29, 0x2D, - 0x2E, 0x2E, 0x37, 0x3F, - 0x00, 0x00, 0x02, 0x10, + 0x2E, 0x2C, 0x29, 0x2D, + 0x2E, 0x2E, 0x37, 0x3F, + 0x00, 0x00, 0x02, 0x10, 0x2a, 3, 0x02, 0x00, 0x81, // _CASET XSTART = 2, XEND = 129 0x2b, 3, 0x02, 0x00, 0x81, // _RASET XSTART = 2, XEND = 129 0x13, 0 | DELAY, 10, // _NORON @@ -70,11 +70,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PB13, &pin_PB15, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -85,7 +85,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/pybadge_airlift/board.c b/ports/atmel-samd/boards/pybadge_airlift/board.c index de7eeda09..fe3549a64 100644 --- a/ports/atmel-samd/boards/pybadge_airlift/board.c +++ b/ports/atmel-samd/boards/pybadge_airlift/board.c @@ -48,11 +48,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PB13, &pin_PB15, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -63,7 +63,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/pybadge_airlift/pins.c b/ports/atmel-samd/boards/pybadge_airlift/pins.c index cdf8071da..cce9b0442 100644 --- a/ports/atmel-samd/boards/pybadge_airlift/pins.c +++ b/ports/atmel-samd/boards/pybadge_airlift/pins.c @@ -68,5 +68,6 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { {MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj)}, {MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj)}, - {MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].display)}}; + {MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].display)} +}; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/pycubed/board.c b/ports/atmel-samd/boards/pycubed/board.c index f092a8d20..2777b9031 100644 --- a/ports/atmel-samd/boards/pycubed/board.c +++ b/ports/atmel-samd/boards/pycubed/board.c @@ -37,10 +37,10 @@ nvm_bytearray_obj_t bootcnt = { .base = { .type = &nvm_bytearray_type - }, - .len = ( uint32_t) 8192, - .start_address = (uint8_t*) (0x00080000 - 8192) - }; + }, + .len = (uint32_t)8192, + .start_address = (uint8_t *)(0x00080000 - 8192) +}; void board_init(void) { diff --git a/ports/atmel-samd/boards/pycubed/mpconfigboard.h b/ports/atmel-samd/boards/pycubed/mpconfigboard.h index fc16e22b5..244f41da3 100644 --- a/ports/atmel-samd/boards/pycubed/mpconfigboard.h +++ b/ports/atmel-samd/boards/pycubed/mpconfigboard.h @@ -7,9 +7,9 @@ #define MICROPY_HW_NEOPIXEL (&pin_PA21) #define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) -#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11) +#define MICROPY_PORT_B (PORT_PB10 | PORT_PB11) #define MICROPY_PORT_C (0) -#define MICROPY_PORT_D (0) +#define MICROPY_PORT_D (0) #define AUTORESET_DELAY_MS 500 diff --git a/ports/atmel-samd/boards/pycubed_mram/board.c b/ports/atmel-samd/boards/pycubed_mram/board.c index f092a8d20..2777b9031 100644 --- a/ports/atmel-samd/boards/pycubed_mram/board.c +++ b/ports/atmel-samd/boards/pycubed_mram/board.c @@ -37,10 +37,10 @@ nvm_bytearray_obj_t bootcnt = { .base = { .type = &nvm_bytearray_type - }, - .len = ( uint32_t) 8192, - .start_address = (uint8_t*) (0x00080000 - 8192) - }; + }, + .len = (uint32_t)8192, + .start_address = (uint8_t *)(0x00080000 - 8192) +}; void board_init(void) { diff --git a/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.h b/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.h index e2a733025..0d49e1b00 100644 --- a/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.h +++ b/ports/atmel-samd/boards/pycubed_mram/mpconfigboard.h @@ -8,7 +8,7 @@ #define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) #define MICROPY_PORT_B (PORT_PA21 | PORT_PB10 | PORT_PB11) #define MICROPY_PORT_C (0) -#define MICROPY_PORT_D (0) +#define MICROPY_PORT_D (0) #define SPI_FLASH_WP_PIN &pin_PA10 #define SPI_FLASH_HOLD_PIN &pin_PA11 diff --git a/ports/atmel-samd/boards/pygamer/board.c b/ports/atmel-samd/boards/pygamer/board.c index 4614e347c..11e18f127 100644 --- a/ports/atmel-samd/boards/pygamer/board.c +++ b/ports/atmel-samd/boards/pygamer/board.c @@ -56,13 +56,13 @@ uint8_t display_init_sequence[] = { // fix on VTL 0x3a, 1, 0x05, // COLMOD - 16bit color 0xe0, 16, 0x02, 0x1c, 0x07, 0x12, // _GMCTRP1 Gamma - 0x37, 0x32, 0x29, 0x2d, - 0x29, 0x25, 0x2B, 0x39, - 0x00, 0x01, 0x03, 0x10, + 0x37, 0x32, 0x29, 0x2d, + 0x29, 0x25, 0x2B, 0x39, + 0x00, 0x01, 0x03, 0x10, 0xe1, 16, 0x03, 0x1d, 0x07, 0x06, // _GMCTRN1 - 0x2E, 0x2C, 0x29, 0x2D, - 0x2E, 0x2E, 0x37, 0x3F, - 0x00, 0x00, 0x02, 0x10, + 0x2E, 0x2C, 0x29, 0x2D, + 0x2E, 0x2E, 0x37, 0x3F, + 0x00, 0x00, 0x02, 0x10, 0x2a, 3, 0x02, 0x00, 0x81, // _CASET XSTART = 2, XEND = 129 0x2b, 3, 0x02, 0x00, 0x81, // _RASET XSTART = 2, XEND = 129 0x13, 0 | DELAY, 10, // _NORON @@ -70,11 +70,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PB13, &pin_PB15, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -85,7 +85,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/pygamer_advance/board.c b/ports/atmel-samd/boards/pygamer_advance/board.c index 39bf65602..0711c4298 100644 --- a/ports/atmel-samd/boards/pygamer_advance/board.c +++ b/ports/atmel-samd/boards/pygamer_advance/board.c @@ -48,11 +48,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PB13, &pin_PB12, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -63,7 +63,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/pyportal/board.c b/ports/atmel-samd/boards/pyportal/board.c index db474a820..6fd169689 100644 --- a/ports/atmel-samd/boards/pyportal/board.c +++ b/ports/atmel-samd/boards/pyportal/board.c @@ -53,15 +53,15 @@ uint8_t display_init_sequence[] = { 0xF2, 1, 0x00, // 3Gamma Function Disable 0x26, 1, 0x01, // Gamma curve selected 0xe0, 15, 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, // Set Gamma - 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00, + 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00, 0xe1, 15, 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, // Set Gamma - 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F, + 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F, 0x11, DELAY, 120, // Exit Sleep 0x29, DELAY, 120, // Display on }; void board_init(void) { - displayio_parallelbus_obj_t* bus = &displays[0].parallel_bus; + displayio_parallelbus_obj_t *bus = &displays[0].parallel_bus; bus->base.type = &displayio_parallelbus_type; common_hal_displayio_parallelbus_construct(bus, &pin_PA16, // Data0 @@ -71,7 +71,7 @@ void board_init(void) { &pin_PB04, // Read &pin_PA00); // Reset - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/pyportal/mpconfigboard.h b/ports/atmel-samd/boards/pyportal/mpconfigboard.h index 00c376ad9..351647b12 100644 --- a/ports/atmel-samd/boards/pyportal/mpconfigboard.h +++ b/ports/atmel-samd/boards/pyportal/mpconfigboard.h @@ -11,10 +11,10 @@ // These are pins not to reset. // QSPI Data pins -#define MICROPY_PORT_A ( PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 ) +#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) // QSPI CS, and QSPI SCK -#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11 | PORT_PB22 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (PORT_PB10 | PORT_PB11 | PORT_PB22) +#define MICROPY_PORT_C (0) #define MICROPY_PORT_D (0) #define DEFAULT_I2C_BUS_SCL (&pin_PB03) diff --git a/ports/atmel-samd/boards/pyportal_titano/board.c b/ports/atmel-samd/boards/pyportal_titano/board.c index 59a25c4ac..d219ba794 100644 --- a/ports/atmel-samd/boards/pyportal_titano/board.c +++ b/ports/atmel-samd/boards/pyportal_titano/board.c @@ -37,48 +37,48 @@ #define DELAY 0x80 uint8_t display_init_sequence[] = { - 0x01, DELAY, 100/5, // Soft reset, then delay 10 ms + 0x01, DELAY, 100 / 5, // Soft reset, then delay 10 ms 0xB9, 3, 0xFF, 0x83, 0x57, // Extension command set - 0xFF, DELAY, 500/5, + 0xFF, DELAY, 500 / 5, 0xB3, 4, 0x80, 0x00, 0x06, 0x06, // 0x80 enables SDO pin (0x00 disables) 0xB6, 2, 0x01, 0x25, // -1.52V 0xB0, 1, 0x68, // Normal mode 70Hz, Idle mode 55 Hz 0xCC, 1, 0x05, 0xB1, 6, - 0x00, // Not deep standby - 0x15, // BT - 0x1C, // VSPR - 0x1C, // VSNR - 0x83, // AP - 0xAA, // FS + 0x00, // Not deep standby + 0x15, // BT + 0x1C, // VSPR + 0x1C, // VSNR + 0x83, // AP + 0xAA, // FS 0xC0, 6, - 0x50, // OPON normal - 0x50, // OPON idle - 0x01, // STBA - 0x3C, // STBA - 0x1E, // STBA - 0x08, // GEN + 0x50, // OPON normal + 0x50, // OPON idle + 0x01, // STBA + 0x3C, // STBA + 0x1E, // STBA + 0x08, // GEN 0xB4, 7, - 0x02, // NW 0x02 - 0x40, // RTN - 0x00, // DIV - 0x2A, // DUM - 0x2A, // DUM - 0x0D, // GDON - 0x78, // GDOFF + 0x02, // NW 0x02 + 0x40, // RTN + 0x00, // DIV + 0x2A, // DUM + 0x2A, // DUM + 0x0D, // GDON + 0x78, // GDOFF 0xE0, 34, - 0x02, 0x0A, 0x11, 0x1d, 0x23, 0x35, 0x41, 0x4b, 0x4b, - 0x42, 0x3A, 0x27, 0x1B, 0x08, 0x09, 0x03, 0x02, 0x0A, - 0x11, 0x1d, 0x23, 0x35, 0x41, 0x4b, 0x4b, 0x42, 0x3A, - 0x27, 0x1B, 0x08, 0x09, 0x03, 0x00, 0x01, + 0x02, 0x0A, 0x11, 0x1d, 0x23, 0x35, 0x41, 0x4b, 0x4b, + 0x42, 0x3A, 0x27, 0x1B, 0x08, 0x09, 0x03, 0x02, 0x0A, + 0x11, 0x1d, 0x23, 0x35, 0x41, 0x4b, 0x4b, 0x42, 0x3A, + 0x27, 0x1B, 0x08, 0x09, 0x03, 0x00, 0x01, 0x3a, 1, 0x55, 0x36, 1, 0x60, - 0x11, DELAY, 150/5, // Exit Sleep, then delay 150 ms - 0x29, DELAY, 50/5 + 0x11, DELAY, 150 / 5, // Exit Sleep, then delay 150 ms + 0x29, DELAY, 50 / 5 }; void board_init(void) { - displayio_parallelbus_obj_t* bus = &displays[0].parallel_bus; + displayio_parallelbus_obj_t *bus = &displays[0].parallel_bus; bus->base.type = &displayio_parallelbus_type; common_hal_displayio_parallelbus_construct(bus, &pin_PA16, // Data0 @@ -88,7 +88,7 @@ void board_init(void) { &pin_PB04, // Read &pin_PA00); // Reset - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/pyportal_titano/mpconfigboard.h b/ports/atmel-samd/boards/pyportal_titano/mpconfigboard.h index a76f1db5c..61c6117d9 100644 --- a/ports/atmel-samd/boards/pyportal_titano/mpconfigboard.h +++ b/ports/atmel-samd/boards/pyportal_titano/mpconfigboard.h @@ -9,10 +9,10 @@ // These are pins not to reset. // QSPI Data pins -#define MICROPY_PORT_A ( PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 ) +#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) // QSPI CS, and QSPI SCK -#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11 | PORT_PB22 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (PORT_PB10 | PORT_PB11 | PORT_PB22) +#define MICROPY_PORT_C (0) #define MICROPY_PORT_D (0) #define DEFAULT_I2C_BUS_SCL (&pin_PB03) diff --git a/ports/atmel-samd/boards/robohatmm1_m4/mpconfigboard.h b/ports/atmel-samd/boards/robohatmm1_m4/mpconfigboard.h index c66873aeb..4e482cff5 100644 --- a/ports/atmel-samd/boards/robohatmm1_m4/mpconfigboard.h +++ b/ports/atmel-samd/boards/robohatmm1_m4/mpconfigboard.h @@ -28,8 +28,8 @@ #define DEFAULT_SPI_BUS_MOSI (&pin_PB08) #define DEFAULT_SPI_BUS_MISO (&pin_PB11) -//#define DEFAULT_UART_BUS_RX (&pin_PB03) -//#define DEFAULT_UART_BUS_TX (&pin_PB02) +// #define DEFAULT_UART_BUS_RX (&pin_PB03) +// #define DEFAULT_UART_BUS_TX (&pin_PB02) // USB is always used internally so skip the pin objects for it. #define IGNORE_PIN_PA24 1 diff --git a/ports/atmel-samd/boards/robohatmm1_m4/pins.c b/ports/atmel-samd/boards/robohatmm1_m4/pins.c index 74dcfd651..32959ef3f 100644 --- a/ports/atmel-samd/boards/robohatmm1_m4/pins.c +++ b/ports/atmel-samd/boards/robohatmm1_m4/pins.c @@ -1,91 +1,91 @@ #include "shared-bindings/board/__init__.h" // Version 2.4 STATIC const mp_rom_map_elem_t board_global_dict_table[] = { - // SERVO Pins - { MP_ROM_QSTR(MP_QSTR_SERVO1), MP_ROM_PTR(&pin_PA18) }, - { MP_ROM_QSTR(MP_QSTR_SERVO2), MP_ROM_PTR(&pin_PA19) }, - { MP_ROM_QSTR(MP_QSTR_SERVO3), MP_ROM_PTR(&pin_PA20) }, - { MP_ROM_QSTR(MP_QSTR_SERVO4), MP_ROM_PTR(&pin_PA21) }, - { MP_ROM_QSTR(MP_QSTR_SERVO5), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_SERVO6), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_SERVO7), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_SERVO8), MP_ROM_PTR(&pin_PA08) }, + // SERVO Pins + { MP_ROM_QSTR(MP_QSTR_SERVO1), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_SERVO2), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_SERVO3), MP_ROM_PTR(&pin_PA20) }, + { MP_ROM_QSTR(MP_QSTR_SERVO4), MP_ROM_PTR(&pin_PA21) }, + { MP_ROM_QSTR(MP_QSTR_SERVO5), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_SERVO6), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_SERVO7), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_SERVO8), MP_ROM_PTR(&pin_PA08) }, - // RCC Pins - { MP_ROM_QSTR(MP_QSTR_RCC1), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_RCC2), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_RCC3), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_RCC4), MP_ROM_PTR(&pin_PA04) }, + // RCC Pins + { MP_ROM_QSTR(MP_QSTR_RCC1), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_RCC2), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_RCC3), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_RCC4), MP_ROM_PTR(&pin_PA04) }, - // Special Function - { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_BATTERY), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_POWER_OFF), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_POWER_DISABLE), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_POWER_ON), MP_ROM_PTR(&pin_PA27) }, - { MP_ROM_QSTR(MP_QSTR_POWER_ENABLE), MP_ROM_PTR(&pin_PA27) }, - { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PA27) }, + // Special Function + { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_BATTERY), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_POWER_OFF), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_POWER_DISABLE), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_POWER_ON), MP_ROM_PTR(&pin_PA27) }, + { MP_ROM_QSTR(MP_QSTR_POWER_ENABLE), MP_ROM_PTR(&pin_PA27) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PA27) }, - { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PB23) }, - { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PB22) }, + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PB23) }, + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PB22) }, - // GROVE on SERCOM0 - { MP_ROM_QSTR(MP_QSTR_GROVE_SCL), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_GROVE_SDA), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_GROVE_RX), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_GROVE_TX), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_GROVE_D1), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_GROVE_D0), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_GROVE_A1), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_GROVE_A0), MP_ROM_PTR(&pin_PA08) }, + // GROVE on SERCOM0 + { MP_ROM_QSTR(MP_QSTR_GROVE_SCL), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_GROVE_SDA), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_GROVE_RX), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_GROVE_TX), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_GROVE_D1), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_GROVE_D0), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_GROVE_A1), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_GROVE_A0), MP_ROM_PTR(&pin_PA08) }, - // UART on SERCOM0 - { MP_ROM_QSTR(MP_QSTR_UART_TX), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_UART_RX), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_UART_CTS), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_UART_RTS), MP_ROM_PTR(&pin_PA07) }, + // UART on SERCOM0 + { MP_ROM_QSTR(MP_QSTR_UART_TX), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_UART_RX), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_UART_CTS), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_UART_RTS), MP_ROM_PTR(&pin_PA07) }, - // UART on SERCOM1 (Raspberry Pi) - { MP_ROM_QSTR(MP_QSTR_TX1), MP_ROM_PTR(&pin_PA16) }, - { MP_ROM_QSTR(MP_QSTR_RX1), MP_ROM_PTR(&pin_PA17) }, - { MP_ROM_QSTR(MP_QSTR_PI_TX), MP_ROM_PTR(&pin_PA16) }, - { MP_ROM_QSTR(MP_QSTR_PI_RX), MP_ROM_PTR(&pin_PA17) }, + // UART on SERCOM1 (Raspberry Pi) + { MP_ROM_QSTR(MP_QSTR_TX1), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_RX1), MP_ROM_PTR(&pin_PA17) }, + { MP_ROM_QSTR(MP_QSTR_PI_TX), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_PI_RX), MP_ROM_PTR(&pin_PA17) }, - // I2C on SERCOM1 (External Connector) - { MP_ROM_QSTR(MP_QSTR_SDA1), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_SCL1), MP_ROM_PTR(&pin_PA01) }, + // I2C on SERCOM1 (External Connector) + { MP_ROM_QSTR(MP_QSTR_SDA1), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_SCL1), MP_ROM_PTR(&pin_PA01) }, - // SPI Flash on SERCOM2 - { MP_ROM_QSTR(MP_QSTR_FLASH_SCK), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_FLASH_MISO), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_FLASH_MOSI), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_FLASH_CS), MP_ROM_PTR(&pin_PA15) }, + // SPI Flash on SERCOM2 + { MP_ROM_QSTR(MP_QSTR_FLASH_SCK), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_FLASH_MISO), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_FLASH_MOSI), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_FLASH_CS), MP_ROM_PTR(&pin_PA15) }, - // I2C on SERCOM3 (RPi & Internal) - { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) }, - { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) }, - { MP_ROM_QSTR(MP_QSTR_PI_SDA), MP_ROM_PTR(&pin_PA22) }, - { MP_ROM_QSTR(MP_QSTR_PI_SCL), MP_ROM_PTR(&pin_PA23) }, + // I2C on SERCOM3 (RPi & Internal) + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) }, + { MP_ROM_QSTR(MP_QSTR_PI_SDA), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_PI_SCL), MP_ROM_PTR(&pin_PA23) }, - // SPI on SERCOM4 - { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB11) }, + // SPI on SERCOM4 + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB11) }, - // GPS on SERCOM5 - { MP_ROM_QSTR(MP_QSTR_GPS_TX), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_GPS_RX), MP_ROM_PTR(&pin_PB03) }, + // GPS on SERCOM5 + { MP_ROM_QSTR(MP_QSTR_GPS_TX), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_GPS_RX), MP_ROM_PTR(&pin_PB03) }, - // Raspberry Pi - { MP_ROM_QSTR(MP_QSTR_PI_GP25), MP_ROM_PTR(&pin_PA30) }, - { MP_ROM_QSTR(MP_QSTR_SWCLK), MP_ROM_PTR(&pin_PA30) }, - { MP_ROM_QSTR(MP_QSTR_PI_GP24), MP_ROM_PTR(&pin_PA31) }, - { MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA31) }, + // Raspberry Pi + { MP_ROM_QSTR(MP_QSTR_PI_GP25), MP_ROM_PTR(&pin_PA30) }, + { MP_ROM_QSTR(MP_QSTR_SWCLK), MP_ROM_PTR(&pin_PA30) }, + { MP_ROM_QSTR(MP_QSTR_PI_GP24), MP_ROM_PTR(&pin_PA31) }, + { MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA31) }, - { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, - { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, - //{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + // { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/sam32/mpconfigboard.h b/ports/atmel-samd/boards/sam32/mpconfigboard.h index 364d380d1..19f326782 100644 --- a/ports/atmel-samd/boards/sam32/mpconfigboard.h +++ b/ports/atmel-samd/boards/sam32/mpconfigboard.h @@ -11,7 +11,7 @@ #define MICROPY_PORT_D (0) #define CIRCUITPY_INTERNAL_NVM_SIZE 0 -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (128*1024) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (128 * 1024) #define BOARD_HAS_CRYSTAL 1 diff --git a/ports/atmel-samd/boards/same54_xplained/mpconfigboard.h b/ports/atmel-samd/boards/same54_xplained/mpconfigboard.h index 934559a2a..dbdd1aaa6 100644 --- a/ports/atmel-samd/boards/same54_xplained/mpconfigboard.h +++ b/ports/atmel-samd/boards/same54_xplained/mpconfigboard.h @@ -9,9 +9,9 @@ // These are pins not to reset. // QSPI Data pins -#define MICROPY_PORT_A ( PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 ) +#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) // QSPI CS, and QSPI SCK -#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11 ) +#define MICROPY_PORT_B (PORT_PB10 | PORT_PB11) #define MICROPY_PORT_C (0) #define MICROPY_PORT_D (0) diff --git a/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c b/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c index 53c43cd44..fe2393a57 100644 --- a/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c +++ b/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c @@ -65,11 +65,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_PB20, &pin_PB19, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -80,7 +80,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, @@ -112,23 +112,23 @@ void board_init(void) { true, // backlight_on_high false); // SH1107_addressing - // Enabling the Power of the 40-pin at the back - CTR_5V.base.type = &digitalio_digitalinout_type; - CTR_3V3.base.type = &digitalio_digitalinout_type; - USB_HOST_ENABLE.base.type = &digitalio_digitalinout_type; + // Enabling the Power of the 40-pin at the back + CTR_5V.base.type = &digitalio_digitalinout_type; + CTR_3V3.base.type = &digitalio_digitalinout_type; + USB_HOST_ENABLE.base.type = &digitalio_digitalinout_type; - common_hal_digitalio_digitalinout_construct(&CTR_5V, PIN_CTR_5V); - common_hal_digitalio_digitalinout_construct(&CTR_3V3, PIN_CTR_3V3); - common_hal_digitalio_digitalinout_construct(&USB_HOST_ENABLE, PIN_USB_HOST_ENABLE); + common_hal_digitalio_digitalinout_construct(&CTR_5V, PIN_CTR_5V); + common_hal_digitalio_digitalinout_construct(&CTR_3V3, PIN_CTR_3V3); + common_hal_digitalio_digitalinout_construct(&USB_HOST_ENABLE, PIN_USB_HOST_ENABLE); - common_hal_digitalio_digitalinout_set_value(&CTR_5V, true); - common_hal_digitalio_digitalinout_set_value(&CTR_3V3, false); - common_hal_digitalio_digitalinout_set_value(&USB_HOST_ENABLE, false); + common_hal_digitalio_digitalinout_set_value(&CTR_5V, true); + common_hal_digitalio_digitalinout_set_value(&CTR_3V3, false); + common_hal_digitalio_digitalinout_set_value(&USB_HOST_ENABLE, false); - // Never reset - common_hal_digitalio_digitalinout_never_reset(&CTR_5V); - common_hal_digitalio_digitalinout_never_reset(&CTR_3V3); - common_hal_digitalio_digitalinout_never_reset(&USB_HOST_ENABLE); + // Never reset + common_hal_digitalio_digitalinout_never_reset(&CTR_5V); + common_hal_digitalio_digitalinout_never_reset(&CTR_3V3); + common_hal_digitalio_digitalinout_never_reset(&USB_HOST_ENABLE); } diff --git a/ports/atmel-samd/boards/seeeduino_wio_terminal/pins.c b/ports/atmel-samd/boards/seeeduino_wio_terminal/pins.c index 0558191e6..45ff7c336 100644 --- a/ports/atmel-samd/boards/seeeduino_wio_terminal/pins.c +++ b/ports/atmel-samd/boards/seeeduino_wio_terminal/pins.c @@ -26,7 +26,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA17) }, // MP_QSTR_SDA - { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA16) }, //MP_QSTR_SCL + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA16) }, // MP_QSTR_SCL { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA15) }, // MP_QSTR_LED // UART pins diff --git a/ports/atmel-samd/boards/snekboard/board.c b/ports/atmel-samd/boards/snekboard/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/snekboard/board.c +++ b/ports/atmel-samd/boards/snekboard/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/snekboard/mpconfigboard.h b/ports/atmel-samd/boards/snekboard/mpconfigboard.h index 1c0804fe7..bea90a0fa 100644 --- a/ports/atmel-samd/boards/snekboard/mpconfigboard.h +++ b/ports/atmel-samd/boards/snekboard/mpconfigboard.h @@ -12,16 +12,16 @@ // These are pins not to reset. #define MICROPY_PORT_A (PORT_PB11) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define BOARD_HAS_CRYSTAL 0 -#define DEFAULT_I2C_BUS_SCL (&pin_PA08) /* ANALOG 5 */ -#define DEFAULT_I2C_BUS_SDA (&pin_PA09) /* ANALOG 6 */ +#define DEFAULT_I2C_BUS_SCL (&pin_PA08) /* ANALOG 5 */ +#define DEFAULT_I2C_BUS_SDA (&pin_PA09) /* ANALOG 6 */ -#define DEFAULT_UART_BUS_RX (&pin_PB08) /* ANALOG 1 */ -#define DEFAULT_UART_BUS_TX (&pin_PB09) /* ANALOG 2 */ +#define DEFAULT_UART_BUS_RX (&pin_PB08) /* ANALOG 1 */ +#define DEFAULT_UART_BUS_TX (&pin_PB09) /* ANALOG 2 */ // USB is always used internally so skip the pin objects for it. #define IGNORE_PIN_PA24 1 diff --git a/ports/atmel-samd/boards/sparkfun_lumidrive/board.c b/ports/atmel-samd/boards/sparkfun_lumidrive/board.c index 6baa43ffa..84960e73c 100755..100644 --- a/ports/atmel-samd/boards/sparkfun_lumidrive/board.c +++ b/ports/atmel-samd/boards/sparkfun_lumidrive/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/sparkfun_lumidrive/mpconfigboard.h b/ports/atmel-samd/boards/sparkfun_lumidrive/mpconfigboard.h index 80f37429f..836261bf8 100755..100644 --- a/ports/atmel-samd/boards/sparkfun_lumidrive/mpconfigboard.h +++ b/ports/atmel-samd/boards/sparkfun_lumidrive/mpconfigboard.h @@ -9,17 +9,17 @@ #define SPI_FLASH_SCK_PIN &pin_PA09 #define SPI_FLASH_CS_PIN &pin_PA13 -#define MICROPY_PORT_A ( 0 ) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define BOARD_HAS_CRYSTAL 1 -//I2C +// I2C #define DEFAULT_I2C_BUS_SCL (&pin_PA23) #define DEFAULT_I2C_BUS_SDA (&pin_PA22) -//SPI +// SPI #define DEFAULT_SPI_BUS_SCK (&pin_PA19) #define DEFAULT_SPI_BUS_MOSI (&pin_PA18) #define DEFAULT_SPI_BUS_MISO (&pin_PA21) diff --git a/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/board.c b/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/board.c +++ b/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/mpconfigboard.h b/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/mpconfigboard.h index dcce97b8d..c2527301f 100644 --- a/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/mpconfigboard.h +++ b/ports/atmel-samd/boards/sparkfun_qwiic_micro_no_flash/mpconfigboard.h @@ -1,23 +1,23 @@ #define MICROPY_HW_BOARD_NAME "SparkFun Qwiic Micro" #define MICROPY_HW_MCU_NAME "samd21e18" -#define MICROPY_PORT_A ( 0 ) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define CALIBRATE_CRYSTALLESS 1 #define BOARD_HAS_CRYSTAL 0 -//I2C and Qwiic Connector +// I2C and Qwiic Connector #define DEFAULT_I2C_BUS_SCL (&pin_PA09) #define DEFAULT_I2C_BUS_SDA (&pin_PA08) -//SPI +// SPI #define DEFAULT_SPI_BUS_SCK (&pin_PA07) #define DEFAULT_SPI_BUS_MOSI (&pin_PA06) #define DEFAULT_SPI_BUS_MISO (&pin_PA05) -//UART +// UART #define DEFAULT_UART_BUS_RX (&pin_PA23) #define DEFAULT_UART_BUS_TX (&pin_PA22) diff --git a/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/board.c b/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/board.c +++ b/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/mpconfigboard.h b/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/mpconfigboard.h index c9b195eef..4fb43629b 100644 --- a/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/mpconfigboard.h +++ b/ports/atmel-samd/boards/sparkfun_qwiic_micro_with_flash/mpconfigboard.h @@ -9,23 +9,23 @@ #define SPI_FLASH_SCK_PIN &pin_PA17 #define SPI_FLASH_CS_PIN &pin_PA19 -#define MICROPY_PORT_A ( 0 ) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define CALIBRATE_CRYSTALLESS 1 #define BOARD_HAS_CRYSTAL 0 -//I2C and Qwiic Connector +// I2C and Qwiic Connector #define DEFAULT_I2C_BUS_SCL (&pin_PA09) #define DEFAULT_I2C_BUS_SDA (&pin_PA08) -//SPI +// SPI #define DEFAULT_SPI_BUS_SCK (&pin_PA07) #define DEFAULT_SPI_BUS_MOSI (&pin_PA06) #define DEFAULT_SPI_BUS_MISO (&pin_PA05) -//UART +// UART #define DEFAULT_UART_BUS_RX (&pin_PA23) #define DEFAULT_UART_BUS_TX (&pin_PA22) diff --git a/ports/atmel-samd/boards/sparkfun_redboard_turbo/board.c b/ports/atmel-samd/boards/sparkfun_redboard_turbo/board.c index 6baa43ffa..84960e73c 100755..100644 --- a/ports/atmel-samd/boards/sparkfun_redboard_turbo/board.c +++ b/ports/atmel-samd/boards/sparkfun_redboard_turbo/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/sparkfun_redboard_turbo/mpconfigboard.h b/ports/atmel-samd/boards/sparkfun_redboard_turbo/mpconfigboard.h index ae272d502..b4076523f 100755..100644 --- a/ports/atmel-samd/boards/sparkfun_redboard_turbo/mpconfigboard.h +++ b/ports/atmel-samd/boards/sparkfun_redboard_turbo/mpconfigboard.h @@ -15,9 +15,9 @@ #define SPI_FLASH_SCK_PIN &pin_PB23 #define SPI_FLASH_CS_PIN &pin_PA13 -#define MICROPY_PORT_A ( 0 ) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define BOARD_HAS_CRYSTAL 1 diff --git a/ports/atmel-samd/boards/stackrduino_m0_pro/pins.c b/ports/atmel-samd/boards/stackrduino_m0_pro/pins.c index 95d2eb5a3..e0278aca0 100644 --- a/ports/atmel-samd/boards/stackrduino_m0_pro/pins.c +++ b/ports/atmel-samd/boards/stackrduino_m0_pro/pins.c @@ -23,16 +23,16 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA20) }, { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) }, { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) }, { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) }, - { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PA28) }, - { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PA28) }, - { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_CHRG_EN), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PA28) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PA28) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_CHRG_EN), MP_ROM_PTR(&pin_PA13) }, { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, diff --git a/ports/atmel-samd/boards/uchip/mpconfigboard.h b/ports/atmel-samd/boards/uchip/mpconfigboard.h index 5d6af4b78..6b8435877 100644 --- a/ports/atmel-samd/boards/uchip/mpconfigboard.h +++ b/ports/atmel-samd/boards/uchip/mpconfigboard.h @@ -3,7 +3,7 @@ #define MICROPY_HW_LED_STATUS (&pin_PA07) -#define MICROPY_PORT_A (PORT_PA00 | PORT_PA01 | PORT_PA14 | PORT_PA15 | PORT_PA28 | PORT_PA27 | PORT_PA24 | PORT_PA25) +#define MICROPY_PORT_A (PORT_PA00 | PORT_PA01 | PORT_PA14 | PORT_PA15 | PORT_PA28 | PORT_PA27 | PORT_PA24 | PORT_PA25) #define MICROPY_PORT_B (0) #define MICROPY_PORT_C (0) diff --git a/ports/atmel-samd/boards/ugame10/board.c b/ports/atmel-samd/boards/ugame10/board.c index 918fe2d59..f17b60ff6 100644 --- a/ports/atmel-samd/boards/ugame10/board.c +++ b/ports/atmel-samd/boards/ugame10/board.c @@ -56,13 +56,13 @@ uint8_t display_init_sequence[] = { // fix on VTL 0x3a, 1, 0x05, // COLMOD - 16bit color 0xe0, 16, 0x02, 0x1c, 0x07, 0x12, // _GMCTRP1 Gamma - 0x37, 0x32, 0x29, 0x2d, - 0x29, 0x25, 0x2B, 0x39, - 0x00, 0x01, 0x03, 0x10, + 0x37, 0x32, 0x29, 0x2d, + 0x29, 0x25, 0x2B, 0x39, + 0x00, 0x01, 0x03, 0x10, 0xe1, 16, 0x03, 0x1d, 0x07, 0x06, // _GMCTRN1 - 0x2E, 0x2C, 0x29, 0x2D, - 0x2E, 0x2E, 0x37, 0x3F, - 0x00, 0x00, 0x02, 0x10, + 0x2E, 0x2C, 0x29, 0x2D, + 0x2E, 0x2E, 0x37, 0x3F, + 0x00, 0x00, 0x02, 0x10, 0x2a, 3, 0x02, 0x00, 0x81, // _CASET XSTART = 2, XEND = 129 0x2b, 3, 0x02, 0x00, 0x81, // _RASET XSTART = 2, XEND = 129 0x13, 0 | DELAY, 10, // _NORON @@ -70,7 +70,7 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; busio_spi_obj_t *spi = common_hal_board_create_spi(); common_hal_displayio_fourwire_construct(bus, @@ -82,7 +82,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/atmel-samd/boards/winterbloom_big_honking_button/board.c b/ports/atmel-samd/boards/winterbloom_big_honking_button/board.c index 6baa43ffa..84960e73c 100644 --- a/ports/atmel-samd/boards/winterbloom_big_honking_button/board.c +++ b/ports/atmel-samd/boards/winterbloom_big_honking_button/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/winterbloom_big_honking_button/mpconfigboard.h b/ports/atmel-samd/boards/winterbloom_big_honking_button/mpconfigboard.h index 8d520f675..67882f633 100644 --- a/ports/atmel-samd/boards/winterbloom_big_honking_button/mpconfigboard.h +++ b/ports/atmel-samd/boards/winterbloom_big_honking_button/mpconfigboard.h @@ -10,8 +10,8 @@ // These are pins not to reset. #define MICROPY_PORT_A (PORT_PA00 | PORT_PA01) -#define MICROPY_PORT_B ( 0 ) -#define MICROPY_PORT_C ( 0 ) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define BOARD_HAS_CRYSTAL 0 diff --git a/ports/atmel-samd/boards/winterbloom_big_honking_button/usermods/_bhb/bhb.c b/ports/atmel-samd/boards/winterbloom_big_honking_button/usermods/_bhb/bhb.c index 54ce173d8..1a340ae22 100644 --- a/ports/atmel-samd/boards/winterbloom_big_honking_button/usermods/_bhb/bhb.c +++ b/ports/atmel-samd/boards/winterbloom_big_honking_button/usermods/_bhb/bhb.c @@ -15,18 +15,22 @@ STATIC mp_obj_t _bhb_init_adc(void) { /* Enable GCLK0 for the ADC */ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | - GCLK_CLKCTRL_GEN_GCLK0 | - GCLK_CLKCTRL_ID_ADC; + GCLK_CLKCTRL_GEN_GCLK0 | + GCLK_CLKCTRL_ID_ADC; /* Wait for bus synchronization. */ - while (GCLK->STATUS.bit.SYNCBUSY) {}; + while (GCLK->STATUS.bit.SYNCBUSY) { + } + ; - uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos; - uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos; - linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5; + uint32_t bias = (*((uint32_t *)ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos; + uint32_t linearity = (*((uint32_t *)ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos; + linearity |= ((*((uint32_t *)ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5; /* Wait for bus synchronization. */ - while (ADC->STATUS.bit.SYNCBUSY) {}; + while (ADC->STATUS.bit.SYNCBUSY) { + } + ; /* Write the calibration data. */ ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity); @@ -43,7 +47,7 @@ STATIC mp_obj_t _bhb_init_adc(void) { Set the resolution to 16 for averaging */ ADC->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV32 | - ADC_CTRLB_RESSEL_16BIT; + ADC_CTRLB_RESSEL_16BIT; /* Configure the input parameters. @@ -56,8 +60,8 @@ STATIC mp_obj_t _bhb_init_adc(void) { - MUXPOS_PIN3 means that the ADC should read from AIN2, or PB08. */ ADC->INPUTCTRL.reg = ADC_INPUTCTRL_GAIN_DIV2 | - ADC_INPUTCTRL_MUXNEG_GND | - ADC_INPUTCTRL_MUXPOS_PIN2; + ADC_INPUTCTRL_MUXNEG_GND | + ADC_INPUTCTRL_MUXPOS_PIN2; /* Set PB08 as an input pin. */ @@ -70,7 +74,9 @@ STATIC mp_obj_t _bhb_init_adc(void) { PORT->Group[1].PMUX[4].reg |= PORT_PMUX_PMUXE_B; /* Wait for bus synchronization. */ - while (ADC->STATUS.bit.SYNCBUSY) {}; + while (ADC->STATUS.bit.SYNCBUSY) { + } + ; /* Enable the ADC. */ ADC->CTRLA.bit.ENABLE = true; @@ -83,13 +89,17 @@ STATIC mp_obj_t _bhb_init_adc(void) { STATIC mp_obj_t _bhb_read_adc(void) { /* Wait for bus synchronization. */ - while (ADC->STATUS.bit.SYNCBUSY) {}; + while (ADC->STATUS.bit.SYNCBUSY) { + } + ; /* Start the ADC using a software trigger. */ ADC->SWTRIG.bit.START = true; /* Wait for the result ready flag to be set. */ - while (ADC->INTFLAG.bit.RESRDY == 0); + while (ADC->INTFLAG.bit.RESRDY == 0) { + ; + } /* Clear the flag. */ ADC->INTFLAG.reg = ADC_INTFLAG_RESRDY; @@ -114,7 +124,7 @@ STATIC MP_DEFINE_CONST_DICT(_bhb_module_globals, _bhb_module_globals_table); const mp_obj_module_t _bhb_user_cmodule = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&_bhb_module_globals, + .globals = (mp_obj_dict_t *)&_bhb_module_globals, }; MP_REGISTER_MODULE(MP_QSTR__bhb, _bhb_user_cmodule, MODULE_BHB_ENABLED); diff --git a/ports/atmel-samd/boards/xinabox_cc03/board.c b/ports/atmel-samd/boards/xinabox_cc03/board.c index 112b173ec..7af05ba45 100644 --- a/ports/atmel-samd/boards/xinabox_cc03/board.c +++ b/ports/atmel-samd/boards/xinabox_cc03/board.c @@ -28,8 +28,7 @@ #include "mpconfigboard.h" #include "hal/include/hal_gpio.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/boards/xinabox_cs11/board.c b/ports/atmel-samd/boards/xinabox_cs11/board.c index 112b173ec..7af05ba45 100644 --- a/ports/atmel-samd/boards/xinabox_cs11/board.c +++ b/ports/atmel-samd/boards/xinabox_cs11/board.c @@ -28,8 +28,7 @@ #include "mpconfigboard.h" #include "hal/include/hal_gpio.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/atmel-samd/common-hal/_pew/PewPew.c b/ports/atmel-samd/common-hal/_pew/PewPew.c index 1e7561ac8..40cd52134 100644 --- a/ports/atmel-samd/common-hal/_pew/PewPew.c +++ b/ports/atmel-samd/common-hal/_pew/PewPew.c @@ -47,7 +47,7 @@ void pewpew_interrupt_handler(uint8_t index) { if (index != pewpew_tc_index) { return; } - Tc* tc = tc_insts[index]; + Tc *tc = tc_insts[index]; if (!tc->COUNT16.INTFLAG.bit.MC0) { return; } @@ -60,7 +60,7 @@ void pewpew_interrupt_handler(uint8_t index) { } void pew_init() { - pew_obj_t* pew = MP_STATE_VM(pew_singleton); + pew_obj_t *pew = MP_STATE_VM(pew_singleton); common_hal_digitalio_digitalinout_switch_to_input(pew->buttons, PULL_UP); @@ -97,8 +97,8 @@ void pew_init() { #ifdef SAMD21 tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 | - TC_CTRLA_PRESCALER_DIV64 | - TC_CTRLA_WAVEGEN_MFRQ; + TC_CTRLA_PRESCALER_DIV64 | + TC_CTRLA_WAVEGEN_MFRQ; #endif #ifdef SAM_D5X_E5X tc_reset(tc); diff --git a/ports/atmel-samd/common-hal/_pew/PewPew.h b/ports/atmel-samd/common-hal/_pew/PewPew.h index a9c3b6626..523be0167 100644 --- a/ports/atmel-samd/common-hal/_pew/PewPew.h +++ b/ports/atmel-samd/common-hal/_pew/PewPew.h @@ -32,9 +32,9 @@ typedef struct { mp_obj_base_t base; - uint8_t* buffer; - mp_obj_t* rows; - mp_obj_t* cols; + uint8_t *buffer; + mp_obj_t *rows; + mp_obj_t *cols; digitalio_digitalinout_obj_t *buttons; uint8_t rows_size; uint8_t cols_size; diff --git a/ports/atmel-samd/common-hal/_pew/__init__.c b/ports/atmel-samd/common-hal/_pew/__init__.c index f3b23c606..b89b464dd 100644 --- a/ports/atmel-samd/common-hal/_pew/__init__.c +++ b/ports/atmel-samd/common-hal/_pew/__init__.c @@ -40,8 +40,10 @@ void pew_tick(void) { static uint8_t last_pressed = 0; digitalio_digitalinout_obj_t *pin; - pew_obj_t* pew = MP_STATE_VM(pew_singleton); - if (!pew) { return; } + pew_obj_t *pew = MP_STATE_VM(pew_singleton); + if (!pew) { + return; + } pin = MP_OBJ_TO_PTR(pew->cols[col]); ++col; @@ -69,7 +71,7 @@ void pew_tick(void) { break; case 2: if (turn == 2 || turn == 5 || turn == 8 || turn == 11) { - value = true; + value = true; } break; case 1: diff --git a/ports/atmel-samd/common-hal/analogio/AnalogIn.c b/ports/atmel-samd/common-hal/analogio/AnalogIn.c index 2bd218cdd..262e44350 100644 --- a/ports/atmel-samd/common-hal/analogio/AnalogIn.c +++ b/ports/atmel-samd/common-hal/analogio/AnalogIn.c @@ -46,8 +46,8 @@ #include "hpl/pm/hpl_pm_base.h" #endif -void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self, + const mcu_pin_obj_t *pin) { uint8_t adc_index; uint8_t adc_channel = 0xff; for (adc_index = 0; adc_index < NUM_ADC_PER_PIN; adc_index++) { @@ -66,7 +66,7 @@ void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self, gpio_set_pin_function(pin->number, GPIO_PIN_FUNCTION_B); - static Adc* adc_insts[] = ADC_INSTS; + static Adc *adc_insts[] = ADC_INSTS; self->instance = adc_insts[adc_index]; self->channel = adc_channel; self->pin = pin; @@ -118,8 +118,8 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { // Empirical observation shows the first reading is quite different than subsequent ones. uint16_t value; - adc_sync_read_channel(&adc, self->channel, ((uint8_t*) &value), 2); - adc_sync_read_channel(&adc, self->channel, ((uint8_t*) &value), 2); + adc_sync_read_channel(&adc, self->channel, ((uint8_t *)&value), 2); + adc_sync_read_channel(&adc, self->channel, ((uint8_t *)&value), 2); adc_sync_deinit(&adc); // Shift the value to be 16 bit. diff --git a/ports/atmel-samd/common-hal/analogio/AnalogIn.h b/ports/atmel-samd/common-hal/analogio/AnalogIn.h index 0b13ba7e1..3a467f64d 100644 --- a/ports/atmel-samd/common-hal/analogio/AnalogIn.h +++ b/ports/atmel-samd/common-hal/analogio/AnalogIn.h @@ -33,8 +33,8 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t * pin; - Adc* instance; + const mcu_pin_obj_t *pin; + Adc *instance; uint8_t channel; } analogio_analogin_obj_t; diff --git a/ports/atmel-samd/common-hal/analogio/AnalogOut.c b/ports/atmel-samd/common-hal/analogio/AnalogOut.c index 3ddd9cac6..f3b3310eb 100644 --- a/ports/atmel-samd/common-hal/analogio/AnalogOut.c +++ b/ports/atmel-samd/common-hal/analogio/AnalogOut.c @@ -47,10 +47,10 @@ #define HAVE_ANALOGOUT ( \ (defined(PIN_PA02) && !defined(IGNORE_PA02)) || \ (defined(SAM_D5X_E5X) && defined(PIN_PA05) && !defined(IGNORE_PA05)) \ -) + ) -void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self, + const mcu_pin_obj_t *pin) { #if !HAVE_ANALOGOUT mp_raise_NotImplementedError(translate("No DAC on chip")); #else @@ -63,15 +63,15 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, break; #endif - #if defined(SAM_D5X_E5X) && defined(PIN_PA05) && !defined(IGNORE_PIN_PA05) + #if defined(SAM_D5X_E5X) && defined(PIN_PA05) && !defined(IGNORE_PIN_PA05) case PIN_PA05: channel = 1; break; - #endif + #endif default: mp_raise_ValueError(translate("AnalogOut not supported on given pin")); - return; + return; } self->channel = channel; @@ -94,14 +94,14 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, #ifdef SAM_D5X_E5X if (!common_hal_mcu_pin_is_free(&pin_PA02) || !common_hal_mcu_pin_is_free(&pin_PA05)) { #endif - // Fake the descriptor if the DAC is already initialized. - self->descriptor.device.hw = DAC; + // Fake the descriptor if the DAC is already initialized. + self->descriptor.device.hw = DAC; #ifdef SAM_D5X_E5X - } else { +} else { #endif - result = dac_sync_init(&self->descriptor, DAC); + result = dac_sync_init(&self->descriptor, DAC); #ifdef SAM_D5X_E5X - } +} #endif if (result != ERR_NONE) { mp_raise_OSError(MP_EIO); @@ -134,9 +134,9 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) { #ifdef SAM_D5X_E5X if (common_hal_mcu_pin_is_free(&pin_PA02) && common_hal_mcu_pin_is_free(&pin_PA05)) { #endif - dac_sync_deinit(&self->descriptor); + dac_sync_deinit(&self->descriptor); #ifdef SAM_D5X_E5X - } +} #endif self->deinited = true; // TODO(tannewt): Turn off the DAC clocks to save power. @@ -144,7 +144,7 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) { } void common_hal_analogio_analogout_set_value(analogio_analogout_obj_t *self, - uint16_t value) { + uint16_t value) { #if HAVE_ANALOGOUT // Input is 16 bit so make sure and set LEFTADJ to 1 so it takes the top // bits. This is currently done in asf4_conf/*/hpl_dac_config.h. @@ -155,15 +155,17 @@ void common_hal_analogio_analogout_set_value(analogio_analogout_obj_t *self, void analogout_reset(void) { // audioout_reset also resets the DAC, and does a smooth ramp down to avoid clicks // if it was enabled, so do that instead if AudioOut is enabled. -#if CIRCUITPY_AUDIOIO + #if CIRCUITPY_AUDIOIO audioout_reset(); -#elif HAVE_ANALOGOUT + #elif HAVE_ANALOGOUT #ifdef SAMD21 - while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {} + while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) { + } #endif #ifdef SAM_D5X_E5X - while (DAC->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) {} + while (DAC->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) { + } #endif DAC->CTRLA.reg |= DAC_CTRLA_SWRST; -#endif + #endif } diff --git a/ports/atmel-samd/common-hal/audiobusio/I2SOut.c b/ports/atmel-samd/common-hal/audiobusio/I2SOut.c index 0aa48c804..2488b7b92 100644 --- a/ports/atmel-samd/common-hal/audiobusio/I2SOut.c +++ b/ports/atmel-samd/common-hal/audiobusio/I2SOut.c @@ -61,11 +61,11 @@ #include "audio_dma.h" #ifdef SAMD21 -#define SERCTRL(name) I2S_SERCTRL_ ## name +#define SERCTRL(name) I2S_SERCTRL_##name #endif #ifdef SAM_D5X_E5X -#define SERCTRL(name) I2S_TXCTRL_ ## name +#define SERCTRL(name) I2S_TXCTRL_##name #endif void i2sout_reset(void) { @@ -77,7 +77,8 @@ void i2sout_reset(void) { #endif if (I2S->CTRLA.bit.ENABLE == 1) { I2S->CTRLA.bit.ENABLE = 0; - while (I2S->SYNCBUSY.bit.ENABLE == 1) {} + while (I2S->SYNCBUSY.bit.ENABLE == 1) { + } } // Make sure the I2S peripheral is running so we can see if the resources we need are free. @@ -95,9 +96,9 @@ void i2sout_reset(void) { } // Caller validates that pins are free. -void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, - const mcu_pin_obj_t* bit_clock, const mcu_pin_obj_t* word_select, - const mcu_pin_obj_t* data, bool left_justified) { +void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t *self, + const mcu_pin_obj_t *bit_clock, const mcu_pin_obj_t *word_select, + const mcu_pin_obj_t *data, bool left_justified) { uint8_t serializer = 0xff; uint8_t bc_clock_unit = 0xff; uint8_t ws_clock_unit = 0xff; @@ -130,10 +131,10 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, if (data == &pin_PA07 || data == &pin_PA19) { // I2S SD[0] serializer = 0; } else if (data == &pin_PA08 - #ifdef PIN_PB16 - || data == &pin_PB16 - #endif - ) { // I2S SD[1] + #ifdef PIN_PB16 + || data == &pin_PB16 + #endif + ) { // I2S SD[1] serializer = 1; } #endif @@ -168,7 +169,8 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, if (I2S->CTRLA.bit.ENABLE == 0) { I2S->CTRLA.bit.SWRST = 1; - while (I2S->CTRLA.bit.SWRST == 1) {} + while (I2S->CTRLA.bit.SWRST == 1) { + } } else { #ifdef SAMD21 if ((I2S->CTRLA.vec.SEREN & (1 << serializer)) != 0) { @@ -206,11 +208,11 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, audio_dma_init(&self->dma); } -bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t *self) { return self->bit_clock == NULL; } -void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t *self) { if (common_hal_audiobusio_i2sout_deinited(self)) { return; } @@ -223,8 +225,8 @@ void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { self->data = NULL; } -void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, - mp_obj_t sample, bool loop) { +void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t *self, + mp_obj_t sample, bool loop) { if (common_hal_audiobusio_i2sout_get_playing(self)) { common_hal_audiobusio_i2sout_stop(self); } @@ -245,8 +247,8 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, self->gclk = gclk; uint32_t clkctrl = I2S_CLKCTRL_MCKSEL_GCLK | - I2S_CLKCTRL_NBSLOTS(1) | - I2S_CLKCTRL_FSWIDTH_HALF; + I2S_CLKCTRL_NBSLOTS(1) | + I2S_CLKCTRL_FSWIDTH_HALF; if (self->left_justified) { clkctrl |= I2S_CLKCTRL_BITDELAY_LJ; } else { @@ -293,11 +295,11 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, i2s_set_enable(true); #ifdef SAMD21 - uint32_t tx_register = (uint32_t) &I2S->DATA[self->serializer].reg; + uint32_t tx_register = (uint32_t)&I2S->DATA[self->serializer].reg; uint8_t dmac_id = I2S_DMAC_ID_TX_0 + self->serializer; #endif #ifdef SAM_D5X_E5X - uint32_t tx_register = (uint32_t) &I2S->TXDATA.reg; + uint32_t tx_register = (uint32_t)&I2S->TXDATA.reg; uint8_t dmac_id = I2S_DMAC_ID_TX_0; #endif audio_dma_result result = audio_dma_setup_playback(&self->dma, sample, loop, false, 0, @@ -314,26 +316,29 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, I2S->INTFLAG.reg = I2S_INTFLAG_TXUR0 | I2S_INTFLAG_TXUR1; I2S->CTRLA.vec.CKEN = 1 << self->clock_unit; - while ((I2S->SYNCBUSY.vec.CKEN & (1 << self->clock_unit)) != 0) {} + while ((I2S->SYNCBUSY.vec.CKEN & (1 << self->clock_unit)) != 0) { + } // Init the serializer after the clock. Otherwise, it will never enable because its unclocked. #ifdef SAMD21 I2S->CTRLA.vec.SEREN = 1 << self->serializer; - while ((I2S->SYNCBUSY.vec.SEREN & (1 << self->serializer)) != 0) {} + while ((I2S->SYNCBUSY.vec.SEREN & (1 << self->serializer)) != 0) { + } #endif #ifdef SAM_D5X_E5X I2S->CTRLA.bit.TXEN = 1; - while (I2S->SYNCBUSY.bit.TXEN == 1) {} + while (I2S->SYNCBUSY.bit.TXEN == 1) { + } #endif self->playing = true; } -void common_hal_audiobusio_i2sout_pause(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_pause(audiobusio_i2sout_obj_t *self) { audio_dma_pause(&self->dma); } -void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t *self) { // Clear any overrun/underrun errors #ifdef SAMD21 I2S->INTFLAG.reg = I2S_INTFLAG_TXUR0 << self->serializer; @@ -345,29 +350,33 @@ void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t* self) { audio_dma_resume(&self->dma); } -bool common_hal_audiobusio_i2sout_get_paused(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_get_paused(audiobusio_i2sout_obj_t *self) { return audio_dma_get_paused(&self->dma); } -void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t *self) { audio_dma_stop(&self->dma); #ifdef SAMD21 I2S->CTRLA.vec.SEREN &= ~(1 << self->serializer); - while ((I2S->SYNCBUSY.vec.SEREN & (1 << self->serializer)) != 0) {} + while ((I2S->SYNCBUSY.vec.SEREN & (1 << self->serializer)) != 0) { + } #endif #ifdef SAM_D5X_E5X I2S->CTRLA.bit.TXEN = 0; - while (I2S->SYNCBUSY.bit.TXEN == 1) {} + while (I2S->SYNCBUSY.bit.TXEN == 1) { + } #endif #ifdef SAMD21 if (self->clock_unit == 0) { I2S->CTRLA.bit.CKEN0 = 0; - while (I2S->SYNCBUSY.bit.CKEN0 == 1) {} + while (I2S->SYNCBUSY.bit.CKEN0 == 1) { + } } else { I2S->CTRLA.bit.CKEN1 = 0; - while (I2S->SYNCBUSY.bit.CKEN1 == 1) {} + while (I2S->SYNCBUSY.bit.CKEN1 == 1) { + } } #endif disconnect_gclk_from_peripheral(self->gclk, I2S_GCLK_ID_0 + self->clock_unit); @@ -380,7 +389,7 @@ void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t* self) { self->playing = false; } -bool common_hal_audiobusio_i2sout_get_playing(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_get_playing(audiobusio_i2sout_obj_t *self) { bool still_playing = audio_dma_get_playing(&self->dma); if (self->playing && !still_playing) { common_hal_audiobusio_i2sout_stop(self); diff --git a/ports/atmel-samd/common-hal/audiobusio/PDMIn.c.uncrustify b/ports/atmel-samd/common-hal/audiobusio/PDMIn.c.uncrustify new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/ports/atmel-samd/common-hal/audiobusio/PDMIn.c.uncrustify diff --git a/ports/atmel-samd/modules/frozentest.py b/ports/atmel-samd/modules/frozentest.py index 0f99b7429..78cdd60bf 100644 --- a/ports/atmel-samd/modules/frozentest.py +++ b/ports/atmel-samd/modules/frozentest.py @@ -1,7 +1,7 @@ -print('uPy') -print('a long string that is not interned') -print('a string that has unicode αβγ chars') -print(b'bytes 1234\x01') +print("uPy") +print("a long string that is not interned") +print("a string that has unicode αβγ chars") +print(b"bytes 1234\x01") print(123456789) for i in range(4): print(i) diff --git a/ports/atmel-samd/tools/gen_pin_name_table.py b/ports/atmel-samd/tools/gen_pin_name_table.py index 4e25c39fd..a78144d40 100644 --- a/ports/atmel-samd/tools/gen_pin_name_table.py +++ b/ports/atmel-samd/tools/gen_pin_name_table.py @@ -27,11 +27,47 @@ import os import os.path -pins = ["PA00", "PA01", "PA02", "PA03", "PB08", "PB09", "PA04", "PA05", "PA06", - "PA07", "PA08", "PA09", "PA10", "PA11", "PB10", "PB11", "PA12", "PA13", - "PA14", "PA15", "PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", - "PA23", "PA24", "PA25", "PB22", "PB23", "PA27", "PA28", "PA29", "PA30", - "PA31", "PB02", "PB03"] +pins = [ + "PA00", + "PA01", + "PA02", + "PA03", + "PB08", + "PB09", + "PA04", + "PA05", + "PA06", + "PA07", + "PA08", + "PA09", + "PA10", + "PA11", + "PB10", + "PB11", + "PA12", + "PA13", + "PA14", + "PA15", + "PA16", + "PA17", + "PA18", + "PA19", + "PA20", + "PA21", + "PA22", + "PA23", + "PA24", + "PA25", + "PB22", + "PB23", + "PA27", + "PA28", + "PA29", + "PA30", + "PA31", + "PB02", + "PB03", +] # Dictionary keys: [board][pin] = list of pin names mapping = {} @@ -46,7 +82,7 @@ for board in os.listdir("boards"): for line in f: if line.startswith(QSTR): board_name, _, pin = line.split(")") - board_name = board_name[len(QSTR):] + board_name = board_name[len(QSTR) :] pin = pin[-8:-4] if pin not in mapping[board]: mapping[board][pin] = [] @@ -108,61 +144,196 @@ ALL_BUT_USB.remove("PA25") # dictionary is [module][class] = [pins] capabilities = { - "analogio" : { - "AnalogIn" : ["PA02", "PA03", "PB08", "PB09", "PA04", "PA05", "PA06", - "PA07", "PA08", "PA09", "PA10", "PA11", "PB02", "PB03"], - "AnalogOut": ["PA02"] - }, - "audioio" : { - "AudioOut": ["PA02"] - }, - "bitbangio": { - "I2C": ALL_BUT_USB, - "OneWire": ALL_BUT_USB, - "SPI": ALL_BUT_USB + "analogio": { + "AnalogIn": [ + "PA02", + "PA03", + "PB08", + "PB09", + "PA04", + "PA05", + "PA06", + "PA07", + "PA08", + "PA09", + "PA10", + "PA11", + "PB02", + "PB03", + ], + "AnalogOut": ["PA02"], }, + "audioio": {"AudioOut": ["PA02"]}, + "bitbangio": {"I2C": ALL_BUT_USB, "OneWire": ALL_BUT_USB, "SPI": ALL_BUT_USB}, "busio": { - "I2C - SDA": ["PA00", "PB08", "PA08", "PA12", "PA16", "PA22", "PB02"], # SERCOM pad 0 - "I2C - SCL": ["PA01", "PB09", "PA09", "PA13", "PA17", "PA23", "PB03"], # SERCOM pad 1 + "I2C - SDA": ["PA00", "PB08", "PA08", "PA12", "PA16", "PA22", "PB02"], # SERCOM pad 0 + "I2C - SCL": ["PA01", "PB09", "PA09", "PA13", "PA17", "PA23", "PB03"], # SERCOM pad 1 "OneWire": ALL_BUT_USB, - "SPI - MISO": ["PA00", "PA01", "PB08", "PB09", "PA04", "PA05", "PA06", - "PA07", "PA08", "PA09", "PA10", "PA11", "PB10", "PB11", - "PA12", "PA13", "PA14", "PA15", "PA16", "PA17", "PA18", - "PA19", "PA20", "PA21", "PA22", "PA23", "PB22", "PB23", - "PA30", "PA31", "PB02", "PB03"], # any SERCOM pad - "SPI - MOSI": ["PA00", "PB08", "PA04", "PA06", "PA08", "PA10", "PA11", - "PB10", "PB11", "PA14", "PA15", "PA16", "PA18", "PA19", - "PA20", "PA21", "PA22", "PB22", "PB23", "PA30", "PA31", - "PB02"], # any pad but 1 - "SPI - SCK": ["PA01", "PB09", "PA05", "PA07", "PA09", "PA11", "PB11", - "PA13", "PA15", "PA17", "PA19", "PA21", "PA23", "PB23", - "PA31", "PB03"], # 1 or 3 - "UART - RX": ["PA00", "PA01", "PB08", "PB09", "PA04", "PA05", "PA06", - "PA07", "PA08", "PA09", "PA10", "PA11", "PB10", "PB11", - "PA12", "PA13", "PA14", "PA15", "PA16", "PA17", "PA18", - "PA19", "PA20", "PA21", "PA22", "PA23", "PB22", "PB23", - "PA30", "PA31", "PB02", "PB03"], # any pad - "UART - TX": ["PA00", "PB08", "PA04", "PA06", "PA08", "PA10", "PB10", - "PA12", "PA14", "PA16", "PA18", "PA20", "PA22", "PB22", - "PA30", "PB02"] # pad 0 or 2 - }, - "digitalio": { - "DigitalInOut": ALL_BUT_USB + "SPI - MISO": [ + "PA00", + "PA01", + "PB08", + "PB09", + "PA04", + "PA05", + "PA06", + "PA07", + "PA08", + "PA09", + "PA10", + "PA11", + "PB10", + "PB11", + "PA12", + "PA13", + "PA14", + "PA15", + "PA16", + "PA17", + "PA18", + "PA19", + "PA20", + "PA21", + "PA22", + "PA23", + "PB22", + "PB23", + "PA30", + "PA31", + "PB02", + "PB03", + ], # any SERCOM pad + "SPI - MOSI": [ + "PA00", + "PB08", + "PA04", + "PA06", + "PA08", + "PA10", + "PA11", + "PB10", + "PB11", + "PA14", + "PA15", + "PA16", + "PA18", + "PA19", + "PA20", + "PA21", + "PA22", + "PB22", + "PB23", + "PA30", + "PA31", + "PB02", + ], # any pad but 1 + "SPI - SCK": [ + "PA01", + "PB09", + "PA05", + "PA07", + "PA09", + "PA11", + "PB11", + "PA13", + "PA15", + "PA17", + "PA19", + "PA21", + "PA23", + "PB23", + "PA31", + "PB03", + ], # 1 or 3 + "UART - RX": [ + "PA00", + "PA01", + "PB08", + "PB09", + "PA04", + "PA05", + "PA06", + "PA07", + "PA08", + "PA09", + "PA10", + "PA11", + "PB10", + "PB11", + "PA12", + "PA13", + "PA14", + "PA15", + "PA16", + "PA17", + "PA18", + "PA19", + "PA20", + "PA21", + "PA22", + "PA23", + "PB22", + "PB23", + "PA30", + "PA31", + "PB02", + "PB03", + ], # any pad + "UART - TX": [ + "PA00", + "PB08", + "PA04", + "PA06", + "PA08", + "PA10", + "PB10", + "PA12", + "PA14", + "PA16", + "PA18", + "PA20", + "PA22", + "PB22", + "PA30", + "PB02", + ], # pad 0 or 2 }, + "digitalio": {"DigitalInOut": ALL_BUT_USB}, "pulseio": { "PulseIn": ALL_BUT_USB, - "PWMOut": ["PA01", "PB09", "PA04", "PA05", "PA06", "PA07", "PA08", - "PA09", "PA10", "PA11", "PB10", "PB11", "PA12", "PA13", - "PA14", "PA15", "PA16", "PA17", "PA18", "PA19", "PA20", - "PA21", "PA22", "PA23", "PA30", "PA31"] - }, - "ps2io": { - "Ps2": ALL_BUT_USB, + "PWMOut": [ + "PA01", + "PB09", + "PA04", + "PA05", + "PA06", + "PA07", + "PA08", + "PA09", + "PA10", + "PA11", + "PB10", + "PB11", + "PA12", + "PA13", + "PA14", + "PA15", + "PA16", + "PA17", + "PA18", + "PA19", + "PA20", + "PA21", + "PA22", + "PA23", + "PA30", + "PA31", + ], }, + "ps2io": {"Ps2": ALL_BUT_USB}, "touchio": { - "TouchIn": ["PA02", "PA03", "PB08", "PB09", "PA04", "PA05", "PA06", - "PA07", "PB02", "PB03"] - } + "TouchIn": ["PA02", "PA03", "PB08", "PB09", "PA04", "PA05", "PA06", "PA07", "PB02", "PB03"] + }, } column_width = {} @@ -178,7 +349,7 @@ for module in capabilities: module_width[module] -= 2 if module_width[module] < (len(module) + 2): - column_width[module + c] += (len(module) + 2 - module_width[module]) + column_width[module + c] += len(module) + 2 - module_width[module] module_width[module] = len(module) + 2 first_column_width = len("`microcontroller.pin`") diff --git a/ports/atmel-samd/tools/mkcandata.py b/ports/atmel-samd/tools/mkcandata.py index 9668d2208..d505c81bd 100755 --- a/ports/atmel-samd/tools/mkcandata.py +++ b/ports/atmel-samd/tools/mkcandata.py @@ -1,22 +1,27 @@ #!/usr/bin/python3 + def defines(name, suffix): - print(f'mcu_pin_function_t {name} [] = {{') + print(f"mcu_pin_function_t {name} [] = {{") for instance in (0, 1): - for function in 'HI': - for port in 'ABCD': + for function in "HI": + for port in "ABCD": for idx in range(32): - pin = f'P{port}{idx:02d}' - pinmux = f'PINMUX_{pin}{function}_CAN{instance}_{suffix}' - print(f'''\ + pin = f"P{port}{idx:02d}" + pinmux = f"PINMUX_{pin}{function}_CAN{instance}_{suffix}" + print( + f"""\ #if defined({pinmux}) && ! defined(IGNORE_PIN_{pin}) {{&pin_{pin}, {instance}, PIN_{pin}, {pinmux} & 0xffff}}, -#endif''') - print(f'{{NULL, 0, 0}}') - print(f'}};') +#endif""" + ) + print(f"{{NULL, 0, 0}}") + print(f"}};") print() -print('''\ + +print( + """\ #include <stdint.h> #include "py/obj.h" #include "sam.h" @@ -25,7 +30,8 @@ print('''\ #include "atmel_start_pins.h" #include "hal/include/hal_gpio.h" #include "common-hal/microcontroller/Pin.h" -''') +""" +) -defines('can_rx', 'RX') -defines('can_tx', 'TX') +defines("can_rx", "RX") +defines("can_tx", "TX") diff --git a/ports/atmel-samd/tools/mksdiodata.py b/ports/atmel-samd/tools/mksdiodata.py index 48c4a085f..bfdcd696c 100755 --- a/ports/atmel-samd/tools/mksdiodata.py +++ b/ports/atmel-samd/tools/mksdiodata.py @@ -1,21 +1,26 @@ #!/usr/bin/python3 + def defines(name, function): - print(f'mcu_pin_function_t {name} [] = {{') + print(f"mcu_pin_function_t {name} [] = {{") for instance in (0, 1): - for port in 'ABCD': + for port in "ABCD": for idx in range(32): - pin = f'P{port}{idx:02d}' - pinmux = f'PINMUX_{pin}I_SDHC{instance}_{function}' - print(f'''\ + pin = f"P{port}{idx:02d}" + pinmux = f"PINMUX_{pin}I_SDHC{instance}_{function}" + print( + f"""\ #if defined({pinmux}) && ! defined(IGNORE_PIN_{pin}) {{&pin_{pin}, {instance}, PIN_{pin}, {pinmux} & 0xffff}}, -#endif''') - print(f'{{NULL, 0, 0}}') - print(f'}};') +#endif""" + ) + print(f"{{NULL, 0, 0}}") + print(f"}};") print() -print('''\ + +print( + """\ #include <stdint.h> #include "py/obj.h" #include "sam.h" @@ -25,11 +30,12 @@ print('''\ #include "hal/include/hal_gpio.h" #include "common-hal/microcontroller/Pin.h" -''') +""" +) -defines('sdio_ck', 'SDCK') -defines('sdio_cmd', 'SDCMD') -defines('sdio_dat0', 'SDDAT0') -defines('sdio_dat1', 'SDDAT1') -defines('sdio_dat2', 'SDDAT2') -defines('sdio_dat3', 'SDDAT3') +defines("sdio_ck", "SDCK") +defines("sdio_cmd", "SDCMD") +defines("sdio_dat0", "SDDAT0") +defines("sdio_dat1", "SDDAT1") +defines("sdio_dat2", "SDDAT2") +defines("sdio_dat3", "SDDAT3") diff --git a/ports/atmel-samd/tools/update_asf.py b/ports/atmel-samd/tools/update_asf.py index 7b7bac10f..a747d6b06 100644 --- a/ports/atmel-samd/tools/update_asf.py +++ b/ports/atmel-samd/tools/update_asf.py @@ -11,7 +11,11 @@ for chip in ["samd21", "samd51"]: if not os.path.isfile(filename): with open("tools/" + chip + ".json", "r") as project_json: headers = {"content-type": "text/plain"} - r = requests.post("http://start.atmel.com/api/v1/generate/?format=atzip&compilers=[make]&file_name_base=My%20Project", headers=headers, data=project_json) + r = requests.post( + "http://start.atmel.com/api/v1/generate/?format=atzip&compilers=[make]&file_name_base=My%20Project", + headers=headers, + data=project_json, + ) if not r.ok: # Double check that the JSON is minified. If its not, you'll get a 404. print(r.text) @@ -40,7 +44,9 @@ for chip in ["samd21", "samd51"]: for patch in os.listdir("asf4/patches/" + chip): patch = "patches/" + chip + "/" + patch print(patch) - result = subprocess.run(["patch", "-l", "-F", "10", "-u", "-p", "1", "-d", tmp_dir, "-i", "../" + patch]) + result = subprocess.run( + ["patch", "-l", "-F", "10", "-u", "-p", "1", "-d", tmp_dir, "-i", "../" + patch] + ) ok = ok and result.returncode == 0 print() diff --git a/ports/cxd56/boards/spresense/board.c b/ports/cxd56/boards/spresense/board.c index fd27d3493..7d6297b64 100644 --- a/ports/cxd56/boards/spresense/board.c +++ b/ports/cxd56/boards/spresense/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/cxd56/common-hal/analogio/AnalogIn.c b/ports/cxd56/common-hal/analogio/AnalogIn.c index 5c47991eb..d1bd68cfb 100644 --- a/ports/cxd56/common-hal/analogio/AnalogIn.c +++ b/ports/cxd56/common-hal/analogio/AnalogIn.c @@ -36,7 +36,7 @@ #include "shared-bindings/analogio/AnalogIn.h" typedef struct { - const char* devpath; + const char *devpath; const mcu_pin_obj_t *pin; int fd; } analogin_dev_t; @@ -109,7 +109,7 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { read(analogin_dev[self->number].fd, &value, sizeof(value)); - return (uint16_t) 32768 + (uint16_t) value; + return (uint16_t)32768 + (uint16_t)value; } // Reference voltage is a fixed value which is depending on the board. diff --git a/ports/cxd56/common-hal/busio/I2C.c b/ports/cxd56/common-hal/busio/I2C.c index 5579bedeb..0e6dbedc0 100644 --- a/ports/cxd56/common-hal/busio/I2C.c +++ b/ports/cxd56/common-hal/busio/I2C.c @@ -101,7 +101,7 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t address, cons msg.frequency = self->frequency; msg.addr = address; msg.flags = (stop ? 0 : I2C_M_NOSTOP); - msg.buffer = (uint8_t *) data; + msg.buffer = (uint8_t *)data; msg.length = len; return -I2C_TRANSFER(self->i2c_dev, &msg, 1); } diff --git a/ports/cxd56/common-hal/busio/I2C.h b/ports/cxd56/common-hal/busio/I2C.h index cdef270bf..4d1d3ce9b 100644 --- a/ports/cxd56/common-hal/busio/I2C.h +++ b/ports/cxd56/common-hal/busio/I2C.h @@ -33,7 +33,7 @@ typedef struct { mp_obj_base_t base; - struct i2c_master_s* i2c_dev; + struct i2c_master_s *i2c_dev; uint32_t frequency; bool has_lock; const mcu_pin_obj_t *scl_pin; diff --git a/ports/cxd56/common-hal/busio/SPI.c b/ports/cxd56/common-hal/busio/SPI.c index 56ab0758d..e77c0224d 100644 --- a/ports/cxd56/common-hal/busio/SPI.c +++ b/ports/cxd56/common-hal/busio/SPI.c @@ -144,7 +144,7 @@ uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) { return self->frequency; } -uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) { return self->phase; } diff --git a/ports/cxd56/common-hal/busio/SPI.h b/ports/cxd56/common-hal/busio/SPI.h index 8985a60d9..ee04de08c 100644 --- a/ports/cxd56/common-hal/busio/SPI.h +++ b/ports/cxd56/common-hal/busio/SPI.h @@ -35,7 +35,7 @@ typedef struct { mp_obj_base_t base; - struct spi_dev_s* spi_dev; + struct spi_dev_s *spi_dev; uint32_t frequency; uint8_t phase; uint8_t polarity; diff --git a/ports/cxd56/common-hal/busio/UART.c b/ports/cxd56/common-hal/busio/UART.c index 52d2afc0c..f7588c710 100644 --- a/ports/cxd56/common-hal/busio/UART.c +++ b/ports/cxd56/common-hal/busio/UART.c @@ -42,7 +42,7 @@ #include "shared-bindings/busio/UART.h" typedef struct { - const char* devpath; + const char *devpath; const mcu_pin_obj_t *tx; const mcu_pin_obj_t *rx; int fd; @@ -53,11 +53,11 @@ STATIC busio_uart_dev_t busio_uart_dev[] = { }; void common_hal_busio_uart_construct(busio_uart_obj_t *self, - const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx, - const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts, - const mcu_pin_obj_t * rs485_dir, bool rs485_invert, + const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx, + const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts, + const mcu_pin_obj_t *rs485_dir, bool rs485_invert, uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, - mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer, + mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer, bool sigint_enabled) { struct termios tio; @@ -180,7 +180,7 @@ void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrat } mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) { - return (mp_float_t) (self->timeout_us / 1000000.0f); + return (mp_float_t)(self->timeout_us / 1000000.0f); } void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) { diff --git a/ports/cxd56/common-hal/camera/Camera.c b/ports/cxd56/common-hal/camera/Camera.c index 35e2ab882..5e159d61d 100644 --- a/ports/cxd56/common-hal/camera/Camera.c +++ b/ports/cxd56/common-hal/camera/Camera.c @@ -36,7 +36,7 @@ #include "shared-bindings/camera/Camera.h" typedef struct { - const char* devpath; + const char *devpath; int fd; } camera_dev_t; diff --git a/ports/cxd56/common-hal/gnss/GNSS.c b/ports/cxd56/common-hal/gnss/GNSS.c index c0aaa3cfb..f345f5261 100644 --- a/ports/cxd56/common-hal/gnss/GNSS.c +++ b/ports/cxd56/common-hal/gnss/GNSS.c @@ -34,7 +34,7 @@ #include "shared-bindings/gnss/GNSS.h" typedef struct { - const char* devpath; + const char *devpath; int fd; } gnss_dev_t; @@ -110,15 +110,15 @@ void common_hal_gnss_update(gnss_obj_t *self) { } mp_float_t common_hal_gnss_get_latitude(gnss_obj_t *self) { - return (mp_float_t) self->latitude; + return (mp_float_t)self->latitude; } mp_float_t common_hal_gnss_get_longitude(gnss_obj_t *self) { - return (mp_float_t) self->longitude; + return (mp_float_t)self->longitude; } mp_float_t common_hal_gnss_get_altitude(gnss_obj_t *self) { - return (mp_float_t) self->altitude; + return (mp_float_t)self->altitude; } void common_hal_gnss_get_timestamp(gnss_obj_t *self, timeutils_struct_time_t *tm) { diff --git a/ports/cxd56/common-hal/microcontroller/Pin.h b/ports/cxd56/common-hal/microcontroller/Pin.h index 6759a2dca..259fc5716 100644 --- a/ports/cxd56/common-hal/microcontroller/Pin.h +++ b/ports/cxd56/common-hal/microcontroller/Pin.h @@ -32,11 +32,11 @@ extern const mp_obj_type_t mcu_pin_type; #define PIN(pin, a) \ -{ \ - { &mcu_pin_type }, \ - .number = (pin), \ - .analog = (a) \ -} + { \ + { &mcu_pin_type }, \ + .number = (pin), \ + .analog = (a) \ + } typedef struct { mp_obj_base_t base; @@ -93,6 +93,6 @@ extern const mcu_pin_obj_t pin_HPADC1; void never_reset_pin_number(uint8_t pin_number); void reset_pin_number(uint8_t pin_number); void reset_all_pins(void); -void claim_pin(const mcu_pin_obj_t* pin); +void claim_pin(const mcu_pin_obj_t *pin); #endif // MICROPY_INCLUDED_CXD56_COMMON_HAL_MICROCONTROLLER_PIN_H diff --git a/ports/cxd56/common-hal/microcontroller/Processor.c b/ports/cxd56/common-hal/microcontroller/Processor.c index 3cb187de6..b5efe37ce 100644 --- a/ports/cxd56/common-hal/microcontroller/Processor.c +++ b/ports/cxd56/common-hal/microcontroller/Processor.c @@ -46,7 +46,7 @@ float common_hal_mcu_processor_get_voltage(void) { } void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { - boardctl(BOARDIOC_UNIQUEID, (uintptr_t) raw_id); + boardctl(BOARDIOC_UNIQUEID, (uintptr_t)raw_id); } mcu_reset_reason_t common_hal_mcu_processor_get_reset_reason(void) { diff --git a/ports/cxd56/common-hal/microcontroller/__init__.c b/ports/cxd56/common-hal/microcontroller/__init__.c index 7aa3b839d..499e0e5f0 100644 --- a/ports/cxd56/common-hal/microcontroller/__init__.c +++ b/ports/cxd56/common-hal/microcontroller/__init__.c @@ -49,14 +49,16 @@ const mcu_processor_obj_t common_hal_mcu_processor_obj = { void common_hal_mcu_delay_us(uint32_t delay) { if (delay) { unsigned long long ticks = cxd56_get_cpu_baseclk() / 1000000L * delay; - if (ticks < DELAY_CORRECTION) return; // delay time already used in calculation + if (ticks < DELAY_CORRECTION) { + return; // delay time already used in calculation + } ticks -= DELAY_CORRECTION; ticks /= 6; // following loop takes 6 cycles do { - __asm__ __volatile__("nop"); - } while(--ticks); + __asm__ __volatile__ ("nop"); + } while (--ticks); } } @@ -69,9 +71,9 @@ void common_hal_mcu_enable_interrupts(void) { } void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) { - if(runmode == RUNMODE_BOOTLOADER) { + if (runmode == RUNMODE_BOOTLOADER) { mp_raise_ValueError(translate("Cannot reset into bootloader because no bootloader is present.")); - } else if(runmode == RUNMODE_SAFE_MODE) { + } else if (runmode == RUNMODE_SAFE_MODE) { safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE); } } diff --git a/ports/cxd56/common-hal/os/__init__.c b/ports/cxd56/common-hal/os/__init__.c index d4b0e23be..e44d293f0 100644 --- a/ports/cxd56/common-hal/os/__init__.c +++ b/ports/cxd56/common-hal/os/__init__.c @@ -50,13 +50,13 @@ STATIC MP_DEFINE_ATTRTUPLE( (mp_obj_t)&os_uname_info_release_obj, (mp_obj_t)&os_uname_info_version_obj, (mp_obj_t)&os_uname_info_machine_obj -); + ); mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; } -bool common_hal_os_urandom(uint8_t* buffer, mp_uint_t length) { +bool common_hal_os_urandom(uint8_t *buffer, mp_uint_t length) { uint32_t i = 0; while (i < length) { diff --git a/ports/cxd56/common-hal/pulseio/PulseIn.c b/ports/cxd56/common-hal/pulseio/PulseIn.c index 7c3e4a9d0..0d2fbbfd9 100644 --- a/ports/cxd56/common-hal/pulseio/PulseIn.c +++ b/ports/cxd56/common-hal/pulseio/PulseIn.c @@ -54,7 +54,7 @@ static int pulsein_interrupt_handler(int irq, FAR void *context, FAR void *arg) // Grab the current time first. struct timeval tv; gettimeofday(&tv, NULL); - uint64_t current_us = ((uint64_t) tv.tv_sec) * 1000000 + tv.tv_usec; + uint64_t current_us = ((uint64_t)tv.tv_sec) * 1000000 + tv.tv_usec; pulseio_pulsein_obj_t *self = pulsein_objects[irq - CXD56_IRQ_EXDEVICE_0]; @@ -85,7 +85,7 @@ static int pulsein_interrupt_handler(int irq, FAR void *context, FAR void *arg) void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t *self, const mcu_pin_obj_t *pin, uint16_t maxlen, bool idle_state) { - self->buffer = (uint16_t *) m_malloc(maxlen * sizeof(uint16_t), false); + self->buffer = (uint16_t *)m_malloc(maxlen * sizeof(uint16_t), false); if (self->buffer == NULL) { mp_raise_msg_varg(&mp_type_MemoryError, translate("Failed to allocate RX buffer of %d bytes"), maxlen * sizeof(uint16_t)); } diff --git a/ports/cxd56/common-hal/pulseio/PulseOut.c b/ports/cxd56/common-hal/pulseio/PulseOut.c index f08e7cd7a..be0d51f57 100644 --- a/ports/cxd56/common-hal/pulseio/PulseOut.c +++ b/ports/cxd56/common-hal/pulseio/PulseOut.c @@ -38,8 +38,7 @@ static uint16_t pulse_index = 0; static uint16_t pulse_length; static int pulse_fd = -1; -static bool pulseout_timer_handler(unsigned int *next_interval_us, void *arg) -{ +static bool pulseout_timer_handler(unsigned int *next_interval_us, void *arg) { uint8_t pwm_num = (uint8_t)(int)arg; pulse_index++; @@ -58,11 +57,11 @@ static bool pulseout_timer_handler(unsigned int *next_interval_us, void *arg) return true; } -void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, - const pwmio_pwmout_obj_t* carrier, - const mcu_pin_obj_t* pin, - uint32_t frequency, - uint16_t duty_cycle) { +void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self, + const pwmio_pwmout_obj_t *carrier, + const mcu_pin_obj_t *pin, + uint32_t frequency, + uint16_t duty_cycle) { if (!carrier || pin || frequency) { mp_raise_NotImplementedError(translate("Port does not accept pins or frequency. Construct and pass a PWMOut Carrier instead")); } @@ -110,12 +109,12 @@ void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pu ioctl(pulse_fd, TCIOC_SETTIMEOUT, timeout); sethandler.handler = pulseout_timer_handler; - sethandler.arg = (void *)(int)self->pwm_num; + sethandler.arg = (void *)(int)self->pwm_num; ioctl(pulse_fd, TCIOC_SETHANDLER, (unsigned long)&sethandler); ioctl(pulse_fd, TCIOC_START, 0); - while(pulse_index < len) { + while (pulse_index < len) { // Do other things while we wait. The interrupts will handle sending the // signal. RUN_BACKGROUND_TASKS; diff --git a/ports/cxd56/common-hal/pwmio/PWMOut.c b/ports/cxd56/common-hal/pwmio/PWMOut.c index e0eb7abde..61806540b 100644 --- a/ports/cxd56/common-hal/pwmio/PWMOut.c +++ b/ports/cxd56/common-hal/pwmio/PWMOut.c @@ -33,7 +33,7 @@ #include "shared-bindings/pwmio/PWMOut.h" typedef struct { - const char* devpath; + const char *devpath; const mcu_pin_obj_t *pin; int fd; bool reset; @@ -141,11 +141,11 @@ void common_hal_pwmio_pwmout_reset_ok(pwmio_pwmout_obj_t *self) { void pwmout_reset(void) { for (int i = 0; i < MP_ARRAY_SIZE(pwmout_dev); i++) { if (pwmout_dev[i].fd >= 0 && pwmout_dev[i].reset) { - ioctl(pwmout_dev[i].fd, PWMIOC_STOP, 0); - close(pwmout_dev[i].fd); - pwmout_dev[i].fd = -1; + ioctl(pwmout_dev[i].fd, PWMIOC_STOP, 0); + close(pwmout_dev[i].fd); + pwmout_dev[i].fd = -1; - reset_pin_number(pwmout_dev[i].pin->number); + reset_pin_number(pwmout_dev[i].pin->number); } } } diff --git a/ports/cxd56/common-hal/sdioio/SDCard.c b/ports/cxd56/common-hal/sdioio/SDCard.c index cf7de422c..cf8986a4f 100644 --- a/ports/cxd56/common-hal/sdioio/SDCard.c +++ b/ports/cxd56/common-hal/sdioio/SDCard.c @@ -96,15 +96,15 @@ bool common_hal_sdioio_sdcard_configure(sdioio_sdcard_obj_t *self, uint32_t baud return true; } -uint32_t common_hal_sdioio_sdcard_get_frequency(sdioio_sdcard_obj_t* self) { +uint32_t common_hal_sdioio_sdcard_get_frequency(sdioio_sdcard_obj_t *self) { return self->frequency; } -uint8_t common_hal_sdioio_sdcard_get_width(sdioio_sdcard_obj_t* self) { +uint8_t common_hal_sdioio_sdcard_get_width(sdioio_sdcard_obj_t *self) { return self->width; } -uint32_t common_hal_sdioio_sdcard_get_count(sdioio_sdcard_obj_t* self) { +uint32_t common_hal_sdioio_sdcard_get_count(sdioio_sdcard_obj_t *self) { return self->count; } @@ -114,7 +114,7 @@ STATIC void check_whole_block(mp_buffer_info_t *bufinfo) { } } -int common_hal_sdioio_sdcard_readblocks(sdioio_sdcard_obj_t* self, uint32_t start_block, mp_buffer_info_t *bufinfo) { +int common_hal_sdioio_sdcard_readblocks(sdioio_sdcard_obj_t *self, uint32_t start_block, mp_buffer_info_t *bufinfo) { if (common_hal_sdioio_sdcard_deinited(self)) { raise_deinited_error(); } @@ -123,13 +123,14 @@ int common_hal_sdioio_sdcard_readblocks(sdioio_sdcard_obj_t* self, uint32_t star return self->inode->u.i_bops->read(self->inode, bufinfo->buf, start_block, bufinfo->len / 512); } -int common_hal_sdioio_sdcard_writeblocks(sdioio_sdcard_obj_t* self, uint32_t start_block, mp_buffer_info_t *bufinfo) { +int common_hal_sdioio_sdcard_writeblocks(sdioio_sdcard_obj_t *self, uint32_t start_block, mp_buffer_info_t *bufinfo) { if (common_hal_sdioio_sdcard_deinited(self)) { raise_deinited_error(); } check_whole_block(bufinfo); - return self->inode->u.i_bops->write(self->inode, bufinfo->buf, start_block, bufinfo->len / 512);; + return self->inode->u.i_bops->write(self->inode, bufinfo->buf, start_block, bufinfo->len / 512); + ; } void common_hal_sdioio_sdcard_never_reset(sdioio_sdcard_obj_t *self) { diff --git a/ports/cxd56/common-hal/sdioio/SDCard.h b/ports/cxd56/common-hal/sdioio/SDCard.h index cbdcd4706..04f6ccdba 100644 --- a/ports/cxd56/common-hal/sdioio/SDCard.h +++ b/ports/cxd56/common-hal/sdioio/SDCard.h @@ -35,7 +35,7 @@ typedef struct { mp_obj_base_t base; - struct inode* inode; + struct inode *inode; uint32_t frequency; uint32_t count; uint8_t width; diff --git a/ports/cxd56/common-hal/supervisor/Runtime.c b/ports/cxd56/common-hal/supervisor/Runtime.c index eeeb1430f..6ecdc2581 100755..100644 --- a/ports/cxd56/common-hal/supervisor/Runtime.c +++ b/ports/cxd56/common-hal/supervisor/Runtime.c @@ -28,9 +28,9 @@ #include "supervisor/serial.h" bool common_hal_supervisor_runtime_get_serial_connected(void) { - return (bool) serial_connected(); + return (bool)serial_connected(); } bool common_hal_supervisor_runtime_get_serial_bytes_available(void) { - return (bool) serial_bytes_available(); + return (bool)serial_bytes_available(); } diff --git a/ports/cxd56/fatfs_port.c b/ports/cxd56/fatfs_port.c index e986b4c6e..a58465b98 100644 --- a/ports/cxd56/fatfs_port.c +++ b/ports/cxd56/fatfs_port.c @@ -35,12 +35,12 @@ #endif DWORD get_fattime(void) { -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC timeutils_struct_time_t tm; common_hal_rtc_get_time(&tm); return ((tm.tm_year - 1980) << 25) | (tm.tm_mon << 21) | (tm.tm_mday << 16) | - (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); -#else + (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); + #else return ((2016 - 1980) << 25) | ((9) << 21) | ((1) << 16) | ((16) << 11) | ((43) << 5) | (35 / 2); -#endif + #endif } diff --git a/ports/cxd56/mkspk/clefia.c b/ports/cxd56/mkspk/clefia.c index 02a175505..e946ee534 100644 --- a/ports/cxd56/mkspk/clefia.c +++ b/ports/cxd56/mkspk/clefia.c @@ -60,458 +60,424 @@ static const unsigned char clefia_s0[256] = { - 0x57u, 0x49u, 0xd1u, 0xc6u, 0x2fu, 0x33u, 0x74u, 0xfbu, - 0x95u, 0x6du, 0x82u, 0xeau, 0x0eu, 0xb0u, 0xa8u, 0x1cu, - 0x28u, 0xd0u, 0x4bu, 0x92u, 0x5cu, 0xeeu, 0x85u, 0xb1u, - 0xc4u, 0x0au, 0x76u, 0x3du, 0x63u, 0xf9u, 0x17u, 0xafu, - 0xbfu, 0xa1u, 0x19u, 0x65u, 0xf7u, 0x7au, 0x32u, 0x20u, - 0x06u, 0xceu, 0xe4u, 0x83u, 0x9du, 0x5bu, 0x4cu, 0xd8u, - 0x42u, 0x5du, 0x2eu, 0xe8u, 0xd4u, 0x9bu, 0x0fu, 0x13u, - 0x3cu, 0x89u, 0x67u, 0xc0u, 0x71u, 0xaau, 0xb6u, 0xf5u, - 0xa4u, 0xbeu, 0xfdu, 0x8cu, 0x12u, 0x00u, 0x97u, 0xdau, - 0x78u, 0xe1u, 0xcfu, 0x6bu, 0x39u, 0x43u, 0x55u, 0x26u, - 0x30u, 0x98u, 0xccu, 0xddu, 0xebu, 0x54u, 0xb3u, 0x8fu, - 0x4eu, 0x16u, 0xfau, 0x22u, 0xa5u, 0x77u, 0x09u, 0x61u, - 0xd6u, 0x2au, 0x53u, 0x37u, 0x45u, 0xc1u, 0x6cu, 0xaeu, - 0xefu, 0x70u, 0x08u, 0x99u, 0x8bu, 0x1du, 0xf2u, 0xb4u, - 0xe9u, 0xc7u, 0x9fu, 0x4au, 0x31u, 0x25u, 0xfeu, 0x7cu, - 0xd3u, 0xa2u, 0xbdu, 0x56u, 0x14u, 0x88u, 0x60u, 0x0bu, - 0xcdu, 0xe2u, 0x34u, 0x50u, 0x9eu, 0xdcu, 0x11u, 0x05u, - 0x2bu, 0xb7u, 0xa9u, 0x48u, 0xffu, 0x66u, 0x8au, 0x73u, - 0x03u, 0x75u, 0x86u, 0xf1u, 0x6au, 0xa7u, 0x40u, 0xc2u, - 0xb9u, 0x2cu, 0xdbu, 0x1fu, 0x58u, 0x94u, 0x3eu, 0xedu, - 0xfcu, 0x1bu, 0xa0u, 0x04u, 0xb8u, 0x8du, 0xe6u, 0x59u, - 0x62u, 0x93u, 0x35u, 0x7eu, 0xcau, 0x21u, 0xdfu, 0x47u, - 0x15u, 0xf3u, 0xbau, 0x7fu, 0xa6u, 0x69u, 0xc8u, 0x4du, - 0x87u, 0x3bu, 0x9cu, 0x01u, 0xe0u, 0xdeu, 0x24u, 0x52u, - 0x7bu, 0x0cu, 0x68u, 0x1eu, 0x80u, 0xb2u, 0x5au, 0xe7u, - 0xadu, 0xd5u, 0x23u, 0xf4u, 0x46u, 0x3fu, 0x91u, 0xc9u, - 0x6eu, 0x84u, 0x72u, 0xbbu, 0x0du, 0x18u, 0xd9u, 0x96u, - 0xf0u, 0x5fu, 0x41u, 0xacu, 0x27u, 0xc5u, 0xe3u, 0x3au, - 0x81u, 0x6fu, 0x07u, 0xa3u, 0x79u, 0xf6u, 0x2du, 0x38u, - 0x1au, 0x44u, 0x5eu, 0xb5u, 0xd2u, 0xecu, 0xcbu, 0x90u, - 0x9au, 0x36u, 0xe5u, 0x29u, 0xc3u, 0x4fu, 0xabu, 0x64u, - 0x51u, 0xf8u, 0x10u, 0xd7u, 0xbcu, 0x02u, 0x7du, 0x8eu + 0x57u, 0x49u, 0xd1u, 0xc6u, 0x2fu, 0x33u, 0x74u, 0xfbu, + 0x95u, 0x6du, 0x82u, 0xeau, 0x0eu, 0xb0u, 0xa8u, 0x1cu, + 0x28u, 0xd0u, 0x4bu, 0x92u, 0x5cu, 0xeeu, 0x85u, 0xb1u, + 0xc4u, 0x0au, 0x76u, 0x3du, 0x63u, 0xf9u, 0x17u, 0xafu, + 0xbfu, 0xa1u, 0x19u, 0x65u, 0xf7u, 0x7au, 0x32u, 0x20u, + 0x06u, 0xceu, 0xe4u, 0x83u, 0x9du, 0x5bu, 0x4cu, 0xd8u, + 0x42u, 0x5du, 0x2eu, 0xe8u, 0xd4u, 0x9bu, 0x0fu, 0x13u, + 0x3cu, 0x89u, 0x67u, 0xc0u, 0x71u, 0xaau, 0xb6u, 0xf5u, + 0xa4u, 0xbeu, 0xfdu, 0x8cu, 0x12u, 0x00u, 0x97u, 0xdau, + 0x78u, 0xe1u, 0xcfu, 0x6bu, 0x39u, 0x43u, 0x55u, 0x26u, + 0x30u, 0x98u, 0xccu, 0xddu, 0xebu, 0x54u, 0xb3u, 0x8fu, + 0x4eu, 0x16u, 0xfau, 0x22u, 0xa5u, 0x77u, 0x09u, 0x61u, + 0xd6u, 0x2au, 0x53u, 0x37u, 0x45u, 0xc1u, 0x6cu, 0xaeu, + 0xefu, 0x70u, 0x08u, 0x99u, 0x8bu, 0x1du, 0xf2u, 0xb4u, + 0xe9u, 0xc7u, 0x9fu, 0x4au, 0x31u, 0x25u, 0xfeu, 0x7cu, + 0xd3u, 0xa2u, 0xbdu, 0x56u, 0x14u, 0x88u, 0x60u, 0x0bu, + 0xcdu, 0xe2u, 0x34u, 0x50u, 0x9eu, 0xdcu, 0x11u, 0x05u, + 0x2bu, 0xb7u, 0xa9u, 0x48u, 0xffu, 0x66u, 0x8au, 0x73u, + 0x03u, 0x75u, 0x86u, 0xf1u, 0x6au, 0xa7u, 0x40u, 0xc2u, + 0xb9u, 0x2cu, 0xdbu, 0x1fu, 0x58u, 0x94u, 0x3eu, 0xedu, + 0xfcu, 0x1bu, 0xa0u, 0x04u, 0xb8u, 0x8du, 0xe6u, 0x59u, + 0x62u, 0x93u, 0x35u, 0x7eu, 0xcau, 0x21u, 0xdfu, 0x47u, + 0x15u, 0xf3u, 0xbau, 0x7fu, 0xa6u, 0x69u, 0xc8u, 0x4du, + 0x87u, 0x3bu, 0x9cu, 0x01u, 0xe0u, 0xdeu, 0x24u, 0x52u, + 0x7bu, 0x0cu, 0x68u, 0x1eu, 0x80u, 0xb2u, 0x5au, 0xe7u, + 0xadu, 0xd5u, 0x23u, 0xf4u, 0x46u, 0x3fu, 0x91u, 0xc9u, + 0x6eu, 0x84u, 0x72u, 0xbbu, 0x0du, 0x18u, 0xd9u, 0x96u, + 0xf0u, 0x5fu, 0x41u, 0xacu, 0x27u, 0xc5u, 0xe3u, 0x3au, + 0x81u, 0x6fu, 0x07u, 0xa3u, 0x79u, 0xf6u, 0x2du, 0x38u, + 0x1au, 0x44u, 0x5eu, 0xb5u, 0xd2u, 0xecu, 0xcbu, 0x90u, + 0x9au, 0x36u, 0xe5u, 0x29u, 0xc3u, 0x4fu, 0xabu, 0x64u, + 0x51u, 0xf8u, 0x10u, 0xd7u, 0xbcu, 0x02u, 0x7du, 0x8eu }; /* S1 (8-bit S-box based on inverse function) */ static const unsigned char clefia_s1[256] = { - 0x6cu, 0xdau, 0xc3u, 0xe9u, 0x4eu, 0x9du, 0x0au, 0x3du, - 0xb8u, 0x36u, 0xb4u, 0x38u, 0x13u, 0x34u, 0x0cu, 0xd9u, - 0xbfu, 0x74u, 0x94u, 0x8fu, 0xb7u, 0x9cu, 0xe5u, 0xdcu, - 0x9eu, 0x07u, 0x49u, 0x4fu, 0x98u, 0x2cu, 0xb0u, 0x93u, - 0x12u, 0xebu, 0xcdu, 0xb3u, 0x92u, 0xe7u, 0x41u, 0x60u, - 0xe3u, 0x21u, 0x27u, 0x3bu, 0xe6u, 0x19u, 0xd2u, 0x0eu, - 0x91u, 0x11u, 0xc7u, 0x3fu, 0x2au, 0x8eu, 0xa1u, 0xbcu, - 0x2bu, 0xc8u, 0xc5u, 0x0fu, 0x5bu, 0xf3u, 0x87u, 0x8bu, - 0xfbu, 0xf5u, 0xdeu, 0x20u, 0xc6u, 0xa7u, 0x84u, 0xceu, - 0xd8u, 0x65u, 0x51u, 0xc9u, 0xa4u, 0xefu, 0x43u, 0x53u, - 0x25u, 0x5du, 0x9bu, 0x31u, 0xe8u, 0x3eu, 0x0du, 0xd7u, - 0x80u, 0xffu, 0x69u, 0x8au, 0xbau, 0x0bu, 0x73u, 0x5cu, - 0x6eu, 0x54u, 0x15u, 0x62u, 0xf6u, 0x35u, 0x30u, 0x52u, - 0xa3u, 0x16u, 0xd3u, 0x28u, 0x32u, 0xfau, 0xaau, 0x5eu, - 0xcfu, 0xeau, 0xedu, 0x78u, 0x33u, 0x58u, 0x09u, 0x7bu, - 0x63u, 0xc0u, 0xc1u, 0x46u, 0x1eu, 0xdfu, 0xa9u, 0x99u, - 0x55u, 0x04u, 0xc4u, 0x86u, 0x39u, 0x77u, 0x82u, 0xecu, - 0x40u, 0x18u, 0x90u, 0x97u, 0x59u, 0xddu, 0x83u, 0x1fu, - 0x9au, 0x37u, 0x06u, 0x24u, 0x64u, 0x7cu, 0xa5u, 0x56u, - 0x48u, 0x08u, 0x85u, 0xd0u, 0x61u, 0x26u, 0xcau, 0x6fu, - 0x7eu, 0x6au, 0xb6u, 0x71u, 0xa0u, 0x70u, 0x05u, 0xd1u, - 0x45u, 0x8cu, 0x23u, 0x1cu, 0xf0u, 0xeeu, 0x89u, 0xadu, - 0x7au, 0x4bu, 0xc2u, 0x2fu, 0xdbu, 0x5au, 0x4du, 0x76u, - 0x67u, 0x17u, 0x2du, 0xf4u, 0xcbu, 0xb1u, 0x4au, 0xa8u, - 0xb5u, 0x22u, 0x47u, 0x3au, 0xd5u, 0x10u, 0x4cu, 0x72u, - 0xccu, 0x00u, 0xf9u, 0xe0u, 0xfdu, 0xe2u, 0xfeu, 0xaeu, - 0xf8u, 0x5fu, 0xabu, 0xf1u, 0x1bu, 0x42u, 0x81u, 0xd6u, - 0xbeu, 0x44u, 0x29u, 0xa6u, 0x57u, 0xb9u, 0xafu, 0xf2u, - 0xd4u, 0x75u, 0x66u, 0xbbu, 0x68u, 0x9fu, 0x50u, 0x02u, - 0x01u, 0x3cu, 0x7fu, 0x8du, 0x1au, 0x88u, 0xbdu, 0xacu, - 0xf7u, 0xe4u, 0x79u, 0x96u, 0xa2u, 0xfcu, 0x6du, 0xb2u, - 0x6bu, 0x03u, 0xe1u, 0x2eu, 0x7du, 0x14u, 0x95u, 0x1du + 0x6cu, 0xdau, 0xc3u, 0xe9u, 0x4eu, 0x9du, 0x0au, 0x3du, + 0xb8u, 0x36u, 0xb4u, 0x38u, 0x13u, 0x34u, 0x0cu, 0xd9u, + 0xbfu, 0x74u, 0x94u, 0x8fu, 0xb7u, 0x9cu, 0xe5u, 0xdcu, + 0x9eu, 0x07u, 0x49u, 0x4fu, 0x98u, 0x2cu, 0xb0u, 0x93u, + 0x12u, 0xebu, 0xcdu, 0xb3u, 0x92u, 0xe7u, 0x41u, 0x60u, + 0xe3u, 0x21u, 0x27u, 0x3bu, 0xe6u, 0x19u, 0xd2u, 0x0eu, + 0x91u, 0x11u, 0xc7u, 0x3fu, 0x2au, 0x8eu, 0xa1u, 0xbcu, + 0x2bu, 0xc8u, 0xc5u, 0x0fu, 0x5bu, 0xf3u, 0x87u, 0x8bu, + 0xfbu, 0xf5u, 0xdeu, 0x20u, 0xc6u, 0xa7u, 0x84u, 0xceu, + 0xd8u, 0x65u, 0x51u, 0xc9u, 0xa4u, 0xefu, 0x43u, 0x53u, + 0x25u, 0x5du, 0x9bu, 0x31u, 0xe8u, 0x3eu, 0x0du, 0xd7u, + 0x80u, 0xffu, 0x69u, 0x8au, 0xbau, 0x0bu, 0x73u, 0x5cu, + 0x6eu, 0x54u, 0x15u, 0x62u, 0xf6u, 0x35u, 0x30u, 0x52u, + 0xa3u, 0x16u, 0xd3u, 0x28u, 0x32u, 0xfau, 0xaau, 0x5eu, + 0xcfu, 0xeau, 0xedu, 0x78u, 0x33u, 0x58u, 0x09u, 0x7bu, + 0x63u, 0xc0u, 0xc1u, 0x46u, 0x1eu, 0xdfu, 0xa9u, 0x99u, + 0x55u, 0x04u, 0xc4u, 0x86u, 0x39u, 0x77u, 0x82u, 0xecu, + 0x40u, 0x18u, 0x90u, 0x97u, 0x59u, 0xddu, 0x83u, 0x1fu, + 0x9au, 0x37u, 0x06u, 0x24u, 0x64u, 0x7cu, 0xa5u, 0x56u, + 0x48u, 0x08u, 0x85u, 0xd0u, 0x61u, 0x26u, 0xcau, 0x6fu, + 0x7eu, 0x6au, 0xb6u, 0x71u, 0xa0u, 0x70u, 0x05u, 0xd1u, + 0x45u, 0x8cu, 0x23u, 0x1cu, 0xf0u, 0xeeu, 0x89u, 0xadu, + 0x7au, 0x4bu, 0xc2u, 0x2fu, 0xdbu, 0x5au, 0x4du, 0x76u, + 0x67u, 0x17u, 0x2du, 0xf4u, 0xcbu, 0xb1u, 0x4au, 0xa8u, + 0xb5u, 0x22u, 0x47u, 0x3au, 0xd5u, 0x10u, 0x4cu, 0x72u, + 0xccu, 0x00u, 0xf9u, 0xe0u, 0xfdu, 0xe2u, 0xfeu, 0xaeu, + 0xf8u, 0x5fu, 0xabu, 0xf1u, 0x1bu, 0x42u, 0x81u, 0xd6u, + 0xbeu, 0x44u, 0x29u, 0xa6u, 0x57u, 0xb9u, 0xafu, 0xf2u, + 0xd4u, 0x75u, 0x66u, 0xbbu, 0x68u, 0x9fu, 0x50u, 0x02u, + 0x01u, 0x3cu, 0x7fu, 0x8du, 0x1au, 0x88u, 0xbdu, 0xacu, + 0xf7u, 0xe4u, 0x79u, 0x96u, 0xa2u, 0xfcu, 0x6du, 0xb2u, + 0x6bu, 0x03u, 0xe1u, 0x2eu, 0x7du, 0x14u, 0x95u, 0x1du }; /**************************************************************************** * Private Functions ****************************************************************************/ -static void bytecpy(unsigned char *dst, const unsigned char *src, int bytelen) -{ - while (bytelen-- > 0) - { - *dst++ = *src++; +static void bytecpy(unsigned char *dst, const unsigned char *src, int bytelen) { + while (bytelen-- > 0) { + *dst++ = *src++; } } -static unsigned char clefiamul2(unsigned char x) -{ - /* multiplication over GF(2^8) (p(x) = '11d') */ +static unsigned char clefiamul2(unsigned char x) { + /* multiplication over GF(2^8) (p(x) = '11d') */ - if (x & 0x80u) - { - x ^= 0x0eu; + if (x & 0x80u) { + x ^= 0x0eu; } - return ((x << 1) | (x >> 7)); + return (x << 1) | (x >> 7); } static void clefiaf0xor(unsigned char *dst, const unsigned char *src, - const unsigned char *rk) -{ - unsigned char x[4]; - unsigned char y[4]; - unsigned char z[4]; + const unsigned char *rk) { + unsigned char x[4]; + unsigned char y[4]; + unsigned char z[4]; - /* F0 */ + /* F0 */ - /* Key addition */ + /* Key addition */ - bytexor(x, src, rk, 4); + bytexor(x, src, rk, 4); - /* Substitution layer */ + /* Substitution layer */ - z[0] = clefia_s0[x[0]]; - z[1] = clefia_s1[x[1]]; - z[2] = clefia_s0[x[2]]; - z[3] = clefia_s1[x[3]]; + z[0] = clefia_s0[x[0]]; + z[1] = clefia_s1[x[1]]; + z[2] = clefia_s0[x[2]]; + z[3] = clefia_s1[x[3]]; - /* Diffusion layer (M0) */ + /* Diffusion layer (M0) */ - y[0] = z[0] ^ clefiamul2(z[1]) ^ clefiamul4(z[2]) ^ clefiamul6(z[3]); - y[1] = clefiamul2(z[0]) ^ z[1] ^ clefiamul6(z[2]) ^ clefiamul4(z[3]); - y[2] = clefiamul4(z[0]) ^ clefiamul6(z[1]) ^ z[2] ^ clefiamul2(z[3]); - y[3] = clefiamul6(z[0]) ^ clefiamul4(z[1]) ^ clefiamul2(z[2]) ^ z[3]; + y[0] = z[0] ^ clefiamul2(z[1]) ^ clefiamul4(z[2]) ^ clefiamul6(z[3]); + y[1] = clefiamul2(z[0]) ^ z[1] ^ clefiamul6(z[2]) ^ clefiamul4(z[3]); + y[2] = clefiamul4(z[0]) ^ clefiamul6(z[1]) ^ z[2] ^ clefiamul2(z[3]); + y[3] = clefiamul6(z[0]) ^ clefiamul4(z[1]) ^ clefiamul2(z[2]) ^ z[3]; - /* Xoring after F0 */ + /* Xoring after F0 */ - bytecpy(dst + 0, src + 0, 4); - bytexor(dst + 4, src + 4, y, 4); + bytecpy(dst + 0, src + 0, 4); + bytexor(dst + 4, src + 4, y, 4); } static void clefiaf1xor(unsigned char *dst, const unsigned char *src, - const unsigned char *rk) -{ - unsigned char x[4]; - unsigned char y[4]; - unsigned char z[4]; + const unsigned char *rk) { + unsigned char x[4]; + unsigned char y[4]; + unsigned char z[4]; - /* F1 */ + /* F1 */ - /* Key addition */ + /* Key addition */ - bytexor(x, src, rk, 4); + bytexor(x, src, rk, 4); - /* Substitution layer */ + /* Substitution layer */ - z[0] = clefia_s1[x[0]]; - z[1] = clefia_s0[x[1]]; - z[2] = clefia_s1[x[2]]; - z[3] = clefia_s0[x[3]]; + z[0] = clefia_s1[x[0]]; + z[1] = clefia_s0[x[1]]; + z[2] = clefia_s1[x[2]]; + z[3] = clefia_s0[x[3]]; - /* Diffusion layer (M1) */ + /* Diffusion layer (M1) */ - y[0] = z[0] ^ clefiamul8(z[1]) ^ clefiamul2(z[2]) ^ clefiamula(z[3]); - y[1] = clefiamul8(z[0]) ^ z[1] ^ clefiamula(z[2]) ^ clefiamul2(z[3]); - y[2] = clefiamul2(z[0]) ^ clefiamula(z[1]) ^ z[2] ^ clefiamul8(z[3]); - y[3] = clefiamula(z[0]) ^ clefiamul2(z[1]) ^ clefiamul8(z[2]) ^ z[3]; + y[0] = z[0] ^ clefiamul8(z[1]) ^ clefiamul2(z[2]) ^ clefiamula(z[3]); + y[1] = clefiamul8(z[0]) ^ z[1] ^ clefiamula(z[2]) ^ clefiamul2(z[3]); + y[2] = clefiamul2(z[0]) ^ clefiamula(z[1]) ^ z[2] ^ clefiamul8(z[3]); + y[3] = clefiamula(z[0]) ^ clefiamul2(z[1]) ^ clefiamul8(z[2]) ^ z[3]; - /* Xoring after F1 */ + /* Xoring after F1 */ - bytecpy(dst + 0, src + 0, 4); - bytexor(dst + 4, src + 4, y, 4); + bytecpy(dst + 0, src + 0, 4); + bytexor(dst + 4, src + 4, y, 4); } static void clefiagfn4(unsigned char *y, const unsigned char *x, - const unsigned char *rk, int r) -{ - unsigned char fin[16]; - unsigned char fout[16]; - - bytecpy(fin, x, 16); - while (r-- > 0) - { - clefiaf0xor(fout + 0, fin + 0, rk + 0); - clefiaf1xor(fout + 8, fin + 8, rk + 4); - rk += 8; - if (r) - { - /* swapping for encryption */ - - bytecpy(fin + 0, fout + 4, 12); - bytecpy(fin + 12, fout + 0, 4); + const unsigned char *rk, int r) { + unsigned char fin[16]; + unsigned char fout[16]; + + bytecpy(fin, x, 16); + while (r-- > 0) { + clefiaf0xor(fout + 0, fin + 0, rk + 0); + clefiaf1xor(fout + 8, fin + 8, rk + 4); + rk += 8; + if (r) { + /* swapping for encryption */ + + bytecpy(fin + 0, fout + 4, 12); + bytecpy(fin + 12, fout + 0, 4); } } - bytecpy(y, fout, 16); + bytecpy(y, fout, 16); } #if 0 /* Not used */ static void clefiagfn8(unsigned char *y, const unsigned char *x, - const unsigned char *rk, int r) -{ - unsigned char fin[32]; - unsigned char fout[32]; - - bytecpy(fin, x, 32); - while (r-- > 0) - { - clefiaf0xor(fout + 0, fin + 0, rk + 0); - clefiaf1xor(fout + 8, fin + 8, rk + 4); - clefiaf0xor(fout + 16, fin + 16, rk + 8); - clefiaf1xor(fout + 24, fin + 24, rk + 12); - rk += 16; - if (r) - { - /* swapping for encryption */ - - bytecpy(fin + 0, fout + 4, 28); - bytecpy(fin + 28, fout + 0, 4); + const unsigned char *rk, int r) { + unsigned char fin[32]; + unsigned char fout[32]; + + bytecpy(fin, x, 32); + while (r-- > 0) { + clefiaf0xor(fout + 0, fin + 0, rk + 0); + clefiaf1xor(fout + 8, fin + 8, rk + 4); + clefiaf0xor(fout + 16, fin + 16, rk + 8); + clefiaf1xor(fout + 24, fin + 24, rk + 12); + rk += 16; + if (r) { + /* swapping for encryption */ + + bytecpy(fin + 0, fout + 4, 28); + bytecpy(fin + 28, fout + 0, 4); } } - bytecpy(y, fout, 32); + bytecpy(y, fout, 32); } #endif #if 0 /* Not used */ static void clefiagfn4inv(unsigned char *y, const unsigned char *x, - const unsigned char *rk, int r) -{ - unsigned char fin[16]; - unsigned char fout[16]; - - rk += (r - 1) * 8; - bytecpy(fin, x, 16); - while (r-- > 0) - { - clefiaf0xor(fout + 0, fin + 0, rk + 0); - clefiaf1xor(fout + 8, fin + 8, rk + 4); - rk -= 8; - if (r) - { - /* swapping for decryption */ - - bytecpy(fin + 0, fout + 12, 4); - bytecpy(fin + 4, fout + 0, 12); + const unsigned char *rk, int r) { + unsigned char fin[16]; + unsigned char fout[16]; + + rk += (r - 1) * 8; + bytecpy(fin, x, 16); + while (r-- > 0) { + clefiaf0xor(fout + 0, fin + 0, rk + 0); + clefiaf1xor(fout + 8, fin + 8, rk + 4); + rk -= 8; + if (r) { + /* swapping for decryption */ + + bytecpy(fin + 0, fout + 12, 4); + bytecpy(fin + 4, fout + 0, 12); } } - bytecpy(y, fout, 16); + bytecpy(y, fout, 16); } #endif -static void clefiadoubleswap(unsigned char *lk) -{ - unsigned char t[16]; - - t[0] = (lk[0] << 7) | (lk[1] >> 1); - t[1] = (lk[1] << 7) | (lk[2] >> 1); - t[2] = (lk[2] << 7) | (lk[3] >> 1); - t[3] = (lk[3] << 7) | (lk[4] >> 1); - t[4] = (lk[4] << 7) | (lk[5] >> 1); - t[5] = (lk[5] << 7) | (lk[6] >> 1); - t[6] = (lk[6] << 7) | (lk[7] >> 1); - t[7] = (lk[7] << 7) | (lk[15] & 0x7fu); - - t[8] = (lk[8] >> 7) | (lk[0] & 0xfeu); - t[9] = (lk[9] >> 7) | (lk[8] << 1); - t[10] = (lk[10] >> 7) | (lk[9] << 1); - t[11] = (lk[11] >> 7) | (lk[10] << 1); - t[12] = (lk[12] >> 7) | (lk[11] << 1); - t[13] = (lk[13] >> 7) | (lk[12] << 1); - t[14] = (lk[14] >> 7) | (lk[13] << 1); - t[15] = (lk[15] >> 7) | (lk[14] << 1); - - bytecpy(lk, t, 16); +static void clefiadoubleswap(unsigned char *lk) { + unsigned char t[16]; + + t[0] = (lk[0] << 7) | (lk[1] >> 1); + t[1] = (lk[1] << 7) | (lk[2] >> 1); + t[2] = (lk[2] << 7) | (lk[3] >> 1); + t[3] = (lk[3] << 7) | (lk[4] >> 1); + t[4] = (lk[4] << 7) | (lk[5] >> 1); + t[5] = (lk[5] << 7) | (lk[6] >> 1); + t[6] = (lk[6] << 7) | (lk[7] >> 1); + t[7] = (lk[7] << 7) | (lk[15] & 0x7fu); + + t[8] = (lk[8] >> 7) | (lk[0] & 0xfeu); + t[9] = (lk[9] >> 7) | (lk[8] << 1); + t[10] = (lk[10] >> 7) | (lk[9] << 1); + t[11] = (lk[11] >> 7) | (lk[10] << 1); + t[12] = (lk[12] >> 7) | (lk[11] << 1); + t[13] = (lk[13] >> 7) | (lk[12] << 1); + t[14] = (lk[14] >> 7) | (lk[13] << 1); + t[15] = (lk[15] >> 7) | (lk[14] << 1); + + bytecpy(lk, t, 16); } -static void clefiaconset(unsigned char *con, const unsigned char *iv, int lk) -{ - unsigned char t[2]; - unsigned char tmp; - - bytecpy(t, iv, 2); - while (lk-- > 0) - { - con[0] = t[0] ^ 0xb7u; /* P_16 = 0xb7e1 (natural logarithm) */ - con[1] = t[1] ^ 0xe1u; - con[2] = ~((t[0] << 1) | (t[1] >> 7)); - con[3] = ~((t[1] << 1) | (t[0] >> 7)); - con[4] = ~t[0] ^ 0x24u; /* Q_16 = 0x243f (circle ratio) */ - con[5] = ~t[1] ^ 0x3fu; - con[6] = t[1]; - con[7] = t[0]; - con += 8; - - /* updating T */ - - if (t[1] & 0x01u) - { - t[0] ^= 0xa8u; - t[1] ^= 0x30u; +static void clefiaconset(unsigned char *con, const unsigned char *iv, int lk) { + unsigned char t[2]; + unsigned char tmp; + + bytecpy(t, iv, 2); + while (lk-- > 0) { + con[0] = t[0] ^ 0xb7u; /* P_16 = 0xb7e1 (natural logarithm) */ + con[1] = t[1] ^ 0xe1u; + con[2] = ~((t[0] << 1) | (t[1] >> 7)); + con[3] = ~((t[1] << 1) | (t[0] >> 7)); + con[4] = ~t[0] ^ 0x24u; /* Q_16 = 0x243f (circle ratio) */ + con[5] = ~t[1] ^ 0x3fu; + con[6] = t[1]; + con[7] = t[0]; + con += 8; + + /* updating T */ + + if (t[1] & 0x01u) { + t[0] ^= 0xa8u; + t[1] ^= 0x30u; } - tmp = t[0] << 7; - t[0] = (t[0] >> 1) | (t[1] << 7); - t[1] = (t[1] >> 1) | tmp; + tmp = t[0] << 7; + t[0] = (t[0] >> 1) | (t[1] << 7); + t[1] = (t[1] >> 1) | tmp; } } -static void left_shift_one(uint8_t * in, uint8_t * out) -{ - int i; - int overflow; +static void left_shift_one(uint8_t *in, uint8_t *out) { + int i; + int overflow; - overflow = 0; - for (i = 15; i >= 0; i--) + overflow = 0; + for (i = 15; i >= 0; i--) { - out[i] = in[i] << 1; - out[i] |= overflow; - overflow = (in[i] >> 7) & 1; + out[i] = in[i] << 1; + out[i] |= overflow; + overflow = (in[i] >> 7) & 1; } } -static void gen_subkey(struct cipher *c) -{ - uint8_t L[16]; +static void gen_subkey(struct cipher *c) { + uint8_t L[16]; - memset(L, 0, 16); - clefiaencrypt(L, L, c->rk, c->round); + memset(L, 0, 16); + clefiaencrypt(L, L, c->rk, c->round); - left_shift_one(L, c->k1); - if (L[0] & 0x80) - { - c->k1[15] = c->k1[15] ^ 0x87; + left_shift_one(L, c->k1); + if (L[0] & 0x80) { + c->k1[15] = c->k1[15] ^ 0x87; } - left_shift_one(c->k1, c->k2); - if (c->k1[0] & 0x80) - { - c->k2[15] = c->k2[15] ^ 0x87; + left_shift_one(c->k1, c->k2); + if (c->k1[0] & 0x80) { + c->k2[15] = c->k2[15] ^ 0x87; } - memset(L, 0, 16); + memset(L, 0, 16); } /**************************************************************************** * Public Functions ****************************************************************************/ -struct cipher *cipher_init(uint8_t * key, uint8_t * iv) -{ - struct cipher *c; +struct cipher *cipher_init(uint8_t *key, uint8_t *iv) { + struct cipher *c; - c = (struct cipher *)malloc(sizeof(*c)); - if (!c) - { - return NULL; + c = (struct cipher *)malloc(sizeof(*c)); + if (!c) { + return NULL; } - c->round = clefiakeyset(c->rk, key); + c->round = clefiakeyset(c->rk, key); - gen_subkey(c); - memset(c->vector, 0, 16); + gen_subkey(c); + memset(c->vector, 0, 16); - return c; + return c; } -void cipher_deinit(struct cipher *c) -{ - memset(c, 0, sizeof(*c)); - free(c); +void cipher_deinit(struct cipher *c) { + memset(c, 0, sizeof(*c)); + free(c); } -int cipher_calc_cmac(struct cipher *c, void *data, int size, void *cmac) -{ - uint8_t m[16]; - uint8_t *p; +int cipher_calc_cmac(struct cipher *c, void *data, int size, void *cmac) { + uint8_t m[16]; + uint8_t *p; - if (size & 0xf) - { - return -1; + if (size & 0xf) { + return -1; } - p = (uint8_t *) data; - while (size) - { - bytexor(m, c->vector, p, 16); - clefiaencrypt(c->vector, m, c->rk, c->round); - size -= 16; - p += 16; + p = (uint8_t *)data; + while (size) { + bytexor(m, c->vector, p, 16); + clefiaencrypt(c->vector, m, c->rk, c->round); + size -= 16; + p += 16; } - bytexor(cmac, m, c->k1, 16); - clefiaencrypt(cmac, cmac, c->rk, c->round); - memset(m, 0, 16); + bytexor(cmac, m, c->k1, 16); + clefiaencrypt(cmac, cmac, c->rk, c->round); + memset(m, 0, 16); - return 0; + return 0; } void bytexor(unsigned char *dst, const unsigned char *a, - const unsigned char *b, int bytelen) -{ - while (bytelen-- > 0) - { - *dst++ = *a++ ^ *b++; + const unsigned char *b, int bytelen) { + while (bytelen-- > 0) { + *dst++ = *a++ ^ *b++; } } -int clefiakeyset(unsigned char *rk, const unsigned char *skey) -{ - const unsigned char iv[2] = - { - 0x42u, 0x8au /* cubic root of 2 */ - }; +int clefiakeyset(unsigned char *rk, const unsigned char *skey) { + const unsigned char iv[2] = + { + 0x42u, 0x8au /* cubic root of 2 */ + }; - unsigned char lk[16]; - unsigned char con128[4 * 60]; - int i; + unsigned char lk[16]; + unsigned char con128[4 * 60]; + int i; - /* generating CONi^(128) (0 <= i < 60, lk = 30) */ + /* generating CONi^(128) (0 <= i < 60, lk = 30) */ - clefiaconset(con128, iv, 30); + clefiaconset(con128, iv, 30); - /* GFN_{4,12} (generating L from K) */ + /* GFN_{4,12} (generating L from K) */ - clefiagfn4(lk, skey, con128, 12); + clefiagfn4(lk, skey, con128, 12); - bytecpy(rk, skey, 8); /* initial whitening key (WK0, WK1) */ - rk += 8; - for (i = 0; i < 9; i++) + bytecpy(rk, skey, 8); /* initial whitening key (WK0, WK1) */ + rk += 8; + for (i = 0; i < 9; i++) { - /* round key (RKi (0 <= i < 36)) */ + /* round key (RKi (0 <= i < 36)) */ - bytexor(rk, lk, con128 + i * 16 + (4 * 24), 16); - if (i % 2) - { - bytexor(rk, rk, skey, 16); /* Xoring K */ + bytexor(rk, lk, con128 + i * 16 + (4 * 24), 16); + if (i % 2) { + bytexor(rk, rk, skey, 16); /* Xoring K */ } - clefiadoubleswap(lk); /* Updating L (DoubleSwap function) */ - rk += 16; + clefiadoubleswap(lk); /* Updating L (DoubleSwap function) */ + rk += 16; } - bytecpy(rk, skey + 8, 8); /* final whitening key (WK2, WK3) */ + bytecpy(rk, skey + 8, 8); /* final whitening key (WK2, WK3) */ - return 18; + return 18; } void clefiaencrypt(unsigned char *ct, const unsigned char *pt, - const unsigned char *rk, const int r) -{ - unsigned char rin[16]; - unsigned char rout[16]; + const unsigned char *rk, const int r) { + unsigned char rin[16]; + unsigned char rout[16]; - bytecpy(rin, pt, 16); + bytecpy(rin, pt, 16); - bytexor(rin + 4, rin + 4, rk + 0, 4); /* initial key whitening */ - bytexor(rin + 12, rin + 12, rk + 4, 4); - rk += 8; + bytexor(rin + 4, rin + 4, rk + 0, 4); /* initial key whitening */ + bytexor(rin + 12, rin + 12, rk + 4, 4); + rk += 8; - clefiagfn4(rout, rin, rk, r); /* GFN_{4,r} */ + clefiagfn4(rout, rin, rk, r); /* GFN_{4,r} */ - bytecpy(ct, rout, 16); - bytexor(ct + 4, ct + 4, rk + r * 8 + 0, 4); /* final key whitening */ - bytexor(ct + 12, ct + 12, rk + r * 8 + 4, 4); + bytecpy(ct, rout, 16); + bytexor(ct + 4, ct + 4, rk + r * 8 + 0, 4); /* final key whitening */ + bytexor(ct + 12, ct + 12, rk + r * 8 + 4, 4); } diff --git a/ports/cxd56/mkspk/clefia.h b/ports/cxd56/mkspk/clefia.h index a0e02587d..0d6764371 100644 --- a/ports/cxd56/mkspk/clefia.h +++ b/ports/cxd56/mkspk/clefia.h @@ -39,7 +39,7 @@ ****************************************************************************/ struct cipher - { +{ int mode; int dir; uint8_t rk[8 * 26 + 16]; @@ -47,19 +47,19 @@ struct cipher int round; uint8_t k1[16]; uint8_t k2[16]; - }; +}; /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -struct cipher *cipher_init(uint8_t * key, uint8_t * iv); +struct cipher *cipher_init(uint8_t *key, uint8_t *iv); void cipher_deinit(struct cipher *c); int cipher_calc_cmac(struct cipher *c, void *data, int size, void *cmac); void bytexor(unsigned char *dst, const unsigned char *a, - const unsigned char *b, int bytelen); + const unsigned char *b, int bytelen); int clefiakeyset(unsigned char *rk, const unsigned char *skey); void clefiaencrypt(unsigned char *ct, const unsigned char *pt, - const unsigned char *rk, const int r); + const unsigned char *rk, const int r); #endif diff --git a/ports/cxd56/mkspk/elf32.h b/ports/cxd56/mkspk/elf32.h index 94a9c81ba..e19ce210a 100644 --- a/ports/cxd56/mkspk/elf32.h +++ b/ports/cxd56/mkspk/elf32.h @@ -59,7 +59,7 @@ #define ELF32_R_SYM(i) ((i) >> 8) #define ELF32_R_TYPE(i) ((i) & 0xff) -#define ELF32_R_INFO(s,t) (((s)<< 8) | ((t) & 0xff)) +#define ELF32_R_INFO(s,t) (((s) << 8) | ((t) & 0xff)) #define ELF_R_SYM(i) ELF32_R_SYM(i) @@ -69,107 +69,107 @@ /* Figure 4.2: 32-Bit Data Types */ -typedef uint32_t Elf32_Addr; /* Unsigned program address */ -typedef uint16_t Elf32_Half; /* Unsigned medium integer */ -typedef uint32_t Elf32_Off; /* Unsigned file offset */ -typedef int32_t Elf32_Sword; /* Signed large integer */ -typedef uint32_t Elf32_Word; /* Unsigned large integer */ +typedef uint32_t Elf32_Addr; /* Unsigned program address */ +typedef uint16_t Elf32_Half; /* Unsigned medium integer */ +typedef uint32_t Elf32_Off; /* Unsigned file offset */ +typedef int32_t Elf32_Sword; /* Signed large integer */ +typedef uint32_t Elf32_Word; /* Unsigned large integer */ /* Figure 4-3: ELF Header */ typedef struct { - unsigned char e_ident[EI_NIDENT]; - Elf32_Half e_type; - Elf32_Half e_machine; - Elf32_Word e_version; - Elf32_Addr e_entry; - Elf32_Off e_phoff; - Elf32_Off e_shoff; - Elf32_Word e_flags; - Elf32_Half e_ehsize; - Elf32_Half e_phentsize; - Elf32_Half e_phnum; - Elf32_Half e_shentsize; - Elf32_Half e_shnum; - Elf32_Half e_shstrndx; + unsigned char e_ident[EI_NIDENT]; + Elf32_Half e_type; + Elf32_Half e_machine; + Elf32_Word e_version; + Elf32_Addr e_entry; + Elf32_Off e_phoff; + Elf32_Off e_shoff; + Elf32_Word e_flags; + Elf32_Half e_ehsize; + Elf32_Half e_phentsize; + Elf32_Half e_phnum; + Elf32_Half e_shentsize; + Elf32_Half e_shnum; + Elf32_Half e_shstrndx; } Elf32_Ehdr; /* Figure 4-8: Section Header */ typedef struct { - Elf32_Word sh_name; - Elf32_Word sh_type; - Elf32_Word sh_flags; - Elf32_Addr sh_addr; - Elf32_Off sh_offset; - Elf32_Word sh_size; - Elf32_Word sh_link; - Elf32_Word sh_info; - Elf32_Word sh_addralign; - Elf32_Word sh_entsize; + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; } Elf32_Shdr; /* Figure 4-15: Symbol Table Entry */ typedef struct { - Elf32_Word st_name; - Elf32_Addr st_value; - Elf32_Word st_size; - unsigned char st_info; - unsigned char st_other; - Elf32_Half st_shndx; + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf32_Half st_shndx; } Elf32_Sym; /* Figure 4-19: Relocation Entries */ typedef struct { - Elf32_Addr r_offset; - Elf32_Word r_info; + Elf32_Addr r_offset; + Elf32_Word r_info; } Elf32_Rel; typedef struct { - Elf32_Addr r_offset; - Elf32_Word r_info; - Elf32_Sword r_addend; + Elf32_Addr r_offset; + Elf32_Word r_info; + Elf32_Sword r_addend; } Elf32_Rela; /* Figure 5-1: Program Header */ typedef struct { - Elf32_Word p_type; - Elf32_Off p_offset; - Elf32_Addr p_vaddr; - Elf32_Addr p_paddr; - Elf32_Word p_filesz; - Elf32_Word p_memsz; - Elf32_Word p_flags; - Elf32_Word p_align; + Elf32_Word p_type; + Elf32_Off p_offset; + Elf32_Addr p_vaddr; + Elf32_Addr p_paddr; + Elf32_Word p_filesz; + Elf32_Word p_memsz; + Elf32_Word p_flags; + Elf32_Word p_align; } Elf32_Phdr; /* Figure 5-9: Dynamic Structure */ typedef struct { - Elf32_Sword d_tag; - union - { - Elf32_Word d_val; - Elf32_Addr d_ptr; - } d_un; + Elf32_Sword d_tag; + union + { + Elf32_Word d_val; + Elf32_Addr d_ptr; + } d_un; } Elf32_Dyn; -typedef Elf32_Addr Elf_Addr; -typedef Elf32_Ehdr Elf_Ehdr; -typedef Elf32_Rel Elf_Rel; -typedef Elf32_Rela Elf_Rela; -typedef Elf32_Sym Elf_Sym; -typedef Elf32_Shdr Elf_Shdr; -typedef Elf32_Word Elf_Word; +typedef Elf32_Addr Elf_Addr; +typedef Elf32_Ehdr Elf_Ehdr; +typedef Elf32_Rel Elf_Rel; +typedef Elf32_Rela Elf_Rela; +typedef Elf32_Sym Elf_Sym; +typedef Elf32_Shdr Elf_Shdr; +typedef Elf32_Word Elf_Word; #endif /* __INCLUDE_ELF32_H */ diff --git a/ports/cxd56/mkspk/mkspk.c b/ports/cxd56/mkspk/mkspk.c index c447ad7da..23bafb834 100644 --- a/ports/cxd56/mkspk/mkspk.c +++ b/ports/cxd56/mkspk/mkspk.c @@ -53,10 +53,10 @@ struct args { - int core; - char *elffile; - char *savename; - char *outputfile; + int core; + char *elffile; + char *savename; + char *outputfile; }; /**************************************************************************** @@ -64,320 +64,295 @@ struct args ****************************************************************************/ static uint8_t vmk[16] = - "\x27\xc0\xaf\x1b\x5d\xcb\xc6\xc5\x58\x22\x1c\xdd\xaf\xf3\x20\x21"; + "\x27\xc0\xaf\x1b\x5d\xcb\xc6\xc5\x58\x22\x1c\xdd\xaf\xf3\x20\x21"; static struct args g_options = { - 0 + 0 }; /**************************************************************************** * Private Functions ****************************************************************************/ -static struct args *parse_args(int argc, char **argv) -{ - int opt; - int show_help; - struct args *args = &g_options; - char *endp; +static struct args *parse_args(int argc, char **argv) { + int opt; + int show_help; + struct args *args = &g_options; + char *endp; - show_help = 0; + show_help = 0; - if (argc < 2) - { - show_help = 1; + if (argc < 2) { + show_help = 1; } - memset(args, 0, sizeof(*args)); - args->core = -1; + memset(args, 0, sizeof(*args)); + args->core = -1; - while ((opt = getopt(argc, argv, "h:c:")) != -1) - { - switch (opt) + while ((opt = getopt(argc, argv, "h:c:")) != -1) { + switch (opt) { - case 'c': - args->core = strtol(optarg, &endp, 0); - if (*endp) - { - fprintf(stderr, "Invalid core number \"%s\"\n", optarg); - show_help = 1; - } - break; - - case 'h': - default: - show_help = 1; + case 'c': + args->core = strtol(optarg, &endp, 0); + if (*endp) { + fprintf(stderr, "Invalid core number \"%s\"\n", optarg); + show_help = 1; + } + break; + + case 'h': + default: + show_help = 1; } } - argc -= optind; - argv += optind; + argc -= optind; + argv += optind; - args->elffile = argv[0]; - args->savename = argv[1]; - argc -= 2; - argv += 2; + args->elffile = argv[0]; + args->savename = argv[1]; + argc -= 2; + argv += 2; - if (argc > 0) - { - args->outputfile = strdup(argv[0]); - } - else - { - show_help = 1; + if (argc > 0) { + args->outputfile = strdup(argv[0]); + } else { + show_help = 1; } - /* Sanity checks for options */ + /* Sanity checks for options */ - if (show_help == 1) - { - fprintf(stderr, - "mkspk [-c <number>] <filename> <save name> [<output file>]\n"); - exit(EXIT_FAILURE); + if (show_help == 1) { + fprintf(stderr, + "mkspk [-c <number>] <filename> <save name> [<output file>]\n"); + exit(EXIT_FAILURE); } - if (args->core < 0) - { - fprintf(stderr, "Core number is not set. Please use -c option.\n"); - exit(EXIT_FAILURE); + if (args->core < 0) { + fprintf(stderr, "Core number is not set. Please use -c option.\n"); + exit(EXIT_FAILURE); } - if (strlen(args->savename) > 63) - { - fprintf(stderr, "savename too long.\n"); - exit(EXIT_FAILURE); + if (strlen(args->savename) > 63) { + fprintf(stderr, "savename too long.\n"); + exit(EXIT_FAILURE); } - return args; + return args; } -static struct elf_file *load_elf(const char *filename) -{ - size_t fsize; - int pos; - char *buf; - FILE *fp; - struct elf_file *ef; - Elf32_Shdr *sh; - uint16_t i; - int ret; - - fp = fopen(filename, "rb"); - if (!fp) - { - return NULL; +static struct elf_file *load_elf(const char *filename) { + size_t fsize; + int pos; + char *buf; + FILE *fp; + struct elf_file *ef; + Elf32_Shdr *sh; + uint16_t i; + int ret; + + fp = fopen(filename, "rb"); + if (!fp) { + return NULL; } - ef = (struct elf_file *)malloc(sizeof(*ef)); - if (!ef) - { - return NULL; + ef = (struct elf_file *)malloc(sizeof(*ef)); + if (!ef) { + return NULL; } - pos = fseek(fp, 0, SEEK_END); - fsize = (size_t) ftell(fp); - fseek(fp, pos, SEEK_SET); + pos = fseek(fp, 0, SEEK_END); + fsize = (size_t)ftell(fp); + fseek(fp, pos, SEEK_SET); - buf = (char *)malloc(fsize); - if (!buf) - { - return NULL; + buf = (char *)malloc(fsize); + if (!buf) { + return NULL; } - ret = fread(buf, fsize, 1, fp); - fclose(fp); - if (ret != 1) - { - return NULL; + ret = fread(buf, fsize, 1, fp); + fclose(fp); + if (ret != 1) { + return NULL; } - ef->data = buf; + ef->data = buf; - ef->ehdr = (Elf32_Ehdr *) buf; + ef->ehdr = (Elf32_Ehdr *)buf; - Elf32_Ehdr *h = (Elf32_Ehdr *) buf; + Elf32_Ehdr *h = (Elf32_Ehdr *)buf; - if (!(h->e_ident[EI_MAG0] == 0x7f && - h->e_ident[EI_MAG1] == 'E' && - h->e_ident[EI_MAG2] == 'L' && h->e_ident[EI_MAG3] == 'F')) - { - free(ef); - free(buf); - return NULL; + if (!(h->e_ident[EI_MAG0] == 0x7f && + h->e_ident[EI_MAG1] == 'E' && + h->e_ident[EI_MAG2] == 'L' && h->e_ident[EI_MAG3] == 'F')) { + free(ef); + free(buf); + return NULL; } - ef->phdr = (Elf32_Phdr *) (buf + ef->ehdr->e_phoff); - ef->shdr = (Elf32_Shdr *) (buf + ef->ehdr->e_shoff); - ef->shstring = buf + ef->shdr[ef->ehdr->e_shstrndx].sh_offset; + ef->phdr = (Elf32_Phdr *)(buf + ef->ehdr->e_phoff); + ef->shdr = (Elf32_Shdr *)(buf + ef->ehdr->e_shoff); + ef->shstring = buf + ef->shdr[ef->ehdr->e_shstrndx].sh_offset; - for (i = 0, sh = ef->shdr; i < ef->ehdr->e_shnum; i++, sh++) + for (i = 0, sh = ef->shdr; i < ef->ehdr->e_shnum; i++, sh++) { - if (sh->sh_type == SHT_SYMTAB) - { - ef->symtab = (Elf32_Sym *) (buf + sh->sh_offset); - ef->nsyms = sh->sh_size / sh->sh_entsize; - continue; + if (sh->sh_type == SHT_SYMTAB) { + ef->symtab = (Elf32_Sym *)(buf + sh->sh_offset); + ef->nsyms = sh->sh_size / sh->sh_entsize; + continue; } - if (sh->sh_type == SHT_STRTAB) - { - if (!strcmp(".strtab", ef->shstring + sh->sh_name)) - { - ef->string = buf + sh->sh_offset; + if (sh->sh_type == SHT_STRTAB) { + if (!strcmp(".strtab", ef->shstring + sh->sh_name)) { + ef->string = buf + sh->sh_offset; } } } - return ef; + return ef; } static void *create_image(struct elf_file *elf, int core, char *savename, - int *image_size) -{ - char *img; - struct spk_header *header; - struct spk_prog_info *pi; - Elf32_Phdr *ph; - Elf32_Sym *sym; - char *name; - int snlen; - int nphs, psize, imgsize; - int i; - int j; - uint32_t offset; - uint32_t sp; - - snlen = alignup(strlen(savename) + 1, 16); - - nphs = 0; - psize = 0; - for (i = 0, ph = elf->phdr; i < elf->ehdr->e_phnum; i++, ph++) + int *image_size) { + char *img; + struct spk_header *header; + struct spk_prog_info *pi; + Elf32_Phdr *ph; + Elf32_Sym *sym; + char *name; + int snlen; + int nphs, psize, imgsize; + int i; + int j; + uint32_t offset; + uint32_t sp; + + snlen = alignup(strlen(savename) + 1, 16); + + nphs = 0; + psize = 0; + for (i = 0, ph = elf->phdr; i < elf->ehdr->e_phnum; i++, ph++) { - if (ph->p_type != PT_LOAD || ph->p_filesz == 0) - { - continue; + if (ph->p_type != PT_LOAD || ph->p_filesz == 0) { + continue; } - nphs++; - psize += alignup(ph->p_filesz, 16); + nphs++; + psize += alignup(ph->p_filesz, 16); } - imgsize = sizeof(*header) + snlen + (nphs * 16) + psize; + imgsize = sizeof(*header) + snlen + (nphs * 16) + psize; - img = (char *)malloc(imgsize + 32); - if (!img) - { - return NULL; + img = (char *)malloc(imgsize + 32); + if (!img) { + return NULL; } - *image_size = imgsize; - sym = elf->symtab; - name = elf->string; - sp = 0; + *image_size = imgsize; + sym = elf->symtab; + name = elf->string; + sp = 0; - for (j = 0; j < elf->nsyms; j++, sym++) + for (j = 0; j < elf->nsyms; j++, sym++) { - if (!strcmp("__stack", name + sym->st_name)) - { - sp = sym->st_value; + if (!strcmp("__stack", name + sym->st_name)) { + sp = sym->st_value; } } - memset(img, 0, imgsize); + memset(img, 0, imgsize); - header = (struct spk_header *)img; - header->magic[0] = 0xef; - header->magic[1] = 'M'; - header->magic[2] = 'O'; - header->magic[3] = 'D'; - header->cpu = core; + header = (struct spk_header *)img; + header->magic[0] = 0xef; + header->magic[1] = 'M'; + header->magic[2] = 'O'; + header->magic[3] = 'D'; + header->cpu = core; - header->entry = elf->ehdr->e_entry; - header->stack = sp; - header->core = core; + header->entry = elf->ehdr->e_entry; + header->stack = sp; + header->core = core; - header->binaries = nphs; - header->phoffs = sizeof(*header) + snlen; - header->mode = 0777; + header->binaries = nphs; + header->phoffs = sizeof(*header) + snlen; + header->mode = 0777; - strncpy(img + sizeof(*header), savename, 63); + strncpy(img + sizeof(*header), savename, 63); - ph = elf->phdr; - pi = (struct spk_prog_info *)(img + header->phoffs); - offset = ((char *)pi - img) + (nphs * sizeof(*pi)); - for (i = 0; i < elf->ehdr->e_phnum; i++, ph++) + ph = elf->phdr; + pi = (struct spk_prog_info *)(img + header->phoffs); + offset = ((char *)pi - img) + (nphs * sizeof(*pi)); + for (i = 0; i < elf->ehdr->e_phnum; i++, ph++) { - if (ph->p_type != PT_LOAD || ph->p_filesz == 0) - continue; - pi->load_address = ph->p_paddr; - pi->offset = offset; - pi->size = alignup(ph->p_filesz, 16); /* need 16 bytes align for + if (ph->p_type != PT_LOAD || ph->p_filesz == 0) { + continue; + } + pi->load_address = ph->p_paddr; + pi->offset = offset; + pi->size = alignup(ph->p_filesz, 16); /* need 16 bytes align for * decryption */ - pi->memsize = ph->p_memsz; + pi->memsize = ph->p_memsz; - memcpy(img + pi->offset, elf->data + ph->p_offset, ph->p_filesz); + memcpy(img + pi->offset, elf->data + ph->p_offset, ph->p_filesz); - offset += alignup(ph->p_filesz, 16); - pi++; + offset += alignup(ph->p_filesz, 16); + pi++; } - return img; + return img; } /**************************************************************************** * Public Functions ****************************************************************************/ -int main(int argc, char **argv) -{ - struct args *args; - struct elf_file *elf; - struct cipher *c; - uint8_t *spkimage; - int size = 0; - FILE *fp; - char footer[16]; - - args = parse_args(argc, argv); - - elf = load_elf(args->elffile); - if (!elf) - { - fprintf(stderr, "Loading ELF %s failure.\n", args->elffile); - exit(EXIT_FAILURE); +int main(int argc, char **argv) { + struct args *args; + struct elf_file *elf; + struct cipher *c; + uint8_t *spkimage; + int size = 0; + FILE *fp; + char footer[16]; + + args = parse_args(argc, argv); + + elf = load_elf(args->elffile); + if (!elf) { + fprintf(stderr, "Loading ELF %s failure.\n", args->elffile); + exit(EXIT_FAILURE); } - spkimage = create_image(elf, args->core, args->savename, &size); - free(elf); + spkimage = create_image(elf, args->core, args->savename, &size); + free(elf); - c = cipher_init(vmk, NULL); - cipher_calc_cmac(c, spkimage, size, (uint8_t *) spkimage + size); - cipher_deinit(c); + c = cipher_init(vmk, NULL); + cipher_calc_cmac(c, spkimage, size, (uint8_t *)spkimage + size); + cipher_deinit(c); - size += 16; /* Extend CMAC size */ + size += 16; /* Extend CMAC size */ - snprintf(footer, 16, "MKSPK_BN_HOOTER"); - footer[15] = '\0'; + snprintf(footer, 16, "MKSPK_BN_HOOTER"); + footer[15] = '\0'; - fp = fopen(args->outputfile, "wb"); - if (!fp) - { - fprintf(stderr, "Output file open error.\n"); - free(spkimage); - exit(EXIT_FAILURE); + fp = fopen(args->outputfile, "wb"); + if (!fp) { + fprintf(stderr, "Output file open error.\n"); + free(spkimage); + exit(EXIT_FAILURE); } - fwrite(spkimage, size, 1, fp); - fwrite(footer, 16, 1, fp); + fwrite(spkimage, size, 1, fp); + fwrite(footer, 16, 1, fp); - fclose(fp); + fclose(fp); - printf("File %s is successfully created.\n", args->outputfile); - free(args->outputfile); + printf("File %s is successfully created.\n", args->outputfile); + free(args->outputfile); - memset(spkimage, 0, size); - free(spkimage); + memset(spkimage, 0, size); + free(spkimage); - exit(EXIT_SUCCESS); + exit(EXIT_SUCCESS); } diff --git a/ports/cxd56/mkspk/mkspk.h b/ports/cxd56/mkspk/mkspk.h index 5c1b979c0..8cdac1185 100644 --- a/ports/cxd56/mkspk/mkspk.h +++ b/ports/cxd56/mkspk/mkspk.h @@ -60,7 +60,7 @@ ****************************************************************************/ struct spk_header - { +{ uint8_t magic[4]; uint8_t cpu; uint8_t reserved[11]; @@ -70,18 +70,18 @@ struct spk_header uint16_t binaries; uint16_t phoffs; uint16_t mode; - }; +}; struct spk_prog_info - { +{ uint32_t load_address; uint32_t offset; uint32_t size; uint32_t memsize; - }; +}; struct elf_file - { +{ Elf32_Ehdr *ehdr; Elf32_Phdr *phdr; Elf32_Shdr *shdr; @@ -90,4 +90,4 @@ struct elf_file char *shstring; char *string; char *data; - }; +}; diff --git a/ports/cxd56/mphalport.h b/ports/cxd56/mphalport.h index 50e805cf5..ba5ca39b9 100644 --- a/ports/cxd56/mphalport.h +++ b/ports/cxd56/mphalport.h @@ -32,6 +32,6 @@ #include "lib/utils/interrupt_char.h" #include "supervisor/shared/tick.h" -#define mp_hal_ticks_ms() ((mp_uint_t) supervisor_ticks_ms32()) +#define mp_hal_ticks_ms() ((mp_uint_t)supervisor_ticks_ms32()) #endif // MICROPY_INCLUDED_CXD56_MPHALPORT_H diff --git a/ports/cxd56/supervisor/port.c b/ports/cxd56/supervisor/port.c index 523d6a496..fa7591918 100644 --- a/ports/cxd56/supervisor/port.c +++ b/ports/cxd56/supervisor/port.c @@ -48,14 +48,16 @@ #define SPRESENSE_MEM_ALIGN (32) -uint32_t* heap; +uint32_t *heap; uint32_t heap_size; safe_mode_t port_init(void) { boardctl(BOARDIOC_INIT, 0); // Wait until RTC is available - while (g_rtc_enabled == false); + while (g_rtc_enabled == false) { + ; + } heap = memalign(SPRESENSE_MEM_ALIGN, 128 * 1024); uint32_t size = CONFIG_RAM_START + CONFIG_RAM_SIZE - (uint32_t)heap - 2 * SPRESENSE_MEM_ALIGN; @@ -76,18 +78,18 @@ void reset_cpu(void) { } void reset_port(void) { -#if CIRCUITPY_ANALOGIO + #if CIRCUITPY_ANALOGIO analogin_reset(); -#endif -#if CIRCUITPY_PULSEIO + #endif + #if CIRCUITPY_PULSEIO pulseout_reset(); -#endif -#if CIRCUITPY_PWMIO + #endif + #if CIRCUITPY_PWMIO pwmout_reset(); -#endif -#if CIRCUITPY_BUSIO + #endif + #if CIRCUITPY_BUSIO busio_uart_reset(); -#endif + #endif reset_all_pins(); } @@ -134,13 +136,12 @@ uint32_t port_get_saved_word(void) { } static background_callback_t callback; -static void usb_background_do(void* unused) { +static void usb_background_do(void *unused) { usb_background(); } volatile bool _tick_enabled; -void board_timerhook(void) -{ +void board_timerhook(void) { // Do things common to all ports when the tick occurs if (_tick_enabled) { supervisor_tick(); @@ -149,7 +150,7 @@ void board_timerhook(void) background_callback_add(&callback, usb_background_do, NULL); } -uint64_t port_get_raw_ticks(uint8_t* subticks) { +uint64_t port_get_raw_ticks(uint8_t *subticks) { uint64_t count = cxd56_rtc_count(); *subticks = count % 32; diff --git a/ports/cxd56/tools/flash_writer.py b/ports/cxd56/tools/flash_writer.py index 840f10c32..a61342e3e 100755 --- a/ports/cxd56/tools/flash_writer.py +++ b/ports/cxd56/tools/flash_writer.py @@ -49,17 +49,17 @@ import_serial_module = True # When SDK release, plase set SDK_RELEASE as True. SDK_RELEASE = False -if SDK_RELEASE : - PRINT_RAW_COMMAND = False - REBOOT_AT_END = True -else : - PRINT_RAW_COMMAND = True - REBOOT_AT_END = True +if SDK_RELEASE: + PRINT_RAW_COMMAND = False + REBOOT_AT_END = True +else: + PRINT_RAW_COMMAND = True + REBOOT_AT_END = True try: - import serial + import serial except: - import_serial_module = False + import_serial_module = False # supported environment various # CXD56_PORT @@ -73,508 +73,599 @@ MAX_DOT_COUNT = 70 # configure parameters and default value class ConfigArgs: - PROTOCOL_TYPE = None - SERIAL_PORT = "COM1" - SERVER_PORT = 4569 - SERVER_IP = "localhost" - EOL = bytes([10]) - WAIT_RESET = True - AUTO_RESET = False - DTR_RESET = False - XMODEM_BAUD = 0 - NO_SET_BOOTABLE = False - PACKAGE_NAME = [] - FILE_NAME = [] - ERASE_NAME = [] - PKGSYS_NAME = [] - PKGAPP_NAME = [] - PKGUPD_NAME = [] + PROTOCOL_TYPE = None + SERIAL_PORT = "COM1" + SERVER_PORT = 4569 + SERVER_IP = "localhost" + EOL = bytes([10]) + WAIT_RESET = True + AUTO_RESET = False + DTR_RESET = False + XMODEM_BAUD = 0 + NO_SET_BOOTABLE = False + PACKAGE_NAME = [] + FILE_NAME = [] + ERASE_NAME = [] + PKGSYS_NAME = [] + PKGAPP_NAME = [] + PKGUPD_NAME = [] + ROM_MSG = [b"Welcome to nash"] XMDM_MSG = "Waiting for XMODEM (CRC or 1K) transfer. Ctrl-X to cancel." -class ConfigArgsLoader(): - def __init__(self): - self.parser = argparse.ArgumentParser(formatter_class=argparse.RawTextHelpFormatter) - self.parser.add_argument("package_name", help="the name of the package to install", nargs='*') - self.parser.add_argument("-f", "--file", dest="file_name", help="save file", action='append') - self.parser.add_argument("-e", "--erase", dest="erase_name", help="erase file", action='append') - - self.parser.add_argument("-S", "--sys", dest="pkgsys_name", help="the name of the system package to install", action='append') - self.parser.add_argument("-A", "--app", dest="pkgapp_name", help="the name of the application package to install", action='append') - self.parser.add_argument("-U", "--upd", dest="pkgupd_name", help="the name of the updater package to install", action='append') - - self.parser.add_argument("-a", "--auto-reset", dest="auto_reset", - action="store_true", default=None, - help="try to auto reset develop board if possible") - self.parser.add_argument("-d", "--dtr-reset", dest="dtr_reset", - action="store_true", default=None, - help="try to auto reset develop board if possible") - self.parser.add_argument("-n", "--no-set-bootable", dest="no_set_bootable", - action="store_true", default=None, - help="not to set bootable") - - group = self.parser.add_argument_group() - group.add_argument("-i", "--server-ip", dest="server_ip", - help="the ip address connected to the telnet server") - group.add_argument("-p", "--server-port", dest="server_port", type=int, - help="the port connected to the telnet server") - - group = self.parser.add_argument_group() - group.add_argument("-c", "--serial-port", dest="serial_port", help="the serial port") - group.add_argument("-b", "--xmodem-baudrate", dest="xmodem_baud", help="Use the faster baudrate in xmodem") - - mutually_group = self.parser.add_mutually_exclusive_group() - mutually_group.add_argument("-t", "--telnet-protocol", dest="telnet_protocol", - action="store_true", default=None, - help="use the telnet protocol for binary transmission") - mutually_group.add_argument("-s", "--serial-protocol", dest="serial_protocol", - action="store_true", default=None, - help="use the serial port for binary transmission, default options") - - mutually_group2 = self.parser.add_mutually_exclusive_group() - mutually_group2.add_argument("-F", "--force-wait-reset", dest="wait_reset", - action="store_true", default=None, - help="force wait for pressing RESET button") - mutually_group2.add_argument("-N", "--no-wait-reset", dest="wait_reset", - action="store_false", default=None, - help="if possible, skip to wait for pressing RESET button") - - def update_config(self): - args = self.parser.parse_args() - - ConfigArgs.PACKAGE_NAME = args.package_name - ConfigArgs.FILE_NAME = args.file_name - ConfigArgs.ERASE_NAME = args.erase_name - ConfigArgs.PKGSYS_NAME = args.pkgsys_name - ConfigArgs.PKGAPP_NAME = args.pkgapp_name - ConfigArgs.PKGUPD_NAME = args.pkgupd_name - - # Get serial port or telnet server ip etc - if args.serial_protocol == True: - ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL - elif args.telnet_protocol == True: - ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET - - if ConfigArgs.PROTOCOL_TYPE == None: - proto = os.environ.get("CXD56_PROTOCOL") - if proto is not None: - if 's' in proto: - ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL - elif 't' in proto: - ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET - - if ConfigArgs.PROTOCOL_TYPE == None: - ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL - - if ConfigArgs.PROTOCOL_TYPE == PROTOCOL_SERIAL: - if args.serial_port is not None: - ConfigArgs.SERIAL_PORT = args.serial_port - else: - # Get serial port from the environment - port = os.environ.get("CXD56_PORT") - if port is not None: - ConfigArgs.SERIAL_PORT = port - else: - print("CXD56_PORT is not set, Use " + ConfigArgs.SERIAL_PORT + ".") - else: - ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET - if args.server_port is not None: - ConfigArgs.SERVER_PORT = args.server_port - else: - port = os.environ.get("CXD56_TELNETSRV_PORT") - if port is not None: - ConfigArgs.SERVER_PORT = port - else: - print("CXD56_TELNETSRV_PORT is not set, Use " + str(ConfigArgs.SERVER_PORT) + ".") - if args.server_ip is not None: - ConfigArgs.SERVER_IP = args.server_ip - else: - ip = os.environ.get("CXD56_TELNETSRV_IP") - if ip is not None: - ConfigArgs.SERVER_IP = ip - else: - print("CXD56_TELNETSRV_IP is not set, Use " + ConfigArgs.SERVER_IP + ".") - - if args.xmodem_baud is not None: - ConfigArgs.XMODEM_BAUD = args.xmodem_baud - - if args.auto_reset is not None: - ConfigArgs.AUTO_RESET = args.auto_reset - - if args.dtr_reset is not None: - ConfigArgs.DTR_RESET = args.dtr_reset - - if args.no_set_bootable is not None: - ConfigArgs.NO_SET_BOOTABLE = args.no_set_bootable - - if args.wait_reset is not None: - ConfigArgs.WAIT_RESET = args.wait_reset + +class ConfigArgsLoader: + def __init__(self): + self.parser = argparse.ArgumentParser(formatter_class=argparse.RawTextHelpFormatter) + self.parser.add_argument( + "package_name", help="the name of the package to install", nargs="*" + ) + self.parser.add_argument( + "-f", "--file", dest="file_name", help="save file", action="append" + ) + self.parser.add_argument( + "-e", "--erase", dest="erase_name", help="erase file", action="append" + ) + + self.parser.add_argument( + "-S", + "--sys", + dest="pkgsys_name", + help="the name of the system package to install", + action="append", + ) + self.parser.add_argument( + "-A", + "--app", + dest="pkgapp_name", + help="the name of the application package to install", + action="append", + ) + self.parser.add_argument( + "-U", + "--upd", + dest="pkgupd_name", + help="the name of the updater package to install", + action="append", + ) + + self.parser.add_argument( + "-a", + "--auto-reset", + dest="auto_reset", + action="store_true", + default=None, + help="try to auto reset develop board if possible", + ) + self.parser.add_argument( + "-d", + "--dtr-reset", + dest="dtr_reset", + action="store_true", + default=None, + help="try to auto reset develop board if possible", + ) + self.parser.add_argument( + "-n", + "--no-set-bootable", + dest="no_set_bootable", + action="store_true", + default=None, + help="not to set bootable", + ) + + group = self.parser.add_argument_group() + group.add_argument( + "-i", + "--server-ip", + dest="server_ip", + help="the ip address connected to the telnet server", + ) + group.add_argument( + "-p", + "--server-port", + dest="server_port", + type=int, + help="the port connected to the telnet server", + ) + + group = self.parser.add_argument_group() + group.add_argument("-c", "--serial-port", dest="serial_port", help="the serial port") + group.add_argument( + "-b", "--xmodem-baudrate", dest="xmodem_baud", help="Use the faster baudrate in xmodem" + ) + + mutually_group = self.parser.add_mutually_exclusive_group() + mutually_group.add_argument( + "-t", + "--telnet-protocol", + dest="telnet_protocol", + action="store_true", + default=None, + help="use the telnet protocol for binary transmission", + ) + mutually_group.add_argument( + "-s", + "--serial-protocol", + dest="serial_protocol", + action="store_true", + default=None, + help="use the serial port for binary transmission, default options", + ) + + mutually_group2 = self.parser.add_mutually_exclusive_group() + mutually_group2.add_argument( + "-F", + "--force-wait-reset", + dest="wait_reset", + action="store_true", + default=None, + help="force wait for pressing RESET button", + ) + mutually_group2.add_argument( + "-N", + "--no-wait-reset", + dest="wait_reset", + action="store_false", + default=None, + help="if possible, skip to wait for pressing RESET button", + ) + + def update_config(self): + args = self.parser.parse_args() + + ConfigArgs.PACKAGE_NAME = args.package_name + ConfigArgs.FILE_NAME = args.file_name + ConfigArgs.ERASE_NAME = args.erase_name + ConfigArgs.PKGSYS_NAME = args.pkgsys_name + ConfigArgs.PKGAPP_NAME = args.pkgapp_name + ConfigArgs.PKGUPD_NAME = args.pkgupd_name + + # Get serial port or telnet server ip etc + if args.serial_protocol == True: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL + elif args.telnet_protocol == True: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET + + if ConfigArgs.PROTOCOL_TYPE == None: + proto = os.environ.get("CXD56_PROTOCOL") + if proto is not None: + if "s" in proto: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL + elif "t" in proto: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET + + if ConfigArgs.PROTOCOL_TYPE == None: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL + + if ConfigArgs.PROTOCOL_TYPE == PROTOCOL_SERIAL: + if args.serial_port is not None: + ConfigArgs.SERIAL_PORT = args.serial_port + else: + # Get serial port from the environment + port = os.environ.get("CXD56_PORT") + if port is not None: + ConfigArgs.SERIAL_PORT = port + else: + print("CXD56_PORT is not set, Use " + ConfigArgs.SERIAL_PORT + ".") + else: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET + if args.server_port is not None: + ConfigArgs.SERVER_PORT = args.server_port + else: + port = os.environ.get("CXD56_TELNETSRV_PORT") + if port is not None: + ConfigArgs.SERVER_PORT = port + else: + print( + "CXD56_TELNETSRV_PORT is not set, Use " + str(ConfigArgs.SERVER_PORT) + "." + ) + if args.server_ip is not None: + ConfigArgs.SERVER_IP = args.server_ip + else: + ip = os.environ.get("CXD56_TELNETSRV_IP") + if ip is not None: + ConfigArgs.SERVER_IP = ip + else: + print("CXD56_TELNETSRV_IP is not set, Use " + ConfigArgs.SERVER_IP + ".") + + if args.xmodem_baud is not None: + ConfigArgs.XMODEM_BAUD = args.xmodem_baud + + if args.auto_reset is not None: + ConfigArgs.AUTO_RESET = args.auto_reset + + if args.dtr_reset is not None: + ConfigArgs.DTR_RESET = args.dtr_reset + + if args.no_set_bootable is not None: + ConfigArgs.NO_SET_BOOTABLE = args.no_set_bootable + + if args.wait_reset is not None: + ConfigArgs.WAIT_RESET = args.wait_reset + class TelnetDev: - def __init__(self): - srv_ipaddr = ConfigArgs.SERVER_IP - srv_port = ConfigArgs.SERVER_PORT - self.recvbuf = b''; - try: - self.telnet = telnetlib.Telnet(host=srv_ipaddr, port=srv_port, timeout=10) - # There is a ack to be sent after connecting to the telnet server. - self.telnet.write(b"\xff") - except Exception as e: - print("Cannot connect to the server %s:%d" % (srv_ipaddr, srv_port)) - sys.exit(e.args[0]) - - def readline(self, size=None): - res = b'' - ch = b'' - while ch != ConfigArgs.EOL: - ch = self.getc_raw(1, timeout=0.1) - if ch == b'': - return res - res += ch - return res - - def getc_raw(self, size, timeout=1): - res = b'' - tm = time.monotonic() - while size > 0: - while self.recvbuf == b'': - self.recvbuf = self.telnet.read_eager() - if self.recvbuf == b'': - if (time.monotonic() - tm) > timeout: - return res - time.sleep(0.1) - res += self.recvbuf[0:1] - self.recvbuf = self.recvbuf[1:] - size -= 1 - return res - - def write(self, buffer): - self.telnet.write(buffer) - - def discard_inputs(self, timeout=1.0): - while True: - ch = self.getc_raw(1, timeout=timeout) - if ch == b'': - break - - def getc(self, size, timeout=1): - c = self.getc_raw(size, timeout) - return c - - def putc(self, buffer, timeout=1): - self.telnet.write(buffer) - self.show_progress(len(buffer)) - - def reboot(self): - # no-op - pass - - def set_file_size(self, filesize): - self.bytes_transfered = 0 - self.filesize = filesize - self.count = 0 - - def show_progress(self, sendsize): - if PRINT_RAW_COMMAND: - if self.count < MAX_DOT_COUNT: - self.bytes_transfered = self.bytes_transfered + sendsize - cur_count = int(self.bytes_transfered * MAX_DOT_COUNT / self.filesize) - if MAX_DOT_COUNT < cur_count: - cur_count = MAX_DOT_COUNT - for idx in range(cur_count - self.count): - print('#',end='') - sys.stdout.flush() - self.count = cur_count - if self.count == MAX_DOT_COUNT: - print("\n") + def __init__(self): + srv_ipaddr = ConfigArgs.SERVER_IP + srv_port = ConfigArgs.SERVER_PORT + self.recvbuf = b"" + try: + self.telnet = telnetlib.Telnet(host=srv_ipaddr, port=srv_port, timeout=10) + # There is a ack to be sent after connecting to the telnet server. + self.telnet.write(b"\xff") + except Exception as e: + print("Cannot connect to the server %s:%d" % (srv_ipaddr, srv_port)) + sys.exit(e.args[0]) + + def readline(self, size=None): + res = b"" + ch = b"" + while ch != ConfigArgs.EOL: + ch = self.getc_raw(1, timeout=0.1) + if ch == b"": + return res + res += ch + return res + + def getc_raw(self, size, timeout=1): + res = b"" + tm = time.monotonic() + while size > 0: + while self.recvbuf == b"": + self.recvbuf = self.telnet.read_eager() + if self.recvbuf == b"": + if (time.monotonic() - tm) > timeout: + return res + time.sleep(0.1) + res += self.recvbuf[0:1] + self.recvbuf = self.recvbuf[1:] + size -= 1 + return res + + def write(self, buffer): + self.telnet.write(buffer) + + def discard_inputs(self, timeout=1.0): + while True: + ch = self.getc_raw(1, timeout=timeout) + if ch == b"": + break + + def getc(self, size, timeout=1): + c = self.getc_raw(size, timeout) + return c + + def putc(self, buffer, timeout=1): + self.telnet.write(buffer) + self.show_progress(len(buffer)) + + def reboot(self): + # no-op + pass + + def set_file_size(self, filesize): + self.bytes_transfered = 0 + self.filesize = filesize + self.count = 0 + + def show_progress(self, sendsize): + if PRINT_RAW_COMMAND: + if self.count < MAX_DOT_COUNT: + self.bytes_transfered = self.bytes_transfered + sendsize + cur_count = int(self.bytes_transfered * MAX_DOT_COUNT / self.filesize) + if MAX_DOT_COUNT < cur_count: + cur_count = MAX_DOT_COUNT + for idx in range(cur_count - self.count): + print("#", end="") + sys.stdout.flush() + self.count = cur_count + if self.count == MAX_DOT_COUNT: + print("\n") + class SerialDev: - def __init__(self): - if import_serial_module is False: - print("Cannot import serial module, maybe it's not install yet.") - print("\n", end="") - print("Please install python-setuptool by Cygwin installer.") - print("After that use easy_intall command to install serial module") - print(" $ cd tool/") - print(" $ python3 -m easy_install pyserial-2.7.tar.gz") - quit() - else: - port = ConfigArgs.SERIAL_PORT - try: - self.serial = serial.Serial(port, baudrate=115200, - parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_ONE, - bytesize=serial.EIGHTBITS, timeout=0.1) - except Exception as e: - print("Cannot open port : " + port) - sys.exit(e.args[0]) - - def readline(self, size=None): - return self.serial.readline(size) - - def write(self, buffer): - self.serial.write(buffer) - self.serial.flush() - - def discard_inputs(self, timeout=1.0): - time.sleep(timeout) - self.serial.flushInput() - - def getc(self, size, timeout=1): - self.serial.timeout = timeout - c = self.serial.read(size) - self.serial.timeout = 0.1 - return c - - def putc(self, buffer, timeout=1): - self.serial.timeout = timeout - self.serial.write(buffer) - self.serial.flush() - self.serial.timeout = 0.1 - self.show_progress(len(buffer)) - - # Note: windows platform dependent code - def putc_win(self, buffer, timeout=1): - self.serial.write(buffer) - self.show_progress(len(buffer)) - while True: - if self.serial.out_waiting == 0: - break - - def setBaudrate(self, baudrate): -# self.serial.setBaudrate(baudrate) - self.serial.baudrate = baudrate - - def reboot(self): - # Target Reset by DTR - self.serial.setDTR(False) - self.serial.setDTR(True) - self.serial.setDTR(False) - - def set_file_size(self, filesize): - self.bytes_transfered = 0 - self.filesize = filesize - self.count = 0 - - def show_progress(self, sendsize): - if PRINT_RAW_COMMAND: - if self.count < MAX_DOT_COUNT: - self.bytes_transfered = self.bytes_transfered + sendsize - cur_count = int(self.bytes_transfered * MAX_DOT_COUNT / self.filesize) - if MAX_DOT_COUNT < cur_count: - cur_count = MAX_DOT_COUNT - for idx in range(cur_count - self.count): - print('#',end='') - sys.stdout.flush() - self.count = cur_count - if self.count == MAX_DOT_COUNT: - print("\n") + def __init__(self): + if import_serial_module is False: + print("Cannot import serial module, maybe it's not install yet.") + print("\n", end="") + print("Please install python-setuptool by Cygwin installer.") + print("After that use easy_intall command to install serial module") + print(" $ cd tool/") + print(" $ python3 -m easy_install pyserial-2.7.tar.gz") + quit() + else: + port = ConfigArgs.SERIAL_PORT + try: + self.serial = serial.Serial( + port, + baudrate=115200, + parity=serial.PARITY_NONE, + stopbits=serial.STOPBITS_ONE, + bytesize=serial.EIGHTBITS, + timeout=0.1, + ) + except Exception as e: + print("Cannot open port : " + port) + sys.exit(e.args[0]) + + def readline(self, size=None): + return self.serial.readline(size) + + def write(self, buffer): + self.serial.write(buffer) + self.serial.flush() + + def discard_inputs(self, timeout=1.0): + time.sleep(timeout) + self.serial.flushInput() + + def getc(self, size, timeout=1): + self.serial.timeout = timeout + c = self.serial.read(size) + self.serial.timeout = 0.1 + return c + + def putc(self, buffer, timeout=1): + self.serial.timeout = timeout + self.serial.write(buffer) + self.serial.flush() + self.serial.timeout = 0.1 + self.show_progress(len(buffer)) + + # Note: windows platform dependent code + def putc_win(self, buffer, timeout=1): + self.serial.write(buffer) + self.show_progress(len(buffer)) + while True: + if self.serial.out_waiting == 0: + break + + def setBaudrate(self, baudrate): + # self.serial.setBaudrate(baudrate) + self.serial.baudrate = baudrate + + def reboot(self): + # Target Reset by DTR + self.serial.setDTR(False) + self.serial.setDTR(True) + self.serial.setDTR(False) + + def set_file_size(self, filesize): + self.bytes_transfered = 0 + self.filesize = filesize + self.count = 0 + + def show_progress(self, sendsize): + if PRINT_RAW_COMMAND: + if self.count < MAX_DOT_COUNT: + self.bytes_transfered = self.bytes_transfered + sendsize + cur_count = int(self.bytes_transfered * MAX_DOT_COUNT / self.filesize) + if MAX_DOT_COUNT < cur_count: + cur_count = MAX_DOT_COUNT + for idx in range(cur_count - self.count): + print("#", end="") + sys.stdout.flush() + self.count = cur_count + if self.count == MAX_DOT_COUNT: + print("\n") + class FlashWriter: - def __init__(self, protocol_sel=PROTOCOL_SERIAL): - if protocol_sel == PROTOCOL_TELNET: - self.serial = TelnetDev() - else: - self.serial = SerialDev() - - def cancel_autoboot(self) : - boot_msg = '' - self.serial.reboot() # Target reboot before send 'r' - while boot_msg == '' : - rx = self.serial.readline().strip() - self.serial.write(b"r") # Send "r" key to avoid auto boot - for msg in ROM_MSG : - if msg in rx : - boot_msg = msg - break - while True : - rx = self.serial.readline().decode(errors="replace").strip() - if "updater" in rx : - # Workaround : Sometime first character is dropped. - # Send line feed as air shot before actual command. - self.serial.write(b"\n") # Send line feed - self.serial.discard_inputs()# Clear input buffer to sync - return boot_msg.decode(errors="ignore") - - def recv(self): - rx = self.serial.readline() - if PRINT_RAW_COMMAND : - serial_line = rx.decode(errors="replace") - if serial_line.strip() != "" and not serial_line.startswith(XMDM_MSG): - print(serial_line, end="") - return rx - - def wait(self, string): - while True: - rx = self.recv() - if string.encode() in rx: - time.sleep(0.1) - break - - def wait_for_prompt(self): - prompt_pat = re.compile(b"updater") - while True: - rx = self.recv() - if prompt_pat.search(rx): - time.sleep(0.1) - break - - def send(self, string): - self.serial.write(str(string).encode() + b"\n") - rx = self.serial.readline() - if PRINT_RAW_COMMAND : - print(rx.decode(errors="replace"), end="") - - def read_output(self, prompt_text) : - output = [] - while True : - rx = self.serial.readline() - if prompt_text.encode() in rx : - time.sleep(0.1) - break - if rx != "" : - output.append(rx.decode(errors="ignore").rstrip()) - return output - - def install_files(self, files, command) : - if ConfigArgs.XMODEM_BAUD: - command += " -b " + ConfigArgs.XMODEM_BAUD - if os.name == 'nt': - modem = xmodem.XMODEM(self.serial.getc, self.serial.putc_win, 'xmodem1k') - else: - modem = xmodem.XMODEM(self.serial.getc, self.serial.putc, 'xmodem1k') - for file in files: - with open(file, "rb") as bin : - self.send(command) - print("Install " + file) - self.wait(XMDM_MSG) - print("|0%" + - "-" * (int(MAX_DOT_COUNT / 2) - 6) + - "50%" + - "-" * (MAX_DOT_COUNT - int(MAX_DOT_COUNT / 2) - 5) + - "100%|") - if ConfigArgs.XMODEM_BAUD: - self.serial.setBaudrate(ConfigArgs.XMODEM_BAUD) - self.serial.discard_inputs() # Clear input buffer to sync - self.serial.set_file_size(os.path.getsize(file)) - modem.send(bin) - if ConfigArgs.XMODEM_BAUD: - self.serial.setBaudrate(115200) - self.wait_for_prompt() - - def save_files(self, files) : - if ConfigArgs.XMODEM_BAUD: - command = "save_file -b " + ConfigArgs.XMODEM_BAUD + " -x " - else: - command = "save_file -x " - if os.name == 'nt': - modem = xmodem.XMODEM(self.serial.getc, self.serial.putc_win, 'xmodem1k') - else: - modem = xmodem.XMODEM(self.serial.getc, self.serial.putc, 'xmodem1k') - for file in files: - with open(file, "rb") as bin : - self.send(command + os.path.basename(file)) - print("Save " + file) - self.wait(XMDM_MSG) - if ConfigArgs.XMODEM_BAUD: - self.serial.setBaudrate(ConfigArgs.XMODEM_BAUD) - self.serial.discard_inputs() # Clear input buffer to sync - self.serial.set_file_size(os.path.getsize(file)) - modem.send(bin) - if ConfigArgs.XMODEM_BAUD: - self.serial.setBaudrate(115200) - self.wait_for_prompt() - self.send("chmod d+rw " + os.path.basename(file)) - self.wait_for_prompt() - - def delete_files(self, files) : - for file in files : - self.delete_binary(file) - - def delete_binary(self, bin_name) : - self.send("rm " + bin_name) - self.wait_for_prompt() + def __init__(self, protocol_sel=PROTOCOL_SERIAL): + if protocol_sel == PROTOCOL_TELNET: + self.serial = TelnetDev() + else: + self.serial = SerialDev() + + def cancel_autoboot(self): + boot_msg = "" + self.serial.reboot() # Target reboot before send 'r' + while boot_msg == "": + rx = self.serial.readline().strip() + self.serial.write(b"r") # Send "r" key to avoid auto boot + for msg in ROM_MSG: + if msg in rx: + boot_msg = msg + break + while True: + rx = self.serial.readline().decode(errors="replace").strip() + if "updater" in rx: + # Workaround : Sometime first character is dropped. + # Send line feed as air shot before actual command. + self.serial.write(b"\n") # Send line feed + self.serial.discard_inputs() # Clear input buffer to sync + return boot_msg.decode(errors="ignore") + + def recv(self): + rx = self.serial.readline() + if PRINT_RAW_COMMAND: + serial_line = rx.decode(errors="replace") + if serial_line.strip() != "" and not serial_line.startswith(XMDM_MSG): + print(serial_line, end="") + return rx + + def wait(self, string): + while True: + rx = self.recv() + if string.encode() in rx: + time.sleep(0.1) + break + + def wait_for_prompt(self): + prompt_pat = re.compile(b"updater") + while True: + rx = self.recv() + if prompt_pat.search(rx): + time.sleep(0.1) + break + + def send(self, string): + self.serial.write(str(string).encode() + b"\n") + rx = self.serial.readline() + if PRINT_RAW_COMMAND: + print(rx.decode(errors="replace"), end="") + + def read_output(self, prompt_text): + output = [] + while True: + rx = self.serial.readline() + if prompt_text.encode() in rx: + time.sleep(0.1) + break + if rx != "": + output.append(rx.decode(errors="ignore").rstrip()) + return output + + def install_files(self, files, command): + if ConfigArgs.XMODEM_BAUD: + command += " -b " + ConfigArgs.XMODEM_BAUD + if os.name == "nt": + modem = xmodem.XMODEM(self.serial.getc, self.serial.putc_win, "xmodem1k") + else: + modem = xmodem.XMODEM(self.serial.getc, self.serial.putc, "xmodem1k") + for file in files: + with open(file, "rb") as bin: + self.send(command) + print("Install " + file) + self.wait(XMDM_MSG) + print( + "|0%" + + "-" * (int(MAX_DOT_COUNT / 2) - 6) + + "50%" + + "-" * (MAX_DOT_COUNT - int(MAX_DOT_COUNT / 2) - 5) + + "100%|" + ) + if ConfigArgs.XMODEM_BAUD: + self.serial.setBaudrate(ConfigArgs.XMODEM_BAUD) + self.serial.discard_inputs() # Clear input buffer to sync + self.serial.set_file_size(os.path.getsize(file)) + modem.send(bin) + if ConfigArgs.XMODEM_BAUD: + self.serial.setBaudrate(115200) + self.wait_for_prompt() + + def save_files(self, files): + if ConfigArgs.XMODEM_BAUD: + command = "save_file -b " + ConfigArgs.XMODEM_BAUD + " -x " + else: + command = "save_file -x " + if os.name == "nt": + modem = xmodem.XMODEM(self.serial.getc, self.serial.putc_win, "xmodem1k") + else: + modem = xmodem.XMODEM(self.serial.getc, self.serial.putc, "xmodem1k") + for file in files: + with open(file, "rb") as bin: + self.send(command + os.path.basename(file)) + print("Save " + file) + self.wait(XMDM_MSG) + if ConfigArgs.XMODEM_BAUD: + self.serial.setBaudrate(ConfigArgs.XMODEM_BAUD) + self.serial.discard_inputs() # Clear input buffer to sync + self.serial.set_file_size(os.path.getsize(file)) + modem.send(bin) + if ConfigArgs.XMODEM_BAUD: + self.serial.setBaudrate(115200) + self.wait_for_prompt() + self.send("chmod d+rw " + os.path.basename(file)) + self.wait_for_prompt() + + def delete_files(self, files): + for file in files: + self.delete_binary(file) + + def delete_binary(self, bin_name): + self.send("rm " + bin_name) + self.wait_for_prompt() + def main(): - try: - config_loader = ConfigArgsLoader() - config_loader.update_config() - except: - return errno.EINVAL - - # Wait to reset the board - writer = FlashWriter(ConfigArgs.PROTOCOL_TYPE) - - do_wait_reset = True - if ConfigArgs.AUTO_RESET: - if subprocess.call("cd " + sys.path[0] + "; ./reset_board.sh", shell=True) == 0: - print("auto reset board sucess!!") - do_wait_reset = False - bootrom_msg = writer.cancel_autoboot() - - if ConfigArgs.DTR_RESET: - do_wait_reset = False - bootrom_msg = writer.cancel_autoboot() - - if ConfigArgs.WAIT_RESET == False and do_wait_reset == True: - rx = writer.recv() - time.sleep(1) - for i in range(3): - writer.send("") - rx = writer.recv() - if "updater".encode() in rx: - # No need to wait for reset - do_wait_reset = False - break - time.sleep(1) - - if do_wait_reset: - # Wait to reset the board - print('Please press RESET button on target board') - sys.stdout.flush() - bootrom_msg = writer.cancel_autoboot() - - # Remove files - if ConfigArgs.ERASE_NAME : - print(">>> Remove exisiting files ...") - writer.delete_files(ConfigArgs.ERASE_NAME) - - # Install files - if ConfigArgs.PACKAGE_NAME or ConfigArgs.PKGSYS_NAME or ConfigArgs.PKGAPP_NAME or ConfigArgs.PKGUPD_NAME: - print(">>> Install files ...") - if ConfigArgs.PACKAGE_NAME : - writer.install_files(ConfigArgs.PACKAGE_NAME, "install") - if ConfigArgs.PKGSYS_NAME : - writer.install_files(ConfigArgs.PKGSYS_NAME, "install") - if ConfigArgs.PKGAPP_NAME : - writer.install_files(ConfigArgs.PKGAPP_NAME, "install") - if ConfigArgs.PKGUPD_NAME : - writer.install_files(ConfigArgs.PKGUPD_NAME, "install -k updater.key") - - # Save files - if ConfigArgs.FILE_NAME : - print(">>> Save files ...") - writer.save_files(ConfigArgs.FILE_NAME) - - # Set auto boot - if not ConfigArgs.NO_SET_BOOTABLE: - print(">>> Save Configuration to FlashROM ...") - writer.send("set bootable M0P") - writer.wait_for_prompt() - - # Sync all cached data to flash - writer.send("sync") - writer.wait_for_prompt() - - if REBOOT_AT_END : - print("Restarting the board ...") - writer.send("reboot") - - return 0 + try: + config_loader = ConfigArgsLoader() + config_loader.update_config() + except: + return errno.EINVAL + + # Wait to reset the board + writer = FlashWriter(ConfigArgs.PROTOCOL_TYPE) + + do_wait_reset = True + if ConfigArgs.AUTO_RESET: + if subprocess.call("cd " + sys.path[0] + "; ./reset_board.sh", shell=True) == 0: + print("auto reset board sucess!!") + do_wait_reset = False + bootrom_msg = writer.cancel_autoboot() + + if ConfigArgs.DTR_RESET: + do_wait_reset = False + bootrom_msg = writer.cancel_autoboot() + + if ConfigArgs.WAIT_RESET == False and do_wait_reset == True: + rx = writer.recv() + time.sleep(1) + for i in range(3): + writer.send("") + rx = writer.recv() + if "updater".encode() in rx: + # No need to wait for reset + do_wait_reset = False + break + time.sleep(1) + + if do_wait_reset: + # Wait to reset the board + print("Please press RESET button on target board") + sys.stdout.flush() + bootrom_msg = writer.cancel_autoboot() + + # Remove files + if ConfigArgs.ERASE_NAME: + print(">>> Remove exisiting files ...") + writer.delete_files(ConfigArgs.ERASE_NAME) + + # Install files + if ( + ConfigArgs.PACKAGE_NAME + or ConfigArgs.PKGSYS_NAME + or ConfigArgs.PKGAPP_NAME + or ConfigArgs.PKGUPD_NAME + ): + print(">>> Install files ...") + if ConfigArgs.PACKAGE_NAME: + writer.install_files(ConfigArgs.PACKAGE_NAME, "install") + if ConfigArgs.PKGSYS_NAME: + writer.install_files(ConfigArgs.PKGSYS_NAME, "install") + if ConfigArgs.PKGAPP_NAME: + writer.install_files(ConfigArgs.PKGAPP_NAME, "install") + if ConfigArgs.PKGUPD_NAME: + writer.install_files(ConfigArgs.PKGUPD_NAME, "install -k updater.key") + + # Save files + if ConfigArgs.FILE_NAME: + print(">>> Save files ...") + writer.save_files(ConfigArgs.FILE_NAME) + + # Set auto boot + if not ConfigArgs.NO_SET_BOOTABLE: + print(">>> Save Configuration to FlashROM ...") + writer.send("set bootable M0P") + writer.wait_for_prompt() + + # Sync all cached data to flash + writer.send("sync") + writer.wait_for_prompt() + + if REBOOT_AT_END: + print("Restarting the board ...") + writer.send("reboot") + + return 0 + if __name__ == "__main__": - try: - sys.exit(main()) - except KeyboardInterrupt: - print("Canceled by keyboard interrupt.") - pass + try: + sys.exit(main()) + except KeyboardInterrupt: + print("Canceled by keyboard interrupt.") + pass diff --git a/ports/cxd56/tools/xmodem.py b/ports/cxd56/tools/xmodem.py index c93430056..cf7833864 100644 --- a/ports/cxd56/tools/xmodem.py +++ b/ports/cxd56/tools/xmodem.py @@ -1,4 +1,4 @@ -''' +""" =============================== XMODEM file transfer protocol =============================== @@ -105,13 +105,12 @@ YMODEM Batch Transmission Session (1 file) <-- ACK -''' +""" -__author__ = 'Wijnand Modderman <maze@pyth0n.org>' -__copyright__ = ['Copyright (c) 2010 Wijnand Modderman', - 'Copyright (c) 1981 Chuck Forsberg'] -__license__ = 'MIT' -__version__ = '0.3.2' +__author__ = "Wijnand Modderman <maze@pyth0n.org>" +__copyright__ = ["Copyright (c) 2010 Wijnand Modderman", "Copyright (c) 1981 Chuck Forsberg"] +__license__ = "MIT" +__version__ = "0.3.2" import logging import time @@ -120,7 +119,7 @@ from functools import partial import collections # Loggerr -log = logging.getLogger('xmodem') +log = logging.getLogger("xmodem") # Protocol bytes SOH = bytes([0x01]) @@ -130,11 +129,11 @@ ACK = bytes([0x06]) DLE = bytes([0x10]) NAK = bytes([0x15]) CAN = bytes([0x18]) -CRC = bytes([0x43]) # C +CRC = bytes([0x43]) # C class XMODEM(object): - ''' + """ XMODEM Protocol handler, expects an object to read from and an object to write to. @@ -156,59 +155,283 @@ class XMODEM(object): :param pad: Padding character to make the packets match the packet size :type pad: char - ''' + """ # crctab calculated by Mark G. Mendel, Network Systems Corporation crctable = [ - 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, - 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, - 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, - 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, - 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, - 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, - 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, - 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, - 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, - 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, - 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, - 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, - 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, - 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, - 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, - 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, - 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, - 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, - 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, - 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, - 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, - 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, + 0x0000, + 0x1021, + 0x2042, + 0x3063, + 0x4084, + 0x50A5, + 0x60C6, + 0x70E7, + 0x8108, + 0x9129, + 0xA14A, + 0xB16B, + 0xC18C, + 0xD1AD, + 0xE1CE, + 0xF1EF, + 0x1231, + 0x0210, + 0x3273, + 0x2252, + 0x52B5, + 0x4294, + 0x72F7, + 0x62D6, + 0x9339, + 0x8318, + 0xB37B, + 0xA35A, + 0xD3BD, + 0xC39C, + 0xF3FF, + 0xE3DE, + 0x2462, + 0x3443, + 0x0420, + 0x1401, + 0x64E6, + 0x74C7, + 0x44A4, + 0x5485, + 0xA56A, + 0xB54B, + 0x8528, + 0x9509, + 0xE5EE, + 0xF5CF, + 0xC5AC, + 0xD58D, + 0x3653, + 0x2672, + 0x1611, + 0x0630, + 0x76D7, + 0x66F6, + 0x5695, + 0x46B4, + 0xB75B, + 0xA77A, + 0x9719, + 0x8738, + 0xF7DF, + 0xE7FE, + 0xD79D, + 0xC7BC, + 0x48C4, + 0x58E5, + 0x6886, + 0x78A7, + 0x0840, + 0x1861, + 0x2802, + 0x3823, + 0xC9CC, + 0xD9ED, + 0xE98E, + 0xF9AF, + 0x8948, + 0x9969, + 0xA90A, + 0xB92B, + 0x5AF5, + 0x4AD4, + 0x7AB7, + 0x6A96, + 0x1A71, + 0x0A50, + 0x3A33, + 0x2A12, + 0xDBFD, + 0xCBDC, + 0xFBBF, + 0xEB9E, + 0x9B79, + 0x8B58, + 0xBB3B, + 0xAB1A, + 0x6CA6, + 0x7C87, + 0x4CE4, + 0x5CC5, + 0x2C22, + 0x3C03, + 0x0C60, + 0x1C41, + 0xEDAE, + 0xFD8F, + 0xCDEC, + 0xDDCD, + 0xAD2A, + 0xBD0B, + 0x8D68, + 0x9D49, + 0x7E97, + 0x6EB6, + 0x5ED5, + 0x4EF4, + 0x3E13, + 0x2E32, + 0x1E51, + 0x0E70, + 0xFF9F, + 0xEFBE, + 0xDFDD, + 0xCFFC, + 0xBF1B, + 0xAF3A, + 0x9F59, + 0x8F78, + 0x9188, + 0x81A9, + 0xB1CA, + 0xA1EB, + 0xD10C, + 0xC12D, + 0xF14E, + 0xE16F, + 0x1080, + 0x00A1, + 0x30C2, + 0x20E3, + 0x5004, + 0x4025, + 0x7046, + 0x6067, + 0x83B9, + 0x9398, + 0xA3FB, + 0xB3DA, + 0xC33D, + 0xD31C, + 0xE37F, + 0xF35E, + 0x02B1, + 0x1290, + 0x22F3, + 0x32D2, + 0x4235, + 0x5214, + 0x6277, + 0x7256, + 0xB5EA, + 0xA5CB, + 0x95A8, + 0x8589, + 0xF56E, + 0xE54F, + 0xD52C, + 0xC50D, + 0x34E2, + 0x24C3, + 0x14A0, + 0x0481, + 0x7466, + 0x6447, + 0x5424, + 0x4405, + 0xA7DB, + 0xB7FA, + 0x8799, + 0x97B8, + 0xE75F, + 0xF77E, + 0xC71D, + 0xD73C, + 0x26D3, + 0x36F2, + 0x0691, + 0x16B0, + 0x6657, + 0x7676, + 0x4615, + 0x5634, + 0xD94C, + 0xC96D, + 0xF90E, + 0xE92F, + 0x99C8, + 0x89E9, + 0xB98A, + 0xA9AB, + 0x5844, + 0x4865, + 0x7806, + 0x6827, + 0x18C0, + 0x08E1, + 0x3882, + 0x28A3, + 0xCB7D, + 0xDB5C, + 0xEB3F, + 0xFB1E, + 0x8BF9, + 0x9BD8, + 0xABBB, + 0xBB9A, + 0x4A75, + 0x5A54, + 0x6A37, + 0x7A16, + 0x0AF1, + 0x1AD0, + 0x2AB3, + 0x3A92, + 0xFD2E, + 0xED0F, + 0xDD6C, + 0xCD4D, + 0xBDAA, + 0xAD8B, + 0x9DE8, + 0x8DC9, + 0x7C26, + 0x6C07, + 0x5C64, + 0x4C45, + 0x3CA2, + 0x2C83, + 0x1CE0, + 0x0CC1, + 0xEF1F, + 0xFF3E, + 0xCF5D, + 0xDF7C, + 0xAF9B, + 0xBFBA, + 0x8FD9, + 0x9FF8, + 0x6E17, + 0x7E36, + 0x4E55, + 0x5E74, + 0x2E93, + 0x3EB2, + 0x0ED1, + 0x1EF0, ] - def __init__(self, getc, putc, mode='xmodem', pad=b'\x1a'): + def __init__(self, getc, putc, mode="xmodem", pad=b"\x1a"): self.getc = getc self.putc = putc self.mode = mode self.pad = pad def abort(self, count=2, timeout=60): - ''' + """ Send an abort sequence using CAN bytes. - ''' + """ for counter in range(0, count): self.putc(CAN, timeout) def send(self, stream, retry=32, timeout=360, quiet=0, callback=None): - ''' + """ Send a stream via the XMODEM protocol. >>> stream = file('/etc/issue', 'rb') @@ -235,14 +458,11 @@ class XMODEM(object): Expected callback signature: def callback(total_packets, success_count, error_count) :type callback: callable - ''' + """ # initialize protocol try: - packet_size = dict( - xmodem = 128, - xmodem1k = 1024, - )[self.mode] + packet_size = dict(xmodem=128, xmodem1k=1024)[self.mode] except AttributeError: raise ValueError("An invalid mode was supplied") @@ -260,14 +480,13 @@ class XMODEM(object): break elif char == CAN: if not quiet: - print('received CAN', file=sys.stderr) + print("received CAN", file=sys.stderr) if cancel: return False else: cancel = 1 else: - log.error('send ERROR expected NAK/CRC, got %s' % \ - (ord(char),)) + log.error("send ERROR expected NAK/CRC, got %s" % (ord(char),)) error_count += 1 if error_count >= retry: @@ -282,7 +501,7 @@ class XMODEM(object): while True: data = stream.read(packet_size) if not data: - log.info('sending EOT') + log.info("sending EOT") # end of stream break total_packets += 1 @@ -299,11 +518,11 @@ class XMODEM(object): else: # packet_size == 1024 self.putc(STX) self.putc(bytes([sequence])) - self.putc(bytes([0xff - sequence])) + self.putc(bytes([0xFF - sequence])) self.putc(data) if crc_mode: self.putc(bytes([crc >> 8])) - self.putc(bytes([crc & 0xff])) + self.putc(bytes([crc & 0xFF])) else: self.putc(bytes([crc])) @@ -321,13 +540,13 @@ class XMODEM(object): # excessive amounts of retransmissions requested, # abort transfer self.abort(timeout=timeout) - log.warning('excessive NAKs, transfer aborted') + log.warning("excessive NAKs, transfer aborted") return False # return to loop and resend continue else: - log.error('Not ACK, Not NAK') + log.error("Not ACK, Not NAK") error_count += 1 if isinstance(callback, collections.Callable): callback(total_packets, success_count, error_count) @@ -335,7 +554,7 @@ class XMODEM(object): # excessive amounts of retransmissions requested, # abort transfer self.abort(timeout=timeout) - log.warning('excessive protocol errors, transfer aborted') + log.warning("excessive protocol errors, transfer aborted") return False # return to loop and resend @@ -343,7 +562,7 @@ class XMODEM(object): # protocol error self.abort(timeout=timeout) - log.error('protocol error') + log.error("protocol error") return False # keep track of sequence @@ -353,7 +572,7 @@ class XMODEM(object): # end of transmission self.putc(EOT) - #An ACK should be returned + # An ACK should be returned char = self.getc(1, timeout) if char == ACK: break @@ -361,13 +580,13 @@ class XMODEM(object): error_count += 1 if error_count >= retry: self.abort(timeout=timeout) - log.warning('EOT was not ACKd, transfer aborted') + log.warning("EOT was not ACKd, transfer aborted") return False return True def recv(self, stream, crc_mode=1, retry=16, timeout=60, delay=1, quiet=0): - ''' + """ Receive a stream via the XMODEM protocol. >>> stream = file('/etc/issue', 'wb') @@ -376,7 +595,7 @@ class XMODEM(object): Returns the number of bytes received on success or ``None`` in case of failure. - ''' + """ # initiate protocol error_count = 0 @@ -403,7 +622,7 @@ class XMODEM(object): error_count += 1 continue elif char == SOH: - #crc_mode = 0 + # crc_mode = 0 break elif char == STX: break @@ -442,7 +661,7 @@ class XMODEM(object): cancel = 1 else: if not quiet: - print('recv ERROR expected SOH/EOT, got', ord(char), file=sys.stderr) + print("recv ERROR expected SOH/EOT, got", ord(char), file=sys.stderr) error_count += 1 if error_count >= retry: self.abort() @@ -451,7 +670,7 @@ class XMODEM(object): error_count = 0 cancel = 0 seq1 = ord(self.getc(1)) - seq2 = 0xff - ord(self.getc(1)) + seq2 = 0xFF - ord(self.getc(1)) if seq1 == sequence and seq2 == sequence: # sequence is ok, read packet # packet_size + checksum @@ -459,14 +678,14 @@ class XMODEM(object): if crc_mode: csum = (ord(data[-2]) << 8) + ord(data[-1]) data = data[:-2] - log.debug('CRC (%04x <> %04x)' % \ - (csum, self.calc_crc(data))) + log.debug("CRC (%04x <> %04x)" % (csum, self.calc_crc(data))) valid = csum == self.calc_crc(data) else: csum = data[-1] data = data[:-1] - log.debug('checksum (checksum(%02x <> %02x)' % \ - (ord(csum), self.calc_checksum(data))) + log.debug( + "checksum (checksum(%02x <> %02x)" % (ord(csum), self.calc_checksum(data)) + ) valid = ord(csum) == self.calc_checksum(data) # valid data, append chunk @@ -480,14 +699,13 @@ class XMODEM(object): else: # consume data self.getc(packet_size + 1 + crc_mode) - self.debug('expecting sequence %d, got %d/%d' % \ - (sequence, seq1, seq2)) + self.debug("expecting sequence %d, got %d/%d" % (sequence, seq1, seq2)) # something went wrong, request retransmission self.putc(NAK) def calc_checksum(self, data, checksum=0): - ''' + """ Calculate the checksum for a given block of data, can also be used to update a checksum. @@ -496,11 +714,11 @@ class XMODEM(object): >>> hex(csum) '0x3c' - ''' + """ return (sum(map(ord, data)) + checksum) % 256 def calc_crc(self, data, crc=0): - ''' + """ Calculate the Cyclic Redundancy Check for a given block of data, can also be used to update a CRC. @@ -509,51 +727,50 @@ class XMODEM(object): >>> hex(crc) '0xd5e3' - ''' + """ for char in data: - crc = (crc << 8) ^ self.crctable[((crc >> 8) ^ int(char)) & 0xff] - return crc & 0xffff + crc = (crc << 8) ^ self.crctable[((crc >> 8) ^ int(char)) & 0xFF] + return crc & 0xFFFF -XMODEM1k = partial(XMODEM, mode='xmodem1k') +XMODEM1k = partial(XMODEM, mode="xmodem1k") def run(): import optparse import subprocess - parser = optparse.OptionParser(usage='%prog [<options>] <send|recv> filename filename') - parser.add_option('-m', '--mode', default='xmodem', - help='XMODEM mode (xmodem, xmodem1k)') + parser = optparse.OptionParser(usage="%prog [<options>] <send|recv> filename filename") + parser.add_option("-m", "--mode", default="xmodem", help="XMODEM mode (xmodem, xmodem1k)") options, args = parser.parse_args() if len(args) != 3: - parser.error('invalid arguments') + parser.error("invalid arguments") return 1 - elif args[0] not in ('send', 'recv'): - parser.error('invalid mode') + elif args[0] not in ("send", "recv"): + parser.error("invalid mode") return 1 def _func(so, si): import select import subprocess - print('si', si) - print('so', so) + print("si", si) + print("so", so) def getc(size, timeout=3): - w,t,f = select.select([so], [], [], timeout) + w, t, f = select.select([so], [], [], timeout) if w: data = so.read(size) else: data = None - print('getc(', repr(data), ')') + print("getc(", repr(data), ")") return data def putc(data, timeout=3): - w,t,f = select.select([], [si], [], timeout) + w, t, f = select.select([], [si], [], timeout) if t: si.write(data) si.flush() @@ -561,30 +778,31 @@ def run(): else: size = None - print('putc(', repr(data), repr(size), ')') + print("putc(", repr(data), repr(size), ")") return size return getc, putc def _pipe(*command): - pipe = subprocess.Popen(command, - stdout=subprocess.PIPE, stdin=subprocess.PIPE) + pipe = subprocess.Popen(command, stdout=subprocess.PIPE, stdin=subprocess.PIPE) return pipe.stdout, pipe.stdin - if args[0] == 'recv': + if args[0] == "recv": import io - getc, putc = _func(*_pipe('sz', '--xmodem', args[2])) - stream = open(args[1], 'wb') + + getc, putc = _func(*_pipe("sz", "--xmodem", args[2])) + stream = open(args[1], "wb") xmodem = XMODEM(getc, putc, mode=options.mode) status = xmodem.recv(stream, retry=8) stream.close() - elif args[0] == 'send': - getc, putc = _func(*_pipe('rz', '--xmodem', args[2])) - stream = open(args[1], 'rb') + elif args[0] == "send": + getc, putc = _func(*_pipe("rz", "--xmodem", args[2])) + stream = open(args[1], "rb") xmodem = XMODEM(getc, putc, mode=options.mode) status = xmodem.send(stream, retry=8) stream.close() -if __name__ == '__main__': + +if __name__ == "__main__": sys.exit(run()) diff --git a/ports/esp32s2/background.c b/ports/esp32s2/background.c index 3160d9974..80b60bebe 100644 --- a/ports/esp32s2/background.c +++ b/ports/esp32s2/background.c @@ -48,6 +48,8 @@ void port_background_task(void) { #endif } -void port_start_background_task(void) {} +void port_start_background_task(void) { +} -void port_finish_background_task(void) {} +void port_finish_background_task(void) { +} diff --git a/ports/esp32s2/bindings/espidf/__init__.c b/ports/esp32s2/bindings/espidf/__init__.c index 708c30c39..97e1136f8 100644 --- a/ports/esp32s2/bindings/espidf/__init__.c +++ b/ports/esp32s2/bindings/espidf/__init__.c @@ -125,13 +125,13 @@ STATIC MP_DEFINE_CONST_DICT(espidf_module_globals, espidf_module_globals_table); const mp_obj_module_t espidf_module = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&espidf_module_globals, + .globals = (mp_obj_dict_t *)&espidf_module_globals, }; void raise_esp_error(esp_err_t err) { const compressed_string_t *msg = NULL; - const mp_obj_type_t * exception_type = &mp_type_espidf_IDFError; - switch(err) { + const mp_obj_type_t *exception_type = &mp_type_espidf_IDFError; + switch (err) { case ESP_FAIL: msg = translate("Generic Failure"); break; @@ -177,9 +177,9 @@ void raise_esp_error(esp_err_t err) { const char *group = "ESP-IDF"; // tests must be in descending order - MP_STATIC_ASSERT( ESP_ERR_FLASH_BASE > ESP_ERR_MESH_BASE ); - MP_STATIC_ASSERT( ESP_ERR_MESH_BASE > ESP_ERR_WIFI_BASE ); - if(err >= ESP_ERR_FLASH_BASE) { + MP_STATIC_ASSERT(ESP_ERR_FLASH_BASE > ESP_ERR_MESH_BASE); + MP_STATIC_ASSERT(ESP_ERR_MESH_BASE > ESP_ERR_WIFI_BASE); + if (err >= ESP_ERR_FLASH_BASE) { group = "Flash"; } else if (err >= ESP_ERR_MESH_BASE) { group = "Mesh"; diff --git a/ports/esp32s2/bindings/espidf/__init__.h b/ports/esp32s2/bindings/espidf/__init__.h index 9248b01ac..866edb128 100644 --- a/ports/esp32s2/bindings/espidf/__init__.h +++ b/ports/esp32s2/bindings/espidf/__init__.h @@ -37,6 +37,6 @@ extern const mp_obj_type_t mp_type_espidf_MemoryError; NORETURN void mp_raise_espidf_MemoryError(void); void raise_esp_error(esp_err_t err) NORETURN; -#define CHECK_ESP_RESULT(x) do { int res = (x); if(res != ESP_OK) raise_esp_error(res); } while(0) +#define CHECK_ESP_RESULT(x) do { int res = (x); if (res != ESP_OK) raise_esp_error(res); } while (0) #endif // MICROPY_INCLUDED_ESP32S2_BINDINGS_ESPIDF___INIT___H diff --git a/ports/esp32s2/boards/adafruit_feather_esp32s2_nopsram/board.c b/ports/esp32s2/boards/adafruit_feather_esp32s2_nopsram/board.c index aaef97c7d..e40b6335b 100644 --- a/ports/esp32s2/boards/adafruit_feather_esp32s2_nopsram/board.c +++ b/ports/esp32s2/boards/adafruit_feather_esp32s2_nopsram/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/adafruit_feather_esp32s2_nopsram/mpconfigboard.h b/ports/esp32s2/boards/adafruit_feather_esp32s2_nopsram/mpconfigboard.h index 9d95e8e43..a04065d25 100644 --- a/ports/esp32s2/boards/adafruit_feather_esp32s2_nopsram/mpconfigboard.h +++ b/ports/esp32s2/boards/adafruit_feather_esp32s2_nopsram/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Feather ESP32S2 without PSRAM" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/board.c b/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/board.c index c8be18747..799494006 100644 --- a/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/board.c +++ b/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/board.c @@ -55,10 +55,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ /* busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; diff --git a/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/mpconfigboard.h b/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/mpconfigboard.h index 9d95e8e43..a04065d25 100644 --- a/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/mpconfigboard.h +++ b/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Feather ESP32S2 without PSRAM" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/pins.c b/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/pins.c index 7e1a72374..0504f9694 100644 --- a/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/pins.c +++ b/ports/esp32s2/boards/adafruit_feather_esp32s2_tftback_nopsram/pins.c @@ -67,6 +67,6 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, - // { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].display)} + // { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].display)} }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/esp32s2/boards/adafruit_magtag_2.9_grayscale/board.c b/ports/esp32s2/boards/adafruit_magtag_2.9_grayscale/board.c index 63a16c120..020e6f6a1 100644 --- a/ports/esp32s2/boards/adafruit_magtag_2.9_grayscale/board.c +++ b/ports/esp32s2/boards/adafruit_magtag_2.9_grayscale/board.c @@ -35,7 +35,7 @@ #include "components/log/include/esp_log.h" -static const char* TAG = "board"; +static const char *TAG = "board"; #define DELAY 0x80 @@ -115,16 +115,16 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_GPIO36, &pin_GPIO35, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -135,7 +135,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_epaperdisplay_obj_t* display = &displays[0].epaper_display; + displayio_epaperdisplay_obj_t *display = &displays[0].epaper_display; display->base.type = &displayio_epaperdisplay_type; common_hal_displayio_epaperdisplay_construct( display, @@ -176,7 +176,7 @@ void reset_board(void) { } void board_deinit(void) { - displayio_epaperdisplay_obj_t* display = &displays[0].epaper_display; + displayio_epaperdisplay_obj_t *display = &displays[0].epaper_display; if (display->base.type == &displayio_epaperdisplay_type) { size_t i = 0; while (common_hal_displayio_epaperdisplay_get_busy(display)) { diff --git a/ports/esp32s2/boards/adafruit_magtag_2.9_grayscale/mpconfigboard.h b/ports/esp32s2/boards/adafruit_magtag_2.9_grayscale/mpconfigboard.h index 8dfe91271..ecfa1d78b 100644 --- a/ports/esp32s2/boards/adafruit_magtag_2.9_grayscale/mpconfigboard.h +++ b/ports/esp32s2/boards/adafruit_magtag_2.9_grayscale/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Adafruit MagTag" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.h b/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.h index b25d7d116..ec992383a 100644 --- a/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.h +++ b/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Adafruit Metro ESP32S2" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/electroniccats_bastwifi/board.c b/ports/esp32s2/boards/electroniccats_bastwifi/board.c index aaef97c7d..e40b6335b 100644 --- a/ports/esp32s2/boards/electroniccats_bastwifi/board.c +++ b/ports/esp32s2/boards/electroniccats_bastwifi/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/electroniccats_bastwifi/mpconfigboard.h b/ports/esp32s2/boards/electroniccats_bastwifi/mpconfigboard.h index 1ec61e946..cc4fd40df 100644 --- a/ports/esp32s2/boards/electroniccats_bastwifi/mpconfigboard.h +++ b/ports/esp32s2/boards/electroniccats_bastwifi/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "BastWiFi" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/espressif_kaluga_1/board.c b/ports/esp32s2/boards/espressif_kaluga_1/board.c index aaef97c7d..e40b6335b 100644 --- a/ports/esp32s2/boards/espressif_kaluga_1/board.c +++ b/ports/esp32s2/boards/espressif_kaluga_1/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/espressif_kaluga_1/mpconfigboard.h b/ports/esp32s2/boards/espressif_kaluga_1/mpconfigboard.h index 2c0f175ab..21f6ae245 100644 --- a/ports/esp32s2/boards/espressif_kaluga_1/mpconfigboard.h +++ b/ports/esp32s2/boards/espressif_kaluga_1/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Kaluga 1" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/espressif_saola_1_wroom/board.c b/ports/esp32s2/boards/espressif_saola_1_wroom/board.c index aaef97c7d..e40b6335b 100644 --- a/ports/esp32s2/boards/espressif_saola_1_wroom/board.c +++ b/ports/esp32s2/boards/espressif_saola_1_wroom/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.h b/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.h index 3f628c0f1..2aac10fe7 100644 --- a/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.h +++ b/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Saola 1 w/Wroom" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/espressif_saola_1_wrover/board.c b/ports/esp32s2/boards/espressif_saola_1_wrover/board.c index aaef97c7d..e40b6335b 100644 --- a/ports/esp32s2/boards/espressif_saola_1_wrover/board.c +++ b/ports/esp32s2/boards/espressif_saola_1_wrover/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.h b/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.h index 961522891..a5aa83814 100644 --- a/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.h +++ b/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Saola 1 w/Wrover" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/franzininho_wifi_wroom/board.c b/ports/esp32s2/boards/franzininho_wifi_wroom/board.c index aaef97c7d..e40b6335b 100644 --- a/ports/esp32s2/boards/franzininho_wifi_wroom/board.c +++ b/ports/esp32s2/boards/franzininho_wifi_wroom/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/franzininho_wifi_wroom/mpconfigboard.h b/ports/esp32s2/boards/franzininho_wifi_wroom/mpconfigboard.h index 0960e96b6..c0a8659b1 100644 --- a/ports/esp32s2/boards/franzininho_wifi_wroom/mpconfigboard.h +++ b/ports/esp32s2/boards/franzininho_wifi_wroom/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Franzininho WIFI w/Wroom" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/franzininho_wifi_wrover/board.c b/ports/esp32s2/boards/franzininho_wifi_wrover/board.c index aaef97c7d..e40b6335b 100644 --- a/ports/esp32s2/boards/franzininho_wifi_wrover/board.c +++ b/ports/esp32s2/boards/franzininho_wifi_wrover/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/franzininho_wifi_wrover/mpconfigboard.h b/ports/esp32s2/boards/franzininho_wifi_wrover/mpconfigboard.h index fd10ee0b5..b17a65c10 100644 --- a/ports/esp32s2/boards/franzininho_wifi_wrover/mpconfigboard.h +++ b/ports/esp32s2/boards/franzininho_wifi_wrover/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Franzininho WIFI w/Wrover" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/lilygo_ttgo_t8_s2_st7789/board.c b/ports/esp32s2/boards/lilygo_ttgo_t8_s2_st7789/board.c index 4aa7b3b24..1002fa6b7 100644 --- a/ports/esp32s2/boards/lilygo_ttgo_t8_s2_st7789/board.c +++ b/ports/esp32s2/boards/lilygo_ttgo_t8_s2_st7789/board.c @@ -62,21 +62,21 @@ uint8_t display_init_sequence[] = { 0x21, 0, // display on 0x29, 0 | DELAY, 255, - }; +}; static void display_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct( spi, &pin_GPIO36, // CLK &pin_GPIO35, // MOSI NULL // MISO not connected - ); + ); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct( @@ -88,9 +88,9 @@ static void display_init(void) { 40000000, // baudrate 0, // polarity 0 // phase - ); + ); - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; // workaround as board_init() is called before reset_port() in main.c @@ -126,7 +126,7 @@ static void display_init(void) { 60, // native_frames_per_second true, // backlight_on_high false // SH1107_addressing - ); + ); common_hal_never_reset_pin(&pin_GPIO33); // backlight pin } @@ -137,10 +137,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ // Display display_init(); diff --git a/ports/esp32s2/boards/lilygo_ttgo_t8_s2_st7789/mpconfigboard.h b/ports/esp32s2/boards/lilygo_ttgo_t8_s2_st7789/mpconfigboard.h index c9020c200..c9159b6f3 100644 --- a/ports/esp32s2/boards/lilygo_ttgo_t8_s2_st7789/mpconfigboard.h +++ b/ports/esp32s2/boards/lilygo_ttgo_t8_s2_st7789/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "LILYGO TTGO T8 ESP32-S2 w/Display" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/microdev_micro_s2/board.c b/ports/esp32s2/boards/microdev_micro_s2/board.c index d8fd3a0a2..a0e399b1e 100644 --- a/ports/esp32s2/boards/microdev_micro_s2/board.c +++ b/ports/esp32s2/boards/microdev_micro_s2/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ // SPI Flash and RAM common_hal_never_reset_pin(&pin_GPIO26); diff --git a/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h b/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h index 272ab20fa..47bcde7e9 100644 --- a/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h +++ b/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "microS2" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/muselab_nanoesp32_s2/board.c b/ports/esp32s2/boards/muselab_nanoesp32_s2/board.c index aaef97c7d..e40b6335b 100644 --- a/ports/esp32s2/boards/muselab_nanoesp32_s2/board.c +++ b/ports/esp32s2/boards/muselab_nanoesp32_s2/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ } bool board_requests_safe_mode(void) { diff --git a/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h b/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h index 6b05ac06f..161215397 100644 --- a/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h +++ b/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "nanoESP32-S2" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/targett_module_clip_wroom/board.c b/ports/esp32s2/boards/targett_module_clip_wroom/board.c index 9c58dd2c8..00b94a025 100644 --- a/ports/esp32s2/boards/targett_module_clip_wroom/board.c +++ b/ports/esp32s2/boards/targett_module_clip_wroom/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ // Crystal common_hal_never_reset_pin(&pin_GPIO15); diff --git a/ports/esp32s2/boards/targett_module_clip_wroom/mpconfigboard.h b/ports/esp32s2/boards/targett_module_clip_wroom/mpconfigboard.h index 6cf69138e..fe57007a9 100644 --- a/ports/esp32s2/boards/targett_module_clip_wroom/mpconfigboard.h +++ b/ports/esp32s2/boards/targett_module_clip_wroom/mpconfigboard.h @@ -24,14 +24,14 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup -//Essentially the same as the Saola board but without the neopixel +// Essentially the same as the Saola board but without the neopixel #define MICROPY_HW_BOARD_NAME "Targett Module Clip w/Wroom" #define MICROPY_HW_MCU_NAME "ESP32S2" -//#define MICROPY_HW_NEOPIXEL (&pin_GPIO18) +// #define MICROPY_HW_NEOPIXEL (&pin_GPIO18) #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0) diff --git a/ports/esp32s2/boards/targett_module_clip_wroom/pins.c b/ports/esp32s2/boards/targett_module_clip_wroom/pins.c index 99db09645..a8ca8ba3e 100644 --- a/ports/esp32s2/boards/targett_module_clip_wroom/pins.c +++ b/ports/esp32s2/boards/targett_module_clip_wroom/pins.c @@ -43,6 +43,6 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_IO45), MP_ROM_PTR(&pin_GPIO45) }, { MP_ROM_QSTR(MP_QSTR_IO46), MP_ROM_PTR(&pin_GPIO46) }, - //{ MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO18) }, + // { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO18) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/esp32s2/boards/targett_module_clip_wrover/board.c b/ports/esp32s2/boards/targett_module_clip_wrover/board.c index f5e66acb6..00b94a025 100644 --- a/ports/esp32s2/boards/targett_module_clip_wrover/board.c +++ b/ports/esp32s2/boards/targett_module_clip_wrover/board.c @@ -34,12 +34,12 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ - //Crystal + // Crystal common_hal_never_reset_pin(&pin_GPIO15); common_hal_never_reset_pin(&pin_GPIO16); } diff --git a/ports/esp32s2/boards/targett_module_clip_wrover/mpconfigboard.h b/ports/esp32s2/boards/targett_module_clip_wrover/mpconfigboard.h index 3c74d27fa..c36ab50d1 100644 --- a/ports/esp32s2/boards/targett_module_clip_wrover/mpconfigboard.h +++ b/ports/esp32s2/boards/targett_module_clip_wrover/mpconfigboard.h @@ -24,14 +24,14 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup -//Same setup as the Saola board but with no Neopixel on board +// Same setup as the Saola board but with no Neopixel on board #define MICROPY_HW_BOARD_NAME "Targett Module Clip w/Wrover" #define MICROPY_HW_MCU_NAME "ESP32S2" -//#define MICROPY_HW_NEOPIXEL (&pin_GPIO18) +// #define MICROPY_HW_NEOPIXEL (&pin_GPIO18) #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0) diff --git a/ports/esp32s2/boards/targett_module_clip_wrover/pins.c b/ports/esp32s2/boards/targett_module_clip_wrover/pins.c index 99db09645..a8ca8ba3e 100644 --- a/ports/esp32s2/boards/targett_module_clip_wrover/pins.c +++ b/ports/esp32s2/boards/targett_module_clip_wrover/pins.c @@ -43,6 +43,6 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_IO45), MP_ROM_PTR(&pin_GPIO45) }, { MP_ROM_QSTR(MP_QSTR_IO46), MP_ROM_PTR(&pin_GPIO46) }, - //{ MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO18) }, + // { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO18) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2/board.c b/ports/esp32s2/boards/unexpectedmaker_feathers2/board.c index d8fd3a0a2..a0e399b1e 100644 --- a/ports/esp32s2/boards/unexpectedmaker_feathers2/board.c +++ b/ports/esp32s2/boards/unexpectedmaker_feathers2/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ // SPI Flash and RAM common_hal_never_reset_pin(&pin_GPIO26); diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.h b/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.h index e100ac118..57f35018d 100644 --- a/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.h +++ b/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "FeatherS2" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/board.c b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/board.c index d8fd3a0a2..a0e399b1e 100644 --- a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/board.c +++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ // SPI Flash and RAM common_hal_never_reset_pin(&pin_GPIO26); diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h index d550ff64f..7304512aa 100644 --- a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h +++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "FeatherS2 PreRelease" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/boards/unexpectedmaker_tinys2/board.c b/ports/esp32s2/boards/unexpectedmaker_tinys2/board.c index d8fd3a0a2..a0e399b1e 100644 --- a/ports/esp32s2/boards/unexpectedmaker_tinys2/board.c +++ b/ports/esp32s2/boards/unexpectedmaker_tinys2/board.c @@ -34,10 +34,10 @@ void board_init(void) { common_hal_never_reset_pin(&pin_GPIO20); // Debug UART -#ifdef DEBUG + #ifdef DEBUG common_hal_never_reset_pin(&pin_GPIO43); common_hal_never_reset_pin(&pin_GPIO44); -#endif /* DEBUG */ + #endif /* DEBUG */ // SPI Flash and RAM common_hal_never_reset_pin(&pin_GPIO26); diff --git a/ports/esp32s2/boards/unexpectedmaker_tinys2/mpconfigboard.h b/ports/esp32s2/boards/unexpectedmaker_tinys2/mpconfigboard.h index 85f252328..e7d50f089 100644 --- a/ports/esp32s2/boards/unexpectedmaker_tinys2/mpconfigboard.h +++ b/ports/esp32s2/boards/unexpectedmaker_tinys2/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "TinyS2" #define MICROPY_HW_MCU_NAME "ESP32S2" diff --git a/ports/esp32s2/common-hal/alarm/SleepMemory.c b/ports/esp32s2/common-hal/alarm/SleepMemory.c index 38e3de2b6..b25bf28d2 100644 --- a/ports/esp32s2/common-hal/alarm/SleepMemory.c +++ b/ports/esp32s2/common-hal/alarm/SleepMemory.c @@ -47,20 +47,20 @@ uint32_t common_hal_alarm_sleep_memory_get_length(alarm_sleep_memory_obj_t *self return sizeof(_sleep_mem); } -bool common_hal_alarm_sleep_memory_set_bytes(alarm_sleep_memory_obj_t *self, uint32_t start_index, const uint8_t* values, uint32_t len) { +bool common_hal_alarm_sleep_memory_set_bytes(alarm_sleep_memory_obj_t *self, uint32_t start_index, const uint8_t *values, uint32_t len) { if (start_index + len > sizeof(_sleep_mem)) { return false; } - memcpy((uint8_t *) (_sleep_mem + start_index), values, len); + memcpy((uint8_t *)(_sleep_mem + start_index), values, len); return true; } -void common_hal_alarm_sleep_memory_get_bytes(alarm_sleep_memory_obj_t *self, uint32_t start_index, uint8_t* values, uint32_t len) { +void common_hal_alarm_sleep_memory_get_bytes(alarm_sleep_memory_obj_t *self, uint32_t start_index, uint8_t *values, uint32_t len) { if (start_index + len > sizeof(_sleep_mem)) { return; } - memcpy(values, (uint8_t *) (_sleep_mem + start_index), len); + memcpy(values, (uint8_t *)(_sleep_mem + start_index), len); } diff --git a/ports/esp32s2/common-hal/alarm/pin/PinAlarm.c b/ports/esp32s2/common-hal/alarm/pin/PinAlarm.c index df8d10ef9..9ccb5700c 100644 --- a/ports/esp32s2/common-hal/alarm/pin/PinAlarm.c +++ b/ports/esp32s2/common-hal/alarm/pin/PinAlarm.c @@ -72,11 +72,11 @@ gpio_isr_handle_t gpio_interrupt_handle; static volatile uint32_t pin_31_0_status = 0; static volatile uint32_t pin_63_32_status = 0; void gpio_interrupt(void *arg) { - (void) arg; + (void)arg; - gpio_ll_get_intr_status(&GPIO, xPortGetCoreID(), (uint32_t*) &pin_31_0_status); + gpio_ll_get_intr_status(&GPIO, xPortGetCoreID(), (uint32_t *)&pin_31_0_status); gpio_ll_clear_intr_status(&GPIO, pin_31_0_status); - gpio_ll_get_intr_status_high(&GPIO, xPortGetCoreID(), (uint32_t*) &pin_63_32_status); + gpio_ll_get_intr_status_high(&GPIO, xPortGetCoreID(), (uint32_t *)&pin_63_32_status); gpio_ll_clear_intr_status_high(&GPIO, pin_63_32_status); // disable the interrupts that fired, maybe all of them @@ -102,12 +102,12 @@ bool alarm_pin_pinalarm_woke_us_up(void) { mp_obj_t alarm_pin_pinalarm_get_wakeup_alarm(size_t n_alarms, const mp_obj_t *alarms) { // First, check to see if we match any given alarms. - uint64_t pin_status = ((uint64_t) pin_63_32_status) << 32 | pin_31_0_status; + uint64_t pin_status = ((uint64_t)pin_63_32_status) << 32 | pin_31_0_status; for (size_t i = 0; i < n_alarms; i++) { if (!MP_OBJ_IS_TYPE(alarms[i], &alarm_pin_pinalarm_type)) { continue; } - alarm_pin_pinalarm_obj_t *alarm = MP_OBJ_TO_PTR(alarms[i]); + alarm_pin_pinalarm_obj_t *alarm = MP_OBJ_TO_PTR(alarms[i]); if ((pin_status & (1ull << alarm->pin->number)) != 0) { return alarms[i]; } @@ -136,8 +136,8 @@ mp_obj_t alarm_pin_pinalarm_get_wakeup_alarm(size_t n_alarms, const mp_obj_t *al alarm->pin = NULL; // Map the pin number back to a pin object. for (size_t i = 0; i < mcu_pin_globals.map.used; i++) { - const mcu_pin_obj_t* pin_obj = MP_OBJ_TO_PTR(mcu_pin_globals.map.table[i].value); - if ((size_t) pin_obj->number == pin_number) { + const mcu_pin_obj_t *pin_obj = MP_OBJ_TO_PTR(mcu_pin_globals.map.table[i].value); + if ((size_t)pin_obj->number == pin_number) { alarm->pin = mcu_pin_globals.map.table[i].value; break; } @@ -182,7 +182,7 @@ void alarm_pin_pinalarm_set_alarms(bool deep_sleep, size_t n_alarms, const mp_ob if (!MP_OBJ_IS_TYPE(alarms[i], &alarm_pin_pinalarm_type)) { continue; } - alarm_pin_pinalarm_obj_t *alarm = MP_OBJ_TO_PTR(alarms[i]); + alarm_pin_pinalarm_obj_t *alarm = MP_OBJ_TO_PTR(alarms[i]); gpio_num_t pin_number = alarm->pin->number; if (alarm->value) { diff --git a/ports/esp32s2/common-hal/alarm/pin/__init__.c b/ports/esp32s2/common-hal/alarm/pin/__init__.c index b39693c6a..ca8cfac7f 100644 --- a/ports/esp32s2/common-hal/alarm/pin/__init__.c +++ b/ports/esp32s2/common-hal/alarm/pin/__init__.c @@ -3,20 +3,20 @@ #include "esp_sleep.h" #include "driver/rtc_io.h" -mp_obj_t common_hal_alarm_io_pin_state (alarm_io_obj_t *self_in) { +mp_obj_t common_hal_alarm_io_pin_state(alarm_io_obj_t *self_in) { if (!rtc_gpio_is_valid_gpio(self_in->gpio)) { mp_raise_ValueError(translate("io must be rtc io")); } if (self_in->pull && !self_in->level) { - for (uint8_t i = 0; i<=4; i+=2) { + for (uint8_t i = 0; i <= 4; i += 2) { if (self_in->gpio == i) { mp_raise_ValueError(translate("IOs 0, 2 & 4 do not support internal pullup in sleep")); } } } - switch(esp_sleep_enable_ext0_wakeup(self_in->gpio, self_in->level)) { + switch (esp_sleep_enable_ext0_wakeup(self_in->gpio, self_in->level)) { case ESP_ERR_INVALID_ARG: mp_raise_ValueError(translate("trigger level must be 0 or 1")); case ESP_ERR_INVALID_STATE: @@ -25,11 +25,13 @@ mp_obj_t common_hal_alarm_io_pin_state (alarm_io_obj_t *self_in) { break; } - if (self_in->pull) { (self_in->level) ? rtc_gpio_pulldown_en(self_in->gpio) : rtc_gpio_pullup_en(self_in->gpio); } + if (self_in->pull) { + (self_in->level) ? rtc_gpio_pulldown_en(self_in->gpio) : rtc_gpio_pullup_en(self_in->gpio); + } return self_in; } -void common_hal_alarm_io_disable (void) { +void common_hal_alarm_io_disable(void) { esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0 | ESP_SLEEP_WAKEUP_EXT1); } diff --git a/ports/esp32s2/common-hal/alarm/time/TimeAlarm.c b/ports/esp32s2/common-hal/alarm/time/TimeAlarm.c index bcde0ab3c..93e4f1809 100644 --- a/ports/esp32s2/common-hal/alarm/time/TimeAlarm.c +++ b/ports/esp32s2/common-hal/alarm/time/TimeAlarm.c @@ -61,7 +61,7 @@ STATIC bool woke_up = false; // This is run in the timer task. We use it to wake the main CircuitPython task. void timer_callback(void *arg) { - (void) arg; + (void)arg; woke_up = true; xTaskNotifyGive(circuitpython_task); } @@ -88,7 +88,7 @@ void alarm_time_timealarm_set_alarms(bool deep_sleep, size_t n_alarms, const mp_ if (timealarm_set) { mp_raise_ValueError(translate("Only one alarm.time alarm can be set.")); } - timealarm = MP_OBJ_TO_PTR(alarms[i]); + timealarm = MP_OBJ_TO_PTR(alarms[i]); timealarm_set = true; } if (!timealarm_set) { @@ -110,7 +110,7 @@ void alarm_time_timealarm_set_alarms(bool deep_sleep, size_t n_alarms, const mp_ // Compute how long to actually sleep, considering the time now. mp_float_t now_secs = uint64_to_float(common_hal_time_monotonic_ms()) / 1000.0f; mp_float_t wakeup_in_secs = MAX(0.0f, timealarm->monotonic_time - now_secs); - const uint64_t sleep_for_us = (uint64_t) (wakeup_in_secs * 1000000); + const uint64_t sleep_for_us = (uint64_t)(wakeup_in_secs * 1000000); esp_sleep_enable_timer_wakeup(sleep_for_us); // Also set the RTC interrupt so it can wake our task. This will be wiped out diff --git a/ports/esp32s2/common-hal/alarm/touch/TouchAlarm.c b/ports/esp32s2/common-hal/alarm/touch/TouchAlarm.c index 3095bc9e8..8c139afaf 100644 --- a/ports/esp32s2/common-hal/alarm/touch/TouchAlarm.c +++ b/ports/esp32s2/common-hal/alarm/touch/TouchAlarm.c @@ -62,7 +62,7 @@ mp_obj_t alarm_touch_touchalarm_get_wakeup_alarm(const size_t n_alarms, const mp // Map the pin number back to a pin object. for (size_t i = 0; i < mcu_pin_globals.map.used; i++) { - const mcu_pin_obj_t* pin_obj = MP_OBJ_TO_PTR(mcu_pin_globals.map.table[i].value); + const mcu_pin_obj_t *pin_obj = MP_OBJ_TO_PTR(mcu_pin_globals.map.table[i].value); if (pin_obj->touch_channel == wake_channel) { alarm->pin = mcu_pin_globals.map.table[i].value; break; @@ -74,7 +74,7 @@ mp_obj_t alarm_touch_touchalarm_get_wakeup_alarm(const size_t n_alarms, const mp // This is used to wake the main CircuitPython task. void touch_interrupt(void *arg) { - (void) arg; + (void)arg; woke_up = true; BaseType_t task_wakeup; vTaskNotifyGiveFromISR(circuitpython_task, &task_wakeup); @@ -121,7 +121,7 @@ void alarm_touch_touchalarm_set_alarm(const bool deep_sleep, const size_t n_alar // configure trigger threshold uint32_t touch_value; touch_pad_read_benchmark(touch_channel, &touch_value); - touch_pad_set_thresh(touch_channel, touch_value * 0.1); //10% + touch_pad_set_thresh(touch_channel, touch_value * 0.1); // 10% } } @@ -161,7 +161,7 @@ void alarm_touch_touchalarm_prepare_for_deep_sleep(void) { // configure trigger threshold uint32_t touch_value; touch_pad_sleep_channel_read_smooth(touch_channel, &touch_value); - touch_pad_sleep_set_threshold(touch_channel, touch_value * 0.1); //10% + touch_pad_sleep_set_threshold(touch_channel, touch_value * 0.1); // 10% // enable touchpad wakeup esp_sleep_enable_touchpad_wakeup(); diff --git a/ports/esp32s2/common-hal/analogio/AnalogIn.c b/ports/esp32s2/common-hal/analogio/AnalogIn.c index b2c09fc07..add4c3e14 100644 --- a/ports/esp32s2/common-hal/analogio/AnalogIn.c +++ b/ports/esp32s2/common-hal/analogio/AnalogIn.c @@ -41,8 +41,8 @@ #define ATTENUATION ADC_ATTEN_DB_11 #define DATA_WIDTH ADC_WIDTH_BIT_13 -void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self, + const mcu_pin_obj_t *pin) { if (pin->adc_index == 0 || pin->adc_channel == ADC_CHANNEL_MAX) { mp_raise_ValueError(translate("Pin does not have ADC capabilities")); } @@ -78,14 +78,14 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { esp_adc_cal_characterize(self->pin->adc_index, ATTENUATION, DATA_WIDTH, DEFAULT_VREF, &adc_chars); uint32_t adc_reading = 0; - //Multisampling + // Multisampling for (int i = 0; i < NO_OF_SAMPLES; i++) { if (self->pin->adc_index == ADC_UNIT_1) { adc_reading += adc1_get_raw((adc1_channel_t)self->pin->adc_channel); } else { int raw; esp_err_t r = adc2_get_raw((adc2_channel_t)self->pin->adc_channel, DATA_WIDTH, &raw); - if ( r != ESP_OK ) { + if (r != ESP_OK) { mp_raise_ValueError(translate("ADC2 is being used by WiFi")); } adc_reading += raw; @@ -95,7 +95,7 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { // This corrects non-linear regions of the ADC range with a LUT, so it's a better reading than raw uint32_t voltage = esp_adc_cal_raw_to_voltage(adc_reading, &adc_chars); - return voltage * ((1 << 16) - 1)/3300; + return voltage * ((1 << 16) - 1) / 3300; } float common_hal_analogio_analogin_get_reference_voltage(analogio_analogin_obj_t *self) { diff --git a/ports/esp32s2/common-hal/analogio/AnalogIn.h b/ports/esp32s2/common-hal/analogio/AnalogIn.h index b9c4866f2..8c1f8a2ff 100644 --- a/ports/esp32s2/common-hal/analogio/AnalogIn.h +++ b/ports/esp32s2/common-hal/analogio/AnalogIn.h @@ -36,7 +36,7 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t * pin; + const mcu_pin_obj_t *pin; } analogio_analogin_obj_t; #endif // MICROPY_INCLUDED_ESP32S2_COMMON_HAL_ANALOGIO_ANALOGIN_H diff --git a/ports/esp32s2/common-hal/analogio/AnalogOut.c b/ports/esp32s2/common-hal/analogio/AnalogOut.c index 080a01b04..589c477a7 100644 --- a/ports/esp32s2/common-hal/analogio/AnalogOut.c +++ b/ports/esp32s2/common-hal/analogio/AnalogOut.c @@ -39,8 +39,8 @@ #include "common-hal/microcontroller/Pin.h" -void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self, + const mcu_pin_obj_t *pin) { if (pin == &pin_GPIO17) { self->channel = DAC_CHANNEL_1; } else if (pin == &pin_GPIO18) { @@ -52,7 +52,7 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, } bool common_hal_analogio_analogout_deinited(analogio_analogout_obj_t *self) { - return (self->channel == DAC_CHANNEL_MAX); + return self->channel == DAC_CHANNEL_MAX; } void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) { @@ -61,7 +61,7 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) { } void common_hal_analogio_analogout_set_value(analogio_analogout_obj_t *self, - uint16_t value) { + uint16_t value) { uint8_t dac_value = (value * 255) / 65535; dac_output_enable(self->channel); dac_output_voltage(self->channel, dac_value); diff --git a/ports/esp32s2/common-hal/analogio/AnalogOut.h b/ports/esp32s2/common-hal/analogio/AnalogOut.h index 6285151ba..6dc823ce5 100644 --- a/ports/esp32s2/common-hal/analogio/AnalogOut.h +++ b/ports/esp32s2/common-hal/analogio/AnalogOut.h @@ -34,7 +34,7 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t * pin; + const mcu_pin_obj_t *pin; uint8_t channel; } analogio_analogout_obj_t; diff --git a/ports/esp32s2/common-hal/audiobusio/I2SOut.c b/ports/esp32s2/common-hal/audiobusio/I2SOut.c index eb9b6f8e1..6548f4607 100644 --- a/ports/esp32s2/common-hal/audiobusio/I2SOut.c +++ b/ports/esp32s2/common-hal/audiobusio/I2SOut.c @@ -47,9 +47,9 @@ #include "driver/i2s.h" // Caller validates that pins are free. -void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, - const mcu_pin_obj_t* bit_clock, const mcu_pin_obj_t* word_select, - const mcu_pin_obj_t* data, bool left_justified) { +void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t *self, + const mcu_pin_obj_t *bit_clock, const mcu_pin_obj_t *word_select, + const mcu_pin_obj_t *data, bool left_justified) { port_i2s_allocate_init(&self->peripheral, left_justified); @@ -68,11 +68,11 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, claim_pin(data); } -bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t *self) { return self->peripheral.instance == -1; } -void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t *self) { if (common_hal_audiobusio_i2sout_deinited(self)) { return; } @@ -98,31 +98,31 @@ void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { self->peripheral.instance = -1; } -void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, - mp_obj_t sample, bool loop) { +void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t *self, + mp_obj_t sample, bool loop) { if (common_hal_audiobusio_i2sout_get_playing(self)) { common_hal_audiobusio_i2sout_stop(self); } port_i2s_play(&self->peripheral, sample, loop); } -void common_hal_audiobusio_i2sout_pause(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_pause(audiobusio_i2sout_obj_t *self) { port_i2s_pause(&self->peripheral); } -void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t *self) { port_i2s_resume(&self->peripheral); } -bool common_hal_audiobusio_i2sout_get_paused(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_get_paused(audiobusio_i2sout_obj_t *self) { return port_i2s_paused(&self->peripheral); } -void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t *self) { port_i2s_stop(&self->peripheral); } -bool common_hal_audiobusio_i2sout_get_playing(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_get_playing(audiobusio_i2sout_obj_t *self) { return port_i2s_playing(&self->peripheral); } diff --git a/ports/esp32s2/common-hal/audiobusio/__init__.c b/ports/esp32s2/common-hal/audiobusio/__init__.c index 01c77c531..60d00aaa6 100644 --- a/ports/esp32s2/common-hal/audiobusio/__init__.c +++ b/ports/esp32s2/common-hal/audiobusio/__init__.c @@ -42,10 +42,14 @@ static QueueHandle_t i2s_queues[I2S_NUM_MAX]; static TaskHandle_t i2s_tasks[I2S_NUM_MAX]; static int8_t port_i2s_allocate(void) { -#if defined(I2S_NUM_1) - if(!i2s_instance[1]) return 1; -#endif - if(!i2s_instance[0]) return 0; + #if defined(I2S_NUM_1) + if (!i2s_instance[1]) { + return 1; + } + #endif + if (!i2s_instance[0]) { + return 0; + } mp_raise_RuntimeError(translate("Peripheral in use")); } @@ -62,7 +66,7 @@ void port_i2s_reset_instance(int i) { } void i2s_reset(void) { - for (int i=0; i < I2S_NUM_MAX; i++) { + for (int i = 0; i < I2S_NUM_MAX; i++) { port_i2s_reset_instance(i); } } @@ -88,7 +92,7 @@ static void i2s_fill_buffer(i2s_t *self) { uint32_t sample_buffer_length; audioio_get_buffer_result_t get_buffer_result = audiosample_get_buffer(self->sample, false, 0, - &self->sample_data, &sample_buffer_length); + &self->sample_data, &sample_buffer_length); self->sample_end = self->sample_data + sample_buffer_length; if (get_buffer_result == GET_BUFFER_DONE) { if (self->loop) { @@ -118,27 +122,27 @@ static void i2s_fill_buffer(i2s_t *self) { if (self->samples_signed) { assert(self->channel_count == 1); if (self->bytes_per_sample == 1) { - audiosample_convert_s8m_s16s(signed_samples, (int8_t*)(void*)self->sample_data, framecount); + audiosample_convert_s8m_s16s(signed_samples, (int8_t *)(void *)self->sample_data, framecount); } else { - audiosample_convert_s16m_s16s(signed_samples, (int16_t*)(void*)self->sample_data, framecount); + audiosample_convert_s16m_s16s(signed_samples, (int16_t *)(void *)self->sample_data, framecount); } } else { if (self->channel_count == 1) { if (self->bytes_per_sample == 1) { - audiosample_convert_u8m_s16s(signed_samples, (uint8_t*)(void*)self->sample_data, framecount); + audiosample_convert_u8m_s16s(signed_samples, (uint8_t *)(void *)self->sample_data, framecount); } else { - audiosample_convert_u16m_s16s(signed_samples, (uint16_t*)(void*)self->sample_data, framecount); + audiosample_convert_u16m_s16s(signed_samples, (uint16_t *)(void *)self->sample_data, framecount); } } else { if (self->bytes_per_sample == 1) { - audiosample_convert_u8s_s16s(signed_samples, (uint8_t*)(void*)self->sample_data, framecount); + audiosample_convert_u8s_s16s(signed_samples, (uint8_t *)(void *)self->sample_data, framecount); } else { - audiosample_convert_u16s_s16s(signed_samples, (uint16_t*)(void*)self->sample_data, framecount); + audiosample_convert_u16s_s16s(signed_samples, (uint16_t *)(void *)self->sample_data, framecount); } } } size_t expanded_bytes_written = 0; - CHECK_ESP_RESULT(i2s_write(self->instance, signed_samples, bytes_per_output_frame*framecount, &expanded_bytes_written, 0)); + CHECK_ESP_RESULT(i2s_write(self->instance, signed_samples, bytes_per_output_frame * framecount, &expanded_bytes_written, 0)); assert(expanded_bytes_written % 4 == 0); bytes_written = expanded_bytes_written / bytes_per_output_frame * bytes_per_input_frame; } @@ -157,7 +161,7 @@ static void i2s_callback_fun(void *self_in) { static void i2s_event_task(void *self_in) { i2s_t *self = self_in; - while(true) { + while (true) { i2s_event_type_t event; BaseType_t result = xQueueReceive(i2s_queues[self->instance], &event, portMAX_DELAY); if (result && event == I2S_EVENT_TX_DONE) { @@ -199,7 +203,7 @@ void port_i2s_play(i2s_t *self, mp_obj_t sample, bool loop) { uint32_t max_buffer_length; uint8_t spacing; audiosample_get_buffer_structure(sample, false, &single_buffer, &samples_signed, - &max_buffer_length, &spacing); + &max_buffer_length, &spacing); self->samples_signed = samples_signed; self->playing = true; self->paused = false; diff --git a/ports/esp32s2/common-hal/busio/I2C.c b/ports/esp32s2/common-hal/busio/I2C.c index a1d0b8f9c..d97ccd9f1 100644 --- a/ports/esp32s2/common-hal/busio/I2C.c +++ b/ports/esp32s2/common-hal/busio/I2C.c @@ -55,7 +55,7 @@ void i2c_reset(void) { } void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, - const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda, uint32_t frequency, uint32_t timeout) { + const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) { // Pins 45 and 46 are "strapping" pins that impact start up behavior. They usually need to // be pulled-down so pulling them up for I2C is a bad idea. To make this hard, we don't // support I2C on these pins. @@ -65,7 +65,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, mp_raise_ValueError(translate("Invalid pins")); } -#if CIRCUITPY_REQUIRE_I2C_PULLUPS + #if CIRCUITPY_REQUIRE_I2C_PULLUPS // Test that the pins are in a high state. (Hopefully indicating they are pulled up.) gpio_set_direction(sda->number, GPIO_MODE_DEF_INPUT); gpio_set_direction(scl->number, GPIO_MODE_DEF_INPUT); @@ -86,7 +86,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, reset_pin_number(scl->number); mp_raise_RuntimeError(translate("No pull up found on SDA or SCL; check your wiring")); } -#endif + #endif if (xSemaphoreCreateMutexStatic(&self->semaphore) != &self->semaphore) { @@ -124,10 +124,10 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, } if (i2c_driver_install(self->i2c_num, - I2C_MODE_MASTER, - 0, - 0, - 0) != ESP_OK) { + I2C_MODE_MASTER, + 0, + 0, + 0) != ESP_OK) { mp_raise_OSError(MP_EIO); } @@ -182,11 +182,11 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) { } uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, - const uint8_t *data, size_t len, bool transmit_stop_bit) { + const uint8_t *data, size_t len, bool transmit_stop_bit) { i2c_cmd_handle_t cmd = i2c_cmd_link_create(); i2c_master_start(cmd); i2c_master_write_byte(cmd, addr << 1, true); - i2c_master_write(cmd, (uint8_t*) data, len, true); + i2c_master_write(cmd, (uint8_t *)data, len, true); if (transmit_stop_bit) { i2c_master_stop(cmd); } @@ -202,7 +202,7 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, } uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, - uint8_t *data, size_t len) { + uint8_t *data, size_t len) { i2c_cmd_handle_t cmd = i2c_cmd_link_create(); i2c_master_start(cmd); i2c_master_write_byte(cmd, addr << 1 | 1, true); // | 1 to indicate read diff --git a/ports/esp32s2/common-hal/busio/I2C.h b/ports/esp32s2/common-hal/busio/I2C.h index 1a989e30a..9629e7b18 100644 --- a/ports/esp32s2/common-hal/busio/I2C.h +++ b/ports/esp32s2/common-hal/busio/I2C.h @@ -36,8 +36,8 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t* scl_pin; - const mcu_pin_obj_t* sda_pin; + const mcu_pin_obj_t *scl_pin; + const mcu_pin_obj_t *sda_pin; i2c_port_t i2c_num; StaticSemaphore_t semaphore; bool has_lock; diff --git a/ports/esp32s2/common-hal/busio/SPI.c b/ports/esp32s2/common-hal/busio/SPI.c index c4d54ec81..917b39111 100644 --- a/ports/esp32s2/common-hal/busio/SPI.c +++ b/ports/esp32s2/common-hal/busio/SPI.c @@ -73,18 +73,27 @@ void spi_reset(void) { // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -static bool bus_uses_iomux_pins(spi_host_device_t host, const spi_bus_config_t* bus_config) -{ - if (bus_config->sclk_io_num>=0 && - bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) return false; - if (bus_config->quadwp_io_num>=0 && - bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) return false; - if (bus_config->quadhd_io_num>=0 && - bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) return false; +static bool bus_uses_iomux_pins(spi_host_device_t host, const spi_bus_config_t *bus_config) { + if (bus_config->sclk_io_num >= 0 && + bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) { + return false; + } + if (bus_config->quadwp_io_num >= 0 && + bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) { + return false; + } + if (bus_config->quadhd_io_num >= 0 && + bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) { + return false; + } if (bus_config->mosi_io_num >= 0 && - bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) return false; - if (bus_config->miso_io_num>=0 && - bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) return false; + bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) { + return false; + } + if (bus_config->miso_io_num >= 0 && + bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) { + return false; + } return true; } @@ -100,20 +109,18 @@ static void spi_interrupt_handler(void *arg) { } // The interrupt may get invoked by the bus lock. -static void spi_bus_intr_enable(void *self) -{ +static void spi_bus_intr_enable(void *self) { esp_intr_enable(((busio_spi_obj_t *)self)->interrupt); } // The interrupt is always disabled by the ISR itself, not exposed -static void spi_bus_intr_disable(void *self) -{ +static void spi_bus_intr_disable(void *self) { esp_intr_disable(((busio_spi_obj_t *)self)->interrupt); } void common_hal_busio_spi_construct(busio_spi_obj_t *self, - const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi, - const mcu_pin_obj_t * miso) { + const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, + const mcu_pin_obj_t *miso) { spi_bus_config_t bus_config; bus_config.mosi_io_num = mosi != NULL ? mosi->number : -1; @@ -123,8 +130,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, bus_config.quadhd_io_num = -1; bus_config.max_transfer_sz = 0; // Uses the default bus_config.flags = SPICOMMON_BUSFLAG_MASTER | SPICOMMON_BUSFLAG_SCLK | - (mosi != NULL ? SPICOMMON_BUSFLAG_MOSI : 0) | - (miso != NULL ? SPICOMMON_BUSFLAG_MISO : 0); + (mosi != NULL ? SPICOMMON_BUSFLAG_MOSI : 0) | + (miso != NULL ? SPICOMMON_BUSFLAG_MISO : 0); bus_config.intr_flags = 0; // RAM and Flash is often on SPI1 and is unsupported by the IDF so use it as @@ -161,8 +168,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, // The returned lock is stored in the bus lock but must be freed separately with // spi_bus_lock_unregister_dev. result = spi_bus_lock_register_dev(spi_bus_get_attr(host_id)->lock, - &config, - &self->lock); + &config, + &self->lock); if (result == ESP_ERR_NO_MEM) { common_hal_busio_spi_deinit(self); mp_raise_msg(&mp_type_MemoryError, translate("ESP-IDF memory allocation failed")); @@ -170,8 +177,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, lock_dev_handle[host_id] = self->lock; result = esp_intr_alloc(spicommon_irqsource_for_host(host_id), - bus_config.intr_flags | ESP_INTR_FLAG_INTRDISABLED, - spi_interrupt_handler, self, &self->interrupt); + bus_config.intr_flags | ESP_INTR_FLAG_INTRDISABLED, + spi_interrupt_handler, self, &self->interrupt); if (result == ESP_ERR_NO_MEM) { common_hal_busio_spi_deinit(self); mp_raise_msg(&mp_type_MemoryError, translate("ESP-IDF memory allocation failed")); @@ -179,7 +186,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, intr_handle[host_id] = self->interrupt; spi_bus_lock_set_bg_control(spi_bus_get_attr(host_id)->lock, spi_bus_intr_enable, spi_bus_intr_disable, self); - spi_hal_context_t* hal = &self->hal_context; + spi_hal_context_t *hal = &self->hal_context; // spi_hal_init clears the given hal context so set everything after. spi_hal_init(hal, host_id); @@ -256,7 +263,7 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { } bool common_hal_busio_spi_configure(busio_spi_obj_t *self, - uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { + uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { if (baudrate == self->target_frequency && polarity == self->polarity && phase == self->phase && @@ -269,13 +276,13 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self, self->bits = bits; self->target_frequency = baudrate; self->hal_context.timing_conf = &self->timing_conf; - esp_err_t result = spi_hal_get_clock_conf(&self->hal_context, - self->target_frequency, - 128 /* duty_cycle */, - self->connected_through_gpio, - 0 /* input_delay_ns */, - &self->real_frequency, - &self->timing_conf); + esp_err_t result = spi_hal_get_clock_conf(&self->hal_context, + self->target_frequency, + 128 /* duty_cycle */, + self->connected_through_gpio, + 0 /* input_delay_ns */, + &self->real_frequency, + &self->timing_conf); if (result != ESP_OK) { return false; } @@ -306,7 +313,7 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) { } bool common_hal_busio_spi_write(busio_spi_obj_t *self, - const uint8_t *data, size_t len) { + const uint8_t *data, size_t len) { if (self->MOSI_pin == NULL) { mp_raise_ValueError(translate("No MOSI Pin")); } @@ -314,7 +321,7 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, } bool common_hal_busio_spi_read(busio_spi_obj_t *self, - uint8_t *data, size_t len, uint8_t write_value) { + uint8_t *data, size_t len, uint8_t write_value) { if (self->MISO_pin == NULL) { mp_raise_ValueError(translate("No MISO Pin")); @@ -339,7 +346,7 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou mp_raise_ValueError(translate("No MISO Pin")); } - spi_hal_context_t* hal = &self->hal_context; + spi_hal_context_t *hal = &self->hal_context; hal->send_buffer = NULL; hal->rcv_buffer = NULL; // Reset timing_conf in case we've moved since the last time we used it. @@ -377,7 +384,7 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou hal->tx_bitlen = this_length * self->bits; hal->rx_bitlen = this_length * self->bits; if (data_out != NULL) { - hal->send_buffer = (uint8_t*) data_out + offset; + hal->send_buffer = (uint8_t *)data_out + offset; } if (data_in != NULL) { hal->rcv_buffer = data_in + offset; @@ -399,14 +406,14 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou return true; } -uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) { +uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) { return self->real_frequency; } -uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) { return self->phase; } -uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) { return self->polarity; } diff --git a/ports/esp32s2/common-hal/busio/SPI.h b/ports/esp32s2/common-hal/busio/SPI.h index d6203feae..488c0954e 100644 --- a/ports/esp32s2/common-hal/busio/SPI.h +++ b/ports/esp32s2/common-hal/busio/SPI.h @@ -36,9 +36,9 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t* clock_pin; - const mcu_pin_obj_t* MOSI_pin; - const mcu_pin_obj_t* MISO_pin; + const mcu_pin_obj_t *clock_pin; + const mcu_pin_obj_t *MOSI_pin; + const mcu_pin_obj_t *MISO_pin; spi_host_device_t host_id; spi_bus_lock_dev_handle_t lock; spi_hal_context_t hal_context; diff --git a/ports/esp32s2/common-hal/busio/UART.c b/ports/esp32s2/common-hal/busio/UART.c index 98cebba67..7da5c0f94 100644 --- a/ports/esp32s2/common-hal/busio/UART.c +++ b/ports/esp32s2/common-hal/busio/UART.c @@ -53,11 +53,11 @@ void uart_reset(void) { } void common_hal_busio_uart_construct(busio_uart_obj_t *self, - const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx, - const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts, - const mcu_pin_obj_t * rs485_dir, bool rs485_invert, + const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx, + const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts, + const mcu_pin_obj_t *rs485_dir, bool rs485_invert, uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, - mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer, + mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer, bool sigint_enabled) { if (bits > 8) { @@ -163,7 +163,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, uart_set_parity(self->uart_num, parity_mode); // Stop is 1 or 2 always. - uart_stop_bits_t stop_bits= UART_STOP_BITS_1; + uart_stop_bits_t stop_bits = UART_STOP_BITS_1; if (stop == 2) { stop_bits = UART_STOP_BITS_2; } @@ -292,7 +292,7 @@ size_t common_hal_busio_uart_write(busio_uart_obj_t *self, const uint8_t *data, } while (len > 0) { - int count = uart_tx_chars(self->uart_num, (const char*) data, len); + int count = uart_tx_chars(self->uart_num, (const char *)data, len); if (count < 0) { *errcode = MP_EAGAIN; return MP_STREAM_ERROR; @@ -322,7 +322,7 @@ void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrat } mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) { - return (mp_float_t) (self->timeout_ms / 1000.0f); + return (mp_float_t)(self->timeout_ms / 1000.0f); } void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) { diff --git a/ports/esp32s2/common-hal/busio/UART.h b/ports/esp32s2/common-hal/busio/UART.h index 751fb2e00..0d19221c8 100644 --- a/ports/esp32s2/common-hal/busio/UART.h +++ b/ports/esp32s2/common-hal/busio/UART.h @@ -34,10 +34,10 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t* rx_pin; - const mcu_pin_obj_t* tx_pin; - const mcu_pin_obj_t* rts_pin; - const mcu_pin_obj_t* cts_pin; + const mcu_pin_obj_t *rx_pin; + const mcu_pin_obj_t *tx_pin; + const mcu_pin_obj_t *rts_pin; + const mcu_pin_obj_t *cts_pin; uart_port_t uart_num; uint8_t character_bits; bool rx_error; diff --git a/ports/esp32s2/common-hal/canio/CAN.c b/ports/esp32s2/common-hal/canio/CAN.c index 768fde243..720034755 100644 --- a/ports/esp32s2/common-hal/canio/CAN.c +++ b/ports/esp32s2/common-hal/canio/CAN.c @@ -39,89 +39,74 @@ STATIC bool reserved_can; twai_timing_config_t get_t_config(int baudrate) { - switch(baudrate) { - case 1000000: - { - // TWAI_TIMING_CONFIG_abc expands to a C designated initializer list - // { .brp = 4, ...}. This is only acceptable to the compiler as an - // initializer and 'return TWAI_TIMING_CONFIG_1MBITS()` is not valid. - // Instead, introduce a temporary, named variable and return it. - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_1MBITS(); - return t_config; - } - case 800000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_800KBITS(); - return t_config; - } - case 500000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_500KBITS(); - return t_config; - } - case 250000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_250KBITS(); - return t_config; - } - case 125000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_125KBITS(); - return t_config; - } - case 100000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_100KBITS(); - return t_config; - } - case 50000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_50KBITS(); - return t_config; - } - case 25000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_25KBITS(); - return t_config; - } - case 20000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_20KBITS(); - return t_config; - } - case 16000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_16KBITS(); - return t_config; - } - case 12500: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_12_5KBITS(); - return t_config; - } - case 10000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_10KBITS(); - return t_config; - } - case 5000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_5KBITS(); - return t_config; - } - case 1000: - { - twai_timing_config_t t_config = TWAI_TIMING_CONFIG_1KBITS(); - return t_config; - } - default: - mp_raise_ValueError(translate("Baudrate not supported by peripheral")); + switch (baudrate) { + case 1000000: { + // TWAI_TIMING_CONFIG_abc expands to a C designated initializer list + // { .brp = 4, ...}. This is only acceptable to the compiler as an + // initializer and 'return TWAI_TIMING_CONFIG_1MBITS()` is not valid. + // Instead, introduce a temporary, named variable and return it. + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_1MBITS(); + return t_config; + } + case 800000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_800KBITS(); + return t_config; + } + case 500000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_500KBITS(); + return t_config; + } + case 250000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_250KBITS(); + return t_config; + } + case 125000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_125KBITS(); + return t_config; + } + case 100000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_100KBITS(); + return t_config; + } + case 50000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_50KBITS(); + return t_config; + } + case 25000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_25KBITS(); + return t_config; + } + case 20000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_20KBITS(); + return t_config; + } + case 16000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_16KBITS(); + return t_config; + } + case 12500: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_12_5KBITS(); + return t_config; + } + case 10000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_10KBITS(); + return t_config; + } + case 5000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_5KBITS(); + return t_config; + } + case 1000: { + twai_timing_config_t t_config = TWAI_TIMING_CONFIG_1KBITS(); + return t_config; + } + default: + mp_raise_ValueError(translate("Baudrate not supported by peripheral")); } } -void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent) -{ -#define DIV_ROUND(a, b) (((a) + (b)/2) / (b)) +void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent) { +#define DIV_ROUND(a, b) (((a) + (b) / 2) / (b)) #define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b)) if (reserved_can) { mp_raise_ValueError(translate("All CAN peripherals are in use")); @@ -170,25 +155,21 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc reserved_can = true; } -bool common_hal_canio_can_loopback_get(canio_can_obj_t *self) -{ +bool common_hal_canio_can_loopback_get(canio_can_obj_t *self) { return self->loopback; } -int common_hal_canio_can_baudrate_get(canio_can_obj_t *self) -{ +int common_hal_canio_can_baudrate_get(canio_can_obj_t *self) { return self->baudrate; } -int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self) -{ +int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self) { twai_status_info_t info; twai_get_status_info(&info); return info.tx_error_counter; } -int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self) -{ +int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self) { twai_status_info_t info; twai_get_status_info(&info); return info.rx_error_counter; @@ -224,7 +205,9 @@ static void can_restart(void) { } void canio_maybe_auto_restart(canio_can_obj_t *self) { - if (self->auto_restart) can_restart(); + if (self->auto_restart) { + can_restart(); + } } void common_hal_canio_can_restart(canio_can_obj_t *self) { @@ -242,8 +225,7 @@ void common_hal_canio_can_auto_restart_set(canio_can_obj_t *self, bool value) { canio_maybe_auto_restart(self); } -void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in) -{ +void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in) { canio_maybe_auto_restart(self); canio_message_obj_t *message = message_in; bool rtr = message->base.type == &canio_remote_transmission_request_type; @@ -275,8 +257,7 @@ void common_hal_canio_can_check_for_deinit(canio_can_obj_t *self) { } } -void common_hal_canio_can_deinit(canio_can_obj_t *self) -{ +void common_hal_canio_can_deinit(canio_can_obj_t *self) { if (self->tx_pin) { (void)twai_stop(); (void)twai_driver_uninstall(); diff --git a/ports/esp32s2/common-hal/canio/CAN.h b/ports/esp32s2/common-hal/canio/CAN.h index 85fb6972b..82f30bc6f 100644 --- a/ports/esp32s2/common-hal/canio/CAN.h +++ b/ports/esp32s2/common-hal/canio/CAN.h @@ -42,8 +42,8 @@ typedef struct canio_can_obj { int baudrate; const mcu_pin_obj_t *rx_pin; const mcu_pin_obj_t *tx_pin; - bool loopback:1; - bool silent:1; - bool auto_restart:1; - bool fifo_in_use:1; + bool loopback : 1; + bool silent : 1; + bool auto_restart : 1; + bool fifo_in_use : 1; } canio_can_obj_t; diff --git a/ports/esp32s2/common-hal/canio/Listener.c b/ports/esp32s2/common-hal/canio/Listener.c index fddbfeb58..5e968f239 100644 --- a/ports/esp32s2/common-hal/canio/Listener.c +++ b/ports/esp32s2/common-hal/canio/Listener.c @@ -41,16 +41,15 @@ // IDE = "extended ID" flag of packet header. We always add this bit to the // mask because a match is always for just one kind of address length -#define FILTER16_IDE (1<<3) -#define FILTER32_IDE (1<<2) +#define FILTER16_IDE (1 << 3) +#define FILTER32_IDE (1 << 2) // Work around a problem reported at // https://github.com/espressif/esp-idf/issues/6020 where // twai_ll_set_acc_filter does not work under -Os optimization __attribute__((optimize("O0"))) __attribute__((noinline)) -static void canio_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter) -{ +static void canio_set_acc_filter(twai_dev_t *hw, uint32_t code, uint32_t mask, bool single_filter) { uint32_t code_swapped = __builtin_bswap32(code); uint32_t mask_swapped = __builtin_bswap32(mask); for (int i = 0; i < 4; i++) { diff --git a/ports/esp32s2/common-hal/canio/Listener.h b/ports/esp32s2/common-hal/canio/Listener.h index d24900e43..cc8545e37 100644 --- a/ports/esp32s2/common-hal/canio/Listener.h +++ b/ports/esp32s2/common-hal/canio/Listener.h @@ -32,9 +32,9 @@ typedef struct canio_listener_obj { mp_obj_base_t base; canio_can_obj_t *can; - bool extended:1; - bool standard:1; - bool pending:1; + bool extended : 1; + bool standard : 1; + bool pending : 1; twai_message_t message_in; uint32_t timeout_ms; } canio_listener_obj_t; diff --git a/ports/esp32s2/common-hal/countio/Counter.c b/ports/esp32s2/common-hal/countio/Counter.c index fe52d93ad..bdc8b290f 100644 --- a/ports/esp32s2/common-hal/countio/Counter.c +++ b/ports/esp32s2/common-hal/countio/Counter.c @@ -30,8 +30,8 @@ #include "py/runtime.h" #include "supervisor/shared/translate.h" -void common_hal_countio_counter_construct(countio_counter_obj_t* self, - const mcu_pin_obj_t* pin) { +void common_hal_countio_counter_construct(countio_counter_obj_t *self, + const mcu_pin_obj_t *pin) { claim_pin(pin); // Prepare configuration for the PCNT unit @@ -55,11 +55,11 @@ void common_hal_countio_counter_construct(countio_counter_obj_t* self, self->unit = (pcnt_unit_t)unit; } -bool common_hal_countio_counter_deinited(countio_counter_obj_t* self) { +bool common_hal_countio_counter_deinited(countio_counter_obj_t *self) { return self->unit == PCNT_UNIT_MAX; } -void common_hal_countio_counter_deinit(countio_counter_obj_t* self) { +void common_hal_countio_counter_deinit(countio_counter_obj_t *self) { if (common_hal_countio_counter_deinited(self)) { return; } @@ -67,18 +67,18 @@ void common_hal_countio_counter_deinit(countio_counter_obj_t* self) { peripherals_pcnt_deinit(&self->unit); } -mp_int_t common_hal_countio_counter_get_count(countio_counter_obj_t* self) { +mp_int_t common_hal_countio_counter_get_count(countio_counter_obj_t *self) { int16_t count; pcnt_get_counter_value(self->unit, &count); - return count+self->count; + return count + self->count; } -void common_hal_countio_counter_set_count(countio_counter_obj_t* self, - mp_int_t new_count) { +void common_hal_countio_counter_set_count(countio_counter_obj_t *self, + mp_int_t new_count) { self->count = new_count; pcnt_counter_clear(self->unit); } -void common_hal_countio_counter_reset(countio_counter_obj_t* self) { - common_hal_countio_counter_set_count(self, 0); +void common_hal_countio_counter_reset(countio_counter_obj_t *self) { + common_hal_countio_counter_set_count(self, 0); } diff --git a/ports/esp32s2/common-hal/countio/__init__.c b/ports/esp32s2/common-hal/countio/__init__.c index b95b20d15..d47de33e5 100644 --- a/ports/esp32s2/common-hal/countio/__init__.c +++ b/ports/esp32s2/common-hal/countio/__init__.c @@ -1 +1 @@ -//No countio module functions +// No countio module functions diff --git a/ports/esp32s2/common-hal/digitalio/DigitalInOut.c b/ports/esp32s2/common-hal/digitalio/DigitalInOut.c index a2a0209f9..f2c40ce9b 100644 --- a/ports/esp32s2/common-hal/digitalio/DigitalInOut.c +++ b/ports/esp32s2/common-hal/digitalio/DigitalInOut.c @@ -33,12 +33,12 @@ #include "components/soc/include/hal/gpio_hal.h" void common_hal_digitalio_digitalinout_never_reset( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { never_reset_pin_number(self->pin->number); } digitalinout_result_t common_hal_digitalio_digitalinout_construct( - digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { + digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { claim_pin(pin); self->pin = pin; @@ -69,20 +69,20 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self } void common_hal_digitalio_digitalinout_switch_to_input( - digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { common_hal_digitalio_digitalinout_set_pull(self, pull); gpio_set_direction(self->pin->number, GPIO_MODE_DEF_INPUT); } digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( - digitalio_digitalinout_obj_t *self, bool value, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, bool value, + digitalio_drive_mode_t drive_mode) { common_hal_digitalio_digitalinout_set_value(self, value); return common_hal_digitalio_digitalinout_set_drive_mode(self, drive_mode); } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { uint32_t iomux = READ_PERI_REG(GPIO_PIN_MUX_REG[self->pin->number]); if ((iomux & FUN_IE) != 0) { return DIRECTION_INPUT; @@ -91,13 +91,13 @@ digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( } void common_hal_digitalio_digitalinout_set_value( - digitalio_digitalinout_obj_t *self, bool value) { + digitalio_digitalinout_obj_t *self, bool value) { self->output_value = value; gpio_set_level(self->pin->number, value); } bool common_hal_digitalio_digitalinout_get_value( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { if (common_hal_digitalio_digitalinout_get_direction(self) == DIRECTION_INPUT) { return gpio_get_level(self->pin->number) == 1; } @@ -105,8 +105,8 @@ bool common_hal_digitalio_digitalinout_get_value( } digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( - digitalio_digitalinout_obj_t *self, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, + digitalio_drive_mode_t drive_mode) { gpio_num_t number = self->pin->number; gpio_mode_t mode; if (drive_mode == DRIVE_MODE_OPEN_DRAIN) { @@ -122,7 +122,7 @@ digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { if (GPIO_HAL_GET_HW(GPIO_PORT_0)->pin[self->pin->number].pad_driver == 1) { return DRIVE_MODE_OPEN_DRAIN; } @@ -130,7 +130,7 @@ digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( } void common_hal_digitalio_digitalinout_set_pull( - digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { gpio_num_t number = self->pin->number; gpio_pullup_dis(number); gpio_pulldown_dis(number); @@ -142,7 +142,7 @@ void common_hal_digitalio_digitalinout_set_pull( } digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { gpio_num_t gpio_num = self->pin->number; if (REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU) == 1) { return PULL_UP; diff --git a/ports/esp32s2/common-hal/displayio/ParallelBus.c b/ports/esp32s2/common-hal/displayio/ParallelBus.c index f77b37b57..5fd2be852 100644 --- a/ports/esp32s2/common-hal/displayio/ParallelBus.c +++ b/ports/esp32s2/common-hal/displayio/ParallelBus.c @@ -38,9 +38,9 @@ * - data0 pin must be byte aligned */ -void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* self, - const mcu_pin_obj_t* data0, const mcu_pin_obj_t* command, const mcu_pin_obj_t* chip_select, - const mcu_pin_obj_t* write, const mcu_pin_obj_t* read, const mcu_pin_obj_t* reset) { +void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t *self, + const mcu_pin_obj_t *data0, const mcu_pin_obj_t *command, const mcu_pin_obj_t *chip_select, + const mcu_pin_obj_t *write, const mcu_pin_obj_t *read, const mcu_pin_obj_t *reset) { uint8_t data_pin = data0->number; if (data_pin % 8 != 0) { @@ -59,8 +59,8 @@ void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* sel // Enable pins with "enable_w1ts" for (uint8_t i = 0; i < 8; i++) { - g->enable_w1ts = (0x1 << (data_pin + i)); - g->func_out_sel_cfg[data_pin + i].val= 256; /* setup output pin for simple GPIO Output, (0x100 = 256) */ + g->enable_w1ts = (0x1 << (data_pin + i)); + g->func_out_sel_cfg[data_pin + i].val = 256; /* setup output pin for simple GPIO Output, (0x100 = 256) */ } @@ -70,10 +70,10 @@ void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* sel if (data_pin < 31) { - self->bus = (uint32_t*) &g->out; //pointer to GPIO output register (for pins 0-31) - } else { - self->bus = (uint32_t*) &g->out1.val; //pointer to GPIO output register (for pins >= 32) - } + self->bus = (uint32_t *)&g->out; // pointer to GPIO output register (for pins 0-31) + } else { + self->bus = (uint32_t *)&g->out1.val; // pointer to GPIO output register (for pins >= 32) + } /* SNIP - common setup of command, chip select, write and read pins, same as from SAMD and NRF ports */ self->command.base.type = &digitalio_digitalinout_type; @@ -95,20 +95,20 @@ void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* sel self->data0_pin = data_pin; if (write->number < 32) { - self->write_clear_register = (uint32_t*) &g->out_w1tc; - self->write_set_register = (uint32_t*) &g->out_w1ts; + self->write_clear_register = (uint32_t *)&g->out_w1tc; + self->write_set_register = (uint32_t *)&g->out_w1ts; } else { - self->write_clear_register = (uint32_t*) &g->out1_w1tc.val; - self->write_set_register = (uint32_t*) &g->out1_w1ts.val; + self->write_clear_register = (uint32_t *)&g->out1_w1tc.val; + self->write_set_register = (uint32_t *)&g->out1_w1ts.val; } // Check to see if the data and write pins are on the same register: - if ( ( ((self->data0_pin < 32) && (write->number < 32)) ) || - ( ((self->data0_pin > 31) && (write->number > 31)) ) ) { - self->data_write_same_register = true; // data pins and write pin are on the same register + if ((((self->data0_pin < 32) && (write->number < 32))) || + (((self->data0_pin > 31) && (write->number > 31)))) { + self->data_write_same_register = true; // data pins and write pin are on the same register } else { - self->data_write_same_register = false; // data pins and write pins are on different registers - } + self->data_write_same_register = false; // data pins and write pins are on different registers + } self->write_mask = 1 << (write->number % 32); /* the write pin triggers the LCD to latch the data */ @@ -133,8 +133,8 @@ void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* sel } -void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) { - /* SNIP - same as from SAMD and NRF ports */ +void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t *self) { + /* SNIP - same as from SAMD and NRF ports */ for (uint8_t i = 0; i < 8; i++) { reset_pin_number(self->data0_pin + i); } @@ -147,8 +147,8 @@ void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) } bool common_hal_displayio_parallelbus_reset(mp_obj_t obj) { - /* SNIP - same as from SAMD and NRF ports */ - displayio_parallelbus_obj_t* self = MP_OBJ_TO_PTR(obj); + /* SNIP - same as from SAMD and NRF ports */ + displayio_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj); if (self->reset.base.type == &mp_type_NoneType) { return false; } @@ -161,24 +161,24 @@ bool common_hal_displayio_parallelbus_reset(mp_obj_t obj) { } bool common_hal_displayio_parallelbus_bus_free(mp_obj_t obj) { - /* SNIP - same as from SAMD and NRF ports */ + /* SNIP - same as from SAMD and NRF ports */ return true; } bool common_hal_displayio_parallelbus_begin_transaction(mp_obj_t obj) { - /* SNIP - same as from SAMD and NRF ports */ - displayio_parallelbus_obj_t* self = MP_OBJ_TO_PTR(obj); + /* SNIP - same as from SAMD and NRF ports */ + displayio_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj); common_hal_digitalio_digitalinout_set_value(&self->chip_select, false); return true; } void common_hal_displayio_parallelbus_send(mp_obj_t obj, display_byte_type_t byte_type, - display_chip_select_behavior_t chip_select, const uint8_t *data, uint32_t data_length) { - displayio_parallelbus_obj_t* self = MP_OBJ_TO_PTR(obj); + display_chip_select_behavior_t chip_select, const uint8_t *data, uint32_t data_length) { + displayio_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj); common_hal_digitalio_digitalinout_set_value(&self->command, byte_type == DISPLAY_DATA); - uint32_t* clear_write = self->write_clear_register; - uint32_t* set_write = self->write_set_register; + uint32_t *clear_write = self->write_clear_register; + uint32_t *set_write = self->write_set_register; const uint32_t mask = self->write_mask; @@ -188,41 +188,40 @@ void common_hal_displayio_parallelbus_send(mp_obj_t obj, display_byte_type_t byt */ *clear_write = mask; // Clear the write pin to prepare the registers before storing the - // register value into data_buffer + // register value into data_buffer const uint32_t data_buffer = *self->bus; // store the initial output register values into the data output buffer - uint8_t* data_address = ((uint8_t*) &data_buffer) + (self->data0_pin / 8); /* address inside data_buffer where - * each data byte will be written to the data pin registers - */ - - - if ( self->data_write_same_register ) { // data and write pins are on the same register - for (uint32_t i = 0; i < data_length; i++) { - - /* Note: If the write pin and data pins are controlled by the same GPIO register, we can eliminate - * the "clear_write" step below, since the write pin is cleared when the data_buffer is written - * to the bus. - */ - - *(data_address) = data[i]; // stuff the data byte into the data_buffer at the correct offset byte location - *self->bus = data_buffer; // write the data to the output register - *set_write = mask; // set the write pin - } - } - else { // data and write pins are on different registers - for (uint32_t i = 0; i < data_length; i++) { - *clear_write = mask; // clear the write pin (See comment above, this may not be necessary). - *(data_address) = data[i]; // stuff the data byte into the data_buffer at the correct offset byte location - *self->bus = data_buffer; // write the data to the output register - *set_write = mask; // set the write pin - - } - } + uint8_t *data_address = ((uint8_t *)&data_buffer) + (self->data0_pin / 8); /* address inside data_buffer where + * each data byte will be written to the data pin registers + */ + + + if (self->data_write_same_register) { // data and write pins are on the same register + for (uint32_t i = 0; i < data_length; i++) { + + /* Note: If the write pin and data pins are controlled by the same GPIO register, we can eliminate + * the "clear_write" step below, since the write pin is cleared when the data_buffer is written + * to the bus. + */ + + *(data_address) = data[i]; // stuff the data byte into the data_buffer at the correct offset byte location + *self->bus = data_buffer; // write the data to the output register + *set_write = mask; // set the write pin + } + } else { // data and write pins are on different registers + for (uint32_t i = 0; i < data_length; i++) { + *clear_write = mask; // clear the write pin (See comment above, this may not be necessary). + *(data_address) = data[i]; // stuff the data byte into the data_buffer at the correct offset byte location + *self->bus = data_buffer; // write the data to the output register + *set_write = mask; // set the write pin + + } + } } void common_hal_displayio_parallelbus_end_transaction(mp_obj_t obj) { - /* SNIP - same as from SAMD and NRF ports */ - displayio_parallelbus_obj_t* self = MP_OBJ_TO_PTR(obj); + /* SNIP - same as from SAMD and NRF ports */ + displayio_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj); common_hal_digitalio_digitalinout_set_value(&self->chip_select, true); } diff --git a/ports/esp32s2/common-hal/displayio/ParallelBus.h b/ports/esp32s2/common-hal/displayio/ParallelBus.h index 84302118b..59eb64f34 100644 --- a/ports/esp32s2/common-hal/displayio/ParallelBus.h +++ b/ports/esp32s2/common-hal/displayio/ParallelBus.h @@ -31,7 +31,7 @@ typedef struct { mp_obj_base_t base; - uint32_t* bus; // pointer where 8 bits of data are written to the display + uint32_t *bus; // pointer where 8 bits of data are written to the display digitalio_digitalinout_obj_t command; digitalio_digitalinout_obj_t chip_select; digitalio_digitalinout_obj_t reset; @@ -39,8 +39,8 @@ typedef struct { digitalio_digitalinout_obj_t read; uint8_t data0_pin; // pin number for the lowest number data pin. Must be 8-bit aligned bool data_write_same_register; // if data and write pins are in the sare - uint32_t* write_set_register; // pointer to the write group for setting the write bit to latch the data on the LCD - uint32_t* write_clear_register; // pointer to the write group for clearing the write bit to latch the data on the LCD + uint32_t *write_set_register; // pointer to the write group for setting the write bit to latch the data on the LCD + uint32_t *write_clear_register; // pointer to the write group for clearing the write bit to latch the data on the LCD uint32_t write_mask; // bit mask for the single bit for the write pin register } displayio_parallelbus_obj_t; diff --git a/ports/esp32s2/common-hal/dualbank/__init__.c b/ports/esp32s2/common-hal/dualbank/__init__.c index 1414f131d..04f5d6203 100644 --- a/ports/esp32s2/common-hal/dualbank/__init__.c +++ b/ports/esp32s2/common-hal/dualbank/__init__.c @@ -62,10 +62,10 @@ void common_hal_dualbank_flash(const void *buf, const size_t len, const size_t o update_partition = esp_ota_get_next_update_partition(NULL); ESP_LOGI(TAG, "Running partition type %d subtype %d (offset 0x%08x)", - running->type, running->subtype, running->address); + running->type, running->subtype, running->address); ESP_LOGI(TAG, "Writing partition type %d subtype %d (offset 0x%08x)\n", - update_partition->type, update_partition->subtype, update_partition->address); + update_partition->type, update_partition->subtype, update_partition->address); assert(update_partition != NULL); } diff --git a/ports/esp32s2/common-hal/dualbank/__init__.h b/ports/esp32s2/common-hal/dualbank/__init__.h index 8b18336c9..eb325b9fb 100644 --- a/ports/esp32s2/common-hal/dualbank/__init__.h +++ b/ports/esp32s2/common-hal/dualbank/__init__.h @@ -29,4 +29,4 @@ extern void dualbank_reset(void); -#endif //MICROPY_INCLUDED_ESP32S2_COMMON_HAL_DUALBANK___INIT___H +#endif // MICROPY_INCLUDED_ESP32S2_COMMON_HAL_DUALBANK___INIT___H diff --git a/ports/esp32s2/common-hal/frequencyio/FrequencyIn.c b/ports/esp32s2/common-hal/frequencyio/FrequencyIn.c index 12d612abb..cd13cddc6 100644 --- a/ports/esp32s2/common-hal/frequencyio/FrequencyIn.c +++ b/ports/esp32s2/common-hal/frequencyio/FrequencyIn.c @@ -29,7 +29,7 @@ #include "py/runtime.h" static void IRAM_ATTR pcnt_overflow_handler(void *self_in) { - frequencyio_frequencyin_obj_t * self = self_in; + frequencyio_frequencyin_obj_t *self = self_in; // reset counter pcnt_counter_clear(self->unit); @@ -41,7 +41,7 @@ static void IRAM_ATTR pcnt_overflow_handler(void *self_in) { } static void IRAM_ATTR timer_interrupt_handler(void *self_in) { - frequencyio_frequencyin_obj_t * self = self_in; + frequencyio_frequencyin_obj_t *self = self_in; // get counter value int16_t count; pcnt_get_counter_value(self->unit, &count); @@ -63,7 +63,7 @@ static void IRAM_ATTR timer_interrupt_handler(void *self_in) { device->hw_timer[self->timer.idx].config.alarm_en = 1; } -static void init_pcnt(frequencyio_frequencyin_obj_t* self) { +static void init_pcnt(frequencyio_frequencyin_obj_t *self) { // Prepare configuration for the PCNT unit const pcnt_config_t pcnt_config = { // Set PCNT input signal and control GPIOs @@ -95,7 +95,7 @@ static void init_pcnt(frequencyio_frequencyin_obj_t* self) { pcnt_intr_enable(self->unit); } -static void init_timer(frequencyio_frequencyin_obj_t* self) { +static void init_timer(frequencyio_frequencyin_obj_t *self) { // Prepare configuration for the timer module const timer_config_t config = { .alarm_en = true, @@ -124,8 +124,8 @@ static void init_timer(frequencyio_frequencyin_obj_t* self) { timer_start(self->timer.group, self->timer.idx); } -void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t* self, - const mcu_pin_obj_t* pin, const uint16_t capture_period) { +void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t *self, + const mcu_pin_obj_t *pin, const uint16_t capture_period) { if ((capture_period == 0) || (capture_period > 500)) { mp_raise_ValueError(translate("Invalid capture period. Valid range: 1 - 500")); } @@ -142,11 +142,11 @@ void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t* claim_pin(pin); } -bool common_hal_frequencyio_frequencyin_deinited(frequencyio_frequencyin_obj_t* self) { +bool common_hal_frequencyio_frequencyin_deinited(frequencyio_frequencyin_obj_t *self) { return self->unit == PCNT_UNIT_MAX; } -void common_hal_frequencyio_frequencyin_deinit(frequencyio_frequencyin_obj_t* self) { +void common_hal_frequencyio_frequencyin_deinit(frequencyio_frequencyin_obj_t *self) { if (common_hal_frequencyio_frequencyin_deinited(self)) { return; } @@ -159,21 +159,21 @@ void common_hal_frequencyio_frequencyin_deinit(frequencyio_frequencyin_obj_t* se } } -uint32_t common_hal_frequencyio_frequencyin_get_item(frequencyio_frequencyin_obj_t* self) { +uint32_t common_hal_frequencyio_frequencyin_get_item(frequencyio_frequencyin_obj_t *self) { return self->frequency; } -void common_hal_frequencyio_frequencyin_pause(frequencyio_frequencyin_obj_t* self) { +void common_hal_frequencyio_frequencyin_pause(frequencyio_frequencyin_obj_t *self) { pcnt_counter_pause(self->unit); timer_pause(self->timer.group, self->timer.idx); } -void common_hal_frequencyio_frequencyin_resume(frequencyio_frequencyin_obj_t* self) { +void common_hal_frequencyio_frequencyin_resume(frequencyio_frequencyin_obj_t *self) { pcnt_counter_resume(self->unit); timer_start(self->timer.group, self->timer.idx); } -void common_hal_frequencyio_frequencyin_clear(frequencyio_frequencyin_obj_t* self) { +void common_hal_frequencyio_frequencyin_clear(frequencyio_frequencyin_obj_t *self) { self->frequency = 0; pcnt_counter_clear(self->unit); timer_set_counter_value(self->timer.group, self->timer.idx, 0); diff --git a/ports/esp32s2/common-hal/microcontroller/Pin.c b/ports/esp32s2/common-hal/microcontroller/Pin.c index ff6d0ed35..5c00ca49e 100644 --- a/ports/esp32s2/common-hal/microcontroller/Pin.c +++ b/ports/esp32s2/common-hal/microcontroller/Pin.c @@ -59,20 +59,20 @@ STATIC void floating_gpio_reset(gpio_num_t pin_number) { } void never_reset_pin_number(gpio_num_t pin_number) { - if (pin_number == -1 ) { - return; + if (pin_number == -1) { + return; } never_reset_pins[pin_number / 32] |= 1 << pin_number % 32; } -void common_hal_never_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_never_reset_pin(const mcu_pin_obj_t *pin) { never_reset_pin_number(pin->number); } // Mark pin as free and return it to a quiescent state. void reset_pin_number(gpio_num_t pin_number) { - if (pin_number == -1 ) { - return; + if (pin_number == -1) { + return; } never_reset_pins[pin_number / 32] &= ~(1 << pin_number % 32); in_use[pin_number / 32] &= ~(1 << pin_number % 32); @@ -88,7 +88,7 @@ void reset_pin_number(gpio_num_t pin_number) { #endif } -void common_hal_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_reset_pin(const mcu_pin_obj_t *pin) { if (pin == NULL) { return; } @@ -112,7 +112,7 @@ void reset_all_pins(void) { #endif } -void claim_pin(const mcu_pin_obj_t* pin) { +void claim_pin(const mcu_pin_obj_t *pin) { in_use[pin->number / 32] |= (1 << (pin->number % 32)); #ifdef MICROPY_HW_NEOPIXEL if (pin == MICROPY_HW_NEOPIXEL) { @@ -121,7 +121,7 @@ void claim_pin(const mcu_pin_obj_t* pin) { #endif } -void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { +void common_hal_mcu_pin_claim(const mcu_pin_obj_t *pin) { claim_pin(pin); } diff --git a/ports/esp32s2/common-hal/microcontroller/Pin.h b/ports/esp32s2/common-hal/microcontroller/Pin.h index f6c008703..e7b488f04 100644 --- a/ports/esp32s2/common-hal/microcontroller/Pin.h +++ b/ports/esp32s2/common-hal/microcontroller/Pin.h @@ -42,8 +42,8 @@ void reset_all_pins(void); // reset_pin_number takes the pin number instead of the pointer so that objects don't // need to store a full pointer. void reset_pin_number(gpio_num_t pin_number); -void common_hal_reset_pin(const mcu_pin_obj_t* pin); -void claim_pin(const mcu_pin_obj_t* pin); +void common_hal_reset_pin(const mcu_pin_obj_t *pin); +void claim_pin(const mcu_pin_obj_t *pin); bool pin_number_is_free(gpio_num_t pin_number); void never_reset_pin_number(gpio_num_t pin_number); diff --git a/ports/esp32s2/common-hal/microcontroller/Processor.c b/ports/esp32s2/common-hal/microcontroller/Processor.c index fffd1a1b1..eb65f2d10 100644 --- a/ports/esp32s2/common-hal/microcontroller/Processor.c +++ b/ports/esp32s2/common-hal/microcontroller/Processor.c @@ -66,17 +66,21 @@ STATIC uint8_t swap_nibbles(uint8_t v) { void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { memset(raw_id, 0, COMMON_HAL_MCU_PROCESSOR_UID_LENGTH); - uint8_t *ptr = &raw_id[COMMON_HAL_MCU_PROCESSOR_UID_LENGTH-1]; + uint8_t *ptr = &raw_id[COMMON_HAL_MCU_PROCESSOR_UID_LENGTH - 1]; // MAC address contains 48 bits (6 bytes), 32 in the low order word uint32_t mac_address_part = REG_READ(EFUSE_RD_MAC_SPI_SYS_0_REG); - *ptr-- = swap_nibbles(mac_address_part & 0xff); mac_address_part >>= 8; - *ptr-- = swap_nibbles(mac_address_part & 0xff); mac_address_part >>= 8; - *ptr-- = swap_nibbles(mac_address_part & 0xff); mac_address_part >>= 8; + *ptr-- = swap_nibbles(mac_address_part & 0xff); + mac_address_part >>= 8; + *ptr-- = swap_nibbles(mac_address_part & 0xff); + mac_address_part >>= 8; + *ptr-- = swap_nibbles(mac_address_part & 0xff); + mac_address_part >>= 8; *ptr-- = swap_nibbles(mac_address_part & 0xff); // and 16 in the high order word mac_address_part = REG_READ(EFUSE_RD_MAC_SPI_SYS_1_REG); - *ptr-- = swap_nibbles(mac_address_part & 0xff); mac_address_part >>= 8; + *ptr-- = swap_nibbles(mac_address_part & 0xff); + mac_address_part >>= 8; *ptr-- = swap_nibbles(mac_address_part & 0xff); } diff --git a/ports/esp32s2/common-hal/microcontroller/__init__.c b/ports/esp32s2/common-hal/microcontroller/__init__.c index e425cbf54..85eb0b522 100644 --- a/ports/esp32s2/common-hal/microcontroller/__init__.c +++ b/ports/esp32s2/common-hal/microcontroller/__init__.c @@ -68,12 +68,13 @@ void common_hal_mcu_enable_interrupts(void) { } void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) { - if(runmode == RUNMODE_SAFE_MODE) + if (runmode == RUNMODE_SAFE_MODE) { safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE); + } } void common_hal_mcu_reset(void) { - filesystem_flush(); //TODO: implement as part of flash improvements + filesystem_flush(); // TODO: implement as part of flash improvements esp_restart(); } @@ -91,7 +92,7 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .base = { .type = &nvm_bytearray_type, }, - .start_address = (uint8_t*) CIRCUITPY_INTERNAL_NVM_START_ADDR, + .start_address = (uint8_t *)CIRCUITPY_INTERNAL_NVM_START_ADDR, .len = CIRCUITPY_INTERNAL_NVM_SIZE, }; #endif diff --git a/ports/esp32s2/common-hal/neopixel_write/__init__.c b/ports/esp32s2/common-hal/neopixel_write/__init__.c index 63d50bf14..89d90ae99 100644 --- a/ports/esp32s2/common-hal/neopixel_write/__init__.c +++ b/ports/esp32s2/common-hal/neopixel_write/__init__.c @@ -58,15 +58,14 @@ static uint32_t ws2812_t0l_ticks = 0; static uint32_t ws2812_t1l_ticks = 0; static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size, - size_t wanted_num, size_t *translated_size, size_t *item_num) -{ + size_t wanted_num, size_t *translated_size, size_t *item_num) { if (src == NULL || dest == NULL) { *translated_size = 0; *item_num = 0; return; } - const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0 - const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1 + const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; // Logical 0 + const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; // Logical 1 size_t size = 0; size_t num = 0; uint8_t *psrc = (uint8_t *)src; @@ -75,9 +74,9 @@ static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, si for (int i = 0; i < 8; i++) { // MSB first if (*psrc & (1 << (7 - i))) { - pdest->val = bit1.val; + pdest->val = bit1.val; } else { - pdest->val = bit0.val; + pdest->val = bit0.val; } num++; pdest++; @@ -89,7 +88,7 @@ static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, si *item_num = num; } -void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, uint32_t numBytes) { +void common_hal_neopixel_write(const digitalio_digitalinout_obj_t *digitalinout, uint8_t *pixels, uint32_t numBytes) { // Reserve channel uint8_t number = digitalinout->pin->number; rmt_channel_t channel = esp32s2_peripherals_find_and_reserve_rmt(); @@ -118,7 +117,7 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout rmt_translator_init(config.channel, ws2812_rmt_adapter); // Write and wait to finish - if(rmt_write_sample(config.channel, pixels, (size_t)numBytes, true) != ESP_OK) { + if (rmt_write_sample(config.channel, pixels, (size_t)numBytes, true) != ESP_OK) { mp_raise_RuntimeError(translate("Input/output error")); } rmt_wait_tx_done(config.channel, pdMS_TO_TICKS(100)); diff --git a/ports/esp32s2/common-hal/nvm/ByteArray.c b/ports/esp32s2/common-hal/nvm/ByteArray.c index 71321e7e6..313087379 100644 --- a/ports/esp32s2/common-hal/nvm/ByteArray.c +++ b/ports/esp32s2/common-hal/nvm/ByteArray.c @@ -33,7 +33,7 @@ uint32_t common_hal_nvm_bytearray_get_length(nvm_bytearray_obj_t *self) { return self->len; } -static void get_nvs_handle(nvs_handle_t * nvs_handle) { +static void get_nvs_handle(nvs_handle_t *nvs_handle) { // Initialize NVS esp_err_t err = nvs_flash_init(); if (err == ESP_ERR_NVS_NO_FREE_PAGES || err == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -51,7 +51,7 @@ static void get_nvs_handle(nvs_handle_t * nvs_handle) { } bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, - uint32_t start_index, uint8_t* values, uint32_t len) { + uint32_t start_index, uint8_t *values, uint32_t len) { char index[9]; // start nvs @@ -77,7 +77,7 @@ bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, } void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t *self, - uint32_t start_index, uint32_t len, uint8_t* values) { + uint32_t start_index, uint32_t len, uint8_t *values) { char index[9]; // start nvs diff --git a/ports/esp32s2/common-hal/nvm/ByteArray.h b/ports/esp32s2/common-hal/nvm/ByteArray.h index 44b63d724..3bd5191fc 100644 --- a/ports/esp32s2/common-hal/nvm/ByteArray.h +++ b/ports/esp32s2/common-hal/nvm/ByteArray.h @@ -31,7 +31,7 @@ typedef struct { mp_obj_base_t base; - uint8_t* start_address; + uint8_t *start_address; uint32_t len; } nvm_bytearray_obj_t; diff --git a/ports/esp32s2/common-hal/os/__init__.c b/ports/esp32s2/common-hal/os/__init__.c index 4d6a6a2bf..ee53bec04 100644 --- a/ports/esp32s2/common-hal/os/__init__.c +++ b/ports/esp32s2/common-hal/os/__init__.c @@ -52,13 +52,13 @@ STATIC MP_DEFINE_ATTRTUPLE( (mp_obj_t)&os_uname_info_release_obj, (mp_obj_t)&os_uname_info_version_obj, (mp_obj_t)&os_uname_info_machine_obj -); + ); mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; } -bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) { +bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { uint32_t i = 0; while (i < length) { uint32_t new_random = esp_random(); diff --git a/ports/esp32s2/common-hal/ps2io/Ps2.c b/ports/esp32s2/common-hal/ps2io/Ps2.c index 003f0d827..f4845b0fa 100644 --- a/ports/esp32s2/common-hal/ps2io/Ps2.c +++ b/ports/esp32s2/common-hal/ps2io/Ps2.c @@ -62,7 +62,7 @@ static void IRAM_ATTR ps2_interrupt_handler(void *self_in) { // Grab the current time first. uint64_t current_tick = port_get_raw_ticks(NULL); - ps2io_ps2_obj_t * self = self_in; + ps2io_ps2_obj_t *self = self_in; int data_bit = gpio_get_level(self->data_pin) ? 1 : 0; // test for timeout @@ -85,7 +85,7 @@ static void IRAM_ATTR ps2_interrupt_handler(void *self_in) { // start bit should be 0 self->last_errors |= ERROR_STARTBIT; self->state = STATE_RECV_ERR; - } else { + } else { self->state = STATE_RECV; } @@ -113,7 +113,7 @@ static void IRAM_ATTR ps2_interrupt_handler(void *self_in) { } else if (self->state == STATE_RECV_STOP) { ++self->bitcount; - if (! data_bit) { + if (!data_bit) { self->last_errors |= ERROR_STOPBIT; } else if (self->waiting_cmd_response) { self->cmd_response = self->bits; @@ -135,31 +135,31 @@ static void IRAM_ATTR ps2_interrupt_handler(void *self_in) { } } -static void enable_interrupt(ps2io_ps2_obj_t* self) { +static void enable_interrupt(ps2io_ps2_obj_t *self) { // turn on falling edge interrupt gpio_install_isr_service(ESP_INTR_FLAG_IRAM); gpio_set_intr_type(self->clk_pin, GPIO_INTR_NEGEDGE); - gpio_isr_handler_add(self->clk_pin, ps2_interrupt_handler, (void*)self); + gpio_isr_handler_add(self->clk_pin, ps2_interrupt_handler, (void *)self); } -static void disable_interrupt(ps2io_ps2_obj_t* self) { +static void disable_interrupt(ps2io_ps2_obj_t *self) { // turn off fallling edge interrupt gpio_isr_handler_remove(self->clk_pin); } -static void resume_interrupt(ps2io_ps2_obj_t* self) { +static void resume_interrupt(ps2io_ps2_obj_t *self) { self->state = STATE_IDLE; - gpio_isr_handler_add(self->clk_pin, ps2_interrupt_handler, (void*)self); + gpio_isr_handler_add(self->clk_pin, ps2_interrupt_handler, (void *)self); } /* gpio handling */ -static void clk_hi(ps2io_ps2_obj_t* self) { +static void clk_hi(ps2io_ps2_obj_t *self) { // external pull-up gpio_set_direction(self->clk_pin, GPIO_MODE_INPUT); } -static bool wait_clk_lo(ps2io_ps2_obj_t* self, uint32_t us) { +static bool wait_clk_lo(ps2io_ps2_obj_t *self, uint32_t us) { clk_hi(self); delay_us(1); while (gpio_get_level(self->clk_pin) && us) { @@ -169,7 +169,7 @@ static bool wait_clk_lo(ps2io_ps2_obj_t* self, uint32_t us) { return us; } -static bool wait_clk_hi(ps2io_ps2_obj_t* self, uint32_t us) { +static bool wait_clk_hi(ps2io_ps2_obj_t *self, uint32_t us) { clk_hi(self); delay_us(1); while (!gpio_get_level(self->clk_pin) && us) { @@ -179,17 +179,17 @@ static bool wait_clk_hi(ps2io_ps2_obj_t* self, uint32_t us) { return us; } -static void clk_lo(ps2io_ps2_obj_t* self) { +static void clk_lo(ps2io_ps2_obj_t *self) { gpio_set_direction(self->clk_pin, GPIO_MODE_OUTPUT); gpio_set_level(self->clk_pin, 0); } -static void data_hi(ps2io_ps2_obj_t* self) { +static void data_hi(ps2io_ps2_obj_t *self) { // external pull-up gpio_set_direction(self->data_pin, GPIO_MODE_INPUT); } -static bool wait_data_lo(ps2io_ps2_obj_t* self, uint32_t us) { +static bool wait_data_lo(ps2io_ps2_obj_t *self, uint32_t us) { data_hi(self); delay_us(1); while (gpio_get_level(self->data_pin) && us) { @@ -199,7 +199,7 @@ static bool wait_data_lo(ps2io_ps2_obj_t* self, uint32_t us) { return us; } -static bool wait_data_hi(ps2io_ps2_obj_t* self, uint32_t us) { +static bool wait_data_hi(ps2io_ps2_obj_t *self, uint32_t us) { data_hi(self); delay_us(1); while (!gpio_get_level(self->data_pin) && us) { @@ -209,25 +209,25 @@ static bool wait_data_hi(ps2io_ps2_obj_t* self, uint32_t us) { return us; } -static void data_lo(ps2io_ps2_obj_t* self) { +static void data_lo(ps2io_ps2_obj_t *self) { gpio_set_direction(self->data_pin, GPIO_MODE_OUTPUT); gpio_set_level(self->data_pin, 0); } -static void idle(ps2io_ps2_obj_t* self) { +static void idle(ps2io_ps2_obj_t *self) { clk_hi(self); data_hi(self); } -static void inhibit(ps2io_ps2_obj_t* self) { +static void inhibit(ps2io_ps2_obj_t *self) { clk_lo(self); data_hi(self); } /* ps2io module functions */ -void common_hal_ps2io_ps2_construct(ps2io_ps2_obj_t* self, - const mcu_pin_obj_t* data_pin, const mcu_pin_obj_t* clk_pin) { +void common_hal_ps2io_ps2_construct(ps2io_ps2_obj_t *self, + const mcu_pin_obj_t *data_pin, const mcu_pin_obj_t *clk_pin) { self->clk_pin = (gpio_num_t)clk_pin->number; self->data_pin = (gpio_num_t)data_pin->number; self->state = STATE_IDLE; @@ -243,11 +243,11 @@ void common_hal_ps2io_ps2_construct(ps2io_ps2_obj_t* self, claim_pin(data_pin); } -bool common_hal_ps2io_ps2_deinited(ps2io_ps2_obj_t* self) { +bool common_hal_ps2io_ps2_deinited(ps2io_ps2_obj_t *self) { return self->clk_pin == GPIO_NUM_MAX; } -void common_hal_ps2io_ps2_deinit(ps2io_ps2_obj_t* self) { +void common_hal_ps2io_ps2_deinit(ps2io_ps2_obj_t *self) { if (common_hal_ps2io_ps2_deinited(self)) { return; } @@ -258,11 +258,11 @@ void common_hal_ps2io_ps2_deinit(ps2io_ps2_obj_t* self) { self->data_pin = GPIO_NUM_MAX; } -uint16_t common_hal_ps2io_ps2_get_len(ps2io_ps2_obj_t* self) { +uint16_t common_hal_ps2io_ps2_get_len(ps2io_ps2_obj_t *self) { return self->bufcount; } -int16_t common_hal_ps2io_ps2_popleft(ps2io_ps2_obj_t* self) { +int16_t common_hal_ps2io_ps2_popleft(ps2io_ps2_obj_t *self) { common_hal_mcu_disable_interrupts(); if (self->bufcount <= 0) { common_hal_mcu_enable_interrupts(); @@ -275,7 +275,7 @@ int16_t common_hal_ps2io_ps2_popleft(ps2io_ps2_obj_t* self) { return b; } -uint16_t common_hal_ps2io_ps2_clear_errors(ps2io_ps2_obj_t* self) { +uint16_t common_hal_ps2io_ps2_clear_errors(ps2io_ps2_obj_t *self) { common_hal_mcu_disable_interrupts(); uint16_t errors = self->last_errors; self->last_errors = 0; @@ -286,7 +286,7 @@ uint16_t common_hal_ps2io_ps2_clear_errors(ps2io_ps2_obj_t* self) { // Based upon TMK implementation of PS/2 protocol // https://github.com/tmk/tmk_keyboard/blob/master/tmk_core/protocol/ps2_interrupt.c -int16_t common_hal_ps2io_ps2_sendcmd(ps2io_ps2_obj_t* self, uint8_t b) { +int16_t common_hal_ps2io_ps2_sendcmd(ps2io_ps2_obj_t *self, uint8_t b) { disable_interrupt(self); /* terminate a transmission if we have */ diff --git a/ports/esp32s2/common-hal/pulseio/PulseIn.c b/ports/esp32s2/common-hal/pulseio/PulseIn.c index 9feeea147..a9533179b 100644 --- a/ports/esp32s2/common-hal/pulseio/PulseIn.c +++ b/ports/esp32s2/common-hal/pulseio/PulseIn.c @@ -29,21 +29,21 @@ #include "py/runtime.h" STATIC uint8_t refcount = 0; -STATIC pulseio_pulsein_obj_t * handles[RMT_CHANNEL_MAX]; +STATIC pulseio_pulsein_obj_t *handles[RMT_CHANNEL_MAX]; // Requires rmt.c void esp32s2_peripherals_reset_all(void) to reset -STATIC void update_internal_buffer(pulseio_pulsein_obj_t* self) { +STATIC void update_internal_buffer(pulseio_pulsein_obj_t *self) { uint32_t length = 0; - rmt_item32_t *items = (rmt_item32_t *) xRingbufferReceive(self->buf_handle, &length, 0); + rmt_item32_t *items = (rmt_item32_t *)xRingbufferReceive(self->buf_handle, &length, 0); if (items) { length /= 4; - for (size_t i=0; i < length; i++) { + for (size_t i = 0; i < length; i++) { uint16_t pos = (self->start + self->len) % self->maxlen; self->buffer[pos] = items[i].duration0 * 3; // Check if second item exists before incrementing if (items[i].duration1) { - self->buffer[pos+1] = items[i].duration1 * 3; + self->buffer[pos + 1] = items[i].duration1 * 3; if (self->len < (self->maxlen - 1)) { self->len += 2; } else { @@ -57,7 +57,7 @@ STATIC void update_internal_buffer(pulseio_pulsein_obj_t* self) { } } } - vRingbufferReturnItem(self->buf_handle, (void *) items); + vRingbufferReturnItem(self->buf_handle, (void *)items); } } @@ -83,9 +83,9 @@ void pulsein_reset(void) { refcount = 0; } -void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu_pin_obj_t* pin, - uint16_t maxlen, bool idle_state) { - self->buffer = (uint16_t *) m_malloc(maxlen * sizeof(uint16_t), false); +void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t *self, const mcu_pin_obj_t *pin, + uint16_t maxlen, bool idle_state) { + self->buffer = (uint16_t *)m_malloc(maxlen * sizeof(uint16_t), false); if (self->buffer == NULL) { mp_raise_msg_varg(&mp_type_MemoryError, translate("Failed to allocate RX buffer of %d bytes"), maxlen * sizeof(uint16_t)); } @@ -115,7 +115,7 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu config.rx_config.idle_threshold = 30000; // 30*3=90ms idle required to register a sequence config.clk_div = 240; // All measurements are divided by 3 to accomodate 65ms pulses rmt_config(&config); - rmt_driver_install(channel, 1000, 0); //TODO: pick a more specific buffer size? + rmt_driver_install(channel, 1000, 0); // TODO: pick a more specific buffer size? // Store this object and the buffer handle for background updates self->channel = channel; @@ -130,11 +130,11 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu } } -bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t *self) { return handles[self->channel] ? false : true; } -void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t *self) { handles[self->channel] = NULL; esp32s2_peripherals_free_rmt(self->channel); reset_pin_number(self->pin->number); @@ -144,14 +144,14 @@ void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { } } -void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t *self) { self->paused = true; rmt_rx_stop(self->channel); } -void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, uint16_t trigger_duration) { +void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t *self, uint16_t trigger_duration) { // Make sure we're paused. - if ( !self->paused ) { + if (!self->paused) { common_hal_pulseio_pulsein_pause(self); } @@ -167,13 +167,13 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, uint16_t tri rmt_rx_start(self->channel, false); } -void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t *self) { // Buffer only updates in BG tasks or fetches, so no extra protection is needed self->start = 0; self->len = 0; } -uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, int16_t index) { +uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t *self, int16_t index) { update_internal_buffer(self); if (index < 0) { index += self->len; @@ -185,7 +185,7 @@ uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, int16_ return value; } -uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t *self) { update_internal_buffer(self); if (self->len == 0) { @@ -199,14 +199,14 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { return value; } -uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t *self) { return self->maxlen; } -bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t *self) { return self->paused; } -uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t *self) { return self->len; } diff --git a/ports/esp32s2/common-hal/pulseio/PulseIn.h b/ports/esp32s2/common-hal/pulseio/PulseIn.h index 289605ed0..3afd8db25 100644 --- a/ports/esp32s2/common-hal/pulseio/PulseIn.h +++ b/ports/esp32s2/common-hal/pulseio/PulseIn.h @@ -36,14 +36,14 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t* pin; + const mcu_pin_obj_t *pin; rmt_channel_t channel; bool idle_state; bool paused; RingbufHandle_t buf_handle; - uint16_t* buffer; + uint16_t *buffer; uint16_t maxlen; volatile uint16_t start; diff --git a/ports/esp32s2/common-hal/pulseio/PulseOut.c b/ports/esp32s2/common-hal/pulseio/PulseOut.c index e45492a89..d3490d181 100644 --- a/ports/esp32s2/common-hal/pulseio/PulseOut.c +++ b/ports/esp32s2/common-hal/pulseio/PulseOut.c @@ -31,11 +31,11 @@ // Requires rmt.c void esp32s2_peripherals_reset_all(void) to reset -void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, - const pwmio_pwmout_obj_t* carrier, - const mcu_pin_obj_t* pin, - uint32_t frequency, - uint16_t duty_cycle) { +void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self, + const pwmio_pwmout_obj_t *carrier, + const mcu_pin_obj_t *pin, + uint32_t frequency, + uint16_t duty_cycle) { if (carrier || !pin || !frequency) { mp_raise_NotImplementedError(translate("Port does not accept PWM carrier. Pass a pin, frequency and duty cycle instead")); } @@ -48,7 +48,7 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, // Configure Channel rmt_config_t config = RMT_DEFAULT_CONFIG_TX(pin->number, channel); config.tx_config.carrier_en = true; - config.tx_config.carrier_duty_percent = (duty_cycle * 100) / (1<<16); + config.tx_config.carrier_duty_percent = (duty_cycle * 100) / (1 << 16); config.tx_config.carrier_freq_hz = frequency; config.clk_div = 80; @@ -58,17 +58,17 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, self->channel = channel; } -bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t* self) { - return (self->channel == RMT_CHANNEL_MAX); +bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t *self) { + return self->channel == RMT_CHANNEL_MAX; } -void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { +void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t *self) { esp32s2_peripherals_free_rmt(self->channel); self->channel = RMT_CHANNEL_MAX; } -void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pulses, uint16_t length) { +void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pulses, uint16_t length) { rmt_item32_t items[length]; // Circuitpython allows 16 bit pulse values, while ESP32 only allows 15 bits diff --git a/ports/esp32s2/common-hal/pwmio/PWMOut.c b/ports/esp32s2/common-hal/pwmio/PWMOut.c index e1fdd4760..81af22606 100644 --- a/ports/esp32s2/common-hal/pwmio/PWMOut.c +++ b/ports/esp32s2/common-hal/pwmio/PWMOut.c @@ -39,7 +39,7 @@ STATIC bool never_reset_tim[LEDC_TIMER_MAX]; STATIC bool never_reset_chan[LEDC_CHANNEL_MAX]; void pwmout_reset(void) { - for (size_t i = 0; i < LEDC_CHANNEL_MAX; i++ ) { + for (size_t i = 0; i < LEDC_CHANNEL_MAX; i++) { if (reserved_channels[i] != INDEX_EMPTY && not_first_reset) { ledc_stop(LEDC_LOW_SPEED_MODE, i, 0); } @@ -47,7 +47,7 @@ void pwmout_reset(void) { reserved_channels[i] = INDEX_EMPTY; } } - for (size_t i = 0; i < LEDC_TIMER_MAX; i++ ) { + for (size_t i = 0; i < LEDC_TIMER_MAX; i++) { if (reserved_timer_freq[i]) { ledc_timer_rst(LEDC_LOW_SPEED_MODE, i); } @@ -58,16 +58,16 @@ void pwmout_reset(void) { not_first_reset = true; } -pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, - const mcu_pin_obj_t* pin, - uint16_t duty, - uint32_t frequency, - bool variable_frequency) { +pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, + const mcu_pin_obj_t *pin, + uint16_t duty, + uint32_t frequency, + bool variable_frequency) { // Calculate duty cycle uint32_t duty_bits = 0; - uint32_t interval = LEDC_APB_CLK_HZ/frequency; + uint32_t interval = LEDC_APB_CLK_HZ / frequency; for (size_t i = 0; i < 32; i++) { - if(!(interval >> i)) { + if (!(interval >> i)) { duty_bits = i - 1; break; } @@ -83,7 +83,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, size_t channel_index = INDEX_EMPTY; for (size_t i = 0; i < LEDC_TIMER_MAX; i++) { if ((reserved_timer_freq[i] == frequency) && !variable_frequency) { - //prioritize matched frequencies so we don't needlessly take slots + // prioritize matched frequencies so we don't needlessly take slots timer_index = i; break; } else if (reserved_timer_freq[i] == 0) { @@ -155,11 +155,11 @@ void common_hal_pwmio_pwmout_reset_ok(pwmio_pwmout_obj_t *self) { never_reset_chan[self->chan_handle.channel] = false; } -bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) { return self->deinited == true; } -void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { +void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) { if (common_hal_pwmio_pwmout_deinited(self)) { return; } @@ -169,7 +169,7 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { } // Search if any other channel is using the timer bool taken = false; - for (size_t i =0; i < LEDC_CHANNEL_MAX; i++) { + for (size_t i = 0; i < LEDC_CHANNEL_MAX; i++) { if (reserved_channels[i] == self->tim_handle.timer_num) { taken = true; } @@ -186,23 +186,23 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { self->deinited = true; } -void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t* self, uint16_t duty) { +void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t duty) { ledc_set_duty(LEDC_LOW_SPEED_MODE, self->chan_handle.channel, duty >> (16 - self->duty_resolution)); ledc_update_duty(LEDC_LOW_SPEED_MODE, self->chan_handle.channel); } -uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) { +uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) { return ledc_get_duty(LEDC_LOW_SPEED_MODE, self->chan_handle.channel) << (16 - self->duty_resolution); } -void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t frequency) { +void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self, uint32_t frequency) { ledc_set_freq(LEDC_LOW_SPEED_MODE, self->tim_handle.timer_num, frequency); } -uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) { +uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) { return ledc_get_freq(LEDC_LOW_SPEED_MODE, self->tim_handle.timer_num); } -bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) { return self->variable_frequency; } diff --git a/ports/esp32s2/common-hal/pwmio/PWMOut.h b/ports/esp32s2/common-hal/pwmio/PWMOut.h index 9055dee8e..9480b8885 100644 --- a/ports/esp32s2/common-hal/pwmio/PWMOut.h +++ b/ports/esp32s2/common-hal/pwmio/PWMOut.h @@ -36,8 +36,8 @@ typedef struct { ledc_channel_config_t chan_handle; uint16_t pin_number; uint8_t duty_resolution; - bool variable_frequency: 1; - bool deinited: 1; + bool variable_frequency : 1; + bool deinited : 1; } pwmio_pwmout_obj_t; void pwmout_reset(void); diff --git a/ports/esp32s2/common-hal/rotaryio/IncrementalEncoder.c b/ports/esp32s2/common-hal/rotaryio/IncrementalEncoder.c index 25529ac72..59fa54880 100644 --- a/ports/esp32s2/common-hal/rotaryio/IncrementalEncoder.c +++ b/ports/esp32s2/common-hal/rotaryio/IncrementalEncoder.c @@ -30,8 +30,8 @@ #include "py/runtime.h" #include "supervisor/shared/translate.h" -void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencoder_obj_t* self, - const mcu_pin_obj_t* pin_a, const mcu_pin_obj_t* pin_b) { +void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencoder_obj_t *self, + const mcu_pin_obj_t *pin_a, const mcu_pin_obj_t *pin_b) { claim_pin(pin_a); claim_pin(pin_b); @@ -49,7 +49,7 @@ void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencode .hctrl_mode = PCNT_MODE_KEEP, // Keep the primary counter mode if high }; - // Initialize PCNT unit + // Initialize PCNT unit const int8_t unit = peripherals_pcnt_init(pcnt_config); if (unit == -1) { mp_raise_RuntimeError(translate("All PCNT units in use")); @@ -60,11 +60,11 @@ void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencode self->unit = (pcnt_unit_t)unit; } -bool common_hal_rotaryio_incrementalencoder_deinited(rotaryio_incrementalencoder_obj_t* self) { +bool common_hal_rotaryio_incrementalencoder_deinited(rotaryio_incrementalencoder_obj_t *self) { return self->unit == PCNT_UNIT_MAX; } -void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_obj_t* self) { +void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_obj_t *self) { if (common_hal_rotaryio_incrementalencoder_deinited(self)) { return; } @@ -73,14 +73,14 @@ void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_o peripherals_pcnt_deinit(&self->unit); } -mp_int_t common_hal_rotaryio_incrementalencoder_get_position(rotaryio_incrementalencoder_obj_t* self) { +mp_int_t common_hal_rotaryio_incrementalencoder_get_position(rotaryio_incrementalencoder_obj_t *self) { int16_t count; pcnt_get_counter_value(self->unit, &count); - return (count/2)+self->position; + return (count / 2) + self->position; } -void common_hal_rotaryio_incrementalencoder_set_position(rotaryio_incrementalencoder_obj_t* self, - mp_int_t new_position) { +void common_hal_rotaryio_incrementalencoder_set_position(rotaryio_incrementalencoder_obj_t *self, + mp_int_t new_position) { self->position = new_position; pcnt_counter_clear(self->unit); } diff --git a/ports/esp32s2/common-hal/socketpool/Socket.c b/ports/esp32s2/common-hal/socketpool/Socket.c index 5f93807bb..385d71b54 100644 --- a/ports/esp32s2/common-hal/socketpool/Socket.c +++ b/ports/esp32s2/common-hal/socketpool/Socket.c @@ -37,7 +37,7 @@ #include "components/lwip/lwip/src/include/lwip/sys.h" #include "components/lwip/lwip/src/include/lwip/netdb.h" -STATIC socketpool_socket_obj_t * open_socket_handles[CONFIG_LWIP_MAX_SOCKETS]; +STATIC socketpool_socket_obj_t *open_socket_handles[CONFIG_LWIP_MAX_SOCKETS]; void socket_reset(void) { for (size_t i = 0; i < MP_ARRAY_SIZE(open_socket_handles); i++) { @@ -52,7 +52,7 @@ void socket_reset(void) { } } -bool register_open_socket(socketpool_socket_obj_t* self) { +bool register_open_socket(socketpool_socket_obj_t *self) { for (size_t i = 0; i < MP_ARRAY_SIZE(open_socket_handles); i++) { if (open_socket_handles[i] == NULL) { open_socket_handles[i] = self; @@ -62,8 +62,8 @@ bool register_open_socket(socketpool_socket_obj_t* self) { return false; } -socketpool_socket_obj_t* common_hal_socketpool_socket_accept(socketpool_socket_obj_t* self, - uint8_t* ip, uint32_t *port) { +socketpool_socket_obj_t *common_hal_socketpool_socket_accept(socketpool_socket_obj_t *self, + uint8_t *ip, uint32_t *port) { struct sockaddr_in accept_addr; socklen_t socklen = sizeof(accept_addr); int newsoc = -1; @@ -87,7 +87,7 @@ socketpool_socket_obj_t* common_hal_socketpool_socket_accept(socketpool_socket_o if (!timed_out) { // harmless on failure but avoiding memcpy is faster - memcpy((void *)ip, (void*)&accept_addr.sin_addr.s_addr, sizeof(accept_addr.sin_addr.s_addr)); + memcpy((void *)ip, (void *)&accept_addr.sin_addr.s_addr, sizeof(accept_addr.sin_addr.s_addr)); *port = accept_addr.sin_port; } else { mp_raise_OSError(ETIMEDOUT); @@ -113,8 +113,8 @@ socketpool_socket_obj_t* common_hal_socketpool_socket_accept(socketpool_socket_o } } -bool common_hal_socketpool_socket_bind(socketpool_socket_obj_t* self, - const char* host, size_t hostlen, uint32_t port) { +bool common_hal_socketpool_socket_bind(socketpool_socket_obj_t *self, + const char *host, size_t hostlen, uint32_t port) { struct sockaddr_in bind_addr; bind_addr.sin_addr.s_addr = inet_addr(host); bind_addr.sin_family = AF_INET; @@ -129,7 +129,7 @@ bool common_hal_socketpool_socket_bind(socketpool_socket_obj_t* self, return result; } -void common_hal_socketpool_socket_close(socketpool_socket_obj_t* self) { +void common_hal_socketpool_socket_close(socketpool_socket_obj_t *self) { self->connected = false; if (self->num >= 0) { lwip_shutdown(self->num, 0); @@ -144,8 +144,8 @@ void common_hal_socketpool_socket_close(socketpool_socket_obj_t* self) { } } -bool common_hal_socketpool_socket_connect(socketpool_socket_obj_t* self, - const char* host, size_t hostlen, uint32_t port) { +bool common_hal_socketpool_socket_connect(socketpool_socket_obj_t *self, + const char *host, size_t hostlen, uint32_t port) { const struct addrinfo hints = { .ai_family = AF_INET, .ai_socktype = SOCK_STREAM, @@ -190,20 +190,20 @@ bool common_hal_socketpool_socket_connect(socketpool_socket_obj_t* self, } } -bool common_hal_socketpool_socket_get_closed(socketpool_socket_obj_t* self) { +bool common_hal_socketpool_socket_get_closed(socketpool_socket_obj_t *self) { return self->num < 0; } -bool common_hal_socketpool_socket_get_connected(socketpool_socket_obj_t* self) { +bool common_hal_socketpool_socket_get_connected(socketpool_socket_obj_t *self) { return self->connected; } -bool common_hal_socketpool_socket_listen(socketpool_socket_obj_t* self, int backlog) { +bool common_hal_socketpool_socket_listen(socketpool_socket_obj_t *self, int backlog) { return lwip_listen(self->num, backlog) == 0; } -mp_uint_t common_hal_socketpool_socket_recvfrom_into(socketpool_socket_obj_t* self, - uint8_t* buf, uint32_t len, uint8_t* ip, uint *port) { +mp_uint_t common_hal_socketpool_socket_recvfrom_into(socketpool_socket_obj_t *self, + uint8_t *buf, uint32_t len, uint8_t *ip, uint *port) { struct sockaddr_in source_addr; socklen_t socklen = sizeof(source_addr); @@ -213,9 +213,9 @@ mp_uint_t common_hal_socketpool_socket_recvfrom_into(socketpool_socket_obj_t* se int received = -1; bool timed_out = false; while (received == -1 && - !timed_out && - !mp_hal_is_interrupted()) { - if (self->timeout_ms != (uint)-1 && self->timeout_ms != 0) { + !timed_out && + !mp_hal_is_interrupted()) { + if (self->timeout_ms != (uint)-1 && self->timeout_ms != 0) { timed_out = supervisor_ticks_ms64() - start_ticks >= self->timeout_ms; } RUN_BACKGROUND_TASKS; @@ -228,7 +228,7 @@ mp_uint_t common_hal_socketpool_socket_recvfrom_into(socketpool_socket_obj_t* se } if (!timed_out) { - memcpy((void *)ip, (void*)&source_addr.sin_addr.s_addr, sizeof(source_addr.sin_addr.s_addr)); + memcpy((void *)ip, (void *)&source_addr.sin_addr.s_addr, sizeof(source_addr.sin_addr.s_addr)); *port = source_addr.sin_port; } else { mp_raise_OSError(ETIMEDOUT); @@ -242,7 +242,7 @@ mp_uint_t common_hal_socketpool_socket_recvfrom_into(socketpool_socket_obj_t* se return received; } -mp_uint_t common_hal_socketpool_socket_recv_into(socketpool_socket_obj_t* self, const uint8_t* buf, uint32_t len) { +mp_uint_t common_hal_socketpool_socket_recv_into(socketpool_socket_obj_t *self, const uint8_t *buf, uint32_t len) { int received = 0; bool timed_out = false; @@ -251,13 +251,13 @@ mp_uint_t common_hal_socketpool_socket_recv_into(socketpool_socket_obj_t* self, uint64_t start_ticks = supervisor_ticks_ms64(); received = -1; while (received == -1 && - !timed_out && - !mp_hal_is_interrupted()) { + !timed_out && + !mp_hal_is_interrupted()) { if (self->timeout_ms != (uint)-1 && self->timeout_ms != 0) { timed_out = supervisor_ticks_ms64() - start_ticks >= self->timeout_ms; } RUN_BACKGROUND_TASKS; - received = lwip_recv(self->num, (void*) buf, len, 0); + received = lwip_recv(self->num, (void *)buf, len, 0); // In non-blocking mode, fail instead of looping if (received == -1 && self->timeout_ms == 0) { @@ -274,7 +274,7 @@ mp_uint_t common_hal_socketpool_socket_recv_into(socketpool_socket_obj_t* self, return received; } -mp_uint_t common_hal_socketpool_socket_send(socketpool_socket_obj_t* self, const uint8_t* buf, uint32_t len) { +mp_uint_t common_hal_socketpool_socket_send(socketpool_socket_obj_t *self, const uint8_t *buf, uint32_t len) { int sent = -1; if (self->num != -1) { // LWIP Socket @@ -290,8 +290,8 @@ mp_uint_t common_hal_socketpool_socket_send(socketpool_socket_obj_t* self, const return sent; } -mp_uint_t common_hal_socketpool_socket_sendto(socketpool_socket_obj_t* self, - const char* host, size_t hostlen, uint32_t port, const uint8_t* buf, uint32_t len) { +mp_uint_t common_hal_socketpool_socket_sendto(socketpool_socket_obj_t *self, + const char *host, size_t hostlen, uint32_t port, const uint8_t *buf, uint32_t len) { // Set parameters const struct addrinfo hints = { @@ -323,6 +323,6 @@ mp_uint_t common_hal_socketpool_socket_sendto(socketpool_socket_obj_t* self, return bytes_sent; } -void common_hal_socketpool_socket_settimeout(socketpool_socket_obj_t* self, uint32_t timeout_ms) { +void common_hal_socketpool_socket_settimeout(socketpool_socket_obj_t *self, uint32_t timeout_ms) { self->timeout_ms = timeout_ms; } diff --git a/ports/esp32s2/common-hal/socketpool/Socket.h b/ports/esp32s2/common-hal/socketpool/Socket.h index b86f5597c..87f8b20db 100644 --- a/ports/esp32s2/common-hal/socketpool/Socket.h +++ b/ports/esp32s2/common-hal/socketpool/Socket.h @@ -41,11 +41,11 @@ typedef struct { int family; int ipproto; bool connected; - socketpool_socketpool_obj_t* pool; + socketpool_socketpool_obj_t *pool; mp_uint_t timeout_ms; } socketpool_socket_obj_t; void socket_reset(void); -bool register_open_socket(socketpool_socket_obj_t* self); +bool register_open_socket(socketpool_socket_obj_t *self); #endif // MICROPY_INCLUDED_ESP32S2_COMMON_HAL_SOCKETPOOL_SOCKET_H diff --git a/ports/esp32s2/common-hal/socketpool/SocketPool.c b/ports/esp32s2/common-hal/socketpool/SocketPool.c index fbd6dca7a..4cea95ec4 100644 --- a/ports/esp32s2/common-hal/socketpool/SocketPool.c +++ b/ports/esp32s2/common-hal/socketpool/SocketPool.c @@ -34,13 +34,13 @@ #include "bindings/espidf/__init__.h" -void common_hal_socketpool_socketpool_construct(socketpool_socketpool_obj_t* self, mp_obj_t radio) { +void common_hal_socketpool_socketpool_construct(socketpool_socketpool_obj_t *self, mp_obj_t radio) { if (radio != MP_OBJ_FROM_PTR(&common_hal_wifi_radio_obj)) { mp_raise_ValueError(translate("SocketPool can only be used with wifi.radio")); } } -socketpool_socket_obj_t* common_hal_socketpool_socket(socketpool_socketpool_obj_t* self, +socketpool_socket_obj_t *common_hal_socketpool_socket(socketpool_socketpool_obj_t *self, socketpool_socketpool_addressfamily_t family, socketpool_socketpool_sock_t type) { int addr_family; @@ -87,8 +87,8 @@ socketpool_socket_obj_t* common_hal_socketpool_socket(socketpool_socketpool_obj_ } -mp_obj_t common_hal_socketpool_socketpool_gethostbyname(socketpool_socketpool_obj_t* self, - const char* host) { +mp_obj_t common_hal_socketpool_socketpool_gethostbyname(socketpool_socketpool_obj_t *self, + const char *host) { const struct addrinfo hints = { .ai_family = AF_INET, diff --git a/ports/esp32s2/common-hal/ssl/SSLContext.c b/ports/esp32s2/common-hal/ssl/SSLContext.c index afc3ecce2..a94c1df1e 100644 --- a/ports/esp32s2/common-hal/ssl/SSLContext.c +++ b/ports/esp32s2/common-hal/ssl/SSLContext.c @@ -31,12 +31,12 @@ #include "py/runtime.h" -void common_hal_ssl_sslcontext_construct(ssl_sslcontext_obj_t* self) { +void common_hal_ssl_sslcontext_construct(ssl_sslcontext_obj_t *self) { } -ssl_sslsocket_obj_t* common_hal_ssl_sslcontext_wrap_socket(ssl_sslcontext_obj_t* self, - socketpool_socket_obj_t* socket, bool server_side, const char* server_hostname) { +ssl_sslsocket_obj_t *common_hal_ssl_sslcontext_wrap_socket(ssl_sslcontext_obj_t *self, + socketpool_socket_obj_t *socket, bool server_side, const char *server_hostname) { if (socket->type != SOCK_STREAM) { mp_raise_RuntimeError(translate("Invalid socket for TLS")); @@ -47,7 +47,7 @@ ssl_sslsocket_obj_t* common_hal_ssl_sslcontext_wrap_socket(ssl_sslcontext_obj_t* sock->ssl_context = self; sock->sock = socket; - esp_tls_t* tls_handle = esp_tls_init(); + esp_tls_t *tls_handle = esp_tls_init(); if (tls_handle == NULL) { mp_raise_espidf_MemoryError(); } diff --git a/ports/esp32s2/common-hal/ssl/SSLSocket.c b/ports/esp32s2/common-hal/ssl/SSLSocket.c index 10c29108c..724d2aac9 100644 --- a/ports/esp32s2/common-hal/ssl/SSLSocket.c +++ b/ports/esp32s2/common-hal/ssl/SSLSocket.c @@ -35,27 +35,27 @@ #include "py/runtime.h" #include "supervisor/shared/tick.h" -ssl_sslsocket_obj_t* common_hal_ssl_sslsocket_accept(ssl_sslsocket_obj_t* self, - uint8_t* ip, uint32_t *port) { - socketpool_socket_obj_t * sock = common_hal_socketpool_socket_accept(self->sock, ip, port); - ssl_sslsocket_obj_t * sslsock = common_hal_ssl_sslcontext_wrap_socket(self->ssl_context, sock, false, NULL); +ssl_sslsocket_obj_t *common_hal_ssl_sslsocket_accept(ssl_sslsocket_obj_t *self, + uint8_t *ip, uint32_t *port) { + socketpool_socket_obj_t *sock = common_hal_socketpool_socket_accept(self->sock, ip, port); + ssl_sslsocket_obj_t *sslsock = common_hal_ssl_sslcontext_wrap_socket(self->ssl_context, sock, false, NULL); return sslsock; } -bool common_hal_ssl_sslsocket_bind(ssl_sslsocket_obj_t* self, - const char* host, size_t hostlen, uint32_t port) { +bool common_hal_ssl_sslsocket_bind(ssl_sslsocket_obj_t *self, + const char *host, size_t hostlen, uint32_t port) { return common_hal_socketpool_socket_bind(self->sock, host, hostlen, port); } -void common_hal_ssl_sslsocket_close(ssl_sslsocket_obj_t* self) { +void common_hal_ssl_sslsocket_close(ssl_sslsocket_obj_t *self) { common_hal_socketpool_socket_close(self->sock); esp_tls_conn_destroy(self->tls); self->tls = NULL; } -bool common_hal_ssl_sslsocket_connect(ssl_sslsocket_obj_t* self, - const char* host, size_t hostlen, uint32_t port) { - esp_tls_cfg_t* tls_config = NULL; +bool common_hal_ssl_sslsocket_connect(ssl_sslsocket_obj_t *self, + const char *host, size_t hostlen, uint32_t port) { + esp_tls_cfg_t *tls_config = NULL; tls_config = &self->ssl_context->ssl_config; int result = esp_tls_conn_new_sync(host, hostlen, port, tls_config, self->tls); self->sock->connected = result >= 0; @@ -88,19 +88,19 @@ bool common_hal_ssl_sslsocket_connect(ssl_sslsocket_obj_t* self, return self->sock->connected; } -bool common_hal_ssl_sslsocket_get_closed(ssl_sslsocket_obj_t* self) { +bool common_hal_ssl_sslsocket_get_closed(ssl_sslsocket_obj_t *self) { return self->tls == NULL && self->sock->num < 0; } -bool common_hal_ssl_sslsocket_get_connected(ssl_sslsocket_obj_t* self) { +bool common_hal_ssl_sslsocket_get_connected(ssl_sslsocket_obj_t *self) { return self->sock->connected; } -bool common_hal_ssl_sslsocket_listen(ssl_sslsocket_obj_t* self, int backlog) { +bool common_hal_ssl_sslsocket_listen(ssl_sslsocket_obj_t *self, int backlog) { return common_hal_socketpool_socket_listen(self->sock, backlog); } -mp_uint_t common_hal_ssl_sslsocket_recv_into(ssl_sslsocket_obj_t* self, const uint8_t* buf, uint32_t len) { +mp_uint_t common_hal_ssl_sslsocket_recv_into(ssl_sslsocket_obj_t *self, const uint8_t *buf, uint32_t len) { int received = 0; bool timed_out = false; int status = 0; @@ -129,7 +129,7 @@ mp_uint_t common_hal_ssl_sslsocket_recv_into(ssl_sslsocket_obj_t* self, const ui available = remaining; } if (available > 0) { - status = esp_tls_conn_read(self->tls, (void*) buf + received, available); + status = esp_tls_conn_read(self->tls, (void *)buf + received, available); if (status == 0) { // Reading zero when something is available indicates a closed // connection. (The available bytes could have been TLS internal.) @@ -140,7 +140,7 @@ mp_uint_t common_hal_ssl_sslsocket_recv_into(ssl_sslsocket_obj_t* self, const ui } } // In non-blocking mode, fail instead of timing out - if (received==0 && self->sock->timeout_ms == 0) { + if (received == 0 && self->sock->timeout_ms == 0) { mp_raise_OSError(MP_EAGAIN); } } @@ -151,7 +151,7 @@ mp_uint_t common_hal_ssl_sslsocket_recv_into(ssl_sslsocket_obj_t* self, const ui return received; } -mp_uint_t common_hal_ssl_sslsocket_send(ssl_sslsocket_obj_t* self, const uint8_t* buf, uint32_t len) { +mp_uint_t common_hal_ssl_sslsocket_send(ssl_sslsocket_obj_t *self, const uint8_t *buf, uint32_t len) { int sent = -1; sent = esp_tls_conn_write(self->tls, buf, len); @@ -171,6 +171,6 @@ mp_uint_t common_hal_ssl_sslsocket_send(ssl_sslsocket_obj_t* self, const uint8_t return sent; } -void common_hal_ssl_sslsocket_settimeout(ssl_sslsocket_obj_t* self, uint32_t timeout_ms) { +void common_hal_ssl_sslsocket_settimeout(ssl_sslsocket_obj_t *self, uint32_t timeout_ms) { self->sock->timeout_ms = timeout_ms; } diff --git a/ports/esp32s2/common-hal/ssl/SSLSocket.h b/ports/esp32s2/common-hal/ssl/SSLSocket.h index e9e5bff06..b48578125 100644 --- a/ports/esp32s2/common-hal/ssl/SSLSocket.h +++ b/ports/esp32s2/common-hal/ssl/SSLSocket.h @@ -36,9 +36,9 @@ typedef struct { mp_obj_base_t base; - socketpool_socket_obj_t * sock; - esp_tls_t* tls; - ssl_sslcontext_obj_t* ssl_context; + socketpool_socket_obj_t *sock; + esp_tls_t *tls; + ssl_sslcontext_obj_t *ssl_context; } ssl_sslsocket_obj_t; #endif // MICROPY_INCLUDED_ESP32S2_COMMON_HAL_SSL_SSLSOCKET_H diff --git a/ports/esp32s2/common-hal/ssl/__init__.c b/ports/esp32s2/common-hal/ssl/__init__.c index 8d386d0c3..a0886adda 100644 --- a/ports/esp32s2/common-hal/ssl/__init__.c +++ b/ports/esp32s2/common-hal/ssl/__init__.c @@ -28,7 +28,7 @@ #include "components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h" -void common_hal_ssl_create_default_context(ssl_sslcontext_obj_t* self) { +void common_hal_ssl_create_default_context(ssl_sslcontext_obj_t *self) { memset(&self->ssl_config, 0, sizeof(esp_tls_cfg_t)); self->ssl_config.crt_bundle_attach = esp_crt_bundle_attach; } diff --git a/ports/esp32s2/common-hal/supervisor/Runtime.c b/ports/esp32s2/common-hal/supervisor/Runtime.c index 974f26cec..f82765178 100644 --- a/ports/esp32s2/common-hal/supervisor/Runtime.c +++ b/ports/esp32s2/common-hal/supervisor/Runtime.c @@ -29,9 +29,9 @@ #include "supervisor/serial.h" bool common_hal_supervisor_runtime_get_serial_connected(void) { - return (bool) serial_connected(); + return (bool)serial_connected(); } bool common_hal_supervisor_runtime_get_serial_bytes_available(void) { - return (bool) serial_bytes_available(); + return (bool)serial_bytes_available(); } diff --git a/ports/esp32s2/common-hal/touchio/TouchIn.c b/ports/esp32s2/common-hal/touchio/TouchIn.c index 401b84d5c..53bc335d3 100644 --- a/ports/esp32s2/common-hal/touchio/TouchIn.c +++ b/ports/esp32s2/common-hal/touchio/TouchIn.c @@ -38,8 +38,8 @@ static uint16_t get_raw_reading(touchio_touchin_obj_t *self) { return touch_value; } -void common_hal_touchio_touchin_construct(touchio_touchin_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_touchio_touchin_construct(touchio_touchin_obj_t *self, + const mcu_pin_obj_t *pin) { if (pin->touch_channel == TOUCH_PAD_MAX) { mp_raise_ValueError(translate("Invalid pin")); } @@ -59,11 +59,11 @@ void common_hal_touchio_touchin_construct(touchio_touchin_obj_t* self, self->threshold = get_raw_reading(self) + 100; } -bool common_hal_touchio_touchin_deinited(touchio_touchin_obj_t* self) { +bool common_hal_touchio_touchin_deinited(touchio_touchin_obj_t *self) { return self->pin == NULL; } -void common_hal_touchio_touchin_deinit(touchio_touchin_obj_t* self) { +void common_hal_touchio_touchin_deinit(touchio_touchin_obj_t *self) { if (common_hal_touchio_touchin_deinited(self)) { return; } diff --git a/ports/esp32s2/common-hal/touchio/TouchIn.h b/ports/esp32s2/common-hal/touchio/TouchIn.h index 2f7c66d2b..d4ce2d8a5 100644 --- a/ports/esp32s2/common-hal/touchio/TouchIn.h +++ b/ports/esp32s2/common-hal/touchio/TouchIn.h @@ -32,7 +32,7 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t * pin; + const mcu_pin_obj_t *pin; uint16_t threshold; } touchio_touchin_obj_t; diff --git a/ports/esp32s2/common-hal/watchdog/WatchDogTimer.c b/ports/esp32s2/common-hal/watchdog/WatchDogTimer.c index 79a84ef59..f17a037ff 100644 --- a/ports/esp32s2/common-hal/watchdog/WatchDogTimer.c +++ b/ports/esp32s2/common-hal/watchdog/WatchDogTimer.c @@ -35,11 +35,11 @@ void esp_task_wdt_isr_user_handler(void) { mp_obj_exception_clear_traceback(MP_OBJ_FROM_PTR(&mp_watchdog_timeout_exception)); MP_STATE_VM(mp_pending_exception) = &mp_watchdog_timeout_exception; -#if MICROPY_ENABLE_SCHEDULER + #if MICROPY_ENABLE_SCHEDULER if (MP_STATE_VM(sched_state) == MP_SCHED_IDLE) { MP_STATE_VM(sched_state) = MP_SCHED_PENDING; } -#endif + #endif } void common_hal_watchdog_feed(watchdog_watchdogtimer_obj_t *self) { @@ -55,7 +55,7 @@ void common_hal_watchdog_deinit(watchdog_watchdogtimer_obj_t *self) { } void watchdog_reset(void) { - common_hal_watchdog_deinit(&common_hal_mcu_watchdogtimer_obj); + common_hal_watchdog_deinit(&common_hal_mcu_watchdogtimer_obj); } static void wdt_config(watchdog_watchdogtimer_obj_t *self) { diff --git a/ports/esp32s2/common-hal/watchdog/WatchDogTimer.h b/ports/esp32s2/common-hal/watchdog/WatchDogTimer.h index 04d9aeee6..c26d14013 100644 --- a/ports/esp32s2/common-hal/watchdog/WatchDogTimer.h +++ b/ports/esp32s2/common-hal/watchdog/WatchDogTimer.h @@ -32,9 +32,9 @@ #include "shared-bindings/watchdog/WatchDogTimer.h" struct _watchdog_watchdogtimer_obj_t { - mp_obj_base_t base; - mp_float_t timeout; - watchdog_watchdogmode_t mode; + mp_obj_base_t base; + mp_float_t timeout; + watchdog_watchdogmode_t mode; }; // This needs to be called in order to disable the watchdog diff --git a/ports/esp32s2/common-hal/wifi/Network.c b/ports/esp32s2/common-hal/wifi/Network.c index b6eb6bb43..49507df0d 100644 --- a/ports/esp32s2/common-hal/wifi/Network.c +++ b/ports/esp32s2/common-hal/wifi/Network.c @@ -31,8 +31,8 @@ #include "py/obj.h" mp_obj_t common_hal_wifi_network_get_ssid(wifi_network_obj_t *self) { - const char* cstr = (const char*) self->record.ssid; - return mp_obj_new_str(cstr, strlen(cstr)); + const char *cstr = (const char *)self->record.ssid; + return mp_obj_new_str(cstr, strlen(cstr)); } #define MAC_ADDRESS_LENGTH 6 @@ -50,13 +50,13 @@ mp_obj_t common_hal_wifi_network_get_channel(wifi_network_obj_t *self) { } mp_obj_t common_hal_wifi_network_get_country(wifi_network_obj_t *self) { - const char* cstr = (const char*) self->record.country.cc; - // 2 instead of strlen(cstr) as this gives us only the country-code - return mp_obj_new_str(cstr, 2); + const char *cstr = (const char *)self->record.country.cc; + // 2 instead of strlen(cstr) as this gives us only the country-code + return mp_obj_new_str(cstr, 2); } mp_obj_t common_hal_wifi_network_get_authmode(wifi_network_obj_t *self) { - const char* authmode = ""; + const char *authmode = ""; switch (self->record.authmode) { case WIFI_AUTH_OPEN: authmode = "OPEN"; @@ -86,5 +86,5 @@ mp_obj_t common_hal_wifi_network_get_authmode(wifi_network_obj_t *self) { authmode = "UNKNOWN"; break; } - return mp_obj_new_str(authmode, strlen(authmode)); + return mp_obj_new_str(authmode, strlen(authmode)); } diff --git a/ports/esp32s2/common-hal/wifi/Radio.c b/ports/esp32s2/common-hal/wifi/Radio.c index 574bab0a1..9c8ccaf7f 100644 --- a/ports/esp32s2/common-hal/wifi/Radio.c +++ b/ports/esp32s2/common-hal/wifi/Radio.c @@ -71,7 +71,7 @@ void common_hal_wifi_radio_set_enabled(wifi_radio_obj_t *self, bool enabled) { return; } if (!self->started && enabled) { - // esp_wifi_start() would default to soft-AP, thus setting it to station + // esp_wifi_start() would default to soft-AP, thus setting it to station start_station(self); ESP_ERROR_CHECK(esp_wifi_start()); self->started = true; @@ -127,7 +127,7 @@ void common_hal_wifi_radio_set_hostname(wifi_radio_obj_t *self, const char *host esp_netif_set_hostname(self->netif, hostname); } -wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t* ssid, size_t ssid_len, uint8_t* password, size_t password_len, uint8_t channel, mp_float_t timeout, uint8_t* bssid, size_t bssid_len) { +wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t *ssid, size_t ssid_len, uint8_t *password, size_t password_len, uint8_t channel, mp_float_t timeout, uint8_t *bssid, size_t bssid_len) { if (!common_hal_wifi_radio_get_enabled(self)) { mp_raise_RuntimeError(translate("wifi is not enabled")); } @@ -149,7 +149,7 @@ wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t xEventGroupClearBits(self->event_group_handle, WIFI_DISCONNECTED_BIT); start_station(self); - wifi_config_t* config = &self->sta_config; + wifi_config_t *config = &self->sta_config; memcpy(&config->sta.ssid, ssid, ssid_len); config->sta.ssid[ssid_len] = 0; memcpy(&config->sta.password, password, password_len); @@ -158,7 +158,7 @@ wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t // From esp_wifi_types.h: // Generally, station_config.bssid_set needs to be 0; and it needs // to be 1 only when users need to check the MAC address of the AP - if (bssid_len > 0){ + if (bssid_len > 0) { memcpy(&config->sta.bssid, bssid, bssid_len); config->sta.bssid[bssid_len] = 0; config->sta.bssid_set = true; @@ -202,7 +202,7 @@ mp_obj_t common_hal_wifi_radio_get_ap_info(wifi_radio_obj_t *self) { } // Make sure the interface is in STA mode - if (!self->sta_mode){ + if (!self->sta_mode) { return mp_const_none; } @@ -212,7 +212,7 @@ mp_obj_t common_hal_wifi_radio_get_ap_info(wifi_radio_obj_t *self) { // ESP_OK: succeed // ESP_ERR_WIFI_CONN: The station interface don't initialized // ESP_ERR_WIFI_NOT_CONNECT: The station is in disconnect status - if (esp_wifi_sta_get_ap_info(&self->ap_info.record) != ESP_OK){ + if (esp_wifi_sta_get_ap_info(&self->ap_info.record) != ESP_OK) { return mp_const_none; } else { if (strlen(self->ap_info.record.country.cc) == 0) { diff --git a/ports/esp32s2/common-hal/wifi/ScannedNetworks.c b/ports/esp32s2/common-hal/wifi/ScannedNetworks.c index cc733308d..62ef62b7f 100644 --- a/ports/esp32s2/common-hal/wifi/ScannedNetworks.c +++ b/ports/esp32s2/common-hal/wifi/ScannedNetworks.c @@ -52,10 +52,10 @@ static void wifi_scannednetworks_done(wifi_scannednetworks_obj_t *self) { static bool wifi_scannednetworks_wait_for_scan(wifi_scannednetworks_obj_t *self) { EventBits_t bits = xEventGroupWaitBits(self->radio_event_group, - WIFI_SCAN_DONE_BIT, - pdTRUE, - pdTRUE, - 0); + WIFI_SCAN_DONE_BIT, + pdTRUE, + pdTRUE, + 0); while ((bits & WIFI_SCAN_DONE_BIT) == 0 && !mp_hal_is_interrupted()) { RUN_BACKGROUND_TASKS; bits = xEventGroupWaitBits(self->radio_event_group, @@ -94,11 +94,11 @@ mp_obj_t common_hal_wifi_scannednetworks_next(wifi_scannednetworks_obj_t *self) } // If we need more space than we have, realloc. if (self->total_results > self->max_results) { - wifi_ap_record_t* results = m_renew_maybe(wifi_ap_record_t, - self->results, - self->max_results, - self->total_results, - true /* allow move */); + wifi_ap_record_t *results = m_renew_maybe(wifi_ap_record_t, + self->results, + self->max_results, + self->total_results, + true /* allow move */); if (results != NULL) { self->results = results; self->max_results = self->total_results; @@ -157,7 +157,7 @@ void wifi_scannednetworks_scan_next_channel(wifi_scannednetworks_obj_t *self) { } } -void wifi_scannednetworks_deinit(wifi_scannednetworks_obj_t* self) { +void wifi_scannednetworks_deinit(wifi_scannednetworks_obj_t *self) { // if a scan is active, make sure and clean up the idf's buffer of results. if (self->scanning) { esp_wifi_scan_stop(); diff --git a/ports/esp32s2/common-hal/wifi/ScannedNetworks.h b/ports/esp32s2/common-hal/wifi/ScannedNetworks.h index 36da387f2..9790c4ab3 100644 --- a/ports/esp32s2/common-hal/wifi/ScannedNetworks.h +++ b/ports/esp32s2/common-hal/wifi/ScannedNetworks.h @@ -43,7 +43,7 @@ typedef struct { EventGroupHandle_t radio_event_group; // Results from the last channel scan - wifi_ap_record_t* results; + wifi_ap_record_t *results; uint16_t current_result; uint16_t total_results; uint16_t max_results; diff --git a/ports/esp32s2/common-hal/wifi/__init__.c b/ports/esp32s2/common-hal/wifi/__init__.c index a3927b7c3..3ec4ebc24 100644 --- a/ports/esp32s2/common-hal/wifi/__init__.c +++ b/ports/esp32s2/common-hal/wifi/__init__.c @@ -39,11 +39,11 @@ wifi_radio_obj_t common_hal_wifi_radio_obj; #include "components/log/include/esp_log.h" -static const char* TAG = "wifi"; +static const char *TAG = "wifi"; -static void event_handler(void* arg, esp_event_base_t event_base, - int32_t event_id, void* event_data) { - wifi_radio_obj_t* radio = arg; +static void event_handler(void *arg, esp_event_base_t event_base, + int32_t event_id, void *event_data) { + wifi_radio_obj_t *radio = arg; if (event_base == WIFI_EVENT) { switch (event_id) { case WIFI_EVENT_SCAN_DONE: @@ -61,13 +61,13 @@ static void event_handler(void* arg, esp_event_base_t event_base, break; case WIFI_EVENT_STA_DISCONNECTED: { ESP_LOGW(TAG, "disconnected"); - wifi_event_sta_disconnected_t* d = (wifi_event_sta_disconnected_t*) event_data; + wifi_event_sta_disconnected_t *d = (wifi_event_sta_disconnected_t *)event_data; uint8_t reason = d->reason; ESP_LOGW(TAG, "reason %d 0x%02x", reason, reason); if (radio->retries_left > 0 && - reason != WIFI_REASON_AUTH_FAIL && - reason != WIFI_REASON_NO_AP_FOUND && - reason != WIFI_REASON_ASSOC_LEAVE) { + reason != WIFI_REASON_AUTH_FAIL && + reason != WIFI_REASON_NO_AP_FOUND && + reason != WIFI_REASON_ASSOC_LEAVE) { radio->retries_left--; ESP_LOGI(TAG, "Retrying connect. %d retries remaining", radio->retries_left); esp_wifi_connect(); @@ -107,7 +107,7 @@ void common_hal_wifi_init(void) { } wifi_ever_inited = true; - wifi_radio_obj_t* self = &common_hal_wifi_radio_obj; + wifi_radio_obj_t *self = &common_hal_wifi_radio_obj; self->netif = esp_netif_create_default_wifi_sta(); self->started = false; @@ -120,15 +120,15 @@ void common_hal_wifi_init(void) { self->event_group_handle = xEventGroupCreateStatic(&self->event_group); ESP_ERROR_CHECK(esp_event_handler_instance_register(WIFI_EVENT, - ESP_EVENT_ANY_ID, - &event_handler, - self, - &self->handler_instance_all_wifi)); + ESP_EVENT_ANY_ID, + &event_handler, + self, + &self->handler_instance_all_wifi)); ESP_ERROR_CHECK(esp_event_handler_instance_register(IP_EVENT, - IP_EVENT_STA_GOT_IP, - &event_handler, - self, - &self->handler_instance_got_ip)); + IP_EVENT_STA_GOT_IP, + &event_handler, + self, + &self->handler_instance_got_ip)); wifi_init_config_t config = WIFI_INIT_CONFIG_DEFAULT(); esp_err_t result = esp_wifi_init(&config); @@ -144,26 +144,26 @@ void wifi_reset(void) { if (!wifi_inited) { return; } - wifi_radio_obj_t* radio = &common_hal_wifi_radio_obj; + wifi_radio_obj_t *radio = &common_hal_wifi_radio_obj; common_hal_wifi_radio_set_enabled(radio, false); ESP_ERROR_CHECK(esp_event_handler_instance_unregister(WIFI_EVENT, - ESP_EVENT_ANY_ID, - radio->handler_instance_all_wifi)); + ESP_EVENT_ANY_ID, + radio->handler_instance_all_wifi)); ESP_ERROR_CHECK(esp_event_handler_instance_unregister(IP_EVENT, - IP_EVENT_STA_GOT_IP, - radio->handler_instance_got_ip)); + IP_EVENT_STA_GOT_IP, + radio->handler_instance_got_ip)); ESP_ERROR_CHECK(esp_wifi_deinit()); esp_netif_destroy(radio->netif); radio->netif = NULL; } -void ipaddress_ipaddress_to_esp_idf(mp_obj_t ip_address, ip_addr_t* esp_ip_address) { +void ipaddress_ipaddress_to_esp_idf(mp_obj_t ip_address, ip_addr_t *esp_ip_address) { if (!MP_OBJ_IS_TYPE(ip_address, &ipaddress_ipv4address_type)) { mp_raise_ValueError(translate("Only IPv4 addresses supported")); } mp_obj_t packed = common_hal_ipaddress_ipv4address_get_packed(ip_address); size_t len; - const char* bytes = mp_obj_str_get_data(packed, &len); + const char *bytes = mp_obj_str_get_data(packed, &len); IP_ADDR4(esp_ip_address, bytes[0], bytes[1], bytes[2], bytes[3]); } diff --git a/ports/esp32s2/common-hal/wifi/__init__.h b/ports/esp32s2/common-hal/wifi/__init__.h index d2bd06c57..1dbe50a04 100644 --- a/ports/esp32s2/common-hal/wifi/__init__.h +++ b/ports/esp32s2/common-hal/wifi/__init__.h @@ -33,6 +33,6 @@ void wifi_reset(void); -void ipaddress_ipaddress_to_esp_idf(mp_obj_t ip_address, ip_addr_t* esp_ip_address); +void ipaddress_ipaddress_to_esp_idf(mp_obj_t ip_address, ip_addr_t *esp_ip_address); #endif // MICROPY_INCLUDED_ESP32S2_COMMON_HAL_WIFI___INIT___H diff --git a/ports/esp32s2/esp_error.c b/ports/esp32s2/esp_error.c index 57bc51528..4bc44674b 100644 --- a/ports/esp32s2/esp_error.c +++ b/ports/esp32s2/esp_error.c @@ -31,8 +31,8 @@ void raise_esp_error(esp_err_t err) { const compressed_string_t *msg = NULL; - const mp_obj_type_t * exception_type = &mp_type_espidf_IDFError; - switch(err) { + const mp_obj_type_t *exception_type = &mp_type_espidf_IDFError; + switch (err) { case ESP_FAIL: msg = translate("Generic Failure"); break; @@ -78,9 +78,9 @@ void raise_esp_error(esp_err_t err) { const char *group = "ESP-IDF"; // tests must be in descending order - MP_STATIC_ASSERT( ESP_ERR_FLASH_BASE > ESP_ERR_MESH_BASE ); - MP_STATIC_ASSERT( ESP_ERR_MESH_BASE > ESP_ERR_WIFI_BASE ); - if(err >= ESP_ERR_FLASH_BASE) { + MP_STATIC_ASSERT(ESP_ERR_FLASH_BASE > ESP_ERR_MESH_BASE); + MP_STATIC_ASSERT(ESP_ERR_MESH_BASE > ESP_ERR_WIFI_BASE); + if (err >= ESP_ERR_FLASH_BASE) { group = "Flash"; } else if (err >= ESP_ERR_MESH_BASE) { group = "Mesh"; diff --git a/ports/esp32s2/fatfs_port.c b/ports/esp32s2/fatfs_port.c index 8bdc047c1..631f7f098 100644 --- a/ports/esp32s2/fatfs_port.c +++ b/ports/esp32s2/fatfs_port.c @@ -28,6 +28,6 @@ #include "lib/oofatfs/ff.h" DWORD get_fattime(void) { - // TODO: Implement this function. For now, fake it. + // TODO: Implement this function. For now, fake it. return ((2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2); } diff --git a/ports/esp32s2/mpconfigport.h b/ports/esp32s2/mpconfigport.h index 0cf695bc9..a3db0ab3d 100644 --- a/ports/esp32s2/mpconfigport.h +++ b/ports/esp32s2/mpconfigport.h @@ -36,7 +36,7 @@ #include "py/circuitpy_mpconfig.h" #define MICROPY_PORT_ROOT_POINTERS \ - CIRCUITPY_COMMON_ROOT_POINTERS + CIRCUITPY_COMMON_ROOT_POINTERS #define MICROPY_NLR_SETJMP (1) #define CIRCUITPY_DEFAULT_STACK_SIZE 0x6000 diff --git a/ports/esp32s2/mphalport.c b/ports/esp32s2/mphalport.c index 9b4c4bc5e..aaf1f468f 100644 --- a/ports/esp32s2/mphalport.c +++ b/ports/esp32s2/mphalport.c @@ -57,5 +57,5 @@ mp_uint_t cpu_get_regs_and_sp(mp_uint_t *regs, uint8_t reg_count) { // because the register value could change after it's been restored but that // is unlikely to happen with a heap pointer while we do a GC. xthal_window_spill(); - return (mp_uint_t) __builtin_frame_address(0); + return (mp_uint_t)__builtin_frame_address(0); } diff --git a/ports/esp32s2/mphalport.h b/ports/esp32s2/mphalport.h index 4feddbd9b..8682baec4 100644 --- a/ports/esp32s2/mphalport.h +++ b/ports/esp32s2/mphalport.h @@ -34,7 +34,7 @@ #include "py/mpconfig.h" #include "supervisor/shared/tick.h" -#define mp_hal_ticks_ms() ((mp_uint_t) supervisor_ticks_ms32()) +#define mp_hal_ticks_ms() ((mp_uint_t)supervisor_ticks_ms32()) bool mp_hal_stdin_any(void); diff --git a/ports/esp32s2/peripherals/pcnt.c b/ports/esp32s2/peripherals/pcnt.c index dd24569be..e4578a279 100644 --- a/ports/esp32s2/peripherals/pcnt.c +++ b/ports/esp32s2/peripherals/pcnt.c @@ -32,14 +32,14 @@ static uint8_t pcnt_unit_state[4]; void peripherals_pcnt_reset(void) { - for (uint8_t i = 0; i<=3; i++) { + for (uint8_t i = 0; i <= 3; i++) { pcnt_unit_state[i] = PCNT_UNIT_INACTIVE; } } int peripherals_pcnt_init(pcnt_config_t pcnt_config) { // Look for available pcnt unit - for (uint8_t i = 0; i<=3; i++) { + for (uint8_t i = 0; i <= 3; i++) { if (pcnt_unit_state[i] == PCNT_UNIT_INACTIVE) { pcnt_config.unit = (pcnt_unit_t)i; pcnt_unit_state[i] = PCNT_UNIT_ACTIVE; @@ -62,7 +62,7 @@ int peripherals_pcnt_init(pcnt_config_t pcnt_config) { return pcnt_config.unit; } -void peripherals_pcnt_deinit(pcnt_unit_t* unit) { +void peripherals_pcnt_deinit(pcnt_unit_t *unit) { pcnt_unit_state[*unit] = PCNT_UNIT_INACTIVE; *unit = PCNT_UNIT_MAX; } diff --git a/ports/esp32s2/peripherals/pcnt.h b/ports/esp32s2/peripherals/pcnt.h index 4fce13f4d..8bd8b0272 100644 --- a/ports/esp32s2/peripherals/pcnt.h +++ b/ports/esp32s2/peripherals/pcnt.h @@ -30,7 +30,7 @@ #include "driver/pcnt.h" extern int peripherals_pcnt_init(pcnt_config_t pcnt_config); -extern void peripherals_pcnt_deinit(pcnt_unit_t* unit); +extern void peripherals_pcnt_deinit(pcnt_unit_t *unit); extern void peripherals_pcnt_reset(void); #endif // MICROPY_INCLUDED_ESP32S2_PERIPHERALS_PCNT_HANDLER_H diff --git a/ports/esp32s2/peripherals/pins.c b/ports/esp32s2/peripherals/pins.c index 0d3d89ad5..f88228140 100755..100644 --- a/ports/esp32s2/peripherals/pins.c +++ b/ports/esp32s2/peripherals/pins.c @@ -33,13 +33,13 @@ // This macro is used to simplify pin definition in boards/<board>/pins.c #define PIN(p_name, p_number, p_adc_index, p_adc_channel, p_touch_channel) \ -const mcu_pin_obj_t pin_## p_name = { \ - PIN_PREFIX_VALUES \ - .number = p_number, \ - .adc_index = p_adc_index, \ - .adc_channel = p_adc_channel, \ - .touch_channel = p_touch_channel, \ -} + const mcu_pin_obj_t pin_##p_name = { \ + PIN_PREFIX_VALUES \ + .number = p_number, \ + .adc_index = p_adc_index, \ + .adc_channel = p_adc_channel, \ + .touch_channel = p_touch_channel, \ + } PIN(GPIO0, 0, NO_ADC, NO_ADC_CHANNEL, NO_TOUCH_CHANNEL); PIN(GPIO1, 1, ADC_UNIT_1, ADC_CHANNEL_0, TOUCH_PAD_NUM1); diff --git a/ports/esp32s2/peripherals/pins.h b/ports/esp32s2/peripherals/pins.h index e0f5e7ddf..c92f4b4cc 100644 --- a/ports/esp32s2/peripherals/pins.h +++ b/ports/esp32s2/peripherals/pins.h @@ -42,8 +42,8 @@ typedef struct { PIN_PREFIX_FIELDS gpio_num_t number; - uint8_t adc_index:2; - uint8_t adc_channel:6; + uint8_t adc_index : 2; + uint8_t adc_channel : 6; touch_pad_t touch_channel; } mcu_pin_obj_t; diff --git a/ports/esp32s2/peripherals/timer.c b/ports/esp32s2/peripherals/timer.c index 0ae140387..674d7fc5b 100644 --- a/ports/esp32s2/peripherals/timer.c +++ b/ports/esp32s2/peripherals/timer.c @@ -45,7 +45,7 @@ void peripherals_timer_reset(void) { } } -void peripherals_timer_init(const timer_config_t * config, timer_index_t * timer) { +void peripherals_timer_init(const timer_config_t *config, timer_index_t *timer) { bool break_loop = false; // get free timer @@ -63,7 +63,9 @@ void peripherals_timer_init(const timer_config_t * config, timer_index_t * timer return; } } - if (break_loop) {break;} + if (break_loop) { + break; + } } // initialize timer module @@ -71,6 +73,6 @@ void peripherals_timer_init(const timer_config_t * config, timer_index_t * timer timer_set_counter_value(timer->group, timer->idx, 0); } -void peripherals_timer_deinit(timer_index_t * timer) { +void peripherals_timer_deinit(timer_index_t *timer) { timer_deinit(timer->group, timer->idx); } diff --git a/ports/esp32s2/peripherals/timer.h b/ports/esp32s2/peripherals/timer.h index 8c9ebd91c..54150069c 100644 --- a/ports/esp32s2/peripherals/timer.h +++ b/ports/esp32s2/peripherals/timer.h @@ -34,8 +34,8 @@ typedef struct { timer_group_t group; } timer_index_t; -extern void peripherals_timer_init(const timer_config_t * config, timer_index_t * timer); -extern void peripherals_timer_deinit(timer_index_t * timer); +extern void peripherals_timer_init(const timer_config_t *config, timer_index_t *timer); +extern void peripherals_timer_deinit(timer_index_t *timer); extern void peripherals_timer_reset(void); #endif // MICROPY_INCLUDED_ESP32S2_PERIPHERALS_TIMER_HANDLER_H diff --git a/ports/esp32s2/supervisor/internal_flash.c b/ports/esp32s2/supervisor/internal_flash.c index de69a49f9..8f3d91776 100644 --- a/ports/esp32s2/supervisor/internal_flash.c +++ b/ports/esp32s2/supervisor/internal_flash.c @@ -41,7 +41,7 @@ #include "supervisor/usb.h" -STATIC const esp_partition_t * _partition; +STATIC const esp_partition_t *_partition; // TODO: Split the caching out of supervisor/shared/external_flash so we can use it. #define SECTOR_SIZE 4096 @@ -50,8 +50,8 @@ STATIC uint32_t _cache_lba = 0xffffffff; void supervisor_flash_init(void) { _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, - ESP_PARTITION_SUBTYPE_DATA_FAT, - NULL); + ESP_PARTITION_SUBTYPE_DATA_FAT, + NULL); } uint32_t supervisor_flash_get_block_size(void) { @@ -68,9 +68,9 @@ void port_internal_flash_flush(void) { mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) { esp_partition_read(_partition, - block * FILESYSTEM_BLOCK_SIZE, - dest, - num_blocks * FILESYSTEM_BLOCK_SIZE); + block * FILESYSTEM_BLOCK_SIZE, + dest, + num_blocks * FILESYSTEM_BLOCK_SIZE); return 0; } @@ -84,26 +84,26 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 if (_cache_lba != block_address) { esp_partition_read(_partition, - sector_offset, - _cache, - SECTOR_SIZE); + sector_offset, + _cache, + SECTOR_SIZE); _cache_lba = sector_offset; } for (uint8_t b = block_offset; b < blocks_per_sector; b++) { // Stop copying after the last block. if (block >= num_blocks) { - break; + break; } memcpy(_cache + b * FILESYSTEM_BLOCK_SIZE, - src + block * FILESYSTEM_BLOCK_SIZE, - FILESYSTEM_BLOCK_SIZE); + src + block * FILESYSTEM_BLOCK_SIZE, + FILESYSTEM_BLOCK_SIZE); block++; } esp_partition_erase_range(_partition, sector_offset, SECTOR_SIZE); esp_partition_write(_partition, - sector_offset, - _cache, - SECTOR_SIZE); + sector_offset, + _cache, + SECTOR_SIZE); } return 0; // success diff --git a/ports/esp32s2/supervisor/port.c b/ports/esp32s2/supervisor/port.c index 534f7f71b..d48b7ef89 100644 --- a/ports/esp32s2/supervisor/port.c +++ b/ports/esp32s2/supervisor/port.c @@ -68,7 +68,7 @@ #define HEAP_SIZE (48 * 1024) -uint32_t* heap; +uint32_t *heap; uint32_t heap_size; STATIC esp_timer_handle_t _tick_timer; @@ -78,7 +78,7 @@ TaskHandle_t circuitpython_task = NULL; extern void esp_restart(void) NORETURN; -void tick_timer_cb(void* arg) { +void tick_timer_cb(void *arg) { supervisor_tick(); // CircuitPython's VM is run in a separate FreeRTOS task from timer callbacks. So, we have to @@ -86,7 +86,7 @@ void tick_timer_cb(void* arg) { xTaskNotifyGive(circuitpython_task); } -void sleep_timer_cb(void* arg); +void sleep_timer_cb(void *arg); safe_mode_t port_init(void) { esp_timer_create_args_t args; @@ -127,8 +127,8 @@ safe_mode_t port_init(void) { #endif #ifdef CONFIG_SPIRAM - heap = (uint32_t*) (DRAM0_CACHE_ADDRESS_HIGH - CONFIG_SPIRAM_SIZE); - heap_size = CONFIG_SPIRAM_SIZE / sizeof(uint32_t); + heap = (uint32_t *)(DRAM0_CACHE_ADDRESS_HIGH - CONFIG_SPIRAM_SIZE); + heap_size = CONFIG_SPIRAM_SIZE / sizeof(uint32_t); #endif if (heap == NULL) { @@ -160,73 +160,73 @@ void reset_port(void) { // A larger delay so the idle task can run and do any IDF cleanup needed. vTaskDelay(4); -#if CIRCUITPY_ANALOGIO + #if CIRCUITPY_ANALOGIO analogout_reset(); -#endif + #endif -#if CIRCUITPY_DUALBANK + #if CIRCUITPY_DUALBANK dualbank_reset(); -#endif + #endif -#if CIRCUITPY_PS2IO + #if CIRCUITPY_PS2IO ps2_reset(); -#endif + #endif -#if CIRCUITPY_AUDIOBUSIO + #if CIRCUITPY_AUDIOBUSIO i2s_reset(); -#endif + #endif -#if CIRCUITPY_PULSEIO + #if CIRCUITPY_PULSEIO esp32s2_peripherals_rmt_reset(); pulsein_reset(); -#endif + #endif -#if CIRCUITPY_PWMIO + #if CIRCUITPY_PWMIO pwmout_reset(); -#endif + #endif -#if CIRCUITPY_BUSIO + #if CIRCUITPY_BUSIO i2c_reset(); spi_reset(); uart_reset(); -#endif + #endif -#if defined(CIRCUITPY_COUNTIO) || defined(CIRCUITPY_ROTARYIO) + #if defined(CIRCUITPY_COUNTIO) || defined(CIRCUITPY_ROTARYIO) peripherals_pcnt_reset(); -#endif + #endif -#if CIRCUITPY_FREQUENCYIO + #if CIRCUITPY_FREQUENCYIO peripherals_timer_reset(); -#endif + #endif -#if CIRCUITPY_PULSEIO + #if CIRCUITPY_PULSEIO esp32s2_peripherals_rmt_reset(); pulsein_reset(); -#endif + #endif -#if CIRCUITPY_PWMIO + #if CIRCUITPY_PWMIO pwmout_reset(); -#endif + #endif -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC rtc_reset(); -#endif + #endif -#if CIRCUITPY_TOUCHIO_USE_NATIVE + #if CIRCUITPY_TOUCHIO_USE_NATIVE peripherals_touch_reset(); -#endif + #endif -#if CIRCUITPY_WATCHDOG + #if CIRCUITPY_WATCHDOG watchdog_reset(); -#endif + #endif -#if CIRCUITPY_WIFI + #if CIRCUITPY_WIFI wifi_reset(); -#endif + #endif -#if CIRCUITPY_SOCKETPOOL + #if CIRCUITPY_SOCKETPOOL socket_reset(); -#endif + #endif } void reset_to_bootloader(void) { @@ -249,7 +249,7 @@ uint32_t *port_heap_get_top(void) { uint32_t *port_stack_get_limit(void) { #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-align" - return (uint32_t*) pxTaskGetStackStart(NULL); + return (uint32_t *)pxTaskGetStackStart(NULL); #pragma GCC diagnostic pop } @@ -281,7 +281,7 @@ uint32_t port_get_saved_word(void) { return REG_READ(RTC_CNTL_STORE0_REG); } -uint64_t port_get_raw_ticks(uint8_t* subticks) { +uint64_t port_get_raw_ticks(uint8_t *subticks) { // Convert microseconds to subticks of 1/32768 seconds // 32768/1000000 = 64/15625 in lowest terms // this arithmetic overflows after 570 years @@ -306,7 +306,7 @@ void port_wake_main_task() { xTaskNotifyGive(circuitpython_task); } -void sleep_timer_cb(void* arg) { +void sleep_timer_cb(void *arg) { port_wake_main_task(); } diff --git a/ports/esp32s2/supervisor/usb.c b/ports/esp32s2/supervisor/usb.c index 16657d407..54ac88dc4 100644 --- a/ports/esp32s2/supervisor/usb.c +++ b/ports/esp32s2/supervisor/usb.c @@ -44,39 +44,36 @@ #include "tusb.h" #ifdef CFG_TUSB_DEBUG - #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE) + #define USBD_STACK_SIZE (3 * configMINIMAL_STACK_SIZE) #else - #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) + #define USBD_STACK_SIZE (3 * configMINIMAL_STACK_SIZE / 2) #endif -StackType_t usb_device_stack[USBD_STACK_SIZE]; +StackType_t usb_device_stack[USBD_STACK_SIZE]; StaticTask_t usb_device_taskdef; // USB Device Driver task // This top level thread process all usb events and invoke callbacks -void usb_device_task(void* param) -{ - (void) param; +void usb_device_task(void *param) { + (void)param; - // RTOS forever loop - while (1) - { - // tinyusb device task - if (tusb_inited()) { - tud_task(); - tud_cdc_write_flush(); + // RTOS forever loop + while (1) { + // tinyusb device task + if (tusb_inited()) { + tud_task(); + tud_cdc_write_flush(); + } + vTaskDelay(1); } - vTaskDelay(1); - } } -static void configure_pins (usb_hal_context_t *usb) -{ +static void configure_pins(usb_hal_context_t *usb) { /* usb_periph_iopins currently configures USB_OTG as USB Device. * Introduce additional parameters in usb_hal_context_t when adding support * for USB Host. */ - for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { + for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) { gpio_pad_select_gpio(iopin->pin); if (iopin->is_output) { @@ -103,22 +100,21 @@ void init_usb_hardware(void) { usb_hal_init(&hal); configure_pins(&hal); - (void) xTaskCreateStatic(usb_device_task, - "usbd", - USBD_STACK_SIZE, - NULL, - 5, - usb_device_stack, - &usb_device_taskdef); + (void)xTaskCreateStatic(usb_device_task, + "usbd", + USBD_STACK_SIZE, + NULL, + 5, + usb_device_stack, + &usb_device_taskdef); } /** * Callback invoked when received an "wanted" char. * @param itf Interface index (for multiple cdc interfaces) * @param wanted_char The wanted char (set previously) */ -void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char) -{ - (void) itf; // not used +void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char) { + (void)itf; // not used // Workaround for using lib/utils/interrupt_char.c // Compare mp_interrupt_char with wanted_char and ignore if not matched if (mp_interrupt_char == wanted_char) { diff --git a/ports/esp32s2/tools/decode_backtrace.py b/ports/esp32s2/tools/decode_backtrace.py index 3f078895a..523677bae 100644 --- a/ports/esp32s2/tools/decode_backtrace.py +++ b/ports/esp32s2/tools/decode_backtrace.py @@ -15,9 +15,10 @@ print(board) while True: addresses = input("? ") if addresses.startswith("Backtrace:"): - addresses = addresses[len("Backtrace:"):] + addresses = addresses[len("Backtrace:") :] addresses = addresses.strip().split() addresses = [address.split(":")[0] for address in addresses] - print('got', addresses) - subprocess.run(["xtensa-esp32s2-elf-addr2line", - "-e", "build-{}/firmware.elf".format(board)] + addresses) + print("got", addresses) + subprocess.run( + ["xtensa-esp32s2-elf-addr2line", "-e", "build-{}/firmware.elf".format(board)] + addresses + ) diff --git a/ports/litex/background.c b/ports/litex/background.c index 174d9588a..da86919c0 100644 --- a/ports/litex/background.c +++ b/ports/litex/background.c @@ -29,6 +29,9 @@ #include "supervisor/usb.h" #include "supervisor/shared/stack.h" -void port_background_task(void) {} -void port_start_background_task(void) {} -void port_finish_background_task(void) {} +void port_background_task(void) { +} +void port_start_background_task(void) { +} +void port_finish_background_task(void) { +} diff --git a/ports/litex/boards/fomu/csr.h b/ports/litex/boards/fomu/csr.h index bf66fe3a1..7405d4312 100644 --- a/ports/litex/boards/fomu/csr.h +++ b/ports/litex/boards/fomu/csr.h @@ -1,6 +1,6 @@ -//-------------------------------------------------------------------------------- +// -------------------------------------------------------------------------------- // Auto-generated by Migen (f4fcd10) & LiteX (de205d4a) on 2019-11-25 14:57:34 -//-------------------------------------------------------------------------------- +// -------------------------------------------------------------------------------- #include <generated/soc.h> #ifndef __GENERATED_CSR_H #define __GENERATED_CSR_H @@ -21,41 +21,41 @@ extern uint32_t csr_readl(unsigned long addr); #define CSR_CTRL_RESET_ADDR 0xe0000000L #define CSR_CTRL_RESET_SIZE 1 static inline unsigned char ctrl_reset_read(void) { - unsigned char r = csr_readl(0xe0000000L); - return r; + unsigned char r = csr_readl(0xe0000000L); + return r; } static inline void ctrl_reset_write(unsigned char value) { - csr_writel(value, 0xe0000000L); + csr_writel(value, 0xe0000000L); } #define CSR_CTRL_SCRATCH_ADDR 0xe0000004L #define CSR_CTRL_SCRATCH_SIZE 4 static inline unsigned int ctrl_scratch_read(void) { - unsigned int r = csr_readl(0xe0000004L); - r <<= 8; - r |= csr_readl(0xe0000008L); - r <<= 8; - r |= csr_readl(0xe000000cL); - r <<= 8; - r |= csr_readl(0xe0000010L); - return r; + unsigned int r = csr_readl(0xe0000004L); + r <<= 8; + r |= csr_readl(0xe0000008L); + r <<= 8; + r |= csr_readl(0xe000000cL); + r <<= 8; + r |= csr_readl(0xe0000010L); + return r; } static inline void ctrl_scratch_write(unsigned int value) { - csr_writel(value >> 24, 0xe0000004L); - csr_writel(value >> 16, 0xe0000008L); - csr_writel(value >> 8, 0xe000000cL); - csr_writel(value, 0xe0000010L); + csr_writel(value >> 24, 0xe0000004L); + csr_writel(value >> 16, 0xe0000008L); + csr_writel(value >> 8, 0xe000000cL); + csr_writel(value, 0xe0000010L); } #define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014L #define CSR_CTRL_BUS_ERRORS_SIZE 4 static inline unsigned int ctrl_bus_errors_read(void) { - unsigned int r = csr_readl(0xe0000014L); - r <<= 8; - r |= csr_readl(0xe0000018L); - r <<= 8; - r |= csr_readl(0xe000001cL); - r <<= 8; - r |= csr_readl(0xe0000020L); - return r; + unsigned int r = csr_readl(0xe0000014L); + r <<= 8; + r |= csr_readl(0xe0000018L); + r <<= 8; + r |= csr_readl(0xe000001cL); + r <<= 8; + r |= csr_readl(0xe0000020L); + return r; } /* lxspi */ @@ -63,11 +63,11 @@ static inline unsigned int ctrl_bus_errors_read(void) { #define CSR_LXSPI_BITBANG_ADDR 0xe0007800L #define CSR_LXSPI_BITBANG_SIZE 1 static inline unsigned char lxspi_bitbang_read(void) { - unsigned char r = csr_readl(0xe0007800L); - return r; + unsigned char r = csr_readl(0xe0007800L); + return r; } static inline void lxspi_bitbang_write(unsigned char value) { - csr_writel(value, 0xe0007800L); + csr_writel(value, 0xe0007800L); } #define CSR_LXSPI_BITBANG_MOSI_OFFSET 0 #define CSR_LXSPI_BITBANG_MOSI_SIZE 1 @@ -80,17 +80,17 @@ static inline void lxspi_bitbang_write(unsigned char value) { #define CSR_LXSPI_MISO_ADDR 0xe0007804L #define CSR_LXSPI_MISO_SIZE 1 static inline unsigned char lxspi_miso_read(void) { - unsigned char r = csr_readl(0xe0007804L); - return r; + unsigned char r = csr_readl(0xe0007804L); + return r; } #define CSR_LXSPI_BITBANG_EN_ADDR 0xe0007808L #define CSR_LXSPI_BITBANG_EN_SIZE 1 static inline unsigned char lxspi_bitbang_en_read(void) { - unsigned char r = csr_readl(0xe0007808L); - return r; + unsigned char r = csr_readl(0xe0007808L); + return r; } static inline void lxspi_bitbang_en_write(unsigned char value) { - csr_writel(value, 0xe0007808L); + csr_writel(value, 0xe0007808L); } /* messible */ @@ -98,23 +98,23 @@ static inline void lxspi_bitbang_en_write(unsigned char value) { #define CSR_MESSIBLE_IN_ADDR 0xe0008000L #define CSR_MESSIBLE_IN_SIZE 1 static inline unsigned char messible_in_read(void) { - unsigned char r = csr_readl(0xe0008000L); - return r; + unsigned char r = csr_readl(0xe0008000L); + return r; } static inline void messible_in_write(unsigned char value) { - csr_writel(value, 0xe0008000L); + csr_writel(value, 0xe0008000L); } #define CSR_MESSIBLE_OUT_ADDR 0xe0008004L #define CSR_MESSIBLE_OUT_SIZE 1 static inline unsigned char messible_out_read(void) { - unsigned char r = csr_readl(0xe0008004L); - return r; + unsigned char r = csr_readl(0xe0008004L); + return r; } #define CSR_MESSIBLE_STATUS_ADDR 0xe0008008L #define CSR_MESSIBLE_STATUS_SIZE 1 static inline unsigned char messible_status_read(void) { - unsigned char r = csr_readl(0xe0008008L); - return r; + unsigned char r = csr_readl(0xe0008008L); + return r; } #define CSR_MESSIBLE_STATUS_FULL_OFFSET 0 #define CSR_MESSIBLE_STATUS_FULL_SIZE 1 @@ -126,11 +126,11 @@ static inline unsigned char messible_status_read(void) { #define CSR_REBOOT_CTRL_ADDR 0xe0006000L #define CSR_REBOOT_CTRL_SIZE 1 static inline unsigned char reboot_ctrl_read(void) { - unsigned char r = csr_readl(0xe0006000L); - return r; + unsigned char r = csr_readl(0xe0006000L); + return r; } static inline void reboot_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0006000L); + csr_writel(value, 0xe0006000L); } #define CSR_REBOOT_CTRL_IMAGE_OFFSET 0 #define CSR_REBOOT_CTRL_IMAGE_SIZE 2 @@ -139,20 +139,20 @@ static inline void reboot_ctrl_write(unsigned char value) { #define CSR_REBOOT_ADDR_ADDR 0xe0006004L #define CSR_REBOOT_ADDR_SIZE 4 static inline unsigned int reboot_addr_read(void) { - unsigned int r = csr_readl(0xe0006004L); - r <<= 8; - r |= csr_readl(0xe0006008L); - r <<= 8; - r |= csr_readl(0xe000600cL); - r <<= 8; - r |= csr_readl(0xe0006010L); - return r; + unsigned int r = csr_readl(0xe0006004L); + r <<= 8; + r |= csr_readl(0xe0006008L); + r <<= 8; + r |= csr_readl(0xe000600cL); + r <<= 8; + r |= csr_readl(0xe0006010L); + return r; } static inline void reboot_addr_write(unsigned int value) { - csr_writel(value >> 24, 0xe0006004L); - csr_writel(value >> 16, 0xe0006008L); - csr_writel(value >> 8, 0xe000600cL); - csr_writel(value, 0xe0006010L); + csr_writel(value >> 24, 0xe0006004L); + csr_writel(value >> 16, 0xe0006008L); + csr_writel(value >> 8, 0xe000600cL); + csr_writel(value, 0xe0006010L); } /* rgb */ @@ -160,29 +160,29 @@ static inline void reboot_addr_write(unsigned int value) { #define CSR_RGB_DAT_ADDR 0xe0006800L #define CSR_RGB_DAT_SIZE 1 static inline unsigned char rgb_dat_read(void) { - unsigned char r = csr_readl(0xe0006800L); - return r; + unsigned char r = csr_readl(0xe0006800L); + return r; } static inline void rgb_dat_write(unsigned char value) { - csr_writel(value, 0xe0006800L); + csr_writel(value, 0xe0006800L); } #define CSR_RGB_ADDR_ADDR 0xe0006804L #define CSR_RGB_ADDR_SIZE 1 static inline unsigned char rgb_addr_read(void) { - unsigned char r = csr_readl(0xe0006804L); - return r; + unsigned char r = csr_readl(0xe0006804L); + return r; } static inline void rgb_addr_write(unsigned char value) { - csr_writel(value, 0xe0006804L); + csr_writel(value, 0xe0006804L); } #define CSR_RGB_CTRL_ADDR 0xe0006808L #define CSR_RGB_CTRL_SIZE 1 static inline unsigned char rgb_ctrl_read(void) { - unsigned char r = csr_readl(0xe0006808L); - return r; + unsigned char r = csr_readl(0xe0006808L); + return r; } static inline void rgb_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0006808L); + csr_writel(value, 0xe0006808L); } #define CSR_RGB_CTRL_EXE_OFFSET 0 #define CSR_RGB_CTRL_EXE_SIZE 1 @@ -199,11 +199,11 @@ static inline void rgb_ctrl_write(unsigned char value) { #define CSR_RGB_RAW_ADDR 0xe000680cL #define CSR_RGB_RAW_SIZE 1 static inline unsigned char rgb_raw_read(void) { - unsigned char r = csr_readl(0xe000680cL); - return r; + unsigned char r = csr_readl(0xe000680cL); + return r; } static inline void rgb_raw_write(unsigned char value) { - csr_writel(value, 0xe000680cL); + csr_writel(value, 0xe000680cL); } #define CSR_RGB_RAW_R_OFFSET 0 #define CSR_RGB_RAW_R_SIZE 1 @@ -217,95 +217,95 @@ static inline void rgb_raw_write(unsigned char value) { #define CSR_TIMER0_LOAD_ADDR 0xe0002800L #define CSR_TIMER0_LOAD_SIZE 4 static inline unsigned int timer0_load_read(void) { - unsigned int r = csr_readl(0xe0002800L); - r <<= 8; - r |= csr_readl(0xe0002804L); - r <<= 8; - r |= csr_readl(0xe0002808L); - r <<= 8; - r |= csr_readl(0xe000280cL); - return r; + unsigned int r = csr_readl(0xe0002800L); + r <<= 8; + r |= csr_readl(0xe0002804L); + r <<= 8; + r |= csr_readl(0xe0002808L); + r <<= 8; + r |= csr_readl(0xe000280cL); + return r; } static inline void timer0_load_write(unsigned int value) { - csr_writel(value >> 24, 0xe0002800L); - csr_writel(value >> 16, 0xe0002804L); - csr_writel(value >> 8, 0xe0002808L); - csr_writel(value, 0xe000280cL); + csr_writel(value >> 24, 0xe0002800L); + csr_writel(value >> 16, 0xe0002804L); + csr_writel(value >> 8, 0xe0002808L); + csr_writel(value, 0xe000280cL); } #define CSR_TIMER0_RELOAD_ADDR 0xe0002810L #define CSR_TIMER0_RELOAD_SIZE 4 static inline unsigned int timer0_reload_read(void) { - unsigned int r = csr_readl(0xe0002810L); - r <<= 8; - r |= csr_readl(0xe0002814L); - r <<= 8; - r |= csr_readl(0xe0002818L); - r <<= 8; - r |= csr_readl(0xe000281cL); - return r; + unsigned int r = csr_readl(0xe0002810L); + r <<= 8; + r |= csr_readl(0xe0002814L); + r <<= 8; + r |= csr_readl(0xe0002818L); + r <<= 8; + r |= csr_readl(0xe000281cL); + return r; } static inline void timer0_reload_write(unsigned int value) { - csr_writel(value >> 24, 0xe0002810L); - csr_writel(value >> 16, 0xe0002814L); - csr_writel(value >> 8, 0xe0002818L); - csr_writel(value, 0xe000281cL); + csr_writel(value >> 24, 0xe0002810L); + csr_writel(value >> 16, 0xe0002814L); + csr_writel(value >> 8, 0xe0002818L); + csr_writel(value, 0xe000281cL); } #define CSR_TIMER0_EN_ADDR 0xe0002820L #define CSR_TIMER0_EN_SIZE 1 static inline unsigned char timer0_en_read(void) { - unsigned char r = csr_readl(0xe0002820L); - return r; + unsigned char r = csr_readl(0xe0002820L); + return r; } static inline void timer0_en_write(unsigned char value) { - csr_writel(value, 0xe0002820L); + csr_writel(value, 0xe0002820L); } #define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824L #define CSR_TIMER0_UPDATE_VALUE_SIZE 1 static inline unsigned char timer0_update_value_read(void) { - unsigned char r = csr_readl(0xe0002824L); - return r; + unsigned char r = csr_readl(0xe0002824L); + return r; } static inline void timer0_update_value_write(unsigned char value) { - csr_writel(value, 0xe0002824L); + csr_writel(value, 0xe0002824L); } #define CSR_TIMER0_VALUE_ADDR 0xe0002828L #define CSR_TIMER0_VALUE_SIZE 4 static inline unsigned int timer0_value_read(void) { - unsigned int r = csr_readl(0xe0002828L); - r <<= 8; - r |= csr_readl(0xe000282cL); - r <<= 8; - r |= csr_readl(0xe0002830L); - r <<= 8; - r |= csr_readl(0xe0002834L); - return r; + unsigned int r = csr_readl(0xe0002828L); + r <<= 8; + r |= csr_readl(0xe000282cL); + r <<= 8; + r |= csr_readl(0xe0002830L); + r <<= 8; + r |= csr_readl(0xe0002834L); + return r; } #define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838L #define CSR_TIMER0_EV_STATUS_SIZE 1 static inline unsigned char timer0_ev_status_read(void) { - unsigned char r = csr_readl(0xe0002838L); - return r; + unsigned char r = csr_readl(0xe0002838L); + return r; } static inline void timer0_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0002838L); + csr_writel(value, 0xe0002838L); } #define CSR_TIMER0_EV_PENDING_ADDR 0xe000283cL #define CSR_TIMER0_EV_PENDING_SIZE 1 static inline unsigned char timer0_ev_pending_read(void) { - unsigned char r = csr_readl(0xe000283cL); - return r; + unsigned char r = csr_readl(0xe000283cL); + return r; } static inline void timer0_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe000283cL); + csr_writel(value, 0xe000283cL); } #define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840L #define CSR_TIMER0_EV_ENABLE_SIZE 1 static inline unsigned char timer0_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0002840L); - return r; + unsigned char r = csr_readl(0xe0002840L); + return r; } static inline void timer0_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0002840L); + csr_writel(value, 0xe0002840L); } /* touch */ @@ -313,26 +313,26 @@ static inline void timer0_ev_enable_write(unsigned char value) { #define CSR_TOUCH_O_ADDR 0xe0005800L #define CSR_TOUCH_O_SIZE 1 static inline unsigned char touch_o_read(void) { - unsigned char r = csr_readl(0xe0005800L); - return r; + unsigned char r = csr_readl(0xe0005800L); + return r; } static inline void touch_o_write(unsigned char value) { - csr_writel(value, 0xe0005800L); + csr_writel(value, 0xe0005800L); } #define CSR_TOUCH_OE_ADDR 0xe0005804L #define CSR_TOUCH_OE_SIZE 1 static inline unsigned char touch_oe_read(void) { - unsigned char r = csr_readl(0xe0005804L); - return r; + unsigned char r = csr_readl(0xe0005804L); + return r; } static inline void touch_oe_write(unsigned char value) { - csr_writel(value, 0xe0005804L); + csr_writel(value, 0xe0005804L); } #define CSR_TOUCH_I_ADDR 0xe0005808L #define CSR_TOUCH_I_SIZE 1 static inline unsigned char touch_i_read(void) { - unsigned char r = csr_readl(0xe0005808L); - return r; + unsigned char r = csr_readl(0xe0005808L); + return r; } /* usb */ @@ -340,28 +340,28 @@ static inline unsigned char touch_i_read(void) { #define CSR_USB_PULLUP_OUT_ADDR 0xe0004800L #define CSR_USB_PULLUP_OUT_SIZE 1 static inline unsigned char usb_pullup_out_read(void) { - unsigned char r = csr_readl(0xe0004800L); - return r; + unsigned char r = csr_readl(0xe0004800L); + return r; } static inline void usb_pullup_out_write(unsigned char value) { - csr_writel(value, 0xe0004800L); + csr_writel(value, 0xe0004800L); } #define CSR_USB_ADDRESS_ADDR 0xe0004804L #define CSR_USB_ADDRESS_SIZE 1 static inline unsigned char usb_address_read(void) { - unsigned char r = csr_readl(0xe0004804L); - return r; + unsigned char r = csr_readl(0xe0004804L); + return r; } static inline void usb_address_write(unsigned char value) { - csr_writel(value, 0xe0004804L); + csr_writel(value, 0xe0004804L); } #define CSR_USB_ADDRESS_ADDR_OFFSET 0 #define CSR_USB_ADDRESS_ADDR_SIZE 7 #define CSR_USB_NEXT_EV_ADDR 0xe0004808L #define CSR_USB_NEXT_EV_SIZE 1 static inline unsigned char usb_next_ev_read(void) { - unsigned char r = csr_readl(0xe0004808L); - return r; + unsigned char r = csr_readl(0xe0004808L); + return r; } #define CSR_USB_NEXT_EV_IN_OFFSET 0 #define CSR_USB_NEXT_EV_IN_SIZE 1 @@ -374,27 +374,27 @@ static inline unsigned char usb_next_ev_read(void) { #define CSR_USB_SETUP_DATA_ADDR 0xe000480cL #define CSR_USB_SETUP_DATA_SIZE 1 static inline unsigned char usb_setup_data_read(void) { - unsigned char r = csr_readl(0xe000480cL); - return r; + unsigned char r = csr_readl(0xe000480cL); + return r; } #define CSR_USB_SETUP_DATA_DATA_OFFSET 0 #define CSR_USB_SETUP_DATA_DATA_SIZE 8 #define CSR_USB_SETUP_CTRL_ADDR 0xe0004810L #define CSR_USB_SETUP_CTRL_SIZE 1 static inline unsigned char usb_setup_ctrl_read(void) { - unsigned char r = csr_readl(0xe0004810L); - return r; + unsigned char r = csr_readl(0xe0004810L); + return r; } static inline void usb_setup_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0004810L); + csr_writel(value, 0xe0004810L); } #define CSR_USB_SETUP_CTRL_RESET_OFFSET 5 #define CSR_USB_SETUP_CTRL_RESET_SIZE 1 #define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L #define CSR_USB_SETUP_STATUS_SIZE 1 static inline unsigned char usb_setup_status_read(void) { - unsigned char r = csr_readl(0xe0004814L); - return r; + unsigned char r = csr_readl(0xe0004814L); + return r; } #define CSR_USB_SETUP_STATUS_EPNO_OFFSET 0 #define CSR_USB_SETUP_STATUS_EPNO_SIZE 4 @@ -409,49 +409,49 @@ static inline unsigned char usb_setup_status_read(void) { #define CSR_USB_SETUP_EV_STATUS_ADDR 0xe0004818L #define CSR_USB_SETUP_EV_STATUS_SIZE 1 static inline unsigned char usb_setup_ev_status_read(void) { - unsigned char r = csr_readl(0xe0004818L); - return r; + unsigned char r = csr_readl(0xe0004818L); + return r; } static inline void usb_setup_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0004818L); + csr_writel(value, 0xe0004818L); } #define CSR_USB_SETUP_EV_PENDING_ADDR 0xe000481cL #define CSR_USB_SETUP_EV_PENDING_SIZE 1 static inline unsigned char usb_setup_ev_pending_read(void) { - unsigned char r = csr_readl(0xe000481cL); - return r; + unsigned char r = csr_readl(0xe000481cL); + return r; } static inline void usb_setup_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe000481cL); + csr_writel(value, 0xe000481cL); } #define CSR_USB_SETUP_EV_ENABLE_ADDR 0xe0004820L #define CSR_USB_SETUP_EV_ENABLE_SIZE 1 static inline unsigned char usb_setup_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0004820L); - return r; + unsigned char r = csr_readl(0xe0004820L); + return r; } static inline void usb_setup_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0004820L); + csr_writel(value, 0xe0004820L); } #define CSR_USB_IN_DATA_ADDR 0xe0004824L #define CSR_USB_IN_DATA_SIZE 1 static inline unsigned char usb_in_data_read(void) { - unsigned char r = csr_readl(0xe0004824L); - return r; + unsigned char r = csr_readl(0xe0004824L); + return r; } static inline void usb_in_data_write(unsigned char value) { - csr_writel(value, 0xe0004824L); + csr_writel(value, 0xe0004824L); } #define CSR_USB_IN_DATA_DATA_OFFSET 0 #define CSR_USB_IN_DATA_DATA_SIZE 8 #define CSR_USB_IN_CTRL_ADDR 0xe0004828L #define CSR_USB_IN_CTRL_SIZE 1 static inline unsigned char usb_in_ctrl_read(void) { - unsigned char r = csr_readl(0xe0004828L); - return r; + unsigned char r = csr_readl(0xe0004828L); + return r; } static inline void usb_in_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0004828L); + csr_writel(value, 0xe0004828L); } #define CSR_USB_IN_CTRL_EPNO_OFFSET 0 #define CSR_USB_IN_CTRL_EPNO_SIZE 4 @@ -462,8 +462,8 @@ static inline void usb_in_ctrl_write(unsigned char value) { #define CSR_USB_IN_STATUS_ADDR 0xe000482cL #define CSR_USB_IN_STATUS_SIZE 1 static inline unsigned char usb_in_status_read(void) { - unsigned char r = csr_readl(0xe000482cL); - return r; + unsigned char r = csr_readl(0xe000482cL); + return r; } #define CSR_USB_IN_STATUS_IDLE_OFFSET 0 #define CSR_USB_IN_STATUS_IDLE_SIZE 1 @@ -474,46 +474,46 @@ static inline unsigned char usb_in_status_read(void) { #define CSR_USB_IN_EV_STATUS_ADDR 0xe0004830L #define CSR_USB_IN_EV_STATUS_SIZE 1 static inline unsigned char usb_in_ev_status_read(void) { - unsigned char r = csr_readl(0xe0004830L); - return r; + unsigned char r = csr_readl(0xe0004830L); + return r; } static inline void usb_in_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0004830L); + csr_writel(value, 0xe0004830L); } #define CSR_USB_IN_EV_PENDING_ADDR 0xe0004834L #define CSR_USB_IN_EV_PENDING_SIZE 1 static inline unsigned char usb_in_ev_pending_read(void) { - unsigned char r = csr_readl(0xe0004834L); - return r; + unsigned char r = csr_readl(0xe0004834L); + return r; } static inline void usb_in_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe0004834L); + csr_writel(value, 0xe0004834L); } #define CSR_USB_IN_EV_ENABLE_ADDR 0xe0004838L #define CSR_USB_IN_EV_ENABLE_SIZE 1 static inline unsigned char usb_in_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0004838L); - return r; + unsigned char r = csr_readl(0xe0004838L); + return r; } static inline void usb_in_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0004838L); + csr_writel(value, 0xe0004838L); } #define CSR_USB_OUT_DATA_ADDR 0xe000483cL #define CSR_USB_OUT_DATA_SIZE 1 static inline unsigned char usb_out_data_read(void) { - unsigned char r = csr_readl(0xe000483cL); - return r; + unsigned char r = csr_readl(0xe000483cL); + return r; } #define CSR_USB_OUT_DATA_DATA_OFFSET 0 #define CSR_USB_OUT_DATA_DATA_SIZE 8 #define CSR_USB_OUT_CTRL_ADDR 0xe0004840L #define CSR_USB_OUT_CTRL_SIZE 1 static inline unsigned char usb_out_ctrl_read(void) { - unsigned char r = csr_readl(0xe0004840L); - return r; + unsigned char r = csr_readl(0xe0004840L); + return r; } static inline void usb_out_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0004840L); + csr_writel(value, 0xe0004840L); } #define CSR_USB_OUT_CTRL_EPNO_OFFSET 0 #define CSR_USB_OUT_CTRL_EPNO_SIZE 4 @@ -526,8 +526,8 @@ static inline void usb_out_ctrl_write(unsigned char value) { #define CSR_USB_OUT_STATUS_ADDR 0xe0004844L #define CSR_USB_OUT_STATUS_SIZE 1 static inline unsigned char usb_out_status_read(void) { - unsigned char r = csr_readl(0xe0004844L); - return r; + unsigned char r = csr_readl(0xe0004844L); + return r; } #define CSR_USB_OUT_STATUS_EPNO_OFFSET 0 #define CSR_USB_OUT_STATUS_EPNO_SIZE 4 @@ -538,41 +538,41 @@ static inline unsigned char usb_out_status_read(void) { #define CSR_USB_OUT_EV_STATUS_ADDR 0xe0004848L #define CSR_USB_OUT_EV_STATUS_SIZE 1 static inline unsigned char usb_out_ev_status_read(void) { - unsigned char r = csr_readl(0xe0004848L); - return r; + unsigned char r = csr_readl(0xe0004848L); + return r; } static inline void usb_out_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0004848L); + csr_writel(value, 0xe0004848L); } #define CSR_USB_OUT_EV_PENDING_ADDR 0xe000484cL #define CSR_USB_OUT_EV_PENDING_SIZE 1 static inline unsigned char usb_out_ev_pending_read(void) { - unsigned char r = csr_readl(0xe000484cL); - return r; + unsigned char r = csr_readl(0xe000484cL); + return r; } static inline void usb_out_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe000484cL); + csr_writel(value, 0xe000484cL); } #define CSR_USB_OUT_EV_ENABLE_ADDR 0xe0004850L #define CSR_USB_OUT_EV_ENABLE_SIZE 1 static inline unsigned char usb_out_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0004850L); - return r; + unsigned char r = csr_readl(0xe0004850L); + return r; } static inline void usb_out_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0004850L); + csr_writel(value, 0xe0004850L); } #define CSR_USB_OUT_ENABLE_STATUS_ADDR 0xe0004854L #define CSR_USB_OUT_ENABLE_STATUS_SIZE 1 static inline unsigned char usb_out_enable_status_read(void) { - unsigned char r = csr_readl(0xe0004854L); - return r; + unsigned char r = csr_readl(0xe0004854L); + return r; } #define CSR_USB_OUT_STALL_STATUS_ADDR 0xe0004858L #define CSR_USB_OUT_STALL_STATUS_SIZE 1 static inline unsigned char usb_out_stall_status_read(void) { - unsigned char r = csr_readl(0xe0004858L); - return r; + unsigned char r = csr_readl(0xe0004858L); + return r; } /* version */ @@ -580,68 +580,68 @@ static inline unsigned char usb_out_stall_status_read(void) { #define CSR_VERSION_MAJOR_ADDR 0xe0007000L #define CSR_VERSION_MAJOR_SIZE 1 static inline unsigned char version_major_read(void) { - unsigned char r = csr_readl(0xe0007000L); - return r; + unsigned char r = csr_readl(0xe0007000L); + return r; } #define CSR_VERSION_MINOR_ADDR 0xe0007004L #define CSR_VERSION_MINOR_SIZE 1 static inline unsigned char version_minor_read(void) { - unsigned char r = csr_readl(0xe0007004L); - return r; + unsigned char r = csr_readl(0xe0007004L); + return r; } #define CSR_VERSION_REVISION_ADDR 0xe0007008L #define CSR_VERSION_REVISION_SIZE 1 static inline unsigned char version_revision_read(void) { - unsigned char r = csr_readl(0xe0007008L); - return r; + unsigned char r = csr_readl(0xe0007008L); + return r; } #define CSR_VERSION_GITREV_ADDR 0xe000700cL #define CSR_VERSION_GITREV_SIZE 4 static inline unsigned int version_gitrev_read(void) { - unsigned int r = csr_readl(0xe000700cL); - r <<= 8; - r |= csr_readl(0xe0007010L); - r <<= 8; - r |= csr_readl(0xe0007014L); - r <<= 8; - r |= csr_readl(0xe0007018L); - return r; + unsigned int r = csr_readl(0xe000700cL); + r <<= 8; + r |= csr_readl(0xe0007010L); + r <<= 8; + r |= csr_readl(0xe0007014L); + r <<= 8; + r |= csr_readl(0xe0007018L); + return r; } #define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL #define CSR_VERSION_GITEXTRA_SIZE 2 static inline unsigned short int version_gitextra_read(void) { - unsigned short int r = csr_readl(0xe000701cL); - r <<= 8; - r |= csr_readl(0xe0007020L); - return r; + unsigned short int r = csr_readl(0xe000701cL); + r <<= 8; + r |= csr_readl(0xe0007020L); + return r; } #define CSR_VERSION_DIRTY_ADDR 0xe0007024L #define CSR_VERSION_DIRTY_SIZE 1 static inline unsigned char version_dirty_read(void) { - unsigned char r = csr_readl(0xe0007024L); - return r; + unsigned char r = csr_readl(0xe0007024L); + return r; } #define CSR_VERSION_DIRTY_DIRTY_OFFSET 0 #define CSR_VERSION_DIRTY_DIRTY_SIZE 1 #define CSR_VERSION_MODEL_ADDR 0xe0007028L #define CSR_VERSION_MODEL_SIZE 1 static inline unsigned char version_model_read(void) { - unsigned char r = csr_readl(0xe0007028L); - return r; + unsigned char r = csr_readl(0xe0007028L); + return r; } #define CSR_VERSION_MODEL_MODEL_OFFSET 0 #define CSR_VERSION_MODEL_MODEL_SIZE 8 #define CSR_VERSION_SEED_ADDR 0xe000702cL #define CSR_VERSION_SEED_SIZE 4 static inline unsigned int version_seed_read(void) { - unsigned int r = csr_readl(0xe000702cL); - r <<= 8; - r |= csr_readl(0xe0007030L); - r <<= 8; - r |= csr_readl(0xe0007034L); - r <<= 8; - r |= csr_readl(0xe0007038L); - return r; + unsigned int r = csr_readl(0xe000702cL); + r <<= 8; + r |= csr_readl(0xe0007030L); + r <<= 8; + r |= csr_readl(0xe0007034L); + r <<= 8; + r |= csr_readl(0xe0007038L); + return r; } #endif diff --git a/ports/litex/boards/fomu/generated/soc.h b/ports/litex/boards/fomu/generated/soc.h index 91b2f1a31..1d73bbf0f 100644 --- a/ports/litex/boards/fomu/generated/soc.h +++ b/ports/litex/boards/fomu/generated/soc.h @@ -1,58 +1,58 @@ -//-------------------------------------------------------------------------------- +// -------------------------------------------------------------------------------- // Auto-generated by Migen (f4fcd10) & LiteX (de205d4a) on 2019-11-25 15:17:59 -//-------------------------------------------------------------------------------- +// -------------------------------------------------------------------------------- #ifndef __GENERATED_SOC_H #define __GENERATED_SOC_H #define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870 static inline int config_bitstream_sync_header1_read(void) { - return 2123999870; + return 2123999870; } #define CONFIG_BITSTREAM_SYNC_HEADER2 2125109630 static inline int config_bitstream_sync_header2_read(void) { - return 2125109630; + return 2125109630; } #define CONFIG_CLOCK_FREQUENCY 12000000 static inline int config_clock_frequency_read(void) { - return 12000000; + return 12000000; } #define CONFIG_CPU_RESET_ADDR 0 static inline int config_cpu_reset_addr_read(void) { - return 0; + return 0; } #define CONFIG_CPU_TYPE "VEXRISCV" -static inline const char * config_cpu_type_read(void) { - return "VEXRISCV"; +static inline const char *config_cpu_type_read(void) { + return "VEXRISCV"; } #define CONFIG_CPU_TYPE_VEXRISCV #define CONFIG_CPU_VARIANT "MIN" -static inline const char * config_cpu_variant_read(void) { - return "MIN"; +static inline const char *config_cpu_variant_read(void) { + return "MIN"; } #define CONFIG_CPU_VARIANT_MIN #define CONFIG_CSR_ALIGNMENT 32 static inline int config_csr_alignment_read(void) { - return 32; + return 32; } #define CONFIG_CSR_DATA_WIDTH 8 static inline int config_csr_data_width_read(void) { - return 8; + return 8; } #define CONFIG_FOMU_REV "HACKER" -static inline const char * config_fomu_rev_read(void) { - return "HACKER"; +static inline const char *config_fomu_rev_read(void) { + return "HACKER"; } #define CONFIG_FOMU_REV_HACKER #define CONFIG_SHADOW_BASE 2147483648 static inline int config_shadow_base_read(void) { - return 2147483648; + return 2147483648; } #define TIMER0_INTERRUPT 2 static inline int timer0_interrupt_read(void) { - return 2; + return 2; } #define USB_INTERRUPT 3 static inline int usb_interrupt_read(void) { - return 3; + return 3; } #endif diff --git a/ports/litex/boards/fomu/mpconfigboard.h b/ports/litex/boards/fomu/mpconfigboard.h index 127301eee..fd627c0b0 100644 --- a/ports/litex/boards/fomu/mpconfigboard.h +++ b/ports/litex/boards/fomu/mpconfigboard.h @@ -24,14 +24,14 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Fomu" #define MICROPY_HW_MCU_NAME "VexRiscv" #define FLASH_SIZE (0x100000) #define FLASH_PAGE_SIZE (0x1000) -#define FLASH_PARTITION_OFFSET_BYTES (1024*1024) +#define FLASH_PARTITION_OFFSET_BYTES (1024 * 1024) #define AUTORESET_DELAY_MS 500 #define BOARD_FLASH_SIZE (FLASH_SIZE) diff --git a/ports/litex/boards/fomu/pins.c b/ports/litex/boards/fomu/pins.c index 6be495c33..804a8b37f 100644 --- a/ports/litex/boards/fomu/pins.c +++ b/ports/litex/boards/fomu/pins.c @@ -1,9 +1,9 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_global_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_TOUCH1) }, - { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_TOUCH2) }, - { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_TOUCH3) }, - { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_TOUCH4) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_TOUCH1) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_TOUCH2) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_TOUCH3) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_TOUCH4) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/litex/common-hal/digitalio/DigitalInOut.c b/ports/litex/common-hal/digitalio/DigitalInOut.c index 53df637c4..96cc95dfa 100644 --- a/ports/litex/common-hal/digitalio/DigitalInOut.c +++ b/ports/litex/common-hal/digitalio/DigitalInOut.c @@ -32,12 +32,12 @@ #include "csr.h" void common_hal_digitalio_digitalinout_never_reset( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { (void)self; } digitalinout_result_t common_hal_digitalio_digitalinout_construct( - digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { + digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { // claim_pin(pin); self->pin = pin; @@ -59,14 +59,14 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self } void common_hal_digitalio_digitalinout_switch_to_input( - digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { (void)pull; touch_oe_write(touch_oe_read() & ~(1 << self->pin->number)); } digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( - digitalio_digitalinout_obj_t *self, bool value, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, bool value, + digitalio_drive_mode_t drive_mode) { (void)drive_mode; common_hal_digitalio_digitalinout_set_value(self, value); touch_oe_write(touch_oe_read() | (1 << self->pin->number)); @@ -74,48 +74,50 @@ digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { return (touch_oe_read() & (1 << self->pin->number)) ? DIRECTION_OUTPUT : DIRECTION_INPUT; } void common_hal_digitalio_digitalinout_set_value( - digitalio_digitalinout_obj_t *self, bool value) { - if (value) + digitalio_digitalinout_obj_t *self, bool value) { + if (value) { touch_o_write(touch_o_read() | (1 << self->pin->number)); - else + } else { touch_o_write(touch_o_read() & ~(1 << self->pin->number)); + } } bool common_hal_digitalio_digitalinout_get_value( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { return !!(touch_i_read() & (1 << self->pin->number)); } digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( - digitalio_digitalinout_obj_t *self, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, + digitalio_drive_mode_t drive_mode) { (void)self; (void)drive_mode; return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( - digitalio_digitalinout_obj_t *self) { - if (common_hal_digitalio_digitalinout_get_direction(self) == DIRECTION_OUTPUT) + digitalio_digitalinout_obj_t *self) { + if (common_hal_digitalio_digitalinout_get_direction(self) == DIRECTION_OUTPUT) { return DRIVE_MODE_PUSH_PULL; - else + } else { return DRIVE_MODE_OPEN_DRAIN; + } } void common_hal_digitalio_digitalinout_set_pull( - digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { (void)self; (void)pull; } digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { return PULL_NONE; } diff --git a/ports/litex/common-hal/microcontroller/Pin.c b/ports/litex/common-hal/microcontroller/Pin.c index 4d088a076..1cc4c41d5 100644 --- a/ports/litex/common-hal/microcontroller/Pin.c +++ b/ports/litex/common-hal/microcontroller/Pin.c @@ -38,27 +38,27 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number) { } // Clear claimed bit. - claimed_pins[pin_port] &= ~(1<<pin_number); + claimed_pins[pin_port] &= ~(1 << pin_number); } -void common_hal_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_reset_pin(const mcu_pin_obj_t *pin) { if (pin == NULL) { return; } reset_pin_number(0, pin->number); } -void claim_pin(const mcu_pin_obj_t* pin) { +void claim_pin(const mcu_pin_obj_t *pin) { // Set bit in claimed_pins bitmask. - claimed_pins[0] |= 1<<pin->number; + claimed_pins[0] |= 1 << pin->number; } -void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { +void common_hal_mcu_pin_claim(const mcu_pin_obj_t *pin) { claim_pin(pin); } bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number) { - return !(claimed_pins[pin_port] & 1<<pin_number); + return !(claimed_pins[pin_port] & 1 << pin_number); } bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { diff --git a/ports/litex/common-hal/microcontroller/Pin.h b/ports/litex/common-hal/microcontroller/Pin.h index 186e120a2..522191f3c 100644 --- a/ports/litex/common-hal/microcontroller/Pin.h +++ b/ports/litex/common-hal/microcontroller/Pin.h @@ -36,10 +36,10 @@ typedef struct { } mcu_pin_obj_t; #define PIN(p_number) \ -{ \ - { &mcu_pin_type }, \ - .number = p_number \ -} + { \ + { &mcu_pin_type }, \ + .number = p_number \ + } extern const mcu_pin_obj_t pin_TOUCH1; extern const mcu_pin_obj_t pin_TOUCH2; @@ -50,7 +50,7 @@ void reset_all_pins(void); // reset_pin_number takes the pin number instead of the pointer so that objects don't // need to store a full pointer. void reset_pin_number(uint8_t pin_port, uint8_t pin_number); -void claim_pin(const mcu_pin_obj_t* pin); +void claim_pin(const mcu_pin_obj_t *pin); bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number); void never_reset_pin_number(uint8_t pin_port, uint8_t pin_number); // GPIO_TypeDef * pin_port(uint8_t pin_port); diff --git a/ports/litex/common-hal/microcontroller/__init__.c b/ports/litex/common-hal/microcontroller/__init__.c index 522a41e2e..0a496d804 100644 --- a/ports/litex/common-hal/microcontroller/__init__.c +++ b/ports/litex/common-hal/microcontroller/__init__.c @@ -72,7 +72,7 @@ void common_hal_mcu_enable_interrupts(void) { if (nesting_count == 0) { // This is very very bad because it means there was mismatched disable/enables so we // "HardFault". - asm("ebreak"); + asm ("ebreak"); } nesting_count--; if (nesting_count > 0) { @@ -82,14 +82,17 @@ void common_hal_mcu_enable_interrupts(void) { } void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) { - if(runmode == RUNMODE_SAFE_MODE) + if (runmode == RUNMODE_SAFE_MODE) { safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE); + } } void common_hal_mcu_reset(void) { - filesystem_flush(); //TODO: implement as part of flash improvements + filesystem_flush(); // TODO: implement as part of flash improvements // NVIC_SystemReset(); - while(1); + while (1) { + ; + } } // The singleton microcontroller.Processor object, bound to microcontroller.cpu @@ -106,9 +109,9 @@ const mcu_pin_obj_t pin_TOUCH3 = PIN(2); const mcu_pin_obj_t pin_TOUCH4 = PIN(3); STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_TOUCH1) }, - { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_TOUCH2) }, - { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_TOUCH3) }, - { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_TOUCH4) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_TOUCH1) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_TOUCH2) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_TOUCH3) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_TOUCH4) }, }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/litex/common-hal/neopixel_write/__init__.c b/ports/litex/common-hal/neopixel_write/__init__.c index 29fd318d4..e7e5600fb 100644 --- a/ports/litex/common-hal/neopixel_write/__init__.c +++ b/ports/litex/common-hal/neopixel_write/__init__.c @@ -60,8 +60,9 @@ static void ledda_write(uint8_t value, uint8_t addr) { static int ledda_init_done; static void ledda_init(void) { - if (ledda_init_done) + if (ledda_init_done) { return; + } // Enable the driver rgb_ctrl_write((1 << CSR_RGB_CTRL_EXE_OFFSET) | (1 << CSR_RGB_CTRL_CURREN_OFFSET) | (1 << CSR_RGB_CTRL_RGBLEDEN_OFFSET)); @@ -69,7 +70,7 @@ static void ledda_init(void) { ledda_write(LEDDCR0_LEDDEN | LEDDCR0_FR250 | LEDDCR0_QUICKSTOP, LEDDCR0); // Set clock register to 12 MHz / 64 kHz - 1 - ledda_write((12000000/64000)-1, LEDDBR); + ledda_write((12000000 / 64000) - 1, LEDDBR); // Ensure LED "breathe" effect is diabled ledda_write(0, LEDDBCRR); @@ -82,7 +83,7 @@ static void ledda_init(void) { ledda_init_done = 1; } -void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, uint32_t numBytes) { +void common_hal_neopixel_write(const digitalio_digitalinout_obj_t *digitalinout, uint8_t *pixels, uint32_t numBytes) { (void)digitalinout; (void)numBytes; ledda_init(); diff --git a/ports/litex/common-hal/os/__init__.c b/ports/litex/common-hal/os/__init__.c index 578f3e8c6..c070c2777 100644 --- a/ports/litex/common-hal/os/__init__.c +++ b/ports/litex/common-hal/os/__init__.c @@ -50,12 +50,12 @@ STATIC MP_DEFINE_ATTRTUPLE( (mp_obj_t)&os_uname_info_release_obj, (mp_obj_t)&os_uname_info_version_obj, (mp_obj_t)&os_uname_info_machine_obj -); + ); mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; } -bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) { +bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { return false; } diff --git a/ports/litex/common-hal/supervisor/Runtime.c b/ports/litex/common-hal/supervisor/Runtime.c index 974f26cec..f82765178 100644 --- a/ports/litex/common-hal/supervisor/Runtime.c +++ b/ports/litex/common-hal/supervisor/Runtime.c @@ -29,9 +29,9 @@ #include "supervisor/serial.h" bool common_hal_supervisor_runtime_get_serial_connected(void) { - return (bool) serial_connected(); + return (bool)serial_connected(); } bool common_hal_supervisor_runtime_get_serial_bytes_available(void) { - return (bool) serial_bytes_available(); + return (bool)serial_bytes_available(); } diff --git a/ports/litex/fatfs_port.c b/ports/litex/fatfs_port.c index 8bdc047c1..631f7f098 100644 --- a/ports/litex/fatfs_port.c +++ b/ports/litex/fatfs_port.c @@ -28,6 +28,6 @@ #include "lib/oofatfs/ff.h" DWORD get_fattime(void) { - // TODO: Implement this function. For now, fake it. + // TODO: Implement this function. For now, fake it. return ((2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2); } diff --git a/ports/litex/hw/common.h b/ports/litex/hw/common.h index b902bc4f2..8b3a0304e 100644 --- a/ports/litex/hw/common.h +++ b/ports/litex/hw/common.h @@ -1,33 +1,27 @@ #ifndef _HW_COMMON_H_ #define _HW_COMMON_H_ #include <stdint.h> -static inline void csr_writeb(uint8_t value, uint32_t addr) -{ - *((volatile uint8_t *)addr) = value; +static inline void csr_writeb(uint8_t value, uint32_t addr) { + *((volatile uint8_t *)addr) = value; } -static inline uint8_t csr_readb(uint32_t addr) -{ - return *(volatile uint8_t *)addr; +static inline uint8_t csr_readb(uint32_t addr) { + return *(volatile uint8_t *)addr; } -static inline void csr_writew(uint16_t value, uint32_t addr) -{ - *((volatile uint16_t *)addr) = value; +static inline void csr_writew(uint16_t value, uint32_t addr) { + *((volatile uint16_t *)addr) = value; } -static inline uint16_t csr_readw(uint32_t addr) -{ - return *(volatile uint16_t *)addr; +static inline uint16_t csr_readw(uint32_t addr) { + return *(volatile uint16_t *)addr; } -static inline void csr_writel(uint32_t value, uint32_t addr) -{ - *((volatile uint32_t *)addr) = value; +static inline void csr_writel(uint32_t value, uint32_t addr) { + *((volatile uint32_t *)addr) = value; } -static inline uint32_t csr_readl(uint32_t addr) -{ - return *(volatile uint32_t *)addr; +static inline uint32_t csr_readl(uint32_t addr) { + return *(volatile uint32_t *)addr; } #endif /* _HW_COMMON_H_ */ diff --git a/ports/litex/irq.h b/ports/litex/irq.h index dc96c228d..34c8b0a10 100644 --- a/ports/litex/irq.h +++ b/ports/litex/irq.h @@ -14,54 +14,53 @@ extern "C" { #define CSR_DCACHE_INFO 0xCC0 #define csrr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) + asm volatile ("csrr %0, " #reg : "=r" (__tmp)); \ + __tmp; }) #define csrw(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" : : "i" (val)); \ + else \ + asm volatile ("csrw " #reg ", %0" : : "r" (val)); }) #define csrs(reg, bit) ({ \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ - else \ - asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs x0, " #reg ", %0" : : "i" (bit)); \ + else \ + asm volatile ("csrrs x0, " #reg ", %0" : : "r" (bit)); }) #define csrc(reg, bit) ({ \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ - else \ - asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) - -static inline unsigned int irq_getie(void) -{ - return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc x0, " #reg ", %0" : : "i" (bit)); \ + else \ + asm volatile ("csrrc x0, " #reg ", %0" : : "r" (bit)); }) + +static inline unsigned int irq_getie(void) { + return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; } -static inline void irq_setie(unsigned int ie) -{ - if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); +static inline void irq_setie(unsigned int ie) { + if (ie) { + csrs(mstatus,CSR_MSTATUS_MIE); + } else { + csrc(mstatus,CSR_MSTATUS_MIE); + } } -static inline unsigned int irq_getmask(void) -{ - unsigned int mask; - asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); - return mask; +static inline unsigned int irq_getmask(void) { + unsigned int mask; + asm volatile ("csrr %0, %1" : "=r" (mask) : "i" (CSR_IRQ_MASK)); + return mask; } -static inline void irq_setmask(unsigned int mask) -{ - asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); +static inline void irq_setmask(unsigned int mask) { + asm volatile ("csrw %0, %1" : : "i" (CSR_IRQ_MASK), "r" (mask)); } -static inline unsigned int irq_pending(void) -{ - unsigned int pending; - asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); - return pending; +static inline unsigned int irq_pending(void) { + unsigned int pending; + asm volatile ("csrr %0, %1" : "=r" (pending) : "i" (CSR_IRQ_PENDING)); + return pending; } #ifdef __cplusplus diff --git a/ports/litex/mpconfigport.h b/ports/litex/mpconfigport.h index 5f739e49e..cedc3badc 100644 --- a/ports/litex/mpconfigport.h +++ b/ports/litex/mpconfigport.h @@ -35,7 +35,7 @@ #include "py/circuitpy_mpconfig.h" #define MICROPY_PORT_ROOT_POINTERS \ - CIRCUITPY_COMMON_ROOT_POINTERS + CIRCUITPY_COMMON_ROOT_POINTERS #define MICROPY_NLR_SETJMP (1) #define CIRCUITPY_DEFAULT_STACK_SIZE 0x6000 diff --git a/ports/litex/mphalport.c b/ports/litex/mphalport.c index c7369dc05..5eedc73f3 100644 --- a/ports/litex/mphalport.c +++ b/ports/litex/mphalport.c @@ -60,12 +60,14 @@ void isr(void) { // Increase the "nesting count". Note: This should be going from 0 -> 1. nesting_count += 1; -#ifdef CFG_TUSB_MCU - if (irqs & (1 << USB_INTERRUPT)) + #ifdef CFG_TUSB_MCU + if (irqs & (1 << USB_INTERRUPT)) { usb_irq_handler(); -#endif - if (irqs & (1 << TIMER0_INTERRUPT)) + } + #endif + if (irqs & (1 << TIMER0_INTERRUPT)) { SysTick_Handler(); + } // Decrease the "nesting count". Note: This should be going from 1 -> 0. nesting_count -= 1; @@ -73,6 +75,6 @@ void isr(void) { mp_uint_t cpu_get_regs_and_sp(mp_uint_t *regs) { unsigned long __tmp; - asm volatile ("mv %0, x2" :"=r"(__tmp)); + asm volatile ("mv %0, x2" : "=r" (__tmp)); return __tmp; } diff --git a/ports/litex/mphalport.h b/ports/litex/mphalport.h index 540575c58..62c8e0bab 100644 --- a/ports/litex/mphalport.h +++ b/ports/litex/mphalport.h @@ -34,8 +34,8 @@ #include "py/mpconfig.h" #include "supervisor/shared/tick.h" -#define mp_hal_ticks_ms() ((mp_uint_t) supervisor_ticks_ms32()) -//#define mp_hal_delay_us(us) NRFX_DELAY_US((uint32_t) (us)) +#define mp_hal_ticks_ms() ((mp_uint_t)supervisor_ticks_ms32()) +// #define mp_hal_delay_us(us) NRFX_DELAY_US((uint32_t) (us)) bool mp_hal_stdin_any(void); diff --git a/ports/litex/supervisor/internal_flash.c b/ports/litex/supervisor/internal_flash.c index 9b1dea685..989fffcc4 100644 --- a/ports/litex/supervisor/internal_flash.c +++ b/ports/litex/supervisor/internal_flash.c @@ -53,9 +53,9 @@ enum pin { #define NO_CACHE 0xffffffff -static uint8_t _flash_cache[FLASH_PAGE_SIZE] __attribute__((aligned(4))); +static uint8_t _flash_cache[FLASH_PAGE_SIZE] __attribute__((aligned(4))); static uint32_t _flash_page_addr = NO_CACHE; -static bool _flash_cache_dirty; +static bool _flash_cache_dirty; // ------------------------------------------------------------------------- // When performing SPI operations, the flash cannot be accessed. Since we // normally execute directly from SPI, this can cause problems. @@ -65,14 +65,12 @@ static bool _flash_cache_dirty; // Therefore, we must re-implement these functions here and explicitly mark // them as being in `.ramtext`, even though they really ought to be inlined. __attribute__((section(".ramtext"))) -static inline void spi_writel(uint32_t value, uint32_t addr) -{ +static inline void spi_writel(uint32_t value, uint32_t addr) { *((volatile uint32_t *)addr) = value; } __attribute__((section(".ramtext"))) -static inline uint32_t spi_readl(uint32_t addr) -{ +static inline uint32_t spi_readl(uint32_t addr) { return *(volatile uint32_t *)addr; } @@ -92,9 +90,12 @@ static inline void bb_spi_en(unsigned int en) { } __attribute__((section(".ramtext"))) -static inline void bb_spi_irq_setie(unsigned int ie) -{ - if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); +static inline void bb_spi_irq_setie(unsigned int ie) { + if (ie) { + csrs(mstatus,CSR_MSTATUS_MIE); + } else { + csrc(mstatus,CSR_MSTATUS_MIE); + } } __attribute__((section(".ramtext"))) @@ -162,14 +163,14 @@ static int bb_spi_beginWrite(uint32_t addr, const void *v_data, unsigned int cou const uint8_t *data = v_data; unsigned int i; -#ifdef NDEBUG + #ifdef NDEBUG if (v_data < (const void *)_flash_cache) { - asm("ebreak"); + asm ("ebreak"); } - if ((v_data+count) > (const void *)&_flash_cache[4096]) { - asm("ebreak"); + if ((v_data + count) > (const void *)&_flash_cache[4096]) { + asm ("ebreak"); } -#endif + #endif // Enable Write-Enable Latch (WEL) bb_spi_begin(); @@ -181,8 +182,9 @@ static int bb_spi_beginWrite(uint32_t addr, const void *v_data, unsigned int cou spi_single_tx(addr >> 16); spi_single_tx(addr >> 8); spi_single_tx(addr >> 0); - for (i = 0; (i < count) && (i < 256); i++) + for (i = 0; (i < count) && (i < 256); i++) { spi_single_tx(*data++); + } bb_spi_end(); return 0; @@ -215,41 +217,46 @@ static void bb_spi_write_page(uint32_t flash_address, const uint8_t *data) { // Ensure we're within the target flash address range. if ((flash_address - FLASH_PARTITION_OFFSET_BYTES) > FLASH_SIZE) { - asm("ebreak"); + asm ("ebreak"); return; } if (flash_address < FLASH_PARTITION_OFFSET_BYTES) { - asm("ebreak"); + asm ("ebreak"); return; } if ((flash_address_end - FLASH_PARTITION_OFFSET_BYTES) > FLASH_SIZE) { - asm("ebreak"); + asm ("ebreak"); return; } if (flash_address_end < FLASH_PARTITION_OFFSET_BYTES) { - asm("ebreak"); + asm ("ebreak"); return; } // Ensure we're not erasing the middle of a flash bank if ((flash_address & 0xfff) != 0) { - asm("ebreak"); + asm ("ebreak"); return; } page_write_log[page_write_log_offset++] = flash_address; - if (page_write_log_offset > sizeof(page_write_log)/sizeof(*page_write_log)) page_write_log_offset=0; + if (page_write_log_offset > sizeof(page_write_log) / sizeof(*page_write_log)) { + page_write_log_offset = 0; + } - while (bb_spi_is_busy()) + while (bb_spi_is_busy()) { ; // relax + } bb_spi_beginErase4(flash_address); - while (bb_spi_is_busy()) + while (bb_spi_is_busy()) { ; // relax + } while (flash_address < flash_address_end) { bb_spi_beginWrite(flash_address, data, 256); - while (bb_spi_is_busy()) + while (bb_spi_is_busy()) { ; // relax + } flash_address += 256; data += 256; } @@ -267,16 +274,18 @@ uint32_t supervisor_flash_get_block_size(void) { } uint32_t supervisor_flash_get_block_count(void) { - return FLASH_SIZE/FILESYSTEM_BLOCK_SIZE; + return FLASH_SIZE / FILESYSTEM_BLOCK_SIZE; } __attribute__((section(".ramtext"))) void port_internal_flash_flush(void) { // Skip if data is the same, or if there is no data in the cache - if (_flash_page_addr == NO_CACHE) + if (_flash_page_addr == NO_CACHE) { return; - if (!_flash_cache_dirty) + } + if (!_flash_cache_dirty) { return; + } // Disable interrupts and enable bit-bang mode on the SPI flash. // This function is running from RAM -- otherwise enabling bitbang mode @@ -291,7 +300,7 @@ void port_internal_flash_flush(void) { bb_spi_en(0); bb_spi_irq_setie(1); - _flash_cache_dirty = false; + _flash_cache_dirty = false; } mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) { @@ -299,7 +308,7 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n supervisor_flash_flush(); uint32_t src = lba2addr(block); - memcpy(dest, (uint8_t*) src, FILESYSTEM_BLOCK_SIZE*num_blocks); + memcpy(dest, (uint8_t *)src, FILESYSTEM_BLOCK_SIZE * num_blocks); #if USB_AVAILABLE usb_background(); @@ -310,7 +319,7 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32_t num_blocks) { while (num_blocks) { - uint32_t const addr = lba2addr(lba); + uint32_t const addr = lba2addr(lba); uint32_t const page_addr = addr & ~(FLASH_PAGE_SIZE - 1); uint32_t count = 8 - (lba % 8); // up to page boundary @@ -334,8 +343,8 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 } // adjust for next run - lba += count; - src += count * FILESYSTEM_BLOCK_SIZE; + lba += count; + src += count * FILESYSTEM_BLOCK_SIZE; num_blocks -= count; #if USB_AVAILABLE diff --git a/ports/litex/supervisor/port.c b/ports/litex/supervisor/port.c index 04ff1c09b..6f108ee05 100644 --- a/ports/litex/supervisor/port.c +++ b/ports/litex/supervisor/port.c @@ -87,7 +87,7 @@ void reset_port(void) { void reset_to_bootloader(void) { reboot_ctrl_write(0xac); - for(;;) {} + for (;;) {} } void reset_cpu(void) { @@ -97,7 +97,7 @@ void reset_cpu(void) { // simply writing this value" -- // https://workshop.fomu.im/en/latest/riscv.html reboot_ctrl_write(0xac); - for(;;) {} + for (;;) {} } bool port_has_fixed_stack(void) { @@ -129,7 +129,7 @@ uint32_t port_get_saved_word(void) { return _ebss; } -uint64_t port_get_raw_ticks(uint8_t* subticks) { +uint64_t port_get_raw_ticks(uint8_t *subticks) { // Reading 64 bits may take two loads, so turn of interrupts while we do it. common_hal_mcu_disable_interrupts(); uint64_t raw_tick_snapshot = raw_ticks; diff --git a/ports/mimxrt10xx/background.c b/ports/mimxrt10xx/background.c index a8a613d41..9e531cea2 100644 --- a/ports/mimxrt10xx/background.c +++ b/ports/mimxrt10xx/background.c @@ -32,5 +32,7 @@ void port_background_task(void) { audio_dma_background(); #endif } -void port_start_background_task(void) {} -void port_finish_background_task(void) {} +void port_start_background_task(void) { +} +void port_finish_background_task(void) { +} diff --git a/ports/mimxrt10xx/boards/feather_m7_1011/board.c b/ports/mimxrt10xx/boards/feather_m7_1011/board.c index 1db1dd686..5e20e5e3c 100644 --- a/ports/mimxrt10xx/boards/feather_m7_1011/board.c +++ b/ports/mimxrt10xx/boards/feather_m7_1011/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_13);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_12);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_13);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); diff --git a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c index 9ba3e168f..5871dda96 100644 --- a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c @@ -14,14 +14,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -29,141 +29,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q32JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, // Bit pattern for setting Quad Enable. + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, // Bit pattern for setting Quad Enable. - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status -2 - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01 /* number of bytes to write */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status -2 + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01 /* number of bytes to write */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/board.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/board.c index 1db1dd686..5e20e5e3c 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1011/board.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_13);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_12);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_13);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c index eafc9ac3a..7460615c4 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c @@ -14,14 +14,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -29,141 +29,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/pins.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/pins.c index 4e5de8de2..b752b8ed3 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1011/pins.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/pins.c @@ -41,7 +41,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = { { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RESET), MP_ROM_PTR(&pin_GPIO_AD_00) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_GPIO_12) }, { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_GPIO_11) }, - //{ MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RTS), MP_ROM_PTR(&pin_) }, + // { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RTS), MP_ROM_PTR(&pin_) }, { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO_SD_05) }, diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/board.c b/ports/mimxrt10xx/boards/feather_mimxrt1062/board.c index 26f55f96e..3782d3f2d 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1062/board.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_06); diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c index fef1c11e3..d6cfc07e6 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c +++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h b/ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h index 4c3953187..7b335d896 100644 --- a/ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h +++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h @@ -1,10 +1,10 @@ #define MICROPY_HW_BOARD_NAME "Feather MIMXRT1062" #define MICROPY_HW_MCU_NAME "IMXRT1062DVJ6A" -//TODO -//#define MICROPY_HW_LED_STATUS (&pin_PA27) +// TODO +// #define MICROPY_HW_LED_STATUS (&pin_PA27) -//#define MICROPY_HW_NEOPIXEL (&pin_PB22) +// #define MICROPY_HW_NEOPIXEL (&pin_PB22) // If you change this, then make sure to update the linker scripts as well to // make sure you don't overwrite code diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board.c b/ports/mimxrt10xx/boards/imxrt1010_evk/board.c index 8519893a5..9f7a22a86 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_13); //SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_12); //SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_13); // SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12); // SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); common_hal_never_reset_pin(&pin_GPIO_SD_11); diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c index 00ee47c98..9c88f689d 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for AT25SF128A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board.c b/ports/mimxrt10xx/boards/imxrt1020_evk/board.c index 531c0c6f6..4ae1e19b0 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_B0_00);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_B0_01);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_B0_00);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_B0_01);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_06); diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c index 4c3ba4717..6589ad9c4 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for IS25LP064A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_30MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_30MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - // RADDR_SDR, FLEXSPI_4PAD, 24 bits to transmit ), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - // READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + // RADDR_SDR, FLEXSPI_4PAD, 24 bits to transmit ), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + // READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/board.c b/ports/mimxrt10xx/boards/imxrt1060_evk/board.c index e7d74ab49..c4a2867ab 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/board.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_B0_06);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_B0_07);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_B1_00); diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c index 502e21a3b..40db33444 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for IS25WP064A with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board.c b/ports/mimxrt10xx/boards/metro_m7_1011/board.c index 1db1dd686..5e20e5e3c 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/board.c +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board.c @@ -32,8 +32,8 @@ void board_init(void) { // SWD Pins - common_hal_never_reset_pin(&pin_GPIO_AD_13);//SWDIO - common_hal_never_reset_pin(&pin_GPIO_AD_12);//SWCLK + common_hal_never_reset_pin(&pin_GPIO_AD_13);// SWDIO + common_hal_never_reset_pin(&pin_GPIO_AD_12);// SWCLK // FLEX flash common_hal_never_reset_pin(&pin_GPIO_SD_12); diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c index 991bc43e4..3f4ab0271 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c +++ b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,151 +30,151 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q16JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { + .seqId = 2u, + .seqNum = 1u, + }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x0200, - .configCmdEnable = 1u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .configCmdSeqs[0] = { - .seqId = 2u, - .seqNum = 1u, - }, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, - DUMMY_SDR, FLEXSPI_1PAD, 8), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, + DUMMY_SDR, FLEXSPI_1PAD, 8), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/teensy40/flash_config.c b/ports/mimxrt10xx/boards/teensy40/flash_config.c index 991bc43e4..3f4ab0271 100644 --- a/ports/mimxrt10xx/boards/teensy40/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy40/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,151 +30,151 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q16JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { + .seqId = 2u, + .seqNum = 1u, + }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x0200, - .configCmdEnable = 1u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .configCmdSeqs[0] = { - .seqId = 2u, - .seqNum = 1u, - }, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, - DUMMY_SDR, FLEXSPI_1PAD, 8), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, + DUMMY_SDR, FLEXSPI_1PAD, 8), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/boards/teensy41/flash_config.c b/ports/mimxrt10xx/boards/teensy41/flash_config.c index c0e0c86f9..09886dece 100644 --- a/ports/mimxrt10xx/boards/teensy41/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy41/flash_config.c @@ -15,14 +15,14 @@ __attribute__((section(".boot_hdr.ivt"))) * IVT Data *************************************/ const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) @@ -30,141 +30,141 @@ __attribute__((section(".boot_hdr.boot_data"))) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ }; // Config for W25Q64JV with QSPI routed. __attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, + .pageSize = 256u, + .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, + .blockSize = 0x00010000, .isUniformBlockSize = false, .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { + .seqId = 4u, + .seqNum = 1u, + }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, + READ_SDR, FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, + READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, + STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, + STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE }, + }, }; diff --git a/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c b/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c index 9587eba63..5e7bb82c7 100644 --- a/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c +++ b/ports/mimxrt10xx/common-hal/analogio/AnalogIn.c @@ -36,8 +36,8 @@ #define ADC_CHANNEL_GROUP 0 -void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self, + const mcu_pin_obj_t *pin) { adc_config_t config = {0}; if (pin->adc == NULL) { diff --git a/ports/mimxrt10xx/common-hal/analogio/AnalogOut.c b/ports/mimxrt10xx/common-hal/analogio/AnalogOut.c index 6bdbeff7c..bf21e30df 100644 --- a/ports/mimxrt10xx/common-hal/analogio/AnalogOut.c +++ b/ports/mimxrt10xx/common-hal/analogio/AnalogOut.c @@ -31,7 +31,7 @@ #include "shared-bindings/microcontroller/Pin.h" #include "supervisor/shared/translate.h" -void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self, const mcu_pin_obj_t *pin) { mp_raise_NotImplementedError(translate("AnalogOut functionality not supported")); } diff --git a/ports/mimxrt10xx/common-hal/busio/I2C.c b/ports/mimxrt10xx/common-hal/busio/I2C.c index c8daddc4b..74639d0ef 100644 --- a/ports/mimxrt10xx/common-hal/busio/I2C.c +++ b/ports/mimxrt10xx/common-hal/busio/I2C.c @@ -37,16 +37,16 @@ #include "fsl_lpi2c.h" #include "fsl_gpio.h" -#define I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (1+CLOCK_GetDiv(kCLOCK_Lpi2cDiv))) +#define I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (1 + CLOCK_GetDiv(kCLOCK_Lpi2cDiv))) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5 5U -//arrays use 0 based numbering: I2C1 is stored at index 0 +// arrays use 0 based numbering: I2C1 is stored at index 0 #define MAX_I2C 4 STATIC bool reserved_i2c[MAX_I2C]; STATIC bool never_reset_i2c[MAX_I2C]; void i2c_reset(void) { - for(uint i = 0; i < MP_ARRAY_SIZE(mcu_i2c_banks); i++) { + for (uint i = 0; i < MP_ARRAY_SIZE(mcu_i2c_banks); i++) { if (!never_reset_i2c[i]) { reserved_i2c[i] = false; LPI2C_MasterDeinit(mcu_i2c_banks[i]); @@ -64,30 +64,29 @@ static void config_periph_pin(const mcu_periph_obj_t *periph) { IOMUXC_SetPinConfig(0, 0, 0, 0, periph->pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(0) - | IOMUXC_SW_PAD_CTL_PAD_PUS(3) - | IOMUXC_SW_PAD_CTL_PAD_PUE(0) - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(1) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) - | IOMUXC_SW_PAD_CTL_PAD_DSE(4) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS(3) + | IOMUXC_SW_PAD_CTL_PAD_PUE(0) + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(1) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(4) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } -static void i2c_check_pin_config(const mcu_pin_obj_t *pin, uint32_t pull) -{ +static void i2c_check_pin_config(const mcu_pin_obj_t *pin, uint32_t pull) { IOMUXC_SetPinConfig(0, 0, 0, 0, pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(1) - | IOMUXC_SW_PAD_CTL_PAD_PUS(0) // Pulldown - | IOMUXC_SW_PAD_CTL_PAD_PUE(pull) // 0=nopull (keeper), 1=pull - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(0) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) - | IOMUXC_SW_PAD_CTL_PAD_DSE(1) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS(0) // Pulldown + | IOMUXC_SW_PAD_CTL_PAD_PUE(pull) // 0=nopull (keeper), 1=pull + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(0) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(1) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, - const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) { + const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) { #if CIRCUITPY_REQUIRE_I2C_PULLUPS // Test that the pins are in a high state. (Hopefully indicating they are pulled up.) @@ -107,7 +106,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, // We must pull up within 3us to achieve 400khz. common_hal_mcu_delay_us(3); - if( !GPIO_PinRead(sda->gpio, sda->number) || !GPIO_PinRead(scl->gpio, scl->number)) { + if (!GPIO_PinRead(sda->gpio, sda->number) || !GPIO_PinRead(scl->gpio, scl->number)) { common_hal_reset_pin(sda); common_hal_reset_pin(scl); mp_raise_RuntimeError(translate("No pull up found on SDA or SCL; check your wiring")); @@ -118,15 +117,18 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const uint32_t scl_count = MP_ARRAY_SIZE(mcu_i2c_scl_list); for (uint32_t i = 0; i < sda_count; ++i) { - if (mcu_i2c_sda_list[i].pin != sda) + if (mcu_i2c_sda_list[i].pin != sda) { continue; + } for (uint32_t j = 0; j < scl_count; ++j) { - if (mcu_i2c_scl_list[j].pin != scl) + if (mcu_i2c_scl_list[j].pin != scl) { continue; + } - if (mcu_i2c_scl_list[j].bank_idx != mcu_i2c_sda_list[i].bank_idx) + if (mcu_i2c_scl_list[j].bank_idx != mcu_i2c_sda_list[i].bank_idx) { continue; + } self->sda = &mcu_i2c_sda_list[i]; self->scl = &mcu_i2c_scl_list[j]; @@ -135,7 +137,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, } } - if(self->sda == NULL || self->scl == NULL) { + if (self->sda == NULL || self->scl == NULL) { mp_raise_ValueError(translate("Invalid pins")); } else { self->i2c = mcu_i2c_banks[self->sda->bank_idx - 1]; @@ -209,23 +211,24 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) { } uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, - const uint8_t *data, size_t len, bool transmit_stop_bit) { + const uint8_t *data, size_t len, bool transmit_stop_bit) { lpi2c_master_transfer_t xfer = { 0 }; xfer.flags = transmit_stop_bit ? kLPI2C_TransferDefaultFlag : kLPI2C_TransferNoStopFlag; xfer.slaveAddress = addr; - xfer.data = (uint8_t*)data; + xfer.data = (uint8_t *)data; xfer.dataSize = len; const status_t status = LPI2C_MasterTransferBlocking(self->i2c, &xfer); - if (status == kStatus_Success) + if (status == kStatus_Success) { return 0; + } return MP_EIO; } uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, - uint8_t *data, size_t len) { + uint8_t *data, size_t len) { lpi2c_master_transfer_t xfer = { 0 }; xfer.direction = kLPI2C_Read; @@ -234,8 +237,9 @@ uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, xfer.dataSize = len; const status_t status = LPI2C_MasterTransferBlocking(self->i2c, &xfer); - if (status == kStatus_Success) + if (status == kStatus_Success) { return 0; + } return MP_EIO; } diff --git a/ports/mimxrt10xx/common-hal/busio/SPI.c b/ports/mimxrt10xx/common-hal/busio/SPI.c index 00d8d9867..3488ac0fb 100644 --- a/ports/mimxrt10xx/common-hal/busio/SPI.c +++ b/ports/mimxrt10xx/common-hal/busio/SPI.c @@ -40,7 +40,7 @@ #define MAX_SPI_BUSY_RETRIES 100 -//arrays use 0 based numbering: SPI1 is stored at index 0 +// arrays use 0 based numbering: SPI1 is stored at index 0 #define MAX_SPI 4 STATIC bool reserved_spi[MAX_SPI]; STATIC bool never_reset_spi[MAX_SPI]; @@ -55,13 +55,13 @@ STATIC void config_periph_pin(const mcu_periph_obj_t *periph) { IOMUXC_SetPinConfig(0, 0, 0, 0, periph->pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(0) - | IOMUXC_SW_PAD_CTL_PAD_PUS(0) - | IOMUXC_SW_PAD_CTL_PAD_PUE(0) - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(0) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) - | IOMUXC_SW_PAD_CTL_PAD_DSE(4) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS(0) + | IOMUXC_SW_PAD_CTL_PAD_PUE(0) + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(0) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(4) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } void spi_reset(void) { @@ -74,8 +74,8 @@ void spi_reset(void) { } void common_hal_busio_spi_construct(busio_spi_obj_t *self, - const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, - const mcu_pin_obj_t *miso) { + const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, + const mcu_pin_obj_t *miso) { const uint32_t sck_count = MP_ARRAY_SIZE(mcu_spi_sck_list); const uint32_t miso_count = MP_ARRAY_SIZE(mcu_spi_miso_list); @@ -86,15 +86,15 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, if (mcu_spi_sck_list[i].pin != clock) { continue; } - //if both MOSI and MISO exist, loop search normally + // if both MOSI and MISO exist, loop search normally if ((mosi != NULL) && (miso != NULL)) { for (uint j = 0; j < mosi_count; j++) { if ((mcu_spi_mosi_list[i].pin != mosi) - || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)){ + || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)) { continue; } for (uint k = 0; k < miso_count; k++) { - if ((mcu_spi_miso_list[k].pin != miso) //everything needs the same index + if ((mcu_spi_miso_list[k].pin != miso) // everything needs the same index || (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[k].bank_idx)) { continue; } @@ -103,7 +103,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, spi_taken = true; break; } - //store pins if not + // store pins if not self->clock = &mcu_spi_sck_list[i]; self->mosi = &mcu_spi_mosi_list[j]; self->miso = &mcu_spi_miso_list[k]; @@ -116,10 +116,10 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, if (self->clock != NULL || spi_taken) { break; } - // if just MISO, reduce search + // if just MISO, reduce search } else if (miso != NULL) { for (uint j = 0; j < miso_count; j++) { - if ((mcu_spi_miso_list[j].pin != miso) //only SCK and MISO need the same index + if ((mcu_spi_miso_list[j].pin != miso) // only SCK and MISO need the same index || (mcu_spi_sck_list[i].bank_idx != mcu_spi_miso_list[j].bank_idx)) { continue; } @@ -134,10 +134,10 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, if (self->clock != NULL || spi_taken) { break; } - // if just MOSI, reduce search + // if just MOSI, reduce search } else if (mosi != NULL) { for (uint j = 0; j < mosi_count; j++) { - if ((mcu_spi_mosi_list[j].pin != mosi) //only SCK and MOSI need the same index + if ((mcu_spi_mosi_list[j].pin != mosi) // only SCK and MOSI need the same index || (mcu_spi_sck_list[i].bank_idx != mcu_spi_mosi_list[j].bank_idx)) { continue; } @@ -153,7 +153,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, break; } } else { - //throw an error immediately + // throw an error immediately mp_raise_ValueError(translate("Must provide MISO or MOSI pin")); } } @@ -231,7 +231,7 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { } bool common_hal_busio_spi_configure(busio_spi_obj_t *self, - uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { + uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { LPSPI_Enable(self->spi, false); uint32_t tcrPrescaleValue; @@ -278,7 +278,7 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) { } bool common_hal_busio_spi_write(busio_spi_obj_t *self, - const uint8_t *data, size_t len) { + const uint8_t *data, size_t len) { if (len == 0) { return true; } @@ -287,7 +287,7 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, } lpspi_transfer_t xfer = { 0 }; - xfer.txData = (uint8_t*)data; + xfer.txData = (uint8_t *)data; xfer.dataSize = len; xfer.configFlags = kLPSPI_MasterPcs0; @@ -297,14 +297,15 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, status = LPSPI_MasterTransferBlocking(self->spi, &xfer); } while (status == kStatus_LPSPI_Busy && --retries > 0); - if (status != kStatus_Success) + if (status != kStatus_Success) { printf("%s: status %ld\r\n", __func__, status); + } - return (status == kStatus_Success); + return status == kStatus_Success; } bool common_hal_busio_spi_read(busio_spi_obj_t *self, - uint8_t *data, size_t len, uint8_t write_value) { + uint8_t *data, size_t len, uint8_t write_value) { if (len == 0) { return true; } @@ -324,10 +325,11 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self, status = LPSPI_MasterTransferBlocking(self->spi, &xfer); } while (status == kStatus_LPSPI_Busy && --retries > 0); - if (status != kStatus_Success) + if (status != kStatus_Success) { printf("%s: status %ld\r\n", __func__, status); + } - return (status == kStatus_Success); + return status == kStatus_Success; } bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_out, uint8_t *data_in, size_t len) { @@ -351,20 +353,21 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou status = LPSPI_MasterTransferBlocking(self->spi, &xfer); } while (status == kStatus_LPSPI_Busy && --retries > 0); - if (status != kStatus_Success) + if (status != kStatus_Success) { printf("%s: status %ld\r\n", __func__, status); + } - return (status == kStatus_Success); + return status == kStatus_Success; } -uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) { +uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) { return self->baudrate; } -uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) { - return ((self->spi->TCR & LPSPI_TCR_CPHA_MASK) == LPSPI_TCR_CPHA_MASK); +uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) { + return (self->spi->TCR & LPSPI_TCR_CPHA_MASK) == LPSPI_TCR_CPHA_MASK; } -uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) { - return ((self->spi->TCR & LPSPI_TCR_CPOL_MASK) == LPSPI_TCR_CPOL_MASK); +uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) { + return (self->spi->TCR & LPSPI_TCR_CPOL_MASK) == LPSPI_TCR_CPOL_MASK; } diff --git a/ports/mimxrt10xx/common-hal/busio/UART.c b/ports/mimxrt10xx/common-hal/busio/UART.c index 503da14c2..29f9ea0b2 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.c +++ b/ports/mimxrt10xx/common-hal/busio/UART.c @@ -40,7 +40,7 @@ #include "fsl_lpuart.h" -//arrays use 0 based numbering: UART1 is stored at index 0 +// arrays use 0 based numbering: UART1 is stored at index 0 #define MAX_UART 8 STATIC bool reserved_uart[MAX_UART]; @@ -56,18 +56,17 @@ static void config_periph_pin(const mcu_periph_obj_t *periph) { IOMUXC_SetPinConfig(0, 0, 0, 0, periph->pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(0) - | IOMUXC_SW_PAD_CTL_PAD_PUS(1) - | IOMUXC_SW_PAD_CTL_PAD_PUE(1) - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(0) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(1) - | IOMUXC_SW_PAD_CTL_PAD_DSE(6) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS(1) + | IOMUXC_SW_PAD_CTL_PAD_PUE(1) + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(0) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(1) + | IOMUXC_SW_PAD_CTL_PAD_DSE(6) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } -void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *user_data) -{ - busio_uart_obj_t *self = (busio_uart_obj_t*)user_data; +void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *user_data) { + busio_uart_obj_t *self = (busio_uart_obj_t *)user_data; if (status == kStatus_LPUART_RxIdle) { self->rx_ongoing = false; @@ -75,19 +74,19 @@ void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t st } void uart_reset(void) { - for(uint i = 0; i < MP_ARRAY_SIZE(mcu_uart_banks); i++) { + for (uint i = 0; i < MP_ARRAY_SIZE(mcu_uart_banks); i++) { reserved_uart[i] = false; LPUART_Deinit(mcu_uart_banks[i]); } } void common_hal_busio_uart_construct(busio_uart_obj_t *self, - const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx, - const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts, - const mcu_pin_obj_t * rs485_dir, bool rs485_invert, - uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, - mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer, - bool sigint_enabled) { + const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx, + const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts, + const mcu_pin_obj_t *rs485_dir, bool rs485_invert, + uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, + mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer, + bool sigint_enabled) { self->baudrate = baudrate; self->character_bits = bits; @@ -169,8 +168,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } // For IMXRT the RTS pin is used for RS485 direction rts = rs485_dir; - } - else { + } else { if (rs485_invert) { mp_raise_ValueError(translate("RS485 inversion specified when not in RS485 mode")); } @@ -181,7 +179,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, const uint32_t cts_count = MP_ARRAY_SIZE(mcu_uart_cts_list); if (rts != NULL) { - for (uint32_t i=0; i < rts_count; ++i) { + for (uint32_t i = 0; i < rts_count; ++i) { if (mcu_uart_rts_list[i].bank_idx == self->rx->bank_idx) { if (mcu_uart_rts_list[i].pin == rts) { self->rts = &mcu_uart_rts_list[i]; @@ -189,13 +187,13 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } } } - if (self->rts == NULL){ + if (self->rts == NULL) { mp_raise_ValueError(translate("Selected RTS pin not valid")); } } if (cts != NULL) { - for (uint32_t i=0; i < cts_count; ++i) { + for (uint32_t i = 0; i < cts_count; ++i) { if (mcu_uart_cts_list[i].bank_idx == self->rx->bank_idx) { if (mcu_uart_cts_list[i].pin == cts) { self->cts = &mcu_uart_cts_list[i]; @@ -203,7 +201,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } } } - if (self->cts == NULL){ + if (self->cts == NULL) { mp_raise_ValueError(translate("Selected CTS pin not valid")); } } @@ -326,7 +324,7 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t uint64_t start_ticks = supervisor_ticks_ms64(); // Wait for all bytes received or timeout - while (self->rx_ongoing && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms) ) { + while (self->rx_ongoing && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms)) { RUN_BACKGROUND_TASKS; // Allow user to break out of a timeout with a KeyboardInterrupt. @@ -372,7 +370,7 @@ void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrat } mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) { - return (mp_float_t) (self->timeout_ms / 1000.0f); + return (mp_float_t)(self->timeout_ms / 1000.0f); } void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) { diff --git a/ports/mimxrt10xx/common-hal/busio/UART.h b/ports/mimxrt10xx/common-hal/busio/UART.h index 94a5fb02c..604fef2cf 100644 --- a/ports/mimxrt10xx/common-hal/busio/UART.h +++ b/ports/mimxrt10xx/common-hal/busio/UART.h @@ -40,7 +40,7 @@ typedef struct { mp_obj_base_t base; LPUART_Type *uart; lpuart_handle_t handle; - uint8_t* ringbuf; + uint8_t *ringbuf; bool rx_ongoing; uint32_t baudrate; uint8_t character_bits; diff --git a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c index e4eda9f4f..445ffa91c 100644 --- a/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c +++ b/ports/mimxrt10xx/common-hal/digitalio/DigitalInOut.c @@ -40,21 +40,20 @@ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5 5U -void pin_config(const mcu_pin_obj_t *pin, bool open_drain, digitalio_pull_t pull) -{ +void pin_config(const mcu_pin_obj_t *pin, bool open_drain, digitalio_pull_t pull) { IOMUXC_SetPinConfig(0, 0, 0, 0, pin->cfg_reg, IOMUXC_SW_PAD_CTL_PAD_HYS(1) - | IOMUXC_SW_PAD_CTL_PAD_PUS((pull == PULL_UP) ? 2 : 0) - | IOMUXC_SW_PAD_CTL_PAD_PUE(pull != PULL_NONE) - | IOMUXC_SW_PAD_CTL_PAD_PKE(1) - | IOMUXC_SW_PAD_CTL_PAD_ODE(open_drain) - | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) - | IOMUXC_SW_PAD_CTL_PAD_DSE(1) - | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); + | IOMUXC_SW_PAD_CTL_PAD_PUS((pull == PULL_UP) ? 2 : 0) + | IOMUXC_SW_PAD_CTL_PAD_PUE(pull != PULL_NONE) + | IOMUXC_SW_PAD_CTL_PAD_PKE(1) + | IOMUXC_SW_PAD_CTL_PAD_ODE(open_drain) + | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) + | IOMUXC_SW_PAD_CTL_PAD_DSE(1) + | IOMUXC_SW_PAD_CTL_PAD_SRE(0)); } digitalinout_result_t common_hal_digitalio_digitalinout_construct( - digitalio_digitalinout_obj_t* self, const mcu_pin_obj_t* pin) { + digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { claim_pin(pin); self->pin = pin; self->output = false; @@ -73,15 +72,15 @@ digitalinout_result_t common_hal_digitalio_digitalinout_construct( } void common_hal_digitalio_digitalinout_never_reset( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { common_hal_never_reset_pin(self->pin); } -bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t* self) { +bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t *self) { return self->pin == NULL; } -void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t* self) { +void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self) { if (common_hal_digitalio_digitalinout_deinited(self)) { return; } @@ -90,7 +89,7 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t* self } void common_hal_digitalio_digitalinout_switch_to_input( - digitalio_digitalinout_obj_t* self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { self->output = false; // This also sets direction to input. @@ -98,8 +97,8 @@ void common_hal_digitalio_digitalinout_switch_to_input( } digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( - digitalio_digitalinout_obj_t* self, bool value, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, bool value, + digitalio_drive_mode_t drive_mode) { self->output = true; self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN; self->pull = PULL_NONE; @@ -112,23 +111,23 @@ digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { return self->output ? DIRECTION_OUTPUT : DIRECTION_INPUT; } void common_hal_digitalio_digitalinout_set_value( - digitalio_digitalinout_obj_t* self, bool value) { + digitalio_digitalinout_obj_t *self, bool value) { GPIO_PinWrite(self->pin->gpio, self->pin->number, value); } bool common_hal_digitalio_digitalinout_get_value( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { return GPIO_PinRead(self->pin->gpio, self->pin->number); } digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( - digitalio_digitalinout_obj_t* self, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, + digitalio_drive_mode_t drive_mode) { bool value = common_hal_digitalio_digitalinout_get_value(self); self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN; @@ -143,7 +142,7 @@ digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { if (self->open_drain) { return DRIVE_MODE_OPEN_DRAIN; } else { @@ -152,7 +151,7 @@ digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( } void common_hal_digitalio_digitalinout_set_pull( - digitalio_digitalinout_obj_t* self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { self->pull = pull; pin_config(self->pin, self->open_drain, self->pull); @@ -162,7 +161,7 @@ void common_hal_digitalio_digitalinout_set_pull( } digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { if (self->output) { mp_raise_AttributeError(translate("Cannot get pull while in output mode")); return PULL_NONE; diff --git a/ports/mimxrt10xx/common-hal/displayio/ParallelBus.c b/ports/mimxrt10xx/common-hal/displayio/ParallelBus.c index 0fdf4413b..6a5a978cf 100644 --- a/ports/mimxrt10xx/common-hal/displayio/ParallelBus.c +++ b/ports/mimxrt10xx/common-hal/displayio/ParallelBus.c @@ -33,19 +33,19 @@ #include "shared-bindings/digitalio/DigitalInOut.h" #include "shared-bindings/microcontroller/__init__.h" -void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* self, - const mcu_pin_obj_t* data0, const mcu_pin_obj_t* command, const mcu_pin_obj_t* chip_select, - const mcu_pin_obj_t* write, const mcu_pin_obj_t* read, const mcu_pin_obj_t* reset) { +void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t *self, + const mcu_pin_obj_t *data0, const mcu_pin_obj_t *command, const mcu_pin_obj_t *chip_select, + const mcu_pin_obj_t *write, const mcu_pin_obj_t *read, const mcu_pin_obj_t *reset) { mp_raise_NotImplementedError(translate("ParallelBus not yet supported")); } -void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) { +void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t *self) { } bool common_hal_displayio_parallelbus_reset(mp_obj_t obj) { - return false; + return false; } bool common_hal_displayio_parallelbus_bus_free(mp_obj_t obj) { diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Pin.c b/ports/mimxrt10xx/common-hal/microcontroller/Pin.c index 50970f8e2..b55ab6e86 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Pin.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/Pin.c @@ -49,9 +49,9 @@ void reset_all_pins(void) { claimed_pins[i] = never_reset_pins[i]; } for (uint8_t i = 0; i < IOMUXC_SW_PAD_CTL_PAD_COUNT; i++) { - if(!never_reset_pins[i]) { - IOMUXC->SW_MUX_CTL_PAD[i] = ((mcu_pin_obj_t*)(mcu_pin_globals.map.table[i].value))->mux_reset; - IOMUXC->SW_PAD_CTL_PAD[i] = ((mcu_pin_obj_t*)(mcu_pin_globals.map.table[i].value))->pad_reset; + if (!never_reset_pins[i]) { + IOMUXC->SW_MUX_CTL_PAD[i] = ((mcu_pin_obj_t *)(mcu_pin_globals.map.table[i].value))->mux_reset; + IOMUXC->SW_PAD_CTL_PAD[i] = ((mcu_pin_obj_t *)(mcu_pin_globals.map.table[i].value))->pad_reset; } } @@ -66,14 +66,14 @@ void reset_all_pins(void) { // Since i.MX pins need extra register and reset information to reset properly, // resetting pins by number alone has been removed. -void common_hal_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_reset_pin(const mcu_pin_obj_t *pin) { if (pin == NULL) { return; } never_reset_pins[pin->mux_idx] = false; claimed_pins[pin->mux_idx] = false; - *(uint32_t*)pin->mux_reg = pin->mux_reset; - *(uint32_t*)pin->cfg_reg = pin->pad_reset; + *(uint32_t *)pin->mux_reg = pin->mux_reset; + *(uint32_t *)pin->cfg_reg = pin->pad_reset; #ifdef MICROPY_HW_NEOPIXEL if (pin == MICROPY_HW_NEOPIXEL) { @@ -95,11 +95,11 @@ void common_hal_reset_pin(const mcu_pin_obj_t* pin) { #endif } -void common_hal_never_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_never_reset_pin(const mcu_pin_obj_t *pin) { never_reset_pins[pin->mux_idx] = true; } -bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t* pin) { +bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { #ifdef MICROPY_HW_NEOPIXEL if (pin == MICROPY_HW_NEOPIXEL) { return !neopixel_in_use; @@ -117,11 +117,11 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t* pin) { return !claimed_pins[pin->mux_idx]; } -uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t* pin) { +uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t *pin) { return pin->mux_idx; // returns IOMUXC to align with pin table } -void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { +void common_hal_mcu_pin_claim(const mcu_pin_obj_t *pin) { claimed_pins[pin->mux_idx] = true; #ifdef MICROPY_HW_NEOPIXEL @@ -139,10 +139,10 @@ void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { #endif } -void claim_pin(const mcu_pin_obj_t* pin) { +void claim_pin(const mcu_pin_obj_t *pin) { common_hal_mcu_pin_claim(pin); } void common_hal_mcu_pin_reset_number(uint8_t pin_no) { - common_hal_reset_pin((mcu_pin_obj_t*)(mcu_pin_globals.map.table[pin_no].value)); + common_hal_reset_pin((mcu_pin_obj_t *)(mcu_pin_globals.map.table[pin_no].value)); } diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Pin.h b/ports/mimxrt10xx/common-hal/microcontroller/Pin.h index 2f1aaa895..fde7fc8b8 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Pin.h +++ b/ports/mimxrt10xx/common-hal/microcontroller/Pin.h @@ -41,6 +41,6 @@ extern bool apa102_mosi_in_use; #endif void reset_all_pins(void); -void claim_pin(const mcu_pin_obj_t* pin); +void claim_pin(const mcu_pin_obj_t *pin); #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_MICROCONTROLLER_PIN_H diff --git a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c index efbde35d2..b097133d5 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/Processor.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/Processor.c @@ -65,7 +65,7 @@ void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { for (int i = 0; i < 4; ++i) { uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1); for (int j = 0; j < 4; j++) { - raw_id[i*4+j] = wr & 0xff; + raw_id[i * 4 + j] = wr & 0xff; wr >>= 8; } } diff --git a/ports/mimxrt10xx/common-hal/microcontroller/__init__.c b/ports/mimxrt10xx/common-hal/microcontroller/__init__.c index 6a8537e2d..2daf108af 100644 --- a/ports/mimxrt10xx/common-hal/microcontroller/__init__.c +++ b/ports/mimxrt10xx/common-hal/microcontroller/__init__.c @@ -24,7 +24,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -//TODO +// TODO #include "py/mphal.h" #include "py/obj.h" #include "py/runtime.h" @@ -102,14 +102,14 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .type = &nvm_bytearray_type, }, .len = CIRCUITPY_INTERNAL_NVM_SIZE, - .start_address = (uint8_t*) (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE) + .start_address = (uint8_t *)(FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE) }; #endif // This maps MCU pin names to pin objects. // NOTE: for all i.MX chips, order MUST match _iomuxc_sw_mux_ctl_pad enum STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = { -#ifdef MIMXRT1011_SERIES + #ifdef MIMXRT1011_SERIES { MP_ROM_QSTR(MP_QSTR_GPIO_AD_14), MP_ROM_PTR(&pin_GPIO_AD_14) }, { MP_ROM_QSTR(MP_QSTR_GPIO_AD_13), MP_ROM_PTR(&pin_GPIO_AD_13) }, { MP_ROM_QSTR(MP_QSTR_GPIO_AD_12), MP_ROM_PTR(&pin_GPIO_AD_12) }, @@ -125,7 +125,7 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_GPIO_AD_02), MP_ROM_PTR(&pin_GPIO_AD_02) }, { MP_ROM_QSTR(MP_QSTR_GPIO_AD_01), MP_ROM_PTR(&pin_GPIO_AD_01) }, { MP_ROM_QSTR(MP_QSTR_GPIO_AD_00), MP_ROM_PTR(&pin_GPIO_AD_00) }, - { MP_ROM_QSTR(MP_QSTR_GPIO_SD_14), MP_ROM_PTR(&pin_GPIO_SD_14) }, //spooky ghost pin + { MP_ROM_QSTR(MP_QSTR_GPIO_SD_14), MP_ROM_PTR(&pin_GPIO_SD_14) }, // spooky ghost pin { MP_ROM_QSTR(MP_QSTR_GPIO_SD_13), MP_ROM_PTR(&pin_GPIO_SD_13) }, { MP_ROM_QSTR(MP_QSTR_GPIO_SD_12), MP_ROM_PTR(&pin_GPIO_SD_12) }, { MP_ROM_QSTR(MP_QSTR_GPIO_SD_11), MP_ROM_PTR(&pin_GPIO_SD_11) }, @@ -154,7 +154,7 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_GPIO_02), MP_ROM_PTR(&pin_GPIO_02) }, { MP_ROM_QSTR(MP_QSTR_GPIO_01), MP_ROM_PTR(&pin_GPIO_01) }, { MP_ROM_QSTR(MP_QSTR_GPIO_00), MP_ROM_PTR(&pin_GPIO_00) }, -#else + #else { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_00), MP_ROM_PTR(&pin_GPIO_EMC_00) }, { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_01), MP_ROM_PTR(&pin_GPIO_EMC_01) }, { MP_ROM_QSTR(MP_QSTR_GPIO_EMC_02), MP_ROM_PTR(&pin_GPIO_EMC_02) }, @@ -284,6 +284,6 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_09), MP_ROM_PTR(&pin_GPIO_SD_B1_09) }, { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_10), MP_ROM_PTR(&pin_GPIO_SD_B1_10) }, { MP_ROM_QSTR(MP_QSTR_GPIO_SD_B1_11), MP_ROM_PTR(&pin_GPIO_SD_B1_11) }, -#endif + #endif }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_global_dict_table); diff --git a/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c b/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c index b86077015..88d045306 100644 --- a/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c +++ b/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c @@ -33,7 +33,7 @@ uint64_t next_start_raw_ticks = 0; -//sysclock divisors +// sysclock divisors #define MAGIC_800_INT 900000 // ~1.11 us -> 1.2 field #define MAGIC_800_T0H 2800000 // ~0.36 us -> 0.44 field #define MAGIC_800_T1H 1350000 // ~0.74 us -> 0.84 field @@ -41,15 +41,15 @@ uint64_t next_start_raw_ticks = 0; #pragma GCC push_options #pragma GCC optimize ("Os") -void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, - uint32_t numBytes) { +void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t * digitalinout, uint8_t *pixels, + uint32_t numBytes) { uint8_t *p = pixels, *end = p + numBytes, pix = *p++, mask = 0x80; uint32_t start = 0; uint32_t cyc = 0; - //assumes 800_000Hz frequency - //Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us - //TODO: try to get dynamic weighting working again + // assumes 800_000Hz frequency + // Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us + // TODO: try to get dynamic weighting working again const uint32_t sys_freq = SystemCoreClock; const uint32_t interval = (sys_freq / MAGIC_800_INT); const uint32_t t0 = (sys_freq / MAGIC_800_T0H); @@ -57,7 +57,8 @@ void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t // Wait to make sure we don't append onto the last transmission. This should only be a tick or // two. - while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {} + while (port_get_raw_ticks(NULL) < next_start_raw_ticks) { + } GPIO_Type *gpio = digitalinout->pin->gpio; const uint32_t pin = digitalinout->pin->number; @@ -68,16 +69,22 @@ void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; DWT->CYCCNT = 0; - for(;;) { + for (;;) { cyc = (pix & mask) ? t1 : t0; start = DWT->CYCCNT; gpio->DR |= (1U << pin); - while((DWT->CYCCNT - start) < cyc); + while ((DWT->CYCCNT - start) < cyc) { + ; + } gpio->DR &= ~(1U << pin); - while((DWT->CYCCNT - start) < interval); - if(!(mask >>= 1)) { - if(p >= end) break; - pix = *p++; + while ((DWT->CYCCNT - start) < interval) { + ; + } + if (!(mask >>= 1)) { + if (p >= end) { + break; + } + pix = *p++; mask = 0x80; } } diff --git a/ports/mimxrt10xx/common-hal/os/__init__.c b/ports/mimxrt10xx/common-hal/os/__init__.c index e84beb526..dd1d186f1 100644 --- a/ports/mimxrt10xx/common-hal/os/__init__.c +++ b/ports/mimxrt10xx/common-hal/os/__init__.c @@ -52,13 +52,13 @@ STATIC MP_DEFINE_ATTRTUPLE( (mp_obj_t)&os_uname_info_release_obj, (mp_obj_t)&os_uname_info_version_obj, (mp_obj_t)&os_uname_info_machine_obj -); + ); mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; } -bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) { +bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { trng_config_t trngConfig; TRNG_GetDefaultConfig(&trngConfig); diff --git a/ports/mimxrt10xx/common-hal/pulseio/PulseIn.c b/ports/mimxrt10xx/common-hal/pulseio/PulseIn.c index cea11a4b9..c1f7ce20b 100644 --- a/ports/mimxrt10xx/common-hal/pulseio/PulseIn.c +++ b/ports/mimxrt10xx/common-hal/pulseio/PulseIn.c @@ -39,7 +39,7 @@ #include "supervisor/shared/translate.h" // TODO -//static void pulsein_set_config(pulseio_pulsein_obj_t* self, bool first_edge) { +// static void pulsein_set_config(pulseio_pulsein_obj_t* self, bool first_edge) { // uint32_t sense_setting; // if (!first_edge) { // sense_setting = EIC_CONFIG_SENSE0_BOTH_Val; @@ -52,9 +52,9 @@ // } // set_eic_handler(self->channel, EIC_HANDLER_PULSEIN); // turn_on_eic_channel(self->channel, sense_setting); -//} +// } -//void pulsein_interrupt_handler(uint8_t channel) { +// void pulsein_interrupt_handler(uint8_t channel) { // // Grab the current time first. // uint32_t current_us; // uint64_t current_ms; @@ -99,10 +99,10 @@ // } // self->last_ms = current_ms; // self->last_us = current_us; -//} +// } -void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, - const mcu_pin_obj_t* pin, uint16_t maxlen, bool idle_state) { +void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t *self, + const mcu_pin_obj_t *pin, uint16_t maxlen, bool idle_state) { // if (!pin->has_extint) { // mp_raise_RuntimeError(translate("No hardware support on pin")); // } @@ -142,12 +142,12 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, // pulsein_set_config(self, true); } -bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t *self) { // return self->pin == NO_PIN; return true; } -void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t *self) { // if (common_hal_pulseio_pulsein_deinited(self)) { // return; // } @@ -157,13 +157,13 @@ void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { // self->pin = NO_PIN; } -void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t *self) { // uint32_t mask = 1 << self->channel; // EIC->INTENCLR.reg = mask << EIC_INTENSET_EXTINT_Pos; } -void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, - uint16_t trigger_duration) { +void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t *self, + uint16_t trigger_duration) { // // Make sure we're paused. // common_hal_pulseio_pulsein_pause(self); // @@ -192,14 +192,14 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, // pulsein_set_config(self, true); } -void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t *self) { // common_hal_mcu_disable_interrupts(); // self->start = 0; // self->len = 0; // common_hal_mcu_enable_interrupts(); } -uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t *self) { // if (self->len == 0) { // mp_raise_IndexError_varg(translate("pop from empty %q"), MP_QSTR_PulseIn); // } @@ -213,24 +213,24 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { return 0; } -uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t *self) { // return self->maxlen; return 0; } -uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t *self) { // return self->len; return 0; } -bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t *self) { // uint32_t mask = 1 << self->channel; // return (EIC->INTENSET.reg & (mask << EIC_INTENSET_EXTINT_Pos)) == 0; return true; } -uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, - int16_t index) { +uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t *self, + int16_t index) { // common_hal_mcu_disable_interrupts(); // if (index < 0) { // index += self->len; diff --git a/ports/mimxrt10xx/common-hal/pulseio/PulseIn.h b/ports/mimxrt10xx/common-hal/pulseio/PulseIn.h index af742f319..cce4f58ca 100644 --- a/ports/mimxrt10xx/common-hal/pulseio/PulseIn.h +++ b/ports/mimxrt10xx/common-hal/pulseio/PulseIn.h @@ -48,8 +48,8 @@ typedef struct { // volatile bool errored_too_fast; } pulseio_pulsein_obj_t; -//void pulsein_reset(void); +// void pulsein_reset(void); // -//void pulsein_interrupt_handler(uint8_t channel); +// void pulsein_interrupt_handler(uint8_t channel); #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_PULSEIO_PULSEIN_H diff --git a/ports/mimxrt10xx/common-hal/pulseio/PulseOut.c b/ports/mimxrt10xx/common-hal/pulseio/PulseOut.c index d3a1a897f..b38f6f093 100644 --- a/ports/mimxrt10xx/common-hal/pulseio/PulseOut.c +++ b/ports/mimxrt10xx/common-hal/pulseio/PulseOut.c @@ -39,25 +39,25 @@ // This timer is shared amongst all PulseOut objects under the assumption that // the code is single threaded. -//static uint8_t refcount = 0; +// static uint8_t refcount = 0; // -//static uint8_t pulseout_tc_index = 0xff; +// static uint8_t pulseout_tc_index = 0xff; // -//static __IO PORT_PINCFG_Type *active_pincfg = NULL; -//static uint16_t *pulse_buffer = NULL; -//static volatile uint16_t pulse_index = 0; -//static uint16_t pulse_length; -//static volatile uint32_t current_compare = 0; +// static __IO PORT_PINCFG_Type *active_pincfg = NULL; +// static uint16_t *pulse_buffer = NULL; +// static volatile uint16_t pulse_index = 0; +// static uint16_t pulse_length; +// static volatile uint32_t current_compare = 0; // -//static void turn_on(__IO PORT_PINCFG_Type * pincfg) { +// static void turn_on(__IO PORT_PINCFG_Type * pincfg) { // pincfg->reg = PORT_PINCFG_PMUXEN; -//} +// } // -//static void turn_off(__IO PORT_PINCFG_Type * pincfg) { +// static void turn_off(__IO PORT_PINCFG_Type * pincfg) { // pincfg->reg = PORT_PINCFG_RESETVALUE; -//} +// } // -//void pulse_finish(void) { +// void pulse_finish(void) { // pulse_index++; // // if (active_pincfg == NULL) { @@ -74,7 +74,7 @@ // if (pulse_index % 2 == 0) { // turn_on(active_pincfg); // } -//} +// } void pulseout_interrupt_handler(uint8_t index) { // if (index != pulseout_tc_index) return; @@ -93,11 +93,11 @@ void pulseout_reset() { // active_pincfg = NULL; } -void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, - const pwmio_pwmout_obj_t* carrier, - const mcu_pin_obj_t* pin, - uint32_t frequency, - uint16_t duty_cycle) { +void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self, + const pwmio_pwmout_obj_t *carrier, + const mcu_pin_obj_t *pin, + uint32_t frequency, + uint16_t duty_cycle) { // if (refcount == 0) { // // Find a spare timer. // Tc *tc = NULL; @@ -155,12 +155,12 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, // turn_off(self->pincfg); } -bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t* self) { +bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t *self) { // return self->pin == NO_PIN; return false; } -void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { +void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t *self) { // if (common_hal_pulseio_pulseout_deinited(self)) { // return; // } @@ -177,7 +177,7 @@ void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { // self->pin = NO_PIN; } -void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pulses, uint16_t length) { +void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pulses, uint16_t length) { // if (active_pincfg != NULL) { // mp_raise_RuntimeError(translate("Another send is already active")); // } diff --git a/ports/mimxrt10xx/common-hal/pulseio/PulseOut.h b/ports/mimxrt10xx/common-hal/pulseio/PulseOut.h index ee70ac17e..da022b738 100644 --- a/ports/mimxrt10xx/common-hal/pulseio/PulseOut.h +++ b/ports/mimxrt10xx/common-hal/pulseio/PulseOut.h @@ -40,6 +40,6 @@ typedef struct { } pulseio_pulseout_obj_t; void pulseout_reset(void); -//void pulseout_interrupt_handler(uint8_t index); +// void pulseout_interrupt_handler(uint8_t index); #endif // MICROPY_INCLUDED_MIMXRT10XX_COMMON_HAL_PULSEIO_PULSEOUT_H diff --git a/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c b/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c index dd464ef84..28ea81fa2 100644 --- a/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c +++ b/ports/mimxrt10xx/common-hal/pwmio/PWMOut.c @@ -41,28 +41,28 @@ #include <stdio.h> // TODO -//#include "samd/pins.h" +// #include "samd/pins.h" -//#undef ENABLE +// #undef ENABLE // -//# define _TCC_SIZE(unused, n) TCC ## n ## _SIZE, -//# define TCC_SIZES { REPEAT_MACRO(_TCC_SIZE, 0, TCC_INST_NUM) } +// # define _TCC_SIZE(unused, n) TCC ## n ## _SIZE, +// # define TCC_SIZES { REPEAT_MACRO(_TCC_SIZE, 0, TCC_INST_NUM) } // -//static uint32_t tcc_periods[TCC_INST_NUM]; -//static uint32_t tc_periods[TC_INST_NUM]; +// static uint32_t tcc_periods[TCC_INST_NUM]; +// static uint32_t tc_periods[TC_INST_NUM]; // -//uint32_t target_tcc_frequencies[TCC_INST_NUM]; -//uint8_t tcc_refcount[TCC_INST_NUM]; +// uint32_t target_tcc_frequencies[TCC_INST_NUM]; +// uint8_t tcc_refcount[TCC_INST_NUM]; // //// This bitmask keeps track of which channels of a TCC are currently claimed. -//#ifdef SAMD21 -//uint8_t tcc_channels[3]; // Set by pwmout_reset() to {0xf0, 0xfc, 0xfc} initially. -//#endif -//#ifdef SAMD51 -//uint8_t tcc_channels[5]; // Set by pwmout_reset() to {0xc0, 0xf0, 0xf8, 0xfc, 0xfc} initially. -//#endif +// #ifdef SAMD21 +// uint8_t tcc_channels[3]; // Set by pwmout_reset() to {0xf0, 0xfc, 0xfc} initially. +// #endif +// #ifdef SAMD51 +// uint8_t tcc_channels[5]; // Set by pwmout_reset() to {0xc0, 0xf0, 0xf8, 0xfc, 0xfc} initially. +// #endif // -//static uint8_t never_reset_tc_or_tcc[TC_INST_NUM + TCC_INST_NUM]; +// static uint8_t never_reset_tc_or_tcc[TC_INST_NUM + TCC_INST_NUM]; void common_hal_pwmio_pwmout_never_reset(pwmio_pwmout_obj_t *self) { // if (self->timer->is_tc) { @@ -119,33 +119,34 @@ void pwmout_reset(void) { // } } -//static uint8_t tcc_channel(const pin_timer_t* t) { +// static uint8_t tcc_channel(const pin_timer_t* t) { // // For the SAMD51 this hardcodes the use of OTMX == 0x0, the output matrix mapping, which uses // // SAMD21-style modulo mapping. // return t->wave_output % tcc_cc_num[t->index]; -//} +// } -//bool channel_ok(const pin_timer_t* t) { +// bool channel_ok(const pin_timer_t* t) { // uint8_t channel_bit = 1 << tcc_channel(t); // return (!t->is_tc && ((tcc_channels[t->index] & channel_bit) == 0)) || // t->is_tc; -//} +// } #define PWM_SRC_CLK_FREQ CLOCK_GetFreq(kCLOCK_IpgClk) pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, - const mcu_pin_obj_t *pin, - uint16_t duty, - uint32_t frequency, - bool variable_frequency) { + const mcu_pin_obj_t *pin, + uint16_t duty, + uint32_t frequency, + bool variable_frequency) { self->pin = pin; self->variable_frequency = variable_frequency; const uint32_t pwm_count = sizeof(mcu_pwm_list) / sizeof(mcu_pwm_obj_t); for (uint32_t i = 0; i < pwm_count; ++i) { - if (mcu_pwm_list[i].pin != pin) + if (mcu_pwm_list[i].pin != pin) { continue; + } printf("pwm: 0x%p, sum %d, chan %d, mux %d\r\n", mcu_pwm_list[i].pwm, mcu_pwm_list[i].submodule, mcu_pwm_list[i].channel, mcu_pwm_list[i].mux_mode); @@ -161,7 +162,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, CLOCK_SetDiv(kCLOCK_AhbDiv, 0x2); /* Set AHB PODF to 2, divide by 3 */ CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ -//TODO re-enable +// TODO re-enable // IOMUXC_SetPinMux( // IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A, /* GPIO_02 is configured as FLEXPWM1_PWM0_A */ // 0U); /* Software Input On Field: Input Path is determined by functionality */ @@ -195,7 +196,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, */ PWM_GetDefaultConfig(&pwmConfig); - //pwmConfig.reloadLogic = kPWM_ReloadPwmFullCycle; + // pwmConfig.reloadLogic = kPWM_ReloadPwmFullCycle; pwmConfig.enableDebugMode = true; if (PWM_Init(PWM1, self->pwm->submodule, &pwmConfig) == kStatus_Fail) { @@ -208,10 +209,10 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, /* Set deadtime count, we set this to about 650ns */ uint16_t deadTimeVal = ((uint64_t)PWM_SRC_CLK_FREQ * 650) / 1000000000; - pwmSignal.pwmChannel = self->pwm->channel; - pwmSignal.level = kPWM_HighTrue; + pwmSignal.pwmChannel = self->pwm->channel; + pwmSignal.level = kPWM_HighTrue; pwmSignal.dutyCyclePercent = frequency / 2; /* 1 percent dutycycle */ - pwmSignal.deadtimeValue = deadTimeVal; + pwmSignal.deadtimeValue = deadTimeVal; PWM_SetupPwm(PWM1, self->pwm->submodule, &pwmSignal, 1, kPWM_SignedCenterAligned, frequency, PWM_SRC_CLK_FREQ); @@ -364,11 +365,11 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, return PWMOUT_OK; } -bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) { return self->pin == NULL; } -void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { +void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) { if (common_hal_pwmio_pwmout_deinited(self)) { return; } @@ -433,7 +434,7 @@ void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t d // } } -uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) { +uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) { return 0; // const pin_timer_t* t = self->timer; // if (t->is_tc) { @@ -471,8 +472,8 @@ uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) { // } } -void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, - uint32_t frequency) { +void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self, + uint32_t frequency) { // if (frequency == 0 || frequency > 6000000) { // mp_raise_ValueError(translate("Invalid PWM frequency")); // } @@ -530,7 +531,7 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, // common_hal_pwmio_pwmout_set_duty_cycle(self, old_duty); } -uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) { +uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) { // uint32_t system_clock = common_hal_mcu_processor_get_frequency(); // const pin_timer_t* t = self->timer; // uint8_t divisor; @@ -546,6 +547,6 @@ uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) { return 0; } -bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) { return self->variable_frequency; } diff --git a/ports/mimxrt10xx/common-hal/rtc/RTC.c b/ports/mimxrt10xx/common-hal/rtc/RTC.c index 6940a1817..aabe2b09f 100644 --- a/ports/mimxrt10xx/common-hal/rtc/RTC.c +++ b/ports/mimxrt10xx/common-hal/rtc/RTC.c @@ -48,19 +48,19 @@ void common_hal_rtc_get_time(timeutils_struct_time_t *tm) { SNVS_HP_RTC_GetDatetime(SNVS, &rtcDate); tm->tm_year = rtcDate.year; - tm->tm_mon = rtcDate.month; + tm->tm_mon = rtcDate.month; tm->tm_mday = rtcDate.day; tm->tm_hour = rtcDate.hour; - tm->tm_min = rtcDate.minute; - tm->tm_sec = rtcDate.second; + tm->tm_min = rtcDate.minute; + tm->tm_sec = rtcDate.second; } void common_hal_rtc_set_time(timeutils_struct_time_t *tm) { snvs_hp_rtc_datetime_t rtcDate; - rtcDate.year = tm->tm_year; - rtcDate.month = tm->tm_mon; - rtcDate.day = tm->tm_mday; - rtcDate.hour = tm->tm_hour; + rtcDate.year = tm->tm_year; + rtcDate.month = tm->tm_mon; + rtcDate.day = tm->tm_mday; + rtcDate.hour = tm->tm_hour; rtcDate.minute = tm->tm_min; rtcDate.second = tm->tm_sec; diff --git a/ports/mimxrt10xx/common-hal/supervisor/Runtime.c b/ports/mimxrt10xx/common-hal/supervisor/Runtime.c index 974f26cec..f82765178 100755..100644 --- a/ports/mimxrt10xx/common-hal/supervisor/Runtime.c +++ b/ports/mimxrt10xx/common-hal/supervisor/Runtime.c @@ -29,9 +29,9 @@ #include "supervisor/serial.h" bool common_hal_supervisor_runtime_get_serial_connected(void) { - return (bool) serial_connected(); + return (bool)serial_connected(); } bool common_hal_supervisor_runtime_get_serial_bytes_available(void) { - return (bool) serial_bytes_available(); + return (bool)serial_bytes_available(); } diff --git a/ports/mimxrt10xx/fatfs_port.c b/ports/mimxrt10xx/fatfs_port.c index c65a73a42..e6eee2049 100644 --- a/ports/mimxrt10xx/fatfs_port.c +++ b/ports/mimxrt10xx/fatfs_port.c @@ -35,14 +35,14 @@ #endif DWORD get_fattime(void) { -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC timeutils_struct_time_t tm; common_hal_rtc_get_time(&tm); return ((tm.tm_year - 1980) << 25) | (tm.tm_mon << 21) | (tm.tm_mday << 16) | - (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); -#else + (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); + #else return ((2016 - 1980) << 25) | ((9) << 21) | ((1) << 16) | ((16) << 11) | ((43) << 5) | (35 / 2); -#endif + #endif } diff --git a/ports/mimxrt10xx/mpconfigport.h b/ports/mimxrt10xx/mpconfigport.h index 51e0ef9ff..16cc63bc2 100644 --- a/ports/mimxrt10xx/mpconfigport.h +++ b/ports/mimxrt10xx/mpconfigport.h @@ -38,14 +38,14 @@ extern uint8_t _ld_filesystem_end; extern uint8_t _ld_default_stack_size; // 20kiB stack -#define CIRCUITPY_DEFAULT_STACK_SIZE ((uint32_t) &_ld_default_stack_size) +#define CIRCUITPY_DEFAULT_STACK_SIZE ((uint32_t)&_ld_default_stack_size) #define MICROPY_PY_BUILTINS_NOTIMPLEMENTED (0) #define MICROPY_PY_FUNCTION_ATTRS (0) #define MICROPY_PY_REVERSE_SPECIAL_METHODS (1) -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR ((uint32_t) &_ld_filesystem_start) -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE ((uint32_t) (&_ld_filesystem_end - &_ld_filesystem_start)) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR ((uint32_t)&_ld_filesystem_start) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE ((uint32_t)(&_ld_filesystem_end - &_ld_filesystem_start)) #include "py/circuitpy_mpconfig.h" diff --git a/ports/mimxrt10xx/mphalport.c b/ports/mimxrt10xx/mphalport.c index 111e97011..ff7a880ab 100644 --- a/ports/mimxrt10xx/mphalport.c +++ b/ports/mimxrt10xx/mphalport.c @@ -34,11 +34,11 @@ #include "fsl_common.h" void mp_hal_delay_us(mp_uint_t delay) { -#if defined(MIMXRT1011_SERIES) || defined(MIMXRT1021_SERIES) + #if defined(MIMXRT1011_SERIES) || defined(MIMXRT1021_SERIES) SDK_DelayAtLeastUs(delay, SystemCoreClock); -#else + #else SDK_DelayAtLeastUs(delay); -#endif + #endif } void mp_hal_disable_all_interrupts(void) { diff --git a/ports/mimxrt10xx/mphalport.h b/ports/mimxrt10xx/mphalport.h index 4ba3a2476..a67e58e33 100644 --- a/ports/mimxrt10xx/mphalport.h +++ b/ports/mimxrt10xx/mphalport.h @@ -36,7 +36,7 @@ // Global millisecond tick count (driven by SysTick interrupt). static inline mp_uint_t mp_hal_ticks_ms(void) { - return supervisor_ticks_ms32(); + return supervisor_ticks_ms32(); } // Number of bytes in receive buffer extern volatile uint8_t usb_rx_count; diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c index 61888fcaa..e6354386a 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/clocks.c @@ -74,17 +74,17 @@ const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; // Based on the hello_world example in the SDK @@ -111,8 +111,7 @@ void clocks_init(void) { /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c index a994e154d..66dc56e4e 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c index cfab35cea..492d1c6f0 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c index cb9dd34c9..fb4d04b99 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c @@ -87,20 +87,20 @@ const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ + .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; // Based on the hello_world example in the SDK @@ -127,8 +127,7 @@ void clocks_init(void) { /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); @@ -167,7 +166,7 @@ void clocks_init(void) { * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as * well.*/ -#ifndef SKIP_SYSCLK_INIT + #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ @@ -176,7 +175,7 @@ void clocks_init(void) { CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif + #endif /* Disable LPSPI clock gate. */ CLOCK_DisableClock(kCLOCK_Lpspi1); CLOCK_DisableClock(kCLOCK_Lpspi2); @@ -268,10 +267,10 @@ void clocks_init(void) { * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as * well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #ifndef SKIP_SYSCLK_INIT + #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif + #endif /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -282,7 +281,7 @@ void clocks_init(void) { CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); /* Init System pfd3. */ CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); -#endif + #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); /* Bypass Audio PLL. */ diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c index 3d043a14e..754ef01c3 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c index a25937cab..fe39f7e19 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c index 7b9af3a6a..1d67956f8 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c @@ -40,22 +40,22 @@ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; +{ + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; +{ + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; +{ + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; // Based on the hello_world example in the SDK void clocks_init(void) { @@ -81,8 +81,7 @@ void clocks_init(void) { /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); @@ -120,7 +119,7 @@ void clocks_init(void) { /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT + #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ @@ -129,7 +128,7 @@ void clocks_init(void) { CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif + #endif /* Disable LPSPI clock gate. */ CLOCK_DisableClock(kCLOCK_Lpspi1); CLOCK_DisableClock(kCLOCK_Lpspi2); @@ -232,7 +231,7 @@ void clocks_init(void) { /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT + #ifndef SKIP_SYSCLK_INIT /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -243,7 +242,7 @@ void clocks_init(void) { CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Init System pfd3. */ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif + #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); /* Bypass Audio PLL. */ @@ -320,11 +319,11 @@ void clocks_init(void) { /* Set ENET1 Tx clock source. */ IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); /* Set ENET2 Tx clock source. */ -#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) + #if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); -#else + #else IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); -#endif + #endif /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c index fd1e4ddb8..e1c6968fc 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c index ce098ea2b..0e440b6b6 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h index 9b9713bb4..ab0ebf045 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h @@ -31,38 +31,38 @@ #include "pins.h" typedef struct { - uint8_t bank_idx:4; - uint8_t mux_mode:4; + uint8_t bank_idx : 4; + uint8_t mux_mode : 4; uint32_t input_reg; uint8_t input_idx; const mcu_pin_obj_t *pin; } mcu_periph_obj_t; #define PERIPH_PIN(p_bank_idx, p_mux_mode, p_input_reg, p_input_idx, p_pin) \ -{ \ - .bank_idx = p_bank_idx, \ - .mux_mode = p_mux_mode, \ - .input_reg = p_input_reg == 0 ? 0 : (uint32_t)&(IOMUXC->SELECT_INPUT[p_input_reg]), \ - .input_idx = p_input_idx, \ - .pin = p_pin, \ -} + { \ + .bank_idx = p_bank_idx, \ + .mux_mode = p_mux_mode, \ + .input_reg = p_input_reg == 0 ? 0 : (uint32_t)&(IOMUXC->SELECT_INPUT[p_input_reg]), \ + .input_idx = p_input_idx, \ + .pin = p_pin, \ + } typedef struct { PWM_Type *pwm; - pwm_submodule_t submodule:4; - pwm_channels_t channel:4; + pwm_submodule_t submodule : 4; + pwm_channels_t channel : 4; uint8_t mux_mode; const mcu_pin_obj_t *pin; } mcu_pwm_obj_t; #define PWM_PIN(p_pwm, p_submodule, p_channel, p_mux_mode, p_pin) \ -{ \ - .pwm = p_pwm, \ - .submodule = p_submodule, \ - .channel = p_channel, \ - .mux_mode = p_mux_mode, \ - .pin = p_pin, \ -} + { \ + .pwm = p_pwm, \ + .submodule = p_submodule, \ + .channel = p_channel, \ + .mux_mode = p_mux_mode, \ + .pin = p_pin, \ + } extern LPI2C_Type *mcu_i2c_banks[]; extern LPSPI_Type *mcu_spi_banks[]; diff --git a/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h b/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h index 7168854a5..d6d12771c 100644 --- a/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h +++ b/ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h @@ -59,18 +59,18 @@ typedef struct { } mcu_pin_obj_t; #define PIN(p_gpio, p_number, p_enum, p_adc, p_adc_channel, p_mux_reset, p_pad_reset) \ -{ \ - { &mcu_pin_type }, \ - .gpio = p_gpio, \ - .number = p_number, \ - .mux_idx = kIOMUXC_SW_MUX_CTL_PAD_ ## p_enum, \ - .mux_reg = (uint32_t)&(IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_ ## p_enum]), \ - .cfg_reg = (uint32_t)&(IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_PAD_CTL_PAD_ ## p_enum]), \ - .adc = p_adc, \ - .adc_channel = p_adc_channel, \ - .mux_reset = p_mux_reset, \ - .pad_reset = p_pad_reset, \ -} + { \ + { &mcu_pin_type }, \ + .gpio = p_gpio, \ + .number = p_number, \ + .mux_idx = kIOMUXC_SW_MUX_CTL_PAD_##p_enum, \ + .mux_reg = (uint32_t)&(IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_##p_enum]), \ + .cfg_reg = (uint32_t)&(IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_PAD_CTL_PAD_##p_enum]), \ + .adc = p_adc, \ + .adc_channel = p_adc_channel, \ + .mux_reset = p_mux_reset, \ + .pad_reset = p_pad_reset, \ + } #ifdef MIMXRT1011_SERIES #include "MIMXRT1011/pins.h" diff --git a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c index bd471f930..251e6f9ac 100644 --- a/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c +++ b/ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c @@ -12,24 +12,24 @@ #include "boards/flash_config.h" #include "supervisor/linker.h" -status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type *base, uint32_t baseAddr) +status_t PLACE_IN_ITCM(flexspi_nor_write_enable)(FLEXSPI_Type * base, uint32_t baseAddr) { flexspi_transfer_t flashXfer; status_t status; /* Write enable */ flashXfer.deviceAddress = baseAddr; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; status = FLEXSPI_TransferBlocking(base, &flashXfer); return status; } -status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type *base) +status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type * base) { /* Wait status ready. */ bool isBusy; @@ -38,57 +38,54 @@ status_t PLACE_IN_ITCM(flexspi_nor_wait_bus_busy)(FLEXSPI_Type *base) flexspi_transfer_t flashXfer; flashXfer.deviceAddress = 0; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Read; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_READSTATUSREG; - flashXfer.data = &readValue; - flashXfer.dataSize = 1; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_READSTATUSREG; + flashXfer.data = &readValue; + flashXfer.dataSize = 1; do { status = FLEXSPI_TransferBlocking(base, &flashXfer); - if (status != kStatus_Success) - { + if (status != kStatus_Success) { return status; } size_t busyBit = readValue & (1U << qspiflash_config.memConfig.busyOffset); isBusy = (qspiflash_config.memConfig.busyBitPolarity == 0 && busyBit != 0) || - (qspiflash_config.memConfig.busyBitPolarity == 1 && busyBit == 0); + (qspiflash_config.memConfig.busyBitPolarity == 1 && busyBit == 0); } while (isBusy); return status; } -status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type *base, uint32_t address) +status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type * base, uint32_t address) { status_t status; flexspi_transfer_t flashXfer; /* Write enable */ flashXfer.deviceAddress = address; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_WRITEENABLE; status = FLEXSPI_TransferBlocking(base, &flashXfer); - if (status != kStatus_Success) - { + if (status != kStatus_Success) { return status; } flashXfer.deviceAddress = address; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_ERASESECTOR; - status = FLEXSPI_TransferBlocking(base, &flashXfer); + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(base, &flashXfer); - if (status != kStatus_Success) - { + if (status != kStatus_Success) { return status; } @@ -100,7 +97,7 @@ status_t PLACE_IN_ITCM(flexspi_nor_flash_erase_sector)(FLEXSPI_Type *base, uint3 return status; } -status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src) +status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type * base, uint32_t dstAddr, const uint32_t *src) { status_t status; flexspi_transfer_t flashXfer; @@ -108,35 +105,33 @@ status_t PLACE_IN_ITCM(flexspi_nor_flash_page_program)(FLEXSPI_Type *base, uint3 /* Write enable */ status = flexspi_nor_write_enable(base, dstAddr); - if (status != kStatus_Success) - { + if (status != kStatus_Success) { return status; } /* Prepare page program command */ flashXfer.deviceAddress = dstAddr; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = ROM_INDEX_PAGEPROGRAM; - flashXfer.data = (uint32_t *)src; - flashXfer.dataSize = FLASH_PAGE_SIZE; - status = FLEXSPI_TransferBlocking(base, &flashXfer); - - if (status != kStatus_Success) - { + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = ROM_INDEX_PAGEPROGRAM; + flashXfer.data = (uint32_t *)src; + flashXfer.dataSize = FLASH_PAGE_SIZE; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) { return status; } status = flexspi_nor_wait_bus_busy(base); /* Do software reset. */ -#if defined(FSL_FEATURE_SOC_OTFAD_COUNT) + #if defined(FSL_FEATURE_SOC_OTFAD_COUNT) base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK; base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK); -#else + #else FLEXSPI_SoftwareReset(base); -#endif + #endif return status; } diff --git a/ports/mimxrt10xx/supervisor/internal_flash.c b/ports/mimxrt10xx/supervisor/internal_flash.c index 9c0d9f895..84c478bcf 100644 --- a/ports/mimxrt10xx/supervisor/internal_flash.c +++ b/ports/mimxrt10xx/supervisor/internal_flash.c @@ -49,7 +49,7 @@ extern uint32_t __fatfs_flash_length[]; #define NO_CACHE 0xffffffff #define SECTOR_SIZE 0x1000 /* 4K */ -uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4))); +uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4))); uint32_t _flash_page_addr = NO_CACHE; extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); @@ -58,7 +58,7 @@ extern status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base); void PLACE_IN_ITCM(supervisor_flash_init)(void) { // Update the LUT to make sure all entries are available. - FLEXSPI_UpdateLUT(FLEXSPI, 0, (const uint32_t*) &qspiflash_config.memConfig.lookupTable, 64); + FLEXSPI_UpdateLUT(FLEXSPI, 0, (const uint32_t *)&qspiflash_config.memConfig.lookupTable, 64); } static inline uint32_t lba2addr(uint32_t block) { @@ -74,7 +74,9 @@ uint32_t supervisor_flash_get_block_count(void) { } void PLACE_IN_ITCM(port_internal_flash_flush)(void) { - if (_flash_page_addr == NO_CACHE) return; + if (_flash_page_addr == NO_CACHE) { + return; + } status_t status; // Skip if data is the same @@ -109,13 +111,13 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n supervisor_flash_flush(); uint32_t src = lba2addr(block); - memcpy(dest, (uint8_t*)src, FILESYSTEM_BLOCK_SIZE * num_blocks); + memcpy(dest, (uint8_t *)src, FILESYSTEM_BLOCK_SIZE * num_blocks); return 0; // success } mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32_t num_blocks) { while (num_blocks) { - uint32_t const addr = lba2addr(lba); + uint32_t const addr = lba2addr(lba); uint32_t const page_addr = addr & ~(SECTOR_SIZE - 1); uint32_t count = 8 - (lba % 8); // up to page boundary @@ -135,8 +137,8 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 memcpy(_flash_cache + (addr & (SECTOR_SIZE - 1)), src, count * FILESYSTEM_BLOCK_SIZE); // adjust for next run - lba += count; - src += count * FILESYSTEM_BLOCK_SIZE; + lba += count; + src += count * FILESYSTEM_BLOCK_SIZE; num_blocks -= count; } diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c index 33a85d2b7..2493252d7 100644 --- a/ports/mimxrt10xx/supervisor/port.c +++ b/ports/mimxrt10xx/supervisor/port.c @@ -110,8 +110,8 @@ extern void main(void); // This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c. __attribute__((used, naked)) void Reset_Handler(void) { __disable_irq(); - SCB->VTOR = (uint32_t) &__isr_vector; - __set_MSP((uint32_t) &_ld_stack_top); + SCB->VTOR = (uint32_t)&__isr_vector; + __set_MSP((uint32_t)&_ld_stack_top); /* Disable I cache and D cache */ SCB_DisableICache(); @@ -135,7 +135,7 @@ __attribute__((used, naked)) void Reset_Handler(void) { IOMUXC_GPR->GPR14 = current_gpr14; #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ /* Disable Watchdog Power Down Counter */ @@ -147,11 +147,10 @@ __attribute__((used, naked)) void Reset_Handler(void) { WDOG2->WCR &= ~WDOG_WCR_WDE_MASK; RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ RTWDOG->TOVAL = 0xFFFF; - RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; + RTWDOG->CS = (uint32_t)((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; /* Disable Systick which might be enabled by bootrom */ - if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) - { + if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) { SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; } @@ -160,7 +159,7 @@ __attribute__((used, naked)) void Reset_Handler(void) { // Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write // protect it. - for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_itcm_size) / 4; i++) { (&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i]; } @@ -226,22 +225,22 @@ __attribute__((used, naked)) void Reset_Handler(void) { SCB_EnableICache(); // Copy all of the data to run from DTCM. - for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_data_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_data_size) / 4; i++) { (&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i]; } // Clear DTCM bss. - for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_bss_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_bss_size) / 4; i++) { (&_ld_dtcm_bss_start)[i] = 0; } // Copy all of the data to run from OCRAM. - for (uint32_t i = 0; i < ((size_t) &_ld_ocram_data_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_ocram_data_size) / 4; i++) { (&_ld_ocram_data_destination)[i] = (&_ld_ocram_data_flash_copy)[i]; } // Clear OCRAM bss. - for (uint32_t i = 0; i < ((size_t) &_ld_ocram_bss_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_ocram_bss_size) / 4; i++) { (&_ld_ocram_bss_start)[i] = 0; } @@ -254,9 +253,9 @@ safe_mode_t port_init(void) { clocks_init(); -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC rtc_init(); -#endif + #endif // Always enable the SNVS interrupt. The GPC won't wake us up unless at least one interrupt is // enabled. It won't occur very often so it'll be low overhead. @@ -275,43 +274,43 @@ safe_mode_t port_init(void) { void reset_port(void) { spi_reset(); -#if CIRCUITPY_AUDIOIO + #if CIRCUITPY_AUDIOIO audio_dma_reset(); audioout_reset(); -#endif -#if CIRCUITPY_AUDIOBUSIO + #endif + #if CIRCUITPY_AUDIOBUSIO i2sout_reset(); - //pdmin_reset(); -#endif + // pdmin_reset(); + #endif -#if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE + #if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE touchin_reset(); -#endif + #endif // eic_reset(); -#if CIRCUITPY_PULSEIO + #if CIRCUITPY_PULSEIO pulseout_reset(); -#endif -#if CIRCUITPY_PWMIO + #endif + #if CIRCUITPY_PWMIO pwmout_reset(); -#endif + #endif -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC rtc_reset(); -#endif + #endif -#if CIRCUITPY_GAMEPAD + #if CIRCUITPY_GAMEPAD gamepad_reset(); -#endif -#if CIRCUITPY_GAMEPADSHIFT + #endif + #if CIRCUITPY_GAMEPADSHIFT gamepadshift_reset(); -#endif -#if CIRCUITPY_PEW + #endif + #if CIRCUITPY_PEW pew_reset(); -#endif + #endif - //reset_event_system(); + // reset_event_system(); reset_all_pins(); } @@ -356,12 +355,12 @@ uint32_t port_get_saved_word(void) { return SNVS->LPGPR[1]; } -uint64_t port_get_raw_ticks(uint8_t* subticks) { +uint64_t port_get_raw_ticks(uint8_t *subticks) { uint64_t ticks = 0; uint64_t next_ticks = 1; while (ticks != next_ticks) { ticks = next_ticks; - next_ticks = ((uint64_t) SNVS->HPRTCMR) << 32 | SNVS->HPRTCLR; + next_ticks = ((uint64_t)SNVS->HPRTCMR) << 32 | SNVS->HPRTCLR; } if (subticks != NULL) { *subticks = ticks % 32; @@ -397,7 +396,8 @@ void port_interrupt_after_ticks(uint32_t ticks) { current_ticks += ticks; SNVS->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK; // Wait for the alarm to be disabled. - while ((SNVS->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0) {} + while ((SNVS->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0) { + } SNVS->HPTAMR = current_ticks >> (32 - 5); SNVS->HPTALR = current_ticks << 5 | subticks; SNVS->HPCR |= SNVS_HPCR_HPTA_EN_MASK; @@ -407,9 +407,9 @@ void port_idle_until_interrupt(void) { // App note here: https://www.nxp.com/docs/en/application-note/AN12085.pdf // Clear the FPU interrupt because it can prevent us from sleeping. - if (__get_FPSCR() & ~(0x9f)) { - __set_FPSCR(__get_FPSCR() & ~(0x9f)); - (void) __get_FPSCR(); + if (__get_FPSCR() & ~(0x9f)) { + __set_FPSCR(__get_FPSCR() & ~(0x9f)); + (void)__get_FPSCR(); } NVIC_ClearPendingIRQ(SNVS_HP_WRAPPER_IRQn); CLOCK_SetMode(kCLOCK_ModeWait); @@ -420,43 +420,39 @@ void port_idle_until_interrupt(void) { /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void MemManage_Handler(void) -{ +__attribute__((used)) void MemManage_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void BusFault_Handler(void) -{ +__attribute__((used)) void BusFault_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void UsageFault_Handler(void) -{ +__attribute__((used)) void UsageFault_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void HardFault_Handler(void) -{ +__attribute__((used)) void HardFault_Handler(void) { reset_into_safe_mode(HARD_CRASH); while (true) { - asm("nop;"); + asm ("nop;"); } } diff --git a/ports/mimxrt10xx/supervisor/serial.c b/ports/mimxrt10xx/supervisor/serial.c index 01656a819..ea706d8a8 100644 --- a/ports/mimxrt10xx/supervisor/serial.c +++ b/ports/mimxrt10xx/supervisor/serial.c @@ -35,7 +35,7 @@ // static LPUART_Type *uart_instance = LPUART1; // evk static LPUART_Type *uart_instance = LPUART4; // feather 1011 -//static LPUART_Type *uart_instance = LPUART2; // feather 1062 +// static LPUART_Type *uart_instance = LPUART2; // feather 1062 static uint32_t UartSrcFreq(void) { uint32_t freq; @@ -79,8 +79,8 @@ bool serial_bytes_available(void) { return LPUART_GetStatusFlags(uart_instance) & kLPUART_RxDataRegFullFlag; } -void serial_write(const char* text) { - LPUART_WriteBlocking(uart_instance, (uint8_t*)text, strlen(text)); +void serial_write(const char *text) { + LPUART_WriteBlocking(uart_instance, (uint8_t *)text, strlen(text)); } void serial_write_substring(const char *text, uint32_t len) { @@ -88,5 +88,5 @@ void serial_write_substring(const char *text, uint32_t len) { return; } - LPUART_WriteBlocking(uart_instance, (uint8_t*)text, len); + LPUART_WriteBlocking(uart_instance, (uint8_t *)text, len); } diff --git a/ports/mimxrt10xx/supervisor/usb.c b/ports/mimxrt10xx/supervisor/usb.c index 91135289c..57f038799 100644 --- a/ports/mimxrt10xx/supervisor/usb.c +++ b/ports/mimxrt10xx/supervisor/usb.c @@ -33,11 +33,11 @@ void init_usb_hardware(void) { CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); -#ifdef USBPHY + #ifdef USBPHY USBPHY_Type *usb_phy = USBPHY; -#else + #else USBPHY_Type *usb_phy = USBPHY1; -#endif + #endif // Enable PHY support for Low speed device + LS via FS Hub usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; diff --git a/ports/nrf/background.c b/ports/nrf/background.c index 10543ddb2..269bf6737 100644 --- a/ports/nrf/background.c +++ b/ports/nrf/background.c @@ -46,14 +46,16 @@ #include "common-hal/_bleio/bonding.h" #endif -void port_start_background_task(void) {} -void port_finish_background_task(void) {} +void port_start_background_task(void) { +} +void port_finish_background_task(void) { +} void port_background_task(void) { -#if CIRCUITPY_AUDIOPWMIO + #if CIRCUITPY_AUDIOPWMIO audiopwmout_background(); -#endif -#if CIRCUITPY_AUDIOBUSIO + #endif + #if CIRCUITPY_AUDIOBUSIO i2s_background(); -#endif + #endif } diff --git a/ports/nrf/bluetooth/ble_drv.c b/ports/nrf/bluetooth/ble_drv.c index 67c6f3468..f1a982024 100644 --- a/ports/nrf/bluetooth/ble_drv.c +++ b/ports/nrf/bluetooth/ble_drv.c @@ -55,7 +55,7 @@ void ble_drv_reset() { sd_flash_operation_status = SD_FLASH_OPERATION_DONE; } -void ble_drv_add_event_handler_entry(ble_drv_evt_handler_entry_t* entry, ble_drv_evt_handler_t func, void *param) { +void ble_drv_add_event_handler_entry(ble_drv_evt_handler_entry_t *entry, ble_drv_evt_handler_t func, void *param) { entry->next = MP_STATE_VM(ble_drv_evt_handler_entries); entry->param = param; entry->func = func; @@ -92,34 +92,34 @@ void ble_drv_remove_event_handler(ble_drv_evt_handler_t func, void *param) { } } -extern void tusb_hal_nrf_power_event (uint32_t event); +extern void tusb_hal_nrf_power_event(uint32_t event); void SD_EVT_IRQHandler(void) { uint32_t evt_id; while (sd_evt_get(&evt_id) != NRF_ERROR_NOT_FOUND) { switch (evt_id) { // usb power event - case NRF_EVT_POWER_USB_DETECTED: - case NRF_EVT_POWER_USB_POWER_READY: - case NRF_EVT_POWER_USB_REMOVED: { - int32_t usbevt = (evt_id == NRF_EVT_POWER_USB_DETECTED ) ? NRFX_POWER_USB_EVT_DETECTED: - (evt_id == NRF_EVT_POWER_USB_POWER_READY) ? NRFX_POWER_USB_EVT_READY : - (evt_id == NRF_EVT_POWER_USB_REMOVED ) ? NRFX_POWER_USB_EVT_REMOVED : -1; - - tusb_hal_nrf_power_event(usbevt); - } + case NRF_EVT_POWER_USB_DETECTED: + case NRF_EVT_POWER_USB_POWER_READY: + case NRF_EVT_POWER_USB_REMOVED: { + int32_t usbevt = (evt_id == NRF_EVT_POWER_USB_DETECTED) ? NRFX_POWER_USB_EVT_DETECTED: + (evt_id == NRF_EVT_POWER_USB_POWER_READY) ? NRFX_POWER_USB_EVT_READY : + (evt_id == NRF_EVT_POWER_USB_REMOVED) ? NRFX_POWER_USB_EVT_REMOVED : -1; + + tusb_hal_nrf_power_event(usbevt); + } break; // Set flag indicating that a flash operation has finished. - case NRF_EVT_FLASH_OPERATION_SUCCESS: - sd_flash_operation_status = SD_FLASH_OPERATION_DONE; - break; - case NRF_EVT_FLASH_OPERATION_ERROR: - sd_flash_operation_status = SD_FLASH_OPERATION_ERROR; - break; - - default: - break; + case NRF_EVT_FLASH_OPERATION_SUCCESS: + sd_flash_operation_status = SD_FLASH_OPERATION_DONE; + break; + case NRF_EVT_FLASH_OPERATION_ERROR: + sd_flash_operation_status = SD_FLASH_OPERATION_ERROR; + break; + + default: + break; } } @@ -134,7 +134,7 @@ void SD_EVT_IRQHandler(void) { break; } - ble_evt_t* event = (ble_evt_t *)m_ble_evt_buf; + ble_evt_t *event = (ble_evt_t *)m_ble_evt_buf; #if CIRCUITPY_VERBOSE_BLE mp_printf(&mp_plat_print, "BLE event: 0x%04x\n", event->header.evt_id); #endif @@ -154,7 +154,7 @@ void SD_EVT_IRQHandler(void) { } #if CIRCUITPY_VERBOSE_BLE if (event->header.evt_id == BLE_GATTS_EVT_WRITE) { - ble_gatts_evt_write_t* write_evt = &event->evt.gatts_evt.params.write; + ble_gatts_evt_write_t *write_evt = &event->evt.gatts_evt.params.write; mp_printf(&mp_plat_print, "Write to: UUID(0x%04x) handle %x of length %d auth %x\n", write_evt->uuid.uuid, write_evt->handle, write_evt->len, write_evt->auth_required); } #endif diff --git a/ports/nrf/bluetooth/ble_drv.h b/ports/nrf/bluetooth/ble_drv.h index d69f83e6e..e7649fcee 100644 --- a/ports/nrf/bluetooth/ble_drv.h +++ b/ports/nrf/bluetooth/ble_drv.h @@ -41,7 +41,7 @@ #define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) #define SEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000000) / (RESOLUTION)) -#define UNITS_TO_SEC(TIME, RESOLUTION) (((TIME) * (RESOLUTION)) / 1000000) +#define UNITS_TO_SEC(TIME, RESOLUTION) (((TIME)*(RESOLUTION)) / 1000000) // 0.625 msecs (625 usecs) #define ADV_INTERVAL_UNIT_FLOAT_SECS (0.000625) // Microseconds is the base unit. The macros above know that. @@ -49,7 +49,7 @@ #define UNIT_1_25_MS (1250) #define UNIT_10_MS (10000) -typedef bool (*ble_drv_evt_handler_t)(ble_evt_t*, void*); +typedef bool (*ble_drv_evt_handler_t)(ble_evt_t *, void *); typedef enum { SD_FLASH_OPERATION_DONE, @@ -71,6 +71,6 @@ void ble_drv_add_event_handler(ble_drv_evt_handler_t func, void *param); void ble_drv_remove_event_handler(ble_drv_evt_handler_t func, void *param); // Allow for user provided entries to prevent allocations outside the VM. -void ble_drv_add_event_handler_entry(ble_drv_evt_handler_entry_t* entry, ble_drv_evt_handler_t func, void *param); +void ble_drv_add_event_handler_entry(ble_drv_evt_handler_entry_t *entry, ble_drv_evt_handler_t func, void *param); #endif // MICROPY_INCLUDED_NRF_BLUETOOTH_BLE_DRV_H diff --git a/ports/nrf/bluetooth/ble_uart.c b/ports/nrf/bluetooth/ble_uart.c index 1b87b82d1..df6456867 100644 --- a/ports/nrf/bluetooth/ble_uart.c +++ b/ports/nrf/bluetooth/ble_uart.c @@ -66,26 +66,24 @@ static ringbuffer_t m_rx_ring_buffer = { STATIC void on_ble_evt(ble_evt_t *ble_evt, void *param) { switch (ble_evt->header.evt_id) { - case BLE_GAP_EVT_DISCONNECTED: - { + case BLE_GAP_EVT_DISCONNECTED: { mp_obj_t device_obj = MP_OBJ_FROM_PTR(&m_device); mp_call_function_0(mp_load_attr(device_obj, qstr_from_str("start_advertising"))); break; } - case BLE_GATTS_EVT_WRITE: - { + case BLE_GATTS_EVT_WRITE: { ble_gatts_evt_write_t *write = &ble_evt->evt.gatts_evt.params.write; if (write->handle == m_tx_chara->cccd_handle) { m_cccd_enabled = true; } else if (write->handle == m_rx_chara->handle) { for (size_t i = 0; i < write->len; ++i) { -#if MICROPY_KBD_EXCEPTION + #if MICROPY_KBD_EXCEPTION if (write->data[i] == mp_interrupt_char) { mp_keyboard_interrupt(); } else -#endif + #endif { bufferWrite(&m_rx_ring_buffer, write->data[i]); } @@ -143,7 +141,7 @@ void ble_uart_init(void) { } bool ble_uart_connected(void) { - return (m_device.conn_handle != BLE_CONN_HANDLE_INVALID); + return m_device.conn_handle != BLE_CONN_HANDLE_INVALID; } char ble_uart_rx_chr(void) { @@ -179,7 +177,7 @@ void mp_hal_stdout_tx_strn(const char *str, size_t len) { } mp_buffer_info_t bufinfo = { - .buf = (uint8_t*)str, + .buf = (uint8_t *)str, .len = send_len, }; diff --git a/ports/nrf/bluetooth/ringbuffer.h b/ports/nrf/bluetooth/ringbuffer.h index 9a06e7ccc..baf273293 100644 --- a/ports/nrf/bluetooth/ringbuffer.h +++ b/ports/nrf/bluetooth/ringbuffer.h @@ -65,18 +65,18 @@ #define _ringbuffer_h #define ringBuffer_typedef(T, NAME) \ - typedef struct { \ - int size; \ - volatile int start; \ - volatile int end; \ - T* elems; \ - } NAME + typedef struct { \ + int size; \ + volatile int start; \ + volatile int end; \ + T *elems; \ + } NAME #define bufferInit(BUF, S, T) \ - BUF.size = S+1; \ - BUF.start = 0; \ - BUF.end = 0; \ - BUF.elems = (T*)calloc(BUF.size, sizeof(T)) + BUF.size = S + 1; \ + BUF.start = 0; \ + BUF.end = 0; \ + BUF.elems = (T *)calloc(BUF.size, sizeof(T)) #define bufferDestroy(BUF) free((BUF)->elems) @@ -86,11 +86,11 @@ #define isBufferFull(BUF) (nextEndIndex(BUF) == (BUF)->start) #define bufferWrite(BUF, ELEM) \ - (BUF)->elems[(BUF)->end] = ELEM; \ - (BUF)->end = ((BUF)->end + 1) % (BUF)->size; \ - if (isBufferEmpty(BUF)) { \ - (BUF)->start = nextStartIndex(BUF); \ - } + (BUF)->elems[(BUF)->end] = ELEM; \ + (BUF)->end = ((BUF)->end + 1) % (BUF)->size; \ + if (isBufferEmpty(BUF)) { \ + (BUF)->start = nextStartIndex(BUF); \ + } #define bufferRead(BUF, ELEM) \ ELEM = (BUF)->elems[(BUF)->start]; \ diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble.h index e2abcd7ad..2ee2c74dc 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble.h @@ -71,17 +71,17 @@ extern "C" { */ enum BLE_COMMON_SVCS { - SD_BLE_ENABLE = BLE_SVC_BASE, /**< Enable and initialize the BLE stack */ - SD_BLE_EVT_GET, /**< Get an event from the pending events queue. */ - SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific base UUID. */ - SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */ - SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */ - SD_BLE_VERSION_GET, /**< Get the local version information (company ID, Link Layer Version, Link Layer Subversion). */ - SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */ - SD_BLE_OPT_SET, /**< Set a BLE option. */ - SD_BLE_OPT_GET, /**< Get a BLE option. */ - SD_BLE_CFG_SET, /**< Add a configuration to the BLE stack. */ - SD_BLE_UUID_VS_REMOVE, /**< Remove a Vendor Specific base UUID. */ + SD_BLE_ENABLE = BLE_SVC_BASE, /**< Enable and initialize the BLE stack */ + SD_BLE_EVT_GET, /**< Get an event from the pending events queue. */ + SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific base UUID. */ + SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */ + SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */ + SD_BLE_VERSION_GET, /**< Get the local version information (company ID, Link Layer Version, Link Layer Subversion). */ + SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */ + SD_BLE_OPT_SET, /**< Set a BLE option. */ + SD_BLE_OPT_GET, /**< Get a BLE option. */ + SD_BLE_CFG_SET, /**< Add a configuration to the BLE stack. */ + SD_BLE_UUID_VS_REMOVE, /**< Remove a Vendor Specific base UUID. */ }; /** @@ -89,8 +89,8 @@ enum BLE_COMMON_SVCS */ enum BLE_COMMON_EVTS { - BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. @ref ble_evt_user_mem_request_t */ - BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1, /**< User Memory release. @ref ble_evt_user_mem_release_t */ + BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. @ref ble_evt_user_mem_request_t */ + BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1, /**< User Memory release. @ref ble_evt_user_mem_release_t */ }; /**@brief BLE Connection Configuration IDs. @@ -112,7 +112,7 @@ enum BLE_CONN_CFGS */ enum BLE_COMMON_CFGS { - BLE_COMMON_CFG_VS_UUID = BLE_CFG_BASE, /**< Vendor specific base UUID configuration */ + BLE_COMMON_CFG_VS_UUID = BLE_CFG_BASE, /**< Vendor specific base UUID configuration */ }; /**@brief Common Option IDs. @@ -120,9 +120,9 @@ enum BLE_COMMON_CFGS */ enum BLE_COMMON_OPTS { - BLE_COMMON_OPT_PA_LNA = BLE_OPT_BASE + 0, /**< PA and LNA options */ - BLE_COMMON_OPT_CONN_EVT_EXT = BLE_OPT_BASE + 1, /**< Extended connection events option */ - BLE_COMMON_OPT_EXTENDED_RC_CAL = BLE_OPT_BASE + 2, /**< Extended RC calibration option */ + BLE_COMMON_OPT_PA_LNA = BLE_OPT_BASE + 0,/**< PA and LNA options */ + BLE_COMMON_OPT_CONN_EVT_EXT = BLE_OPT_BASE + 1,/**< Extended connection events option */ + BLE_COMMON_OPT_EXTENDED_RC_CAL = BLE_OPT_BASE + 2, /**< Extended RC calibration option */ }; /** @} */ @@ -143,8 +143,8 @@ enum BLE_COMMON_OPTS * If that value has not been configured for any connections then @ref BLE_GATT_ATT_MTU_DEFAULT must be used instead. */ #define BLE_EVT_LEN_MAX(ATT_MTU) ( \ - offsetof(ble_evt_t, evt.gattc_evt.params.prim_srvc_disc_rsp.services) + ((ATT_MTU) - 1) / 4 * sizeof(ble_gattc_service_t) \ -) + offsetof(ble_evt_t, evt.gattc_evt.params.prim_srvc_disc_rsp.services) + ((ATT_MTU)-1) / 4 * sizeof(ble_gattc_service_t) \ + ) /** @defgroup BLE_USER_MEM_TYPES User Memory Types * @{ */ @@ -174,53 +174,53 @@ enum BLE_COMMON_OPTS /**@brief User Memory Block. */ typedef struct { - uint8_t *p_mem; /**< Pointer to the start of the user memory block. */ - uint16_t len; /**< Length in bytes of the user memory block. */ + uint8_t *p_mem; /**< Pointer to the start of the user memory block. */ + uint16_t len; /**< Length in bytes of the user memory block. */ } ble_user_mem_block_t; /**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */ typedef struct { - uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ } ble_evt_user_mem_request_t; /**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */ typedef struct { - uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ - ble_user_mem_block_t mem_block; /**< User memory block */ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ + ble_user_mem_block_t mem_block; /**< User memory block */ } ble_evt_user_mem_release_t; /**@brief Event structure for events not associated with a specific function module. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which this event occurred. */ - union - { - ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */ - ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */ - } params; /**< Event parameter union. */ + uint16_t conn_handle; /**< Connection Handle on which this event occurred. */ + union + { + ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */ + ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */ + } params; /**< Event parameter union. */ } ble_common_evt_t; /**@brief BLE Event header. */ typedef struct { - uint16_t evt_id; /**< Value from a BLE_<module>_EVT series. */ - uint16_t evt_len; /**< Length in octets including this header. */ + uint16_t evt_id; /**< Value from a BLE_<module>_EVT series. */ + uint16_t evt_len; /**< Length in octets including this header. */ } ble_evt_hdr_t; /**@brief Common BLE Event type, wrapping the module specific event reports. */ typedef struct { - ble_evt_hdr_t header; /**< Event header. */ - union - { - ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ - ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ - ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ - ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ - ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ - } evt; /**< Event union. */ + ble_evt_hdr_t header; /**< Event header. */ + union + { + ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ + ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ + ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ + ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ + ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ + } evt; /**< Event union. */ } ble_evt_t; @@ -229,9 +229,9 @@ typedef struct */ typedef struct { - uint8_t version_number; /**< Link Layer Version number. See https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer for assigned values. */ - uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ - uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ + uint8_t version_number; /**< Link Layer Version number. See https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer for assigned values. */ + uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ + uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ } ble_version_t; /** @@ -239,9 +239,9 @@ typedef struct */ typedef struct { - uint8_t enable :1; /**< Enable toggling for this amplifier */ - uint8_t active_high :1; /**< Set the pin to be active high */ - uint8_t gpio_pin :6; /**< The GPIO pin to toggle for this amplifier */ + uint8_t enable : 1; /**< Enable toggling for this amplifier */ + uint8_t active_high : 1; /**< Set the pin to be active high */ + uint8_t gpio_pin : 6; /**< The GPIO pin to toggle for this amplifier */ } ble_pa_lna_cfg_t; /** @@ -259,12 +259,12 @@ typedef struct */ typedef struct { - ble_pa_lna_cfg_t pa_cfg; /**< Power Amplifier configuration */ - ble_pa_lna_cfg_t lna_cfg; /**< Low Noise Amplifier configuration */ + ble_pa_lna_cfg_t pa_cfg; /**< Power Amplifier configuration */ + ble_pa_lna_cfg_t lna_cfg; /**< Low Noise Amplifier configuration */ - uint8_t ppi_ch_id_set; /**< PPI channel used for radio pin setting */ - uint8_t ppi_ch_id_clr; /**< PPI channel used for radio pin clearing */ - uint8_t gpiote_ch_id; /**< GPIOTE channel used for radio pin toggling */ + uint8_t ppi_ch_id_set; /**< PPI channel used for radio pin setting */ + uint8_t ppi_ch_id_clr; /**< PPI channel used for radio pin clearing */ + uint8_t gpiote_ch_id; /**< GPIOTE channel used for radio pin toggling */ } ble_common_opt_pa_lna_t; /** @@ -280,7 +280,7 @@ typedef struct */ typedef struct { - uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */ + uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */ } ble_common_opt_conn_evt_ext_t; /** @@ -300,22 +300,22 @@ typedef struct */ typedef struct { - uint8_t enable : 1; /**< Enable extended RC calibration, enabled by default. */ + uint8_t enable : 1; /**< Enable extended RC calibration, enabled by default. */ } ble_common_opt_extended_rc_cal_t; /**@brief Option structure for common options. */ typedef union { - ble_common_opt_pa_lna_t pa_lna; /**< Parameters for controlling PA and LNA pin toggling. */ - ble_common_opt_conn_evt_ext_t conn_evt_ext; /**< Parameters for enabling extended connection events. */ - ble_common_opt_extended_rc_cal_t extended_rc_cal; /**< Parameters for enabling extended RC calibration. */ + ble_common_opt_pa_lna_t pa_lna; /**< Parameters for controlling PA and LNA pin toggling. */ + ble_common_opt_conn_evt_ext_t conn_evt_ext; /**< Parameters for enabling extended connection events. */ + ble_common_opt_extended_rc_cal_t extended_rc_cal; /**< Parameters for enabling extended RC calibration. */ } ble_common_opt_t; /**@brief Common BLE Option type, wrapping the module specific options. */ typedef union { - ble_common_opt_t common_opt; /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */ - ble_gap_opt_t gap_opt; /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */ + ble_common_opt_t common_opt; /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */ + ble_gap_opt_t gap_opt; /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */ } ble_opt_t; /**@brief BLE connection configuration type, wrapping the module specific configurations, set with @@ -337,17 +337,17 @@ typedef union */ typedef struct { - uint8_t conn_cfg_tag; /**< The application chosen tag it can use with the + uint8_t conn_cfg_tag; /**< The application chosen tag it can use with the @ref sd_ble_gap_adv_start() and @ref sd_ble_gap_connect() calls to select this configuration when creating a connection. Must be different for all connection configurations added and not @ref BLE_CONN_CFG_TAG_DEFAULT. */ - union { - ble_gap_conn_cfg_t gap_conn_cfg; /**< GAP connection configuration, cfg_id is @ref BLE_CONN_CFG_GAP. */ - ble_gattc_conn_cfg_t gattc_conn_cfg; /**< GATTC connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTC. */ - ble_gatts_conn_cfg_t gatts_conn_cfg; /**< GATTS connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTS. */ - ble_gatt_conn_cfg_t gatt_conn_cfg; /**< GATT connection configuration, cfg_id is @ref BLE_CONN_CFG_GATT. */ - ble_l2cap_conn_cfg_t l2cap_conn_cfg; /**< L2CAP connection configuration, cfg_id is @ref BLE_CONN_CFG_L2CAP. */ - } params; /**< Connection configuration union. */ + union { + ble_gap_conn_cfg_t gap_conn_cfg; /**< GAP connection configuration, cfg_id is @ref BLE_CONN_CFG_GAP. */ + ble_gattc_conn_cfg_t gattc_conn_cfg; /**< GATTC connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTC. */ + ble_gatts_conn_cfg_t gatts_conn_cfg; /**< GATTS connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTS. */ + ble_gatt_conn_cfg_t gatt_conn_cfg; /**< GATT connection configuration, cfg_id is @ref BLE_CONN_CFG_GATT. */ + ble_l2cap_conn_cfg_t l2cap_conn_cfg; /**< L2CAP connection configuration, cfg_id is @ref BLE_CONN_CFG_L2CAP. */ + } params; /**< Connection configuration union. */ } ble_conn_cfg_t; /** @@ -357,7 +357,7 @@ typedef struct */ typedef struct { - uint8_t vs_uuid_count; /**< Number of 128-bit Vendor Specific base UUID bases to allocate memory for. + uint8_t vs_uuid_count; /**< Number of 128-bit Vendor Specific base UUID bases to allocate memory for. Default value is @ref BLE_UUID_VS_COUNT_DEFAULT. Maximum value is @ref BLE_UUID_VS_COUNT_MAX. */ } ble_common_cfg_vs_uuid_t; @@ -365,16 +365,16 @@ typedef struct /**@brief Common BLE Configuration type, wrapping the common configurations. */ typedef union { - ble_common_cfg_vs_uuid_t vs_uuid_cfg; /**< Vendor Specific base UUID configuration, cfg_id is @ref BLE_COMMON_CFG_VS_UUID. */ + ble_common_cfg_vs_uuid_t vs_uuid_cfg; /**< Vendor Specific base UUID configuration, cfg_id is @ref BLE_COMMON_CFG_VS_UUID. */ } ble_common_cfg_t; /**@brief BLE Configuration type, wrapping the module specific configurations. */ typedef union { - ble_conn_cfg_t conn_cfg; /**< Connection specific configurations, cfg_id in @ref BLE_CONN_CFGS series. */ - ble_common_cfg_t common_cfg; /**< Global common configurations, cfg_id in @ref BLE_COMMON_CFGS series. */ - ble_gap_cfg_t gap_cfg; /**< Global GAP configurations, cfg_id in @ref BLE_GAP_CFGS series. */ - ble_gatts_cfg_t gatts_cfg; /**< Global GATTS configuration, cfg_id in @ref BLE_GATTS_CFGS series. */ + ble_conn_cfg_t conn_cfg; /**< Connection specific configurations, cfg_id in @ref BLE_CONN_CFGS series. */ + ble_common_cfg_t common_cfg; /**< Global common configurations, cfg_id in @ref BLE_COMMON_CFGS series. */ + ble_gap_cfg_t gap_cfg; /**< Global GAP configurations, cfg_id in @ref BLE_GAP_CFGS series. */ + ble_gatts_cfg_t gatts_cfg; /**< Global GATTS configuration, cfg_id in @ref BLE_GATTS_CFGS series. */ } ble_cfg_t; /** @} */ @@ -450,7 +450,7 @@ SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(uint32_t * p_app_ram_base)); * @retval ::NRF_ERROR_NO_MEM The amount of memory assigned to the SoftDevice by app_ram_base is not * large enough to fit this configuration's memory requirement. */ -SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * p_cfg, uint32_t app_ram_base)); +SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const *p_cfg, uint32_t app_ram_base)); /**@brief Get an event from the pending events queue. * @@ -488,7 +488,7 @@ SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled. * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer. */ -SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len)); +SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t * p_dest, uint16_t * p_len)); /**@brief Add a Vendor Specific base UUID. @@ -517,7 +517,7 @@ SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid. * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs. */ -SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type)); +SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t * p_uuid_type)); /**@brief Remove a Vendor Specific base UUID. @@ -539,7 +539,7 @@ SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_v * @retval ::NRF_ERROR_FORBIDDEN If the Vendor Specific base UUID is in use by the ATT Server. */ -SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t *p_uuid_type)); +SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t * p_uuid_type)); /** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure. @@ -560,7 +560,7 @@ SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t *p_uuid_ty * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length. * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs. */ -SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid)); +SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t * p_uuid)); /** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit). @@ -575,7 +575,7 @@ SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uin * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type. */ -SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le)); +SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t * p_uuid_le_len, uint8_t * p_uuid_le)); /**@brief Get Version Information. @@ -588,7 +588,7 @@ SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure). */ -SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version)); +SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t * p_version)); /**@brief Provide a user memory block. @@ -653,7 +653,7 @@ SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported. * */ -SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt)); +SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t * p_opt)); /** @} */ #ifdef __cplusplus diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_err.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_err.h index 1b4820dc3..64e610a2f 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_err.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_err.h @@ -62,12 +62,12 @@ extern "C" { /* @defgroup BLE_ERRORS Error Codes * @{ */ -#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */ -#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */ -#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */ -#define BLE_ERROR_INVALID_ADV_HANDLE (NRF_ERROR_STK_BASE_NUM+0x004) /**< Invalid advertising handle. */ -#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */ -#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM+0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */ +#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM + 0x001) /**< @ref sd_ble_enable has not been called. */ +#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM + 0x002) /**< Invalid connection handle. */ +#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM + 0x003) /**< Invalid attribute handle. */ +#define BLE_ERROR_INVALID_ADV_HANDLE (NRF_ERROR_STK_BASE_NUM + 0x004) /**< Invalid advertising handle. */ +#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM + 0x005) /**< Invalid role. */ +#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM + 0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */ /** @} */ @@ -75,10 +75,10 @@ extern "C" { * @brief Assignment of subranges for module specific error codes. * @note For specific error codes, see ble_<module>.h or ble_error_<module>.h. * @{ */ -#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */ -#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */ -#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */ -#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */ +#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM + 0x100) /**< L2CAP specific errors. */ +#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM + 0x200) /**< GAP specific errors. */ +#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM + 0x300) /**< GATT client specific errors. */ +#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM + 0x400) /**< GATT server specific errors. */ /** @} */ #ifdef __cplusplus diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gap.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gap.h index 6750e742f..f5a8199a9 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gap.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gap.h @@ -64,46 +64,46 @@ extern "C" { */ enum BLE_GAP_SVCS { - SD_BLE_GAP_ADDR_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ - SD_BLE_GAP_ADDR_GET = BLE_GAP_SVC_BASE + 1, /**< Get own Bluetooth Address. */ - SD_BLE_GAP_WHITELIST_SET = BLE_GAP_SVC_BASE + 2, /**< Set active whitelist. */ - SD_BLE_GAP_DEVICE_IDENTITIES_SET = BLE_GAP_SVC_BASE + 3, /**< Set device identity list. */ - SD_BLE_GAP_PRIVACY_SET = BLE_GAP_SVC_BASE + 4, /**< Set Privacy settings*/ - SD_BLE_GAP_PRIVACY_GET = BLE_GAP_SVC_BASE + 5, /**< Get Privacy settings*/ - SD_BLE_GAP_ADV_SET_CONFIGURE = BLE_GAP_SVC_BASE + 6, /**< Configure an advertising set. */ - SD_BLE_GAP_ADV_START = BLE_GAP_SVC_BASE + 7, /**< Start Advertising. */ - SD_BLE_GAP_ADV_STOP = BLE_GAP_SVC_BASE + 8, /**< Stop Advertising. */ - SD_BLE_GAP_CONN_PARAM_UPDATE = BLE_GAP_SVC_BASE + 9, /**< Connection Parameter Update. */ - SD_BLE_GAP_DISCONNECT = BLE_GAP_SVC_BASE + 10, /**< Disconnect. */ - SD_BLE_GAP_TX_POWER_SET = BLE_GAP_SVC_BASE + 11, /**< Set TX Power. */ - SD_BLE_GAP_APPEARANCE_SET = BLE_GAP_SVC_BASE + 12, /**< Set Appearance. */ - SD_BLE_GAP_APPEARANCE_GET = BLE_GAP_SVC_BASE + 13, /**< Get Appearance. */ - SD_BLE_GAP_PPCP_SET = BLE_GAP_SVC_BASE + 14, /**< Set PPCP. */ - SD_BLE_GAP_PPCP_GET = BLE_GAP_SVC_BASE + 15, /**< Get PPCP. */ - SD_BLE_GAP_DEVICE_NAME_SET = BLE_GAP_SVC_BASE + 16, /**< Set Device Name. */ - SD_BLE_GAP_DEVICE_NAME_GET = BLE_GAP_SVC_BASE + 17, /**< Get Device Name. */ - SD_BLE_GAP_AUTHENTICATE = BLE_GAP_SVC_BASE + 18, /**< Initiate Pairing/Bonding. */ - SD_BLE_GAP_SEC_PARAMS_REPLY = BLE_GAP_SVC_BASE + 19, /**< Reply with Security Parameters. */ - SD_BLE_GAP_AUTH_KEY_REPLY = BLE_GAP_SVC_BASE + 20, /**< Reply with an authentication key. */ - SD_BLE_GAP_LESC_DHKEY_REPLY = BLE_GAP_SVC_BASE + 21, /**< Reply with an LE Secure Connections DHKey. */ - SD_BLE_GAP_KEYPRESS_NOTIFY = BLE_GAP_SVC_BASE + 22, /**< Notify of a keypress during an authentication procedure. */ - SD_BLE_GAP_LESC_OOB_DATA_GET = BLE_GAP_SVC_BASE + 23, /**< Get the local LE Secure Connections OOB data. */ - SD_BLE_GAP_LESC_OOB_DATA_SET = BLE_GAP_SVC_BASE + 24, /**< Set the remote LE Secure Connections OOB data. */ - SD_BLE_GAP_ENCRYPT = BLE_GAP_SVC_BASE + 25, /**< Initiate encryption procedure. */ - SD_BLE_GAP_SEC_INFO_REPLY = BLE_GAP_SVC_BASE + 26, /**< Reply with Security Information. */ - SD_BLE_GAP_CONN_SEC_GET = BLE_GAP_SVC_BASE + 27, /**< Obtain connection security level. */ - SD_BLE_GAP_RSSI_START = BLE_GAP_SVC_BASE + 28, /**< Start reporting of changes in RSSI. */ - SD_BLE_GAP_RSSI_STOP = BLE_GAP_SVC_BASE + 29, /**< Stop reporting of changes in RSSI. */ - SD_BLE_GAP_SCAN_START = BLE_GAP_SVC_BASE + 30, /**< Start Scanning. */ - SD_BLE_GAP_SCAN_STOP = BLE_GAP_SVC_BASE + 31, /**< Stop Scanning. */ - SD_BLE_GAP_CONNECT = BLE_GAP_SVC_BASE + 32, /**< Connect. */ - SD_BLE_GAP_CONNECT_CANCEL = BLE_GAP_SVC_BASE + 33, /**< Cancel ongoing connection procedure. */ - SD_BLE_GAP_RSSI_GET = BLE_GAP_SVC_BASE + 34, /**< Get the last RSSI sample. */ - SD_BLE_GAP_PHY_UPDATE = BLE_GAP_SVC_BASE + 35, /**< Initiate or respond to a PHY Update Procedure. */ - SD_BLE_GAP_DATA_LENGTH_UPDATE = BLE_GAP_SVC_BASE + 36, /**< Initiate or respond to a Data Length Update Procedure. */ - SD_BLE_GAP_QOS_CHANNEL_SURVEY_START = BLE_GAP_SVC_BASE + 37, /**< Start Quality of Service (QoS) channel survey module. */ - SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP = BLE_GAP_SVC_BASE + 38, /**< Stop Quality of Service (QoS) channel survey module. */ - SD_BLE_GAP_ADV_ADDR_GET = BLE_GAP_SVC_BASE + 39, /**< Get the Address used on air while Advertising. */ + SD_BLE_GAP_ADDR_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ + SD_BLE_GAP_ADDR_GET = BLE_GAP_SVC_BASE + 1, /**< Get own Bluetooth Address. */ + SD_BLE_GAP_WHITELIST_SET = BLE_GAP_SVC_BASE + 2, /**< Set active whitelist. */ + SD_BLE_GAP_DEVICE_IDENTITIES_SET = BLE_GAP_SVC_BASE + 3, /**< Set device identity list. */ + SD_BLE_GAP_PRIVACY_SET = BLE_GAP_SVC_BASE + 4, /**< Set Privacy settings*/ + SD_BLE_GAP_PRIVACY_GET = BLE_GAP_SVC_BASE + 5, /**< Get Privacy settings*/ + SD_BLE_GAP_ADV_SET_CONFIGURE = BLE_GAP_SVC_BASE + 6, /**< Configure an advertising set. */ + SD_BLE_GAP_ADV_START = BLE_GAP_SVC_BASE + 7, /**< Start Advertising. */ + SD_BLE_GAP_ADV_STOP = BLE_GAP_SVC_BASE + 8, /**< Stop Advertising. */ + SD_BLE_GAP_CONN_PARAM_UPDATE = BLE_GAP_SVC_BASE + 9, /**< Connection Parameter Update. */ + SD_BLE_GAP_DISCONNECT = BLE_GAP_SVC_BASE + 10,/**< Disconnect. */ + SD_BLE_GAP_TX_POWER_SET = BLE_GAP_SVC_BASE + 11,/**< Set TX Power. */ + SD_BLE_GAP_APPEARANCE_SET = BLE_GAP_SVC_BASE + 12,/**< Set Appearance. */ + SD_BLE_GAP_APPEARANCE_GET = BLE_GAP_SVC_BASE + 13,/**< Get Appearance. */ + SD_BLE_GAP_PPCP_SET = BLE_GAP_SVC_BASE + 14,/**< Set PPCP. */ + SD_BLE_GAP_PPCP_GET = BLE_GAP_SVC_BASE + 15,/**< Get PPCP. */ + SD_BLE_GAP_DEVICE_NAME_SET = BLE_GAP_SVC_BASE + 16,/**< Set Device Name. */ + SD_BLE_GAP_DEVICE_NAME_GET = BLE_GAP_SVC_BASE + 17,/**< Get Device Name. */ + SD_BLE_GAP_AUTHENTICATE = BLE_GAP_SVC_BASE + 18,/**< Initiate Pairing/Bonding. */ + SD_BLE_GAP_SEC_PARAMS_REPLY = BLE_GAP_SVC_BASE + 19,/**< Reply with Security Parameters. */ + SD_BLE_GAP_AUTH_KEY_REPLY = BLE_GAP_SVC_BASE + 20,/**< Reply with an authentication key. */ + SD_BLE_GAP_LESC_DHKEY_REPLY = BLE_GAP_SVC_BASE + 21,/**< Reply with an LE Secure Connections DHKey. */ + SD_BLE_GAP_KEYPRESS_NOTIFY = BLE_GAP_SVC_BASE + 22,/**< Notify of a keypress during an authentication procedure. */ + SD_BLE_GAP_LESC_OOB_DATA_GET = BLE_GAP_SVC_BASE + 23,/**< Get the local LE Secure Connections OOB data. */ + SD_BLE_GAP_LESC_OOB_DATA_SET = BLE_GAP_SVC_BASE + 24,/**< Set the remote LE Secure Connections OOB data. */ + SD_BLE_GAP_ENCRYPT = BLE_GAP_SVC_BASE + 25,/**< Initiate encryption procedure. */ + SD_BLE_GAP_SEC_INFO_REPLY = BLE_GAP_SVC_BASE + 26,/**< Reply with Security Information. */ + SD_BLE_GAP_CONN_SEC_GET = BLE_GAP_SVC_BASE + 27,/**< Obtain connection security level. */ + SD_BLE_GAP_RSSI_START = BLE_GAP_SVC_BASE + 28,/**< Start reporting of changes in RSSI. */ + SD_BLE_GAP_RSSI_STOP = BLE_GAP_SVC_BASE + 29,/**< Stop reporting of changes in RSSI. */ + SD_BLE_GAP_SCAN_START = BLE_GAP_SVC_BASE + 30,/**< Start Scanning. */ + SD_BLE_GAP_SCAN_STOP = BLE_GAP_SVC_BASE + 31,/**< Stop Scanning. */ + SD_BLE_GAP_CONNECT = BLE_GAP_SVC_BASE + 32,/**< Connect. */ + SD_BLE_GAP_CONNECT_CANCEL = BLE_GAP_SVC_BASE + 33,/**< Cancel ongoing connection procedure. */ + SD_BLE_GAP_RSSI_GET = BLE_GAP_SVC_BASE + 34,/**< Get the last RSSI sample. */ + SD_BLE_GAP_PHY_UPDATE = BLE_GAP_SVC_BASE + 35,/**< Initiate or respond to a PHY Update Procedure. */ + SD_BLE_GAP_DATA_LENGTH_UPDATE = BLE_GAP_SVC_BASE + 36,/**< Initiate or respond to a Data Length Update Procedure. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_START = BLE_GAP_SVC_BASE + 37,/**< Start Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP = BLE_GAP_SVC_BASE + 38,/**< Stop Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_ADV_ADDR_GET = BLE_GAP_SVC_BASE + 39,/**< Get the Address used on air while Advertising. */ }; /**@brief GAP Event IDs. @@ -111,29 +111,29 @@ enum BLE_GAP_SVCS */ enum BLE_GAP_EVTS { - BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connected to peer. \n See @ref ble_gap_evt_connected_t */ - BLE_GAP_EVT_DISCONNECTED = BLE_GAP_EVT_BASE + 1, /**< Disconnected from peer. \n See @ref ble_gap_evt_disconnected_t. */ - BLE_GAP_EVT_CONN_PARAM_UPDATE = BLE_GAP_EVT_BASE + 2, /**< Connection Parameters updated. \n See @ref ble_gap_evt_conn_param_update_t. */ - BLE_GAP_EVT_SEC_PARAMS_REQUEST = BLE_GAP_EVT_BASE + 3, /**< Request to provide security parameters. \n Reply with @ref sd_ble_gap_sec_params_reply. \n See @ref ble_gap_evt_sec_params_request_t. */ - BLE_GAP_EVT_SEC_INFO_REQUEST = BLE_GAP_EVT_BASE + 4, /**< Request to provide security information. \n Reply with @ref sd_ble_gap_sec_info_reply. \n See @ref ble_gap_evt_sec_info_request_t. */ - BLE_GAP_EVT_PASSKEY_DISPLAY = BLE_GAP_EVT_BASE + 5, /**< Request to display a passkey to the user. \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */ - BLE_GAP_EVT_KEY_PRESSED = BLE_GAP_EVT_BASE + 6, /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t */ - BLE_GAP_EVT_AUTH_KEY_REQUEST = BLE_GAP_EVT_BASE + 7, /**< Request to provide an authentication key. \n Reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_auth_key_request_t. */ - BLE_GAP_EVT_LESC_DHKEY_REQUEST = BLE_GAP_EVT_BASE + 8, /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply. \n See @ref ble_gap_evt_lesc_dhkey_request_t */ - BLE_GAP_EVT_AUTH_STATUS = BLE_GAP_EVT_BASE + 9, /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t. */ - BLE_GAP_EVT_CONN_SEC_UPDATE = BLE_GAP_EVT_BASE + 10, /**< Connection security updated. \n See @ref ble_gap_evt_conn_sec_update_t. */ - BLE_GAP_EVT_TIMEOUT = BLE_GAP_EVT_BASE + 11, /**< Timeout expired. \n See @ref ble_gap_evt_timeout_t. */ - BLE_GAP_EVT_RSSI_CHANGED = BLE_GAP_EVT_BASE + 12, /**< RSSI report. \n See @ref ble_gap_evt_rssi_changed_t. */ - BLE_GAP_EVT_ADV_REPORT = BLE_GAP_EVT_BASE + 13, /**< Advertising report. \n See @ref ble_gap_evt_adv_report_t. */ - BLE_GAP_EVT_SEC_REQUEST = BLE_GAP_EVT_BASE + 14, /**< Security Request. \n See @ref ble_gap_evt_sec_request_t. */ - BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 15, /**< Connection Parameter Update Request. \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */ - BLE_GAP_EVT_SCAN_REQ_REPORT = BLE_GAP_EVT_BASE + 16, /**< Scan request report. \n See @ref ble_gap_evt_scan_req_report_t. */ - BLE_GAP_EVT_PHY_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 17, /**< PHY Update Request. \n Reply with @ref sd_ble_gap_phy_update. \n See @ref ble_gap_evt_phy_update_request_t. */ - BLE_GAP_EVT_PHY_UPDATE = BLE_GAP_EVT_BASE + 18, /**< PHY Update Procedure is complete. \n See @ref ble_gap_evt_phy_update_t. */ - BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 19, /**< Data Length Update Request. \n Reply with @ref sd_ble_gap_data_length_update.\n See @ref ble_gap_evt_data_length_update_request_t. */ - BLE_GAP_EVT_DATA_LENGTH_UPDATE = BLE_GAP_EVT_BASE + 20, /**< LL Data Channel PDU payload length updated. \n See @ref ble_gap_evt_data_length_update_t. */ - BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT = BLE_GAP_EVT_BASE + 21, /**< Channel survey report. \n See @ref ble_gap_evt_qos_channel_survey_report_t. */ - BLE_GAP_EVT_ADV_SET_TERMINATED = BLE_GAP_EVT_BASE + 22, /**< Advertising set terminated. \n See @ref ble_gap_evt_adv_set_terminated_t. */ + BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connected to peer. \n See @ref ble_gap_evt_connected_t */ + BLE_GAP_EVT_DISCONNECTED = BLE_GAP_EVT_BASE + 1, /**< Disconnected from peer. \n See @ref ble_gap_evt_disconnected_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE = BLE_GAP_EVT_BASE + 2, /**< Connection Parameters updated. \n See @ref ble_gap_evt_conn_param_update_t. */ + BLE_GAP_EVT_SEC_PARAMS_REQUEST = BLE_GAP_EVT_BASE + 3, /**< Request to provide security parameters. \n Reply with @ref sd_ble_gap_sec_params_reply. \n See @ref ble_gap_evt_sec_params_request_t. */ + BLE_GAP_EVT_SEC_INFO_REQUEST = BLE_GAP_EVT_BASE + 4, /**< Request to provide security information. \n Reply with @ref sd_ble_gap_sec_info_reply. \n See @ref ble_gap_evt_sec_info_request_t. */ + BLE_GAP_EVT_PASSKEY_DISPLAY = BLE_GAP_EVT_BASE + 5, /**< Request to display a passkey to the user. \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */ + BLE_GAP_EVT_KEY_PRESSED = BLE_GAP_EVT_BASE + 6, /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t */ + BLE_GAP_EVT_AUTH_KEY_REQUEST = BLE_GAP_EVT_BASE + 7, /**< Request to provide an authentication key. \n Reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_auth_key_request_t. */ + BLE_GAP_EVT_LESC_DHKEY_REQUEST = BLE_GAP_EVT_BASE + 8, /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply. \n See @ref ble_gap_evt_lesc_dhkey_request_t */ + BLE_GAP_EVT_AUTH_STATUS = BLE_GAP_EVT_BASE + 9, /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t. */ + BLE_GAP_EVT_CONN_SEC_UPDATE = BLE_GAP_EVT_BASE + 10,/**< Connection security updated. \n See @ref ble_gap_evt_conn_sec_update_t. */ + BLE_GAP_EVT_TIMEOUT = BLE_GAP_EVT_BASE + 11,/**< Timeout expired. \n See @ref ble_gap_evt_timeout_t. */ + BLE_GAP_EVT_RSSI_CHANGED = BLE_GAP_EVT_BASE + 12,/**< RSSI report. \n See @ref ble_gap_evt_rssi_changed_t. */ + BLE_GAP_EVT_ADV_REPORT = BLE_GAP_EVT_BASE + 13,/**< Advertising report. \n See @ref ble_gap_evt_adv_report_t. */ + BLE_GAP_EVT_SEC_REQUEST = BLE_GAP_EVT_BASE + 14,/**< Security Request. \n See @ref ble_gap_evt_sec_request_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 15,/**< Connection Parameter Update Request. \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */ + BLE_GAP_EVT_SCAN_REQ_REPORT = BLE_GAP_EVT_BASE + 16,/**< Scan request report. \n See @ref ble_gap_evt_scan_req_report_t. */ + BLE_GAP_EVT_PHY_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 17,/**< PHY Update Request. \n Reply with @ref sd_ble_gap_phy_update. \n See @ref ble_gap_evt_phy_update_request_t. */ + BLE_GAP_EVT_PHY_UPDATE = BLE_GAP_EVT_BASE + 18,/**< PHY Update Procedure is complete. \n See @ref ble_gap_evt_phy_update_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 19, /**< Data Length Update Request. \n Reply with @ref sd_ble_gap_data_length_update.\n See @ref ble_gap_evt_data_length_update_request_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE = BLE_GAP_EVT_BASE + 20, /**< LL Data Channel PDU payload length updated. \n See @ref ble_gap_evt_data_length_update_t. */ + BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT = BLE_GAP_EVT_BASE + 21, /**< Channel survey report. \n See @ref ble_gap_evt_qos_channel_survey_report_t. */ + BLE_GAP_EVT_ADV_SET_TERMINATED = BLE_GAP_EVT_BASE + 22, /**< Advertising set terminated. \n See @ref ble_gap_evt_adv_set_terminated_t. */ }; /**@brief GAP Option IDs. @@ -141,12 +141,12 @@ enum BLE_GAP_EVTS */ enum BLE_GAP_OPTS { - BLE_GAP_OPT_CH_MAP = BLE_GAP_OPT_BASE, /**< Channel Map. @ref ble_gap_opt_ch_map_t */ - BLE_GAP_OPT_LOCAL_CONN_LATENCY = BLE_GAP_OPT_BASE + 1, /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */ - BLE_GAP_OPT_PASSKEY = BLE_GAP_OPT_BASE + 2, /**< Set passkey. @ref ble_gap_opt_passkey_t */ - BLE_GAP_OPT_COMPAT_MODE_1 = BLE_GAP_OPT_BASE + 3, /**< Compatibility mode. @ref ble_gap_opt_compat_mode_1_t */ - BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT = BLE_GAP_OPT_BASE + 4, /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */ - BLE_GAP_OPT_SLAVE_LATENCY_DISABLE = BLE_GAP_OPT_BASE + 5, /**< Disable slave latency. @ref ble_gap_opt_slave_latency_disable_t */ + BLE_GAP_OPT_CH_MAP = BLE_GAP_OPT_BASE, /**< Channel Map. @ref ble_gap_opt_ch_map_t */ + BLE_GAP_OPT_LOCAL_CONN_LATENCY = BLE_GAP_OPT_BASE + 1, /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */ + BLE_GAP_OPT_PASSKEY = BLE_GAP_OPT_BASE + 2, /**< Set passkey. @ref ble_gap_opt_passkey_t */ + BLE_GAP_OPT_COMPAT_MODE_1 = BLE_GAP_OPT_BASE + 3, /**< Compatibility mode. @ref ble_gap_opt_compat_mode_1_t */ + BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT = BLE_GAP_OPT_BASE + 4, /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */ + BLE_GAP_OPT_SLAVE_LATENCY_DISABLE = BLE_GAP_OPT_BASE + 5, /**< Disable slave latency. @ref ble_gap_opt_slave_latency_disable_t */ }; /**@brief GAP Configuration IDs. @@ -155,17 +155,17 @@ enum BLE_GAP_OPTS */ enum BLE_GAP_CFGS { - BLE_GAP_CFG_ROLE_COUNT = BLE_GAP_CFG_BASE, /**< Role count configuration. */ - BLE_GAP_CFG_DEVICE_NAME = BLE_GAP_CFG_BASE + 1, /**< Device name configuration. */ + BLE_GAP_CFG_ROLE_COUNT = BLE_GAP_CFG_BASE, /**< Role count configuration. */ + BLE_GAP_CFG_DEVICE_NAME = BLE_GAP_CFG_BASE + 1,/**< Device name configuration. */ }; /**@brief GAP TX Power roles. */ enum BLE_GAP_TX_POWER_ROLES { - BLE_GAP_TX_POWER_ROLE_ADV = 1, /**< Advertiser role. */ - BLE_GAP_TX_POWER_ROLE_SCAN_INIT = 2, /**< Scanner and initiator role. */ - BLE_GAP_TX_POWER_ROLE_CONN = 3, /**< Connection role. */ + BLE_GAP_TX_POWER_ROLE_ADV = 1, /**< Advertiser role. */ + BLE_GAP_TX_POWER_ROLE_SCAN_INIT = 2, /**< Scanner and initiator role. */ + BLE_GAP_TX_POWER_ROLE_CONN = 3, /**< Connection role. */ }; /** @} */ @@ -315,28 +315,28 @@ enum BLE_GAP_TX_POWER_ROLES * @{ */ #define BLE_GAP_ADV_INTERVAL_MIN 0x000020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */ #define BLE_GAP_ADV_INTERVAL_MAX 0x004000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */ - /**@} */ +/**@} */ /**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min * @{ */ #define BLE_GAP_SCAN_INTERVAL_MIN 0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */ #define BLE_GAP_SCAN_INTERVAL_MAX 0xFFFF /**< Maximum Scan interval in 625 us units, i.e. 40,959.375 s. */ - /** @} */ +/** @} */ /**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min * @{ */ #define BLE_GAP_SCAN_WINDOW_MIN 0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */ #define BLE_GAP_SCAN_WINDOW_MAX 0xFFFF /**< Maximum Scan window in 625 us units, i.e. 40,959.375 s. */ - /** @} */ +/** @} */ /**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min * @{ */ #define BLE_GAP_SCAN_TIMEOUT_MIN 0x0001 /**< Minimum Scan timeout in 10 ms units, i.e 10 ms. */ #define BLE_GAP_SCAN_TIMEOUT_UNLIMITED 0x0000 /**< Continue to scan forever. */ - /** @} */ +/** @} */ /**@defgroup BLE_GAP_SCAN_BUFFER_SIZE GAP Minimum scanner buffer size * @@ -555,19 +555,19 @@ enum BLE_GAP_TX_POWER_ROLES * See @ref ble_gap_conn_sec_mode_t. * @{ */ /**@brief Set sec_mode pointed to by ptr to have no access rights.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while (0) /**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while (0) /**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while (0) /**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while (0) /**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while (0) /**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while (0) /**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while (0) /**@} */ @@ -642,7 +642,7 @@ enum BLE_GAP_TX_POWER_ROLES #define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS (0) /**< Continuous channel survey. */ #define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MIN_US (7500) /**< Minimum channel survey interval in microseconds (7.5 ms). */ #define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MAX_US (4000000) /**< Maximum channel survey interval in microseconds (4 s). */ - /**@} */ +/**@} */ /** @} */ @@ -653,45 +653,45 @@ enum BLE_GAP_TX_POWER_ROLES /**@brief Advertising event properties. */ typedef struct { - uint8_t type; /**< Advertising type. See @ref BLE_GAP_ADV_TYPES. */ - uint8_t anonymous : 1; /**< Omit advertiser's address from all PDUs. + uint8_t type; /**< Advertising type. See @ref BLE_GAP_ADV_TYPES. */ + uint8_t anonymous : 1;/**< Omit advertiser's address from all PDUs. @note Anonymous advertising is only available for @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED and @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED. */ - uint8_t include_tx_power : 1; /**< This feature is not supported on this SoftDevice. */ + uint8_t include_tx_power : 1; /**< This feature is not supported on this SoftDevice. */ } ble_gap_adv_properties_t; /**@brief Advertising report type. */ typedef struct { - uint16_t connectable : 1; /**< Connectable advertising event type. */ - uint16_t scannable : 1; /**< Scannable advertising event type. */ - uint16_t directed : 1; /**< Directed advertising event type. */ - uint16_t scan_response : 1; /**< Received a scan response. */ - uint16_t extended_pdu : 1; /**< Received an extended advertising set. */ - uint16_t status : 2; /**< Data status. See @ref BLE_GAP_ADV_DATA_STATUS. */ - uint16_t reserved : 9; /**< Reserved for future use. */ + uint16_t connectable : 1;/**< Connectable advertising event type. */ + uint16_t scannable : 1;/**< Scannable advertising event type. */ + uint16_t directed : 1;/**< Directed advertising event type. */ + uint16_t scan_response : 1; /**< Received a scan response. */ + uint16_t extended_pdu : 1;/**< Received an extended advertising set. */ + uint16_t status : 2;/**< Data status. See @ref BLE_GAP_ADV_DATA_STATUS. */ + uint16_t reserved : 9;/**< Reserved for future use. */ } ble_gap_adv_report_type_t; /**@brief Advertising Auxiliary Pointer. */ typedef struct { - uint16_t aux_offset; /**< Time offset from the beginning of advertising packet to the auxiliary packet in 100 us units. */ - uint8_t aux_phy; /**< Indicates the PHY on which the auxiliary advertising packet is sent. See @ref BLE_GAP_PHYS. */ + uint16_t aux_offset; /**< Time offset from the beginning of advertising packet to the auxiliary packet in 100 us units. */ + uint8_t aux_phy; /**< Indicates the PHY on which the auxiliary advertising packet is sent. See @ref BLE_GAP_PHYS. */ } ble_gap_aux_pointer_t; /**@brief Bluetooth Low Energy address. */ typedef struct { - uint8_t addr_id_peer : 1; /**< Only valid for peer addresses. + uint8_t addr_id_peer : 1; /**< Only valid for peer addresses. This bit is set by the SoftDevice to indicate whether the address has been resolved from a Resolvable Private Address (when the peer is using privacy). If set to 1, @ref addr and @ref addr_type refer to the identity address of the resolved address. This bit is ignored when a variable of type @ref ble_gap_addr_t is used as input to API functions. */ - uint8_t addr_type : 7; /**< See @ref BLE_GAP_ADDR_TYPES. */ - uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. + uint8_t addr_type : 7; /**< See @ref BLE_GAP_ADDR_TYPES. */ + uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. @ref addr is not used if @ref addr_type is @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. */ } ble_gap_addr_t; @@ -709,10 +709,10 @@ typedef struct */ typedef struct { - uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ } ble_gap_conn_params_t; @@ -728,8 +728,8 @@ typedef struct */ typedef struct { - uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ - uint8_t lv : 4; /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */ + uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ + uint8_t lv : 4; /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */ } ble_gap_conn_sec_mode_t; @@ -737,14 +737,14 @@ typedef struct /**@brief GAP connection security status.*/ typedef struct { - ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ - uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ + ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ + uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ } ble_gap_conn_sec_t; /**@brief Identity Resolving Key. */ typedef struct { - uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ + uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ } ble_gap_irk_t; @@ -759,8 +759,8 @@ typedef uint8_t ble_gap_ch_mask_t[5]; /**@brief GAP advertising parameters. */ typedef struct { - ble_gap_adv_properties_t properties; /**< The properties of the advertising events. */ - ble_gap_addr_t const *p_peer_addr; /**< Address of a known peer. + ble_gap_adv_properties_t properties; /**< The properties of the advertising events. */ + ble_gap_addr_t const *p_peer_addr; /**< Address of a known peer. @note ble_gap_addr_t::addr_type cannot be @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. - When privacy is enabled and the local device uses @@ -774,16 +774,16 @@ typedef struct in the device identity list, the peer IRK for that device will be used to generate @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE target addresses used in the advertising event PDUs. */ - uint32_t interval; /**< Advertising interval in 625 us units. @sa BLE_GAP_ADV_INTERVALS. + uint32_t interval; /**< Advertising interval in 625 us units. @sa BLE_GAP_ADV_INTERVALS. @note If @ref ble_gap_adv_properties_t::type is set to @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE advertising, this parameter is ignored. */ - uint16_t duration; /**< Advertising duration in 10 ms units. When timeout is reached, + uint16_t duration; /**< Advertising duration in 10 ms units. When timeout is reached, an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised. @sa BLE_GAP_ADV_TIMEOUT_VALUES. @note The SoftDevice will always complete at least one advertising event even if the duration is set too low. */ - uint8_t max_adv_evts; /**< Maximum advertising events that shall be sent prior to disabling + uint8_t max_adv_evts; /**< Maximum advertising events that shall be sent prior to disabling advertising. Setting the value to 0 disables the limitation. When the count of advertising events specified by this parameter (if not 0) is reached, advertising will be automatically stopped @@ -791,17 +791,17 @@ typedef struct @note If @ref ble_gap_adv_properties_t::type is set to @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE, this parameter is ignored. */ - ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. At least one of the primary channels, that is channel index 37-39, must be used. Masking away secondary advertising channels is not supported. */ - uint8_t filter_policy; /**< Filter Policy. @sa BLE_GAP_ADV_FILTER_POLICIES. */ - uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising channel packets + uint8_t filter_policy; /**< Filter Policy. @sa BLE_GAP_ADV_FILTER_POLICIES. */ + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising channel packets are transmitted. If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS will be used. Valid values are @ref BLE_GAP_PHY_1MBPS and @ref BLE_GAP_PHY_CODED. @note The primary_phy shall indicate @ref BLE_GAP_PHY_1MBPS if @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ - uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising channel packets + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising channel packets are transmitted. If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS will be used. Valid values are @@ -811,11 +811,11 @@ typedef struct connection and send AUX_ADV_IND packets on. @note This parameter will be ignored when @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ - uint8_t set_id:4; /**< The advertising set identifier distinguishes this advertising set from other + uint8_t set_id : 4; /**< The advertising set identifier distinguishes this advertising set from other advertising sets transmitted by this and other devices. @note This parameter will be ignored when @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ - uint8_t scan_req_notification:1; /**< Enable scan request notifications for this advertising set. When a + uint8_t scan_req_notification : 1; /**< Enable scan request notifications for this advertising set. When a scan request is received and the scanner address is allowed by the filter policy, @ref BLE_GAP_EVT_SCAN_REQ_REPORT is raised. @note This parameter will be ignored when @@ -836,11 +836,11 @@ typedef struct * To update advertising data while advertising, provide new buffers to @ref sd_ble_gap_adv_set_configure. */ typedef struct { - ble_data_t adv_data; /**< Advertising data. + ble_data_t adv_data; /**< Advertising data. @note Advertising data can only be specified for a @ref ble_gap_adv_properties_t::type that is allowed to contain advertising data. */ - ble_data_t scan_rsp_data; /**< Scan response data. + ble_data_t scan_rsp_data; /**< Scan response data. @note Scan response data can only be specified for a @ref ble_gap_adv_properties_t::type that is scannable. */ @@ -850,11 +850,11 @@ typedef struct /**@brief GAP scanning parameters. */ typedef struct { - uint8_t extended : 1; /**< If 1, the scanner will accept extended advertising packets. + uint8_t extended : 1; /**< If 1, the scanner will accept extended advertising packets. If set to 0, the scanner will not receive advertising packets on secondary advertising channels, and will not be able to receive long advertising PDUs. */ - uint8_t report_incomplete_evts : 1; /**< If 1, events of type @ref ble_gap_evt_adv_report_t may have + uint8_t report_incomplete_evts : 1; /**< If 1, events of type @ref ble_gap_evt_adv_report_t may have @ref ble_gap_adv_report_type_t::status set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. This parameter is ignored when used with @ref sd_ble_gap_connect @@ -862,13 +862,13 @@ typedef struct advertising event, and is only available for extended scanning, see @ref sd_ble_gap_scan_start. @note This feature is not supported by this SoftDevice. */ - uint8_t active : 1; /**< If 1, perform active scanning by sending scan requests. + uint8_t active : 1; /**< If 1, perform active scanning by sending scan requests. This parameter is ignored when used with @ref sd_ble_gap_connect. */ - uint8_t filter_policy : 2; /**< Scanning filter policy. @sa BLE_GAP_SCAN_FILTER_POLICIES. + uint8_t filter_policy : 2; /**< Scanning filter policy. @sa BLE_GAP_SCAN_FILTER_POLICIES. @note Only @ref BLE_GAP_SCAN_FP_ACCEPT_ALL and @ref BLE_GAP_SCAN_FP_WHITELIST are valid when used with @ref sd_ble_gap_connect */ - uint8_t scan_phys; /**< Bitfield of PHYs to scan on. If set to @ref BLE_GAP_PHY_AUTO, + uint8_t scan_phys; /**< Bitfield of PHYs to scan on. If set to @ref BLE_GAP_PHY_AUTO, scan_phys will default to @ref BLE_GAP_PHY_1MBPS. - If @ref ble_gap_scan_params_t::extended is set to 0, the only supported PHY is @ref BLE_GAP_PHY_1MBPS. @@ -884,13 +884,13 @@ typedef struct PHY will also contain @ref BLE_GAP_PHY_CODED. If the only scan PHY is @ref BLE_GAP_PHY_CODED, the primary scan PHY is @ref BLE_GAP_PHY_CODED only. */ - uint16_t interval; /**< Scan interval in 625 us units. @sa BLE_GAP_SCAN_INTERVALS. */ - uint16_t window; /**< Scan window in 625 us units. @sa BLE_GAP_SCAN_WINDOW. + uint16_t interval; /**< Scan interval in 625 us units. @sa BLE_GAP_SCAN_INTERVALS. */ + uint16_t window; /**< Scan window in 625 us units. @sa BLE_GAP_SCAN_WINDOW. If scan_phys contains both @ref BLE_GAP_PHY_1MBPS and @ref BLE_GAP_PHY_CODED interval shall be larger than or equal to twice the scan window. */ - uint16_t timeout; /**< Scan timeout in 10 ms units. @sa BLE_GAP_SCAN_TIMEOUT. */ - ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + uint16_t timeout; /**< Scan timeout in 10 ms units. @sa BLE_GAP_SCAN_TIMEOUT. */ + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. At least one of the primary channels, that is channel index 37-39, must be set to 0. Masking away secondary channels is not supported. */ @@ -916,10 +916,10 @@ typedef struct */ typedef struct { - uint8_t privacy_mode; /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */ - uint8_t private_addr_type; /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */ - uint16_t private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */ - ble_gap_irk_t *p_device_irk; /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used. + uint8_t privacy_mode; /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */ + uint8_t private_addr_type; /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */ + uint16_t private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */ + ble_gap_irk_t *p_device_irk; /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used. When used as output, pointer to IRK structure where the current default IRK will be written to. If NULL, this argument is ignored. By default, the default IRK is used to generate random private resolvable addresses for the local device unless instructed otherwise. */ } ble_gap_privacy_params_t; @@ -935,98 +935,98 @@ typedef struct */ typedef struct { - uint8_t tx_phys; /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */ - uint8_t rx_phys; /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */ + uint8_t tx_phys; /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phys; /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */ } ble_gap_phys_t; /** @brief Keys that can be exchanged during a bonding procedure. */ typedef struct { - uint8_t enc : 1; /**< Long Term Key and Master Identification. */ - uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */ - uint8_t sign : 1; /**< Connection Signature Resolving Key. */ - uint8_t link : 1; /**< Derive the Link Key from the LTK. */ + uint8_t enc : 1; /**< Long Term Key and Master Identification. */ + uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */ + uint8_t sign : 1; /**< Connection Signature Resolving Key. */ + uint8_t link : 1; /**< Derive the Link Key from the LTK. */ } ble_gap_sec_kdist_t; /**@brief GAP security parameters. */ typedef struct { - uint8_t bond : 1; /**< Perform bonding. */ - uint8_t mitm : 1; /**< Enable Man In The Middle protection. */ - uint8_t lesc : 1; /**< Enable LE Secure Connection pairing. */ - uint8_t keypress : 1; /**< Enable generation of keypress notifications. */ - uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ - uint8_t oob : 1; /**< The OOB data flag. + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Enable Man In The Middle protection. */ + uint8_t lesc : 1; /**< Enable LE Secure Connection pairing. */ + uint8_t keypress : 1; /**< Enable generation of keypress notifications. */ + uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ + uint8_t oob : 1; /**< The OOB data flag. - In LE legacy pairing, this flag is set if a device has out of band authentication data. The OOB method is used if both of the devices have out of band authentication data. - In LE Secure Connections pairing, this flag is set if a device has the peer device's out of band authentication data. The OOB method is used if at least one device has the peer device's OOB data available. */ - uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */ - uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ - ble_gap_sec_kdist_t kdist_own; /**< Key distribution bitmap: keys that the local device will distribute. */ - ble_gap_sec_kdist_t kdist_peer; /**< Key distribution bitmap: keys that the remote device will distribute. */ + uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */ + uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ + ble_gap_sec_kdist_t kdist_own; /**< Key distribution bitmap: keys that the local device will distribute. */ + ble_gap_sec_kdist_t kdist_peer; /**< Key distribution bitmap: keys that the remote device will distribute. */ } ble_gap_sec_params_t; /**@brief GAP Encryption Information. */ typedef struct { - uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ - uint8_t lesc : 1; /**< Key generated using LE Secure Connections. */ - uint8_t auth : 1; /**< Authenticated Key. */ - uint8_t ltk_len : 6; /**< LTK length in octets. */ + uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ + uint8_t lesc : 1; /**< Key generated using LE Secure Connections. */ + uint8_t auth : 1; /**< Authenticated Key. */ + uint8_t ltk_len : 6; /**< LTK length in octets. */ } ble_gap_enc_info_t; /**@brief GAP Master Identification. */ typedef struct { - uint16_t ediv; /**< Encrypted Diversifier. */ - uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */ + uint16_t ediv; /**< Encrypted Diversifier. */ + uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */ } ble_gap_master_id_t; /**@brief GAP Signing Information. */ typedef struct { - uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */ + uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */ } ble_gap_sign_info_t; /**@brief GAP LE Secure Connections P-256 Public Key. */ typedef struct { - uint8_t pk[BLE_GAP_LESC_P256_PK_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */ + uint8_t pk[BLE_GAP_LESC_P256_PK_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */ } ble_gap_lesc_p256_pk_t; /**@brief GAP LE Secure Connections DHKey. */ typedef struct { - uint8_t key[BLE_GAP_LESC_DHKEY_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */ + uint8_t key[BLE_GAP_LESC_DHKEY_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */ } ble_gap_lesc_dhkey_t; /**@brief GAP LE Secure Connections OOB data. */ typedef struct { - ble_gap_addr_t addr; /**< Bluetooth address of the device. */ - uint8_t r[BLE_GAP_SEC_KEY_LEN]; /**< Random Number. */ - uint8_t c[BLE_GAP_SEC_KEY_LEN]; /**< Confirm Value. */ + ble_gap_addr_t addr; /**< Bluetooth address of the device. */ + uint8_t r[BLE_GAP_SEC_KEY_LEN]; /**< Random Number. */ + uint8_t c[BLE_GAP_SEC_KEY_LEN]; /**< Confirm Value. */ } ble_gap_lesc_oob_data_t; /**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */ typedef struct { - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the device's identity address. */ - uint8_t role; /**< BLE role for this connection, see @ref BLE_GAP_ROLES */ - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ - uint8_t adv_handle; /**< Advertising handle in which advertising has ended. + uint8_t role; /**< BLE role for this connection, see @ref BLE_GAP_ROLES */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ - ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated advertising set. The advertising buffers provided in @ref sd_ble_gap_adv_set_configure are now released. This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ @@ -1036,53 +1036,53 @@ typedef struct /**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */ typedef struct { - uint8_t reason; /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */ + uint8_t reason; /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */ } ble_gap_evt_disconnected_t; /**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */ typedef struct { - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ } ble_gap_evt_conn_param_update_t; /**@brief Event structure for @ref BLE_GAP_EVT_PHY_UPDATE_REQUEST. */ typedef struct { - ble_gap_phys_t peer_preferred_phys; /**< The PHYs the peer prefers to use. */ + ble_gap_phys_t peer_preferred_phys; /**< The PHYs the peer prefers to use. */ } ble_gap_evt_phy_update_request_t; /**@brief Event Structure for @ref BLE_GAP_EVT_PHY_UPDATE. */ typedef struct { - uint8_t status; /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES.*/ - uint8_t tx_phy; /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */ - uint8_t rx_phy; /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */ + uint8_t status; /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES.*/ + uint8_t tx_phy; /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phy; /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */ } ble_gap_evt_phy_update_t; /**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */ typedef struct { - ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ + ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ } ble_gap_evt_sec_params_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */ typedef struct { - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ - ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */ - uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ - uint8_t id_info : 1; /**< If 1, Identity Information required. */ - uint8_t sign_info : 1; /**< If 1, Signing Information required. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ + ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */ + uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ + uint8_t id_info : 1; /**< If 1, Identity Information required. */ + uint8_t sign_info : 1; /**< If 1, Signing Information required. */ } ble_gap_evt_sec_info_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */ typedef struct { - uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ - uint8_t match_request : 1; /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply + uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ + uint8_t match_request : 1; /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */ } ble_gap_evt_passkey_display_t; @@ -1090,22 +1090,22 @@ typedef struct /**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */ typedef struct { - uint8_t kp_not; /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */ + uint8_t kp_not; /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */ } ble_gap_evt_key_pressed_t; /**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */ typedef struct { - uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ + uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ } ble_gap_evt_auth_key_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */ typedef struct { - ble_gap_lesc_p256_pk_t *p_pk_peer; /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory + ble_gap_lesc_p256_pk_t *p_pk_peer; /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */ - uint8_t oobd_req :1; /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */ + uint8_t oobd_req : 1; /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */ } ble_gap_evt_lesc_dhkey_request_t; @@ -1114,36 +1114,36 @@ typedef struct */ typedef struct { - uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ - uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ - uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ - uint8_t lv4 : 1; /**< If 1: Level 4 is supported. */ + uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ + uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ + uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ + uint8_t lv4 : 1; /**< If 1: Level 4 is supported. */ } ble_gap_sec_levels_t; /**@brief Encryption Key. */ typedef struct { - ble_gap_enc_info_t enc_info; /**< Encryption Information. */ - ble_gap_master_id_t master_id; /**< Master Identification. */ + ble_gap_enc_info_t enc_info; /**< Encryption Information. */ + ble_gap_master_id_t master_id; /**< Master Identification. */ } ble_gap_enc_key_t; /**@brief Identity Key. */ typedef struct { - ble_gap_irk_t id_info; /**< Identity Resolving Key. */ - ble_gap_addr_t id_addr_info; /**< Identity Address. */ + ble_gap_irk_t id_info; /**< Identity Resolving Key. */ + ble_gap_addr_t id_addr_info; /**< Identity Address. */ } ble_gap_id_key_t; /**@brief Security Keys. */ typedef struct { - ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */ - ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */ - ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */ - ble_gap_lesc_p256_pk_t *p_pk; /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined + ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */ + ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */ + ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */ + ble_gap_lesc_p256_pk_t *p_pk; /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */ } ble_gap_sec_keys_t; @@ -1151,80 +1151,80 @@ typedef struct /**@brief Security key set for both local and peer keys. */ typedef struct { - ble_gap_sec_keys_t keys_own; /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */ - ble_gap_sec_keys_t keys_peer; /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */ + ble_gap_sec_keys_t keys_own; /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */ + ble_gap_sec_keys_t keys_peer; /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */ } ble_gap_sec_keyset_t; /**@brief Data Length Update Procedure parameters. */ typedef struct { - uint16_t max_tx_octets; /**< Maximum number of payload octets that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ - uint16_t max_rx_octets; /**< Maximum number of payload octets that a Controller supports for reception of a single Link Layer Data Channel PDU. */ - uint16_t max_tx_time_us; /**< Maximum time, in microseconds, that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ - uint16_t max_rx_time_us; /**< Maximum time, in microseconds, that a Controller supports for reception of a single Link Layer Data Channel PDU. */ + uint16_t max_tx_octets; /**< Maximum number of payload octets that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_octets; /**< Maximum number of payload octets that a Controller supports for reception of a single Link Layer Data Channel PDU. */ + uint16_t max_tx_time_us; /**< Maximum time, in microseconds, that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_time_us; /**< Maximum time, in microseconds, that a Controller supports for reception of a single Link Layer Data Channel PDU. */ } ble_gap_data_length_params_t; /**@brief Data Length Update Procedure local limitation. */ typedef struct { - uint16_t tx_payload_limited_octets; /**< If > 0, the requested TX packet length is too long by this many octets. */ - uint16_t rx_payload_limited_octets; /**< If > 0, the requested RX packet length is too long by this many octets. */ - uint16_t tx_rx_time_limited_us; /**< If > 0, the requested combination of TX and RX packet lengths is too long by this many microseconds. */ + uint16_t tx_payload_limited_octets; /**< If > 0, the requested TX packet length is too long by this many octets. */ + uint16_t rx_payload_limited_octets; /**< If > 0, the requested RX packet length is too long by this many octets. */ + uint16_t tx_rx_time_limited_us; /**< If > 0, the requested combination of TX and RX packet lengths is too long by this many microseconds. */ } ble_gap_data_length_limitation_t; /**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */ typedef struct { - uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ - uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ - uint8_t bonded : 1; /**< Procedure resulted in a bond. */ - uint8_t lesc : 1; /**< Procedure resulted in a LE Secure Connection. */ - ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ - ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ - ble_gap_sec_kdist_t kdist_own; /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */ - ble_gap_sec_kdist_t kdist_peer; /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */ + uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ + uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ + uint8_t bonded : 1; /**< Procedure resulted in a bond. */ + uint8_t lesc : 1; /**< Procedure resulted in a LE Secure Connection. */ + ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ + ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ + ble_gap_sec_kdist_t kdist_own; /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */ + ble_gap_sec_kdist_t kdist_peer; /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */ } ble_gap_evt_auth_status_t; /**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */ typedef struct { - ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ + ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ } ble_gap_evt_conn_sec_update_t; /**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */ typedef struct { - uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ - union - { - ble_data_t adv_report_buffer; /**< If source is set to @ref BLE_GAP_TIMEOUT_SRC_SCAN, the released + uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ + union + { + ble_data_t adv_report_buffer; /**< If source is set to @ref BLE_GAP_TIMEOUT_SRC_SCAN, the released scan buffer is contained in this field. */ - } params; /**< Event Parameters. */ + } params; /**< Event Parameters. */ } ble_gap_evt_timeout_t; /**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */ typedef struct { - int8_t rssi; /**< Received Signal Strength Indication in dBm. + int8_t rssi; /**< Received Signal Strength Indication in dBm. @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ - uint8_t ch_index; /**< Data Channel Index on which the Signal Strength is measured (0-36). */ + uint8_t ch_index; /**< Data Channel Index on which the Signal Strength is measured (0-36). */ } ble_gap_evt_rssi_changed_t; /**@brief Event structure for @ref BLE_GAP_EVT_ADV_SET_TERMINATED */ typedef struct { - uint8_t reason; /**< Reason for why the advertising set terminated. See + uint8_t reason; /**< Reason for why the advertising set terminated. See @ref BLE_GAP_EVT_ADV_SET_TERMINATED_REASON. */ - uint8_t adv_handle; /**< Advertising handle in which advertising has ended. */ - uint8_t num_completed_adv_events; /**< If @ref ble_gap_adv_params_t::max_adv_evts was not set to 0, + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. */ + uint8_t num_completed_adv_events; /**< If @ref ble_gap_adv_params_t::max_adv_evts was not set to 0, this field indicates the number of completed advertising events. */ - ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated advertising set. The advertising buffers provided in @ref sd_ble_gap_adv_set_configure are now released. */ } ble_gap_evt_adv_set_terminated_t; @@ -1239,11 +1239,11 @@ typedef struct */ typedef struct { - ble_gap_adv_report_type_t type; /**< Advertising report type. See @ref ble_gap_adv_report_type_t. */ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr is resolved: + ble_gap_adv_report_type_t type; /**< Advertising report type. See @ref ble_gap_adv_report_type_t. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr is resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the peer's identity address. */ - ble_gap_addr_t direct_addr; /**< Contains the target address of the advertising event if + ble_gap_addr_t direct_addr; /**< Contains the target address of the advertising event if @ref ble_gap_adv_report_type_t::directed is set to 1. If the SoftDevice was able to resolve the address, @ref ble_gap_addr_t::addr_id_peer is set to 1 and the direct_addr @@ -1252,28 +1252,28 @@ typedef struct and the SoftDevice was unable to resolve it, the application may try to resolve this address to find out if the advertising event was directed to us. */ - uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising packet was received. + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising packet was received. See @ref BLE_GAP_PHYS. */ - uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising packet was received. + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising packet was received. See @ref BLE_GAP_PHYS. This field is set to @ref BLE_GAP_PHY_NOT_SET if no packets were received on a secondary advertising channel. */ - int8_t tx_power; /**< TX Power reported by the advertiser in the last packet header received. + int8_t tx_power; /**< TX Power reported by the advertiser in the last packet header received. This field is set to @ref BLE_GAP_POWER_LEVEL_INVALID if the last received packet did not contain the Tx Power field. @note TX Power is only included in extended advertising packets. */ - int8_t rssi; /**< Received Signal Strength Indication in dBm of the last packet received. + int8_t rssi; /**< Received Signal Strength Indication in dBm of the last packet received. @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ - uint8_t ch_index; /**< Channel Index on which the last advertising packet is received (0-39). */ - uint8_t set_id; /**< Set ID of the received advertising data. Set ID is not present + uint8_t ch_index; /**< Channel Index on which the last advertising packet is received (0-39). */ + uint8_t set_id; /**< Set ID of the received advertising data. Set ID is not present if set to @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ - uint16_t data_id:12; /**< The advertising data ID of the received advertising data. Data ID + uint16_t data_id : 12; /**< The advertising data ID of the received advertising data. Data ID is not present if @ref ble_gap_evt_adv_report_t::set_id is set to @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ - ble_data_t data; /**< Received advertising or scan response data. If + ble_data_t data; /**< Received advertising or scan response data. If @ref ble_gap_adv_report_type_t::status is not set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the data buffer provided in @ref sd_ble_gap_scan_start is now released. */ - ble_gap_aux_pointer_t aux_pointer; /**< The offset and PHY of the next advertising packet in this extended advertising + ble_gap_aux_pointer_t aux_pointer; /**< The offset and PHY of the next advertising packet in this extended advertising event. @note This field is only set if @ref ble_gap_adv_report_type_t::status is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. */ } ble_gap_evt_adv_report_t; @@ -1282,27 +1282,27 @@ typedef struct /**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */ typedef struct { - uint8_t bond : 1; /**< Perform bonding. */ - uint8_t mitm : 1; /**< Man In The Middle protection requested. */ - uint8_t lesc : 1; /**< LE Secure Connections requested. */ - uint8_t keypress : 1; /**< Generation of keypress notifications requested. */ + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Man In The Middle protection requested. */ + uint8_t lesc : 1; /**< LE Secure Connections requested. */ + uint8_t keypress : 1; /**< Generation of keypress notifications requested. */ } ble_gap_evt_sec_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */ typedef struct { - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ } ble_gap_evt_conn_param_update_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */ typedef struct { - uint8_t adv_handle; /**< Advertising handle for the advertising set which received the Scan Request */ - int8_t rssi; /**< Received Signal Strength Indication in dBm. + uint8_t adv_handle; /**< Advertising handle for the advertising set which received the Scan Request */ + int8_t rssi; /**< Received Signal Strength Indication in dBm. @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the device's identity address. */ } ble_gap_evt_scan_req_report_t; @@ -1310,20 +1310,20 @@ typedef struct /**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST. */ typedef struct { - ble_gap_data_length_params_t peer_params; /**< Peer data length parameters. */ + ble_gap_data_length_params_t peer_params; /**< Peer data length parameters. */ } ble_gap_evt_data_length_update_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE. */ typedef struct { - ble_gap_data_length_params_t effective_params; /**< The effective data length parameters. */ + ble_gap_data_length_params_t effective_params; /**< The effective data length parameters. */ } ble_gap_evt_data_length_update_t; /**@brief Event structure for @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT. */ typedef struct { - int8_t channel_energy[BLE_GAP_CHANNEL_COUNT]; /**< The measured energy on the Bluetooth Low Energy + int8_t channel_energy[BLE_GAP_CHANNEL_COUNT]; /**< The measured energy on the Bluetooth Low Energy channels, in dBm, indexed by Channel Index. If no measurement is available for the given channel, channel_energy is set to @ref BLE_GAP_POWER_LEVEL_INVALID. */ @@ -1332,33 +1332,33 @@ typedef struct /**@brief GAP event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ - union /**< union alternative identified by evt_id in enclosing struct. */ - { - ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ - ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ - ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ - ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ - ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ - ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ - ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. */ - ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ - ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. */ - ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ - ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ - ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ - ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event Parameters. */ - ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */ - ble_gap_evt_adv_set_terminated_t adv_set_terminated; /**< Advertising Set Terminated Event Parameters. */ - ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */ - ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */ - ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report Parameters. */ - ble_gap_evt_phy_update_request_t phy_update_request; /**< PHY Update Request Event Parameters. */ - ble_gap_evt_phy_update_t phy_update; /**< PHY Update Parameters. */ - ble_gap_evt_data_length_update_request_t data_length_update_request; /**< Data Length Update Request Event Parameters. */ - ble_gap_evt_data_length_update_t data_length_update; /**< Data Length Update Event Parameters. */ - ble_gap_evt_qos_channel_survey_report_t qos_channel_survey_report; /**< Quality of Service (QoS) Channel Survey Report Parameters. */ - } params; /**< Event Parameters. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + union /**< union alternative identified by evt_id in enclosing struct. */ + { + ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ + ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ + ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ + ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ + ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ + ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. */ + ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ + ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. */ + ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ + ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ + ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event Parameters. */ + ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */ + ble_gap_evt_adv_set_terminated_t adv_set_terminated; /**< Advertising Set Terminated Event Parameters. */ + ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */ + ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report Parameters. */ + ble_gap_evt_phy_update_request_t phy_update_request; /**< PHY Update Request Event Parameters. */ + ble_gap_evt_phy_update_t phy_update; /**< PHY Update Parameters. */ + ble_gap_evt_data_length_update_request_t data_length_update_request; /**< Data Length Update Request Event Parameters. */ + ble_gap_evt_data_length_update_t data_length_update; /**< Data Length Update Event Parameters. */ + ble_gap_evt_qos_channel_survey_report_t qos_channel_survey_report; /**< Quality of Service (QoS) Channel Survey Report Parameters. */ + } params; /**< Event Parameters. */ } ble_gap_evt_t; @@ -1372,9 +1372,9 @@ typedef struct */ typedef struct { - uint8_t conn_count; /**< The number of concurrent connections the application can create with this configuration. + uint8_t conn_count; /**< The number of concurrent connections the application can create with this configuration. The default and minimum value is @ref BLE_GAP_CONN_COUNT_DEFAULT. */ - uint16_t event_length; /**< The time set aside for this connection on every connection interval in 1.25 ms units. + uint16_t event_length; /**< The time set aside for this connection on every connection interval in 1.25 ms units. The default value is @ref BLE_GAP_EVENT_LENGTH_DEFAULT, the minimum value is @ref BLE_GAP_EVENT_LENGTH_MIN. The event length and the connection interval are the primary parameters for setting the throughput of a connection. @@ -1396,11 +1396,11 @@ typedef struct */ typedef struct { - uint8_t adv_set_count; /**< Maximum number of advertising sets. Default value is @ref BLE_GAP_ADV_SET_COUNT_DEFAULT. */ - uint8_t periph_role_count; /**< Maximum number of connections concurrently acting as a peripheral. Default value is @ref BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT. */ - uint8_t central_role_count; /**< Maximum number of connections concurrently acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT. */ - uint8_t central_sec_count; /**< Number of SMP instances shared between all connections acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT. */ - uint8_t qos_channel_survey_role_available:1; /**< If set, the Quality of Service (QoS) channel survey module is available to the + uint8_t adv_set_count; /**< Maximum number of advertising sets. Default value is @ref BLE_GAP_ADV_SET_COUNT_DEFAULT. */ + uint8_t periph_role_count; /**< Maximum number of connections concurrently acting as a peripheral. Default value is @ref BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT. */ + uint8_t central_role_count; /**< Maximum number of connections concurrently acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT. */ + uint8_t central_sec_count; /**< Number of SMP instances shared between all connections acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT. */ + uint8_t qos_channel_survey_role_available : 1; /**< If set, the Quality of Service (QoS) channel survey module is available to the application using @ref sd_ble_gap_qos_channel_survey_start. */ } ble_gap_cfg_role_count_t; @@ -1435,19 +1435,19 @@ typedef struct */ typedef struct { - ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ - uint8_t vloc:2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ - uint8_t *p_value; /**< Pointer to where the value (device name) is stored or will be stored. */ - uint16_t current_len; /**< Current length in bytes of the memory pointed to by p_value.*/ - uint16_t max_len; /**< Maximum length in bytes of the memory pointed to by p_value.*/ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vloc : 2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t *p_value; /**< Pointer to where the value (device name) is stored or will be stored. */ + uint16_t current_len; /**< Current length in bytes of the memory pointed to by p_value.*/ + uint16_t max_len; /**< Maximum length in bytes of the memory pointed to by p_value.*/ } ble_gap_cfg_device_name_t; /**@brief Configuration structure for GAP configurations. */ typedef union { - ble_gap_cfg_role_count_t role_count_cfg; /**< Role count configuration, cfg_id is @ref BLE_GAP_CFG_ROLE_COUNT. */ - ble_gap_cfg_device_name_t device_name_cfg; /**< Device name configuration, cfg_id is @ref BLE_GAP_CFG_DEVICE_NAME. */ + ble_gap_cfg_role_count_t role_count_cfg; /**< Role count configuration, cfg_id is @ref BLE_GAP_CFG_ROLE_COUNT. */ + ble_gap_cfg_device_name_t device_name_cfg; /**< Device name configuration, cfg_id is @ref BLE_GAP_CFG_DEVICE_NAME. */ } ble_gap_cfg_t; @@ -1476,8 +1476,8 @@ typedef union */ typedef struct { - uint16_t conn_handle; /**< Connection Handle (only applicable for get) */ - uint8_t ch_map[5]; /**< Channel Map (37-bit). */ + uint16_t conn_handle; /**< Connection Handle (only applicable for get) */ + uint8_t ch_map[5]; /**< Channel Map (37-bit). */ } ble_gap_opt_ch_map_t; @@ -1505,9 +1505,9 @@ typedef struct */ typedef struct { - uint16_t conn_handle; /**< Connection Handle */ - uint16_t requested_latency; /**< Requested local connection latency. */ - uint16_t * p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t requested_latency; /**< Requested local connection latency. */ + uint16_t *p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ } ble_gap_opt_local_conn_latency_t; /**@brief Disable slave latency @@ -1524,8 +1524,8 @@ typedef struct */ typedef struct { - uint16_t conn_handle; /**< Connection Handle */ - uint8_t disable : 1; /**< Set to 1 to disable slave latency. Set to 0 enable it again.*/ + uint16_t conn_handle; /**< Connection Handle */ + uint8_t disable : 1; /**< Set to 1 to disable slave latency. Set to 0 enable it again.*/ } ble_gap_opt_slave_latency_disable_t; /**@brief Passkey Option. @@ -1541,7 +1541,7 @@ typedef struct */ typedef struct { - uint8_t const * p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ + uint8_t const *p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ } ble_gap_opt_passkey_t; @@ -1562,7 +1562,7 @@ typedef struct */ typedef struct { - uint8_t enable : 1; /**< Enable compatibility mode 1.*/ + uint8_t enable : 1; /**< Enable compatibility mode 1.*/ } ble_gap_opt_compat_mode_1_t; @@ -1587,19 +1587,19 @@ typedef struct */ typedef struct { - uint16_t conn_handle; /**< Connection Handle */ - uint16_t auth_payload_timeout; /**< Requested timeout in 10 ms unit, see @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT. */ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t auth_payload_timeout; /**< Requested timeout in 10 ms unit, see @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT. */ } ble_gap_opt_auth_payload_timeout_t; /**@brief Option structure for GAP options. */ typedef union { - ble_gap_opt_ch_map_t ch_map; /**< Parameters for the Channel Map option. */ - ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Parameters for the Local connection latency option */ - ble_gap_opt_passkey_t passkey; /**< Parameters for the Passkey option.*/ - ble_gap_opt_compat_mode_1_t compat_mode_1; /**< Parameters for the compatibility mode 1 option.*/ - ble_gap_opt_auth_payload_timeout_t auth_payload_timeout; /**< Parameters for the authenticated payload timeout option.*/ - ble_gap_opt_slave_latency_disable_t slave_latency_disable; /**< Parameters for the Disable slave latency option */ + ble_gap_opt_ch_map_t ch_map; /**< Parameters for the Channel Map option. */ + ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Parameters for the Local connection latency option */ + ble_gap_opt_passkey_t passkey; /**< Parameters for the Passkey option.*/ + ble_gap_opt_compat_mode_1_t compat_mode_1; /**< Parameters for the compatibility mode 1 option.*/ + ble_gap_opt_auth_payload_timeout_t auth_payload_timeout; /**< Parameters for the authenticated payload timeout option.*/ + ble_gap_opt_slave_latency_disable_t slave_latency_disable; /**< Parameters for the Disable slave latency option */ } ble_gap_opt_t; /**@} */ @@ -1648,7 +1648,7 @@ SVCALL(SD_BLE_GAP_ADDR_SET, uint32_t, sd_ble_gap_addr_set(ble_gap_addr_t const * * @retval ::NRF_SUCCESS Address successfully retrieved. * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. */ -SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr)); +SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t * p_addr)); /**@brief Get the Bluetooth device address used by the advertiser. @@ -1667,7 +1667,7 @@ SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. * @retval ::NRF_ERROR_INVALID_STATE The advertising set is currently not advertising. */ -SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr)); +SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t * p_addr)); /**@brief Set the active whitelist in the SoftDevice. @@ -1693,7 +1693,7 @@ SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_ha * @retval ::NRF_ERROR_DATA_SIZE The given whitelist size is invalid (zero or too large); this can only return when * pp_wl_addrs is not NULL. */ -SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const * const * pp_wl_addrs, uint8_t len)); +SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const *const *pp_wl_addrs, uint8_t len)); /**@brief Set device identity list. @@ -1724,7 +1724,7 @@ SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr * @retval ::NRF_ERROR_DATA_SIZE The given device identity list size invalid (zero or too large); this can * only return when pp_id_keys is not NULL. */ -SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const * const * pp_id_keys, ble_gap_irk_t const * const * pp_local_irks, uint8_t len)); +SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const *const *pp_id_keys, ble_gap_irk_t const *const *pp_local_irks, uint8_t len)); /**@brief Set privacy settings. @@ -1762,7 +1762,7 @@ SVCALL(SD_BLE_GAP_PRIVACY_SET, uint32_t, sd_ble_gap_privacy_set(ble_gap_privacy_ * @retval ::NRF_ERROR_INVALID_ADDR The pointer given for returning the privacy settings may be NULL or invalid. * Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer. */ -SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t *p_privacy_params)); +SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t * p_privacy_params)); /**@brief Configure an advertising set. Set, clear or update advertising and scan response data. @@ -1809,7 +1809,7 @@ SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_ * existing advertising handle instead. * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied. */ -SVCALL(SD_BLE_GAP_ADV_SET_CONFIGURE, uint32_t, sd_ble_gap_adv_set_configure(uint8_t *p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params)); +SVCALL(SD_BLE_GAP_ADV_SET_CONFIGURE, uint32_t, sd_ble_gap_adv_set_configure(uint8_t * p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params)); /**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). @@ -1975,7 +1975,7 @@ SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t a * @retval ::NRF_SUCCESS Appearance value retrieved successfully. * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. */ -SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance)); +SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t * p_appearance)); /**@brief Set GAP Peripheral Preferred Connection Parameters. @@ -1996,7 +1996,7 @@ SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully. * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. */ -SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params)); +SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t * p_conn_params)); /**@brief Set GAP device name. @@ -2031,7 +2031,7 @@ SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. */ -SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len)); +SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t * p_dev_name, uint16_t * p_len)); /**@brief Initiate the GAP Authentication procedure. @@ -2255,7 +2255,7 @@ SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. */ -SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own)); +SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t * p_oobd_own)); /**@brief Provide the OOB data sent/received out of band. * @@ -2354,7 +2354,7 @@ SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t c * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. */ -SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec)); +SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t * p_conn_sec)); /**@brief Start reporting the received signal strength to the application. @@ -2421,7 +2421,7 @@ SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing. */ -SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi, uint8_t *p_ch_index)); +SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t * p_rssi, uint8_t * p_ch_index)); /**@brief Start or continue scanning (GAP Discovery procedure, Observer Procedure). @@ -2474,7 +2474,7 @@ SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available. * Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again */ -SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const * p_adv_report_buffer)); +SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const *p_adv_report_buffer)); /**@brief Stop scanning (GAP Discovery procedure, Observer Procedure). @@ -2637,7 +2637,7 @@ SVCALL(SD_BLE_GAP_PHY_UPDATE, uint32_t, sd_ble_gap_phy_update(uint16_t conn_hand * @retval ::NRF_ERROR_BUSY Peer has already initiated a Data Length Update Procedure. Process the * pending @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST event to respond. */ -SVCALL(SD_BLE_GAP_DATA_LENGTH_UPDATE, uint32_t, sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t *p_dl_limitation)); +SVCALL(SD_BLE_GAP_DATA_LENGTH_UPDATE, uint32_t, sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t * p_dl_limitation)); /**@brief Start the Quality of Service (QoS) channel survey module. * diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gatt.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gatt.h index 9cb577cc8..45b78a75e 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gatt.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gatt.h @@ -189,7 +189,7 @@ extern "C" { */ typedef struct { - uint16_t att_mtu; /**< Maximum size of ATT packet the SoftDevice can send or receive. + uint16_t att_mtu; /**< Maximum size of ATT packet the SoftDevice can send or receive. The default and minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. @mscs @mmsc{@ref BLE_GATTC_MTU_EXCHANGE} @@ -201,22 +201,22 @@ typedef struct /**@brief GATT Characteristic Properties. */ typedef struct { - /* Standard properties */ - uint8_t broadcast :1; /**< Broadcasting of the value permitted. */ - uint8_t read :1; /**< Reading the value permitted. */ - uint8_t write_wo_resp :1; /**< Writing the value with Write Command permitted. */ - uint8_t write :1; /**< Writing the value with Write Request permitted. */ - uint8_t notify :1; /**< Notification of the value permitted. */ - uint8_t indicate :1; /**< Indications of the value permitted. */ - uint8_t auth_signed_wr :1; /**< Writing the value with Signed Write Command permitted. */ + /* Standard properties */ + uint8_t broadcast : 1;/**< Broadcasting of the value permitted. */ + uint8_t read : 1;/**< Reading the value permitted. */ + uint8_t write_wo_resp : 1;/**< Writing the value with Write Command permitted. */ + uint8_t write : 1;/**< Writing the value with Write Request permitted. */ + uint8_t notify : 1;/**< Notification of the value permitted. */ + uint8_t indicate : 1;/**< Indications of the value permitted. */ + uint8_t auth_signed_wr : 1;/**< Writing the value with Signed Write Command permitted. */ } ble_gatt_char_props_t; /**@brief GATT Characteristic Extended Properties. */ typedef struct { - /* Extended properties */ - uint8_t reliable_wr :1; /**< Writing the value with Queued Write operations permitted. */ - uint8_t wr_aux :1; /**< Writing the Characteristic User Description descriptor permitted. */ + /* Extended properties */ + uint8_t reliable_wr : 1;/**< Writing the value with Queued Write operations permitted. */ + uint8_t wr_aux : 1;/**< Writing the Characteristic User Description descriptor permitted. */ } ble_gatt_char_ext_props_t; /** @} */ diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gattc.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gattc.h index 7fb392024..c4c8322ca 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gattc.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gattc.h @@ -64,17 +64,17 @@ extern "C" { /**@brief GATTC API SVC numbers. */ enum BLE_GATTC_SVCS { - SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ - SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ - SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ - SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ - SD_BLE_GATTC_ATTR_INFO_DISCOVER, /**< Attribute Information Discovery. */ - SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ - SD_BLE_GATTC_READ, /**< Generic read. */ - SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ - SD_BLE_GATTC_WRITE, /**< Generic write. */ - SD_BLE_GATTC_HV_CONFIRM, /**< Handle Value Confirmation. */ - SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. */ + SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ + SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ + SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ + SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ + SD_BLE_GATTC_ATTR_INFO_DISCOVER, /**< Attribute Information Discovery. */ + SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ + SD_BLE_GATTC_READ, /**< Generic read. */ + SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ + SD_BLE_GATTC_WRITE, /**< Generic write. */ + SD_BLE_GATTC_HV_CONFIRM, /**< Handle Value Confirmation. */ + SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. */ }; /** @@ -82,19 +82,19 @@ enum BLE_GATTC_SVCS */ enum BLE_GATTC_EVTS { - BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t. */ - BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. \n See @ref ble_gattc_evt_rel_disc_rsp_t. */ - BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. \n See @ref ble_gattc_evt_char_disc_rsp_t. */ - BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. \n See @ref ble_gattc_evt_desc_disc_rsp_t. */ - BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, /**< Attribute Information Response event. \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */ - BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t. */ - BLE_GATTC_EVT_READ_RSP, /**< Read Response event. \n See @ref ble_gattc_evt_read_rsp_t. */ - BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. \n See @ref ble_gattc_evt_char_vals_read_rsp_t. */ - BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. \n See @ref ble_gattc_evt_write_rsp_t. */ - BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm. \n See @ref ble_gattc_evt_hvx_t. */ - BLE_GATTC_EVT_EXCHANGE_MTU_RSP, /**< Exchange MTU Response event. \n See @ref ble_gattc_evt_exchange_mtu_rsp_t. */ - BLE_GATTC_EVT_TIMEOUT, /**< Timeout event. \n See @ref ble_gattc_evt_timeout_t. */ - BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE /**< Write without Response transmission complete. \n See @ref ble_gattc_evt_write_cmd_tx_complete_t. */ + BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t. */ + BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. \n See @ref ble_gattc_evt_rel_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. \n See @ref ble_gattc_evt_char_disc_rsp_t. */ + BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. \n See @ref ble_gattc_evt_desc_disc_rsp_t. */ + BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, /**< Attribute Information Response event. \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t. */ + BLE_GATTC_EVT_READ_RSP, /**< Read Response event. \n See @ref ble_gattc_evt_read_rsp_t. */ + BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. \n See @ref ble_gattc_evt_char_vals_read_rsp_t. */ + BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. \n See @ref ble_gattc_evt_write_rsp_t. */ + BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm. \n See @ref ble_gattc_evt_hvx_t. */ + BLE_GATTC_EVT_EXCHANGE_MTU_RSP, /**< Exchange MTU Response event. \n See @ref ble_gattc_evt_exchange_mtu_rsp_t. */ + BLE_GATTC_EVT_TIMEOUT, /**< Timeout event. \n See @ref ble_gattc_evt_timeout_t. */ + BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE /**< Write without Response transmission complete. \n See @ref ble_gattc_evt_write_cmd_tx_complete_t. */ }; /** @} */ @@ -128,138 +128,138 @@ enum BLE_GATTC_EVTS */ typedef struct { - uint8_t write_cmd_tx_queue_size; /**< The guaranteed minimum number of Write without Response that can be queued for transmission. + uint8_t write_cmd_tx_queue_size; /**< The guaranteed minimum number of Write without Response that can be queued for transmission. The default value is @ref BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT */ } ble_gattc_conn_cfg_t; /**@brief Operation Handle Range. */ typedef struct { - uint16_t start_handle; /**< Start Handle. */ - uint16_t end_handle; /**< End Handle. */ + uint16_t start_handle; /**< Start Handle. */ + uint16_t end_handle; /**< End Handle. */ } ble_gattc_handle_range_t; /**@brief GATT service. */ typedef struct { - ble_uuid_t uuid; /**< Service UUID. */ - ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ + ble_uuid_t uuid; /**< Service UUID. */ + ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ } ble_gattc_service_t; /**@brief GATT include. */ typedef struct { - uint16_t handle; /**< Include Handle. */ - ble_gattc_service_t included_srvc; /**< Handle of the included service. */ + uint16_t handle; /**< Include Handle. */ + ble_gattc_service_t included_srvc; /**< Handle of the included service. */ } ble_gattc_include_t; /**@brief GATT characteristic. */ typedef struct { - ble_uuid_t uuid; /**< Characteristic UUID. */ - ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ - uint8_t char_ext_props : 1; /**< Extended properties present. */ - uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ - uint16_t handle_value; /**< Handle of the Characteristic Value. */ + ble_uuid_t uuid; /**< Characteristic UUID. */ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + uint8_t char_ext_props : 1; /**< Extended properties present. */ + uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ + uint16_t handle_value; /**< Handle of the Characteristic Value. */ } ble_gattc_char_t; /**@brief GATT descriptor. */ typedef struct { - uint16_t handle; /**< Descriptor Handle. */ - ble_uuid_t uuid; /**< Descriptor UUID. */ + uint16_t handle; /**< Descriptor Handle. */ + ble_uuid_t uuid; /**< Descriptor UUID. */ } ble_gattc_desc_t; /**@brief Write Parameters. */ typedef struct { - uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ - uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ - uint16_t handle; /**< Handle to the attribute to be written. */ - uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ - uint16_t len; /**< Length of data in bytes. */ - uint8_t const *p_value; /**< Pointer to the value data. */ + uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ + uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ + uint16_t handle; /**< Handle to the attribute to be written. */ + uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ + uint16_t len; /**< Length of data in bytes. */ + uint8_t const *p_value; /**< Pointer to the value data. */ } ble_gattc_write_params_t; /**@brief Attribute Information for 16-bit Attribute UUID. */ typedef struct { - uint16_t handle; /**< Attribute handle. */ - ble_uuid_t uuid; /**< 16-bit Attribute UUID. */ + uint16_t handle; /**< Attribute handle. */ + ble_uuid_t uuid; /**< 16-bit Attribute UUID. */ } ble_gattc_attr_info16_t; /**@brief Attribute Information for 128-bit Attribute UUID. */ typedef struct { - uint16_t handle; /**< Attribute handle. */ - ble_uuid128_t uuid; /**< 128-bit Attribute UUID. */ + uint16_t handle; /**< Attribute handle. */ + ble_uuid128_t uuid; /**< 128-bit Attribute UUID. */ } ble_gattc_attr_info128_t; /**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */ typedef struct { - uint16_t count; /**< Service count. */ - ble_gattc_service_t services[1]; /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t count; /**< Service count. */ + ble_gattc_service_t services[1]; /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_prim_srvc_disc_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */ typedef struct { - uint16_t count; /**< Include count. */ - ble_gattc_include_t includes[1]; /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t count; /**< Include count. */ + ble_gattc_include_t includes[1]; /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_rel_disc_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */ typedef struct { - uint16_t count; /**< Characteristic count. */ - ble_gattc_char_t chars[1]; /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t count; /**< Characteristic count. */ + ble_gattc_char_t chars[1]; /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_char_disc_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */ typedef struct { - uint16_t count; /**< Descriptor count. */ - ble_gattc_desc_t descs[1]; /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t count; /**< Descriptor count. */ + ble_gattc_desc_t descs[1]; /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_desc_disc_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */ typedef struct { - uint16_t count; /**< Attribute count. */ - uint8_t format; /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */ - union { - ble_gattc_attr_info16_t attr_info16[1]; /**< Attribute information for 16-bit Attribute UUID. + uint16_t count; /**< Attribute count. */ + uint8_t format; /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */ + union { + ble_gattc_attr_info16_t attr_info16[1]; /**< Attribute information for 16-bit Attribute UUID. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ - ble_gattc_attr_info128_t attr_info128[1]; /**< Attribute information for 128-bit Attribute UUID. + ble_gattc_attr_info128_t attr_info128[1]; /**< Attribute information for 128-bit Attribute UUID. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ - } info; /**< Attribute information union. */ + } info; /**< Attribute information union. */ } ble_gattc_evt_attr_info_disc_rsp_t; /**@brief GATT read by UUID handle value pair. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - uint8_t *p_value; /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */ + uint16_t handle; /**< Attribute Handle. */ + uint8_t *p_value; /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */ } ble_gattc_handle_value_t; /**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */ typedef struct { - uint16_t count; /**< Handle-Value Pair Count. */ - uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ - uint8_t handle_value[1]; /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter. + uint16_t count; /**< Handle-Value Pair Count. */ + uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ + uint8_t handle_value[1]; /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_char_val_by_uuid_read_rsp_t; @@ -267,82 +267,82 @@ typedef struct /**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - uint16_t offset; /**< Offset of the attribute data. */ - uint16_t len; /**< Attribute data length. */ - uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t handle; /**< Attribute Handle. */ + uint16_t offset; /**< Offset of the attribute data. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_read_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */ typedef struct { - uint16_t len; /**< Concatenated Attribute values length. */ - uint8_t values[1]; /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t len; /**< Concatenated Attribute values length. */ + uint8_t values[1]; /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_char_vals_read_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ - uint16_t offset; /**< Data offset. */ - uint16_t len; /**< Data length. */ - uint8_t data[1]; /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t handle; /**< Attribute Handle. */ + uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ + uint16_t offset; /**< Data offset. */ + uint16_t len; /**< Data length. */ + uint8_t data[1]; /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_write_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */ typedef struct { - uint16_t handle; /**< Handle to which the HVx operation applies. */ - uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ - uint16_t len; /**< Attribute data length. */ - uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t handle; /**< Handle to which the HVx operation applies. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_hvx_t; /**@brief Event structure for @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. */ typedef struct { - uint16_t server_rx_mtu; /**< Server RX MTU size. */ + uint16_t server_rx_mtu; /**< Server RX MTU size. */ } ble_gattc_evt_exchange_mtu_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */ typedef struct { - uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ } ble_gattc_evt_timeout_t; /**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE. */ typedef struct { - uint8_t count; /**< Number of write without response transmissions completed. */ + uint8_t count; /**< Number of write without response transmissions completed. */ } ble_gattc_evt_write_cmd_tx_complete_t; /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ - uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ - union - { - ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ - ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ - ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ - ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ - ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ - ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ - ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ - ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ - ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ - ble_gattc_evt_exchange_mtu_rsp_t exchange_mtu_rsp; /**< Exchange MTU Response Event Parameters. */ - ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ - ble_gattc_evt_attr_info_disc_rsp_t attr_info_disc_rsp; /**< Attribute Information Discovery Event Parameters. */ - ble_gattc_evt_write_cmd_tx_complete_t write_cmd_tx_complete; /**< Write without Response transmission complete Event Parameters. */ - } params; /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ + union + { + ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ + ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ + ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ + ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ + ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ + ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ + ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ + ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ + ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ + ble_gattc_evt_exchange_mtu_rsp_t exchange_mtu_rsp; /**< Exchange MTU Response Event Parameters. */ + ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gattc_evt_attr_info_disc_rsp_t attr_info_disc_rsp; /**< Attribute Information Discovery Event Parameters. */ + ble_gattc_evt_write_cmd_tx_complete_t write_cmd_tx_complete; /**< Write without Response transmission complete Event Parameters. */ + } params; /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */ } ble_gattc_evt_t; /** @} */ @@ -621,7 +621,7 @@ SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_ * @retval ::NRF_ERROR_BUSY Client procedure already in progress. * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. */ -SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range)); +SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); /**@brief Start an ATT_MTU exchange by sending an Exchange MTU Request to the server. * @@ -685,22 +685,18 @@ __STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gat #ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter) -{ - uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len; - uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value; - uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first; - - if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count) - { - p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0]; - p_iter->p_value = p_next + sizeof(uint16_t); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_NOT_FOUND; - } +__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter) { + uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len; + uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value; + uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first; + + if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count) { + p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0]; + p_iter->p_value = p_next + sizeof(uint16_t); + return NRF_SUCCESS; + } else { + return NRF_ERROR_NOT_FOUND; + } } #endif /* SUPPRESS_INLINE_IMPLEMENTATION */ diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gatts.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gatts.h index 394d8d189..1a7a51ac1 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gatts.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_gatts.h @@ -67,20 +67,20 @@ extern "C" { */ enum BLE_GATTS_SVCS { - SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ - SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ - SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ - SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ - SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ - SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ - SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ - SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ - SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ - SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ - SD_BLE_GATTS_SYS_ATTR_GET, /**< Retrieve the persistent system attributes. */ - SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, /**< Retrieve the first valid user handle. */ - SD_BLE_GATTS_ATTR_GET, /**< Retrieve the UUID and/or metadata of an attribute. */ - SD_BLE_GATTS_EXCHANGE_MTU_REPLY /**< Reply to Exchange MTU Request. */ + SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ + SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ + SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ + SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ + SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ + SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ + SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ + SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ + SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ + SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ + SD_BLE_GATTS_SYS_ATTR_GET, /**< Retrieve the persistent system attributes. */ + SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, /**< Retrieve the first valid user handle. */ + SD_BLE_GATTS_ATTR_GET, /**< Retrieve the UUID and/or metadata of an attribute. */ + SD_BLE_GATTS_EXCHANGE_MTU_REPLY /**< Reply to Exchange MTU Request. */ }; /** @@ -88,14 +88,14 @@ enum BLE_GATTS_SVCS */ enum BLE_GATTS_EVTS { - BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. \n See @ref ble_gatts_evt_write_t. */ - BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */ - BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending. \n Respond with @ref sd_ble_gatts_sys_attr_set. \n See @ref ble_gatts_evt_sys_attr_missing_t. */ - BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. \n See @ref ble_gatts_evt_hvc_t. */ - BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. \n No additional event structure applies. */ - BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */ - BLE_GATTS_EVT_TIMEOUT, /**< Peer failed to respond to an ATT request in time. \n See @ref ble_gatts_evt_timeout_t. */ - BLE_GATTS_EVT_HVN_TX_COMPLETE /**< Handle Value Notification transmission complete. \n See @ref ble_gatts_evt_hvn_tx_complete_t. */ + BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. \n See @ref ble_gatts_evt_write_t. */ + BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */ + BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending. \n Respond with @ref sd_ble_gatts_sys_attr_set. \n See @ref ble_gatts_evt_sys_attr_missing_t. */ + BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. \n See @ref ble_gatts_evt_hvc_t. */ + BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. \n No additional event structure applies. */ + BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */ + BLE_GATTS_EVT_TIMEOUT, /**< Peer failed to respond to an ATT request in time. \n See @ref ble_gatts_evt_timeout_t. */ + BLE_GATTS_EVT_HVN_TX_COMPLETE /**< Handle Value Notification transmission complete. \n See @ref ble_gatts_evt_hvn_tx_complete_t. */ }; /**@brief GATTS Configuration IDs. @@ -104,8 +104,8 @@ enum BLE_GATTS_EVTS */ enum BLE_GATTS_CFGS { - BLE_GATTS_CFG_SERVICE_CHANGED = BLE_GATTS_CFG_BASE, /**< Service changed configuration. */ - BLE_GATTS_CFG_ATTR_TAB_SIZE, /**< Attribute table size configuration. */ + BLE_GATTS_CFG_SERVICE_CHANGED = BLE_GATTS_CFG_BASE, /**< Service changed configuration. */ + BLE_GATTS_CFG_ATTR_TAB_SIZE, /**< Attribute table size configuration. */ }; /** @} */ @@ -207,31 +207,31 @@ enum BLE_GATTS_CFGS */ typedef struct { - uint8_t hvn_tx_queue_size; /**< Minimum guaranteed number of Handle Value Notifications that can be queued for transmission. + uint8_t hvn_tx_queue_size; /**< Minimum guaranteed number of Handle Value Notifications that can be queued for transmission. The default value is @ref BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT */ } ble_gatts_conn_cfg_t; /**@brief Attribute metadata. */ typedef struct { - ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ - ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ - uint8_t vlen :1; /**< Variable length attribute. */ - uint8_t vloc :2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ - uint8_t rd_auth :1; /**< Read authorization and value will be requested from the application on every read operation. */ - uint8_t wr_auth :1; /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */ + ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vlen : 1; /**< Variable length attribute. */ + uint8_t vloc : 2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t rd_auth : 1; /**< Read authorization and value will be requested from the application on every read operation. */ + uint8_t wr_auth : 1; /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */ } ble_gatts_attr_md_t; /**@brief GATT Attribute. */ typedef struct { - ble_uuid_t const *p_uuid; /**< Pointer to the attribute UUID. */ - ble_gatts_attr_md_t const *p_attr_md; /**< Pointer to the attribute metadata structure. */ - uint16_t init_len; /**< Initial attribute value length in bytes. */ - uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ - uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ - uint8_t *p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer + ble_uuid_t const *p_uuid; /**< Pointer to the attribute UUID. */ + ble_gatts_attr_md_t const *p_attr_md; /**< Pointer to the attribute metadata structure. */ + uint16_t init_len; /**< Initial attribute value length in bytes. */ + uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ + uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ + uint8_t *p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location. The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/ } ble_gatts_attr_t; @@ -239,9 +239,9 @@ typedef struct /**@brief GATT Attribute Value. */ typedef struct { - uint16_t len; /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/ - uint16_t offset; /**< Attribute value offset. */ - uint8_t *p_value; /**< Pointer to where value is stored or will be stored. + uint16_t len; /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/ + uint16_t offset; /**< Attribute value offset. */ + uint8_t *p_value; /**< Pointer to where value is stored or will be stored. If value is stored in user memory, only the attribute length is updated when p_value == NULL. Set to NULL when reading to obtain the complete length of the attribute value */ } ble_gatts_value_t; @@ -250,75 +250,75 @@ typedef struct /**@brief GATT Characteristic Presentation Format. */ typedef struct { - uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ - int8_t exponent; /**< Exponent for integer data types. */ - uint16_t unit; /**< Unit from Bluetooth Assigned Numbers. */ - uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ - uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ + uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ + int8_t exponent; /**< Exponent for integer data types. */ + uint16_t unit; /**< Unit from Bluetooth Assigned Numbers. */ + uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ + uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ } ble_gatts_char_pf_t; /**@brief GATT Characteristic metadata. */ typedef struct { - ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ - ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ - uint8_t const *p_char_user_desc; /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */ - uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ - uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ - ble_gatts_char_pf_t const *p_char_pf; /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */ - ble_gatts_attr_md_t const *p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ - ble_gatts_attr_md_t const *p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ - ble_gatts_attr_md_t const *p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ + uint8_t const *p_char_user_desc; /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */ + uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ + uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ + ble_gatts_char_pf_t const *p_char_pf; /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */ + ble_gatts_attr_md_t const *p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ } ble_gatts_char_md_t; /**@brief GATT Characteristic Definition Handles. */ typedef struct { - uint16_t value_handle; /**< Handle to the characteristic value. */ - uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ - uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ - uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t value_handle; /**< Handle to the characteristic value. */ + uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ } ble_gatts_char_handles_t; /**@brief GATT HVx parameters. */ typedef struct { - uint16_t handle; /**< Characteristic Value Handle. */ - uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ - uint16_t offset; /**< Offset within the attribute value. */ - uint16_t *p_len; /**< Length in bytes to be written, length in bytes written after return. */ - uint8_t const *p_data; /**< Actual data content, use NULL to use the current attribute value. */ + uint16_t handle; /**< Characteristic Value Handle. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t offset; /**< Offset within the attribute value. */ + uint16_t *p_len; /**< Length in bytes to be written, length in bytes written after return. */ + uint8_t const *p_data; /**< Actual data content, use NULL to use the current attribute value. */ } ble_gatts_hvx_params_t; /**@brief GATT Authorization parameters. */ typedef struct { - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ - uint8_t update : 1; /**< If set, data supplied in p_data will be used to update the attribute value. + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint8_t update : 1; /**< If set, data supplied in p_data will be used to update the attribute value. Please note that for @ref BLE_GATTS_AUTHORIZE_TYPE_WRITE operations this bit must always be set, as the data to be written needs to be stored and later provided by the application. */ - uint16_t offset; /**< Offset of the attribute value being updated. */ - uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ - uint8_t const *p_data; /**< Pointer to new value used to update the attribute value. */ + uint16_t offset; /**< Offset of the attribute value being updated. */ + uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ + uint8_t const *p_data; /**< Pointer to new value used to update the attribute value. */ } ble_gatts_authorize_params_t; /**@brief GATT Read or Write Authorize Reply parameters. */ typedef struct { - uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ - union { - ble_gatts_authorize_params_t read; /**< Read authorization parameters. */ - ble_gatts_authorize_params_t write; /**< Write authorization parameters. */ - } params; /**< Reply Parameters. */ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_authorize_params_t read; /**< Read authorization parameters. */ + ble_gatts_authorize_params_t write; /**< Write authorization parameters. */ + } params; /**< Reply Parameters. */ } ble_gatts_rw_authorize_reply_params_t; /**@brief Service Changed Inclusion configuration parameters, set with @ref sd_ble_cfg_set. */ typedef struct { - uint8_t service_changed : 1; /**< If 1, include the Service Changed characteristic in the Attribute Table. Default is @ref BLE_GATTS_SERVICE_CHANGED_DEFAULT. */ + uint8_t service_changed : 1; /**< If 1, include the Service Changed characteristic in the Attribute Table. Default is @ref BLE_GATTS_SERVICE_CHANGED_DEFAULT. */ } ble_gatts_cfg_service_changed_t; /**@brief Attribute table size configuration parameters, set with @ref sd_ble_cfg_set. @@ -330,93 +330,93 @@ typedef struct */ typedef struct { - uint32_t attr_tab_size; /**< Attribute table size. Default is @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT, minimum is @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. */ + uint32_t attr_tab_size; /**< Attribute table size. Default is @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT, minimum is @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. */ } ble_gatts_cfg_attr_tab_size_t; /**@brief Config structure for GATTS configurations. */ typedef union { - ble_gatts_cfg_service_changed_t service_changed; /**< Include service changed characteristic, cfg_id is @ref BLE_GATTS_CFG_SERVICE_CHANGED. */ - ble_gatts_cfg_attr_tab_size_t attr_tab_size; /**< Attribute table size, cfg_id is @ref BLE_GATTS_CFG_ATTR_TAB_SIZE. */ + ble_gatts_cfg_service_changed_t service_changed; /**< Include service changed characteristic, cfg_id is @ref BLE_GATTS_CFG_SERVICE_CHANGED. */ + ble_gatts_cfg_attr_tab_size_t attr_tab_size; /**< Attribute table size, cfg_id is @ref BLE_GATTS_CFG_ATTR_TAB_SIZE. */ } ble_gatts_cfg_t; /**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - ble_uuid_t uuid; /**< Attribute UUID. */ - uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ - uint8_t auth_required; /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalize the writing operation. */ - uint16_t offset; /**< Offset for the write operation. */ - uint16_t len; /**< Length of the received data. */ - uint8_t data[1]; /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ + uint8_t auth_required; /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalize the writing operation. */ + uint16_t offset; /**< Offset for the write operation. */ + uint16_t len; /**< Length of the received data. */ + uint8_t data[1]; /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gatts_evt_write_t; /**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - ble_uuid_t uuid; /**< Attribute UUID. */ - uint16_t offset; /**< Offset for the read operation. */ + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint16_t offset; /**< Offset for the read operation. */ } ble_gatts_evt_read_t; /**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */ typedef struct { - uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ - union { - ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ - ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ - } request; /**< Request Parameters. */ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ + ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ + } request; /**< Request Parameters. */ } ble_gatts_evt_rw_authorize_request_t; /**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */ typedef struct { - uint8_t hint; /**< Hint (currently unused). */ + uint8_t hint; /**< Hint (currently unused). */ } ble_gatts_evt_sys_attr_missing_t; /**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ + uint16_t handle; /**< Attribute Handle. */ } ble_gatts_evt_hvc_t; /**@brief Event structure for @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST. */ typedef struct { - uint16_t client_rx_mtu; /**< Client RX MTU size. */ + uint16_t client_rx_mtu; /**< Client RX MTU size. */ } ble_gatts_evt_exchange_mtu_request_t; /**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */ typedef struct { - uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ } ble_gatts_evt_timeout_t; /**@brief Event structure for @ref BLE_GATTS_EVT_HVN_TX_COMPLETE. */ typedef struct { - uint8_t count; /**< Number of notification transmissions completed. */ + uint8_t count; /**< Number of notification transmissions completed. */ } ble_gatts_evt_hvn_tx_complete_t; /**@brief GATTS event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which the event occurred. */ - union - { - ble_gatts_evt_write_t write; /**< Write Event Parameters. */ - ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ - ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ - ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ - ble_gatts_evt_exchange_mtu_request_t exchange_mtu_request; /**< Exchange MTU Request Event Parameters. */ - ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ - ble_gatts_evt_hvn_tx_complete_t hvn_tx_complete; /**< Handle Value Notification transmission complete Event Parameters. */ - } params; /**< Event Parameters. */ + uint16_t conn_handle; /**< Connection Handle on which the event occurred. */ + union + { + ble_gatts_evt_write_t write; /**< Write Event Parameters. */ + ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ + ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ + ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ + ble_gatts_evt_exchange_mtu_request_t exchange_mtu_request; /**< Exchange MTU Request Event Parameters. */ + ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ + ble_gatts_evt_hvn_tx_complete_t hvn_tx_complete; /**< Handle Value Notification transmission complete Event Parameters. */ + } params; /**< Event Parameters. */ } ble_gatts_evt_t; /** @} */ @@ -443,7 +443,7 @@ typedef struct * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. */ -SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle)); +SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t * p_handle)); /**@brief Add an include declaration to the Attribute Table. @@ -469,7 +469,7 @@ SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. */ -SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle)); +SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t * p_include_handle)); /**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table. @@ -498,7 +498,7 @@ SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t ser * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. */ -SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles)); +SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t * p_handles)); /**@brief Add a descriptor to the Attribute Table. @@ -521,7 +521,7 @@ SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_ad * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. */ -SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle)); +SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t * p_handle)); /**@brief Set the value of a given attribute. * @@ -544,7 +544,7 @@ SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16 * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. */ -SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); +SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t * p_value)); /**@brief Get the value of a given attribute. * @@ -568,7 +568,7 @@ SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_ha * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. */ -SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); +SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t * p_value)); /**@brief Notify or Indicate an attribute value. * @@ -779,7 +779,7 @@ SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t c * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer. * @retval ::NRF_ERROR_NOT_FOUND No system attributes found. */ -SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags)); +SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t * p_sys_attr_data, uint16_t * p_len, uint32_t flags)); /**@brief Retrieve the first valid user attribute handle. @@ -789,7 +789,7 @@ SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t c * @retval ::NRF_SUCCESS Successfully retrieved the handle. * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. */ -SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle)); +SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t * p_handle)); /**@brief Retrieve the attribute UUID and/or metadata. * diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_l2cap.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_l2cap.h index edaf6641f..d04bec3fb 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_l2cap.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_l2cap.h @@ -84,31 +84,31 @@ extern "C" { /**@brief L2CAP API SVC numbers. */ enum BLE_L2CAP_SVCS { - SD_BLE_L2CAP_CH_SETUP = BLE_L2CAP_SVC_BASE + 0, /**< Set up an L2CAP channel. */ - SD_BLE_L2CAP_CH_RELEASE = BLE_L2CAP_SVC_BASE + 1, /**< Release an L2CAP channel. */ - SD_BLE_L2CAP_CH_RX = BLE_L2CAP_SVC_BASE + 2, /**< Receive an SDU on an L2CAP channel. */ - SD_BLE_L2CAP_CH_TX = BLE_L2CAP_SVC_BASE + 3, /**< Transmit an SDU on an L2CAP channel. */ - SD_BLE_L2CAP_CH_FLOW_CONTROL = BLE_L2CAP_SVC_BASE + 4, /**< Advanced SDU reception flow control. */ + SD_BLE_L2CAP_CH_SETUP = BLE_L2CAP_SVC_BASE + 0,/**< Set up an L2CAP channel. */ + SD_BLE_L2CAP_CH_RELEASE = BLE_L2CAP_SVC_BASE + 1,/**< Release an L2CAP channel. */ + SD_BLE_L2CAP_CH_RX = BLE_L2CAP_SVC_BASE + 2,/**< Receive an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_TX = BLE_L2CAP_SVC_BASE + 3,/**< Transmit an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_FLOW_CONTROL = BLE_L2CAP_SVC_BASE + 4, /**< Advanced SDU reception flow control. */ }; /**@brief L2CAP Event IDs. */ enum BLE_L2CAP_EVTS { - BLE_L2CAP_EVT_CH_SETUP_REQUEST = BLE_L2CAP_EVT_BASE + 0, /**< L2CAP Channel Setup Request event. + BLE_L2CAP_EVT_CH_SETUP_REQUEST = BLE_L2CAP_EVT_BASE + 0, /**< L2CAP Channel Setup Request event. \n See @ref ble_l2cap_evt_ch_setup_request_t. */ - BLE_L2CAP_EVT_CH_SETUP_REFUSED = BLE_L2CAP_EVT_BASE + 1, /**< L2CAP Channel Setup Refused event. + BLE_L2CAP_EVT_CH_SETUP_REFUSED = BLE_L2CAP_EVT_BASE + 1, /**< L2CAP Channel Setup Refused event. \n See @ref ble_l2cap_evt_ch_setup_refused_t. */ - BLE_L2CAP_EVT_CH_SETUP = BLE_L2CAP_EVT_BASE + 2, /**< L2CAP Channel Setup Completed event. + BLE_L2CAP_EVT_CH_SETUP = BLE_L2CAP_EVT_BASE + 2, /**< L2CAP Channel Setup Completed event. \n See @ref ble_l2cap_evt_ch_setup_t. */ - BLE_L2CAP_EVT_CH_RELEASED = BLE_L2CAP_EVT_BASE + 3, /**< L2CAP Channel Released event. + BLE_L2CAP_EVT_CH_RELEASED = BLE_L2CAP_EVT_BASE + 3, /**< L2CAP Channel Released event. \n No additional event structure applies. */ - BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED = BLE_L2CAP_EVT_BASE + 4, /**< L2CAP Channel SDU data buffer released event. + BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED = BLE_L2CAP_EVT_BASE + 4, /**< L2CAP Channel SDU data buffer released event. \n See @ref ble_l2cap_evt_ch_sdu_buf_released_t. */ - BLE_L2CAP_EVT_CH_CREDIT = BLE_L2CAP_EVT_BASE + 5, /**< L2CAP Channel Credit received. + BLE_L2CAP_EVT_CH_CREDIT = BLE_L2CAP_EVT_BASE + 5, /**< L2CAP Channel Credit received. \n See @ref ble_l2cap_evt_ch_credit_t. */ - BLE_L2CAP_EVT_CH_RX = BLE_L2CAP_EVT_BASE + 6, /**< L2CAP Channel SDU received. + BLE_L2CAP_EVT_CH_RX = BLE_L2CAP_EVT_BASE + 6, /**< L2CAP Channel SDU received. \n See @ref ble_l2cap_evt_ch_rx_t. */ - BLE_L2CAP_EVT_CH_TX = BLE_L2CAP_EVT_BASE + 7, /**< L2CAP Channel SDU transmitted. + BLE_L2CAP_EVT_CH_TX = BLE_L2CAP_EVT_BASE + 7, /**< L2CAP Channel SDU transmitted. \n See @ref ble_l2cap_evt_ch_tx_t. */ }; @@ -136,9 +136,9 @@ enum BLE_L2CAP_EVTS * @{ */ #define BLE_L2CAP_CH_SETUP_REFUSED_SRC_LOCAL (0x01) /**< Local. */ #define BLE_L2CAP_CH_SETUP_REFUSED_SRC_REMOTE (0x02) /**< Remote. */ - /** @} */ +/** @} */ - /** @defgroup BLE_L2CAP_CH_STATUS_CODES L2CAP channel status codes +/** @defgroup BLE_L2CAP_CH_STATUS_CODES L2CAP channel status codes * @{ */ #define BLE_L2CAP_CH_STATUS_CODE_SUCCESS (0x0000) /**< Success. */ #define BLE_L2CAP_CH_STATUS_CODE_LE_PSM_NOT_SUPPORTED (0x0002) /**< LE_PSM not supported. */ @@ -173,17 +173,17 @@ enum BLE_L2CAP_EVTS */ typedef struct { - uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be able to receive on L2CAP channels on connections with this configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ - uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be able to transmit on L2CAP channels on connections with this configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ - uint8_t rx_queue_size; /**< Number of SDU data buffers that can be queued for reception per + uint8_t rx_queue_size; /**< Number of SDU data buffers that can be queued for reception per L2CAP channel. The minimum value is one. */ - uint8_t tx_queue_size; /**< Number of SDU data buffers that can be queued for transmission + uint8_t tx_queue_size; /**< Number of SDU data buffers that can be queued for transmission per L2CAP channel. The minimum value is one. */ - uint8_t ch_count; /**< Number of L2CAP channels the application can create per connection + uint8_t ch_count; /**< Number of L2CAP channels the application can create per connection with this configuration. The default value is zero, the maximum value is @ref BLE_L2CAP_CH_COUNT_MAX. @note if this parameter is set to zero, all other parameters in @@ -193,14 +193,14 @@ typedef struct /**@brief L2CAP channel RX parameters. */ typedef struct { - uint16_t rx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP shall be able to + uint16_t rx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP shall be able to receive on this L2CAP channel. - Must be equal to or greater than @ref BLE_L2CAP_MTU_MIN. */ - uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be able to receive on this L2CAP channel. - Must be equal to or greater than @ref BLE_L2CAP_MPS_MIN. - Must be equal to or less than @ref ble_l2cap_conn_cfg_t::rx_mps. */ - ble_data_t sdu_buf; /**< SDU data buffer for reception. + ble_data_t sdu_buf; /**< SDU data buffer for reception. - If @ref ble_data_t::p_data is non-NULL, initial credits are issued to the peer. - If @ref ble_data_t::p_data is NULL, no initial credits are @@ -210,10 +210,10 @@ typedef struct /**@brief L2CAP channel setup parameters. */ typedef struct { - ble_l2cap_ch_rx_params_t rx_params; /**< L2CAP channel RX parameters. */ - uint16_t le_psm; /**< LE Protocol/Service Multiplexer. Used when requesting + ble_l2cap_ch_rx_params_t rx_params; /**< L2CAP channel RX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. Used when requesting setup of an L2CAP channel, ignored otherwise. */ - uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES. + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES. Used when replying to a setup request of an L2CAP channel, ignored otherwise. */ } ble_l2cap_ch_setup_params_t; @@ -221,41 +221,41 @@ typedef struct /**@brief L2CAP channel TX parameters. */ typedef struct { - uint16_t tx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP is able to + uint16_t tx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP is able to transmit on this L2CAP channel. */ - uint16_t peer_mps; /**< The maximum L2CAP PDU payload size, in bytes, that the peer is + uint16_t peer_mps; /**< The maximum L2CAP PDU payload size, in bytes, that the peer is able to receive on this L2CAP channel. */ - uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP is able + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP is able to transmit on this L2CAP channel. This is effective tx_mps, selected by the SoftDevice as MIN( @ref ble_l2cap_ch_tx_params_t::peer_mps, @ref ble_l2cap_conn_cfg_t::tx_mps ) */ - uint16_t credits; /**< Initial credits given by the peer. */ + uint16_t credits; /**< Initial credits given by the peer. */ } ble_l2cap_ch_tx_params_t; /**@brief L2CAP Channel Setup Request event. */ typedef struct { - ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ - uint16_t le_psm; /**< LE Protocol/Service Multiplexer. */ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. */ } ble_l2cap_evt_ch_setup_request_t; /**@brief L2CAP Channel Setup Refused event. */ typedef struct { - uint8_t source; /**< Source, see @ref BLE_L2CAP_CH_SETUP_REFUSED_SRCS */ - uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES */ + uint8_t source; /**< Source, see @ref BLE_L2CAP_CH_SETUP_REFUSED_SRCS */ + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES */ } ble_l2cap_evt_ch_setup_refused_t; /**@brief L2CAP Channel Setup Completed event. */ typedef struct { - ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ } ble_l2cap_evt_ch_setup_t; /**@brief L2CAP Channel SDU Data Buffer Released event. */ typedef struct { - ble_data_t sdu_buf; /**< Returned reception or transmission SDU data buffer. The SoftDevice + ble_data_t sdu_buf; /**< Returned reception or transmission SDU data buffer. The SoftDevice returns SDU data buffers supplied by the application, which have not yet been returned previously via a @ref BLE_L2CAP_EVT_CH_RX or @ref BLE_L2CAP_EVT_CH_TX event. */ @@ -264,14 +264,14 @@ typedef struct /**@brief L2CAP Channel Credit received event. */ typedef struct { - uint16_t credits; /**< Additional credits given by the peer. */ + uint16_t credits; /**< Additional credits given by the peer. */ } ble_l2cap_evt_ch_credit_t; /**@brief L2CAP Channel received SDU event. */ typedef struct { - uint16_t sdu_len; /**< Total SDU length, in bytes. */ - ble_data_t sdu_buf; /**< SDU data buffer. + uint16_t sdu_len; /**< Total SDU length, in bytes. */ + ble_data_t sdu_buf; /**< SDU data buffer. @note If there is not enough space in the buffer (sdu_buf.len < sdu_len) then the rest of the SDU will be silently discarded by the SoftDevice. */ @@ -280,25 +280,25 @@ typedef struct /**@brief L2CAP Channel transmitted SDU event. */ typedef struct { - ble_data_t sdu_buf; /**< SDU data buffer. */ + ble_data_t sdu_buf; /**< SDU data buffer. */ } ble_l2cap_evt_ch_tx_t; /**@brief L2CAP event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which the event occured. */ - uint16_t local_cid; /**< Local Channel ID of the L2CAP channel, or + uint16_t conn_handle; /**< Connection Handle on which the event occured. */ + uint16_t local_cid; /**< Local Channel ID of the L2CAP channel, or @ref BLE_L2CAP_CID_INVALID if not present. */ - union - { - ble_l2cap_evt_ch_setup_request_t ch_setup_request; /**< L2CAP Channel Setup Request Event Parameters. */ - ble_l2cap_evt_ch_setup_refused_t ch_setup_refused; /**< L2CAP Channel Setup Refused Event Parameters. */ - ble_l2cap_evt_ch_setup_t ch_setup; /**< L2CAP Channel Setup Completed Event Parameters. */ - ble_l2cap_evt_ch_sdu_buf_released_t ch_sdu_buf_released;/**< L2CAP Channel SDU Data Buffer Released Event Parameters. */ - ble_l2cap_evt_ch_credit_t credit; /**< L2CAP Channel Credit Received Event Parameters. */ - ble_l2cap_evt_ch_rx_t rx; /**< L2CAP Channel SDU Received Event Parameters. */ - ble_l2cap_evt_ch_tx_t tx; /**< L2CAP Channel SDU Transmitted Event Parameters. */ - } params; /**< Event Parameters. */ + union + { + ble_l2cap_evt_ch_setup_request_t ch_setup_request; /**< L2CAP Channel Setup Request Event Parameters. */ + ble_l2cap_evt_ch_setup_refused_t ch_setup_refused; /**< L2CAP Channel Setup Refused Event Parameters. */ + ble_l2cap_evt_ch_setup_t ch_setup; /**< L2CAP Channel Setup Completed Event Parameters. */ + ble_l2cap_evt_ch_sdu_buf_released_t ch_sdu_buf_released;/**< L2CAP Channel SDU Data Buffer Released Event Parameters. */ + ble_l2cap_evt_ch_credit_t credit; /**< L2CAP Channel Credit Received Event Parameters. */ + ble_l2cap_evt_ch_rx_t rx; /**< L2CAP Channel SDU Received Event Parameters. */ + ble_l2cap_evt_ch_tx_t tx; /**< L2CAP Channel SDU Transmitted Event Parameters. */ + } params; /**< Event Parameters. */ } ble_l2cap_evt_t; /** @} */ @@ -346,7 +346,7 @@ typedef struct * @retval ::NRF_ERROR_RESOURCES The limit has been reached for available L2CAP channels, * see @ref ble_l2cap_conn_cfg_t::ch_count. */ -SVCALL(SD_BLE_L2CAP_CH_SETUP, uint32_t, sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t *p_local_cid, ble_l2cap_ch_setup_params_t const *p_params)); +SVCALL(SD_BLE_L2CAP_CH_SETUP, uint32_t, sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t * p_local_cid, ble_l2cap_ch_setup_params_t const *p_params)); /**@brief Release an L2CAP channel. * @@ -492,7 +492,7 @@ SVCALL(SD_BLE_L2CAP_CH_TX, uint32_t, sd_ble_l2cap_ch_tx(uint16_t conn_handle, ui * in progress for an L2CAP channel). * @retval ::NRF_ERROR_NOT_FOUND CID not found. */ -SVCALL(SD_BLE_L2CAP_CH_FLOW_CONTROL, uint32_t, sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t *p_credits)); +SVCALL(SD_BLE_L2CAP_CH_FLOW_CONTROL, uint32_t, sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t * p_credits)); /** @} */ diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_types.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_types.h index 88c93180c..350495913 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_types.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/ble_types.h @@ -155,27 +155,27 @@ extern "C" { /** @} */ /** @brief Set .type and .uuid fields of ble_uuid_struct to specified UUID value. */ -#define BLE_UUID_BLE_ASSIGN(instance, value) do {\ - instance.type = BLE_UUID_TYPE_BLE; \ - instance.uuid = value;} while(0) +#define BLE_UUID_BLE_ASSIGN(instance, value) do { \ + instance.type = BLE_UUID_TYPE_BLE; \ + instance.uuid = value;} while (0) /** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */ -#define BLE_UUID_COPY_PTR(dst, src) do {\ - (dst)->type = (src)->type; \ - (dst)->uuid = (src)->uuid;} while(0) +#define BLE_UUID_COPY_PTR(dst, src) do { \ + (dst)->type = (src)->type; \ + (dst)->uuid = (src)->uuid;} while (0) /** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */ -#define BLE_UUID_COPY_INST(dst, src) do {\ - (dst).type = (src).type; \ - (dst).uuid = (src).uuid;} while(0) +#define BLE_UUID_COPY_INST(dst, src) do { \ + (dst).type = (src).type; \ + (dst).uuid = (src).uuid;} while (0) /** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ #define BLE_UUID_EQ(p_uuid1, p_uuid2) \ - (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) + (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) /** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ #define BLE_UUID_NEQ(p_uuid1, p_uuid2) \ - (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) + (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) /** @} */ @@ -185,21 +185,21 @@ extern "C" { /** @brief 128 bit UUID values. */ typedef struct { - uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */ + uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */ } ble_uuid128_t; /** @brief Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */ typedef struct { - uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ - uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ + uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ + uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ } ble_uuid_t; /**@brief Data structure. */ typedef struct { - uint8_t *p_data; /**< Pointer to the data buffer provided to/from the application. */ - uint16_t len; /**< Length of the data buffer, in bytes. */ + uint8_t *p_data; /**< Pointer to the data buffer provided to/from the application. */ + uint16_t len; /**< Length of the data buffer, in bytes. */ } ble_data_t; /** @} */ diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf52/nrf_mbr.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf52/nrf_mbr.h index e0c80e278..1c7f3e1f3 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf52/nrf_mbr.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf52/nrf_mbr.h @@ -75,19 +75,19 @@ This is the offset where the first byte of the SoftDevice hex file is written.*/ /**@brief nRF Master Boot Record API SVC numbers. */ enum NRF_MBR_SVCS { - SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */ + SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */ }; /**@brief Possible values for ::sd_mbr_command_t.command */ enum NRF_MBR_COMMANDS { - SD_MBR_COMMAND_COPY_BL, /**< Copy a new BootLoader. @see ::sd_mbr_command_copy_bl_t*/ - SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/ - SD_MBR_COMMAND_INIT_SD, /**< Initialize forwarding interrupts to SD, and run reset function in SD. Does not require any parameters in ::sd_mbr_command_t params.*/ - SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/ - SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Change the address the MBR starts after a reset. @see ::sd_mbr_command_vector_table_base_set_t*/ - SD_MBR_COMMAND_RESERVED, - SD_MBR_COMMAND_IRQ_FORWARD_ADDRESS_SET, /**< Start forwarding all interrupts to this address. @see ::sd_mbr_command_irq_forward_address_set_t*/ + SD_MBR_COMMAND_COPY_BL, /**< Copy a new BootLoader. @see ::sd_mbr_command_copy_bl_t*/ + SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/ + SD_MBR_COMMAND_INIT_SD, /**< Initialize forwarding interrupts to SD, and run reset function in SD. Does not require any parameters in ::sd_mbr_command_t params.*/ + SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/ + SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Change the address the MBR starts after a reset. @see ::sd_mbr_command_vector_table_base_set_t*/ + SD_MBR_COMMAND_RESERVED, + SD_MBR_COMMAND_IRQ_FORWARD_ADDRESS_SET, /**< Start forwarding all interrupts to this address. @see ::sd_mbr_command_irq_forward_address_set_t*/ }; /** @} */ @@ -108,9 +108,9 @@ enum NRF_MBR_COMMANDS */ typedef struct { - uint32_t *src; /**< Pointer to the source of data to be copied.*/ - uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/ - uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/ + uint32_t *src; /**< Pointer to the source of data to be copied.*/ + uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/ + uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/ } sd_mbr_command_copy_sd_t; @@ -121,9 +121,9 @@ typedef struct */ typedef struct { - uint32_t *ptr1; /**< Pointer to block of memory. */ - uint32_t *ptr2; /**< Pointer to block of memory. */ - uint32_t len; /**< Number of 32 bit words to compare.*/ + uint32_t *ptr1; /**< Pointer to block of memory. */ + uint32_t *ptr2; /**< Pointer to block of memory. */ + uint32_t len; /**< Number of 32 bit words to compare.*/ } sd_mbr_command_compare_t; @@ -147,8 +147,8 @@ typedef struct */ typedef struct { - uint32_t *bl_src; /**< Pointer to the source of the Bootloader to be be copied.*/ - uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader. */ + uint32_t *bl_src; /**< Pointer to the source of the Bootloader to be be copied.*/ + uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader. */ } sd_mbr_command_copy_bl_t; /**@brief Change the address the MBR starts after a reset @@ -168,7 +168,7 @@ typedef struct */ typedef struct { - uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ + uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ } sd_mbr_command_vector_table_base_set_t; /**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR @@ -180,7 +180,7 @@ typedef struct */ typedef struct { - uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ + uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ } sd_mbr_command_irq_forward_address_set_t; /**@brief Input structure containing data used when calling ::sd_mbr_command @@ -191,15 +191,15 @@ typedef struct */ typedef struct { - uint32_t command; /**< Type of command to be issued. See @ref NRF_MBR_COMMANDS. */ - union - { - sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy SoftDevice.*/ - sd_mbr_command_compare_t compare; /**< Parameters for verify.*/ - sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy BootLoader. Requires parameter page. */ - sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/ - sd_mbr_command_irq_forward_address_set_t irq_forward_address_set; /**< Parameters for irq forward address set*/ - } params; /**< Command parameters. */ + uint32_t command; /**< Type of command to be issued. See @ref NRF_MBR_COMMANDS. */ + union + { + sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy SoftDevice.*/ + sd_mbr_command_compare_t compare; /**< Parameters for verify.*/ + sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy BootLoader. Requires parameter page. */ + sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/ + sd_mbr_command_irq_forward_address_set_t irq_forward_address_set; /**< Parameters for irq forward address set*/ + } params; /**< Command parameters. */ } sd_mbr_command_t; /** @} */ @@ -228,7 +228,7 @@ typedef struct * @retval ::NRF_ERROR_NO_MEM if UICR.NRFFW[1] is not set (i.e. is 0xFFFFFFFF). * @retval ::NRF_ERROR_INVALID_PARAM if an invalid command is given. */ -SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param)); +SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t * param)); /** @} */ diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_error.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_error.h index 6badee98e..7e9bf748d 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_error.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_error.h @@ -36,7 +36,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - /** +/** @defgroup nrf_error SoftDevice Global Error Codes @{ diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_error_sdm.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_error_sdm.h index 530959b9d..8e43a6102 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_error_sdm.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_error_sdm.h @@ -36,7 +36,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - /** +/** @addtogroup nrf_sdm_api @{ @defgroup nrf_sdm_error SoftDevice Manager Error Codes diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_nvic.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_nvic.h index 1f79cc3c8..c2fa90f66 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_nvic.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_nvic.h @@ -77,17 +77,17 @@ extern "C" { /**@brief Interrupt priority levels used by the SoftDevice. */ #define __NRF_NVIC_SD_IRQ_PRIOS ((uint8_t)( \ - (1U << 0) /**< Priority level high .*/ \ + (1U << 0) /**< Priority level high .*/ \ | (1U << 1) /**< Priority level medium. */ \ | (1U << 4) /**< Priority level low. */ \ - )) + )) /**@brief Interrupt priority levels available to the application. */ -#define __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t)~__NRF_NVIC_SD_IRQ_PRIOS) +#define __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t) ~__NRF_NVIC_SD_IRQ_PRIOS) /**@brief Interrupts used by the SoftDevice, with IRQn in the range 0-31. */ #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \ - (1U << POWER_CLOCK_IRQn) \ + (1U << POWER_CLOCK_IRQn) \ | (1U << RADIO_IRQn) \ | (1U << RTC0_IRQn) \ | (1U << TIMER0_IRQn) \ @@ -97,7 +97,7 @@ extern "C" { | (1U << TEMP_IRQn) \ | (1U << __NRF_NVIC_NVMC_IRQn) \ | (1U << (uint32_t)SWI5_IRQn) \ - )) + )) /**@brief Interrupts used by the SoftDevice, with IRQn in the range 32-63. */ #define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0) @@ -118,8 +118,8 @@ extern "C" { /**@brief Type representing the state struct for the SoftDevice NVIC module. */ typedef struct { - uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */ - uint32_t volatile __cr_flag; /**< Non-zero if already in a critical region */ + uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */ + uint32_t volatile __cr_flag; /**< Non-zero if already in a critical region */ } nrf_nvic_state_t; /**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an @@ -196,7 +196,7 @@ __STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn); * @retval ::NRF_SUCCESS The interrupt is available for the application. * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. */ -__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq); +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t *p_pending_irq); /**@brief Set Pending Interrupt. * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. @@ -248,7 +248,7 @@ __STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority); * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application. */ -__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority); +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t *p_priority); /**@brief System Reset. * @note Corresponds to NVIC_SystemReset in CMSIS. @@ -268,7 +268,7 @@ __STATIC_INLINE uint32_t sd_nvic_SystemReset(void); * * @retval ::NRF_SUCCESS */ -__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region); +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t *p_is_nested_critical_region); /**@brief Exit critical region. * @@ -285,199 +285,150 @@ __STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical #ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE int __sd_nvic_irq_disable(void) -{ - int pm = __get_PRIMASK(); - __disable_irq(); - return pm; +__STATIC_INLINE int __sd_nvic_irq_disable(void) { + int pm = __get_PRIMASK(); + __disable_irq(); + return pm; } -__STATIC_INLINE void __sd_nvic_irq_enable(void) -{ - __enable_irq(); +__STATIC_INLINE void __sd_nvic_irq_enable(void) { + __enable_irq(); } -__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn) -{ - if (IRQn < 32) - { - return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0; - } - else if (IRQn < 64) - { - return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0; - } - else - { - return 1; - } +__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn) { + if (IRQn < 32) { + return ((1UL << IRQn) & __NRF_NVIC_APP_IRQS_0) != 0; + } else if (IRQn < 64) { + return ((1UL << (IRQn - 32)) & __NRF_NVIC_APP_IRQS_1) != 0; + } else { + return 1; + } } -__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority) -{ - if( (priority >= (1 << __NVIC_PRIO_BITS)) - || (((1 << priority) & __NRF_NVIC_APP_IRQ_PRIOS) == 0) - ) - { - return 0; - } - return 1; +__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority) { + if ((priority >= (1 << __NVIC_PRIO_BITS)) + || (((1 << priority) & __NRF_NVIC_APP_IRQ_PRIOS) == 0) + ) { + return 0; + } + return 1; } -__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn))) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; - } - - if (nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); - } - else - { - NVIC_EnableIRQ(IRQn); - } - return NRF_SUCCESS; -} +__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) { + if (!__sd_nvic_app_accessible_irq(IRQn)) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn))) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } -__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - - if (nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F)); - } - else - { - NVIC_DisableIRQ(IRQn); - } - - return NRF_SUCCESS; + if (nrf_nvic_state.__cr_flag) { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); + } else { + NVIC_EnableIRQ(IRQn); + } + return NRF_SUCCESS; } -__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - *p_pending_irq = NVIC_GetPendingIRQ(IRQn); +__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) { + if (!__sd_nvic_app_accessible_irq(IRQn)) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (nrf_nvic_state.__cr_flag) { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F)); + } else { + NVIC_DisableIRQ(IRQn); + } + return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } } -__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - NVIC_SetPendingIRQ(IRQn); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t *p_pending_irq) { + if (__sd_nvic_app_accessible_irq(IRQn)) { + *p_pending_irq = NVIC_GetPendingIRQ(IRQn); + return NRF_SUCCESS; + } else { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } } -__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - NVIC_ClearPendingIRQ(IRQn); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } +__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) { + if (__sd_nvic_app_accessible_irq(IRQn)) { + NVIC_SetPendingIRQ(IRQn); + return NRF_SUCCESS; + } else { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } } -__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - - if (!__sd_nvic_is_app_accessible_priority(priority)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; - } - - NVIC_SetPriority(IRQn, (uint32_t)priority); - return NRF_SUCCESS; +__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) { + if (__sd_nvic_app_accessible_irq(IRQn)) { + NVIC_ClearPendingIRQ(IRQn); + return NRF_SUCCESS; + } else { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } } -__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - *p_priority = (NVIC_GetPriority(IRQn) & 0xFF); +__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) { + if (!__sd_nvic_app_accessible_irq(IRQn)) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (!__sd_nvic_is_app_accessible_priority(priority)) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } + + NVIC_SetPriority(IRQn, (uint32_t)priority); return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } } -__STATIC_INLINE uint32_t sd_nvic_SystemReset(void) -{ - NVIC_SystemReset(); - return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN; +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t *p_priority) { + if (__sd_nvic_app_accessible_irq(IRQn)) { + *p_priority = (NVIC_GetPriority(IRQn) & 0xFF); + return NRF_SUCCESS; + } else { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } } -__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region) -{ - int was_masked = __sd_nvic_irq_disable(); - if (!nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__cr_flag = 1; - nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); - NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; - nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); - NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; - *p_is_nested_critical_region = 0; - } - else - { - *p_is_nested_critical_region = 1; - } - if (!was_masked) - { - __sd_nvic_irq_enable(); - } - return NRF_SUCCESS; +__STATIC_INLINE uint32_t sd_nvic_SystemReset(void) { + NVIC_SystemReset(); + return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN; } -__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) -{ - if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0)) - { +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t *p_is_nested_critical_region) { int was_masked = __sd_nvic_irq_disable(); - NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; - NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; - nrf_nvic_state.__cr_flag = 0; - if (!was_masked) - { - __sd_nvic_irq_enable(); + if (!nrf_nvic_state.__cr_flag) { + nrf_nvic_state.__cr_flag = 1; + nrf_nvic_state.__irq_masks[0] = (NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0); + NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; + nrf_nvic_state.__irq_masks[1] = (NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1); + NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; + *p_is_nested_critical_region = 0; + } else { + *p_is_nested_critical_region = 1; + } + if (!was_masked) { + __sd_nvic_irq_enable(); } - } + return NRF_SUCCESS; +} - return NRF_SUCCESS; +__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) { + if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0)) { + int was_masked = __sd_nvic_irq_disable(); + NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; + NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; + nrf_nvic_state.__cr_flag = 0; + if (!was_masked) { + __sd_nvic_irq_enable(); + } + } + + return NRF_SUCCESS; } #endif /* SUPPRESS_INLINE_IMPLEMENTATION */ diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_sdm.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_sdm.h index 282e762e0..8a9979af2 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_sdm.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_sdm.h @@ -130,12 +130,12 @@ the start of the SoftDevice (without MBR)*/ /** @brief Defines a macro for retrieving the actual SoftDevice Information Structure size value * from a given base address. Use @ref MBR_SIZE as the argument when the SoftDevice is * installed just above the MBR (the usual case). */ -#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *) ((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET))) +#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *)((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET))) /** @brief Defines a macro for retrieving the actual SoftDevice size value from a given base * address. Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above * the MBR (the usual case). */ -#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET))) +#define SD_SIZE_GET(baseaddr) (*((uint32_t *)((baseaddr) + SD_SIZE_OFFSET))) /** @brief Defines the amount of flash that is used by the SoftDevice. * Add @ref MBR_SIZE to find the first available flash address when the SoftDevice is installed @@ -146,25 +146,25 @@ the start of the SoftDevice (without MBR)*/ /** @brief Defines a macro for retrieving the actual FWID value from a given base address. Use * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the usual * case). */ -#define SD_FWID_GET(baseaddr) (*((uint16_t *) ((baseaddr) + SD_FWID_OFFSET))) +#define SD_FWID_GET(baseaddr) (*((uint16_t *)((baseaddr) + SD_FWID_OFFSET))) /** @brief Defines a macro for retrieving the actual SoftDevice ID from a given base address. Use * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the * usual case). */ #define SD_ID_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_ID_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ - ? (*((uint32_t *) ((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID) + ? (*((uint32_t *)((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID) /** @brief Defines a macro for retrieving the actual SoftDevice version from a given base address. * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR * (the usual case). */ #define SD_VERSION_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_VERSION_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ - ? (*((uint32_t *) ((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID) + ? (*((uint32_t *)((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID) /** @brief Defines a macro for retrieving the address of SoftDevice unique str based on a given base address. * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR * (the usual case). */ #define SD_UNIQUE_STR_ADDR_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_UNIQUE_STR_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ - ? (((uint8_t *) ((baseaddr) + SD_UNIQUE_STR_OFFSET))) : SDM_INFO_FIELD_INVALID) + ? (((uint8_t *)((baseaddr) + SD_UNIQUE_STR_OFFSET))) : SDM_INFO_FIELD_INVALID) /**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges * @{ */ @@ -174,7 +174,7 @@ the start of the SoftDevice (without MBR)*/ /**@defgroup NRF_FAULT_IDS Fault ID types * @{ */ -#define NRF_FAULT_ID_SD_ASSERT (NRF_FAULT_ID_SD_RANGE_START + 1) /**< SoftDevice assertion. The info parameter is reserved for future used. */ +#define NRF_FAULT_ID_SD_ASSERT (NRF_FAULT_ID_SD_RANGE_START + 1) /**< SoftDevice assertion. The info parameter is reserved for future used. */ #define NRF_FAULT_ID_APP_MEMACC (NRF_FAULT_ID_APP_RANGE_START + 1) /**< Application invalid memory access. The info parameter will contain 0x00000000, in case of SoftDevice RAM access violation. In case of SoftDevice peripheral register violation the info parameter will contain the sub-region number of @@ -190,11 +190,11 @@ the start of the SoftDevice (without MBR)*/ /**@brief nRF SoftDevice Manager API SVC numbers. */ enum NRF_SD_SVCS { - SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ - SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ - SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ - SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ - SVC_SDM_LAST /**< Placeholder for last SDM SVC */ + SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ + SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ + SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ + SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ + SVC_SDM_LAST /**< Placeholder for last SDM SVC */ }; /** @} */ @@ -237,15 +237,15 @@ enum NRF_SD_SVCS /**@brief Type representing LFCLK oscillator source. */ typedef struct { - uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ - uint8_t rc_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second + uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ + uint8_t rc_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second units (nRF52: 1-32). @note To avoid excessive clock drift, 0.5 degrees Celsius is the maximum temperature change allowed in one calibration timer interval. The interval should be selected to ensure this. @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC. */ - uint8_t rc_temp_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: How often (in number of calibration + uint8_t rc_temp_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: How often (in number of calibration intervals) the RC oscillator shall be calibrated if the temperature hasn't changed. 0: Always calibrate even if the temperature hasn't changed. @@ -263,7 +263,7 @@ typedef struct least once every 8 seconds and for temperature changes of 0.5 degrees Celsius every 4 seconds. See the Product Specification for the nRF52 device being used for more information.*/ - uint8_t accuracy; /**< External clock accuracy used in the LL to compute timing + uint8_t accuracy; /**< External clock accuracy used in the LL to compute timing windows, see @ref NRF_CLOCK_LF_ACCURACY.*/ } nrf_clock_lf_cfg_t; @@ -319,7 +319,7 @@ typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info); * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected. * @retval ::NRF_ERROR_INVALID_PARAM Invalid clock source configuration supplied in p_clock_lf_cfg. */ -SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler)); +SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const *p_clock_lf_cfg, nrf_fault_handler_t fault_handler)); /**@brief Disables the SoftDevice and by extension the protocol stack. diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_soc.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_soc.h index beb4d3a54..e3790a9f4 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_soc.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_soc.h @@ -100,7 +100,7 @@ extern "C" { /**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is enabled. */ #define NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK ((uint32_t)( \ - (1U << 17) \ + (1U << 17) \ | (1U << 18) \ | (1U << 19) \ | (1U << 20) \ @@ -115,7 +115,7 @@ extern "C" { | (1U << 29) \ | (1U << 30) \ | (1U << 31) \ - )) + )) /**@brief Mask of PPI channels available to the application when the SoftDevice is disabled. */ #define NRF_SOC_APP_PPI_CHANNELS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK) @@ -128,9 +128,9 @@ extern "C" { /**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is enabled. */ #define NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK ((uint32_t)( \ - (1U << 4) \ + (1U << 4) \ | (1U << 5) \ - )) + )) /**@brief Mask of PPI groups available to the application when the SoftDevice is disabled. */ #define NRF_SOC_APP_PPI_GROUPS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK) @@ -146,148 +146,148 @@ extern "C" { /**@brief The SVC numbers used by the SVC functions in the SoC library. */ enum NRF_SOC_SVCS { - SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE, - SD_PPI_CHANNEL_ENABLE_SET = SOC_SVC_BASE + 1, - SD_PPI_CHANNEL_ENABLE_CLR = SOC_SVC_BASE + 2, - SD_PPI_CHANNEL_ASSIGN = SOC_SVC_BASE + 3, - SD_PPI_GROUP_TASK_ENABLE = SOC_SVC_BASE + 4, - SD_PPI_GROUP_TASK_DISABLE = SOC_SVC_BASE + 5, - SD_PPI_GROUP_ASSIGN = SOC_SVC_BASE + 6, - SD_PPI_GROUP_GET = SOC_SVC_BASE + 7, - SD_FLASH_PAGE_ERASE = SOC_SVC_BASE + 8, - SD_FLASH_WRITE = SOC_SVC_BASE + 9, - SD_PROTECTED_REGISTER_WRITE = SOC_SVC_BASE + 11, - SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, - SD_MUTEX_ACQUIRE = SOC_SVC_BASE_NOT_AVAILABLE + 1, - SD_MUTEX_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 2, - SD_RAND_APPLICATION_POOL_CAPACITY_GET = SOC_SVC_BASE_NOT_AVAILABLE + 3, - SD_RAND_APPLICATION_BYTES_AVAILABLE_GET = SOC_SVC_BASE_NOT_AVAILABLE + 4, - SD_RAND_APPLICATION_VECTOR_GET = SOC_SVC_BASE_NOT_AVAILABLE + 5, - SD_POWER_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 6, - SD_POWER_SYSTEM_OFF = SOC_SVC_BASE_NOT_AVAILABLE + 7, - SD_POWER_RESET_REASON_GET = SOC_SVC_BASE_NOT_AVAILABLE + 8, - SD_POWER_RESET_REASON_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 9, - SD_POWER_POF_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 10, - SD_POWER_POF_THRESHOLD_SET = SOC_SVC_BASE_NOT_AVAILABLE + 11, - SD_POWER_POF_THRESHOLDVDDH_SET = SOC_SVC_BASE_NOT_AVAILABLE + 12, - SD_POWER_RAM_POWER_SET = SOC_SVC_BASE_NOT_AVAILABLE + 13, - SD_POWER_RAM_POWER_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 14, - SD_POWER_RAM_POWER_GET = SOC_SVC_BASE_NOT_AVAILABLE + 15, - SD_POWER_GPREGRET_SET = SOC_SVC_BASE_NOT_AVAILABLE + 16, - SD_POWER_GPREGRET_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 17, - SD_POWER_GPREGRET_GET = SOC_SVC_BASE_NOT_AVAILABLE + 18, - SD_POWER_DCDC_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 19, - SD_POWER_DCDC0_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 20, - SD_APP_EVT_WAIT = SOC_SVC_BASE_NOT_AVAILABLE + 21, - SD_CLOCK_HFCLK_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 22, - SD_CLOCK_HFCLK_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 23, - SD_CLOCK_HFCLK_IS_RUNNING = SOC_SVC_BASE_NOT_AVAILABLE + 24, - SD_RADIO_NOTIFICATION_CFG_SET = SOC_SVC_BASE_NOT_AVAILABLE + 25, - SD_ECB_BLOCK_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 26, - SD_ECB_BLOCKS_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 27, - SD_RADIO_SESSION_OPEN = SOC_SVC_BASE_NOT_AVAILABLE + 28, - SD_RADIO_SESSION_CLOSE = SOC_SVC_BASE_NOT_AVAILABLE + 29, - SD_RADIO_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 30, - SD_EVT_GET = SOC_SVC_BASE_NOT_AVAILABLE + 31, - SD_TEMP_GET = SOC_SVC_BASE_NOT_AVAILABLE + 32, - SD_POWER_USBPWRRDY_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 33, - SD_POWER_USBDETECTED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 34, - SD_POWER_USBREMOVED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 35, - SD_POWER_USBREGSTATUS_GET = SOC_SVC_BASE_NOT_AVAILABLE + 36, - SVC_SOC_LAST = SOC_SVC_BASE_NOT_AVAILABLE + 37 + SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE, + SD_PPI_CHANNEL_ENABLE_SET = SOC_SVC_BASE + 1, + SD_PPI_CHANNEL_ENABLE_CLR = SOC_SVC_BASE + 2, + SD_PPI_CHANNEL_ASSIGN = SOC_SVC_BASE + 3, + SD_PPI_GROUP_TASK_ENABLE = SOC_SVC_BASE + 4, + SD_PPI_GROUP_TASK_DISABLE = SOC_SVC_BASE + 5, + SD_PPI_GROUP_ASSIGN = SOC_SVC_BASE + 6, + SD_PPI_GROUP_GET = SOC_SVC_BASE + 7, + SD_FLASH_PAGE_ERASE = SOC_SVC_BASE + 8, + SD_FLASH_WRITE = SOC_SVC_BASE + 9, + SD_PROTECTED_REGISTER_WRITE = SOC_SVC_BASE + 11, + SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, + SD_MUTEX_ACQUIRE = SOC_SVC_BASE_NOT_AVAILABLE + 1, + SD_MUTEX_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 2, + SD_RAND_APPLICATION_POOL_CAPACITY_GET = SOC_SVC_BASE_NOT_AVAILABLE + 3, + SD_RAND_APPLICATION_BYTES_AVAILABLE_GET = SOC_SVC_BASE_NOT_AVAILABLE + 4, + SD_RAND_APPLICATION_VECTOR_GET = SOC_SVC_BASE_NOT_AVAILABLE + 5, + SD_POWER_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 6, + SD_POWER_SYSTEM_OFF = SOC_SVC_BASE_NOT_AVAILABLE + 7, + SD_POWER_RESET_REASON_GET = SOC_SVC_BASE_NOT_AVAILABLE + 8, + SD_POWER_RESET_REASON_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 9, + SD_POWER_POF_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 10, + SD_POWER_POF_THRESHOLD_SET = SOC_SVC_BASE_NOT_AVAILABLE + 11, + SD_POWER_POF_THRESHOLDVDDH_SET = SOC_SVC_BASE_NOT_AVAILABLE + 12, + SD_POWER_RAM_POWER_SET = SOC_SVC_BASE_NOT_AVAILABLE + 13, + SD_POWER_RAM_POWER_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 14, + SD_POWER_RAM_POWER_GET = SOC_SVC_BASE_NOT_AVAILABLE + 15, + SD_POWER_GPREGRET_SET = SOC_SVC_BASE_NOT_AVAILABLE + 16, + SD_POWER_GPREGRET_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 17, + SD_POWER_GPREGRET_GET = SOC_SVC_BASE_NOT_AVAILABLE + 18, + SD_POWER_DCDC_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 19, + SD_POWER_DCDC0_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 20, + SD_APP_EVT_WAIT = SOC_SVC_BASE_NOT_AVAILABLE + 21, + SD_CLOCK_HFCLK_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 22, + SD_CLOCK_HFCLK_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 23, + SD_CLOCK_HFCLK_IS_RUNNING = SOC_SVC_BASE_NOT_AVAILABLE + 24, + SD_RADIO_NOTIFICATION_CFG_SET = SOC_SVC_BASE_NOT_AVAILABLE + 25, + SD_ECB_BLOCK_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 26, + SD_ECB_BLOCKS_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 27, + SD_RADIO_SESSION_OPEN = SOC_SVC_BASE_NOT_AVAILABLE + 28, + SD_RADIO_SESSION_CLOSE = SOC_SVC_BASE_NOT_AVAILABLE + 29, + SD_RADIO_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 30, + SD_EVT_GET = SOC_SVC_BASE_NOT_AVAILABLE + 31, + SD_TEMP_GET = SOC_SVC_BASE_NOT_AVAILABLE + 32, + SD_POWER_USBPWRRDY_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 33, + SD_POWER_USBDETECTED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 34, + SD_POWER_USBREMOVED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 35, + SD_POWER_USBREGSTATUS_GET = SOC_SVC_BASE_NOT_AVAILABLE + 36, + SVC_SOC_LAST = SOC_SVC_BASE_NOT_AVAILABLE + 37 }; /**@brief Possible values of a ::nrf_mutex_t. */ enum NRF_MUTEX_VALUES { - NRF_MUTEX_FREE, - NRF_MUTEX_TAKEN + NRF_MUTEX_FREE, + NRF_MUTEX_TAKEN }; /**@brief Power modes. */ enum NRF_POWER_MODES { - NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ - NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ + NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ + NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ }; /**@brief Power failure thresholds */ enum NRF_POWER_THRESHOLDS { - NRF_POWER_THRESHOLD_V17 = 4UL, /**< 1.7 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V18, /**< 1.8 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V19, /**< 1.9 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V20, /**< 2.0 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V22, /**< 2.2 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V24, /**< 2.4 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V26, /**< 2.6 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V27, /**< 2.7 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V28 /**< 2.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V17 = 4UL, /**< 1.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V18, /**< 1.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V19, /**< 1.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V20, /**< 2.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V22, /**< 2.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V24, /**< 2.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V26, /**< 2.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V28 /**< 2.8 Volts power failure threshold. */ }; /**@brief Power failure thresholds for high voltage */ enum NRF_POWER_THRESHOLDVDDHS { - NRF_POWER_THRESHOLDVDDH_V27, /**< 2.7 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V28, /**< 2.8 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V29, /**< 2.9 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V30, /**< 3.0 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V31, /**< 3.1 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V32, /**< 3.2 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V33, /**< 3.3 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V34, /**< 3.4 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V35, /**< 3.5 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V36, /**< 3.6 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V37, /**< 3.7 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V38, /**< 3.8 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V39, /**< 3.9 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V40, /**< 4.0 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V41, /**< 4.1 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V42 /**< 4.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V28, /**< 2.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V29, /**< 2.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V30, /**< 3.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V31, /**< 3.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V32, /**< 3.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V33, /**< 3.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V34, /**< 3.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V35, /**< 3.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V36, /**< 3.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V37, /**< 3.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V38, /**< 3.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V39, /**< 3.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V40, /**< 4.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V41, /**< 4.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V42 /**< 4.2 Volts power failure threshold. */ }; /**@brief DC/DC converter modes. */ enum NRF_POWER_DCDC_MODES { - NRF_POWER_DCDC_DISABLE, /**< The DCDC is disabled. */ - NRF_POWER_DCDC_ENABLE /**< The DCDC is enabled. */ + NRF_POWER_DCDC_DISABLE, /**< The DCDC is disabled. */ + NRF_POWER_DCDC_ENABLE /**< The DCDC is enabled. */ }; /**@brief Radio notification distances. */ enum NRF_RADIO_NOTIFICATION_DISTANCES { - NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ - NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ + NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ }; /**@brief Radio notification types. */ enum NRF_RADIO_NOTIFICATION_TYPES { - NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ + NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ }; /**@brief The Radio signal callback types. */ enum NRF_RADIO_CALLBACK_SIGNAL_TYPE { - NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ }; /**@brief The actions requested by the signal callback. @@ -297,28 +297,28 @@ enum NRF_RADIO_CALLBACK_SIGNAL_TYPE */ enum NRF_RADIO_SIGNAL_CALLBACK_ACTION { - NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current + NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current timeslot. Maximum execution time for this action: @ref NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US. This action must be started at least @ref NRF_RADIO_MIN_EXTENSION_MARGIN_US before the end of the timeslot. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ }; /**@brief Radio timeslot high frequency clock source configuration. */ enum NRF_RADIO_HFCLK_CFG { - NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the + NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the external crystal for the whole duration of the timeslot. This should be the preferred option for events that use the radio or require high timing accuracy. @note The SoftDevice will automatically turn on and off the external crystal, at the beginning and end of the timeslot, respectively. The crystal may also intentionally be left running after the timeslot, in cases where it is needed by the SoftDevice shortly after the end of the timeslot. */ - NRF_RADIO_HFCLK_CFG_NO_GUARANTEE /**< This configuration allows for earlier and tighter scheduling of timeslots. + NRF_RADIO_HFCLK_CFG_NO_GUARANTEE /**< This configuration allows for earlier and tighter scheduling of timeslots. The RC oscillator may be the clock source in part or for the whole duration of the timeslot. The RC oscillator's accuracy must therefore be taken into consideration. @note If the application will use the radio peripheral in timeslots with this configuration, @@ -328,33 +328,33 @@ enum NRF_RADIO_HFCLK_CFG /**@brief Radio timeslot priorities. */ enum NRF_RADIO_PRIORITY { - NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ - NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activities of the SoftDevice stack(s)). */ + NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ + NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activities of the SoftDevice stack(s)). */ }; /**@brief Radio timeslot request type. */ enum NRF_RADIO_REQUEST_TYPE { - NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */ - NRF_RADIO_REQ_TYPE_NORMAL /**< Normal radio timeslot request. */ + NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */ + NRF_RADIO_REQ_TYPE_NORMAL /**< Normal radio timeslot request. */ }; /**@brief SoC Events. */ enum NRF_SOC_EVTS { - NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ - NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ - NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ - NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ - NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ - NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ - NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */ - NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio timeslot session is idle. */ - NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio timeslot session is closed. */ - NRF_EVT_POWER_USB_POWER_READY, /**< Event indicating that a USB 3.3 V supply is ready. */ - NRF_EVT_POWER_USB_DETECTED, /**< Event indicating that voltage supply is detected on VBUS. */ - NRF_EVT_POWER_USB_REMOVED, /**< Event indicating that voltage supply is removed from VBUS. */ - NRF_EVT_NUMBER_OF_EVTS + NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ + NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ + NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ + NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ + NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ + NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ + NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */ + NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio timeslot session is idle. */ + NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio timeslot session is closed. */ + NRF_EVT_POWER_USB_POWER_READY, /**< Event indicating that a USB 3.3 V supply is ready. */ + NRF_EVT_POWER_USB_DETECTED, /**< Event indicating that voltage supply is detected on VBUS. */ + NRF_EVT_POWER_USB_REMOVED, /**< Event indicating that voltage supply is removed from VBUS. */ + NRF_EVT_NUMBER_OF_EVTS }; /**@} */ @@ -371,47 +371,47 @@ typedef volatile uint8_t nrf_mutex_t; /**@brief Parameters for a request for a timeslot as early as possible. */ typedef struct { - uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ - uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ - uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ - uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ + uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ } nrf_radio_request_earliest_t; /**@brief Parameters for a normal radio timeslot request. */ typedef struct { - uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ - uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ - uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ - uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ + uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ } nrf_radio_request_normal_t; /**@brief Radio timeslot request parameters. */ typedef struct { - uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ - union - { - nrf_radio_request_earliest_t earliest; /**< Parameters for requesting a radio timeslot as early as possible. */ - nrf_radio_request_normal_t normal; /**< Parameters for requesting a normal radio timeslot. */ - } params; /**< Parameter union. */ + uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ + union + { + nrf_radio_request_earliest_t earliest; /**< Parameters for requesting a radio timeslot as early as possible. */ + nrf_radio_request_normal_t normal; /**< Parameters for requesting a normal radio timeslot. */ + } params; /**< Parameter union. */ } nrf_radio_request_t; /**@brief Return parameters of the radio timeslot signal callback. */ typedef struct { - uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ - union - { - struct - { - nrf_radio_request_t * p_next; /**< The request parameters for the next radio timeslot. */ - } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ - struct + uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ + union { - uint32_t length_us; /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ - } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ - } params; /**< Parameter union. */ + struct + { + nrf_radio_request_t *p_next; /**< The request parameters for the next radio timeslot. */ + } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ + struct + { + uint32_t length_us; /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ + } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ + } params; /**< Parameter union. */ } nrf_radio_signal_callback_return_param_t; /**@brief The radio timeslot signal callback type. @@ -426,7 +426,7 @@ typedef struct * * @return Pointer to structure containing action requested by the application. */ -typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type); +typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t)(uint8_t signal_type); /**@brief AES ECB parameter typedefs */ typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH]; /**< Encryption key type. */ @@ -436,18 +436,18 @@ typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Ciphertex /**@brief AES ECB data structure */ typedef struct { - soc_ecb_key_t key; /**< Encryption key. */ - soc_ecb_cleartext_t cleartext; /**< Cleartext data. */ - soc_ecb_ciphertext_t ciphertext; /**< Ciphertext data. */ + soc_ecb_key_t key; /**< Encryption key. */ + soc_ecb_cleartext_t cleartext; /**< Cleartext data. */ + soc_ecb_ciphertext_t ciphertext; /**< Ciphertext data. */ } nrf_ecb_hal_data_t; /**@brief AES ECB block. Used to provide multiple blocks in a single call to @ref sd_ecb_blocks_encrypt.*/ typedef struct { - soc_ecb_key_t const * p_key; /**< Pointer to the Encryption key. */ - soc_ecb_cleartext_t const * p_cleartext; /**< Pointer to the Cleartext data. */ - soc_ecb_ciphertext_t * p_ciphertext; /**< Pointer to the Ciphertext data. */ + soc_ecb_key_t const *p_key; /**< Pointer to the Encryption key. */ + soc_ecb_cleartext_t const *p_cleartext; /**< Pointer to the Cleartext data. */ + soc_ecb_ciphertext_t *p_ciphertext; /**< Pointer to the Ciphertext data. */ } nrf_ecb_hal_data_block_t; /**@} */ @@ -667,7 +667,7 @@ SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_ * * @retval ::NRF_SUCCESS */ -SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t *p_gpregret)); +SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t * p_gpregret)); /**@brief Enable or disable the DC/DC regulator for the regulator stage 1 (REG1). * @@ -784,7 +784,7 @@ SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t c * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid. * @retval ::NRF_SUCCESS */ -SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)); +SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void *evt_endpoint, const volatile void *task_endpoint)); /**@brief Task to enable a channel group. * @@ -945,7 +945,7 @@ SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp)); * @retval ::NRF_ERROR_FORBIDDEN Tried to write to an address outside the application flash area. * @retval ::NRF_SUCCESS The command was accepted. */ -SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * p_dst, uint32_t const * p_src, uint32_t size)); +SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * p_dst, uint32_t const *p_src, uint32_t size)); /**@brief Flash Erase page @@ -1001,7 +1001,7 @@ SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)) * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. * @retval ::NRF_SUCCESS Otherwise. */ - SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); +SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); /**@brief Closes a session for radio timeslot requests. * @@ -1014,7 +1014,7 @@ SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)) * @retval ::NRF_ERROR_BUSY If session is currently being closed. * @retval ::NRF_SUCCESS Otherwise. */ - SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); +SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); /**@brief Requests a radio timeslot. * @@ -1046,7 +1046,7 @@ SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)) * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid. * @retval ::NRF_SUCCESS Otherwise. */ - SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t const * p_request)); +SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t const *p_request)); /**@brief Write register protected by the SoftDevice * diff --git a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_svc.h b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_svc.h index 292c69298..e95c298e0 100644 --- a/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_svc.h +++ b/ports/nrf/bluetooth/s140_nrf52_6.1.0/s140_nrf52_6.1.0_API/include/nrf_svc.h @@ -50,33 +50,33 @@ extern "C" { #else #ifndef SVCALL -#if defined (__CC_ARM) +#if defined(__CC_ARM) #define SVCALL(number, return_type, signature) return_type __svc(number) signature -#elif defined (__GNUC__) +#elif defined(__GNUC__) #ifdef __cplusplus #define GCC_CAST_CPP (uint16_t) #else #define GCC_CAST_CPP #endif #define SVCALL(number, return_type, signature) \ - _Pragma("GCC diagnostic push") \ - _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ - __attribute__((naked)) \ - __attribute__((unused)) \ - static return_type signature \ - { \ - __asm( \ - "svc %0\n" \ - "bx r14" : : "I" (GCC_CAST_CPP number) : "r0" \ - ); \ - } \ - _Pragma("GCC diagnostic pop") + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ + __attribute__((naked)) \ + __attribute__((unused)) \ + static return_type signature \ + { \ + __asm( \ + "svc %0\n" \ + "bx r14" : : "I" (GCC_CAST_CPP number) : "r0" \ + ); \ + } \ + _Pragma("GCC diagnostic pop") -#elif defined (__ICCARM__) +#elif defined(__ICCARM__) #define PRAGMA(x) _Pragma(#x) #define SVCALL(number, return_type, signature) \ -PRAGMA(swi_number = (number)) \ - __swi return_type signature; + PRAGMA(swi_number = (number)) \ + __swi return_type signature; #else #define SVCALL(number, return_type, signature) return_type signature #endif diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble.h index d17ac9a59..aa5abd5ef 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble.h @@ -71,17 +71,17 @@ extern "C" { */ enum BLE_COMMON_SVCS { - SD_BLE_ENABLE = BLE_SVC_BASE, /**< Enable and initialize the BLE stack */ - SD_BLE_EVT_GET, /**< Get an event from the pending events queue. */ - SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific base UUID. */ - SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */ - SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */ - SD_BLE_VERSION_GET, /**< Get the local version information (company ID, Link Layer Version, Link Layer Subversion). */ - SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */ - SD_BLE_OPT_SET, /**< Set a BLE option. */ - SD_BLE_OPT_GET, /**< Get a BLE option. */ - SD_BLE_CFG_SET, /**< Add a configuration to the BLE stack. */ - SD_BLE_UUID_VS_REMOVE, /**< Remove a Vendor Specific base UUID. */ + SD_BLE_ENABLE = BLE_SVC_BASE, /**< Enable and initialize the BLE stack */ + SD_BLE_EVT_GET, /**< Get an event from the pending events queue. */ + SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific base UUID. */ + SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */ + SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */ + SD_BLE_VERSION_GET, /**< Get the local version information (company ID, Link Layer Version, Link Layer Subversion). */ + SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */ + SD_BLE_OPT_SET, /**< Set a BLE option. */ + SD_BLE_OPT_GET, /**< Get a BLE option. */ + SD_BLE_CFG_SET, /**< Add a configuration to the BLE stack. */ + SD_BLE_UUID_VS_REMOVE, /**< Remove a Vendor Specific base UUID. */ }; /** @@ -89,9 +89,9 @@ enum BLE_COMMON_SVCS */ enum BLE_COMMON_EVTS { - BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. See @ref ble_evt_user_mem_request_t + BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. See @ref ble_evt_user_mem_request_t \n Reply with @ref sd_ble_user_mem_reply. */ - BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1, /**< User Memory release. See @ref ble_evt_user_mem_release_t */ + BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1, /**< User Memory release. See @ref ble_evt_user_mem_release_t */ }; /**@brief BLE Connection Configuration IDs. @@ -113,7 +113,7 @@ enum BLE_CONN_CFGS */ enum BLE_COMMON_CFGS { - BLE_COMMON_CFG_VS_UUID = BLE_CFG_BASE, /**< Vendor specific base UUID configuration */ + BLE_COMMON_CFG_VS_UUID = BLE_CFG_BASE, /**< Vendor specific base UUID configuration */ }; /**@brief Common Option IDs. @@ -121,9 +121,9 @@ enum BLE_COMMON_CFGS */ enum BLE_COMMON_OPTS { - BLE_COMMON_OPT_PA_LNA = BLE_OPT_BASE + 0, /**< PA and LNA options */ - BLE_COMMON_OPT_CONN_EVT_EXT = BLE_OPT_BASE + 1, /**< Extended connection events option */ - BLE_COMMON_OPT_EXTENDED_RC_CAL = BLE_OPT_BASE + 2, /**< Extended RC calibration option */ + BLE_COMMON_OPT_PA_LNA = BLE_OPT_BASE + 0,/**< PA and LNA options */ + BLE_COMMON_OPT_CONN_EVT_EXT = BLE_OPT_BASE + 1,/**< Extended connection events option */ + BLE_COMMON_OPT_EXTENDED_RC_CAL = BLE_OPT_BASE + 2, /**< Extended RC calibration option */ }; /** @} */ @@ -144,8 +144,8 @@ enum BLE_COMMON_OPTS * If that value has not been configured for any connections then @ref BLE_GATT_ATT_MTU_DEFAULT must be used instead. */ #define BLE_EVT_LEN_MAX(ATT_MTU) ( \ - offsetof(ble_evt_t, evt.gattc_evt.params.prim_srvc_disc_rsp.services) + ((ATT_MTU) - 1) / 4 * sizeof(ble_gattc_service_t) \ -) + offsetof(ble_evt_t, evt.gattc_evt.params.prim_srvc_disc_rsp.services) + ((ATT_MTU)-1) / 4 * sizeof(ble_gattc_service_t) \ + ) /** @defgroup BLE_USER_MEM_TYPES User Memory Types * @{ */ @@ -175,53 +175,53 @@ enum BLE_COMMON_OPTS /**@brief User Memory Block. */ typedef struct { - uint8_t *p_mem; /**< Pointer to the start of the user memory block. */ - uint16_t len; /**< Length in bytes of the user memory block. */ + uint8_t *p_mem; /**< Pointer to the start of the user memory block. */ + uint16_t len; /**< Length in bytes of the user memory block. */ } ble_user_mem_block_t; /**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */ typedef struct { - uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ } ble_evt_user_mem_request_t; /**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */ typedef struct { - uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ - ble_user_mem_block_t mem_block; /**< User memory block */ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ + ble_user_mem_block_t mem_block; /**< User memory block */ } ble_evt_user_mem_release_t; /**@brief Event structure for events not associated with a specific function module. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which this event occurred. */ - union - { - ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */ - ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */ - } params; /**< Event parameter union. */ + uint16_t conn_handle; /**< Connection Handle on which this event occurred. */ + union + { + ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */ + ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */ + } params; /**< Event parameter union. */ } ble_common_evt_t; /**@brief BLE Event header. */ typedef struct { - uint16_t evt_id; /**< Value from a BLE_<module>_EVT series. */ - uint16_t evt_len; /**< Length in octets including this header. */ + uint16_t evt_id; /**< Value from a BLE_<module>_EVT series. */ + uint16_t evt_len; /**< Length in octets including this header. */ } ble_evt_hdr_t; /**@brief Common BLE Event type, wrapping the module specific event reports. */ typedef struct { - ble_evt_hdr_t header; /**< Event header. */ - union - { - ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ - ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ - ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ - ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ - ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ - } evt; /**< Event union. */ + ble_evt_hdr_t header; /**< Event header. */ + union + { + ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ + ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ + ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ + ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ + ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ + } evt; /**< Event union. */ } ble_evt_t; @@ -230,9 +230,9 @@ typedef struct */ typedef struct { - uint8_t version_number; /**< Link Layer Version number. See https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer for assigned values. */ - uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ - uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ + uint8_t version_number; /**< Link Layer Version number. See https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer for assigned values. */ + uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ + uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ } ble_version_t; /** @@ -240,9 +240,9 @@ typedef struct */ typedef struct { - uint8_t enable :1; /**< Enable toggling for this amplifier */ - uint8_t active_high :1; /**< Set the pin to be active high */ - uint8_t gpio_pin :6; /**< The GPIO pin to toggle for this amplifier */ + uint8_t enable : 1; /**< Enable toggling for this amplifier */ + uint8_t active_high : 1; /**< Set the pin to be active high */ + uint8_t gpio_pin : 6; /**< The GPIO pin to toggle for this amplifier */ } ble_pa_lna_cfg_t; /** @@ -260,12 +260,12 @@ typedef struct */ typedef struct { - ble_pa_lna_cfg_t pa_cfg; /**< Power Amplifier configuration */ - ble_pa_lna_cfg_t lna_cfg; /**< Low Noise Amplifier configuration */ + ble_pa_lna_cfg_t pa_cfg; /**< Power Amplifier configuration */ + ble_pa_lna_cfg_t lna_cfg; /**< Low Noise Amplifier configuration */ - uint8_t ppi_ch_id_set; /**< PPI channel used for radio pin setting */ - uint8_t ppi_ch_id_clr; /**< PPI channel used for radio pin clearing */ - uint8_t gpiote_ch_id; /**< GPIOTE channel used for radio pin toggling */ + uint8_t ppi_ch_id_set; /**< PPI channel used for radio pin setting */ + uint8_t ppi_ch_id_clr; /**< PPI channel used for radio pin clearing */ + uint8_t gpiote_ch_id; /**< GPIOTE channel used for radio pin toggling */ } ble_common_opt_pa_lna_t; /** @@ -281,7 +281,7 @@ typedef struct */ typedef struct { - uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */ + uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */ } ble_common_opt_conn_evt_ext_t; /** @@ -301,22 +301,22 @@ typedef struct */ typedef struct { - uint8_t enable : 1; /**< Enable extended RC calibration, enabled by default. */ + uint8_t enable : 1; /**< Enable extended RC calibration, enabled by default. */ } ble_common_opt_extended_rc_cal_t; /**@brief Option structure for common options. */ typedef union { - ble_common_opt_pa_lna_t pa_lna; /**< Parameters for controlling PA and LNA pin toggling. */ - ble_common_opt_conn_evt_ext_t conn_evt_ext; /**< Parameters for enabling extended connection events. */ - ble_common_opt_extended_rc_cal_t extended_rc_cal; /**< Parameters for enabling extended RC calibration. */ + ble_common_opt_pa_lna_t pa_lna; /**< Parameters for controlling PA and LNA pin toggling. */ + ble_common_opt_conn_evt_ext_t conn_evt_ext; /**< Parameters for enabling extended connection events. */ + ble_common_opt_extended_rc_cal_t extended_rc_cal; /**< Parameters for enabling extended RC calibration. */ } ble_common_opt_t; /**@brief Common BLE Option type, wrapping the module specific options. */ typedef union { - ble_common_opt_t common_opt; /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */ - ble_gap_opt_t gap_opt; /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */ + ble_common_opt_t common_opt; /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */ + ble_gap_opt_t gap_opt; /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */ } ble_opt_t; /**@brief BLE connection configuration type, wrapping the module specific configurations, set with @@ -338,17 +338,17 @@ typedef union */ typedef struct { - uint8_t conn_cfg_tag; /**< The application chosen tag it can use with the + uint8_t conn_cfg_tag; /**< The application chosen tag it can use with the @ref sd_ble_gap_adv_start() and @ref sd_ble_gap_connect() calls to select this configuration when creating a connection. Must be different for all connection configurations added and not @ref BLE_CONN_CFG_TAG_DEFAULT. */ - union { - ble_gap_conn_cfg_t gap_conn_cfg; /**< GAP connection configuration, cfg_id is @ref BLE_CONN_CFG_GAP. */ - ble_gattc_conn_cfg_t gattc_conn_cfg; /**< GATTC connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTC. */ - ble_gatts_conn_cfg_t gatts_conn_cfg; /**< GATTS connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTS. */ - ble_gatt_conn_cfg_t gatt_conn_cfg; /**< GATT connection configuration, cfg_id is @ref BLE_CONN_CFG_GATT. */ - ble_l2cap_conn_cfg_t l2cap_conn_cfg; /**< L2CAP connection configuration, cfg_id is @ref BLE_CONN_CFG_L2CAP. */ - } params; /**< Connection configuration union. */ + union { + ble_gap_conn_cfg_t gap_conn_cfg; /**< GAP connection configuration, cfg_id is @ref BLE_CONN_CFG_GAP. */ + ble_gattc_conn_cfg_t gattc_conn_cfg; /**< GATTC connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTC. */ + ble_gatts_conn_cfg_t gatts_conn_cfg; /**< GATTS connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTS. */ + ble_gatt_conn_cfg_t gatt_conn_cfg; /**< GATT connection configuration, cfg_id is @ref BLE_CONN_CFG_GATT. */ + ble_l2cap_conn_cfg_t l2cap_conn_cfg; /**< L2CAP connection configuration, cfg_id is @ref BLE_CONN_CFG_L2CAP. */ + } params; /**< Connection configuration union. */ } ble_conn_cfg_t; /** @@ -358,7 +358,7 @@ typedef struct */ typedef struct { - uint8_t vs_uuid_count; /**< Number of 128-bit Vendor Specific base UUID bases to allocate memory for. + uint8_t vs_uuid_count; /**< Number of 128-bit Vendor Specific base UUID bases to allocate memory for. Default value is @ref BLE_UUID_VS_COUNT_DEFAULT. Maximum value is @ref BLE_UUID_VS_COUNT_MAX. */ } ble_common_cfg_vs_uuid_t; @@ -366,16 +366,16 @@ typedef struct /**@brief Common BLE Configuration type, wrapping the common configurations. */ typedef union { - ble_common_cfg_vs_uuid_t vs_uuid_cfg; /**< Vendor Specific base UUID configuration, cfg_id is @ref BLE_COMMON_CFG_VS_UUID. */ + ble_common_cfg_vs_uuid_t vs_uuid_cfg; /**< Vendor Specific base UUID configuration, cfg_id is @ref BLE_COMMON_CFG_VS_UUID. */ } ble_common_cfg_t; /**@brief BLE Configuration type, wrapping the module specific configurations. */ typedef union { - ble_conn_cfg_t conn_cfg; /**< Connection specific configurations, cfg_id in @ref BLE_CONN_CFGS series. */ - ble_common_cfg_t common_cfg; /**< Global common configurations, cfg_id in @ref BLE_COMMON_CFGS series. */ - ble_gap_cfg_t gap_cfg; /**< Global GAP configurations, cfg_id in @ref BLE_GAP_CFGS series. */ - ble_gatts_cfg_t gatts_cfg; /**< Global GATTS configuration, cfg_id in @ref BLE_GATTS_CFGS series. */ + ble_conn_cfg_t conn_cfg; /**< Connection specific configurations, cfg_id in @ref BLE_CONN_CFGS series. */ + ble_common_cfg_t common_cfg; /**< Global common configurations, cfg_id in @ref BLE_COMMON_CFGS series. */ + ble_gap_cfg_t gap_cfg; /**< Global GAP configurations, cfg_id in @ref BLE_GAP_CFGS series. */ + ble_gatts_cfg_t gatts_cfg; /**< Global GATTS configuration, cfg_id in @ref BLE_GATTS_CFGS series. */ } ble_cfg_t; /** @} */ @@ -466,7 +466,7 @@ SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(uint32_t * p_app_ram_base)); * @retval ::NRF_ERROR_NO_MEM The amount of memory assigned to the SoftDevice by app_ram_base is not * large enough to fit this configuration's memory requirement. */ -SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * p_cfg, uint32_t app_ram_base)); +SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const *p_cfg, uint32_t app_ram_base)); /**@brief Get an event from the pending events queue. * @@ -504,7 +504,7 @@ SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled. * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer. */ -SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len)); +SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t * p_dest, uint16_t * p_len)); /**@brief Add a Vendor Specific base UUID. @@ -533,7 +533,7 @@ SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid. * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs. */ -SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type)); +SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t * p_uuid_type)); /**@brief Remove a Vendor Specific base UUID. @@ -554,7 +554,7 @@ SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_v * @retval ::NRF_ERROR_INVALID_PARAM If p_uuid_type points to a non-valid UUID type. * @retval ::NRF_ERROR_FORBIDDEN If the Vendor Specific base UUID is in use by the ATT Server. */ -SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t *p_uuid_type)); +SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t * p_uuid_type)); /** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure. @@ -575,7 +575,7 @@ SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t *p_uuid_ty * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length. * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs. */ -SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid)); +SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t * p_uuid)); /** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit). @@ -590,7 +590,7 @@ SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uin * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type. */ -SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le)); +SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t * p_uuid_le_len, uint8_t * p_uuid_le)); /**@brief Get Version Information. @@ -603,7 +603,7 @@ SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure). */ -SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version)); +SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t * p_version)); /**@brief Provide a user memory block. @@ -664,7 +664,7 @@ SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported. * */ -SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt)); +SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t * p_opt)); /** @} */ #ifdef __cplusplus diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_err.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_err.h index 1b4820dc3..64e610a2f 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_err.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_err.h @@ -62,12 +62,12 @@ extern "C" { /* @defgroup BLE_ERRORS Error Codes * @{ */ -#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */ -#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */ -#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */ -#define BLE_ERROR_INVALID_ADV_HANDLE (NRF_ERROR_STK_BASE_NUM+0x004) /**< Invalid advertising handle. */ -#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */ -#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM+0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */ +#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM + 0x001) /**< @ref sd_ble_enable has not been called. */ +#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM + 0x002) /**< Invalid connection handle. */ +#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM + 0x003) /**< Invalid attribute handle. */ +#define BLE_ERROR_INVALID_ADV_HANDLE (NRF_ERROR_STK_BASE_NUM + 0x004) /**< Invalid advertising handle. */ +#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM + 0x005) /**< Invalid role. */ +#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM + 0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */ /** @} */ @@ -75,10 +75,10 @@ extern "C" { * @brief Assignment of subranges for module specific error codes. * @note For specific error codes, see ble_<module>.h or ble_error_<module>.h. * @{ */ -#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */ -#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */ -#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */ -#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */ +#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM + 0x100) /**< L2CAP specific errors. */ +#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM + 0x200) /**< GAP specific errors. */ +#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM + 0x300) /**< GATT client specific errors. */ +#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM + 0x400) /**< GATT server specific errors. */ /** @} */ #ifdef __cplusplus diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gap.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gap.h index d657fd6c1..3a3ccc495 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gap.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gap.h @@ -64,49 +64,49 @@ extern "C" { */ enum BLE_GAP_SVCS { - SD_BLE_GAP_ADDR_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ - SD_BLE_GAP_ADDR_GET = BLE_GAP_SVC_BASE + 1, /**< Get own Bluetooth Address. */ - SD_BLE_GAP_WHITELIST_SET = BLE_GAP_SVC_BASE + 2, /**< Set active whitelist. */ - SD_BLE_GAP_DEVICE_IDENTITIES_SET = BLE_GAP_SVC_BASE + 3, /**< Set device identity list. */ - SD_BLE_GAP_PRIVACY_SET = BLE_GAP_SVC_BASE + 4, /**< Set Privacy settings*/ - SD_BLE_GAP_PRIVACY_GET = BLE_GAP_SVC_BASE + 5, /**< Get Privacy settings*/ - SD_BLE_GAP_ADV_SET_CONFIGURE = BLE_GAP_SVC_BASE + 6, /**< Configure an advertising set. */ - SD_BLE_GAP_ADV_START = BLE_GAP_SVC_BASE + 7, /**< Start Advertising. */ - SD_BLE_GAP_ADV_STOP = BLE_GAP_SVC_BASE + 8, /**< Stop Advertising. */ - SD_BLE_GAP_CONN_PARAM_UPDATE = BLE_GAP_SVC_BASE + 9, /**< Connection Parameter Update. */ - SD_BLE_GAP_DISCONNECT = BLE_GAP_SVC_BASE + 10, /**< Disconnect. */ - SD_BLE_GAP_TX_POWER_SET = BLE_GAP_SVC_BASE + 11, /**< Set TX Power. */ - SD_BLE_GAP_APPEARANCE_SET = BLE_GAP_SVC_BASE + 12, /**< Set Appearance. */ - SD_BLE_GAP_APPEARANCE_GET = BLE_GAP_SVC_BASE + 13, /**< Get Appearance. */ - SD_BLE_GAP_PPCP_SET = BLE_GAP_SVC_BASE + 14, /**< Set PPCP. */ - SD_BLE_GAP_PPCP_GET = BLE_GAP_SVC_BASE + 15, /**< Get PPCP. */ - SD_BLE_GAP_DEVICE_NAME_SET = BLE_GAP_SVC_BASE + 16, /**< Set Device Name. */ - SD_BLE_GAP_DEVICE_NAME_GET = BLE_GAP_SVC_BASE + 17, /**< Get Device Name. */ - SD_BLE_GAP_AUTHENTICATE = BLE_GAP_SVC_BASE + 18, /**< Initiate Pairing/Bonding. */ - SD_BLE_GAP_SEC_PARAMS_REPLY = BLE_GAP_SVC_BASE + 19, /**< Reply with Security Parameters. */ - SD_BLE_GAP_AUTH_KEY_REPLY = BLE_GAP_SVC_BASE + 20, /**< Reply with an authentication key. */ - SD_BLE_GAP_LESC_DHKEY_REPLY = BLE_GAP_SVC_BASE + 21, /**< Reply with an LE Secure Connections DHKey. */ - SD_BLE_GAP_KEYPRESS_NOTIFY = BLE_GAP_SVC_BASE + 22, /**< Notify of a keypress during an authentication procedure. */ - SD_BLE_GAP_LESC_OOB_DATA_GET = BLE_GAP_SVC_BASE + 23, /**< Get the local LE Secure Connections OOB data. */ - SD_BLE_GAP_LESC_OOB_DATA_SET = BLE_GAP_SVC_BASE + 24, /**< Set the remote LE Secure Connections OOB data. */ - SD_BLE_GAP_ENCRYPT = BLE_GAP_SVC_BASE + 25, /**< Initiate encryption procedure. */ - SD_BLE_GAP_SEC_INFO_REPLY = BLE_GAP_SVC_BASE + 26, /**< Reply with Security Information. */ - SD_BLE_GAP_CONN_SEC_GET = BLE_GAP_SVC_BASE + 27, /**< Obtain connection security level. */ - SD_BLE_GAP_RSSI_START = BLE_GAP_SVC_BASE + 28, /**< Start reporting of changes in RSSI. */ - SD_BLE_GAP_RSSI_STOP = BLE_GAP_SVC_BASE + 29, /**< Stop reporting of changes in RSSI. */ - SD_BLE_GAP_SCAN_START = BLE_GAP_SVC_BASE + 30, /**< Start Scanning. */ - SD_BLE_GAP_SCAN_STOP = BLE_GAP_SVC_BASE + 31, /**< Stop Scanning. */ - SD_BLE_GAP_CONNECT = BLE_GAP_SVC_BASE + 32, /**< Connect. */ - SD_BLE_GAP_CONNECT_CANCEL = BLE_GAP_SVC_BASE + 33, /**< Cancel ongoing connection procedure. */ - SD_BLE_GAP_RSSI_GET = BLE_GAP_SVC_BASE + 34, /**< Get the last RSSI sample. */ - SD_BLE_GAP_PHY_UPDATE = BLE_GAP_SVC_BASE + 35, /**< Initiate or respond to a PHY Update Procedure. */ - SD_BLE_GAP_DATA_LENGTH_UPDATE = BLE_GAP_SVC_BASE + 36, /**< Initiate or respond to a Data Length Update Procedure. */ - SD_BLE_GAP_QOS_CHANNEL_SURVEY_START = BLE_GAP_SVC_BASE + 37, /**< Start Quality of Service (QoS) channel survey module. */ - SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP = BLE_GAP_SVC_BASE + 38, /**< Stop Quality of Service (QoS) channel survey module. */ - SD_BLE_GAP_ADV_ADDR_GET = BLE_GAP_SVC_BASE + 39, /**< Get the Address used on air while Advertising. */ - SD_BLE_GAP_NEXT_CONN_EVT_COUNTER_GET = BLE_GAP_SVC_BASE + 40, /**< Get the next connection event counter. */ - SD_BLE_GAP_CONN_EVT_TRIGGER_START = BLE_GAP_SVC_BASE + 41, /** Start triggering a given task on connection event start. */ - SD_BLE_GAP_CONN_EVT_TRIGGER_STOP = BLE_GAP_SVC_BASE + 42, /** Stop triggering the task configured using @ref sd_ble_gap_conn_evt_trigger_start. */ + SD_BLE_GAP_ADDR_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ + SD_BLE_GAP_ADDR_GET = BLE_GAP_SVC_BASE + 1, /**< Get own Bluetooth Address. */ + SD_BLE_GAP_WHITELIST_SET = BLE_GAP_SVC_BASE + 2, /**< Set active whitelist. */ + SD_BLE_GAP_DEVICE_IDENTITIES_SET = BLE_GAP_SVC_BASE + 3, /**< Set device identity list. */ + SD_BLE_GAP_PRIVACY_SET = BLE_GAP_SVC_BASE + 4, /**< Set Privacy settings*/ + SD_BLE_GAP_PRIVACY_GET = BLE_GAP_SVC_BASE + 5, /**< Get Privacy settings*/ + SD_BLE_GAP_ADV_SET_CONFIGURE = BLE_GAP_SVC_BASE + 6, /**< Configure an advertising set. */ + SD_BLE_GAP_ADV_START = BLE_GAP_SVC_BASE + 7, /**< Start Advertising. */ + SD_BLE_GAP_ADV_STOP = BLE_GAP_SVC_BASE + 8, /**< Stop Advertising. */ + SD_BLE_GAP_CONN_PARAM_UPDATE = BLE_GAP_SVC_BASE + 9, /**< Connection Parameter Update. */ + SD_BLE_GAP_DISCONNECT = BLE_GAP_SVC_BASE + 10,/**< Disconnect. */ + SD_BLE_GAP_TX_POWER_SET = BLE_GAP_SVC_BASE + 11,/**< Set TX Power. */ + SD_BLE_GAP_APPEARANCE_SET = BLE_GAP_SVC_BASE + 12,/**< Set Appearance. */ + SD_BLE_GAP_APPEARANCE_GET = BLE_GAP_SVC_BASE + 13,/**< Get Appearance. */ + SD_BLE_GAP_PPCP_SET = BLE_GAP_SVC_BASE + 14,/**< Set PPCP. */ + SD_BLE_GAP_PPCP_GET = BLE_GAP_SVC_BASE + 15,/**< Get PPCP. */ + SD_BLE_GAP_DEVICE_NAME_SET = BLE_GAP_SVC_BASE + 16,/**< Set Device Name. */ + SD_BLE_GAP_DEVICE_NAME_GET = BLE_GAP_SVC_BASE + 17,/**< Get Device Name. */ + SD_BLE_GAP_AUTHENTICATE = BLE_GAP_SVC_BASE + 18,/**< Initiate Pairing/Bonding. */ + SD_BLE_GAP_SEC_PARAMS_REPLY = BLE_GAP_SVC_BASE + 19,/**< Reply with Security Parameters. */ + SD_BLE_GAP_AUTH_KEY_REPLY = BLE_GAP_SVC_BASE + 20,/**< Reply with an authentication key. */ + SD_BLE_GAP_LESC_DHKEY_REPLY = BLE_GAP_SVC_BASE + 21,/**< Reply with an LE Secure Connections DHKey. */ + SD_BLE_GAP_KEYPRESS_NOTIFY = BLE_GAP_SVC_BASE + 22,/**< Notify of a keypress during an authentication procedure. */ + SD_BLE_GAP_LESC_OOB_DATA_GET = BLE_GAP_SVC_BASE + 23,/**< Get the local LE Secure Connections OOB data. */ + SD_BLE_GAP_LESC_OOB_DATA_SET = BLE_GAP_SVC_BASE + 24,/**< Set the remote LE Secure Connections OOB data. */ + SD_BLE_GAP_ENCRYPT = BLE_GAP_SVC_BASE + 25,/**< Initiate encryption procedure. */ + SD_BLE_GAP_SEC_INFO_REPLY = BLE_GAP_SVC_BASE + 26,/**< Reply with Security Information. */ + SD_BLE_GAP_CONN_SEC_GET = BLE_GAP_SVC_BASE + 27,/**< Obtain connection security level. */ + SD_BLE_GAP_RSSI_START = BLE_GAP_SVC_BASE + 28,/**< Start reporting of changes in RSSI. */ + SD_BLE_GAP_RSSI_STOP = BLE_GAP_SVC_BASE + 29,/**< Stop reporting of changes in RSSI. */ + SD_BLE_GAP_SCAN_START = BLE_GAP_SVC_BASE + 30,/**< Start Scanning. */ + SD_BLE_GAP_SCAN_STOP = BLE_GAP_SVC_BASE + 31,/**< Stop Scanning. */ + SD_BLE_GAP_CONNECT = BLE_GAP_SVC_BASE + 32,/**< Connect. */ + SD_BLE_GAP_CONNECT_CANCEL = BLE_GAP_SVC_BASE + 33,/**< Cancel ongoing connection procedure. */ + SD_BLE_GAP_RSSI_GET = BLE_GAP_SVC_BASE + 34,/**< Get the last RSSI sample. */ + SD_BLE_GAP_PHY_UPDATE = BLE_GAP_SVC_BASE + 35,/**< Initiate or respond to a PHY Update Procedure. */ + SD_BLE_GAP_DATA_LENGTH_UPDATE = BLE_GAP_SVC_BASE + 36,/**< Initiate or respond to a Data Length Update Procedure. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_START = BLE_GAP_SVC_BASE + 37,/**< Start Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP = BLE_GAP_SVC_BASE + 38,/**< Stop Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_ADV_ADDR_GET = BLE_GAP_SVC_BASE + 39,/**< Get the Address used on air while Advertising. */ + SD_BLE_GAP_NEXT_CONN_EVT_COUNTER_GET = BLE_GAP_SVC_BASE + 40,/**< Get the next connection event counter. */ + SD_BLE_GAP_CONN_EVT_TRIGGER_START = BLE_GAP_SVC_BASE + 41,/** Start triggering a given task on connection event start. */ + SD_BLE_GAP_CONN_EVT_TRIGGER_STOP = BLE_GAP_SVC_BASE + 42,/** Stop triggering the task configured using @ref sd_ble_gap_conn_evt_trigger_start. */ }; /**@brief GAP Event IDs. @@ -114,31 +114,31 @@ enum BLE_GAP_SVCS */ enum BLE_GAP_EVTS { - BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connected to peer. \n See @ref ble_gap_evt_connected_t */ - BLE_GAP_EVT_DISCONNECTED = BLE_GAP_EVT_BASE + 1, /**< Disconnected from peer. \n See @ref ble_gap_evt_disconnected_t. */ - BLE_GAP_EVT_CONN_PARAM_UPDATE = BLE_GAP_EVT_BASE + 2, /**< Connection Parameters updated. \n See @ref ble_gap_evt_conn_param_update_t. */ - BLE_GAP_EVT_SEC_PARAMS_REQUEST = BLE_GAP_EVT_BASE + 3, /**< Request to provide security parameters. \n Reply with @ref sd_ble_gap_sec_params_reply. \n See @ref ble_gap_evt_sec_params_request_t. */ - BLE_GAP_EVT_SEC_INFO_REQUEST = BLE_GAP_EVT_BASE + 4, /**< Request to provide security information. \n Reply with @ref sd_ble_gap_sec_info_reply. \n See @ref ble_gap_evt_sec_info_request_t. */ - BLE_GAP_EVT_PASSKEY_DISPLAY = BLE_GAP_EVT_BASE + 5, /**< Request to display a passkey to the user. \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */ - BLE_GAP_EVT_KEY_PRESSED = BLE_GAP_EVT_BASE + 6, /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t */ - BLE_GAP_EVT_AUTH_KEY_REQUEST = BLE_GAP_EVT_BASE + 7, /**< Request to provide an authentication key. \n Reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_auth_key_request_t. */ - BLE_GAP_EVT_LESC_DHKEY_REQUEST = BLE_GAP_EVT_BASE + 8, /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply. \n See @ref ble_gap_evt_lesc_dhkey_request_t */ - BLE_GAP_EVT_AUTH_STATUS = BLE_GAP_EVT_BASE + 9, /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t. */ - BLE_GAP_EVT_CONN_SEC_UPDATE = BLE_GAP_EVT_BASE + 10, /**< Connection security updated. \n See @ref ble_gap_evt_conn_sec_update_t. */ - BLE_GAP_EVT_TIMEOUT = BLE_GAP_EVT_BASE + 11, /**< Timeout expired. \n See @ref ble_gap_evt_timeout_t. */ - BLE_GAP_EVT_RSSI_CHANGED = BLE_GAP_EVT_BASE + 12, /**< RSSI report. \n See @ref ble_gap_evt_rssi_changed_t. */ - BLE_GAP_EVT_ADV_REPORT = BLE_GAP_EVT_BASE + 13, /**< Advertising report. \n See @ref ble_gap_evt_adv_report_t. */ - BLE_GAP_EVT_SEC_REQUEST = BLE_GAP_EVT_BASE + 14, /**< Security Request. \n Reply with @ref sd_ble_gap_authenticate + BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connected to peer. \n See @ref ble_gap_evt_connected_t */ + BLE_GAP_EVT_DISCONNECTED = BLE_GAP_EVT_BASE + 1, /**< Disconnected from peer. \n See @ref ble_gap_evt_disconnected_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE = BLE_GAP_EVT_BASE + 2, /**< Connection Parameters updated. \n See @ref ble_gap_evt_conn_param_update_t. */ + BLE_GAP_EVT_SEC_PARAMS_REQUEST = BLE_GAP_EVT_BASE + 3, /**< Request to provide security parameters. \n Reply with @ref sd_ble_gap_sec_params_reply. \n See @ref ble_gap_evt_sec_params_request_t. */ + BLE_GAP_EVT_SEC_INFO_REQUEST = BLE_GAP_EVT_BASE + 4, /**< Request to provide security information. \n Reply with @ref sd_ble_gap_sec_info_reply. \n See @ref ble_gap_evt_sec_info_request_t. */ + BLE_GAP_EVT_PASSKEY_DISPLAY = BLE_GAP_EVT_BASE + 5, /**< Request to display a passkey to the user. \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */ + BLE_GAP_EVT_KEY_PRESSED = BLE_GAP_EVT_BASE + 6, /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t */ + BLE_GAP_EVT_AUTH_KEY_REQUEST = BLE_GAP_EVT_BASE + 7, /**< Request to provide an authentication key. \n Reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_auth_key_request_t. */ + BLE_GAP_EVT_LESC_DHKEY_REQUEST = BLE_GAP_EVT_BASE + 8, /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply. \n See @ref ble_gap_evt_lesc_dhkey_request_t */ + BLE_GAP_EVT_AUTH_STATUS = BLE_GAP_EVT_BASE + 9, /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t. */ + BLE_GAP_EVT_CONN_SEC_UPDATE = BLE_GAP_EVT_BASE + 10,/**< Connection security updated. \n See @ref ble_gap_evt_conn_sec_update_t. */ + BLE_GAP_EVT_TIMEOUT = BLE_GAP_EVT_BASE + 11,/**< Timeout expired. \n See @ref ble_gap_evt_timeout_t. */ + BLE_GAP_EVT_RSSI_CHANGED = BLE_GAP_EVT_BASE + 12,/**< RSSI report. \n See @ref ble_gap_evt_rssi_changed_t. */ + BLE_GAP_EVT_ADV_REPORT = BLE_GAP_EVT_BASE + 13,/**< Advertising report. \n See @ref ble_gap_evt_adv_report_t. */ + BLE_GAP_EVT_SEC_REQUEST = BLE_GAP_EVT_BASE + 14,/**< Security Request. \n Reply with @ref sd_ble_gap_authenticate \n or with @ref sd_ble_gap_encrypt if required security information is available . \n See @ref ble_gap_evt_sec_request_t. */ - BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 15, /**< Connection Parameter Update Request. \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */ - BLE_GAP_EVT_SCAN_REQ_REPORT = BLE_GAP_EVT_BASE + 16, /**< Scan request report. \n See @ref ble_gap_evt_scan_req_report_t. */ - BLE_GAP_EVT_PHY_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 17, /**< PHY Update Request. \n Reply with @ref sd_ble_gap_phy_update. \n See @ref ble_gap_evt_phy_update_request_t. */ - BLE_GAP_EVT_PHY_UPDATE = BLE_GAP_EVT_BASE + 18, /**< PHY Update Procedure is complete. \n See @ref ble_gap_evt_phy_update_t. */ - BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 19, /**< Data Length Update Request. \n Reply with @ref sd_ble_gap_data_length_update. \n See @ref ble_gap_evt_data_length_update_request_t. */ - BLE_GAP_EVT_DATA_LENGTH_UPDATE = BLE_GAP_EVT_BASE + 20, /**< LL Data Channel PDU payload length updated. \n See @ref ble_gap_evt_data_length_update_t. */ - BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT = BLE_GAP_EVT_BASE + 21, /**< Channel survey report. \n See @ref ble_gap_evt_qos_channel_survey_report_t. */ - BLE_GAP_EVT_ADV_SET_TERMINATED = BLE_GAP_EVT_BASE + 22, /**< Advertising set terminated. \n See @ref ble_gap_evt_adv_set_terminated_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 15,/**< Connection Parameter Update Request. \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */ + BLE_GAP_EVT_SCAN_REQ_REPORT = BLE_GAP_EVT_BASE + 16,/**< Scan request report. \n See @ref ble_gap_evt_scan_req_report_t. */ + BLE_GAP_EVT_PHY_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 17,/**< PHY Update Request. \n Reply with @ref sd_ble_gap_phy_update. \n See @ref ble_gap_evt_phy_update_request_t. */ + BLE_GAP_EVT_PHY_UPDATE = BLE_GAP_EVT_BASE + 18,/**< PHY Update Procedure is complete. \n See @ref ble_gap_evt_phy_update_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 19, /**< Data Length Update Request. \n Reply with @ref sd_ble_gap_data_length_update. \n See @ref ble_gap_evt_data_length_update_request_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE = BLE_GAP_EVT_BASE + 20, /**< LL Data Channel PDU payload length updated. \n See @ref ble_gap_evt_data_length_update_t. */ + BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT = BLE_GAP_EVT_BASE + 21, /**< Channel survey report. \n See @ref ble_gap_evt_qos_channel_survey_report_t. */ + BLE_GAP_EVT_ADV_SET_TERMINATED = BLE_GAP_EVT_BASE + 22, /**< Advertising set terminated. \n See @ref ble_gap_evt_adv_set_terminated_t. */ }; /**@brief GAP Option IDs. @@ -146,12 +146,12 @@ enum BLE_GAP_EVTS */ enum BLE_GAP_OPTS { - BLE_GAP_OPT_CH_MAP = BLE_GAP_OPT_BASE, /**< Channel Map. @ref ble_gap_opt_ch_map_t */ - BLE_GAP_OPT_LOCAL_CONN_LATENCY = BLE_GAP_OPT_BASE + 1, /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */ - BLE_GAP_OPT_PASSKEY = BLE_GAP_OPT_BASE + 2, /**< Set passkey. @ref ble_gap_opt_passkey_t */ - BLE_GAP_OPT_COMPAT_MODE_1 = BLE_GAP_OPT_BASE + 3, /**< Compatibility mode. @ref ble_gap_opt_compat_mode_1_t */ - BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT = BLE_GAP_OPT_BASE + 4, /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */ - BLE_GAP_OPT_SLAVE_LATENCY_DISABLE = BLE_GAP_OPT_BASE + 5, /**< Disable slave latency. @ref ble_gap_opt_slave_latency_disable_t */ + BLE_GAP_OPT_CH_MAP = BLE_GAP_OPT_BASE, /**< Channel Map. @ref ble_gap_opt_ch_map_t */ + BLE_GAP_OPT_LOCAL_CONN_LATENCY = BLE_GAP_OPT_BASE + 1, /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */ + BLE_GAP_OPT_PASSKEY = BLE_GAP_OPT_BASE + 2, /**< Set passkey. @ref ble_gap_opt_passkey_t */ + BLE_GAP_OPT_COMPAT_MODE_1 = BLE_GAP_OPT_BASE + 3, /**< Compatibility mode. @ref ble_gap_opt_compat_mode_1_t */ + BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT = BLE_GAP_OPT_BASE + 4, /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */ + BLE_GAP_OPT_SLAVE_LATENCY_DISABLE = BLE_GAP_OPT_BASE + 5, /**< Disable slave latency. @ref ble_gap_opt_slave_latency_disable_t */ }; /**@brief GAP Configuration IDs. @@ -160,11 +160,11 @@ enum BLE_GAP_OPTS */ enum BLE_GAP_CFGS { - BLE_GAP_CFG_ROLE_COUNT = BLE_GAP_CFG_BASE, /**< Role count configuration. */ - BLE_GAP_CFG_DEVICE_NAME = BLE_GAP_CFG_BASE + 1, /**< Device name configuration. */ - BLE_GAP_CFG_PPCP_INCL_CONFIG = BLE_GAP_CFG_BASE + 2, /**< Peripheral Preferred Connection Parameters characteristic + BLE_GAP_CFG_ROLE_COUNT = BLE_GAP_CFG_BASE, /**< Role count configuration. */ + BLE_GAP_CFG_DEVICE_NAME = BLE_GAP_CFG_BASE + 1,/**< Device name configuration. */ + BLE_GAP_CFG_PPCP_INCL_CONFIG = BLE_GAP_CFG_BASE + 2, /**< Peripheral Preferred Connection Parameters characteristic inclusion configuration. */ - BLE_GAP_CFG_CAR_INCL_CONFIG = BLE_GAP_CFG_BASE + 3, /**< Central Address Resolution characteristic + BLE_GAP_CFG_CAR_INCL_CONFIG = BLE_GAP_CFG_BASE + 3,/**< Central Address Resolution characteristic inclusion configuration. */ }; @@ -172,9 +172,9 @@ enum BLE_GAP_CFGS */ enum BLE_GAP_TX_POWER_ROLES { - BLE_GAP_TX_POWER_ROLE_ADV = 1, /**< Advertiser role. */ - BLE_GAP_TX_POWER_ROLE_SCAN_INIT = 2, /**< Scanner and initiator role. */ - BLE_GAP_TX_POWER_ROLE_CONN = 3, /**< Connection role. */ + BLE_GAP_TX_POWER_ROLE_ADV = 1, /**< Advertiser role. */ + BLE_GAP_TX_POWER_ROLE_SCAN_INIT = 2, /**< Scanner and initiator role. */ + BLE_GAP_TX_POWER_ROLE_CONN = 3, /**< Connection role. */ }; /** @} */ @@ -324,28 +324,28 @@ enum BLE_GAP_TX_POWER_ROLES * @{ */ #define BLE_GAP_ADV_INTERVAL_MIN 0x000020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */ #define BLE_GAP_ADV_INTERVAL_MAX 0x004000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */ - /**@} */ +/**@} */ /**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min * @{ */ #define BLE_GAP_SCAN_INTERVAL_MIN 0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */ #define BLE_GAP_SCAN_INTERVAL_MAX 0xFFFF /**< Maximum Scan interval in 625 us units, i.e. 40,959.375 s. */ - /** @} */ +/** @} */ /**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min * @{ */ #define BLE_GAP_SCAN_WINDOW_MIN 0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */ #define BLE_GAP_SCAN_WINDOW_MAX 0xFFFF /**< Maximum Scan window in 625 us units, i.e. 40,959.375 s. */ - /** @} */ +/** @} */ /**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min * @{ */ #define BLE_GAP_SCAN_TIMEOUT_MIN 0x0001 /**< Minimum Scan timeout in 10 ms units, i.e 10 ms. */ #define BLE_GAP_SCAN_TIMEOUT_UNLIMITED 0x0000 /**< Continue to scan forever. */ - /** @} */ +/** @} */ /**@defgroup BLE_GAP_SCAN_BUFFER_SIZE GAP Minimum scanner buffer size * @@ -564,19 +564,19 @@ enum BLE_GAP_TX_POWER_ROLES * See @ref ble_gap_conn_sec_mode_t. * @{ */ /**@brief Set sec_mode pointed to by ptr to have no access rights.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while (0) /**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while (0) /**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while (0) /**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while (0) /**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while (0) /**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while (0) /**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0) +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while (0) /**@} */ @@ -651,7 +651,7 @@ enum BLE_GAP_TX_POWER_ROLES #define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS (0) /**< Continuous channel survey. */ #define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MIN_US (7500) /**< Minimum channel survey interval in microseconds (7.5 ms). */ #define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MAX_US (4000000) /**< Maximum channel survey interval in microseconds (4 s). */ - /**@} */ +/**@} */ /** @} */ @@ -683,45 +683,45 @@ enum BLE_GAP_TX_POWER_ROLES /**@brief Advertising event properties. */ typedef struct { - uint8_t type; /**< Advertising type. See @ref BLE_GAP_ADV_TYPES. */ - uint8_t anonymous : 1; /**< Omit advertiser's address from all PDUs. + uint8_t type; /**< Advertising type. See @ref BLE_GAP_ADV_TYPES. */ + uint8_t anonymous : 1;/**< Omit advertiser's address from all PDUs. @note Anonymous advertising is only available for @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED and @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED. */ - uint8_t include_tx_power : 1; /**< This feature is not supported on this SoftDevice. */ + uint8_t include_tx_power : 1; /**< This feature is not supported on this SoftDevice. */ } ble_gap_adv_properties_t; /**@brief Advertising report type. */ typedef struct { - uint16_t connectable : 1; /**< Connectable advertising event type. */ - uint16_t scannable : 1; /**< Scannable advertising event type. */ - uint16_t directed : 1; /**< Directed advertising event type. */ - uint16_t scan_response : 1; /**< Received a scan response. */ - uint16_t extended_pdu : 1; /**< Received an extended advertising set. */ - uint16_t status : 2; /**< Data status. See @ref BLE_GAP_ADV_DATA_STATUS. */ - uint16_t reserved : 9; /**< Reserved for future use. */ + uint16_t connectable : 1;/**< Connectable advertising event type. */ + uint16_t scannable : 1;/**< Scannable advertising event type. */ + uint16_t directed : 1;/**< Directed advertising event type. */ + uint16_t scan_response : 1; /**< Received a scan response. */ + uint16_t extended_pdu : 1;/**< Received an extended advertising set. */ + uint16_t status : 2;/**< Data status. See @ref BLE_GAP_ADV_DATA_STATUS. */ + uint16_t reserved : 9;/**< Reserved for future use. */ } ble_gap_adv_report_type_t; /**@brief Advertising Auxiliary Pointer. */ typedef struct { - uint16_t aux_offset; /**< Time offset from the beginning of advertising packet to the auxiliary packet in 100 us units. */ - uint8_t aux_phy; /**< Indicates the PHY on which the auxiliary advertising packet is sent. See @ref BLE_GAP_PHYS. */ + uint16_t aux_offset; /**< Time offset from the beginning of advertising packet to the auxiliary packet in 100 us units. */ + uint8_t aux_phy; /**< Indicates the PHY on which the auxiliary advertising packet is sent. See @ref BLE_GAP_PHYS. */ } ble_gap_aux_pointer_t; /**@brief Bluetooth Low Energy address. */ typedef struct { - uint8_t addr_id_peer : 1; /**< Only valid for peer addresses. + uint8_t addr_id_peer : 1; /**< Only valid for peer addresses. This bit is set by the SoftDevice to indicate whether the address has been resolved from a Resolvable Private Address (when the peer is using privacy). If set to 1, @ref addr and @ref addr_type refer to the identity address of the resolved address. This bit is ignored when a variable of type @ref ble_gap_addr_t is used as input to API functions. */ - uint8_t addr_type : 7; /**< See @ref BLE_GAP_ADDR_TYPES. */ - uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. + uint8_t addr_type : 7; /**< See @ref BLE_GAP_ADDR_TYPES. */ + uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. @ref addr is not used if @ref addr_type is @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. */ } ble_gap_addr_t; @@ -739,10 +739,10 @@ typedef struct */ typedef struct { - uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ } ble_gap_conn_params_t; @@ -758,8 +758,8 @@ typedef struct */ typedef struct { - uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ - uint8_t lv : 4; /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */ + uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ + uint8_t lv : 4; /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */ } ble_gap_conn_sec_mode_t; @@ -767,14 +767,14 @@ typedef struct /**@brief GAP connection security status.*/ typedef struct { - ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ - uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ + ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ + uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ } ble_gap_conn_sec_t; /**@brief Identity Resolving Key. */ typedef struct { - uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ + uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ } ble_gap_irk_t; @@ -789,8 +789,8 @@ typedef uint8_t ble_gap_ch_mask_t[5]; /**@brief GAP advertising parameters. */ typedef struct { - ble_gap_adv_properties_t properties; /**< The properties of the advertising events. */ - ble_gap_addr_t const *p_peer_addr; /**< Address of a known peer. + ble_gap_adv_properties_t properties; /**< The properties of the advertising events. */ + ble_gap_addr_t const *p_peer_addr; /**< Address of a known peer. @note ble_gap_addr_t::addr_type cannot be @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. - When privacy is enabled and the local device uses @@ -804,16 +804,16 @@ typedef struct in the device identity list, the peer IRK for that device will be used to generate @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE target addresses used in the advertising event PDUs. */ - uint32_t interval; /**< Advertising interval in 625 us units. @sa BLE_GAP_ADV_INTERVALS. + uint32_t interval; /**< Advertising interval in 625 us units. @sa BLE_GAP_ADV_INTERVALS. @note If @ref ble_gap_adv_properties_t::type is set to @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE advertising, this parameter is ignored. */ - uint16_t duration; /**< Advertising duration in 10 ms units. When timeout is reached, + uint16_t duration; /**< Advertising duration in 10 ms units. When timeout is reached, an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised. @sa BLE_GAP_ADV_TIMEOUT_VALUES. @note The SoftDevice will always complete at least one advertising event even if the duration is set too low. */ - uint8_t max_adv_evts; /**< Maximum advertising events that shall be sent prior to disabling + uint8_t max_adv_evts; /**< Maximum advertising events that shall be sent prior to disabling advertising. Setting the value to 0 disables the limitation. When the count of advertising events specified by this parameter (if not 0) is reached, advertising will be automatically stopped @@ -821,17 +821,17 @@ typedef struct @note If @ref ble_gap_adv_properties_t::type is set to @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE, this parameter is ignored. */ - ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. At least one of the primary channels, that is channel index 37-39, must be used. Masking away secondary advertising channels is not supported. */ - uint8_t filter_policy; /**< Filter Policy. @sa BLE_GAP_ADV_FILTER_POLICIES. */ - uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising channel packets + uint8_t filter_policy; /**< Filter Policy. @sa BLE_GAP_ADV_FILTER_POLICIES. */ + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising channel packets are transmitted. If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS will be used. Valid values are @ref BLE_GAP_PHY_1MBPS and @ref BLE_GAP_PHY_CODED. @note The primary_phy shall indicate @ref BLE_GAP_PHY_1MBPS if @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ - uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising channel packets + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising channel packets are transmitted. If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS will be used. Valid values are @@ -841,11 +841,11 @@ typedef struct connection and send AUX_ADV_IND packets on. @note This parameter will be ignored when @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ - uint8_t set_id:4; /**< The advertising set identifier distinguishes this advertising set from other + uint8_t set_id : 4; /**< The advertising set identifier distinguishes this advertising set from other advertising sets transmitted by this and other devices. @note This parameter will be ignored when @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ - uint8_t scan_req_notification:1; /**< Enable scan request notifications for this advertising set. When a + uint8_t scan_req_notification : 1; /**< Enable scan request notifications for this advertising set. When a scan request is received and the scanner address is allowed by the filter policy, @ref BLE_GAP_EVT_SCAN_REQ_REPORT is raised. @note This parameter will be ignored when @@ -866,11 +866,11 @@ typedef struct * To update advertising data while advertising, provide new buffers to @ref sd_ble_gap_adv_set_configure. */ typedef struct { - ble_data_t adv_data; /**< Advertising data. + ble_data_t adv_data; /**< Advertising data. @note Advertising data can only be specified for a @ref ble_gap_adv_properties_t::type that is allowed to contain advertising data. */ - ble_data_t scan_rsp_data; /**< Scan response data. + ble_data_t scan_rsp_data; /**< Scan response data. @note Scan response data can only be specified for a @ref ble_gap_adv_properties_t::type that is scannable. */ @@ -880,11 +880,11 @@ typedef struct /**@brief GAP scanning parameters. */ typedef struct { - uint8_t extended : 1; /**< If 1, the scanner will accept extended advertising packets. + uint8_t extended : 1; /**< If 1, the scanner will accept extended advertising packets. If set to 0, the scanner will not receive advertising packets on secondary advertising channels, and will not be able to receive long advertising PDUs. */ - uint8_t report_incomplete_evts : 1; /**< If 1, events of type @ref ble_gap_evt_adv_report_t may have + uint8_t report_incomplete_evts : 1; /**< If 1, events of type @ref ble_gap_evt_adv_report_t may have @ref ble_gap_adv_report_type_t::status set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. This parameter is ignored when used with @ref sd_ble_gap_connect @@ -892,13 +892,13 @@ typedef struct advertising event, and is only available for extended scanning, see @ref sd_ble_gap_scan_start. @note This feature is not supported by this SoftDevice. */ - uint8_t active : 1; /**< If 1, perform active scanning by sending scan requests. + uint8_t active : 1; /**< If 1, perform active scanning by sending scan requests. This parameter is ignored when used with @ref sd_ble_gap_connect. */ - uint8_t filter_policy : 2; /**< Scanning filter policy. @sa BLE_GAP_SCAN_FILTER_POLICIES. + uint8_t filter_policy : 2; /**< Scanning filter policy. @sa BLE_GAP_SCAN_FILTER_POLICIES. @note Only @ref BLE_GAP_SCAN_FP_ACCEPT_ALL and @ref BLE_GAP_SCAN_FP_WHITELIST are valid when used with @ref sd_ble_gap_connect */ - uint8_t scan_phys; /**< Bitfield of PHYs to scan on. If set to @ref BLE_GAP_PHY_AUTO, + uint8_t scan_phys; /**< Bitfield of PHYs to scan on. If set to @ref BLE_GAP_PHY_AUTO, scan_phys will default to @ref BLE_GAP_PHY_1MBPS. - If @ref ble_gap_scan_params_t::extended is set to 0, the only supported PHY is @ref BLE_GAP_PHY_1MBPS. @@ -916,13 +916,13 @@ typedef struct PHY will also contain @ref BLE_GAP_PHY_CODED. If the only scan PHY is @ref BLE_GAP_PHY_CODED, the primary scan PHY is @ref BLE_GAP_PHY_CODED only. */ - uint16_t interval; /**< Scan interval in 625 us units. @sa BLE_GAP_SCAN_INTERVALS. */ - uint16_t window; /**< Scan window in 625 us units. @sa BLE_GAP_SCAN_WINDOW. + uint16_t interval; /**< Scan interval in 625 us units. @sa BLE_GAP_SCAN_INTERVALS. */ + uint16_t window; /**< Scan window in 625 us units. @sa BLE_GAP_SCAN_WINDOW. If scan_phys contains both @ref BLE_GAP_PHY_1MBPS and @ref BLE_GAP_PHY_CODED interval shall be larger than or equal to twice the scan window. */ - uint16_t timeout; /**< Scan timeout in 10 ms units. @sa BLE_GAP_SCAN_TIMEOUT. */ - ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + uint16_t timeout; /**< Scan timeout in 10 ms units. @sa BLE_GAP_SCAN_TIMEOUT. */ + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. At least one of the primary channels, that is channel index 37-39, must be set to 0. Masking away secondary channels is not supported. */ @@ -948,10 +948,10 @@ typedef struct */ typedef struct { - uint8_t privacy_mode; /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */ - uint8_t private_addr_type; /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */ - uint16_t private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */ - ble_gap_irk_t *p_device_irk; /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used. + uint8_t privacy_mode; /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */ + uint8_t private_addr_type; /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */ + uint16_t private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */ + ble_gap_irk_t *p_device_irk; /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used. When used as output, pointer to IRK structure where the current default IRK will be written to. If NULL, this argument is ignored. By default, the default IRK is used to generate random private resolvable addresses for the local device unless instructed otherwise. */ } ble_gap_privacy_params_t; @@ -967,98 +967,98 @@ typedef struct */ typedef struct { - uint8_t tx_phys; /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */ - uint8_t rx_phys; /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */ + uint8_t tx_phys; /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phys; /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */ } ble_gap_phys_t; /** @brief Keys that can be exchanged during a bonding procedure. */ typedef struct { - uint8_t enc : 1; /**< Long Term Key and Master Identification. */ - uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */ - uint8_t sign : 1; /**< Connection Signature Resolving Key. */ - uint8_t link : 1; /**< Derive the Link Key from the LTK. */ + uint8_t enc : 1; /**< Long Term Key and Master Identification. */ + uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */ + uint8_t sign : 1; /**< Connection Signature Resolving Key. */ + uint8_t link : 1; /**< Derive the Link Key from the LTK. */ } ble_gap_sec_kdist_t; /**@brief GAP security parameters. */ typedef struct { - uint8_t bond : 1; /**< Perform bonding. */ - uint8_t mitm : 1; /**< Enable Man In The Middle protection. */ - uint8_t lesc : 1; /**< Enable LE Secure Connection pairing. */ - uint8_t keypress : 1; /**< Enable generation of keypress notifications. */ - uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ - uint8_t oob : 1; /**< The OOB data flag. + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Enable Man In The Middle protection. */ + uint8_t lesc : 1; /**< Enable LE Secure Connection pairing. */ + uint8_t keypress : 1; /**< Enable generation of keypress notifications. */ + uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ + uint8_t oob : 1; /**< The OOB data flag. - In LE legacy pairing, this flag is set if a device has out of band authentication data. The OOB method is used if both of the devices have out of band authentication data. - In LE Secure Connections pairing, this flag is set if a device has the peer device's out of band authentication data. The OOB method is used if at least one device has the peer device's OOB data available. */ - uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */ - uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ - ble_gap_sec_kdist_t kdist_own; /**< Key distribution bitmap: keys that the local device will distribute. */ - ble_gap_sec_kdist_t kdist_peer; /**< Key distribution bitmap: keys that the remote device will distribute. */ + uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */ + uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ + ble_gap_sec_kdist_t kdist_own; /**< Key distribution bitmap: keys that the local device will distribute. */ + ble_gap_sec_kdist_t kdist_peer; /**< Key distribution bitmap: keys that the remote device will distribute. */ } ble_gap_sec_params_t; /**@brief GAP Encryption Information. */ typedef struct { - uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ - uint8_t lesc : 1; /**< Key generated using LE Secure Connections. */ - uint8_t auth : 1; /**< Authenticated Key. */ - uint8_t ltk_len : 6; /**< LTK length in octets. */ + uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ + uint8_t lesc : 1; /**< Key generated using LE Secure Connections. */ + uint8_t auth : 1; /**< Authenticated Key. */ + uint8_t ltk_len : 6; /**< LTK length in octets. */ } ble_gap_enc_info_t; /**@brief GAP Master Identification. */ typedef struct { - uint16_t ediv; /**< Encrypted Diversifier. */ - uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */ + uint16_t ediv; /**< Encrypted Diversifier. */ + uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */ } ble_gap_master_id_t; /**@brief GAP Signing Information. */ typedef struct { - uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */ + uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */ } ble_gap_sign_info_t; /**@brief GAP LE Secure Connections P-256 Public Key. */ typedef struct { - uint8_t pk[BLE_GAP_LESC_P256_PK_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */ + uint8_t pk[BLE_GAP_LESC_P256_PK_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */ } ble_gap_lesc_p256_pk_t; /**@brief GAP LE Secure Connections DHKey. */ typedef struct { - uint8_t key[BLE_GAP_LESC_DHKEY_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */ + uint8_t key[BLE_GAP_LESC_DHKEY_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */ } ble_gap_lesc_dhkey_t; /**@brief GAP LE Secure Connections OOB data. */ typedef struct { - ble_gap_addr_t addr; /**< Bluetooth address of the device. */ - uint8_t r[BLE_GAP_SEC_KEY_LEN]; /**< Random Number. */ - uint8_t c[BLE_GAP_SEC_KEY_LEN]; /**< Confirm Value. */ + ble_gap_addr_t addr; /**< Bluetooth address of the device. */ + uint8_t r[BLE_GAP_SEC_KEY_LEN]; /**< Random Number. */ + uint8_t c[BLE_GAP_SEC_KEY_LEN]; /**< Confirm Value. */ } ble_gap_lesc_oob_data_t; /**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */ typedef struct { - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the device's identity address. */ - uint8_t role; /**< BLE role for this connection, see @ref BLE_GAP_ROLES */ - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ - uint8_t adv_handle; /**< Advertising handle in which advertising has ended. + uint8_t role; /**< BLE role for this connection, see @ref BLE_GAP_ROLES */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ - ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated advertising set. The advertising buffers provided in @ref sd_ble_gap_adv_set_configure are now released. This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ @@ -1068,53 +1068,53 @@ typedef struct /**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */ typedef struct { - uint8_t reason; /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */ + uint8_t reason; /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */ } ble_gap_evt_disconnected_t; /**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */ typedef struct { - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ } ble_gap_evt_conn_param_update_t; /**@brief Event structure for @ref BLE_GAP_EVT_PHY_UPDATE_REQUEST. */ typedef struct { - ble_gap_phys_t peer_preferred_phys; /**< The PHYs the peer prefers to use. */ + ble_gap_phys_t peer_preferred_phys; /**< The PHYs the peer prefers to use. */ } ble_gap_evt_phy_update_request_t; /**@brief Event Structure for @ref BLE_GAP_EVT_PHY_UPDATE. */ typedef struct { - uint8_t status; /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES.*/ - uint8_t tx_phy; /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */ - uint8_t rx_phy; /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */ + uint8_t status; /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES.*/ + uint8_t tx_phy; /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phy; /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */ } ble_gap_evt_phy_update_t; /**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */ typedef struct { - ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ + ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ } ble_gap_evt_sec_params_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */ typedef struct { - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ - ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */ - uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ - uint8_t id_info : 1; /**< If 1, Identity Information required. */ - uint8_t sign_info : 1; /**< If 1, Signing Information required. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ + ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */ + uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ + uint8_t id_info : 1; /**< If 1, Identity Information required. */ + uint8_t sign_info : 1; /**< If 1, Signing Information required. */ } ble_gap_evt_sec_info_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */ typedef struct { - uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ - uint8_t match_request : 1; /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply + uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ + uint8_t match_request : 1; /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */ } ble_gap_evt_passkey_display_t; @@ -1122,22 +1122,22 @@ typedef struct /**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */ typedef struct { - uint8_t kp_not; /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */ + uint8_t kp_not; /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */ } ble_gap_evt_key_pressed_t; /**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */ typedef struct { - uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ + uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ } ble_gap_evt_auth_key_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */ typedef struct { - ble_gap_lesc_p256_pk_t *p_pk_peer; /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory + ble_gap_lesc_p256_pk_t *p_pk_peer; /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */ - uint8_t oobd_req :1; /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */ + uint8_t oobd_req : 1; /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */ } ble_gap_evt_lesc_dhkey_request_t; @@ -1146,36 +1146,36 @@ typedef struct */ typedef struct { - uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ - uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ - uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ - uint8_t lv4 : 1; /**< If 1: Level 4 is supported. */ + uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ + uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ + uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ + uint8_t lv4 : 1; /**< If 1: Level 4 is supported. */ } ble_gap_sec_levels_t; /**@brief Encryption Key. */ typedef struct { - ble_gap_enc_info_t enc_info; /**< Encryption Information. */ - ble_gap_master_id_t master_id; /**< Master Identification. */ + ble_gap_enc_info_t enc_info; /**< Encryption Information. */ + ble_gap_master_id_t master_id; /**< Master Identification. */ } ble_gap_enc_key_t; /**@brief Identity Key. */ typedef struct { - ble_gap_irk_t id_info; /**< Identity Resolving Key. */ - ble_gap_addr_t id_addr_info; /**< Identity Address. */ + ble_gap_irk_t id_info; /**< Identity Resolving Key. */ + ble_gap_addr_t id_addr_info; /**< Identity Address. */ } ble_gap_id_key_t; /**@brief Security Keys. */ typedef struct { - ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */ - ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */ - ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */ - ble_gap_lesc_p256_pk_t *p_pk; /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined + ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */ + ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */ + ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */ + ble_gap_lesc_p256_pk_t *p_pk; /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */ } ble_gap_sec_keys_t; @@ -1183,80 +1183,80 @@ typedef struct /**@brief Security key set for both local and peer keys. */ typedef struct { - ble_gap_sec_keys_t keys_own; /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */ - ble_gap_sec_keys_t keys_peer; /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */ + ble_gap_sec_keys_t keys_own; /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */ + ble_gap_sec_keys_t keys_peer; /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */ } ble_gap_sec_keyset_t; /**@brief Data Length Update Procedure parameters. */ typedef struct { - uint16_t max_tx_octets; /**< Maximum number of payload octets that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ - uint16_t max_rx_octets; /**< Maximum number of payload octets that a Controller supports for reception of a single Link Layer Data Channel PDU. */ - uint16_t max_tx_time_us; /**< Maximum time, in microseconds, that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ - uint16_t max_rx_time_us; /**< Maximum time, in microseconds, that a Controller supports for reception of a single Link Layer Data Channel PDU. */ + uint16_t max_tx_octets; /**< Maximum number of payload octets that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_octets; /**< Maximum number of payload octets that a Controller supports for reception of a single Link Layer Data Channel PDU. */ + uint16_t max_tx_time_us; /**< Maximum time, in microseconds, that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_time_us; /**< Maximum time, in microseconds, that a Controller supports for reception of a single Link Layer Data Channel PDU. */ } ble_gap_data_length_params_t; /**@brief Data Length Update Procedure local limitation. */ typedef struct { - uint16_t tx_payload_limited_octets; /**< If > 0, the requested TX packet length is too long by this many octets. */ - uint16_t rx_payload_limited_octets; /**< If > 0, the requested RX packet length is too long by this many octets. */ - uint16_t tx_rx_time_limited_us; /**< If > 0, the requested combination of TX and RX packet lengths is too long by this many microseconds. */ + uint16_t tx_payload_limited_octets; /**< If > 0, the requested TX packet length is too long by this many octets. */ + uint16_t rx_payload_limited_octets; /**< If > 0, the requested RX packet length is too long by this many octets. */ + uint16_t tx_rx_time_limited_us; /**< If > 0, the requested combination of TX and RX packet lengths is too long by this many microseconds. */ } ble_gap_data_length_limitation_t; /**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */ typedef struct { - uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ - uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ - uint8_t bonded : 1; /**< Procedure resulted in a bond. */ - uint8_t lesc : 1; /**< Procedure resulted in a LE Secure Connection. */ - ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ - ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ - ble_gap_sec_kdist_t kdist_own; /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */ - ble_gap_sec_kdist_t kdist_peer; /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */ + uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ + uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ + uint8_t bonded : 1; /**< Procedure resulted in a bond. */ + uint8_t lesc : 1; /**< Procedure resulted in a LE Secure Connection. */ + ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ + ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ + ble_gap_sec_kdist_t kdist_own; /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */ + ble_gap_sec_kdist_t kdist_peer; /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */ } ble_gap_evt_auth_status_t; /**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */ typedef struct { - ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ + ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ } ble_gap_evt_conn_sec_update_t; /**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */ typedef struct { - uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ - union - { - ble_data_t adv_report_buffer; /**< If source is set to @ref BLE_GAP_TIMEOUT_SRC_SCAN, the released + uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ + union + { + ble_data_t adv_report_buffer; /**< If source is set to @ref BLE_GAP_TIMEOUT_SRC_SCAN, the released scan buffer is contained in this field. */ - } params; /**< Event Parameters. */ + } params; /**< Event Parameters. */ } ble_gap_evt_timeout_t; /**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */ typedef struct { - int8_t rssi; /**< Received Signal Strength Indication in dBm. + int8_t rssi; /**< Received Signal Strength Indication in dBm. @note ERRATA-153 and ERRATA-225 require the rssi sample to be compensated based on a temperature measurement. */ - uint8_t ch_index; /**< Data Channel Index on which the Signal Strength is measured (0-36). */ + uint8_t ch_index; /**< Data Channel Index on which the Signal Strength is measured (0-36). */ } ble_gap_evt_rssi_changed_t; /**@brief Event structure for @ref BLE_GAP_EVT_ADV_SET_TERMINATED */ typedef struct { - uint8_t reason; /**< Reason for why the advertising set terminated. See + uint8_t reason; /**< Reason for why the advertising set terminated. See @ref BLE_GAP_EVT_ADV_SET_TERMINATED_REASON. */ - uint8_t adv_handle; /**< Advertising handle in which advertising has ended. */ - uint8_t num_completed_adv_events; /**< If @ref ble_gap_adv_params_t::max_adv_evts was not set to 0, + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. */ + uint8_t num_completed_adv_events; /**< If @ref ble_gap_adv_params_t::max_adv_evts was not set to 0, this field indicates the number of completed advertising events. */ - ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated advertising set. The advertising buffers provided in @ref sd_ble_gap_adv_set_configure are now released. */ } ble_gap_evt_adv_set_terminated_t; @@ -1271,11 +1271,11 @@ typedef struct */ typedef struct { - ble_gap_adv_report_type_t type; /**< Advertising report type. See @ref ble_gap_adv_report_type_t. */ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr is resolved: + ble_gap_adv_report_type_t type; /**< Advertising report type. See @ref ble_gap_adv_report_type_t. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr is resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the peer's identity address. */ - ble_gap_addr_t direct_addr; /**< Contains the target address of the advertising event if + ble_gap_addr_t direct_addr; /**< Contains the target address of the advertising event if @ref ble_gap_adv_report_type_t::directed is set to 1. If the SoftDevice was able to resolve the address, @ref ble_gap_addr_t::addr_id_peer is set to 1 and the direct_addr @@ -1284,28 +1284,28 @@ typedef struct and the SoftDevice was unable to resolve it, the application may try to resolve this address to find out if the advertising event was directed to us. */ - uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising packet was received. + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising packet was received. See @ref BLE_GAP_PHYS. */ - uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising packet was received. + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising packet was received. See @ref BLE_GAP_PHYS. This field is set to @ref BLE_GAP_PHY_NOT_SET if no packets were received on a secondary advertising channel. */ - int8_t tx_power; /**< TX Power reported by the advertiser in the last packet header received. + int8_t tx_power; /**< TX Power reported by the advertiser in the last packet header received. This field is set to @ref BLE_GAP_POWER_LEVEL_INVALID if the last received packet did not contain the Tx Power field. @note TX Power is only included in extended advertising packets. */ - int8_t rssi; /**< Received Signal Strength Indication in dBm of the last packet received. + int8_t rssi; /**< Received Signal Strength Indication in dBm of the last packet received. @note ERRATA-153 and ERRATA-225 require the rssi sample to be compensated based on a temperature measurement. */ - uint8_t ch_index; /**< Channel Index on which the last advertising packet is received (0-39). */ - uint8_t set_id; /**< Set ID of the received advertising data. Set ID is not present + uint8_t ch_index; /**< Channel Index on which the last advertising packet is received (0-39). */ + uint8_t set_id; /**< Set ID of the received advertising data. Set ID is not present if set to @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ - uint16_t data_id:12; /**< The advertising data ID of the received advertising data. Data ID + uint16_t data_id : 12; /**< The advertising data ID of the received advertising data. Data ID is not present if @ref ble_gap_evt_adv_report_t::set_id is set to @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ - ble_data_t data; /**< Received advertising or scan response data. If + ble_data_t data; /**< Received advertising or scan response data. If @ref ble_gap_adv_report_type_t::status is not set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the data buffer provided in @ref sd_ble_gap_scan_start is now released. */ - ble_gap_aux_pointer_t aux_pointer; /**< The offset and PHY of the next advertising packet in this extended advertising + ble_gap_aux_pointer_t aux_pointer; /**< The offset and PHY of the next advertising packet in this extended advertising event. @note This field is only set if @ref ble_gap_adv_report_type_t::status is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. */ } ble_gap_evt_adv_report_t; @@ -1314,27 +1314,27 @@ typedef struct /**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */ typedef struct { - uint8_t bond : 1; /**< Perform bonding. */ - uint8_t mitm : 1; /**< Man In The Middle protection requested. */ - uint8_t lesc : 1; /**< LE Secure Connections requested. */ - uint8_t keypress : 1; /**< Generation of keypress notifications requested. */ + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Man In The Middle protection requested. */ + uint8_t lesc : 1; /**< LE Secure Connections requested. */ + uint8_t keypress : 1; /**< Generation of keypress notifications requested. */ } ble_gap_evt_sec_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */ typedef struct { - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ } ble_gap_evt_conn_param_update_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */ typedef struct { - uint8_t adv_handle; /**< Advertising handle for the advertising set which received the Scan Request */ - int8_t rssi; /**< Received Signal Strength Indication in dBm. + uint8_t adv_handle; /**< Advertising handle for the advertising set which received the Scan Request */ + int8_t rssi; /**< Received Signal Strength Indication in dBm. @note ERRATA-153 and ERRATA-225 require the rssi sample to be compensated based on a temperature measurement. */ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the device's identity address. */ } ble_gap_evt_scan_req_report_t; @@ -1342,7 +1342,7 @@ typedef struct /**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST. */ typedef struct { - ble_gap_data_length_params_t peer_params; /**< Peer data length parameters. */ + ble_gap_data_length_params_t peer_params; /**< Peer data length parameters. */ } ble_gap_evt_data_length_update_request_t; /**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE. @@ -1351,14 +1351,14 @@ typedef struct */ typedef struct { - ble_gap_data_length_params_t effective_params; /**< The effective data length parameters. */ + ble_gap_data_length_params_t effective_params; /**< The effective data length parameters. */ } ble_gap_evt_data_length_update_t; /**@brief Event structure for @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT. */ typedef struct { - int8_t channel_energy[BLE_GAP_CHANNEL_COUNT]; /**< The measured energy on the Bluetooth Low Energy + int8_t channel_energy[BLE_GAP_CHANNEL_COUNT]; /**< The measured energy on the Bluetooth Low Energy channels, in dBm, indexed by Channel Index. If no measurement is available for the given channel, channel_energy is set to @ref BLE_GAP_POWER_LEVEL_INVALID. */ @@ -1367,33 +1367,33 @@ typedef struct /**@brief GAP event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ - union /**< union alternative identified by evt_id in enclosing struct. */ - { - ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ - ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ - ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ - ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ - ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ - ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ - ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. */ - ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ - ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. */ - ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ - ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ - ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ - ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event Parameters. */ - ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */ - ble_gap_evt_adv_set_terminated_t adv_set_terminated; /**< Advertising Set Terminated Event Parameters. */ - ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */ - ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */ - ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report Parameters. */ - ble_gap_evt_phy_update_request_t phy_update_request; /**< PHY Update Request Event Parameters. */ - ble_gap_evt_phy_update_t phy_update; /**< PHY Update Parameters. */ - ble_gap_evt_data_length_update_request_t data_length_update_request; /**< Data Length Update Request Event Parameters. */ - ble_gap_evt_data_length_update_t data_length_update; /**< Data Length Update Event Parameters. */ - ble_gap_evt_qos_channel_survey_report_t qos_channel_survey_report; /**< Quality of Service (QoS) Channel Survey Report Parameters. */ - } params; /**< Event Parameters. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + union /**< union alternative identified by evt_id in enclosing struct. */ + { + ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ + ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ + ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ + ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ + ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ + ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. */ + ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ + ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. */ + ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ + ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ + ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event Parameters. */ + ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */ + ble_gap_evt_adv_set_terminated_t adv_set_terminated; /**< Advertising Set Terminated Event Parameters. */ + ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */ + ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report Parameters. */ + ble_gap_evt_phy_update_request_t phy_update_request; /**< PHY Update Request Event Parameters. */ + ble_gap_evt_phy_update_t phy_update; /**< PHY Update Parameters. */ + ble_gap_evt_data_length_update_request_t data_length_update_request; /**< Data Length Update Request Event Parameters. */ + ble_gap_evt_data_length_update_t data_length_update; /**< Data Length Update Event Parameters. */ + ble_gap_evt_qos_channel_survey_report_t qos_channel_survey_report; /**< Quality of Service (QoS) Channel Survey Report Parameters. */ + } params; /**< Event Parameters. */ } ble_gap_evt_t; @@ -1407,9 +1407,9 @@ typedef struct */ typedef struct { - uint8_t conn_count; /**< The number of concurrent connections the application can create with this configuration. + uint8_t conn_count; /**< The number of concurrent connections the application can create with this configuration. The default and minimum value is @ref BLE_GAP_CONN_COUNT_DEFAULT. */ - uint16_t event_length; /**< The time set aside for this connection on every connection interval in 1.25 ms units. + uint16_t event_length; /**< The time set aside for this connection on every connection interval in 1.25 ms units. The default value is @ref BLE_GAP_EVENT_LENGTH_DEFAULT, the minimum value is @ref BLE_GAP_EVENT_LENGTH_MIN. The event length and the connection interval are the primary parameters for setting the throughput of a connection. @@ -1431,11 +1431,11 @@ typedef struct */ typedef struct { - uint8_t adv_set_count; /**< Maximum number of advertising sets. Default value is @ref BLE_GAP_ADV_SET_COUNT_DEFAULT. */ - uint8_t periph_role_count; /**< Maximum number of connections concurrently acting as a peripheral. Default value is @ref BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT. */ - uint8_t central_role_count; /**< Maximum number of connections concurrently acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT. */ - uint8_t central_sec_count; /**< Number of SMP instances shared between all connections acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT. */ - uint8_t qos_channel_survey_role_available:1; /**< If set, the Quality of Service (QoS) channel survey module is available to the + uint8_t adv_set_count; /**< Maximum number of advertising sets. Default value is @ref BLE_GAP_ADV_SET_COUNT_DEFAULT. */ + uint8_t periph_role_count; /**< Maximum number of connections concurrently acting as a peripheral. Default value is @ref BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT. */ + uint8_t central_role_count; /**< Maximum number of connections concurrently acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT. */ + uint8_t central_sec_count; /**< Number of SMP instances shared between all connections acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT. */ + uint8_t qos_channel_survey_role_available : 1; /**< If set, the Quality of Service (QoS) channel survey module is available to the application using @ref sd_ble_gap_qos_channel_survey_start. */ } ble_gap_cfg_role_count_t; @@ -1470,18 +1470,18 @@ typedef struct */ typedef struct { - ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ - uint8_t vloc:2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ - uint8_t *p_value; /**< Pointer to where the value (device name) is stored or will be stored. */ - uint16_t current_len; /**< Current length in bytes of the memory pointed to by p_value.*/ - uint16_t max_len; /**< Maximum length in bytes of the memory pointed to by p_value.*/ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vloc : 2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t *p_value; /**< Pointer to where the value (device name) is stored or will be stored. */ + uint16_t current_len; /**< Current length in bytes of the memory pointed to by p_value.*/ + uint16_t max_len; /**< Maximum length in bytes of the memory pointed to by p_value.*/ } ble_gap_cfg_device_name_t; /**@brief Peripheral Preferred Connection Parameters include configuration parameters, set with @ref sd_ble_cfg_set. */ typedef struct { - uint8_t include_cfg; /**< Inclusion configuration of the Peripheral Preferred Connection Parameters characteristic. + uint8_t include_cfg; /**< Inclusion configuration of the Peripheral Preferred Connection Parameters characteristic. See @ref BLE_GAP_CHAR_INCL_CONFIG. Default is @ref BLE_GAP_PPCP_INCL_CONFIG_DEFAULT. */ } ble_gap_cfg_ppcp_incl_cfg_t; @@ -1489,7 +1489,7 @@ typedef struct /**@brief Central Address Resolution include configuration parameters, set with @ref sd_ble_cfg_set. */ typedef struct { - uint8_t include_cfg; /**< Inclusion configuration of the Central Address Resolution characteristic. + uint8_t include_cfg; /**< Inclusion configuration of the Central Address Resolution characteristic. See @ref BLE_GAP_CHAR_INCL_CONFIG. Default is @ref BLE_GAP_CAR_INCL_CONFIG_DEFAULT. */ } ble_gap_cfg_car_incl_cfg_t; @@ -1497,11 +1497,11 @@ typedef struct /**@brief Configuration structure for GAP configurations. */ typedef union { - ble_gap_cfg_role_count_t role_count_cfg; /**< Role count configuration, cfg_id is @ref BLE_GAP_CFG_ROLE_COUNT. */ - ble_gap_cfg_device_name_t device_name_cfg; /**< Device name configuration, cfg_id is @ref BLE_GAP_CFG_DEVICE_NAME. */ - ble_gap_cfg_ppcp_incl_cfg_t ppcp_include_cfg; /**< Peripheral Preferred Connection Parameters characteristic include + ble_gap_cfg_role_count_t role_count_cfg; /**< Role count configuration, cfg_id is @ref BLE_GAP_CFG_ROLE_COUNT. */ + ble_gap_cfg_device_name_t device_name_cfg; /**< Device name configuration, cfg_id is @ref BLE_GAP_CFG_DEVICE_NAME. */ + ble_gap_cfg_ppcp_incl_cfg_t ppcp_include_cfg; /**< Peripheral Preferred Connection Parameters characteristic include configuration, cfg_id is @ref BLE_GAP_CFG_PPCP_INCL_CONFIG. */ - ble_gap_cfg_car_incl_cfg_t car_include_cfg; /**< Central Address Resolution characteristic include configuration, + ble_gap_cfg_car_incl_cfg_t car_include_cfg; /**< Central Address Resolution characteristic include configuration, cfg_id is @ref BLE_GAP_CFG_CAR_INCL_CONFIG. */ } ble_gap_cfg_t; @@ -1531,8 +1531,8 @@ typedef union */ typedef struct { - uint16_t conn_handle; /**< Connection Handle (only applicable for get) */ - uint8_t ch_map[5]; /**< Channel Map (37-bit). */ + uint16_t conn_handle; /**< Connection Handle (only applicable for get) */ + uint8_t ch_map[5]; /**< Channel Map (37-bit). */ } ble_gap_opt_ch_map_t; @@ -1560,9 +1560,9 @@ typedef struct */ typedef struct { - uint16_t conn_handle; /**< Connection Handle */ - uint16_t requested_latency; /**< Requested local connection latency. */ - uint16_t * p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t requested_latency; /**< Requested local connection latency. */ + uint16_t *p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ } ble_gap_opt_local_conn_latency_t; /**@brief Disable slave latency @@ -1579,8 +1579,8 @@ typedef struct */ typedef struct { - uint16_t conn_handle; /**< Connection Handle */ - uint8_t disable : 1; /**< Set to 1 to disable slave latency. Set to 0 enable it again.*/ + uint16_t conn_handle; /**< Connection Handle */ + uint8_t disable : 1; /**< Set to 1 to disable slave latency. Set to 0 enable it again.*/ } ble_gap_opt_slave_latency_disable_t; /**@brief Passkey Option. @@ -1600,7 +1600,7 @@ typedef struct */ typedef struct { - uint8_t const * p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ + uint8_t const *p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ } ble_gap_opt_passkey_t; @@ -1621,7 +1621,7 @@ typedef struct */ typedef struct { - uint8_t enable : 1; /**< Enable compatibility mode 1.*/ + uint8_t enable : 1; /**< Enable compatibility mode 1.*/ } ble_gap_opt_compat_mode_1_t; @@ -1646,31 +1646,31 @@ typedef struct */ typedef struct { - uint16_t conn_handle; /**< Connection Handle */ - uint16_t auth_payload_timeout; /**< Requested timeout in 10 ms unit, see @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT. */ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t auth_payload_timeout; /**< Requested timeout in 10 ms unit, see @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT. */ } ble_gap_opt_auth_payload_timeout_t; /**@brief Option structure for GAP options. */ typedef union { - ble_gap_opt_ch_map_t ch_map; /**< Parameters for the Channel Map option. */ - ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Parameters for the Local connection latency option */ - ble_gap_opt_passkey_t passkey; /**< Parameters for the Passkey option.*/ - ble_gap_opt_compat_mode_1_t compat_mode_1; /**< Parameters for the compatibility mode 1 option.*/ - ble_gap_opt_auth_payload_timeout_t auth_payload_timeout; /**< Parameters for the authenticated payload timeout option.*/ - ble_gap_opt_slave_latency_disable_t slave_latency_disable; /**< Parameters for the Disable slave latency option */ + ble_gap_opt_ch_map_t ch_map; /**< Parameters for the Channel Map option. */ + ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Parameters for the Local connection latency option */ + ble_gap_opt_passkey_t passkey; /**< Parameters for the Passkey option.*/ + ble_gap_opt_compat_mode_1_t compat_mode_1; /**< Parameters for the compatibility mode 1 option.*/ + ble_gap_opt_auth_payload_timeout_t auth_payload_timeout; /**< Parameters for the authenticated payload timeout option.*/ + ble_gap_opt_slave_latency_disable_t slave_latency_disable; /**< Parameters for the Disable slave latency option */ } ble_gap_opt_t; /**@brief Connection event triggering parameters. */ typedef struct { - uint8_t ppi_ch_id; /**< PPI channel to use. This channel should be regarded as reserved until + uint8_t ppi_ch_id; /**< PPI channel to use. This channel should be regarded as reserved until connection event PPI task triggering is stopped. The PPI channel ID can not be one of the PPI channels reserved by the SoftDevice. See @ref NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK. */ - uint32_t task_endpoint; /**< Task Endpoint to trigger. */ - uint16_t conn_evt_counter_start; /**< The connection event on which the task triggering should start. */ - uint16_t period_in_events; /**< Trigger period. Valid range is [1, 32767]. + uint32_t task_endpoint; /**< Task Endpoint to trigger. */ + uint16_t conn_evt_counter_start; /**< The connection event on which the task triggering should start. */ + uint16_t period_in_events; /**< Trigger period. Valid range is [1, 32767]. If the device is in slave role and slave latency is enabled, this parameter should be set to a multiple of (slave latency + 1) to ensure low power operation. */ @@ -1721,7 +1721,7 @@ SVCALL(SD_BLE_GAP_ADDR_SET, uint32_t, sd_ble_gap_addr_set(ble_gap_addr_t const * * @retval ::NRF_SUCCESS Address successfully retrieved. * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. */ -SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr)); +SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t * p_addr)); /**@brief Get the Bluetooth device address used by the advertiser. @@ -1740,7 +1740,7 @@ SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. * @retval ::NRF_ERROR_INVALID_STATE The advertising set is currently not advertising. */ -SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr)); +SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t * p_addr)); /**@brief Set the active whitelist in the SoftDevice. @@ -1766,7 +1766,7 @@ SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_ha * @retval ::NRF_ERROR_DATA_SIZE The given whitelist size is invalid (zero or too large); this can only return when * pp_wl_addrs is not NULL. */ -SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const * const * pp_wl_addrs, uint8_t len)); +SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const *const *pp_wl_addrs, uint8_t len)); /**@brief Set device identity list. @@ -1797,7 +1797,7 @@ SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr * @retval ::NRF_ERROR_DATA_SIZE The given device identity list size invalid (zero or too large); this can * only return when pp_id_keys is not NULL. */ -SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const * const * pp_id_keys, ble_gap_irk_t const * const * pp_local_irks, uint8_t len)); +SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const *const *pp_id_keys, ble_gap_irk_t const *const *pp_local_irks, uint8_t len)); /**@brief Set privacy settings. @@ -1839,7 +1839,7 @@ SVCALL(SD_BLE_GAP_PRIVACY_SET, uint32_t, sd_ble_gap_privacy_set(ble_gap_privacy_ * @retval ::NRF_ERROR_INVALID_ADDR The pointer given for returning the privacy settings may be NULL or invalid. * Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer. */ -SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t *p_privacy_params)); +SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t * p_privacy_params)); /**@brief Configure an advertising set. Set, clear or update advertising and scan response data. @@ -1886,7 +1886,7 @@ SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_ * existing advertising handle instead. * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied. */ -SVCALL(SD_BLE_GAP_ADV_SET_CONFIGURE, uint32_t, sd_ble_gap_adv_set_configure(uint8_t *p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params)); +SVCALL(SD_BLE_GAP_ADV_SET_CONFIGURE, uint32_t, sd_ble_gap_adv_set_configure(uint8_t * p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params)); /**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). @@ -2058,7 +2058,7 @@ SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t a * @retval ::NRF_SUCCESS Appearance value retrieved successfully. * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. */ -SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance)); +SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t * p_appearance)); /**@brief Set GAP Peripheral Preferred Connection Parameters. @@ -2083,7 +2083,7 @@ SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t * @retval ::NRF_ERROR_NOT_SUPPORTED The characteristic is not included in the Attribute Table, see @ref ble_gap_cfg_ppcp_incl_cfg_t. */ -SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params)); +SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t * p_conn_params)); /**@brief Set GAP device name. @@ -2118,7 +2118,7 @@ SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. */ -SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len)); +SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t * p_dev_name, uint16_t * p_len)); /**@brief Initiate the GAP Authentication procedure. @@ -2350,7 +2350,7 @@ SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. */ -SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own)); +SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t * p_oobd_own)); /**@brief Provide the OOB data sent/received out of band. * @@ -2449,7 +2449,7 @@ SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t c * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. */ -SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec)); +SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t * p_conn_sec)); /**@brief Start reporting the received signal strength to the application. @@ -2516,7 +2516,7 @@ SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing. */ -SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi, uint8_t *p_ch_index)); +SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t * p_rssi, uint8_t * p_ch_index)); /**@brief Start or continue scanning (GAP Discovery procedure, Observer Procedure). @@ -2569,7 +2569,7 @@ SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available. * Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again */ -SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const * p_adv_report_buffer)); +SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const *p_adv_report_buffer)); /**@brief Stop scanning (GAP Discovery procedure, Observer Procedure). @@ -2737,7 +2737,7 @@ SVCALL(SD_BLE_GAP_PHY_UPDATE, uint32_t, sd_ble_gap_phy_update(uint16_t conn_hand * @retval ::NRF_ERROR_BUSY Peer has already initiated a Data Length Update Procedure. Process the * pending @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST event to respond. */ -SVCALL(SD_BLE_GAP_DATA_LENGTH_UPDATE, uint32_t, sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t *p_dl_limitation)); +SVCALL(SD_BLE_GAP_DATA_LENGTH_UPDATE, uint32_t, sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t * p_dl_limitation)); /**@brief Start the Quality of Service (QoS) channel survey module. * @@ -2825,7 +2825,7 @@ SVCALL(SD_BLE_GAP_NEXT_CONN_EVT_COUNTER_GET, uint32_t, sd_ble_gap_next_conn_evt_ * Use @ref sd_ble_gap_next_conn_evt_counter_get to find a new value to be used as ble_gap_conn_event_trigger_t::conn_evt_counter_start. */ -SVCALL(SD_BLE_GAP_CONN_EVT_TRIGGER_START, uint32_t, sd_ble_gap_conn_evt_trigger_start(uint16_t conn_handle, ble_gap_conn_event_trigger_t const * p_params)); +SVCALL(SD_BLE_GAP_CONN_EVT_TRIGGER_START, uint32_t, sd_ble_gap_conn_evt_trigger_start(uint16_t conn_handle, ble_gap_conn_event_trigger_t const *p_params)); /**@brief Stop triggering the task configured using @ref sd_ble_gap_conn_evt_trigger_start. diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gatt.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gatt.h index c39288441..cb760720e 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gatt.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gatt.h @@ -189,7 +189,7 @@ extern "C" { */ typedef struct { - uint16_t att_mtu; /**< Maximum size of ATT packet the SoftDevice can send or receive. + uint16_t att_mtu; /**< Maximum size of ATT packet the SoftDevice can send or receive. The default and minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. @mscs @mmsc{@ref BLE_GATTC_MTU_EXCHANGE} @@ -201,22 +201,22 @@ typedef struct /**@brief GATT Characteristic Properties. */ typedef struct { - /* Standard properties */ - uint8_t broadcast :1; /**< Broadcasting of the value permitted. */ - uint8_t read :1; /**< Reading the value permitted. */ - uint8_t write_wo_resp :1; /**< Writing the value with Write Command permitted. */ - uint8_t write :1; /**< Writing the value with Write Request permitted. */ - uint8_t notify :1; /**< Notification of the value permitted. */ - uint8_t indicate :1; /**< Indications of the value permitted. */ - uint8_t auth_signed_wr :1; /**< Writing the value with Signed Write Command permitted. */ + /* Standard properties */ + uint8_t broadcast : 1;/**< Broadcasting of the value permitted. */ + uint8_t read : 1;/**< Reading the value permitted. */ + uint8_t write_wo_resp : 1;/**< Writing the value with Write Command permitted. */ + uint8_t write : 1;/**< Writing the value with Write Request permitted. */ + uint8_t notify : 1;/**< Notification of the value permitted. */ + uint8_t indicate : 1;/**< Indications of the value permitted. */ + uint8_t auth_signed_wr : 1;/**< Writing the value with Signed Write Command permitted. */ } ble_gatt_char_props_t; /**@brief GATT Characteristic Extended Properties. */ typedef struct { - /* Extended properties */ - uint8_t reliable_wr :1; /**< Writing the value with Queued Write operations permitted. */ - uint8_t wr_aux :1; /**< Writing the Characteristic User Description descriptor permitted. */ + /* Extended properties */ + uint8_t reliable_wr : 1;/**< Writing the value with Queued Write operations permitted. */ + uint8_t wr_aux : 1;/**< Writing the Characteristic User Description descriptor permitted. */ } ble_gatt_char_ext_props_t; /** @} */ diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gattc.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gattc.h index 7fb392024..c4c8322ca 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gattc.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gattc.h @@ -64,17 +64,17 @@ extern "C" { /**@brief GATTC API SVC numbers. */ enum BLE_GATTC_SVCS { - SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ - SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ - SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ - SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ - SD_BLE_GATTC_ATTR_INFO_DISCOVER, /**< Attribute Information Discovery. */ - SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ - SD_BLE_GATTC_READ, /**< Generic read. */ - SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ - SD_BLE_GATTC_WRITE, /**< Generic write. */ - SD_BLE_GATTC_HV_CONFIRM, /**< Handle Value Confirmation. */ - SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. */ + SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ + SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ + SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ + SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ + SD_BLE_GATTC_ATTR_INFO_DISCOVER, /**< Attribute Information Discovery. */ + SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ + SD_BLE_GATTC_READ, /**< Generic read. */ + SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ + SD_BLE_GATTC_WRITE, /**< Generic write. */ + SD_BLE_GATTC_HV_CONFIRM, /**< Handle Value Confirmation. */ + SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. */ }; /** @@ -82,19 +82,19 @@ enum BLE_GATTC_SVCS */ enum BLE_GATTC_EVTS { - BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t. */ - BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. \n See @ref ble_gattc_evt_rel_disc_rsp_t. */ - BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. \n See @ref ble_gattc_evt_char_disc_rsp_t. */ - BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. \n See @ref ble_gattc_evt_desc_disc_rsp_t. */ - BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, /**< Attribute Information Response event. \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */ - BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t. */ - BLE_GATTC_EVT_READ_RSP, /**< Read Response event. \n See @ref ble_gattc_evt_read_rsp_t. */ - BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. \n See @ref ble_gattc_evt_char_vals_read_rsp_t. */ - BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. \n See @ref ble_gattc_evt_write_rsp_t. */ - BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm. \n See @ref ble_gattc_evt_hvx_t. */ - BLE_GATTC_EVT_EXCHANGE_MTU_RSP, /**< Exchange MTU Response event. \n See @ref ble_gattc_evt_exchange_mtu_rsp_t. */ - BLE_GATTC_EVT_TIMEOUT, /**< Timeout event. \n See @ref ble_gattc_evt_timeout_t. */ - BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE /**< Write without Response transmission complete. \n See @ref ble_gattc_evt_write_cmd_tx_complete_t. */ + BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t. */ + BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. \n See @ref ble_gattc_evt_rel_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. \n See @ref ble_gattc_evt_char_disc_rsp_t. */ + BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. \n See @ref ble_gattc_evt_desc_disc_rsp_t. */ + BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, /**< Attribute Information Response event. \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t. */ + BLE_GATTC_EVT_READ_RSP, /**< Read Response event. \n See @ref ble_gattc_evt_read_rsp_t. */ + BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. \n See @ref ble_gattc_evt_char_vals_read_rsp_t. */ + BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. \n See @ref ble_gattc_evt_write_rsp_t. */ + BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm. \n See @ref ble_gattc_evt_hvx_t. */ + BLE_GATTC_EVT_EXCHANGE_MTU_RSP, /**< Exchange MTU Response event. \n See @ref ble_gattc_evt_exchange_mtu_rsp_t. */ + BLE_GATTC_EVT_TIMEOUT, /**< Timeout event. \n See @ref ble_gattc_evt_timeout_t. */ + BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE /**< Write without Response transmission complete. \n See @ref ble_gattc_evt_write_cmd_tx_complete_t. */ }; /** @} */ @@ -128,138 +128,138 @@ enum BLE_GATTC_EVTS */ typedef struct { - uint8_t write_cmd_tx_queue_size; /**< The guaranteed minimum number of Write without Response that can be queued for transmission. + uint8_t write_cmd_tx_queue_size; /**< The guaranteed minimum number of Write without Response that can be queued for transmission. The default value is @ref BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT */ } ble_gattc_conn_cfg_t; /**@brief Operation Handle Range. */ typedef struct { - uint16_t start_handle; /**< Start Handle. */ - uint16_t end_handle; /**< End Handle. */ + uint16_t start_handle; /**< Start Handle. */ + uint16_t end_handle; /**< End Handle. */ } ble_gattc_handle_range_t; /**@brief GATT service. */ typedef struct { - ble_uuid_t uuid; /**< Service UUID. */ - ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ + ble_uuid_t uuid; /**< Service UUID. */ + ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ } ble_gattc_service_t; /**@brief GATT include. */ typedef struct { - uint16_t handle; /**< Include Handle. */ - ble_gattc_service_t included_srvc; /**< Handle of the included service. */ + uint16_t handle; /**< Include Handle. */ + ble_gattc_service_t included_srvc; /**< Handle of the included service. */ } ble_gattc_include_t; /**@brief GATT characteristic. */ typedef struct { - ble_uuid_t uuid; /**< Characteristic UUID. */ - ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ - uint8_t char_ext_props : 1; /**< Extended properties present. */ - uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ - uint16_t handle_value; /**< Handle of the Characteristic Value. */ + ble_uuid_t uuid; /**< Characteristic UUID. */ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + uint8_t char_ext_props : 1; /**< Extended properties present. */ + uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ + uint16_t handle_value; /**< Handle of the Characteristic Value. */ } ble_gattc_char_t; /**@brief GATT descriptor. */ typedef struct { - uint16_t handle; /**< Descriptor Handle. */ - ble_uuid_t uuid; /**< Descriptor UUID. */ + uint16_t handle; /**< Descriptor Handle. */ + ble_uuid_t uuid; /**< Descriptor UUID. */ } ble_gattc_desc_t; /**@brief Write Parameters. */ typedef struct { - uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ - uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ - uint16_t handle; /**< Handle to the attribute to be written. */ - uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ - uint16_t len; /**< Length of data in bytes. */ - uint8_t const *p_value; /**< Pointer to the value data. */ + uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ + uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ + uint16_t handle; /**< Handle to the attribute to be written. */ + uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ + uint16_t len; /**< Length of data in bytes. */ + uint8_t const *p_value; /**< Pointer to the value data. */ } ble_gattc_write_params_t; /**@brief Attribute Information for 16-bit Attribute UUID. */ typedef struct { - uint16_t handle; /**< Attribute handle. */ - ble_uuid_t uuid; /**< 16-bit Attribute UUID. */ + uint16_t handle; /**< Attribute handle. */ + ble_uuid_t uuid; /**< 16-bit Attribute UUID. */ } ble_gattc_attr_info16_t; /**@brief Attribute Information for 128-bit Attribute UUID. */ typedef struct { - uint16_t handle; /**< Attribute handle. */ - ble_uuid128_t uuid; /**< 128-bit Attribute UUID. */ + uint16_t handle; /**< Attribute handle. */ + ble_uuid128_t uuid; /**< 128-bit Attribute UUID. */ } ble_gattc_attr_info128_t; /**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */ typedef struct { - uint16_t count; /**< Service count. */ - ble_gattc_service_t services[1]; /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t count; /**< Service count. */ + ble_gattc_service_t services[1]; /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_prim_srvc_disc_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */ typedef struct { - uint16_t count; /**< Include count. */ - ble_gattc_include_t includes[1]; /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t count; /**< Include count. */ + ble_gattc_include_t includes[1]; /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_rel_disc_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */ typedef struct { - uint16_t count; /**< Characteristic count. */ - ble_gattc_char_t chars[1]; /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t count; /**< Characteristic count. */ + ble_gattc_char_t chars[1]; /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_char_disc_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */ typedef struct { - uint16_t count; /**< Descriptor count. */ - ble_gattc_desc_t descs[1]; /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t count; /**< Descriptor count. */ + ble_gattc_desc_t descs[1]; /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_desc_disc_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */ typedef struct { - uint16_t count; /**< Attribute count. */ - uint8_t format; /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */ - union { - ble_gattc_attr_info16_t attr_info16[1]; /**< Attribute information for 16-bit Attribute UUID. + uint16_t count; /**< Attribute count. */ + uint8_t format; /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */ + union { + ble_gattc_attr_info16_t attr_info16[1]; /**< Attribute information for 16-bit Attribute UUID. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ - ble_gattc_attr_info128_t attr_info128[1]; /**< Attribute information for 128-bit Attribute UUID. + ble_gattc_attr_info128_t attr_info128[1]; /**< Attribute information for 128-bit Attribute UUID. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ - } info; /**< Attribute information union. */ + } info; /**< Attribute information union. */ } ble_gattc_evt_attr_info_disc_rsp_t; /**@brief GATT read by UUID handle value pair. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - uint8_t *p_value; /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */ + uint16_t handle; /**< Attribute Handle. */ + uint8_t *p_value; /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */ } ble_gattc_handle_value_t; /**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */ typedef struct { - uint16_t count; /**< Handle-Value Pair Count. */ - uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ - uint8_t handle_value[1]; /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter. + uint16_t count; /**< Handle-Value Pair Count. */ + uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ + uint8_t handle_value[1]; /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_char_val_by_uuid_read_rsp_t; @@ -267,82 +267,82 @@ typedef struct /**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - uint16_t offset; /**< Offset of the attribute data. */ - uint16_t len; /**< Attribute data length. */ - uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t handle; /**< Attribute Handle. */ + uint16_t offset; /**< Offset of the attribute data. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_read_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */ typedef struct { - uint16_t len; /**< Concatenated Attribute values length. */ - uint8_t values[1]; /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t len; /**< Concatenated Attribute values length. */ + uint8_t values[1]; /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_char_vals_read_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ - uint16_t offset; /**< Data offset. */ - uint16_t len; /**< Data length. */ - uint8_t data[1]; /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t handle; /**< Attribute Handle. */ + uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ + uint16_t offset; /**< Data offset. */ + uint16_t len; /**< Data length. */ + uint8_t data[1]; /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_write_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */ typedef struct { - uint16_t handle; /**< Handle to which the HVx operation applies. */ - uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ - uint16_t len; /**< Attribute data length. */ - uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t handle; /**< Handle to which the HVx operation applies. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gattc_evt_hvx_t; /**@brief Event structure for @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. */ typedef struct { - uint16_t server_rx_mtu; /**< Server RX MTU size. */ + uint16_t server_rx_mtu; /**< Server RX MTU size. */ } ble_gattc_evt_exchange_mtu_rsp_t; /**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */ typedef struct { - uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ } ble_gattc_evt_timeout_t; /**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE. */ typedef struct { - uint8_t count; /**< Number of write without response transmissions completed. */ + uint8_t count; /**< Number of write without response transmissions completed. */ } ble_gattc_evt_write_cmd_tx_complete_t; /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ - uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ - union - { - ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ - ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ - ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ - ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ - ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ - ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ - ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ - ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ - ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ - ble_gattc_evt_exchange_mtu_rsp_t exchange_mtu_rsp; /**< Exchange MTU Response Event Parameters. */ - ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ - ble_gattc_evt_attr_info_disc_rsp_t attr_info_disc_rsp; /**< Attribute Information Discovery Event Parameters. */ - ble_gattc_evt_write_cmd_tx_complete_t write_cmd_tx_complete; /**< Write without Response transmission complete Event Parameters. */ - } params; /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ + union + { + ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ + ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ + ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ + ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ + ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ + ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ + ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ + ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ + ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ + ble_gattc_evt_exchange_mtu_rsp_t exchange_mtu_rsp; /**< Exchange MTU Response Event Parameters. */ + ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gattc_evt_attr_info_disc_rsp_t attr_info_disc_rsp; /**< Attribute Information Discovery Event Parameters. */ + ble_gattc_evt_write_cmd_tx_complete_t write_cmd_tx_complete; /**< Write without Response transmission complete Event Parameters. */ + } params; /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */ } ble_gattc_evt_t; /** @} */ @@ -621,7 +621,7 @@ SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_ * @retval ::NRF_ERROR_BUSY Client procedure already in progress. * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. */ -SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range)); +SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); /**@brief Start an ATT_MTU exchange by sending an Exchange MTU Request to the server. * @@ -685,22 +685,18 @@ __STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gat #ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter) -{ - uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len; - uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value; - uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first; - - if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count) - { - p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0]; - p_iter->p_value = p_next + sizeof(uint16_t); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_NOT_FOUND; - } +__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter) { + uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len; + uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value; + uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first; + + if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count) { + p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0]; + p_iter->p_value = p_next + sizeof(uint16_t); + return NRF_SUCCESS; + } else { + return NRF_ERROR_NOT_FOUND; + } } #endif /* SUPPRESS_INLINE_IMPLEMENTATION */ diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gatts.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gatts.h index 394d8d189..1a7a51ac1 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gatts.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_gatts.h @@ -67,20 +67,20 @@ extern "C" { */ enum BLE_GATTS_SVCS { - SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ - SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ - SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ - SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ - SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ - SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ - SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ - SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ - SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ - SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ - SD_BLE_GATTS_SYS_ATTR_GET, /**< Retrieve the persistent system attributes. */ - SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, /**< Retrieve the first valid user handle. */ - SD_BLE_GATTS_ATTR_GET, /**< Retrieve the UUID and/or metadata of an attribute. */ - SD_BLE_GATTS_EXCHANGE_MTU_REPLY /**< Reply to Exchange MTU Request. */ + SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ + SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ + SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ + SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ + SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ + SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ + SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ + SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ + SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ + SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ + SD_BLE_GATTS_SYS_ATTR_GET, /**< Retrieve the persistent system attributes. */ + SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, /**< Retrieve the first valid user handle. */ + SD_BLE_GATTS_ATTR_GET, /**< Retrieve the UUID and/or metadata of an attribute. */ + SD_BLE_GATTS_EXCHANGE_MTU_REPLY /**< Reply to Exchange MTU Request. */ }; /** @@ -88,14 +88,14 @@ enum BLE_GATTS_SVCS */ enum BLE_GATTS_EVTS { - BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. \n See @ref ble_gatts_evt_write_t. */ - BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */ - BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending. \n Respond with @ref sd_ble_gatts_sys_attr_set. \n See @ref ble_gatts_evt_sys_attr_missing_t. */ - BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. \n See @ref ble_gatts_evt_hvc_t. */ - BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. \n No additional event structure applies. */ - BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */ - BLE_GATTS_EVT_TIMEOUT, /**< Peer failed to respond to an ATT request in time. \n See @ref ble_gatts_evt_timeout_t. */ - BLE_GATTS_EVT_HVN_TX_COMPLETE /**< Handle Value Notification transmission complete. \n See @ref ble_gatts_evt_hvn_tx_complete_t. */ + BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. \n See @ref ble_gatts_evt_write_t. */ + BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */ + BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending. \n Respond with @ref sd_ble_gatts_sys_attr_set. \n See @ref ble_gatts_evt_sys_attr_missing_t. */ + BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. \n See @ref ble_gatts_evt_hvc_t. */ + BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. \n No additional event structure applies. */ + BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */ + BLE_GATTS_EVT_TIMEOUT, /**< Peer failed to respond to an ATT request in time. \n See @ref ble_gatts_evt_timeout_t. */ + BLE_GATTS_EVT_HVN_TX_COMPLETE /**< Handle Value Notification transmission complete. \n See @ref ble_gatts_evt_hvn_tx_complete_t. */ }; /**@brief GATTS Configuration IDs. @@ -104,8 +104,8 @@ enum BLE_GATTS_EVTS */ enum BLE_GATTS_CFGS { - BLE_GATTS_CFG_SERVICE_CHANGED = BLE_GATTS_CFG_BASE, /**< Service changed configuration. */ - BLE_GATTS_CFG_ATTR_TAB_SIZE, /**< Attribute table size configuration. */ + BLE_GATTS_CFG_SERVICE_CHANGED = BLE_GATTS_CFG_BASE, /**< Service changed configuration. */ + BLE_GATTS_CFG_ATTR_TAB_SIZE, /**< Attribute table size configuration. */ }; /** @} */ @@ -207,31 +207,31 @@ enum BLE_GATTS_CFGS */ typedef struct { - uint8_t hvn_tx_queue_size; /**< Minimum guaranteed number of Handle Value Notifications that can be queued for transmission. + uint8_t hvn_tx_queue_size; /**< Minimum guaranteed number of Handle Value Notifications that can be queued for transmission. The default value is @ref BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT */ } ble_gatts_conn_cfg_t; /**@brief Attribute metadata. */ typedef struct { - ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ - ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ - uint8_t vlen :1; /**< Variable length attribute. */ - uint8_t vloc :2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ - uint8_t rd_auth :1; /**< Read authorization and value will be requested from the application on every read operation. */ - uint8_t wr_auth :1; /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */ + ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vlen : 1; /**< Variable length attribute. */ + uint8_t vloc : 2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t rd_auth : 1; /**< Read authorization and value will be requested from the application on every read operation. */ + uint8_t wr_auth : 1; /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */ } ble_gatts_attr_md_t; /**@brief GATT Attribute. */ typedef struct { - ble_uuid_t const *p_uuid; /**< Pointer to the attribute UUID. */ - ble_gatts_attr_md_t const *p_attr_md; /**< Pointer to the attribute metadata structure. */ - uint16_t init_len; /**< Initial attribute value length in bytes. */ - uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ - uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ - uint8_t *p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer + ble_uuid_t const *p_uuid; /**< Pointer to the attribute UUID. */ + ble_gatts_attr_md_t const *p_attr_md; /**< Pointer to the attribute metadata structure. */ + uint16_t init_len; /**< Initial attribute value length in bytes. */ + uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ + uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ + uint8_t *p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location. The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/ } ble_gatts_attr_t; @@ -239,9 +239,9 @@ typedef struct /**@brief GATT Attribute Value. */ typedef struct { - uint16_t len; /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/ - uint16_t offset; /**< Attribute value offset. */ - uint8_t *p_value; /**< Pointer to where value is stored or will be stored. + uint16_t len; /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/ + uint16_t offset; /**< Attribute value offset. */ + uint8_t *p_value; /**< Pointer to where value is stored or will be stored. If value is stored in user memory, only the attribute length is updated when p_value == NULL. Set to NULL when reading to obtain the complete length of the attribute value */ } ble_gatts_value_t; @@ -250,75 +250,75 @@ typedef struct /**@brief GATT Characteristic Presentation Format. */ typedef struct { - uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ - int8_t exponent; /**< Exponent for integer data types. */ - uint16_t unit; /**< Unit from Bluetooth Assigned Numbers. */ - uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ - uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ + uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ + int8_t exponent; /**< Exponent for integer data types. */ + uint16_t unit; /**< Unit from Bluetooth Assigned Numbers. */ + uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ + uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ } ble_gatts_char_pf_t; /**@brief GATT Characteristic metadata. */ typedef struct { - ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ - ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ - uint8_t const *p_char_user_desc; /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */ - uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ - uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ - ble_gatts_char_pf_t const *p_char_pf; /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */ - ble_gatts_attr_md_t const *p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ - ble_gatts_attr_md_t const *p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ - ble_gatts_attr_md_t const *p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ + uint8_t const *p_char_user_desc; /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */ + uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ + uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ + ble_gatts_char_pf_t const *p_char_pf; /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */ + ble_gatts_attr_md_t const *p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ } ble_gatts_char_md_t; /**@brief GATT Characteristic Definition Handles. */ typedef struct { - uint16_t value_handle; /**< Handle to the characteristic value. */ - uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ - uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ - uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t value_handle; /**< Handle to the characteristic value. */ + uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ } ble_gatts_char_handles_t; /**@brief GATT HVx parameters. */ typedef struct { - uint16_t handle; /**< Characteristic Value Handle. */ - uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ - uint16_t offset; /**< Offset within the attribute value. */ - uint16_t *p_len; /**< Length in bytes to be written, length in bytes written after return. */ - uint8_t const *p_data; /**< Actual data content, use NULL to use the current attribute value. */ + uint16_t handle; /**< Characteristic Value Handle. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t offset; /**< Offset within the attribute value. */ + uint16_t *p_len; /**< Length in bytes to be written, length in bytes written after return. */ + uint8_t const *p_data; /**< Actual data content, use NULL to use the current attribute value. */ } ble_gatts_hvx_params_t; /**@brief GATT Authorization parameters. */ typedef struct { - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ - uint8_t update : 1; /**< If set, data supplied in p_data will be used to update the attribute value. + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint8_t update : 1; /**< If set, data supplied in p_data will be used to update the attribute value. Please note that for @ref BLE_GATTS_AUTHORIZE_TYPE_WRITE operations this bit must always be set, as the data to be written needs to be stored and later provided by the application. */ - uint16_t offset; /**< Offset of the attribute value being updated. */ - uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ - uint8_t const *p_data; /**< Pointer to new value used to update the attribute value. */ + uint16_t offset; /**< Offset of the attribute value being updated. */ + uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ + uint8_t const *p_data; /**< Pointer to new value used to update the attribute value. */ } ble_gatts_authorize_params_t; /**@brief GATT Read or Write Authorize Reply parameters. */ typedef struct { - uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ - union { - ble_gatts_authorize_params_t read; /**< Read authorization parameters. */ - ble_gatts_authorize_params_t write; /**< Write authorization parameters. */ - } params; /**< Reply Parameters. */ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_authorize_params_t read; /**< Read authorization parameters. */ + ble_gatts_authorize_params_t write; /**< Write authorization parameters. */ + } params; /**< Reply Parameters. */ } ble_gatts_rw_authorize_reply_params_t; /**@brief Service Changed Inclusion configuration parameters, set with @ref sd_ble_cfg_set. */ typedef struct { - uint8_t service_changed : 1; /**< If 1, include the Service Changed characteristic in the Attribute Table. Default is @ref BLE_GATTS_SERVICE_CHANGED_DEFAULT. */ + uint8_t service_changed : 1; /**< If 1, include the Service Changed characteristic in the Attribute Table. Default is @ref BLE_GATTS_SERVICE_CHANGED_DEFAULT. */ } ble_gatts_cfg_service_changed_t; /**@brief Attribute table size configuration parameters, set with @ref sd_ble_cfg_set. @@ -330,93 +330,93 @@ typedef struct */ typedef struct { - uint32_t attr_tab_size; /**< Attribute table size. Default is @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT, minimum is @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. */ + uint32_t attr_tab_size; /**< Attribute table size. Default is @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT, minimum is @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. */ } ble_gatts_cfg_attr_tab_size_t; /**@brief Config structure for GATTS configurations. */ typedef union { - ble_gatts_cfg_service_changed_t service_changed; /**< Include service changed characteristic, cfg_id is @ref BLE_GATTS_CFG_SERVICE_CHANGED. */ - ble_gatts_cfg_attr_tab_size_t attr_tab_size; /**< Attribute table size, cfg_id is @ref BLE_GATTS_CFG_ATTR_TAB_SIZE. */ + ble_gatts_cfg_service_changed_t service_changed; /**< Include service changed characteristic, cfg_id is @ref BLE_GATTS_CFG_SERVICE_CHANGED. */ + ble_gatts_cfg_attr_tab_size_t attr_tab_size; /**< Attribute table size, cfg_id is @ref BLE_GATTS_CFG_ATTR_TAB_SIZE. */ } ble_gatts_cfg_t; /**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - ble_uuid_t uuid; /**< Attribute UUID. */ - uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ - uint8_t auth_required; /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalize the writing operation. */ - uint16_t offset; /**< Offset for the write operation. */ - uint16_t len; /**< Length of the received data. */ - uint8_t data[1]; /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ + uint8_t auth_required; /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalize the writing operation. */ + uint16_t offset; /**< Offset for the write operation. */ + uint16_t len; /**< Length of the received data. */ + uint8_t data[1]; /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ } ble_gatts_evt_write_t; /**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ - ble_uuid_t uuid; /**< Attribute UUID. */ - uint16_t offset; /**< Offset for the read operation. */ + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint16_t offset; /**< Offset for the read operation. */ } ble_gatts_evt_read_t; /**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */ typedef struct { - uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ - union { - ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ - ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ - } request; /**< Request Parameters. */ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ + ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ + } request; /**< Request Parameters. */ } ble_gatts_evt_rw_authorize_request_t; /**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */ typedef struct { - uint8_t hint; /**< Hint (currently unused). */ + uint8_t hint; /**< Hint (currently unused). */ } ble_gatts_evt_sys_attr_missing_t; /**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */ typedef struct { - uint16_t handle; /**< Attribute Handle. */ + uint16_t handle; /**< Attribute Handle. */ } ble_gatts_evt_hvc_t; /**@brief Event structure for @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST. */ typedef struct { - uint16_t client_rx_mtu; /**< Client RX MTU size. */ + uint16_t client_rx_mtu; /**< Client RX MTU size. */ } ble_gatts_evt_exchange_mtu_request_t; /**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */ typedef struct { - uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ } ble_gatts_evt_timeout_t; /**@brief Event structure for @ref BLE_GATTS_EVT_HVN_TX_COMPLETE. */ typedef struct { - uint8_t count; /**< Number of notification transmissions completed. */ + uint8_t count; /**< Number of notification transmissions completed. */ } ble_gatts_evt_hvn_tx_complete_t; /**@brief GATTS event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which the event occurred. */ - union - { - ble_gatts_evt_write_t write; /**< Write Event Parameters. */ - ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ - ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ - ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ - ble_gatts_evt_exchange_mtu_request_t exchange_mtu_request; /**< Exchange MTU Request Event Parameters. */ - ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ - ble_gatts_evt_hvn_tx_complete_t hvn_tx_complete; /**< Handle Value Notification transmission complete Event Parameters. */ - } params; /**< Event Parameters. */ + uint16_t conn_handle; /**< Connection Handle on which the event occurred. */ + union + { + ble_gatts_evt_write_t write; /**< Write Event Parameters. */ + ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ + ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ + ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ + ble_gatts_evt_exchange_mtu_request_t exchange_mtu_request; /**< Exchange MTU Request Event Parameters. */ + ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ + ble_gatts_evt_hvn_tx_complete_t hvn_tx_complete; /**< Handle Value Notification transmission complete Event Parameters. */ + } params; /**< Event Parameters. */ } ble_gatts_evt_t; /** @} */ @@ -443,7 +443,7 @@ typedef struct * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. */ -SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle)); +SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t * p_handle)); /**@brief Add an include declaration to the Attribute Table. @@ -469,7 +469,7 @@ SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. */ -SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle)); +SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t * p_include_handle)); /**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table. @@ -498,7 +498,7 @@ SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t ser * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. */ -SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles)); +SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t * p_handles)); /**@brief Add a descriptor to the Attribute Table. @@ -521,7 +521,7 @@ SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_ad * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. */ -SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle)); +SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t * p_handle)); /**@brief Set the value of a given attribute. * @@ -544,7 +544,7 @@ SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16 * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. */ -SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); +SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t * p_value)); /**@brief Get the value of a given attribute. * @@ -568,7 +568,7 @@ SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_ha * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. */ -SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); +SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t * p_value)); /**@brief Notify or Indicate an attribute value. * @@ -779,7 +779,7 @@ SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t c * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer. * @retval ::NRF_ERROR_NOT_FOUND No system attributes found. */ -SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags)); +SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t * p_sys_attr_data, uint16_t * p_len, uint32_t flags)); /**@brief Retrieve the first valid user attribute handle. @@ -789,7 +789,7 @@ SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t c * @retval ::NRF_SUCCESS Successfully retrieved the handle. * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. */ -SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle)); +SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t * p_handle)); /**@brief Retrieve the attribute UUID and/or metadata. * diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_l2cap.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_l2cap.h index 7587350cf..933f398b5 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_l2cap.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_l2cap.h @@ -84,32 +84,32 @@ extern "C" { /**@brief L2CAP API SVC numbers. */ enum BLE_L2CAP_SVCS { - SD_BLE_L2CAP_CH_SETUP = BLE_L2CAP_SVC_BASE + 0, /**< Set up an L2CAP channel. */ - SD_BLE_L2CAP_CH_RELEASE = BLE_L2CAP_SVC_BASE + 1, /**< Release an L2CAP channel. */ - SD_BLE_L2CAP_CH_RX = BLE_L2CAP_SVC_BASE + 2, /**< Receive an SDU on an L2CAP channel. */ - SD_BLE_L2CAP_CH_TX = BLE_L2CAP_SVC_BASE + 3, /**< Transmit an SDU on an L2CAP channel. */ - SD_BLE_L2CAP_CH_FLOW_CONTROL = BLE_L2CAP_SVC_BASE + 4, /**< Advanced SDU reception flow control. */ + SD_BLE_L2CAP_CH_SETUP = BLE_L2CAP_SVC_BASE + 0,/**< Set up an L2CAP channel. */ + SD_BLE_L2CAP_CH_RELEASE = BLE_L2CAP_SVC_BASE + 1,/**< Release an L2CAP channel. */ + SD_BLE_L2CAP_CH_RX = BLE_L2CAP_SVC_BASE + 2,/**< Receive an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_TX = BLE_L2CAP_SVC_BASE + 3,/**< Transmit an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_FLOW_CONTROL = BLE_L2CAP_SVC_BASE + 4, /**< Advanced SDU reception flow control. */ }; /**@brief L2CAP Event IDs. */ enum BLE_L2CAP_EVTS { - BLE_L2CAP_EVT_CH_SETUP_REQUEST = BLE_L2CAP_EVT_BASE + 0, /**< L2CAP Channel Setup Request event. + BLE_L2CAP_EVT_CH_SETUP_REQUEST = BLE_L2CAP_EVT_BASE + 0, /**< L2CAP Channel Setup Request event. \n Reply with @ref sd_ble_l2cap_ch_setup. \n See @ref ble_l2cap_evt_ch_setup_request_t. */ - BLE_L2CAP_EVT_CH_SETUP_REFUSED = BLE_L2CAP_EVT_BASE + 1, /**< L2CAP Channel Setup Refused event. + BLE_L2CAP_EVT_CH_SETUP_REFUSED = BLE_L2CAP_EVT_BASE + 1, /**< L2CAP Channel Setup Refused event. \n See @ref ble_l2cap_evt_ch_setup_refused_t. */ - BLE_L2CAP_EVT_CH_SETUP = BLE_L2CAP_EVT_BASE + 2, /**< L2CAP Channel Setup Completed event. + BLE_L2CAP_EVT_CH_SETUP = BLE_L2CAP_EVT_BASE + 2, /**< L2CAP Channel Setup Completed event. \n See @ref ble_l2cap_evt_ch_setup_t. */ - BLE_L2CAP_EVT_CH_RELEASED = BLE_L2CAP_EVT_BASE + 3, /**< L2CAP Channel Released event. + BLE_L2CAP_EVT_CH_RELEASED = BLE_L2CAP_EVT_BASE + 3, /**< L2CAP Channel Released event. \n No additional event structure applies. */ - BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED = BLE_L2CAP_EVT_BASE + 4, /**< L2CAP Channel SDU data buffer released event. + BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED = BLE_L2CAP_EVT_BASE + 4, /**< L2CAP Channel SDU data buffer released event. \n See @ref ble_l2cap_evt_ch_sdu_buf_released_t. */ - BLE_L2CAP_EVT_CH_CREDIT = BLE_L2CAP_EVT_BASE + 5, /**< L2CAP Channel Credit received. + BLE_L2CAP_EVT_CH_CREDIT = BLE_L2CAP_EVT_BASE + 5, /**< L2CAP Channel Credit received. \n See @ref ble_l2cap_evt_ch_credit_t. */ - BLE_L2CAP_EVT_CH_RX = BLE_L2CAP_EVT_BASE + 6, /**< L2CAP Channel SDU received. + BLE_L2CAP_EVT_CH_RX = BLE_L2CAP_EVT_BASE + 6, /**< L2CAP Channel SDU received. \n See @ref ble_l2cap_evt_ch_rx_t. */ - BLE_L2CAP_EVT_CH_TX = BLE_L2CAP_EVT_BASE + 7, /**< L2CAP Channel SDU transmitted. + BLE_L2CAP_EVT_CH_TX = BLE_L2CAP_EVT_BASE + 7, /**< L2CAP Channel SDU transmitted. \n See @ref ble_l2cap_evt_ch_tx_t. */ }; @@ -137,9 +137,9 @@ enum BLE_L2CAP_EVTS * @{ */ #define BLE_L2CAP_CH_SETUP_REFUSED_SRC_LOCAL (0x01) /**< Local. */ #define BLE_L2CAP_CH_SETUP_REFUSED_SRC_REMOTE (0x02) /**< Remote. */ - /** @} */ +/** @} */ - /** @defgroup BLE_L2CAP_CH_STATUS_CODES L2CAP channel status codes +/** @defgroup BLE_L2CAP_CH_STATUS_CODES L2CAP channel status codes * @{ */ #define BLE_L2CAP_CH_STATUS_CODE_SUCCESS (0x0000) /**< Success. */ #define BLE_L2CAP_CH_STATUS_CODE_LE_PSM_NOT_SUPPORTED (0x0002) /**< LE_PSM not supported. */ @@ -174,17 +174,17 @@ enum BLE_L2CAP_EVTS */ typedef struct { - uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be able to receive on L2CAP channels on connections with this configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ - uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be able to transmit on L2CAP channels on connections with this configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ - uint8_t rx_queue_size; /**< Number of SDU data buffers that can be queued for reception per + uint8_t rx_queue_size; /**< Number of SDU data buffers that can be queued for reception per L2CAP channel. The minimum value is one. */ - uint8_t tx_queue_size; /**< Number of SDU data buffers that can be queued for transmission + uint8_t tx_queue_size; /**< Number of SDU data buffers that can be queued for transmission per L2CAP channel. The minimum value is one. */ - uint8_t ch_count; /**< Number of L2CAP channels the application can create per connection + uint8_t ch_count; /**< Number of L2CAP channels the application can create per connection with this configuration. The default value is zero, the maximum value is @ref BLE_L2CAP_CH_COUNT_MAX. @note if this parameter is set to zero, all other parameters in @@ -194,14 +194,14 @@ typedef struct /**@brief L2CAP channel RX parameters. */ typedef struct { - uint16_t rx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP shall be able to + uint16_t rx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP shall be able to receive on this L2CAP channel. - Must be equal to or greater than @ref BLE_L2CAP_MTU_MIN. */ - uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be able to receive on this L2CAP channel. - Must be equal to or greater than @ref BLE_L2CAP_MPS_MIN. - Must be equal to or less than @ref ble_l2cap_conn_cfg_t::rx_mps. */ - ble_data_t sdu_buf; /**< SDU data buffer for reception. + ble_data_t sdu_buf; /**< SDU data buffer for reception. - If @ref ble_data_t::p_data is non-NULL, initial credits are issued to the peer. - If @ref ble_data_t::p_data is NULL, no initial credits are @@ -211,10 +211,10 @@ typedef struct /**@brief L2CAP channel setup parameters. */ typedef struct { - ble_l2cap_ch_rx_params_t rx_params; /**< L2CAP channel RX parameters. */ - uint16_t le_psm; /**< LE Protocol/Service Multiplexer. Used when requesting + ble_l2cap_ch_rx_params_t rx_params; /**< L2CAP channel RX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. Used when requesting setup of an L2CAP channel, ignored otherwise. */ - uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES. + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES. Used when replying to a setup request of an L2CAP channel, ignored otherwise. */ } ble_l2cap_ch_setup_params_t; @@ -222,41 +222,41 @@ typedef struct /**@brief L2CAP channel TX parameters. */ typedef struct { - uint16_t tx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP is able to + uint16_t tx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP is able to transmit on this L2CAP channel. */ - uint16_t peer_mps; /**< The maximum L2CAP PDU payload size, in bytes, that the peer is + uint16_t peer_mps; /**< The maximum L2CAP PDU payload size, in bytes, that the peer is able to receive on this L2CAP channel. */ - uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP is able + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP is able to transmit on this L2CAP channel. This is effective tx_mps, selected by the SoftDevice as MIN( @ref ble_l2cap_ch_tx_params_t::peer_mps, @ref ble_l2cap_conn_cfg_t::tx_mps ) */ - uint16_t credits; /**< Initial credits given by the peer. */ + uint16_t credits; /**< Initial credits given by the peer. */ } ble_l2cap_ch_tx_params_t; /**@brief L2CAP Channel Setup Request event. */ typedef struct { - ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ - uint16_t le_psm; /**< LE Protocol/Service Multiplexer. */ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. */ } ble_l2cap_evt_ch_setup_request_t; /**@brief L2CAP Channel Setup Refused event. */ typedef struct { - uint8_t source; /**< Source, see @ref BLE_L2CAP_CH_SETUP_REFUSED_SRCS */ - uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES */ + uint8_t source; /**< Source, see @ref BLE_L2CAP_CH_SETUP_REFUSED_SRCS */ + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES */ } ble_l2cap_evt_ch_setup_refused_t; /**@brief L2CAP Channel Setup Completed event. */ typedef struct { - ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ } ble_l2cap_evt_ch_setup_t; /**@brief L2CAP Channel SDU Data Buffer Released event. */ typedef struct { - ble_data_t sdu_buf; /**< Returned reception or transmission SDU data buffer. The SoftDevice + ble_data_t sdu_buf; /**< Returned reception or transmission SDU data buffer. The SoftDevice returns SDU data buffers supplied by the application, which have not yet been returned previously via a @ref BLE_L2CAP_EVT_CH_RX or @ref BLE_L2CAP_EVT_CH_TX event. */ @@ -265,14 +265,14 @@ typedef struct /**@brief L2CAP Channel Credit received event. */ typedef struct { - uint16_t credits; /**< Additional credits given by the peer. */ + uint16_t credits; /**< Additional credits given by the peer. */ } ble_l2cap_evt_ch_credit_t; /**@brief L2CAP Channel received SDU event. */ typedef struct { - uint16_t sdu_len; /**< Total SDU length, in bytes. */ - ble_data_t sdu_buf; /**< SDU data buffer. + uint16_t sdu_len; /**< Total SDU length, in bytes. */ + ble_data_t sdu_buf; /**< SDU data buffer. @note If there is not enough space in the buffer (sdu_buf.len < sdu_len) then the rest of the SDU will be silently discarded by the SoftDevice. */ @@ -281,25 +281,25 @@ typedef struct /**@brief L2CAP Channel transmitted SDU event. */ typedef struct { - ble_data_t sdu_buf; /**< SDU data buffer. */ + ble_data_t sdu_buf; /**< SDU data buffer. */ } ble_l2cap_evt_ch_tx_t; /**@brief L2CAP event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which the event occured. */ - uint16_t local_cid; /**< Local Channel ID of the L2CAP channel, or + uint16_t conn_handle; /**< Connection Handle on which the event occured. */ + uint16_t local_cid; /**< Local Channel ID of the L2CAP channel, or @ref BLE_L2CAP_CID_INVALID if not present. */ - union - { - ble_l2cap_evt_ch_setup_request_t ch_setup_request; /**< L2CAP Channel Setup Request Event Parameters. */ - ble_l2cap_evt_ch_setup_refused_t ch_setup_refused; /**< L2CAP Channel Setup Refused Event Parameters. */ - ble_l2cap_evt_ch_setup_t ch_setup; /**< L2CAP Channel Setup Completed Event Parameters. */ - ble_l2cap_evt_ch_sdu_buf_released_t ch_sdu_buf_released;/**< L2CAP Channel SDU Data Buffer Released Event Parameters. */ - ble_l2cap_evt_ch_credit_t credit; /**< L2CAP Channel Credit Received Event Parameters. */ - ble_l2cap_evt_ch_rx_t rx; /**< L2CAP Channel SDU Received Event Parameters. */ - ble_l2cap_evt_ch_tx_t tx; /**< L2CAP Channel SDU Transmitted Event Parameters. */ - } params; /**< Event Parameters. */ + union + { + ble_l2cap_evt_ch_setup_request_t ch_setup_request; /**< L2CAP Channel Setup Request Event Parameters. */ + ble_l2cap_evt_ch_setup_refused_t ch_setup_refused; /**< L2CAP Channel Setup Refused Event Parameters. */ + ble_l2cap_evt_ch_setup_t ch_setup; /**< L2CAP Channel Setup Completed Event Parameters. */ + ble_l2cap_evt_ch_sdu_buf_released_t ch_sdu_buf_released;/**< L2CAP Channel SDU Data Buffer Released Event Parameters. */ + ble_l2cap_evt_ch_credit_t credit; /**< L2CAP Channel Credit Received Event Parameters. */ + ble_l2cap_evt_ch_rx_t rx; /**< L2CAP Channel SDU Received Event Parameters. */ + ble_l2cap_evt_ch_tx_t tx; /**< L2CAP Channel SDU Transmitted Event Parameters. */ + } params; /**< Event Parameters. */ } ble_l2cap_evt_t; /** @} */ @@ -347,7 +347,7 @@ typedef struct * @retval ::NRF_ERROR_RESOURCES The limit has been reached for available L2CAP channels, * see @ref ble_l2cap_conn_cfg_t::ch_count. */ -SVCALL(SD_BLE_L2CAP_CH_SETUP, uint32_t, sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t *p_local_cid, ble_l2cap_ch_setup_params_t const *p_params)); +SVCALL(SD_BLE_L2CAP_CH_SETUP, uint32_t, sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t * p_local_cid, ble_l2cap_ch_setup_params_t const *p_params)); /**@brief Release an L2CAP channel. * @@ -493,7 +493,7 @@ SVCALL(SD_BLE_L2CAP_CH_TX, uint32_t, sd_ble_l2cap_ch_tx(uint16_t conn_handle, ui * in progress for an L2CAP channel). * @retval ::NRF_ERROR_NOT_FOUND CID not found. */ -SVCALL(SD_BLE_L2CAP_CH_FLOW_CONTROL, uint32_t, sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t *p_credits)); +SVCALL(SD_BLE_L2CAP_CH_FLOW_CONTROL, uint32_t, sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t * p_credits)); /** @} */ diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_types.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_types.h index 88c93180c..350495913 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_types.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/ble_types.h @@ -155,27 +155,27 @@ extern "C" { /** @} */ /** @brief Set .type and .uuid fields of ble_uuid_struct to specified UUID value. */ -#define BLE_UUID_BLE_ASSIGN(instance, value) do {\ - instance.type = BLE_UUID_TYPE_BLE; \ - instance.uuid = value;} while(0) +#define BLE_UUID_BLE_ASSIGN(instance, value) do { \ + instance.type = BLE_UUID_TYPE_BLE; \ + instance.uuid = value;} while (0) /** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */ -#define BLE_UUID_COPY_PTR(dst, src) do {\ - (dst)->type = (src)->type; \ - (dst)->uuid = (src)->uuid;} while(0) +#define BLE_UUID_COPY_PTR(dst, src) do { \ + (dst)->type = (src)->type; \ + (dst)->uuid = (src)->uuid;} while (0) /** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */ -#define BLE_UUID_COPY_INST(dst, src) do {\ - (dst).type = (src).type; \ - (dst).uuid = (src).uuid;} while(0) +#define BLE_UUID_COPY_INST(dst, src) do { \ + (dst).type = (src).type; \ + (dst).uuid = (src).uuid;} while (0) /** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ #define BLE_UUID_EQ(p_uuid1, p_uuid2) \ - (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) + (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) /** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ #define BLE_UUID_NEQ(p_uuid1, p_uuid2) \ - (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) + (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) /** @} */ @@ -185,21 +185,21 @@ extern "C" { /** @brief 128 bit UUID values. */ typedef struct { - uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */ + uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */ } ble_uuid128_t; /** @brief Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */ typedef struct { - uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ - uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ + uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ + uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ } ble_uuid_t; /**@brief Data structure. */ typedef struct { - uint8_t *p_data; /**< Pointer to the data buffer provided to/from the application. */ - uint16_t len; /**< Length of the data buffer, in bytes. */ + uint8_t *p_data; /**< Pointer to the data buffer provided to/from the application. */ + uint16_t len; /**< Length of the data buffer, in bytes. */ } ble_data_t; /** @} */ diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf52/nrf_mbr.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf52/nrf_mbr.h index 42e09fc87..34132e210 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf52/nrf_mbr.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf52/nrf_mbr.h @@ -88,19 +88,19 @@ This is the offset where the first byte of the SoftDevice hex file is written. * /**@brief nRF Master Boot Record API SVC numbers. */ enum NRF_MBR_SVCS { - SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */ + SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */ }; /**@brief Possible values for ::sd_mbr_command_t.command */ enum NRF_MBR_COMMANDS { - SD_MBR_COMMAND_COPY_BL, /**< Copy a new BootLoader. @see ::sd_mbr_command_copy_bl_t*/ - SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/ - SD_MBR_COMMAND_INIT_SD, /**< Initialize forwarding interrupts to SD, and run reset function in SD. Does not require any parameters in ::sd_mbr_command_t params.*/ - SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/ - SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Change the address the MBR starts after a reset. @see ::sd_mbr_command_vector_table_base_set_t*/ - SD_MBR_COMMAND_RESERVED, - SD_MBR_COMMAND_IRQ_FORWARD_ADDRESS_SET, /**< Start forwarding all interrupts to this address. @see ::sd_mbr_command_irq_forward_address_set_t*/ + SD_MBR_COMMAND_COPY_BL, /**< Copy a new BootLoader. @see ::sd_mbr_command_copy_bl_t*/ + SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/ + SD_MBR_COMMAND_INIT_SD, /**< Initialize forwarding interrupts to SD, and run reset function in SD. Does not require any parameters in ::sd_mbr_command_t params.*/ + SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/ + SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Change the address the MBR starts after a reset. @see ::sd_mbr_command_vector_table_base_set_t*/ + SD_MBR_COMMAND_RESERVED, + SD_MBR_COMMAND_IRQ_FORWARD_ADDRESS_SET, /**< Start forwarding all interrupts to this address. @see ::sd_mbr_command_irq_forward_address_set_t*/ }; /** @} */ @@ -121,9 +121,9 @@ enum NRF_MBR_COMMANDS */ typedef struct { - uint32_t *src; /**< Pointer to the source of data to be copied.*/ - uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/ - uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/ + uint32_t *src; /**< Pointer to the source of data to be copied.*/ + uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/ + uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/ } sd_mbr_command_copy_sd_t; @@ -134,9 +134,9 @@ typedef struct */ typedef struct { - uint32_t *ptr1; /**< Pointer to block of memory. */ - uint32_t *ptr2; /**< Pointer to block of memory. */ - uint32_t len; /**< Number of 32 bit words to compare.*/ + uint32_t *ptr1; /**< Pointer to block of memory. */ + uint32_t *ptr2; /**< Pointer to block of memory. */ + uint32_t len; /**< Number of 32 bit words to compare.*/ } sd_mbr_command_compare_t; @@ -164,8 +164,8 @@ typedef struct */ typedef struct { - uint32_t *bl_src; /**< Pointer to the source of the bootloader to be be copied.*/ - uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader. */ + uint32_t *bl_src; /**< Pointer to the source of the bootloader to be be copied.*/ + uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader. */ } sd_mbr_command_copy_bl_t; /**@brief Change the address the MBR starts after a reset @@ -192,7 +192,7 @@ typedef struct */ typedef struct { - uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ + uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ } sd_mbr_command_vector_table_base_set_t; /**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR @@ -204,7 +204,7 @@ typedef struct */ typedef struct { - uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ + uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ } sd_mbr_command_irq_forward_address_set_t; /**@brief Input structure containing data used when calling ::sd_mbr_command @@ -215,15 +215,15 @@ typedef struct */ typedef struct { - uint32_t command; /**< Type of command to be issued. See @ref NRF_MBR_COMMANDS. */ - union - { - sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy SoftDevice.*/ - sd_mbr_command_compare_t compare; /**< Parameters for verify.*/ - sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy BootLoader. Requires parameter page. */ - sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/ - sd_mbr_command_irq_forward_address_set_t irq_forward_address_set; /**< Parameters for irq forward address set*/ - } params; /**< Command parameters. */ + uint32_t command; /**< Type of command to be issued. See @ref NRF_MBR_COMMANDS. */ + union + { + sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy SoftDevice.*/ + sd_mbr_command_compare_t compare; /**< Parameters for verify.*/ + sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy BootLoader. Requires parameter page. */ + sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/ + sd_mbr_command_irq_forward_address_set_t irq_forward_address_set; /**< Parameters for irq forward address set*/ + } params; /**< Command parameters. */ } sd_mbr_command_t; /** @} */ @@ -254,7 +254,7 @@ typedef struct * @retval ::NRF_ERROR_NO_MEM No MBR parameter page provided * @retval ::NRF_ERROR_INVALID_PARAM if an invalid command is given. */ -SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param)); +SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t * param)); /** @} */ diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_error.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_error.h index 6badee98e..7e9bf748d 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_error.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_error.h @@ -36,7 +36,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - /** +/** @defgroup nrf_error SoftDevice Global Error Codes @{ diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_error_sdm.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_error_sdm.h index 530959b9d..8e43a6102 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_error_sdm.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_error_sdm.h @@ -36,7 +36,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - /** +/** @addtogroup nrf_sdm_api @{ @defgroup nrf_sdm_error SoftDevice Manager Error Codes diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_nvic.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_nvic.h index 1f79cc3c8..c2fa90f66 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_nvic.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_nvic.h @@ -77,17 +77,17 @@ extern "C" { /**@brief Interrupt priority levels used by the SoftDevice. */ #define __NRF_NVIC_SD_IRQ_PRIOS ((uint8_t)( \ - (1U << 0) /**< Priority level high .*/ \ + (1U << 0) /**< Priority level high .*/ \ | (1U << 1) /**< Priority level medium. */ \ | (1U << 4) /**< Priority level low. */ \ - )) + )) /**@brief Interrupt priority levels available to the application. */ -#define __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t)~__NRF_NVIC_SD_IRQ_PRIOS) +#define __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t) ~__NRF_NVIC_SD_IRQ_PRIOS) /**@brief Interrupts used by the SoftDevice, with IRQn in the range 0-31. */ #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \ - (1U << POWER_CLOCK_IRQn) \ + (1U << POWER_CLOCK_IRQn) \ | (1U << RADIO_IRQn) \ | (1U << RTC0_IRQn) \ | (1U << TIMER0_IRQn) \ @@ -97,7 +97,7 @@ extern "C" { | (1U << TEMP_IRQn) \ | (1U << __NRF_NVIC_NVMC_IRQn) \ | (1U << (uint32_t)SWI5_IRQn) \ - )) + )) /**@brief Interrupts used by the SoftDevice, with IRQn in the range 32-63. */ #define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0) @@ -118,8 +118,8 @@ extern "C" { /**@brief Type representing the state struct for the SoftDevice NVIC module. */ typedef struct { - uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */ - uint32_t volatile __cr_flag; /**< Non-zero if already in a critical region */ + uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */ + uint32_t volatile __cr_flag; /**< Non-zero if already in a critical region */ } nrf_nvic_state_t; /**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an @@ -196,7 +196,7 @@ __STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn); * @retval ::NRF_SUCCESS The interrupt is available for the application. * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. */ -__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq); +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t *p_pending_irq); /**@brief Set Pending Interrupt. * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. @@ -248,7 +248,7 @@ __STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority); * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application. */ -__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority); +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t *p_priority); /**@brief System Reset. * @note Corresponds to NVIC_SystemReset in CMSIS. @@ -268,7 +268,7 @@ __STATIC_INLINE uint32_t sd_nvic_SystemReset(void); * * @retval ::NRF_SUCCESS */ -__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region); +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t *p_is_nested_critical_region); /**@brief Exit critical region. * @@ -285,199 +285,150 @@ __STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical #ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE int __sd_nvic_irq_disable(void) -{ - int pm = __get_PRIMASK(); - __disable_irq(); - return pm; +__STATIC_INLINE int __sd_nvic_irq_disable(void) { + int pm = __get_PRIMASK(); + __disable_irq(); + return pm; } -__STATIC_INLINE void __sd_nvic_irq_enable(void) -{ - __enable_irq(); +__STATIC_INLINE void __sd_nvic_irq_enable(void) { + __enable_irq(); } -__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn) -{ - if (IRQn < 32) - { - return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0; - } - else if (IRQn < 64) - { - return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0; - } - else - { - return 1; - } +__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn) { + if (IRQn < 32) { + return ((1UL << IRQn) & __NRF_NVIC_APP_IRQS_0) != 0; + } else if (IRQn < 64) { + return ((1UL << (IRQn - 32)) & __NRF_NVIC_APP_IRQS_1) != 0; + } else { + return 1; + } } -__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority) -{ - if( (priority >= (1 << __NVIC_PRIO_BITS)) - || (((1 << priority) & __NRF_NVIC_APP_IRQ_PRIOS) == 0) - ) - { - return 0; - } - return 1; +__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority) { + if ((priority >= (1 << __NVIC_PRIO_BITS)) + || (((1 << priority) & __NRF_NVIC_APP_IRQ_PRIOS) == 0) + ) { + return 0; + } + return 1; } -__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn))) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; - } - - if (nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); - } - else - { - NVIC_EnableIRQ(IRQn); - } - return NRF_SUCCESS; -} +__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) { + if (!__sd_nvic_app_accessible_irq(IRQn)) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn))) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } -__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - - if (nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F)); - } - else - { - NVIC_DisableIRQ(IRQn); - } - - return NRF_SUCCESS; + if (nrf_nvic_state.__cr_flag) { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); + } else { + NVIC_EnableIRQ(IRQn); + } + return NRF_SUCCESS; } -__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - *p_pending_irq = NVIC_GetPendingIRQ(IRQn); +__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) { + if (!__sd_nvic_app_accessible_irq(IRQn)) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (nrf_nvic_state.__cr_flag) { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F)); + } else { + NVIC_DisableIRQ(IRQn); + } + return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } } -__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - NVIC_SetPendingIRQ(IRQn); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t *p_pending_irq) { + if (__sd_nvic_app_accessible_irq(IRQn)) { + *p_pending_irq = NVIC_GetPendingIRQ(IRQn); + return NRF_SUCCESS; + } else { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } } -__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - NVIC_ClearPendingIRQ(IRQn); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } +__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) { + if (__sd_nvic_app_accessible_irq(IRQn)) { + NVIC_SetPendingIRQ(IRQn); + return NRF_SUCCESS; + } else { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } } -__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - - if (!__sd_nvic_is_app_accessible_priority(priority)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; - } - - NVIC_SetPriority(IRQn, (uint32_t)priority); - return NRF_SUCCESS; +__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) { + if (__sd_nvic_app_accessible_irq(IRQn)) { + NVIC_ClearPendingIRQ(IRQn); + return NRF_SUCCESS; + } else { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } } -__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - *p_priority = (NVIC_GetPriority(IRQn) & 0xFF); +__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) { + if (!__sd_nvic_app_accessible_irq(IRQn)) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (!__sd_nvic_is_app_accessible_priority(priority)) { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } + + NVIC_SetPriority(IRQn, (uint32_t)priority); return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } } -__STATIC_INLINE uint32_t sd_nvic_SystemReset(void) -{ - NVIC_SystemReset(); - return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN; +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t *p_priority) { + if (__sd_nvic_app_accessible_irq(IRQn)) { + *p_priority = (NVIC_GetPriority(IRQn) & 0xFF); + return NRF_SUCCESS; + } else { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } } -__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region) -{ - int was_masked = __sd_nvic_irq_disable(); - if (!nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__cr_flag = 1; - nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); - NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; - nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); - NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; - *p_is_nested_critical_region = 0; - } - else - { - *p_is_nested_critical_region = 1; - } - if (!was_masked) - { - __sd_nvic_irq_enable(); - } - return NRF_SUCCESS; +__STATIC_INLINE uint32_t sd_nvic_SystemReset(void) { + NVIC_SystemReset(); + return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN; } -__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) -{ - if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0)) - { +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t *p_is_nested_critical_region) { int was_masked = __sd_nvic_irq_disable(); - NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; - NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; - nrf_nvic_state.__cr_flag = 0; - if (!was_masked) - { - __sd_nvic_irq_enable(); + if (!nrf_nvic_state.__cr_flag) { + nrf_nvic_state.__cr_flag = 1; + nrf_nvic_state.__irq_masks[0] = (NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0); + NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; + nrf_nvic_state.__irq_masks[1] = (NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1); + NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; + *p_is_nested_critical_region = 0; + } else { + *p_is_nested_critical_region = 1; + } + if (!was_masked) { + __sd_nvic_irq_enable(); } - } + return NRF_SUCCESS; +} - return NRF_SUCCESS; +__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) { + if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0)) { + int was_masked = __sd_nvic_irq_disable(); + NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; + NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; + nrf_nvic_state.__cr_flag = 0; + if (!was_masked) { + __sd_nvic_irq_enable(); + } + } + + return NRF_SUCCESS; } #endif /* SUPPRESS_INLINE_IMPLEMENTATION */ diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_sdm.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_sdm.h index 6834599e8..24001fb12 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_sdm.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_sdm.h @@ -130,12 +130,12 @@ the start of the SoftDevice (without MBR)*/ /** @brief Defines a macro for retrieving the actual SoftDevice Information Structure size value * from a given base address. Use @ref MBR_SIZE as the argument when the SoftDevice is * installed just above the MBR (the usual case). */ -#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *) ((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET))) +#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *)((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET))) /** @brief Defines a macro for retrieving the actual SoftDevice size value from a given base * address. Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above * the MBR (the usual case). */ -#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET))) +#define SD_SIZE_GET(baseaddr) (*((uint32_t *)((baseaddr) + SD_SIZE_OFFSET))) /** @brief Defines the amount of flash that is used by the SoftDevice. * Add @ref MBR_SIZE to find the first available flash address when the SoftDevice is installed @@ -146,25 +146,25 @@ the start of the SoftDevice (without MBR)*/ /** @brief Defines a macro for retrieving the actual FWID value from a given base address. Use * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the usual * case). */ -#define SD_FWID_GET(baseaddr) (*((uint16_t *) ((baseaddr) + SD_FWID_OFFSET))) +#define SD_FWID_GET(baseaddr) (*((uint16_t *)((baseaddr) + SD_FWID_OFFSET))) /** @brief Defines a macro for retrieving the actual SoftDevice ID from a given base address. Use * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the * usual case). */ #define SD_ID_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_ID_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ - ? (*((uint32_t *) ((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID) + ? (*((uint32_t *)((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID) /** @brief Defines a macro for retrieving the actual SoftDevice version from a given base address. * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR * (the usual case). */ #define SD_VERSION_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_VERSION_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ - ? (*((uint32_t *) ((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID) + ? (*((uint32_t *)((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID) /** @brief Defines a macro for retrieving the address of SoftDevice unique str based on a given base address. * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR * (the usual case). */ #define SD_UNIQUE_STR_ADDR_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_UNIQUE_STR_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ - ? (((uint8_t *) ((baseaddr) + SD_UNIQUE_STR_OFFSET))) : SDM_INFO_FIELD_INVALID) + ? (((uint8_t *)((baseaddr) + SD_UNIQUE_STR_OFFSET))) : SDM_INFO_FIELD_INVALID) /**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges * @{ */ @@ -174,7 +174,7 @@ the start of the SoftDevice (without MBR)*/ /**@defgroup NRF_FAULT_IDS Fault ID types * @{ */ -#define NRF_FAULT_ID_SD_ASSERT (NRF_FAULT_ID_SD_RANGE_START + 1) /**< SoftDevice assertion. The info parameter is reserved for future used. */ +#define NRF_FAULT_ID_SD_ASSERT (NRF_FAULT_ID_SD_RANGE_START + 1) /**< SoftDevice assertion. The info parameter is reserved for future used. */ #define NRF_FAULT_ID_APP_MEMACC (NRF_FAULT_ID_APP_RANGE_START + 1) /**< Application invalid memory access. The info parameter will contain 0x00000000, in case of SoftDevice RAM access violation. In case of SoftDevice peripheral register violation the info parameter will contain the sub-region number of @@ -190,11 +190,11 @@ the start of the SoftDevice (without MBR)*/ /**@brief nRF SoftDevice Manager API SVC numbers. */ enum NRF_SD_SVCS { - SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ - SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ - SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ - SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ - SVC_SDM_LAST /**< Placeholder for last SDM SVC */ + SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ + SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ + SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ + SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ + SVC_SDM_LAST /**< Placeholder for last SDM SVC */ }; /** @} */ @@ -237,15 +237,15 @@ enum NRF_SD_SVCS /**@brief Type representing LFCLK oscillator source. */ typedef struct { - uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ - uint8_t rc_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second + uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ + uint8_t rc_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second units (nRF52: 1-32). @note To avoid excessive clock drift, 0.5 degrees Celsius is the maximum temperature change allowed in one calibration timer interval. The interval should be selected to ensure this. @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC. */ - uint8_t rc_temp_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: How often (in number of calibration + uint8_t rc_temp_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: How often (in number of calibration intervals) the RC oscillator shall be calibrated if the temperature hasn't changed. 0: Always calibrate even if the temperature hasn't changed. @@ -263,7 +263,7 @@ typedef struct least once every 8 seconds and for temperature changes of 0.5 degrees Celsius every 4 seconds. See the Product Specification for the nRF52 device being used for more information.*/ - uint8_t accuracy; /**< External clock accuracy used in the LL to compute timing + uint8_t accuracy; /**< External clock accuracy used in the LL to compute timing windows, see @ref NRF_CLOCK_LF_ACCURACY.*/ } nrf_clock_lf_cfg_t; @@ -323,7 +323,7 @@ typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info); * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected. * @retval ::NRF_ERROR_INVALID_PARAM Invalid clock source configuration supplied in p_clock_lf_cfg. */ -SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler)); +SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const *p_clock_lf_cfg, nrf_fault_handler_t fault_handler)); /**@brief Disables the SoftDevice and by extension the protocol stack. diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_soc.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_soc.h index 3751d133f..2baf305c7 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_soc.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_soc.h @@ -100,7 +100,7 @@ extern "C" { /**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is enabled. */ #define NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK ((uint32_t)( \ - (1U << 17) \ + (1U << 17) \ | (1U << 18) \ | (1U << 19) \ | (1U << 20) \ @@ -115,16 +115,16 @@ extern "C" { | (1U << 29) \ | (1U << 30) \ | (1U << 31) \ - )) + )) /**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is disabled. */ #define NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK ((uint32_t)(0)) /**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is enabled. */ #define NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK ((uint32_t)( \ - (1U << 4) \ + (1U << 4) \ | (1U << 5) \ - )) + )) /**@} */ @@ -134,148 +134,148 @@ extern "C" { /**@brief The SVC numbers used by the SVC functions in the SoC library. */ enum NRF_SOC_SVCS { - SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE, - SD_PPI_CHANNEL_ENABLE_SET = SOC_SVC_BASE + 1, - SD_PPI_CHANNEL_ENABLE_CLR = SOC_SVC_BASE + 2, - SD_PPI_CHANNEL_ASSIGN = SOC_SVC_BASE + 3, - SD_PPI_GROUP_TASK_ENABLE = SOC_SVC_BASE + 4, - SD_PPI_GROUP_TASK_DISABLE = SOC_SVC_BASE + 5, - SD_PPI_GROUP_ASSIGN = SOC_SVC_BASE + 6, - SD_PPI_GROUP_GET = SOC_SVC_BASE + 7, - SD_FLASH_PAGE_ERASE = SOC_SVC_BASE + 8, - SD_FLASH_WRITE = SOC_SVC_BASE + 9, - SD_PROTECTED_REGISTER_WRITE = SOC_SVC_BASE + 11, - SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, - SD_MUTEX_ACQUIRE = SOC_SVC_BASE_NOT_AVAILABLE + 1, - SD_MUTEX_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 2, - SD_RAND_APPLICATION_POOL_CAPACITY_GET = SOC_SVC_BASE_NOT_AVAILABLE + 3, - SD_RAND_APPLICATION_BYTES_AVAILABLE_GET = SOC_SVC_BASE_NOT_AVAILABLE + 4, - SD_RAND_APPLICATION_VECTOR_GET = SOC_SVC_BASE_NOT_AVAILABLE + 5, - SD_POWER_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 6, - SD_POWER_SYSTEM_OFF = SOC_SVC_BASE_NOT_AVAILABLE + 7, - SD_POWER_RESET_REASON_GET = SOC_SVC_BASE_NOT_AVAILABLE + 8, - SD_POWER_RESET_REASON_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 9, - SD_POWER_POF_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 10, - SD_POWER_POF_THRESHOLD_SET = SOC_SVC_BASE_NOT_AVAILABLE + 11, - SD_POWER_POF_THRESHOLDVDDH_SET = SOC_SVC_BASE_NOT_AVAILABLE + 12, - SD_POWER_RAM_POWER_SET = SOC_SVC_BASE_NOT_AVAILABLE + 13, - SD_POWER_RAM_POWER_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 14, - SD_POWER_RAM_POWER_GET = SOC_SVC_BASE_NOT_AVAILABLE + 15, - SD_POWER_GPREGRET_SET = SOC_SVC_BASE_NOT_AVAILABLE + 16, - SD_POWER_GPREGRET_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 17, - SD_POWER_GPREGRET_GET = SOC_SVC_BASE_NOT_AVAILABLE + 18, - SD_POWER_DCDC_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 19, - SD_POWER_DCDC0_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 20, - SD_APP_EVT_WAIT = SOC_SVC_BASE_NOT_AVAILABLE + 21, - SD_CLOCK_HFCLK_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 22, - SD_CLOCK_HFCLK_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 23, - SD_CLOCK_HFCLK_IS_RUNNING = SOC_SVC_BASE_NOT_AVAILABLE + 24, - SD_RADIO_NOTIFICATION_CFG_SET = SOC_SVC_BASE_NOT_AVAILABLE + 25, - SD_ECB_BLOCK_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 26, - SD_ECB_BLOCKS_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 27, - SD_RADIO_SESSION_OPEN = SOC_SVC_BASE_NOT_AVAILABLE + 28, - SD_RADIO_SESSION_CLOSE = SOC_SVC_BASE_NOT_AVAILABLE + 29, - SD_RADIO_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 30, - SD_EVT_GET = SOC_SVC_BASE_NOT_AVAILABLE + 31, - SD_TEMP_GET = SOC_SVC_BASE_NOT_AVAILABLE + 32, - SD_POWER_USBPWRRDY_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 33, - SD_POWER_USBDETECTED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 34, - SD_POWER_USBREMOVED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 35, - SD_POWER_USBREGSTATUS_GET = SOC_SVC_BASE_NOT_AVAILABLE + 36, - SVC_SOC_LAST = SOC_SVC_BASE_NOT_AVAILABLE + 37 + SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE, + SD_PPI_CHANNEL_ENABLE_SET = SOC_SVC_BASE + 1, + SD_PPI_CHANNEL_ENABLE_CLR = SOC_SVC_BASE + 2, + SD_PPI_CHANNEL_ASSIGN = SOC_SVC_BASE + 3, + SD_PPI_GROUP_TASK_ENABLE = SOC_SVC_BASE + 4, + SD_PPI_GROUP_TASK_DISABLE = SOC_SVC_BASE + 5, + SD_PPI_GROUP_ASSIGN = SOC_SVC_BASE + 6, + SD_PPI_GROUP_GET = SOC_SVC_BASE + 7, + SD_FLASH_PAGE_ERASE = SOC_SVC_BASE + 8, + SD_FLASH_WRITE = SOC_SVC_BASE + 9, + SD_PROTECTED_REGISTER_WRITE = SOC_SVC_BASE + 11, + SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, + SD_MUTEX_ACQUIRE = SOC_SVC_BASE_NOT_AVAILABLE + 1, + SD_MUTEX_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 2, + SD_RAND_APPLICATION_POOL_CAPACITY_GET = SOC_SVC_BASE_NOT_AVAILABLE + 3, + SD_RAND_APPLICATION_BYTES_AVAILABLE_GET = SOC_SVC_BASE_NOT_AVAILABLE + 4, + SD_RAND_APPLICATION_VECTOR_GET = SOC_SVC_BASE_NOT_AVAILABLE + 5, + SD_POWER_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 6, + SD_POWER_SYSTEM_OFF = SOC_SVC_BASE_NOT_AVAILABLE + 7, + SD_POWER_RESET_REASON_GET = SOC_SVC_BASE_NOT_AVAILABLE + 8, + SD_POWER_RESET_REASON_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 9, + SD_POWER_POF_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 10, + SD_POWER_POF_THRESHOLD_SET = SOC_SVC_BASE_NOT_AVAILABLE + 11, + SD_POWER_POF_THRESHOLDVDDH_SET = SOC_SVC_BASE_NOT_AVAILABLE + 12, + SD_POWER_RAM_POWER_SET = SOC_SVC_BASE_NOT_AVAILABLE + 13, + SD_POWER_RAM_POWER_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 14, + SD_POWER_RAM_POWER_GET = SOC_SVC_BASE_NOT_AVAILABLE + 15, + SD_POWER_GPREGRET_SET = SOC_SVC_BASE_NOT_AVAILABLE + 16, + SD_POWER_GPREGRET_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 17, + SD_POWER_GPREGRET_GET = SOC_SVC_BASE_NOT_AVAILABLE + 18, + SD_POWER_DCDC_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 19, + SD_POWER_DCDC0_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 20, + SD_APP_EVT_WAIT = SOC_SVC_BASE_NOT_AVAILABLE + 21, + SD_CLOCK_HFCLK_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 22, + SD_CLOCK_HFCLK_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 23, + SD_CLOCK_HFCLK_IS_RUNNING = SOC_SVC_BASE_NOT_AVAILABLE + 24, + SD_RADIO_NOTIFICATION_CFG_SET = SOC_SVC_BASE_NOT_AVAILABLE + 25, + SD_ECB_BLOCK_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 26, + SD_ECB_BLOCKS_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 27, + SD_RADIO_SESSION_OPEN = SOC_SVC_BASE_NOT_AVAILABLE + 28, + SD_RADIO_SESSION_CLOSE = SOC_SVC_BASE_NOT_AVAILABLE + 29, + SD_RADIO_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 30, + SD_EVT_GET = SOC_SVC_BASE_NOT_AVAILABLE + 31, + SD_TEMP_GET = SOC_SVC_BASE_NOT_AVAILABLE + 32, + SD_POWER_USBPWRRDY_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 33, + SD_POWER_USBDETECTED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 34, + SD_POWER_USBREMOVED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 35, + SD_POWER_USBREGSTATUS_GET = SOC_SVC_BASE_NOT_AVAILABLE + 36, + SVC_SOC_LAST = SOC_SVC_BASE_NOT_AVAILABLE + 37 }; /**@brief Possible values of a ::nrf_mutex_t. */ enum NRF_MUTEX_VALUES { - NRF_MUTEX_FREE, - NRF_MUTEX_TAKEN + NRF_MUTEX_FREE, + NRF_MUTEX_TAKEN }; /**@brief Power modes. */ enum NRF_POWER_MODES { - NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ - NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ + NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ + NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ }; /**@brief Power failure thresholds */ enum NRF_POWER_THRESHOLDS { - NRF_POWER_THRESHOLD_V17 = 4UL, /**< 1.7 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V18, /**< 1.8 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V19, /**< 1.9 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V20, /**< 2.0 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V22, /**< 2.2 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V24, /**< 2.4 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V26, /**< 2.6 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V27, /**< 2.7 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V28 /**< 2.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V17 = 4UL, /**< 1.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V18, /**< 1.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V19, /**< 1.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V20, /**< 2.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V22, /**< 2.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V24, /**< 2.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V26, /**< 2.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V28 /**< 2.8 Volts power failure threshold. */ }; /**@brief Power failure thresholds for high voltage */ enum NRF_POWER_THRESHOLDVDDHS { - NRF_POWER_THRESHOLDVDDH_V27, /**< 2.7 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V28, /**< 2.8 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V29, /**< 2.9 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V30, /**< 3.0 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V31, /**< 3.1 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V32, /**< 3.2 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V33, /**< 3.3 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V34, /**< 3.4 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V35, /**< 3.5 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V36, /**< 3.6 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V37, /**< 3.7 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V38, /**< 3.8 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V39, /**< 3.9 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V40, /**< 4.0 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V41, /**< 4.1 Volts power failure threshold. */ - NRF_POWER_THRESHOLDVDDH_V42 /**< 4.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V28, /**< 2.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V29, /**< 2.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V30, /**< 3.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V31, /**< 3.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V32, /**< 3.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V33, /**< 3.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V34, /**< 3.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V35, /**< 3.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V36, /**< 3.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V37, /**< 3.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V38, /**< 3.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V39, /**< 3.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V40, /**< 4.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V41, /**< 4.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V42 /**< 4.2 Volts power failure threshold. */ }; /**@brief DC/DC converter modes. */ enum NRF_POWER_DCDC_MODES { - NRF_POWER_DCDC_DISABLE, /**< The DCDC is disabled. */ - NRF_POWER_DCDC_ENABLE /**< The DCDC is enabled. */ + NRF_POWER_DCDC_DISABLE, /**< The DCDC is disabled. */ + NRF_POWER_DCDC_ENABLE /**< The DCDC is enabled. */ }; /**@brief Radio notification distances. */ enum NRF_RADIO_NOTIFICATION_DISTANCES { - NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ - NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ + NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ }; /**@brief Radio notification types. */ enum NRF_RADIO_NOTIFICATION_TYPES { - NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ + NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ }; /**@brief The Radio signal callback types. */ enum NRF_RADIO_CALLBACK_SIGNAL_TYPE { - NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ }; /**@brief The actions requested by the signal callback. @@ -285,28 +285,28 @@ enum NRF_RADIO_CALLBACK_SIGNAL_TYPE */ enum NRF_RADIO_SIGNAL_CALLBACK_ACTION { - NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current + NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current timeslot. Maximum execution time for this action: @ref NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US. This action must be started at least @ref NRF_RADIO_MIN_EXTENSION_MARGIN_US before the end of the timeslot. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ }; /**@brief Radio timeslot high frequency clock source configuration. */ enum NRF_RADIO_HFCLK_CFG { - NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the + NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the external crystal for the whole duration of the timeslot. This should be the preferred option for events that use the radio or require high timing accuracy. @note The SoftDevice will automatically turn on and off the external crystal, at the beginning and end of the timeslot, respectively. The crystal may also intentionally be left running after the timeslot, in cases where it is needed by the SoftDevice shortly after the end of the timeslot. */ - NRF_RADIO_HFCLK_CFG_NO_GUARANTEE /**< This configuration allows for earlier and tighter scheduling of timeslots. + NRF_RADIO_HFCLK_CFG_NO_GUARANTEE /**< This configuration allows for earlier and tighter scheduling of timeslots. The RC oscillator may be the clock source in part or for the whole duration of the timeslot. The RC oscillator's accuracy must therefore be taken into consideration. @note If the application will use the radio peripheral in timeslots with this configuration, @@ -316,33 +316,33 @@ enum NRF_RADIO_HFCLK_CFG /**@brief Radio timeslot priorities. */ enum NRF_RADIO_PRIORITY { - NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ - NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activities of the SoftDevice stack(s)). */ + NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ + NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activities of the SoftDevice stack(s)). */ }; /**@brief Radio timeslot request type. */ enum NRF_RADIO_REQUEST_TYPE { - NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */ - NRF_RADIO_REQ_TYPE_NORMAL /**< Normal radio timeslot request. */ + NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */ + NRF_RADIO_REQ_TYPE_NORMAL /**< Normal radio timeslot request. */ }; /**@brief SoC Events. */ enum NRF_SOC_EVTS { - NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ - NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ - NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ - NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ - NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ - NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ - NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */ - NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio timeslot session is idle. */ - NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio timeslot session is closed. */ - NRF_EVT_POWER_USB_POWER_READY, /**< Event indicating that a USB 3.3 V supply is ready. */ - NRF_EVT_POWER_USB_DETECTED, /**< Event indicating that voltage supply is detected on VBUS. */ - NRF_EVT_POWER_USB_REMOVED, /**< Event indicating that voltage supply is removed from VBUS. */ - NRF_EVT_NUMBER_OF_EVTS + NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ + NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ + NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ + NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ + NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ + NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ + NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */ + NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio timeslot session is idle. */ + NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio timeslot session is closed. */ + NRF_EVT_POWER_USB_POWER_READY, /**< Event indicating that a USB 3.3 V supply is ready. */ + NRF_EVT_POWER_USB_DETECTED, /**< Event indicating that voltage supply is detected on VBUS. */ + NRF_EVT_POWER_USB_REMOVED, /**< Event indicating that voltage supply is removed from VBUS. */ + NRF_EVT_NUMBER_OF_EVTS }; /**@} */ @@ -359,47 +359,47 @@ typedef volatile uint8_t nrf_mutex_t; /**@brief Parameters for a request for a timeslot as early as possible. */ typedef struct { - uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ - uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ - uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ - uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ + uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ } nrf_radio_request_earliest_t; /**@brief Parameters for a normal radio timeslot request. */ typedef struct { - uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ - uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ - uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ - uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ + uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ } nrf_radio_request_normal_t; /**@brief Radio timeslot request parameters. */ typedef struct { - uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ - union - { - nrf_radio_request_earliest_t earliest; /**< Parameters for requesting a radio timeslot as early as possible. */ - nrf_radio_request_normal_t normal; /**< Parameters for requesting a normal radio timeslot. */ - } params; /**< Parameter union. */ + uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ + union + { + nrf_radio_request_earliest_t earliest; /**< Parameters for requesting a radio timeslot as early as possible. */ + nrf_radio_request_normal_t normal; /**< Parameters for requesting a normal radio timeslot. */ + } params; /**< Parameter union. */ } nrf_radio_request_t; /**@brief Return parameters of the radio timeslot signal callback. */ typedef struct { - uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ - union - { - struct - { - nrf_radio_request_t * p_next; /**< The request parameters for the next radio timeslot. */ - } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ - struct + uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ + union { - uint32_t length_us; /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ - } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ - } params; /**< Parameter union. */ + struct + { + nrf_radio_request_t *p_next; /**< The request parameters for the next radio timeslot. */ + } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ + struct + { + uint32_t length_us; /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ + } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ + } params; /**< Parameter union. */ } nrf_radio_signal_callback_return_param_t; /**@brief The radio timeslot signal callback type. @@ -414,7 +414,7 @@ typedef struct * * @return Pointer to structure containing action requested by the application. */ -typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type); +typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t)(uint8_t signal_type); /**@brief AES ECB parameter typedefs */ typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH]; /**< Encryption key type. */ @@ -424,18 +424,18 @@ typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Ciphertex /**@brief AES ECB data structure */ typedef struct { - soc_ecb_key_t key; /**< Encryption key. */ - soc_ecb_cleartext_t cleartext; /**< Cleartext data. */ - soc_ecb_ciphertext_t ciphertext; /**< Ciphertext data. */ + soc_ecb_key_t key; /**< Encryption key. */ + soc_ecb_cleartext_t cleartext; /**< Cleartext data. */ + soc_ecb_ciphertext_t ciphertext; /**< Ciphertext data. */ } nrf_ecb_hal_data_t; /**@brief AES ECB block. Used to provide multiple blocks in a single call to @ref sd_ecb_blocks_encrypt.*/ typedef struct { - soc_ecb_key_t const * p_key; /**< Pointer to the Encryption key. */ - soc_ecb_cleartext_t const * p_cleartext; /**< Pointer to the Cleartext data. */ - soc_ecb_ciphertext_t * p_ciphertext; /**< Pointer to the Ciphertext data. */ + soc_ecb_key_t const *p_key; /**< Pointer to the Encryption key. */ + soc_ecb_cleartext_t const *p_cleartext; /**< Pointer to the Cleartext data. */ + soc_ecb_ciphertext_t *p_ciphertext; /**< Pointer to the Ciphertext data. */ } nrf_ecb_hal_data_block_t; /**@} */ @@ -663,7 +663,7 @@ SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_ * * @retval ::NRF_SUCCESS */ -SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t *p_gpregret)); +SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t * p_gpregret)); /**@brief Enable or disable the DC/DC regulator for the regulator stage 1 (REG1). * @@ -780,7 +780,7 @@ SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t c * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid. * @retval ::NRF_SUCCESS */ -SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)); +SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void *evt_endpoint, const volatile void *task_endpoint)); /**@brief Task to enable a channel group. * @@ -941,7 +941,7 @@ SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp)); * @retval ::NRF_ERROR_FORBIDDEN Tried to write to an address outside the application flash area. * @retval ::NRF_SUCCESS The command was accepted. */ -SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * p_dst, uint32_t const * p_src, uint32_t size)); +SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * p_dst, uint32_t const *p_src, uint32_t size)); /**@brief Flash Erase page @@ -997,7 +997,7 @@ SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)) * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. * @retval ::NRF_SUCCESS Otherwise. */ - SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); +SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); /**@brief Closes a session for radio timeslot requests. * @@ -1010,7 +1010,7 @@ SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)) * @retval ::NRF_ERROR_BUSY If session is currently being closed. * @retval ::NRF_SUCCESS Otherwise. */ - SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); +SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); /**@brief Requests a radio timeslot. * @@ -1047,7 +1047,7 @@ SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)) * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid. * @retval ::NRF_SUCCESS Otherwise. */ - SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t const * p_request)); +SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t const *p_request)); /**@brief Write register protected by the SoftDevice * diff --git a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_svc.h b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_svc.h index 231a54f94..293001ecc 100644 --- a/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_svc.h +++ b/ports/nrf/bluetooth/s140_nrf52_7.0.1/s140_nrf52_7.0.1_API/include/nrf_svc.h @@ -60,33 +60,33 @@ extern "C" { #else #ifndef SVCALL -#if defined (__CC_ARM) +#if defined(__CC_ARM) #define SVCALL(number, return_type, signature) return_type __svc(number) signature -#elif defined (__GNUC__) +#elif defined(__GNUC__) #ifdef __cplusplus #define GCC_CAST_CPP (uint16_t) #else #define GCC_CAST_CPP #endif #define SVCALL(number, return_type, signature) \ - _Pragma("GCC diagnostic push") \ - _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ - __attribute__((naked)) \ - __attribute__((unused)) \ - static return_type signature \ - { \ - __asm( \ - "svc %0\n" \ - "bx r14" : : "I" (GCC_CAST_CPP number) : "r0" \ - ); \ - } \ - _Pragma("GCC diagnostic pop") + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ + __attribute__((naked)) \ + __attribute__((unused)) \ + static return_type signature \ + { \ + __asm( \ + "svc %0\n" \ + "bx r14" : : "I" (GCC_CAST_CPP number) : "r0" \ + ); \ + } \ + _Pragma("GCC diagnostic pop") -#elif defined (__ICCARM__) +#elif defined(__ICCARM__) #define PRAGMA(x) _Pragma(#x) #define SVCALL(number, return_type, signature) \ -PRAGMA(swi_number = (number)) \ - __swi return_type signature; + PRAGMA(swi_number = (number)) \ + __swi return_type signature; #else #define SVCALL(number, return_type, signature) return_type signature #endif diff --git a/ports/nrf/boards/ADM_B_NRF52840_1/board.c b/ports/nrf/boards/ADM_B_NRF52840_1/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/ADM_B_NRF52840_1/board.c +++ b/ports/nrf/boards/ADM_B_NRF52840_1/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/TG-Watch/board.c b/ports/nrf/boards/TG-Watch/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/TG-Watch/board.c +++ b/ports/nrf/boards/TG-Watch/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/arduino_nano_33_ble/board.c b/ports/nrf/boards/arduino_nano_33_ble/board.c index d1689e9dd..8359b3946 100644 --- a/ports/nrf/boards/arduino_nano_33_ble/board.c +++ b/ports/nrf/boards/arduino_nano_33_ble/board.c @@ -55,7 +55,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/bastble/board.c b/ports/nrf/boards/bastble/board.c index b6fb04f06..ee999b650 100644 --- a/ports/nrf/boards/bastble/board.c +++ b/ports/nrf/boards/bastble/board.c @@ -33,7 +33,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/bless_dev_board_multi_sensor/board.c b/ports/nrf/boards/bless_dev_board_multi_sensor/board.c index 6970294ec..d1f26b0b5 100644 --- a/ports/nrf/boards/bless_dev_board_multi_sensor/board.c +++ b/ports/nrf/boards/bless_dev_board_multi_sensor/board.c @@ -4,7 +4,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/circuitplayground_bluefruit/board.c b/ports/nrf/boards/circuitplayground_bluefruit/board.c index ff731d8f9..a0013e721 100644 --- a/ports/nrf/boards/circuitplayground_bluefruit/board.c +++ b/ports/nrf/boards/circuitplayground_bluefruit/board.c @@ -36,17 +36,17 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { // Turn off board.POWER_SWITCH (power-saving switch) on each soft reload, to prevent confusion. nrf_gpio_cfg(POWER_SWITCH_PIN->number, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); nrf_gpio_pin_write(POWER_SWITCH_PIN->number, false); board_reset_user_neopixels(&pin_P0_13, 10); diff --git a/ports/nrf/boards/clue_nrf52840_express/board.c b/ports/nrf/boards/clue_nrf52840_express/board.c index cd46ce75d..b5c0f56ba 100644 --- a/ports/nrf/boards/clue_nrf52840_express/board.c +++ b/ports/nrf/boards/clue_nrf52840_express/board.c @@ -47,11 +47,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_P0_14, &pin_P0_15, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -62,7 +62,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/nrf/boards/electronut_labs_blip/board.c b/ports/nrf/boards/electronut_labs_blip/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/electronut_labs_blip/board.c +++ b/ports/nrf/boards/electronut_labs_blip/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/electronut_labs_papyr/board.c b/ports/nrf/boards/electronut_labs_papyr/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/electronut_labs_papyr/board.c +++ b/ports/nrf/boards/electronut_labs_papyr/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/feather_bluefruit_sense/board.c b/ports/nrf/boards/feather_bluefruit_sense/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/feather_bluefruit_sense/board.c +++ b/ports/nrf/boards/feather_bluefruit_sense/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/feather_nrf52840_express/board.c b/ports/nrf/boards/feather_nrf52840_express/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/feather_nrf52840_express/board.c +++ b/ports/nrf/boards/feather_nrf52840_express/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/hiibot_bluefi/board.c b/ports/nrf/boards/hiibot_bluefi/board.c index a3fd5cf12..daca53961 100644 --- a/ports/nrf/boards/hiibot_bluefi/board.c +++ b/ports/nrf/boards/hiibot_bluefi/board.c @@ -47,23 +47,23 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_P0_07, &pin_P1_08, NULL); // SCK, MOSI, MISO common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, &pin_P0_27, // TFT_DC Command or data &pin_P0_05, // TFT_CS Chip select - NULL, // no TFT_RST Reset - //&pin_P1_14, // TFT_RST Reset + NULL, // no TFT_RST Reset + // &pin_P1_14, // TFT_RST Reset 60000000, // Baudrate 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/nrf/boards/hiibot_bluefi/mpconfigboard.h b/ports/nrf/boards/hiibot_bluefi/mpconfigboard.h index 4b7a884cf..3c0af124e 100644 --- a/ports/nrf/boards/hiibot_bluefi/mpconfigboard.h +++ b/ports/nrf/boards/hiibot_bluefi/mpconfigboard.h @@ -30,35 +30,35 @@ #define MICROPY_HW_BOARD_NAME "HiiBot BlueFi" #define MICROPY_HW_MCU_NAME "nRF52840" -#define MICROPY_HW_NEOPIXEL (&pin_P1_10) // P18 / D18 +#define MICROPY_HW_NEOPIXEL (&pin_P1_10) // P18 / D18 -#define MICROPY_HW_LED_STATUS (&pin_P1_12) // P17 / D17 +#define MICROPY_HW_LED_STATUS (&pin_P1_12) // P17 / D17 #if QSPI_FLASH_FILESYSTEM -#define MICROPY_QSPI_DATA0 NRF_GPIO_PIN_MAP(1, 1) -#define MICROPY_QSPI_DATA1 NRF_GPIO_PIN_MAP(1, 4) -#define MICROPY_QSPI_DATA2 NRF_GPIO_PIN_MAP(1, 6) -#define MICROPY_QSPI_DATA3 NRF_GPIO_PIN_MAP(1, 5) -#define MICROPY_QSPI_SCK NRF_GPIO_PIN_MAP(1, 3) -#define MICROPY_QSPI_CS NRF_GPIO_PIN_MAP(1, 2) +#define MICROPY_QSPI_DATA0 NRF_GPIO_PIN_MAP(1, 1) +#define MICROPY_QSPI_DATA1 NRF_GPIO_PIN_MAP(1, 4) +#define MICROPY_QSPI_DATA2 NRF_GPIO_PIN_MAP(1, 6) +#define MICROPY_QSPI_DATA3 NRF_GPIO_PIN_MAP(1, 5) +#define MICROPY_QSPI_SCK NRF_GPIO_PIN_MAP(1, 3) +#define MICROPY_QSPI_CS NRF_GPIO_PIN_MAP(1, 2) #endif #if SPI_FLASH_FILESYSTEM -#define SPI_FLASH_MOSI_PIN &pin_P1_01 -#define SPI_FLASH_MISO_PIN &pin_P1_04 -#define SPI_FLASH_SCK_PIN &pin_P1_03 -#define SPI_FLASH_CS_PIN &pin_P1_02 +#define SPI_FLASH_MOSI_PIN &pin_P1_01 +#define SPI_FLASH_MISO_PIN &pin_P1_04 +#define SPI_FLASH_SCK_PIN &pin_P1_03 +#define SPI_FLASH_CS_PIN &pin_P1_02 #endif // No 32kHz crystal. THere's a 32MHz crystal in the nRF module. -#define BOARD_HAS_32KHZ_XTAL (0) +#define BOARD_HAS_32KHZ_XTAL (0) -#define DEFAULT_I2C_BUS_SCL (&pin_P0_00) -#define DEFAULT_I2C_BUS_SDA (&pin_P0_31) +#define DEFAULT_I2C_BUS_SCL (&pin_P0_00) +#define DEFAULT_I2C_BUS_SDA (&pin_P0_31) -#define DEFAULT_SPI_BUS_SCK (&pin_P0_06) -#define DEFAULT_SPI_BUS_MOSI (&pin_P0_26) -#define DEFAULT_SPI_BUS_MISO (&pin_P0_04) +#define DEFAULT_SPI_BUS_SCK (&pin_P0_06) +#define DEFAULT_SPI_BUS_MOSI (&pin_P0_26) +#define DEFAULT_SPI_BUS_MISO (&pin_P0_04) -#define DEFAULT_UART_BUS_RX (&pin_P0_28) -#define DEFAULT_UART_BUS_TX (&pin_P0_02) +#define DEFAULT_UART_BUS_RX (&pin_P0_28) +#define DEFAULT_UART_BUS_TX (&pin_P0_02) diff --git a/ports/nrf/boards/hiibot_bluefi/pins.c b/ports/nrf/boards/hiibot_bluefi/pins.c index c7879c4c2..f871d5db8 100644 --- a/ports/nrf/boards/hiibot_bluefi/pins.c +++ b/ports/nrf/boards/hiibot_bluefi/pins.c @@ -111,7 +111,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_P27), MP_ROM_PTR(&pin_P1_13) }, { MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_P1_13) }, - //{ MP_ROM_QSTR(MP_QSTR_TFT_RESET), MP_ROM_PTR(&pin_P1_13) }, + // { MP_ROM_QSTR(MP_QSTR_TFT_RESET), MP_ROM_PTR(&pin_P1_13) }, { MP_ROM_QSTR(MP_QSTR_TFT_BACKLIGHT), MP_ROM_PTR(&pin_P1_13) }, // P28~P33/D28~D33 connecte into QSPI FlashROM (W25Q16JV_IQ) diff --git a/ports/nrf/boards/ikigaisense_vita/board.c b/ports/nrf/boards/ikigaisense_vita/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/ikigaisense_vita/board.c +++ b/ports/nrf/boards/ikigaisense_vita/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/itsybitsy_nrf52840_express/board.c b/ports/nrf/boards/itsybitsy_nrf52840_express/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/itsybitsy_nrf52840_express/board.c +++ b/ports/nrf/boards/itsybitsy_nrf52840_express/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/makerdiary_m60_keyboard/board.c b/ports/nrf/boards/makerdiary_m60_keyboard/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/makerdiary_m60_keyboard/board.c +++ b/ports/nrf/boards/makerdiary_m60_keyboard/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/makerdiary_m60_keyboard/pins.c b/ports/nrf/boards/makerdiary_m60_keyboard/pins.c index fc85fa24b..82e9dfc5a 100644 --- a/ports/nrf/boards/makerdiary_m60_keyboard/pins.c +++ b/ports/nrf/boards/makerdiary_m60_keyboard/pins.c @@ -4,38 +4,38 @@ #include "shared-module/displayio/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_R1), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_R2), MP_ROM_PTR(&pin_P0_06) }, - { MP_ROM_QSTR(MP_QSTR_R3), MP_ROM_PTR(&pin_P0_07) }, - { MP_ROM_QSTR(MP_QSTR_R4), MP_ROM_PTR(&pin_P0_08) }, - { MP_ROM_QSTR(MP_QSTR_R5), MP_ROM_PTR(&pin_P1_09) }, - { MP_ROM_QSTR(MP_QSTR_R6), MP_ROM_PTR(&pin_P1_08) }, - { MP_ROM_QSTR(MP_QSTR_R7), MP_ROM_PTR(&pin_P0_12) }, - { MP_ROM_QSTR(MP_QSTR_R8), MP_ROM_PTR(&pin_P0_11) }, - - { MP_ROM_QSTR(MP_QSTR_C1), MP_ROM_PTR(&pin_P0_19) }, - { MP_ROM_QSTR(MP_QSTR_C2), MP_ROM_PTR(&pin_P0_20) }, - { MP_ROM_QSTR(MP_QSTR_C3), MP_ROM_PTR(&pin_P0_21) }, - { MP_ROM_QSTR(MP_QSTR_C4), MP_ROM_PTR(&pin_P0_22) }, - { MP_ROM_QSTR(MP_QSTR_C5), MP_ROM_PTR(&pin_P0_23) }, - { MP_ROM_QSTR(MP_QSTR_C6), MP_ROM_PTR(&pin_P0_24) }, - { MP_ROM_QSTR(MP_QSTR_C7), MP_ROM_PTR(&pin_P0_25) }, - { MP_ROM_QSTR(MP_QSTR_C8), MP_ROM_PTR(&pin_P0_26) }, - - { MP_ROM_QSTR(MP_QSTR_TXD), MP_ROM_PTR(&pin_P0_16) }, - { MP_ROM_QSTR(MP_QSTR_RXD), MP_ROM_PTR(&pin_P0_15) }, - - { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_P1_06) }, - { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_P1_05) }, - - { MP_ROM_QSTR(MP_QSTR_LED_R), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_P0_31) }, - - { MP_ROM_QSTR(MP_QSTR_BTN), MP_ROM_PTR(&pin_P0_27) }, + { MP_ROM_QSTR(MP_QSTR_R1), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_R2), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_R3), MP_ROM_PTR(&pin_P0_07) }, + { MP_ROM_QSTR(MP_QSTR_R4), MP_ROM_PTR(&pin_P0_08) }, + { MP_ROM_QSTR(MP_QSTR_R5), MP_ROM_PTR(&pin_P1_09) }, + { MP_ROM_QSTR(MP_QSTR_R6), MP_ROM_PTR(&pin_P1_08) }, + { MP_ROM_QSTR(MP_QSTR_R7), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_R8), MP_ROM_PTR(&pin_P0_11) }, + + { MP_ROM_QSTR(MP_QSTR_C1), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_C2), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_C3), MP_ROM_PTR(&pin_P0_21) }, + { MP_ROM_QSTR(MP_QSTR_C4), MP_ROM_PTR(&pin_P0_22) }, + { MP_ROM_QSTR(MP_QSTR_C5), MP_ROM_PTR(&pin_P0_23) }, + { MP_ROM_QSTR(MP_QSTR_C6), MP_ROM_PTR(&pin_P0_24) }, + { MP_ROM_QSTR(MP_QSTR_C7), MP_ROM_PTR(&pin_P0_25) }, + { MP_ROM_QSTR(MP_QSTR_C8), MP_ROM_PTR(&pin_P0_26) }, + + { MP_ROM_QSTR(MP_QSTR_TXD), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_RXD), MP_ROM_PTR(&pin_P0_15) }, + + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_P1_06) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_P1_05) }, + + { MP_ROM_QSTR(MP_QSTR_LED_R), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_P0_31) }, + + { MP_ROM_QSTR(MP_QSTR_BTN), MP_ROM_PTR(&pin_P0_27) }, // { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, - { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) } + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) } }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/board.c b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/board.c index 569106ec2..51e453c1f 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/board.c +++ b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/board.c @@ -48,11 +48,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_P0_11, &pin_P0_12, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -63,7 +63,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c index 189286833..a8eaab092 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/pins.c @@ -4,112 +4,112 @@ #include "shared-module/displayio/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_AIN0), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_AIN1), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_AIN2), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_AIN3), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_AIN4), MP_ROM_PTR(&pin_P0_28) }, - { MP_ROM_QSTR(MP_QSTR_AIN5), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_AIN6), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_AIN7), MP_ROM_PTR(&pin_P0_31) }, - - { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, - - { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, - - { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_06) }, - { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_07) }, - { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_08) }, - { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_10) }, - { MP_ROM_QSTR(MP_QSTR_P11), MP_ROM_PTR(&pin_P0_11) }, - { MP_ROM_QSTR(MP_QSTR_P12), MP_ROM_PTR(&pin_P0_12) }, - { MP_ROM_QSTR(MP_QSTR_P13), MP_ROM_PTR(&pin_P0_13) }, - { MP_ROM_QSTR(MP_QSTR_P14), MP_ROM_PTR(&pin_P0_14) }, - { MP_ROM_QSTR(MP_QSTR_P15), MP_ROM_PTR(&pin_P0_15) }, - { MP_ROM_QSTR(MP_QSTR_P16), MP_ROM_PTR(&pin_P0_16) }, - { MP_ROM_QSTR(MP_QSTR_P17), MP_ROM_PTR(&pin_P0_17) }, - { MP_ROM_QSTR(MP_QSTR_P18), MP_ROM_PTR(&pin_P0_18) }, - { MP_ROM_QSTR(MP_QSTR_P19), MP_ROM_PTR(&pin_P0_19) }, - { MP_ROM_QSTR(MP_QSTR_P20), MP_ROM_PTR(&pin_P0_20) }, - { MP_ROM_QSTR(MP_QSTR_P21), MP_ROM_PTR(&pin_P0_21) }, - { MP_ROM_QSTR(MP_QSTR_P25), MP_ROM_PTR(&pin_P0_25) }, - { MP_ROM_QSTR(MP_QSTR_P26), MP_ROM_PTR(&pin_P0_26) }, - { MP_ROM_QSTR(MP_QSTR_P27), MP_ROM_PTR(&pin_P0_27) }, - { MP_ROM_QSTR(MP_QSTR_P28), MP_ROM_PTR(&pin_P0_28) }, - { MP_ROM_QSTR(MP_QSTR_P29), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_P30), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_P31), MP_ROM_PTR(&pin_P0_31) }, - - { MP_ROM_QSTR(MP_QSTR_P1_0), MP_ROM_PTR(&pin_P1_00) }, - { MP_ROM_QSTR(MP_QSTR_P1_1), MP_ROM_PTR(&pin_P1_01) }, - { MP_ROM_QSTR(MP_QSTR_P1_2), MP_ROM_PTR(&pin_P1_02) }, - { MP_ROM_QSTR(MP_QSTR_P1_3), MP_ROM_PTR(&pin_P1_03) }, - { MP_ROM_QSTR(MP_QSTR_P1_4), MP_ROM_PTR(&pin_P1_04) }, - { MP_ROM_QSTR(MP_QSTR_P1_5), MP_ROM_PTR(&pin_P1_05) }, - { MP_ROM_QSTR(MP_QSTR_P1_6), MP_ROM_PTR(&pin_P1_06) }, - { MP_ROM_QSTR(MP_QSTR_P1_7), MP_ROM_PTR(&pin_P1_07) }, - { MP_ROM_QSTR(MP_QSTR_P1_8), MP_ROM_PTR(&pin_P1_08) }, - { MP_ROM_QSTR(MP_QSTR_P1_9), MP_ROM_PTR(&pin_P1_09) }, - - { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_P0_15) }, - { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_P0_15) }, - - { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_P0_16) }, - { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_P0_16) }, - - { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_P0_19) }, - { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_P0_20) }, - { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_P0_21) }, - { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_P0_22) }, - { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_P0_23) }, - { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_P0_24) }, - { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_P1_00) }, - { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_P1_01) }, - { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_P1_02) }, - { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_P1_03) }, - { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_P1_04) }, - { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_P1_07) }, - - { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_P1_05) }, - { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_P1_05) }, - - { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_P1_06) }, - { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_P1_06) }, - - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_P0_28) }, - { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_P0_27) }, - { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_P0_26) }, - { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_P0_04) }, - - { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P0_11) }, - { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_P0_12) }, - { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_P1_08) }, - - { MP_ROM_QSTR(MP_QSTR_LCD_DC), MP_ROM_PTR(&pin_P0_08) }, - { MP_ROM_QSTR(MP_QSTR_LCD_CS), MP_ROM_PTR(&pin_P0_06) }, - { MP_ROM_QSTR(MP_QSTR_LCD_BL), MP_ROM_PTR(&pin_P0_20) }, - { MP_ROM_QSTR(MP_QSTR_LCD_RST), MP_ROM_PTR(&pin_P1_09) }, - - { MP_ROM_QSTR(MP_QSTR_LED_R), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_P0_31) }, - - { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_P0_19) }, - - { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, - { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, - { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, - - { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].display)} + { MP_ROM_QSTR(MP_QSTR_AIN0), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_AIN1), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_AIN2), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_AIN3), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_AIN4), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_AIN5), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_AIN6), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_AIN7), MP_ROM_PTR(&pin_P0_31) }, + + { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, + + { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, + + { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_07) }, + { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_08) }, + { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_P11), MP_ROM_PTR(&pin_P0_11) }, + { MP_ROM_QSTR(MP_QSTR_P12), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_P13), MP_ROM_PTR(&pin_P0_13) }, + { MP_ROM_QSTR(MP_QSTR_P14), MP_ROM_PTR(&pin_P0_14) }, + { MP_ROM_QSTR(MP_QSTR_P15), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_P16), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_P17), MP_ROM_PTR(&pin_P0_17) }, + { MP_ROM_QSTR(MP_QSTR_P18), MP_ROM_PTR(&pin_P0_18) }, + { MP_ROM_QSTR(MP_QSTR_P19), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_P20), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_P21), MP_ROM_PTR(&pin_P0_21) }, + { MP_ROM_QSTR(MP_QSTR_P25), MP_ROM_PTR(&pin_P0_25) }, + { MP_ROM_QSTR(MP_QSTR_P26), MP_ROM_PTR(&pin_P0_26) }, + { MP_ROM_QSTR(MP_QSTR_P27), MP_ROM_PTR(&pin_P0_27) }, + { MP_ROM_QSTR(MP_QSTR_P28), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_P29), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_P30), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_P31), MP_ROM_PTR(&pin_P0_31) }, + + { MP_ROM_QSTR(MP_QSTR_P1_0), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_P1_1), MP_ROM_PTR(&pin_P1_01) }, + { MP_ROM_QSTR(MP_QSTR_P1_2), MP_ROM_PTR(&pin_P1_02) }, + { MP_ROM_QSTR(MP_QSTR_P1_3), MP_ROM_PTR(&pin_P1_03) }, + { MP_ROM_QSTR(MP_QSTR_P1_4), MP_ROM_PTR(&pin_P1_04) }, + { MP_ROM_QSTR(MP_QSTR_P1_5), MP_ROM_PTR(&pin_P1_05) }, + { MP_ROM_QSTR(MP_QSTR_P1_6), MP_ROM_PTR(&pin_P1_06) }, + { MP_ROM_QSTR(MP_QSTR_P1_7), MP_ROM_PTR(&pin_P1_07) }, + { MP_ROM_QSTR(MP_QSTR_P1_8), MP_ROM_PTR(&pin_P1_08) }, + { MP_ROM_QSTR(MP_QSTR_P1_9), MP_ROM_PTR(&pin_P1_09) }, + + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_P0_15) }, + + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_P0_16) }, + + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_P0_21) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_P0_22) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_P0_23) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_P0_24) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_P1_01) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_P1_02) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_P1_03) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_P1_04) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_P1_07) }, + + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_P1_05) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_P1_05) }, + + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_P1_06) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_P1_06) }, + + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_P0_27) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_P0_26) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_P0_04) }, + + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P0_11) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_P1_08) }, + + { MP_ROM_QSTR(MP_QSTR_LCD_DC), MP_ROM_PTR(&pin_P0_08) }, + { MP_ROM_QSTR(MP_QSTR_LCD_CS), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_LCD_BL), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_LCD_RST), MP_ROM_PTR(&pin_P1_09) }, + + { MP_ROM_QSTR(MP_QSTR_LED_R), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_P0_31) }, + + { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_P0_19) }, + + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + + { MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].display)} }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/nrf/boards/makerdiary_nrf52840_mdk/board.c b/ports/nrf/boards/makerdiary_nrf52840_mdk/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_mdk/board.c +++ b/ports/nrf/boards/makerdiary_nrf52840_mdk/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c b/ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c index 34f487b1d..bd0e6e480 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_mdk/pins.c @@ -1,61 +1,61 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_AIN0), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_AIN1), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_AIN2), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_AIN3), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_AIN4), MP_ROM_PTR(&pin_P0_28) }, - { MP_ROM_QSTR(MP_QSTR_AIN5), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_AIN6), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_AIN7), MP_ROM_PTR(&pin_P0_31) }, - - { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, - - { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, - - { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_06) }, - { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_07) }, - { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_08) }, - { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_10) }, - { MP_ROM_QSTR(MP_QSTR_P11), MP_ROM_PTR(&pin_P0_11) }, - { MP_ROM_QSTR(MP_QSTR_P12), MP_ROM_PTR(&pin_P0_12) }, - { MP_ROM_QSTR(MP_QSTR_P13), MP_ROM_PTR(&pin_P0_13) }, - { MP_ROM_QSTR(MP_QSTR_P14), MP_ROM_PTR(&pin_P0_14) }, - { MP_ROM_QSTR(MP_QSTR_P15), MP_ROM_PTR(&pin_P0_15) }, - { MP_ROM_QSTR(MP_QSTR_P16), MP_ROM_PTR(&pin_P0_16) }, - { MP_ROM_QSTR(MP_QSTR_P17), MP_ROM_PTR(&pin_P0_17) }, - { MP_ROM_QSTR(MP_QSTR_P21), MP_ROM_PTR(&pin_P0_21) }, - { MP_ROM_QSTR(MP_QSTR_P25), MP_ROM_PTR(&pin_P0_25) }, - { MP_ROM_QSTR(MP_QSTR_P26), MP_ROM_PTR(&pin_P0_26) }, - { MP_ROM_QSTR(MP_QSTR_P27), MP_ROM_PTR(&pin_P0_27) }, - { MP_ROM_QSTR(MP_QSTR_P28), MP_ROM_PTR(&pin_P0_28) }, - { MP_ROM_QSTR(MP_QSTR_P29), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_P30), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_P31), MP_ROM_PTR(&pin_P0_31) }, - - { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P1_03) }, - { MP_ROM_QSTR(MP_QSTR_CSN), MP_ROM_PTR(&pin_P1_06) }, - { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_P1_05) }, - { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_P1_04) }, - { MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_P1_02) }, - { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_P1_01) }, - - { MP_ROM_QSTR(MP_QSTR_TXD), MP_ROM_PTR(&pin_P0_20) }, - { MP_ROM_QSTR(MP_QSTR_RXD), MP_ROM_PTR(&pin_P0_19) }, - - { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_P0_23) }, - { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_P0_22) }, - { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_P0_24) }, - - { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_AIN0), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_AIN1), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_AIN2), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_AIN3), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_AIN4), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_AIN5), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_AIN6), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_AIN7), MP_ROM_PTR(&pin_P0_31) }, + + { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, + + { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, + + { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_07) }, + { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_08) }, + { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_P11), MP_ROM_PTR(&pin_P0_11) }, + { MP_ROM_QSTR(MP_QSTR_P12), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_P13), MP_ROM_PTR(&pin_P0_13) }, + { MP_ROM_QSTR(MP_QSTR_P14), MP_ROM_PTR(&pin_P0_14) }, + { MP_ROM_QSTR(MP_QSTR_P15), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_P16), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_P17), MP_ROM_PTR(&pin_P0_17) }, + { MP_ROM_QSTR(MP_QSTR_P21), MP_ROM_PTR(&pin_P0_21) }, + { MP_ROM_QSTR(MP_QSTR_P25), MP_ROM_PTR(&pin_P0_25) }, + { MP_ROM_QSTR(MP_QSTR_P26), MP_ROM_PTR(&pin_P0_26) }, + { MP_ROM_QSTR(MP_QSTR_P27), MP_ROM_PTR(&pin_P0_27) }, + { MP_ROM_QSTR(MP_QSTR_P28), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_P29), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_P30), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_P31), MP_ROM_PTR(&pin_P0_31) }, + + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P1_03) }, + { MP_ROM_QSTR(MP_QSTR_CSN), MP_ROM_PTR(&pin_P1_06) }, + { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_P1_05) }, + { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_P1_04) }, + { MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_P1_02) }, + { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_P1_01) }, + + { MP_ROM_QSTR(MP_QSTR_TXD), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_RXD), MP_ROM_PTR(&pin_P0_19) }, + + { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_P0_23) }, + { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_P0_22) }, + { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_P0_24) }, + + { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_P1_00) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/board.c b/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/board.c +++ b/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c b/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c index d46f36942..05813bd04 100644 --- a/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c +++ b/ports/nrf/boards/makerdiary_nrf52840_mdk_usb_dongle/pins.c @@ -1,38 +1,38 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_AIN0), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_AIN1), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_AIN2), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_AIN3), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_AIN0), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_AIN1), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_AIN2), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_AIN3), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, // User must connect manually. - { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, // User must connect manually. + { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, // User must connect manually. + { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, // User must connect manually. - { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, - { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_06) }, - { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_07) }, - { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_08) }, - { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_10) }, - { MP_ROM_QSTR(MP_QSTR_P18), MP_ROM_PTR(&pin_P0_18) }, // !Reset button. - { MP_ROM_QSTR(MP_QSTR_P19), MP_ROM_PTR(&pin_P0_19) }, - { MP_ROM_QSTR(MP_QSTR_P22), MP_ROM_PTR(&pin_P0_22) }, // green led, low is on. - { MP_ROM_QSTR(MP_QSTR_P23), MP_ROM_PTR(&pin_P0_23) }, // red led, low is on. - { MP_ROM_QSTR(MP_QSTR_P24), MP_ROM_PTR(&pin_P0_24) }, // blue led, low is on. + { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_07) }, + { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_08) }, + { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_P18), MP_ROM_PTR(&pin_P0_18) }, // !Reset button. + { MP_ROM_QSTR(MP_QSTR_P19), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_P22), MP_ROM_PTR(&pin_P0_22) }, // green led, low is on. + { MP_ROM_QSTR(MP_QSTR_P23), MP_ROM_PTR(&pin_P0_23) }, // red led, low is on. + { MP_ROM_QSTR(MP_QSTR_P24), MP_ROM_PTR(&pin_P0_24) }, // blue led, low is on. - { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_P0_23) }, // Low is on. - { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_P0_22) }, // Low is on. - { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_P0_24) }, // Low is on. + { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_P0_23) }, // Low is on. + { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_P0_22) }, // Low is on. + { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_P0_24) }, // Low is on. - // BUT this is the RESET pin so we can't really use it. - { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_P0_18) }, // Low is pressed. + // BUT this is the RESET pin so we can't really use it. + { MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_P0_18) }, // Low is pressed. }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/nrf/boards/metro_nrf52840_express/board.c b/ports/nrf/boards/metro_nrf52840_express/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/metro_nrf52840_express/board.c +++ b/ports/nrf/boards/metro_nrf52840_express/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/nice_nano/board.c b/ports/nrf/boards/nice_nano/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/nice_nano/board.c +++ b/ports/nrf/boards/nice_nano/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/nice_nano/mpconfigboard.h b/ports/nrf/boards/nice_nano/mpconfigboard.h index 5f6194700..fd605e12f 100644 --- a/ports/nrf/boards/nice_nano/mpconfigboard.h +++ b/ports/nrf/boards/nice_nano/mpconfigboard.h @@ -34,12 +34,12 @@ #define BOARD_HAS_CRYSTAL 1 -#define DEFAULT_I2C_BUS_SCL (&pin_P0_20) -#define DEFAULT_I2C_BUS_SDA (&pin_P0_17) +#define DEFAULT_I2C_BUS_SCL (&pin_P0_20) +#define DEFAULT_I2C_BUS_SDA (&pin_P0_17) -#define DEFAULT_SPI_BUS_SCK (&pin_P1_13) -#define DEFAULT_SPI_BUS_MOSI (&pin_P0_10) -#define DEFAULT_SPI_BUS_MISO (&pin_P1_11) +#define DEFAULT_SPI_BUS_SCK (&pin_P1_13) +#define DEFAULT_SPI_BUS_MOSI (&pin_P0_10) +#define DEFAULT_SPI_BUS_MISO (&pin_P1_11) -#define DEFAULT_UART_BUS_RX (&pin_P0_08) -#define DEFAULT_UART_BUS_TX (&pin_P0_06) +#define DEFAULT_UART_BUS_RX (&pin_P0_08) +#define DEFAULT_UART_BUS_TX (&pin_P0_06) diff --git a/ports/nrf/boards/nrf52_prefix.c b/ports/nrf/boards/nrf52_prefix.c index 0c96eb61e..92fb165b5 100644 --- a/ports/nrf/boards/nrf52_prefix.c +++ b/ports/nrf/boards/nrf52_prefix.c @@ -7,10 +7,10 @@ #include "nrf_pin.h" #define PIN(p_name, p_port, p_pin, p_adc_channel) \ -{ \ - { &mcu_pin_type }, \ - .name = MP_QSTR_ ## p_name, \ - .port = (p_port), \ - .pin = (p_pin), \ - .adc_channel = (p_adc_channel), \ -} + { \ + { &mcu_pin_type }, \ + .name = MP_QSTR_##p_name, \ + .port = (p_port), \ + .pin = (p_pin), \ + .adc_channel = (p_adc_channel), \ + } diff --git a/ports/nrf/boards/ohs2020_badge/board.c b/ports/nrf/boards/ohs2020_badge/board.c index 20abf4e2a..1522e45c9 100644 --- a/ports/nrf/boards/ohs2020_badge/board.c +++ b/ports/nrf/boards/ohs2020_badge/board.c @@ -47,11 +47,11 @@ uint8_t display_init_sequence[] = { }; void board_init(void) { - busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus; + busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus; common_hal_busio_spi_construct(spi, &pin_P0_11, &pin_P0_12, NULL); common_hal_busio_spi_never_reset(spi); - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; common_hal_displayio_fourwire_construct(bus, spi, @@ -62,7 +62,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/nrf/boards/particle_argon/board.c b/ports/nrf/boards/particle_argon/board.c index a41f0ae06..94ee5d695 100644 --- a/ports/nrf/boards/particle_argon/board.c +++ b/ports/nrf/boards/particle_argon/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/particle_boron/board.c b/ports/nrf/boards/particle_boron/board.c index a41f0ae06..94ee5d695 100644 --- a/ports/nrf/boards/particle_boron/board.c +++ b/ports/nrf/boards/particle_boron/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/particle_xenon/board.c b/ports/nrf/boards/particle_xenon/board.c index a41f0ae06..94ee5d695 100644 --- a/ports/nrf/boards/particle_xenon/board.c +++ b/ports/nrf/boards/particle_xenon/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/pca10056/board.c b/ports/nrf/boards/pca10056/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/pca10056/board.c +++ b/ports/nrf/boards/pca10056/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/pca10056/examples/buttons.py b/ports/nrf/boards/pca10056/examples/buttons.py index 1a0c5aabb..4db357697 100644 --- a/ports/nrf/boards/pca10056/examples/buttons.py +++ b/ports/nrf/boards/pca10056/examples/buttons.py @@ -17,9 +17,9 @@ while True: if buttons != prev_buttons: for i in range(0, 4): - bit = (1 << i) + bit = 1 << i if (buttons & bit) != (prev_buttons & bit): - print('Button %d %s' % (i + 1, 'pressed' if buttons & bit else 'released')) + print("Button %d %s" % (i + 1, "pressed" if buttons & bit else "released")) prev_buttons = buttons diff --git a/ports/nrf/boards/pca10059/board.c b/ports/nrf/boards/pca10059/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/pca10059/board.c +++ b/ports/nrf/boards/pca10059/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/pca10100/board.c b/ports/nrf/boards/pca10100/board.c index a41f0ae06..94ee5d695 100644 --- a/ports/nrf/boards/pca10100/board.c +++ b/ports/nrf/boards/pca10100/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/pca10100/mpconfigboard.h b/ports/nrf/boards/pca10100/mpconfigboard.h index 4639a208b..00c10fc25 100644 --- a/ports/nrf/boards/pca10100/mpconfigboard.h +++ b/ports/nrf/boards/pca10100/mpconfigboard.h @@ -35,9 +35,9 @@ #define MICROPY_HW_LED_RX (&pin_P0_15) #define CIRCUITPY_INTERNAL_NVM_SIZE 0 -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (60*1024) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (60 * 1024) -#define CIRCUITPY_BLE_CONFIG_SIZE (12*1024) +#define CIRCUITPY_BLE_CONFIG_SIZE (12 * 1024) // Reduce nRF SoftRadio memory usage #define BLEIO_VS_UUID_COUNT 10 @@ -47,4 +47,4 @@ #define BLEIO_TOTAL_CONNECTION_COUNT 2 #define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 2) -#define SOFTDEVICE_RAM_SIZE (32*1024) +#define SOFTDEVICE_RAM_SIZE (32 * 1024) diff --git a/ports/nrf/boards/pitaya_go/board.c b/ports/nrf/boards/pitaya_go/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/pitaya_go/board.c +++ b/ports/nrf/boards/pitaya_go/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/pitaya_go/pins.c b/ports/nrf/boards/pitaya_go/pins.c index ba333fc2b..c0f2976a5 100644 --- a/ports/nrf/boards/pitaya_go/pins.c +++ b/ports/nrf/boards/pitaya_go/pins.c @@ -1,64 +1,64 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_AIN0), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_AIN1), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_AIN2), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_AIN3), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_AIN4), MP_ROM_PTR(&pin_P0_28) }, - { MP_ROM_QSTR(MP_QSTR_AIN5), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_AIN6), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_AIN7), MP_ROM_PTR(&pin_P0_31) }, + { MP_ROM_QSTR(MP_QSTR_AIN0), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_AIN1), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_AIN2), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_AIN3), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_AIN4), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_AIN5), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_AIN6), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_AIN7), MP_ROM_PTR(&pin_P0_31) }, - { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_AREF), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_VDIV), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_NFC1), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_NFC2), MP_ROM_PTR(&pin_P0_10) }, - { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_06) }, - { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_07) }, - { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_08) }, - { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_10) }, - { MP_ROM_QSTR(MP_QSTR_P11), MP_ROM_PTR(&pin_P0_11) }, - { MP_ROM_QSTR(MP_QSTR_P12), MP_ROM_PTR(&pin_P0_12) }, - { MP_ROM_QSTR(MP_QSTR_P13), MP_ROM_PTR(&pin_P0_13) }, - { MP_ROM_QSTR(MP_QSTR_P14), MP_ROM_PTR(&pin_P0_14) }, - { MP_ROM_QSTR(MP_QSTR_P15), MP_ROM_PTR(&pin_P0_15) }, - { MP_ROM_QSTR(MP_QSTR_P16), MP_ROM_PTR(&pin_P0_16) }, - { MP_ROM_QSTR(MP_QSTR_P17), MP_ROM_PTR(&pin_P0_17) }, - { MP_ROM_QSTR(MP_QSTR_P18), MP_ROM_PTR(&pin_P0_18) }, - { MP_ROM_QSTR(MP_QSTR_P19), MP_ROM_PTR(&pin_P0_19) }, - { MP_ROM_QSTR(MP_QSTR_P20), MP_ROM_PTR(&pin_P0_20) }, - { MP_ROM_QSTR(MP_QSTR_P21), MP_ROM_PTR(&pin_P0_21) }, - { MP_ROM_QSTR(MP_QSTR_P22), MP_ROM_PTR(&pin_P0_22) }, - { MP_ROM_QSTR(MP_QSTR_P23), MP_ROM_PTR(&pin_P0_23) }, - { MP_ROM_QSTR(MP_QSTR_P24), MP_ROM_PTR(&pin_P0_24) }, - { MP_ROM_QSTR(MP_QSTR_P25), MP_ROM_PTR(&pin_P0_25) }, - { MP_ROM_QSTR(MP_QSTR_P26), MP_ROM_PTR(&pin_P0_26) }, - { MP_ROM_QSTR(MP_QSTR_P27), MP_ROM_PTR(&pin_P0_27) }, - { MP_ROM_QSTR(MP_QSTR_P28), MP_ROM_PTR(&pin_P0_28) }, - { MP_ROM_QSTR(MP_QSTR_P29), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_P30), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_P31), MP_ROM_PTR(&pin_P0_31) }, + { MP_ROM_QSTR(MP_QSTR_P2), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_P3), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_P0_07) }, + { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_P0_08) }, + { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_P10), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_P11), MP_ROM_PTR(&pin_P0_11) }, + { MP_ROM_QSTR(MP_QSTR_P12), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_P13), MP_ROM_PTR(&pin_P0_13) }, + { MP_ROM_QSTR(MP_QSTR_P14), MP_ROM_PTR(&pin_P0_14) }, + { MP_ROM_QSTR(MP_QSTR_P15), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_P16), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_P17), MP_ROM_PTR(&pin_P0_17) }, + { MP_ROM_QSTR(MP_QSTR_P18), MP_ROM_PTR(&pin_P0_18) }, + { MP_ROM_QSTR(MP_QSTR_P19), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_P20), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_P21), MP_ROM_PTR(&pin_P0_21) }, + { MP_ROM_QSTR(MP_QSTR_P22), MP_ROM_PTR(&pin_P0_22) }, + { MP_ROM_QSTR(MP_QSTR_P23), MP_ROM_PTR(&pin_P0_23) }, + { MP_ROM_QSTR(MP_QSTR_P24), MP_ROM_PTR(&pin_P0_24) }, + { MP_ROM_QSTR(MP_QSTR_P25), MP_ROM_PTR(&pin_P0_25) }, + { MP_ROM_QSTR(MP_QSTR_P26), MP_ROM_PTR(&pin_P0_26) }, + { MP_ROM_QSTR(MP_QSTR_P27), MP_ROM_PTR(&pin_P0_27) }, + { MP_ROM_QSTR(MP_QSTR_P28), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_P29), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_P30), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_P31), MP_ROM_PTR(&pin_P0_31) }, - { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P1_04) }, - { MP_ROM_QSTR(MP_QSTR_CSN), MP_ROM_PTR(&pin_P1_03) }, - { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_P1_06) }, - { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_P1_01) }, - { MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_P1_05) }, - { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_P1_02) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_P1_04) }, + { MP_ROM_QSTR(MP_QSTR_CSN), MP_ROM_PTR(&pin_P1_03) }, + { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_P1_06) }, + { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_P1_01) }, + { MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_P1_05) }, + { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_P1_02) }, - { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_P0_10) }, - { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_P0_11) }, - { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_P0_11) }, + { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_P0_12) }, - { MP_ROM_QSTR(MP_QSTR_BUTTON_USER), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON_USER), MP_ROM_PTR(&pin_P1_00) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/nrf/boards/raytac_mdbt50q-db-40/board.c b/ports/nrf/boards/raytac_mdbt50q-db-40/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/raytac_mdbt50q-db-40/board.c +++ b/ports/nrf/boards/raytac_mdbt50q-db-40/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/simmel/board.c b/ports/nrf/boards/simmel/board.c index a41f0ae06..94ee5d695 100644 --- a/ports/nrf/boards/simmel/board.c +++ b/ports/nrf/boards/simmel/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/simmel/mpconfigboard.h b/ports/nrf/boards/simmel/mpconfigboard.h index a89f540b0..9361e8ef2 100644 --- a/ports/nrf/boards/simmel/mpconfigboard.h +++ b/ports/nrf/boards/simmel/mpconfigboard.h @@ -40,10 +40,10 @@ #endif #define CIRCUITPY_INTERNAL_NVM_SIZE 0 -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (76*1024) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (76 * 1024) #define BOOTLOADER_SIZE (0x4000) // 12 kiB -#define CIRCUITPY_BLE_CONFIG_SIZE (12*1024) +#define CIRCUITPY_BLE_CONFIG_SIZE (12 * 1024) #define DEFAULT_I2C_BUS_SCL (&pin_P0_08) #define DEFAULT_I2C_BUS_SDA (&pin_P1_09) @@ -56,4 +56,4 @@ #define BLEIO_TOTAL_CONNECTION_COUNT 2 #define BLEIO_ATTR_TAB_SIZE (BLE_GATTS_ATTR_TAB_SIZE_DEFAULT * 2) -#define SOFTDEVICE_RAM_SIZE (32*1024) +#define SOFTDEVICE_RAM_SIZE (32 * 1024) diff --git a/ports/nrf/boards/sparkfun_nrf52840_micromod/board.c b/ports/nrf/boards/sparkfun_nrf52840_micromod/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/sparkfun_nrf52840_micromod/board.c +++ b/ports/nrf/boards/sparkfun_nrf52840_micromod/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/sparkfun_nrf52840_mini/board.c b/ports/nrf/boards/sparkfun_nrf52840_mini/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/sparkfun_nrf52840_mini/board.c +++ b/ports/nrf/boards/sparkfun_nrf52840_mini/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/sparkfun_nrf52840_mini/pins.c b/ports/nrf/boards/sparkfun_nrf52840_mini/pins.c index e7b61db58..026b566ef 100644 --- a/ports/nrf/boards/sparkfun_nrf52840_mini/pins.c +++ b/ports/nrf/boards/sparkfun_nrf52840_mini/pins.c @@ -3,7 +3,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_P1_15) }, // D1/TX { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_P0_17) }, // D0/RX - // D2 on qwiic gap + // D2 on qwiic gap { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_P0_19) }, // D3 { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_P0_20) }, // D4 { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_P0_21) }, // D5 diff --git a/ports/nrf/boards/teknikio_bluebird/board.c b/ports/nrf/boards/teknikio_bluebird/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/teknikio_bluebird/board.c +++ b/ports/nrf/boards/teknikio_bluebird/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/boards/teknikio_bluebird/mpconfigboard.h b/ports/nrf/boards/teknikio_bluebird/mpconfigboard.h index c130cd8c0..8ddeeb72a 100644 --- a/ports/nrf/boards/teknikio_bluebird/mpconfigboard.h +++ b/ports/nrf/boards/teknikio_bluebird/mpconfigboard.h @@ -25,7 +25,7 @@ * THE SOFTWARE. */ -//https://github.com/Teknikio/TKInventionBuilderFramework +// https://github.com/Teknikio/TKInventionBuilderFramework #include "nrfx/hal/nrf_gpio.h" diff --git a/ports/nrf/boards/tinkeringtech_scoutmakes_azul/board.c b/ports/nrf/boards/tinkeringtech_scoutmakes_azul/board.c index 781793328..688cfb4de 100644 --- a/ports/nrf/boards/tinkeringtech_scoutmakes_azul/board.c +++ b/ports/nrf/boards/tinkeringtech_scoutmakes_azul/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/nrf/common-hal/_bleio/Adapter.c b/ports/nrf/common-hal/_bleio/Adapter.c index 10794c16a..ca21222b5 100644 --- a/ports/nrf/common-hal/_bleio/Adapter.c +++ b/ports/nrf/common-hal/_bleio/Adapter.c @@ -80,7 +80,7 @@ const nvm_bytearray_obj_t common_hal_bleio_nvm_obj = { .base = { .type = &nvm_bytearray_type, }, - .start_address = (uint8_t*) CIRCUITPY_BLE_CONFIG_START_ADDR, + .start_address = (uint8_t *)CIRCUITPY_BLE_CONFIG_START_ADDR, .len = CIRCUITPY_BLE_CONFIG_SIZE, }; @@ -94,17 +94,17 @@ bleio_connection_internal_t bleio_connections[BLEIO_TOTAL_CONNECTION_COUNT]; extern uint32_t _ram_start; STATIC uint32_t ble_stack_enable(void) { nrf_clock_lf_cfg_t clock_config = { -#if BOARD_HAS_32KHZ_XTAL - .source = NRF_CLOCK_LF_SRC_XTAL, - .rc_ctiv = 0, + #if BOARD_HAS_32KHZ_XTAL + .source = NRF_CLOCK_LF_SRC_XTAL, + .rc_ctiv = 0, .rc_temp_ctiv = 0, - .accuracy = NRF_CLOCK_LF_ACCURACY_20_PPM, -#else - .source = NRF_CLOCK_LF_SRC_RC, - .rc_ctiv = 16, + .accuracy = NRF_CLOCK_LF_ACCURACY_20_PPM, + #else + .source = NRF_CLOCK_LF_SRC_RC, + .rc_ctiv = 16, .rc_temp_ctiv = 2, - .accuracy = NRF_CLOCK_LF_ACCURACY_250_PPM, -#endif + .accuracy = NRF_CLOCK_LF_ACCURACY_250_PPM, + #endif }; uint32_t err_code = sd_softdevice_enable(&clock_config, softdevice_assert_handler); @@ -211,20 +211,20 @@ STATIC uint32_t ble_stack_enable(void) { ble_gap_conn_params_t gap_conn_params = { .min_conn_interval = BLE_MIN_CONN_INTERVAL, .max_conn_interval = BLE_MAX_CONN_INTERVAL, - .slave_latency = BLE_SLAVE_LATENCY, - .conn_sup_timeout = BLE_CONN_SUP_TIMEOUT, + .slave_latency = BLE_SLAVE_LATENCY, + .conn_sup_timeout = BLE_CONN_SUP_TIMEOUT, }; - err_code = sd_ble_gap_ppcp_set(&gap_conn_params); - if (err_code != NRF_SUCCESS) { - return err_code; - } + err_code = sd_ble_gap_ppcp_set(&gap_conn_params); + if (err_code != NRF_SUCCESS) { + return err_code; + } - err_code = sd_ble_gap_appearance_set(BLE_APPEARANCE_UNKNOWN); - return err_code; + err_code = sd_ble_gap_appearance_set(BLE_APPEARANCE_UNKNOWN); + return err_code; } STATIC bool adapter_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { - bleio_adapter_obj_t *self = (bleio_adapter_obj_t*)self_in; + bleio_adapter_obj_t *self = (bleio_adapter_obj_t *)self_in; // For debugging. // mp_printf(&mp_plat_print, "Adapter event: 0x%04x\n", ble_evt->header.evt_id); @@ -242,7 +242,7 @@ STATIC bool adapter_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { } // Central has connected. - ble_gap_evt_connected_t* connected = &ble_evt->evt.gap_evt.params.connected; + ble_gap_evt_connected_t *connected = &ble_evt->evt.gap_evt.params.connected; connection->conn_handle = ble_evt->evt.gap_evt.conn_handle; connection->connection_obj = mp_const_none; @@ -284,7 +284,7 @@ STATIC bool adapter_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { connection->conn_handle = BLE_CONN_HANDLE_INVALID; connection->pair_status = PAIR_NOT_PAIRED; if (connection->connection_obj != mp_const_none) { - bleio_connection_obj_t* obj = connection->connection_obj; + bleio_connection_obj_t *obj = connection->connection_obj; obj->connection = NULL; obj->disconnect_reason = ble_evt->evt.gap_evt.params.disconnected.reason; } @@ -310,7 +310,7 @@ STATIC void get_address(bleio_adapter_obj_t *self, ble_gap_addr_t *address) { check_nrf_error(sd_ble_gap_addr_get(address)); } -char default_ble_name[] = { 'C', 'I', 'R', 'C', 'U', 'I', 'T', 'P', 'Y', 0, 0, 0, 0 , 0}; +char default_ble_name[] = { 'C', 'I', 'R', 'C', 'U', 'I', 'T', 'P', 'Y', 0, 0, 0, 0, 0}; STATIC void bleio_adapter_reset_name(bleio_adapter_obj_t *self) { uint8_t len = sizeof(default_ble_name) - 1; @@ -324,7 +324,7 @@ STATIC void bleio_adapter_reset_name(bleio_adapter_obj_t *self) { default_ble_name[len - 1] = nibble_to_hex_lower[local_address.addr[0] & 0xf]; default_ble_name[len] = '\0'; // for now we add null for compatibility with C ASCIIZ strings - common_hal_bleio_adapter_set_name(self, (char*) default_ble_name); + common_hal_bleio_adapter_set_name(self, (char *)default_ble_name); } void common_hal_bleio_adapter_set_enabled(bleio_adapter_obj_t *self, bool enabled) { @@ -401,7 +401,7 @@ bool common_hal_bleio_adapter_set_address(bleio_adapter_obj_t *self, bleio_addre return sd_ble_gap_addr_set(&local_address) == NRF_SUCCESS; } -mp_obj_str_t* common_hal_bleio_adapter_get_name(bleio_adapter_obj_t *self) { +mp_obj_str_t *common_hal_bleio_adapter_get_name(bleio_adapter_obj_t *self) { uint16_t len = 0; sd_ble_gap_device_name_get(NULL, &len); uint8_t buf[len]; @@ -409,18 +409,18 @@ mp_obj_str_t* common_hal_bleio_adapter_get_name(bleio_adapter_obj_t *self) { if (err_code != NRF_SUCCESS) { return NULL; } - return mp_obj_new_str((char*) buf, len); + return mp_obj_new_str((char *)buf, len); } -void common_hal_bleio_adapter_set_name(bleio_adapter_obj_t *self, const char* name) { +void common_hal_bleio_adapter_set_name(bleio_adapter_obj_t *self, const char *name) { ble_gap_conn_sec_mode_t sec; sec.lv = 0; sec.sm = 0; - sd_ble_gap_device_name_set(&sec, (const uint8_t*) name, strlen(name)); + sd_ble_gap_device_name_set(&sec, (const uint8_t *)name, strlen(name)); } STATIC bool scan_on_ble_evt(ble_evt_t *ble_evt, void *scan_results_in) { - bleio_scanresults_obj_t *scan_results = (bleio_scanresults_obj_t*)scan_results_in; + bleio_scanresults_obj_t *scan_results = (bleio_scanresults_obj_t *)scan_results_in; if (ble_evt->header.evt_id == BLE_GAP_EVT_TIMEOUT && ble_evt->evt.gap_evt.params.timeout.src == BLE_GAP_TIMEOUT_SRC_SCAN) { @@ -435,14 +435,14 @@ STATIC bool scan_on_ble_evt(ble_evt_t *ble_evt, void *scan_results_in) { ble_gap_evt_adv_report_t *report = &ble_evt->evt.gap_evt.params.adv_report; shared_module_bleio_scanresults_append(scan_results, - supervisor_ticks_ms64(), - report->type.connectable, - report->type.scan_response, - report->rssi, - report->peer_addr.addr, - report->peer_addr.addr_type, - report->data.p_data, - report->data.len); + supervisor_ticks_ms64(), + report->type.connectable, + report->type.scan_response, + report->rssi, + report->peer_addr.addr, + report->peer_addr.addr_type, + report->data.p_data, + report->data.len); const uint32_t err_code = sd_ble_gap_scan_start(NULL, scan_results->common_hal_data); if (err_code != NRF_SUCCESS) { @@ -452,7 +452,7 @@ STATIC bool scan_on_ble_evt(ble_evt_t *ble_evt, void *scan_results_in) { return true; } -mp_obj_t common_hal_bleio_adapter_start_scan(bleio_adapter_obj_t *self, uint8_t* prefixes, size_t prefix_length, bool extended, mp_int_t buffer_size, mp_float_t timeout, mp_float_t interval, mp_float_t window, mp_int_t minimum_rssi, bool active) { +mp_obj_t common_hal_bleio_adapter_start_scan(bleio_adapter_obj_t *self, uint8_t *prefixes, size_t prefix_length, bool extended, mp_int_t buffer_size, mp_float_t timeout, mp_float_t interval, mp_float_t window, mp_int_t minimum_rssi, bool active) { if (self->scan_results != NULL) { if (!shared_module_bleio_scanresults_get_done(self->scan_results)) { mp_raise_bleio_BluetoothError(translate("Scan already in progess. Stop with stop_scan.")); @@ -462,7 +462,7 @@ mp_obj_t common_hal_bleio_adapter_start_scan(bleio_adapter_obj_t *self, uint8_t* self->scan_results = shared_module_bleio_new_scanresults(buffer_size, prefixes, prefix_length, minimum_rssi); size_t max_packet_size = extended ? BLE_GAP_SCAN_BUFFER_EXTENDED_MAX_SUPPORTED : BLE_GAP_SCAN_BUFFER_MAX; uint8_t *raw_data = m_malloc(sizeof(ble_data_t) + max_packet_size, false); - ble_data_t * sd_data = (ble_data_t *) raw_data; + ble_data_t *sd_data = (ble_data_t *)raw_data; self->scan_results->common_hal_data = sd_data; sd_data->len = max_packet_size; sd_data->p_data = raw_data + sizeof(ble_data_t); @@ -517,7 +517,7 @@ typedef struct { } connect_info_t; STATIC bool connect_on_ble_evt(ble_evt_t *ble_evt, void *info_in) { - connect_info_t *info = (connect_info_t*)info_in; + connect_info_t *info = (connect_info_t *)info_in; switch (ble_evt->header.evt_id) { case BLE_GAP_EVT_CONNECTED: @@ -546,7 +546,7 @@ mp_obj_t common_hal_bleio_adapter_connect(bleio_adapter_obj_t *self, bleio_addre addr.addr_type = address->type; mp_buffer_info_t address_buf_info; mp_get_buffer_raise(address->bytes, &address_buf_info, MP_BUFFER_READ); - memcpy(addr.addr, (uint8_t *) address_buf_info.buf, NUM_BLEIO_ADDRESS_BYTES); + memcpy(addr.addr, (uint8_t *)address_buf_info.buf, NUM_BLEIO_ADDRESS_BYTES); ble_gap_scan_params_t scan_params = { .interval = MSEC_TO_UNITS(100, UNIT_0_625_MS), @@ -621,7 +621,7 @@ STATIC void check_data_fit(size_t data_len, bool connectable) { } STATIC bool advertising_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { - bleio_adapter_obj_t *self = (bleio_adapter_obj_t*)self_in; + bleio_adapter_obj_t *self = (bleio_adapter_obj_t *)self_in; switch (ble_evt->header.evt_id) { case BLE_GAP_EVT_ADV_SET_TERMINATED: @@ -651,7 +651,7 @@ uint32_t _common_hal_bleio_adapter_start_advertising(bleio_adapter_obj_t *self, uint32_t err_code; bool extended = advertising_data_len > BLE_GAP_ADV_SET_DATA_SIZE_MAX || - scan_response_data_len > BLE_GAP_ADV_SET_DATA_SIZE_MAX; + scan_response_data_len > BLE_GAP_ADV_SET_DATA_SIZE_MAX; uint8_t adv_type; if (extended) { @@ -749,39 +749,39 @@ void common_hal_bleio_adapter_start_advertising(bleio_adapter_obj_t *self, bool uint32_t adv_timeout_max_secs = UNITS_TO_SEC(BLE_GAP_ADV_TIMEOUT_LIMITED_MAX, UNIT_10_MS); uint32_t rotate_timeout_max_secs = BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S; timeout = MIN(adv_timeout_max_secs, rotate_timeout_max_secs); - } - else { + } else { timeout = BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED; } } else { if (SEC_TO_UNITS(timeout, UNIT_10_MS) > BLE_GAP_ADV_TIMEOUT_LIMITED_MAX) { mp_raise_bleio_BluetoothError(translate("Timeout is too long: Maximum timeout length is %d seconds"), - UNITS_TO_SEC(BLE_GAP_ADV_TIMEOUT_LIMITED_MAX, UNIT_10_MS)); + UNITS_TO_SEC(BLE_GAP_ADV_TIMEOUT_LIMITED_MAX, UNIT_10_MS)); } } // The advertising data buffers must not move, because the SoftDevice depends on them. // So make them long-lived and reuse them onwards. if (self->advertising_data == NULL) { - self->advertising_data = (uint8_t *) gc_alloc(BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED * sizeof(uint8_t), false, true); + self->advertising_data = (uint8_t *)gc_alloc(BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED * sizeof(uint8_t), false, true); } if (self->scan_response_data == NULL) { - self->scan_response_data = (uint8_t *) gc_alloc(BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED * sizeof(uint8_t), false, true); + self->scan_response_data = (uint8_t *)gc_alloc(BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED * sizeof(uint8_t), false, true); } memcpy(self->advertising_data, advertising_data_bufinfo->buf, advertising_data_bufinfo->len); memcpy(self->scan_response_data, scan_response_data_bufinfo->buf, scan_response_data_bufinfo->len); check_nrf_error(_common_hal_bleio_adapter_start_advertising(self, connectable, anonymous, timeout, interval, - self->advertising_data, - advertising_data_bufinfo->len, - self->scan_response_data, - scan_response_data_bufinfo->len)); + self->advertising_data, + advertising_data_bufinfo->len, + self->scan_response_data, + scan_response_data_bufinfo->len)); } void common_hal_bleio_adapter_stop_advertising(bleio_adapter_obj_t *self) { - if (adv_handle == BLE_GAP_ADV_SET_HANDLE_NOT_SET) + if (adv_handle == BLE_GAP_ADV_SET_HANDLE_NOT_SET) { return; + } // TODO: Don't actually stop. Switch to advertising CircuitPython if we don't already have a connection. const uint32_t err_code = sd_ble_gap_adv_stop(adv_handle); @@ -830,12 +830,12 @@ void common_hal_bleio_adapter_erase_bonding(bleio_adapter_obj_t *self) { bonding_erase_storage(); } -void bleio_adapter_gc_collect(bleio_adapter_obj_t* adapter) { - gc_collect_root((void**)adapter, sizeof(bleio_adapter_obj_t) / sizeof(size_t)); - gc_collect_root((void**)bleio_connections, sizeof(bleio_connections) / sizeof(size_t)); +void bleio_adapter_gc_collect(bleio_adapter_obj_t *adapter) { + gc_collect_root((void **)adapter, sizeof(bleio_adapter_obj_t) / sizeof(size_t)); + gc_collect_root((void **)bleio_connections, sizeof(bleio_connections) / sizeof(size_t)); } -void bleio_adapter_reset(bleio_adapter_obj_t* adapter) { +void bleio_adapter_reset(bleio_adapter_obj_t *adapter) { common_hal_bleio_adapter_stop_scan(adapter); if (adapter->current_advertising_data != NULL) { common_hal_bleio_adapter_stop_advertising(adapter); diff --git a/ports/nrf/common-hal/_bleio/Adapter.h b/ports/nrf/common-hal/_bleio/Adapter.h index 837e5c111..68a8b4864 100644 --- a/ports/nrf/common-hal/_bleio/Adapter.h +++ b/ports/nrf/common-hal/_bleio/Adapter.h @@ -43,16 +43,16 @@ extern bleio_connection_internal_t bleio_connections[BLEIO_TOTAL_CONNECTION_COUN typedef struct { mp_obj_base_t base; - uint8_t* advertising_data; - uint8_t* scan_response_data; - uint8_t* current_advertising_data; - bleio_scanresults_obj_t* scan_results; + uint8_t *advertising_data; + uint8_t *scan_response_data; + uint8_t *current_advertising_data; + bleio_scanresults_obj_t *scan_results; mp_obj_t name; mp_obj_tuple_t *connection_objs; ble_drv_evt_handler_entry_t handler_entry; } bleio_adapter_obj_t; -void bleio_adapter_gc_collect(bleio_adapter_obj_t* adapter); -void bleio_adapter_reset(bleio_adapter_obj_t* adapter); +void bleio_adapter_gc_collect(bleio_adapter_obj_t *adapter); +void bleio_adapter_reset(bleio_adapter_obj_t *adapter); #endif // MICROPY_INCLUDED_NRF_COMMON_HAL_BLEIO_ADAPTER_H diff --git a/ports/nrf/common-hal/_bleio/Characteristic.c b/ports/nrf/common-hal/_bleio/Characteristic.c index c0f0372c3..4c5de3124 100644 --- a/ports/nrf/common-hal/_bleio/Characteristic.c +++ b/ports/nrf/common-hal/_bleio/Characteristic.c @@ -38,7 +38,7 @@ STATIC uint16_t characteristic_get_cccd(uint16_t cccd_handle, uint16_t conn_handle) { uint16_t cccd; ble_gatts_value_t value = { - .p_value = (uint8_t*) &cccd, + .p_value = (uint8_t *)&cccd, .len = 2, }; @@ -96,7 +96,7 @@ void common_hal_bleio_characteristic_construct(bleio_characteristic_obj_t *self, const mp_int_t max_length_max = fixed_length ? BLE_GATTS_FIX_ATTR_LEN_MAX : BLE_GATTS_VAR_ATTR_LEN_MAX; if (max_length < 0 || max_length > max_length_max) { mp_raise_ValueError_varg(translate("max_length must be 0-%d when fixed_length is %s"), - max_length_max, fixed_length ? "True" : "False"); + max_length_max, fixed_length ? "True" : "False"); } self->max_length = max_length; self->fixed_length = fixed_length; @@ -116,7 +116,7 @@ bleio_service_obj_t *common_hal_bleio_characteristic_get_service(bleio_character return self->service; } -size_t common_hal_bleio_characteristic_get_value(bleio_characteristic_obj_t *self, uint8_t* buf, size_t len) { +size_t common_hal_bleio_characteristic_get_value(bleio_characteristic_obj_t *self, uint8_t *buf, size_t len) { // Do GATT operations only if this characteristic has been added to a registered service. if (self->handle != BLE_GATT_HANDLE_INVALID) { uint16_t conn_handle = bleio_connection_get_conn_handle(self->service->connection); @@ -139,7 +139,7 @@ void common_hal_bleio_characteristic_set_value(bleio_characteristic_obj_t *self, uint16_t conn_handle = bleio_connection_get_conn_handle(self->service->connection); // Last argument is true if write-no-reponse desired. common_hal_bleio_gattc_write(self->handle, conn_handle, bufinfo, - (self->props & CHAR_PROP_WRITE_NO_RESPONSE)); + (self->props & CHAR_PROP_WRITE_NO_RESPONSE)); } else { // Validate data length for local characteristics only. if (self->fixed_length && bufinfo->len != self->max_length) { @@ -216,7 +216,7 @@ void common_hal_bleio_characteristic_add_descriptor(bleio_characteristic_obj_t * check_nrf_error(sd_ble_gatts_descriptor_add(self->handle, &desc_attr, &descriptor->handle)); mp_obj_list_append(MP_OBJ_FROM_PTR(self->descriptor_list), - MP_OBJ_FROM_PTR(descriptor)); + MP_OBJ_FROM_PTR(descriptor)); } void common_hal_bleio_characteristic_set_cccd(bleio_characteristic_obj_t *self, bool notify, bool indicate) { @@ -238,7 +238,7 @@ void common_hal_bleio_characteristic_set_cccd(bleio_characteristic_obj_t *self, ble_gattc_write_params_t write_params = { .write_op = BLE_GATT_OP_WRITE_REQ, .handle = self->cccd_handle, - .p_value = (uint8_t *) &cccd_value, + .p_value = (uint8_t *)&cccd_value, .len = 2, }; diff --git a/ports/nrf/common-hal/_bleio/CharacteristicBuffer.c b/ports/nrf/common-hal/_bleio/CharacteristicBuffer.c index 132e392dd..b17327da4 100644 --- a/ports/nrf/common-hal/_bleio/CharacteristicBuffer.c +++ b/ports/nrf/common-hal/_bleio/CharacteristicBuffer.c @@ -49,7 +49,7 @@ STATIC void write_to_ringbuf(bleio_characteristic_buffer_obj_t *self, uint8_t *d } STATIC bool characteristic_buffer_on_ble_evt(ble_evt_t *ble_evt, void *param) { - bleio_characteristic_buffer_obj_t *self = (bleio_characteristic_buffer_obj_t *) param; + bleio_characteristic_buffer_obj_t *self = (bleio_characteristic_buffer_obj_t *)param; switch (ble_evt->header.evt_id) { case BLE_GATTS_EVT_WRITE: { // A client wrote to this server characteristic. @@ -65,7 +65,7 @@ STATIC bool characteristic_buffer_on_ble_evt(ble_evt_t *ble_evt, void *param) { case BLE_GATTC_EVT_HVX: { // A remote service wrote to this characteristic. - ble_gattc_evt_hvx_t* evt_hvx = &ble_evt->evt.gattc_evt.params.hvx; + ble_gattc_evt_hvx_t *evt_hvx = &ble_evt->evt.gattc_evt.params.hvx; // Must be a notification, and event handle must match the handle for my characteristic. if (evt_hvx->type == BLE_GATT_HVX_NOTIFICATION && evt_hvx->handle == self->characteristic->handle) { @@ -82,9 +82,9 @@ STATIC bool characteristic_buffer_on_ble_evt(ble_evt_t *ble_evt, void *param) { // Assumes that timeout and buffer_size have been validated before call. void common_hal_bleio_characteristic_buffer_construct(bleio_characteristic_buffer_obj_t *self, - bleio_characteristic_obj_t *characteristic, - mp_float_t timeout, - size_t buffer_size) { + bleio_characteristic_obj_t *characteristic, + mp_float_t timeout, + size_t buffer_size) { self->characteristic = characteristic; self->timeout_ms = timeout * 1000; @@ -100,10 +100,10 @@ uint32_t common_hal_bleio_characteristic_buffer_read(bleio_characteristic_buffer uint64_t start_ticks = supervisor_ticks_ms64(); // Wait for all bytes received or timeout - while ( (ringbuf_num_filled(&self->ringbuf) < len) && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms) ) { + while ((ringbuf_num_filled(&self->ringbuf) < len) && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms)) { RUN_BACKGROUND_TASKS; // Allow user to break out of a timeout with a KeyboardInterrupt. - if ( mp_hal_is_interrupted() ) { + if (mp_hal_is_interrupted()) { return 0; } } @@ -148,8 +148,8 @@ void common_hal_bleio_characteristic_buffer_deinit(bleio_characteristic_buffer_o bool common_hal_bleio_characteristic_buffer_connected(bleio_characteristic_buffer_obj_t *self) { return self->characteristic != NULL && - self->characteristic->service != NULL && - (!self->characteristic->service->is_remote || - (self->characteristic->service->connection != MP_OBJ_NULL && - common_hal_bleio_connection_get_connected(self->characteristic->service->connection))); + self->characteristic->service != NULL && + (!self->characteristic->service->is_remote || + (self->characteristic->service->connection != MP_OBJ_NULL && + common_hal_bleio_connection_get_connected(self->characteristic->service->connection))); } diff --git a/ports/nrf/common-hal/_bleio/Connection.c b/ports/nrf/common-hal/_bleio/Connection.c index 36fda0bb3..f57ee639a 100644 --- a/ports/nrf/common-hal/_bleio/Connection.c +++ b/ports/nrf/common-hal/_bleio/Connection.c @@ -63,8 +63,8 @@ static const ble_gap_sec_params_t pairing_sec_params = { .io_caps = BLE_GAP_IO_CAPS_NONE, .min_key_size = 7, .max_key_size = 16, - .kdist_own = { .enc = 1, .id = 1}, - .kdist_peer = { .enc = 1, .id = 1}, + .kdist_own = { .enc = 1, .id = 1}, + .kdist_peer = { .enc = 1, .id = 1}, }; #define CONNECTION_DEBUG (1) @@ -81,7 +81,7 @@ static bleio_service_obj_t *m_char_discovery_service; static bleio_characteristic_obj_t *m_desc_discovery_characteristic; bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { - bleio_connection_internal_t *self = (bleio_connection_internal_t*)self_in; + bleio_connection_internal_t *self = (bleio_connection_internal_t *)self_in; if (BLE_GAP_EVT_BASE <= ble_evt->header.evt_id && ble_evt->header.evt_id <= BLE_GAP_EVT_LAST && ble_evt->evt.gap_evt.conn_handle != self->conn_handle) { @@ -121,7 +121,7 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { case BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST: { ble_gatts_evt_exchange_mtu_request_t *request = - &ble_evt->evt.gatts_evt.params.exchange_mtu_request; + &ble_evt->evt.gatts_evt.params.exchange_mtu_request; uint16_t new_mtu = BLE_GATTS_VAR_ATTR_LEN_MAX; if (request->client_rx_mtu < new_mtu) { @@ -142,7 +142,7 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { case BLE_GATTC_EVT_EXCHANGE_MTU_RSP: { ble_gattc_evt_exchange_mtu_rsp_t *response = - &ble_evt->evt.gattc_evt.params.exchange_mtu_rsp; + &ble_evt->evt.gattc_evt.params.exchange_mtu_rsp; self->mtu = response->server_rx_mtu; break; @@ -169,12 +169,12 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { sd_ble_gatts_sys_attr_set(self->conn_handle, NULL, 0, 0); break; - #if CIRCUITPY_VERBOSE_BLE + #if CIRCUITPY_VERBOSE_BLE // Use read authorization to snoop on all reads when doing verbose debugging. case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST: { ble_gatts_evt_rw_authorize_request_t *request = - &ble_evt->evt.gatts_evt.params.authorize_request; + &ble_evt->evt.gatts_evt.params.authorize_request; mp_printf(&mp_plat_print, "Read %x offset %d ", request->request.read.handle, request->request.read.offset); uint8_t value_bytes[22]; @@ -200,20 +200,20 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { sd_ble_gatts_rw_authorize_reply(self->conn_handle, &reply); break; } - #endif + #endif case BLE_GATTS_EVT_HVN_TX_COMPLETE: // Capture this for now. 0x55 break; case BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST: { self->conn_params_updating = true; ble_gap_evt_conn_param_update_request_t *request = - &ble_evt->evt.gap_evt.params.conn_param_update_request; + &ble_evt->evt.gap_evt.params.conn_param_update_request; sd_ble_gap_conn_param_update(self->conn_handle, &request->conn_params); break; } case BLE_GAP_EVT_CONN_PARAM_UPDATE: { // 0x12 ble_gap_evt_conn_param_update_t *result = - &ble_evt->evt.gap_evt.params.conn_param_update; + &ble_evt->evt.gap_evt.params.conn_param_update; #if CIRCUITPY_VERBOSE_BLE ble_gap_conn_params_t *cp = &ble_evt->evt.gap_evt.params.conn_param_update.conn_params; @@ -236,23 +236,23 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { self->ediv = EDIV_INVALID; ble_gap_sec_keyset_t keyset = { .keys_own = { - .p_enc_key = &self->bonding_keys.own_enc, - .p_id_key = NULL, + .p_enc_key = &self->bonding_keys.own_enc, + .p_id_key = NULL, .p_sign_key = NULL, - .p_pk = NULL + .p_pk = NULL }, .keys_peer = { - .p_enc_key = &self->bonding_keys.peer_enc, - .p_id_key = &self->bonding_keys.peer_id, + .p_enc_key = &self->bonding_keys.peer_enc, + .p_id_key = &self->bonding_keys.peer_id, .p_sign_key = NULL, - .p_pk = NULL + .p_pk = NULL } }; sd_ble_gap_sec_params_reply(self->conn_handle, BLE_GAP_SEC_STATUS_SUCCESS, - self->is_central ? NULL : &pairing_sec_params, - &keyset); + self->is_central ? NULL : &pairing_sec_params, + &keyset); break; } @@ -263,7 +263,7 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { case BLE_GAP_EVT_AUTH_STATUS: { // 0x19 // Key exchange completed. - ble_gap_evt_auth_status_t* status = &ble_evt->evt.gap_evt.params.auth_status; + ble_gap_evt_auth_status_t *status = &ble_evt->evt.gap_evt.params.auth_status; self->sec_status = status->auth_status; if (status->auth_status == BLE_GAP_SEC_STATUS_SUCCESS) { self->ediv = self->bonding_keys.own_enc.master_id.ediv; @@ -281,9 +281,9 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { // Peer asks for the stored keys. // - load key and return if bonded previously. // - Else return NULL --> Initiate key exchange - ble_gap_evt_sec_info_request_t* sec_info_request = &ble_evt->evt.gap_evt.params.sec_info_request; - (void) sec_info_request; - if ( bonding_load_keys(self->is_central, sec_info_request->master_id.ediv, &self->bonding_keys) ) { + ble_gap_evt_sec_info_request_t *sec_info_request = &ble_evt->evt.gap_evt.params.sec_info_request; + (void)sec_info_request; + if (bonding_load_keys(self->is_central, sec_info_request->master_id.ediv, &self->bonding_keys)) { sd_ble_gap_sec_info_reply( self->conn_handle, &self->bonding_keys.own_enc.enc_info, @@ -299,7 +299,7 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { case BLE_GAP_EVT_CONN_SEC_UPDATE: { // 0x1a // We get this both on first-time pairing and on subsequent pairings using stored keys. - ble_gap_conn_sec_t* conn_sec = &ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec; + ble_gap_conn_sec_t *conn_sec = &ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec; if (conn_sec->sec_mode.sm <= 1 && conn_sec->sec_mode.lv <= 1) { // Security setup did not succeed: // mode 0, level 0 means no access @@ -391,7 +391,7 @@ void common_hal_bleio_connection_set_connection_interval(bleio_connection_intern } // service_uuid may be NULL, to discover all services. -STATIC bool discover_next_services(bleio_connection_internal_t* connection, uint16_t start_handle, ble_uuid_t *service_uuid) { +STATIC bool discover_next_services(bleio_connection_internal_t *connection, uint16_t start_handle, ble_uuid_t *service_uuid) { m_discovery_successful = false; m_discovery_in_process = true; @@ -408,7 +408,7 @@ STATIC bool discover_next_services(bleio_connection_internal_t* connection, uint return m_discovery_successful; } -STATIC bool discover_next_characteristics(bleio_connection_internal_t* connection, bleio_service_obj_t *service, uint16_t start_handle) { +STATIC bool discover_next_characteristics(bleio_connection_internal_t *connection, bleio_service_obj_t *service, uint16_t start_handle) { m_char_discovery_service = service; ble_gattc_handle_range_t handle_range; @@ -430,7 +430,7 @@ STATIC bool discover_next_characteristics(bleio_connection_internal_t* connectio return m_discovery_successful; } -STATIC bool discover_next_descriptors(bleio_connection_internal_t* connection, bleio_characteristic_obj_t *characteristic, uint16_t start_handle, uint16_t end_handle) { +STATIC bool discover_next_descriptors(bleio_connection_internal_t *connection, bleio_characteristic_obj_t *characteristic, uint16_t start_handle, uint16_t end_handle) { m_desc_discovery_characteristic = characteristic; ble_gattc_handle_range_t handle_range; @@ -452,7 +452,7 @@ STATIC bool discover_next_descriptors(bleio_connection_internal_t* connection, b return m_discovery_successful; } -STATIC void on_primary_srv_discovery_rsp(ble_gattc_evt_prim_srvc_disc_rsp_t *response, bleio_connection_internal_t* connection) { +STATIC void on_primary_srv_discovery_rsp(ble_gattc_evt_prim_srvc_disc_rsp_t *response, bleio_connection_internal_t *connection) { for (size_t i = 0; i < response->count; ++i) { ble_gattc_service_t *gattc_service = &response->services[i]; @@ -481,7 +481,7 @@ STATIC void on_primary_srv_discovery_rsp(ble_gattc_evt_prim_srvc_disc_rsp_t *res } mp_obj_list_append(MP_OBJ_FROM_PTR(connection->remote_service_list), - MP_OBJ_FROM_PTR(service)); + MP_OBJ_FROM_PTR(service)); } if (response->count > 0) { @@ -490,7 +490,7 @@ STATIC void on_primary_srv_discovery_rsp(ble_gattc_evt_prim_srvc_disc_rsp_t *res m_discovery_in_process = false; } -STATIC void on_char_discovery_rsp(ble_gattc_evt_char_disc_rsp_t *response, bleio_connection_internal_t* connection) { +STATIC void on_char_discovery_rsp(ble_gattc_evt_char_disc_rsp_t *response, bleio_connection_internal_t *connection) { for (size_t i = 0; i < response->count; ++i) { ble_gattc_char_t *gattc_char = &response->chars[i]; @@ -526,7 +526,7 @@ STATIC void on_char_discovery_rsp(ble_gattc_evt_char_disc_rsp_t *response, bleio mp_const_empty_bytes); mp_obj_list_append(MP_OBJ_FROM_PTR(m_char_discovery_service->characteristic_list), - MP_OBJ_FROM_PTR(characteristic)); + MP_OBJ_FROM_PTR(characteristic)); } if (response->count > 0) { @@ -535,7 +535,7 @@ STATIC void on_char_discovery_rsp(ble_gattc_evt_char_disc_rsp_t *response, bleio m_discovery_in_process = false; } -STATIC void on_desc_discovery_rsp(ble_gattc_evt_desc_disc_rsp_t *response, bleio_connection_internal_t* connection) { +STATIC void on_desc_discovery_rsp(ble_gattc_evt_desc_disc_rsp_t *response, bleio_connection_internal_t *connection) { for (size_t i = 0; i < response->count; ++i) { ble_gattc_desc_t *gattc_desc = &response->descs[i]; @@ -583,7 +583,7 @@ STATIC void on_desc_discovery_rsp(ble_gattc_evt_desc_disc_rsp_t *response, bleio descriptor->handle = gattc_desc->handle; mp_obj_list_append(MP_OBJ_FROM_PTR(m_desc_discovery_characteristic->descriptor_list), - MP_OBJ_FROM_PTR(descriptor)); + MP_OBJ_FROM_PTR(descriptor)); } if (response->count > 0) { @@ -593,7 +593,7 @@ STATIC void on_desc_discovery_rsp(ble_gattc_evt_desc_disc_rsp_t *response, bleio } STATIC bool discovery_on_ble_evt(ble_evt_t *ble_evt, mp_obj_t payload) { - bleio_connection_internal_t* connection = MP_OBJ_TO_PTR(payload); + bleio_connection_internal_t *connection = MP_OBJ_TO_PTR(payload); switch (ble_evt->header.evt_id) { case BLE_GAP_EVT_DISCONNECTED: m_discovery_successful = false; @@ -714,7 +714,7 @@ STATIC void discover_remote_services(bleio_connection_internal_t *self, mp_obj_t while (next_desc_start_handle <= service->end_handle && next_desc_start_handle <= next_desc_end_handle && discover_next_descriptors(self, characteristic, - next_desc_start_handle, next_desc_end_handle)) { + next_desc_start_handle, next_desc_end_handle)) { // Get the most recently discovered descriptor, and then ask for descriptors // whose handles start after that descriptor's handle. // There must be at least one if discover_next_descriptors() returned true. @@ -735,7 +735,7 @@ mp_obj_tuple_t *common_hal_bleio_connection_discover_remote_services(bleio_conne // Convert to a tuple and then clear the list so the callee will take ownership. mp_obj_tuple_t *services_tuple = mp_obj_new_tuple(self->connection->remote_service_list->len, - self->connection->remote_service_list->items); + self->connection->remote_service_list->items); mp_obj_list_clear(MP_OBJ_FROM_PTR(self->connection->remote_service_list)); return services_tuple; @@ -748,7 +748,7 @@ uint16_t bleio_connection_get_conn_handle(bleio_connection_obj_t *self) { return self->connection->conn_handle; } -mp_obj_t bleio_connection_new_from_internal(bleio_connection_internal_t* internal) { +mp_obj_t bleio_connection_new_from_internal(bleio_connection_internal_t *internal) { if (internal->connection_obj != mp_const_none) { return internal->connection_obj; } diff --git a/ports/nrf/common-hal/_bleio/Connection.h b/ports/nrf/common-hal/_bleio/Connection.h index 180b2727c..eb095c993 100644 --- a/ports/nrf/common-hal/_bleio/Connection.h +++ b/ports/nrf/common-hal/_bleio/Connection.h @@ -78,7 +78,7 @@ typedef struct { typedef struct { mp_obj_base_t base; - bleio_connection_internal_t* connection; + bleio_connection_internal_t *connection; // The HCI disconnect reason. uint8_t disconnect_reason; } bleio_connection_obj_t; @@ -87,7 +87,7 @@ void bleio_connection_clear(bleio_connection_internal_t *self); bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in); uint16_t bleio_connection_get_conn_handle(bleio_connection_obj_t *self); -mp_obj_t bleio_connection_new_from_internal(bleio_connection_internal_t* connection); +mp_obj_t bleio_connection_new_from_internal(bleio_connection_internal_t *connection); bleio_connection_internal_t *bleio_conn_handle_to_connection(uint16_t conn_handle); #endif // MICROPY_INCLUDED_NRF_COMMON_HAL_BLEIO_CONNECTION_H diff --git a/ports/nrf/common-hal/_bleio/Descriptor.c b/ports/nrf/common-hal/_bleio/Descriptor.c index d848659fc..7ec287260 100644 --- a/ports/nrf/common-hal/_bleio/Descriptor.c +++ b/ports/nrf/common-hal/_bleio/Descriptor.c @@ -44,7 +44,7 @@ void common_hal_bleio_descriptor_construct(bleio_descriptor_obj_t *self, bleio_c const mp_int_t max_length_max = fixed_length ? BLE_GATTS_FIX_ATTR_LEN_MAX : BLE_GATTS_VAR_ATTR_LEN_MAX; if (max_length < 0 || max_length > max_length_max) { mp_raise_ValueError_varg(translate("max_length must be 0-%d when fixed_length is %s"), - max_length_max, fixed_length ? "True" : "False"); + max_length_max, fixed_length ? "True" : "False"); } self->max_length = max_length; self->fixed_length = fixed_length; @@ -58,7 +58,7 @@ bleio_characteristic_obj_t *common_hal_bleio_descriptor_get_characteristic(bleio return self->characteristic; } -size_t common_hal_bleio_descriptor_get_value(bleio_descriptor_obj_t *self, uint8_t* buf, size_t len) { +size_t common_hal_bleio_descriptor_get_value(bleio_descriptor_obj_t *self, uint8_t *buf, size_t len) { // Do GATT operations only if this descriptor has been registered if (self->handle != BLE_GATT_HANDLE_INVALID) { uint16_t conn_handle = bleio_connection_get_conn_handle(self->characteristic->service->connection); diff --git a/ports/nrf/common-hal/_bleio/PacketBuffer.c b/ports/nrf/common-hal/_bleio/PacketBuffer.c index 6d587984c..8f87b2497 100644 --- a/ports/nrf/common-hal/_bleio/PacketBuffer.c +++ b/ports/nrf/common-hal/_bleio/PacketBuffer.c @@ -51,13 +51,13 @@ STATIC void write_to_ringbuf(bleio_packet_buffer_obj_t *self, uint8_t *data, uin // Make room for the new value by dropping the oldest packets first. while (ringbuf_capacity(&self->ringbuf) - ringbuf_num_filled(&self->ringbuf) < len + sizeof(uint16_t)) { uint16_t packet_length; - ringbuf_get_n(&self->ringbuf, (uint8_t*) &packet_length, sizeof(uint16_t)); + ringbuf_get_n(&self->ringbuf, (uint8_t *)&packet_length, sizeof(uint16_t)); for (uint16_t i = 0; i < packet_length; i++) { ringbuf_get(&self->ringbuf); } // set an overflow flag? } - ringbuf_put_n(&self->ringbuf, (uint8_t*) &len, sizeof(uint16_t)); + ringbuf_put_n(&self->ringbuf, (uint8_t *)&len, sizeof(uint16_t)); ringbuf_put_n(&self->ringbuf, data, len); sd_nvic_critical_region_exit(is_nested_critical_region); } @@ -112,14 +112,14 @@ STATIC bool packet_buffer_on_ble_client_evt(ble_evt_t *ble_evt, void *param) { } uint16_t conn_handle = ble_evt->evt.gattc_evt.conn_handle; - bleio_packet_buffer_obj_t *self = (bleio_packet_buffer_obj_t *) param; + bleio_packet_buffer_obj_t *self = (bleio_packet_buffer_obj_t *)param; if (conn_handle != self->conn_handle) { return false; } switch (evt_id) { case BLE_GATTC_EVT_HVX: { // A remote service wrote to this characteristic. - ble_gattc_evt_hvx_t* evt_hvx = &ble_evt->evt.gattc_evt.params.hvx; + ble_gattc_evt_hvx_t *evt_hvx = &ble_evt->evt.gattc_evt.params.hvx; // Must be a notification, and event handle must match the handle for my characteristic. if (evt_hvx->handle == self->characteristic->handle) { write_to_ringbuf(self, evt_hvx->data, evt_hvx->len); @@ -143,7 +143,7 @@ STATIC bool packet_buffer_on_ble_client_evt(ble_evt_t *ble_evt, void *param) { } STATIC bool packet_buffer_on_ble_server_evt(ble_evt_t *ble_evt, void *param) { - bleio_packet_buffer_obj_t *self = (bleio_packet_buffer_obj_t *) param; + bleio_packet_buffer_obj_t *self = (bleio_packet_buffer_obj_t *)param; switch (ble_evt->header.evt_id) { case BLE_GATTS_EVT_WRITE: { uint16_t conn_handle = ble_evt->evt.gatts_evt.conn_handle; @@ -160,7 +160,7 @@ STATIC bool packet_buffer_on_ble_server_evt(ble_evt_t *ble_evt, void *param) { } write_to_ringbuf(self, evt_write->data, evt_write->len); } else if (evt_write->handle == self->characteristic->cccd_handle) { - uint16_t cccd = *((uint16_t*) evt_write->data); + uint16_t cccd = *((uint16_t *)evt_write->data); if (cccd & BLE_GATT_HVX_NOTIFICATION) { self->conn_handle = conn_handle; } else { @@ -185,8 +185,8 @@ STATIC bool packet_buffer_on_ble_server_evt(ble_evt_t *ble_evt, void *param) { } void common_hal_bleio_packet_buffer_construct( - bleio_packet_buffer_obj_t *self, bleio_characteristic_obj_t *characteristic, - size_t buffer_size) { + bleio_packet_buffer_obj_t *self, bleio_characteristic_obj_t *characteristic, + size_t buffer_size) { self->characteristic = characteristic; self->client = self->characteristic->service->is_remote; @@ -259,7 +259,7 @@ mp_int_t common_hal_bleio_packet_buffer_readinto(bleio_packet_buffer_obj_t *self // Get packet length, which is in first two bytes of packet. uint16_t packet_length; - ringbuf_get_n(&self->ringbuf, (uint8_t*) &packet_length, sizeof(uint16_t)); + ringbuf_get_n(&self->ringbuf, (uint8_t *)&packet_length, sizeof(uint16_t)); mp_int_t ret; if (packet_length > len) { @@ -267,7 +267,7 @@ mp_int_t common_hal_bleio_packet_buffer_readinto(bleio_packet_buffer_obj_t *self ret = len - packet_length; // Discard the packet if it's too large. Don't fill data. while (packet_length--) { - (void) ringbuf_get(&self->ringbuf); + (void)ringbuf_get(&self->ringbuf); } } else { // Read as much as possible, but might be shorter than len. @@ -281,7 +281,7 @@ mp_int_t common_hal_bleio_packet_buffer_readinto(bleio_packet_buffer_obj_t *self return ret; } -mp_int_t common_hal_bleio_packet_buffer_write(bleio_packet_buffer_obj_t *self, uint8_t *data, size_t len, uint8_t* header, size_t header_len) { +mp_int_t common_hal_bleio_packet_buffer_write(bleio_packet_buffer_obj_t *self, uint8_t *data, size_t len, uint8_t *header, size_t header_len) { if (self->outgoing[0] == NULL) { mp_raise_bleio_BluetoothError(translate("Writes not supported on Characteristic")); } @@ -311,7 +311,7 @@ mp_int_t common_hal_bleio_packet_buffer_write(bleio_packet_buffer_obj_t *self, u uint8_t is_nested_critical_region; sd_nvic_critical_region_enter(&is_nested_critical_region); - uint8_t* pending = self->outgoing[self->pending_index]; + uint8_t *pending = self->outgoing[self->pending_index]; if (self->pending_size == 0) { memcpy(pending, header, header_len); @@ -352,7 +352,7 @@ mp_int_t common_hal_bleio_packet_buffer_get_incoming_packet_length(bleio_packet_ bleio_connection_internal_t *connection = bleio_conn_handle_to_connection(self->conn_handle); if (connection) { return MIN(common_hal_bleio_connection_get_max_packet_length(connection), - self->characteristic->max_length); + self->characteristic->max_length); } } // There's no current connection, so we don't know the MTU, and @@ -383,7 +383,7 @@ mp_int_t common_hal_bleio_packet_buffer_get_outgoing_packet_length(bleio_packet_ bleio_connection_internal_t *connection = bleio_conn_handle_to_connection(self->conn_handle); if (connection) { return MIN(common_hal_bleio_connection_get_max_packet_length(connection), - self->characteristic->max_length); + self->characteristic->max_length); } } // There's no current connection, so we don't know the MTU, and diff --git a/ports/nrf/common-hal/_bleio/PacketBuffer.h b/ports/nrf/common-hal/_bleio/PacketBuffer.h index 699291749..94e0f11d8 100644 --- a/ports/nrf/common-hal/_bleio/PacketBuffer.h +++ b/ports/nrf/common-hal/_bleio/PacketBuffer.h @@ -39,7 +39,7 @@ typedef struct { ringbuf_t ringbuf; // Two outgoing buffers to alternate between. One will be queued for transmission by the SD and // the other is waiting to be queued and can be extended. - uint8_t* outgoing[2]; + uint8_t *outgoing[2]; volatile uint16_t pending_size; // We remember the conn_handle so we can do a NOTIFY/INDICATE to a client. // We can find out the conn_handle on a Characteristic write or a CCCD write (but not a read). diff --git a/ports/nrf/common-hal/_bleio/Service.c b/ports/nrf/common-hal/_bleio/Service.c index 3159d3392..74e74fac9 100644 --- a/ports/nrf/common-hal/_bleio/Service.c +++ b/ports/nrf/common-hal/_bleio/Service.c @@ -34,7 +34,7 @@ #include "shared-bindings/_bleio/Service.h" #include "shared-bindings/_bleio/Adapter.h" -uint32_t _common_hal_bleio_service_construct(bleio_service_obj_t *self, bleio_uuid_obj_t *uuid, bool is_secondary, mp_obj_list_t * characteristic_list) { +uint32_t _common_hal_bleio_service_construct(bleio_service_obj_t *self, bleio_uuid_obj_t *uuid, bool is_secondary, mp_obj_list_t *characteristic_list) { self->handle = 0xFFFF; self->uuid = uuid; self->characteristic_list = characteristic_list; @@ -57,7 +57,7 @@ uint32_t _common_hal_bleio_service_construct(bleio_service_obj_t *self, bleio_uu void common_hal_bleio_service_construct(bleio_service_obj_t *self, bleio_uuid_obj_t *uuid, bool is_secondary) { check_nrf_error(_common_hal_bleio_service_construct(self, uuid, is_secondary, - mp_obj_new_list(0, NULL))); + mp_obj_new_list(0, NULL))); } void bleio_service_from_connection(bleio_service_obj_t *self, mp_obj_t connection) { @@ -86,15 +86,15 @@ bool common_hal_bleio_service_get_is_secondary(bleio_service_obj_t *self) { } void common_hal_bleio_service_add_characteristic(bleio_service_obj_t *self, - bleio_characteristic_obj_t *characteristic, - mp_buffer_info_t *initial_value_bufinfo) { + bleio_characteristic_obj_t *characteristic, + mp_buffer_info_t *initial_value_bufinfo) { ble_gatts_char_md_t char_md = { - .char_props.broadcast = (characteristic->props & CHAR_PROP_BROADCAST) ? 1 : 0, - .char_props.read = (characteristic->props & CHAR_PROP_READ) ? 1 : 0, - .char_props.write_wo_resp = (characteristic->props & CHAR_PROP_WRITE_NO_RESPONSE) ? 1 : 0, - .char_props.write = (characteristic->props & CHAR_PROP_WRITE) ? 1 : 0, - .char_props.notify = (characteristic->props & CHAR_PROP_NOTIFY) ? 1 : 0, - .char_props.indicate = (characteristic->props & CHAR_PROP_INDICATE) ? 1 : 0, + .char_props.broadcast = (characteristic->props & CHAR_PROP_BROADCAST) ? 1 : 0, + .char_props.read = (characteristic->props & CHAR_PROP_READ) ? 1 : 0, + .char_props.write_wo_resp = (characteristic->props & CHAR_PROP_WRITE_NO_RESPONSE) ? 1 : 0, + .char_props.write = (characteristic->props & CHAR_PROP_WRITE) ? 1 : 0, + .char_props.notify = (characteristic->props & CHAR_PROP_NOTIFY) ? 1 : 0, + .char_props.indicate = (characteristic->props & CHAR_PROP_INDICATE) ? 1 : 0, }; ble_gatts_attr_md_t cccd_md = { diff --git a/ports/nrf/common-hal/_bleio/UUID.c b/ports/nrf/common-hal/_bleio/UUID.c index 0c79e980e..399bf23ed 100644 --- a/ports/nrf/common-hal/_bleio/UUID.c +++ b/ports/nrf/common-hal/_bleio/UUID.c @@ -67,7 +67,7 @@ void common_hal_bleio_uuid_get_uuid128(bleio_uuid_obj_t *self, uint8_t uuid128[1 check_nrf_error(sd_ble_uuid_encode(&self->nrf_ble_uuid, &length, uuid128)); } -void common_hal_bleio_uuid_pack_into(bleio_uuid_obj_t *self, uint8_t* buf) { +void common_hal_bleio_uuid_pack_into(bleio_uuid_obj_t *self, uint8_t *buf) { if (self->nrf_ble_uuid.type == BLE_UUID_TYPE_BLE) { buf[0] = self->nrf_ble_uuid.uuid & 0xff; buf[1] = self->nrf_ble_uuid.uuid >> 8; diff --git a/ports/nrf/common-hal/_bleio/__init__.c b/ports/nrf/common-hal/_bleio/__init__.c index 5293f7ad1..7248f8315 100644 --- a/ports/nrf/common-hal/_bleio/__init__.c +++ b/ports/nrf/common-hal/_bleio/__init__.c @@ -120,7 +120,7 @@ void common_hal_bleio_check_connected(uint16_t conn_handle) { } // GATTS read of a Characteristic or Descriptor. -size_t common_hal_bleio_gatts_read(uint16_t handle, uint16_t conn_handle, uint8_t* buf, size_t len) { +size_t common_hal_bleio_gatts_read(uint16_t handle, uint16_t conn_handle, uint8_t *buf, size_t len) { // conn_handle is ignored unless this is a system attribute. // If we're not connected, that's OK, because we can still read and write the local value. @@ -147,7 +147,7 @@ void common_hal_bleio_gatts_write(uint16_t handle, uint16_t conn_handle, mp_buff } typedef struct { - uint8_t* buf; + uint8_t *buf; size_t len; size_t final_len; uint16_t conn_handle; @@ -156,13 +156,13 @@ typedef struct { } read_info_t; STATIC bool _on_gattc_read_rsp_evt(ble_evt_t *ble_evt, void *param) { - read_info_t* read = param; + read_info_t *read = param; switch (ble_evt->header.evt_id) { // More events may be handled later, so keep this as a switch. case BLE_GATTC_EVT_READ_RSP: { - ble_gattc_evt_t* evt = &ble_evt->evt.gattc_evt; + ble_gattc_evt_t *evt = &ble_evt->evt.gattc_evt; ble_gattc_evt_read_rsp_t *response = &evt->params.read_rsp; if (read && evt->conn_handle == read->conn_handle) { read->status = evt->gatt_status; @@ -184,7 +184,7 @@ STATIC bool _on_gattc_read_rsp_evt(ble_evt_t *ble_evt, void *param) { return true; } -size_t common_hal_bleio_gattc_read(uint16_t handle, uint16_t conn_handle, uint8_t* buf, size_t len) { +size_t common_hal_bleio_gattc_read(uint16_t handle, uint16_t conn_handle, uint8_t *buf, size_t len) { common_hal_bleio_check_connected(conn_handle); read_info_t read_info; diff --git a/ports/nrf/common-hal/_bleio/bonding.c b/ports/nrf/common-hal/_bleio/bonding.c index 081ba992f..0c39bfe42 100644 --- a/ports/nrf/common-hal/_bleio/bonding.c +++ b/ports/nrf/common-hal/_bleio/bonding.c @@ -59,12 +59,12 @@ const uint32_t BONDING_FLAG = ('1' | '0' << 8 | 'D' << 16 | 'B' << 24); #if BONDING_DEBUG void bonding_print_block(bonding_block_t *block) { printf("at 0x%08lx: is_central: %1d, type: 0x%x, ediv: 0x%04x, data_length: %d\n", - (uint32_t) block, block->is_central, block->type, block->ediv, block->data_length); + (uint32_t)block, block->is_central, block->type, block->ediv, block->data_length); } void bonding_print_keys(bonding_keys_t *keys) { - for (size_t i = 0; i < sizeof(bonding_keys_t); i ++) { - printf("%x", ((uint8_t*) keys)[i]); + for (size_t i = 0; i < sizeof(bonding_keys_t); i++) { + printf("%x", ((uint8_t *)keys)[i]); } printf("\n"); } @@ -77,16 +77,16 @@ STATIC size_t compute_block_size(uint16_t data_length) { void bonding_erase_storage(void) { // Erase all pages in the bonding area. - for(uint32_t page_address = BONDING_PAGES_START_ADDR; - page_address < BONDING_PAGES_END_ADDR; - page_address += FLASH_PAGE_SIZE) { + for (uint32_t page_address = BONDING_PAGES_START_ADDR; + page_address < BONDING_PAGES_END_ADDR; + page_address += FLASH_PAGE_SIZE) { // Argument is page number, not address. sd_flash_page_erase_sync(page_address / FLASH_PAGE_SIZE); } // Write marker words at the beginning and the end of the bonding area. uint32_t flag = BONDING_FLAG; - sd_flash_write_sync((uint32_t *) BONDING_START_FLAG_ADDR, &flag, 1); - sd_flash_write_sync((uint32_t *) BONDING_END_FLAG_ADDR, &flag, 1); + sd_flash_write_sync((uint32_t *)BONDING_START_FLAG_ADDR, &flag, 1); + sd_flash_write_sync((uint32_t *)BONDING_END_FLAG_ADDR, &flag, 1); } // Given NULL to start or block address, return the address of the next valid block. @@ -97,16 +97,16 @@ STATIC bonding_block_t *next_block(bonding_block_t *block) { while (1) { // Advance to next block. if (block == NULL) { - return (bonding_block_t *) BONDING_DATA_START_ADDR; + return (bonding_block_t *)BONDING_DATA_START_ADDR; } else if (block->type == BLOCK_UNUSED) { // Already at last block (the unused block). return NULL; } // Advance to next block. - block = (bonding_block_t *) ((uint8_t *) block + compute_block_size(block->data_length)); + block = (bonding_block_t *)((uint8_t *)block + compute_block_size(block->data_length)); - if (block >= (bonding_block_t *) BONDING_DATA_END_ADDR) { + if (block >= (bonding_block_t *)BONDING_DATA_END_ADDR) { // Went past end of bonding space. return NULL; } @@ -133,20 +133,20 @@ STATIC bonding_block_t *find_existing_block(bool is_central, bonding_block_type_ if (type == block->type) { if (type == BLOCK_UNUSED || (is_central == block->is_central && ediv == block->ediv)) { - return block; + return block; } } } } // Get an empty block large enough to store data_length data. -STATIC bonding_block_t* find_unused_block(uint16_t data_length) { +STATIC bonding_block_t *find_unused_block(uint16_t data_length) { bonding_block_t *unused_block = find_existing_block(true, BLOCK_UNUSED, EDIV_INVALID); // If no more room, erase all existing blocks and start over. if (!unused_block || - (uint8_t *) unused_block + compute_block_size(data_length) >= (uint8_t *) BONDING_DATA_END_ADDR) { + (uint8_t *)unused_block + compute_block_size(data_length) >= (uint8_t *)BONDING_DATA_END_ADDR) { bonding_erase_storage(); - unused_block = (bonding_block_t *) BONDING_DATA_START_ADDR; + unused_block = (bonding_block_t *)BONDING_DATA_START_ADDR; } return unused_block; } @@ -155,12 +155,12 @@ STATIC bonding_block_t* find_unused_block(uint16_t data_length) { // We don't change data_length, so we can still skip over this block. STATIC void invalidate_block(bonding_block_t *block) { uint32_t zero = 0; - sd_flash_write_sync((uint32_t *) block, &zero, 1); + sd_flash_write_sync((uint32_t *)block, &zero, 1); } // Write bonding block header. STATIC void write_block_header(bonding_block_t *dest_block, bonding_block_t *source_block_header) { - sd_flash_write_sync((uint32_t *) dest_block, (uint32_t *) source_block_header, sizeof(bonding_block_t) / 4); + sd_flash_write_sync((uint32_t *)dest_block, (uint32_t *)source_block_header, sizeof(bonding_block_t) / 4); } // Write variable-length data at end of bonding block. @@ -168,7 +168,7 @@ STATIC void write_block_data(bonding_block_t *dest_block, uint8_t *data, uint16_ // Minimize the number of writes. Datasheet says no more than two writes per word before erasing again. // Start writing after the current header. - uint32_t *flash_word_p = (uint32_t *) ((uint8_t *) dest_block + sizeof(bonding_block_t)); + uint32_t *flash_word_p = (uint32_t *)((uint8_t *)dest_block + sizeof(bonding_block_t)); while (1) { uint32_t word = 0xffffffff; memcpy(&word, data, data_length >= 4 ? 4 : data_length); @@ -186,11 +186,11 @@ STATIC void write_block_data(bonding_block_t *dest_block, uint8_t *data, uint16_ STATIC void write_sys_attr_block(bleio_connection_internal_t *connection) { uint16_t length = 0; // First find out how big a buffer we need, then fetch the data. - if(sd_ble_gatts_sys_attr_get(connection->conn_handle, NULL, &length, SYS_ATTR_FLAGS) != NRF_SUCCESS) { + if (sd_ble_gatts_sys_attr_get(connection->conn_handle, NULL, &length, SYS_ATTR_FLAGS) != NRF_SUCCESS) { return; } uint8_t sys_attr[length]; - if(sd_ble_gatts_sys_attr_get(connection->conn_handle, sys_attr, &length, SYS_ATTR_FLAGS) != NRF_SUCCESS) { + if (sd_ble_gatts_sys_attr_get(connection->conn_handle, sys_attr, &length, SYS_ATTR_FLAGS) != NRF_SUCCESS) { return; } @@ -246,16 +246,16 @@ STATIC void write_keys_block(bleio_connection_internal_t *connection) { }; bonding_block_t *new_block = find_unused_block(sizeof(bonding_keys_t)); write_block_header(new_block, &block_header); - write_block_data(new_block, (uint8_t *) &connection->bonding_keys, sizeof(bonding_keys_t)); + write_block_data(new_block, (uint8_t *)&connection->bonding_keys, sizeof(bonding_keys_t)); } void bonding_clear_keys(bonding_keys_t *bonding_keys) { - memset((uint8_t*) bonding_keys, 0, sizeof(bonding_keys_t)); + memset((uint8_t *)bonding_keys, 0, sizeof(bonding_keys_t)); } void bonding_reset(void) { - if (BONDING_FLAG != *((uint32_t *) BONDING_START_FLAG_ADDR) || - BONDING_FLAG != *((uint32_t *) BONDING_END_FLAG_ADDR)) { + if (BONDING_FLAG != *((uint32_t *)BONDING_START_FLAG_ADDR) || + BONDING_FLAG != *((uint32_t *)BONDING_END_FLAG_ADDR)) { bonding_erase_storage(); } } @@ -292,7 +292,7 @@ bool bonding_load_cccd_info(bool is_central, uint16_t conn_handle, uint16_t ediv } return NRF_SUCCESS == - sd_ble_gatts_sys_attr_set(conn_handle, block->data, block->data_length, SYS_ATTR_FLAGS); + sd_ble_gatts_sys_attr_set(conn_handle, block->data, block->data_length, SYS_ATTR_FLAGS); } bool bonding_load_keys(bool is_central, uint16_t ediv, bonding_keys_t *bonding_keys) { diff --git a/ports/nrf/common-hal/_bleio/bonding.h b/ports/nrf/common-hal/_bleio/bonding.h index cb8e7c427..c0dbe2aec 100644 --- a/ports/nrf/common-hal/_bleio/bonding.h +++ b/ports/nrf/common-hal/_bleio/bonding.h @@ -63,9 +63,9 @@ typedef enum { } bonding_block_type_t; typedef struct { - bool is_central: 1; // 1 if data is for a central role. - uint16_t reserved: 7; // Not currently used - bonding_block_type_t type: 8; // What kind of data is stored in. + bool is_central : 1; // 1 if data is for a central role. + uint16_t reserved : 7; // Not currently used + bonding_block_type_t type : 8; // What kind of data is stored in. uint16_t ediv; // ediv value; used as a lookup key. uint16_t conn_handle; // Connection handle: used when a BLOCK_SYS_ATTR is queued to write. // Not used as a key, etc. diff --git a/ports/nrf/common-hal/analogio/AnalogIn.c b/ports/nrf/common-hal/analogio/AnalogIn.c index dbcc5281c..2f7bede16 100644 --- a/ports/nrf/common-hal/analogio/AnalogIn.c +++ b/ports/nrf/common-hal/analogio/AnalogIn.c @@ -39,14 +39,16 @@ void analogin_init(void) { nrf_saadc_enable(NRF_SAADC); nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE); nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_CALIBRATEOFFSET); - while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE) == 0) { } + while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE) == 0) { + } nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE); nrf_saadc_disable(NRF_SAADC); } void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self, const mcu_pin_obj_t *pin) { - if (pin->adc_channel == 0) + if (pin->adc_channel == 0) { mp_raise_ValueError(translate("Pin does not have ADC capabilities")); + } nrf_gpio_cfg_default(pin->number); @@ -59,8 +61,9 @@ bool common_hal_analogio_analogin_deinited(analogio_analogin_obj_t *self) { } void common_hal_analogio_analogin_deinit(analogio_analogin_obj_t *self) { - if (common_hal_analogio_analogin_deinited(self)) + if (common_hal_analogio_analogin_deinited(self)) { return; + } nrf_gpio_cfg_default(self->pin->number); @@ -88,32 +91,40 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { nrf_saadc_oversample_set(NRF_SAADC, NRF_SAADC_OVERSAMPLE_DISABLED); nrf_saadc_enable(NRF_SAADC); - for (uint32_t i = 0; i < SAADC_CH_NUM; i++) + for (uint32_t i = 0; i < SAADC_CH_NUM; i++) { nrf_saadc_channel_input_set(NRF_SAADC, i, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED); + } nrf_saadc_channel_init(NRF_SAADC, CHANNEL_NO, &config); nrf_saadc_channel_input_set(NRF_SAADC, CHANNEL_NO, self->pin->adc_channel, self->pin->adc_channel); nrf_saadc_buffer_init(NRF_SAADC, &value, 1); nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_START); - while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STARTED) == 0); + while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STARTED) == 0) { + ; + } nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STARTED); nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_SAMPLE); - while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_END) == 0); + while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_END) == 0) { + ; + } nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END); nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_STOP); - while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STOPPED) == 0); + while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STOPPED) == 0) { + ; + } nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED); nrf_saadc_disable(NRF_SAADC); - if (value < 0) + if (value < 0) { value = 0; + } // Map value to from 14 to 16 bits - return (value << 2); + return value << 2; } float common_hal_analogio_analogin_get_reference_voltage(analogio_analogin_obj_t *self) { diff --git a/ports/nrf/common-hal/analogio/AnalogIn.h b/ports/nrf/common-hal/analogio/AnalogIn.h index a268bb54e..0f5fe3208 100644 --- a/ports/nrf/common-hal/analogio/AnalogIn.h +++ b/ports/nrf/common-hal/analogio/AnalogIn.h @@ -33,7 +33,7 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t * pin; + const mcu_pin_obj_t *pin; } analogio_analogin_obj_t; void analogin_init(void); diff --git a/ports/nrf/common-hal/analogio/AnalogOut.c b/ports/nrf/common-hal/analogio/AnalogOut.c index adafa15d5..7afa773d3 100644 --- a/ports/nrf/common-hal/analogio/AnalogOut.c +++ b/ports/nrf/common-hal/analogio/AnalogOut.c @@ -33,7 +33,7 @@ #include "py/runtime.h" #include "supervisor/shared/translate.h" -void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self, const mcu_pin_obj_t *pin) { mp_raise_RuntimeError(translate("AnalogOut functionality not supported")); } diff --git a/ports/nrf/common-hal/audiobusio/I2SOut.c b/ports/nrf/common-hal/audiobusio/I2SOut.c index 34eecf8d5..ded03c07c 100644 --- a/ports/nrf/common-hal/audiobusio/I2SOut.c +++ b/ports/nrf/common-hal/audiobusio/I2SOut.c @@ -38,11 +38,20 @@ static audiobusio_i2sout_obj_t *instance; -struct { int16_t l, r; } static_sample16 = {0x8000, 0x8000}; -struct { uint8_t l1, r1, l2, r2; } static_sample8 = {0x80, 0x80, 0x80, 0x80}; - -struct frequency_info { uint32_t RATIO; uint32_t MCKFREQ; int sample_rate; float abserr; }; -struct ratio_info { uint32_t RATIO; int16_t divisor; bool can_16bit; }; +struct { int16_t l, r; +} static_sample16 = {0x8000, 0x8000}; +struct { uint8_t l1, r1, l2, r2; +} static_sample8 = {0x80, 0x80, 0x80, 0x80}; + +struct frequency_info { uint32_t RATIO; + uint32_t MCKFREQ; + int sample_rate; + float abserr; +}; +struct ratio_info { uint32_t RATIO; + int16_t divisor; + bool can_16bit; +}; struct ratio_info ratios[] = { { I2S_CONFIG_RATIO_RATIO_32X, 32, true }, { I2S_CONFIG_RATIO_RATIO_48X, 48, false }, @@ -55,7 +64,9 @@ struct ratio_info ratios[] = { { I2S_CONFIG_RATIO_RATIO_512X, 512, true }, }; -struct mclk_info { uint32_t MCKFREQ; int divisor; }; +struct mclk_info { uint32_t MCKFREQ; + int divisor; +}; struct mclk_info mclks[] = { { I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, 8 }, { I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, 10 }, @@ -71,7 +82,7 @@ struct mclk_info mclks[] = { }; static void calculate_ratio_info(uint32_t target_sample_rate, struct frequency_info *info, - int ratio_index, int mclk_index) { + int ratio_index, int mclk_index) { info->RATIO = ratios[ratio_index].RATIO; info->MCKFREQ = mclks[mclk_index].MCKFREQ; info->sample_rate = 32000000 @@ -82,24 +93,24 @@ static void calculate_ratio_info(uint32_t target_sample_rate, struct frequency_i void choose_i2s_clocking(audiobusio_i2sout_obj_t *self, uint32_t sample_rate) { struct frequency_info best = {0, 0, 0, 1.0}; - for (size_t ri=0; ri<sizeof(ratios) / sizeof(ratios[0]); ri++) { + for (size_t ri = 0; ri < sizeof(ratios) / sizeof(ratios[0]); ri++) { if (NRF_I2S->CONFIG.SWIDTH == I2S_CONFIG_SWIDTH_SWIDTH_16Bit - && !ratios[ri].can_16bit) { + && !ratios[ri].can_16bit) { continue; } - for (size_t mi=0; mi<sizeof(mclks) / sizeof(mclks[0]); mi++) { + for (size_t mi = 0; mi < sizeof(mclks) / sizeof(mclks[0]); mi++) { struct frequency_info info = {0, 0, 1.0}; calculate_ratio_info(sample_rate, &info, ri, mi); if (info.abserr < best.abserr) { best = info; } -#ifdef DEBUG_CLOCKING + #ifdef DEBUG_CLOCKING mp_printf(&mp_plat_print, - "RATIO=%3d MCKFREQ=%08x rate=%d abserr=%.4f\n", - info.RATIO, info.MCKFREQ, info.sample_rate, - (double)info.abserr); -#endif + "RATIO=%3d MCKFREQ=%08x rate=%d abserr=%.4f\n", + info.RATIO, info.MCKFREQ, info.sample_rate, + (double)info.abserr); + #endif } } NRF_I2S->CONFIG.RATIO = best.RATIO; @@ -107,7 +118,7 @@ void choose_i2s_clocking(audiobusio_i2sout_obj_t *self, uint32_t sample_rate) { self->sample_rate = best.sample_rate; } -static void i2s_buffer_fill(audiobusio_i2sout_obj_t* self) { +static void i2s_buffer_fill(audiobusio_i2sout_obj_t *self) { void *buffer = self->buffers[self->next_buffer]; void *buffer_start = buffer; NRF_I2S->TXD.PTR = (uintptr_t)buffer; @@ -119,7 +130,7 @@ static void i2s_buffer_fill(audiobusio_i2sout_obj_t* self) { uint32_t sample_buffer_length; audioio_get_buffer_result_t get_buffer_result = audiosample_get_buffer(self->sample, false, 0, - &self->sample_data, &sample_buffer_length); + &self->sample_data, &sample_buffer_length); self->sample_end = self->sample_data + sample_buffer_length; if (get_buffer_result == GET_BUFFER_DONE) { if (self->loop) { @@ -138,16 +149,16 @@ static void i2s_buffer_fill(audiobusio_i2sout_obj_t* self) { if (self->samples_signed) { memcpy(buffer, self->sample_data, bytecount); } else if (self->bytes_per_sample == 2) { - uint16_t *bp = (uint16_t*)buffer; - uint16_t *be = (uint16_t*)(buffer + bytecount); - uint16_t *sp = (uint16_t*)self->sample_data; + uint16_t *bp = (uint16_t *)buffer; + uint16_t *be = (uint16_t *)(buffer + bytecount); + uint16_t *sp = (uint16_t *)self->sample_data; for (; bp < be;) { *bp++ = *sp++ + 0x8000; } } else { - uint8_t *bp = (uint8_t*)buffer; - uint8_t *be = (uint8_t*)(buffer + bytecount); - uint8_t *sp = (uint8_t*)self->sample_data; + uint8_t *bp = (uint8_t *)buffer; + uint8_t *be = (uint8_t *)(buffer + bytecount); + uint8_t *sp = (uint8_t *)self->sample_data; for (; bp < be;) { *bp++ = *sp++ + 0x80; } @@ -162,13 +173,13 @@ static void i2s_buffer_fill(audiobusio_i2sout_obj_t* self) { if (buffer != buffer_start) { if (self->bytes_per_sample == 1 && self->channel_count == 1) { // For 8-bit mono, 4 copies of the final sample are required - self->hold_value = 0x01010101 * *(uint8_t*)(buffer-1); + self->hold_value = 0x01010101 * *(uint8_t *)(buffer - 1); } else if (self->bytes_per_sample == 2 && self->channel_count == 2) { // For 16-bit stereo, 1 copy of the final sample is required - self->hold_value = *(uint32_t*)(buffer-4); + self->hold_value = *(uint32_t *)(buffer - 4); } else { // For 8-bit stereo and 16-bit mono, 2 copies of the final sample are required - self->hold_value = 0x00010001 * *(uint16_t*)(buffer-2); + self->hold_value = 0x00010001 * *(uint16_t *)(buffer - 2); } } @@ -180,19 +191,21 @@ static void i2s_buffer_fill(audiobusio_i2sout_obj_t* self) { NRF_I2S->TASKS_STOP = 1; self->playing = false; } - uint32_t *bp = (uint32_t*)buffer; - uint32_t *be = (uint32_t*)(buffer + bytesleft); - for (; bp != be; ) + uint32_t *bp = (uint32_t *)buffer; + uint32_t *be = (uint32_t *)(buffer + bytesleft); + for (; bp != be;) { *bp++ = self->hold_value; + } return; } } -void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, - const mcu_pin_obj_t* bit_clock, const mcu_pin_obj_t* word_select, - const mcu_pin_obj_t* data, bool left_justified) { - if (instance) +void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t *self, + const mcu_pin_obj_t *bit_clock, const mcu_pin_obj_t *word_select, + const mcu_pin_obj_t *data, bool left_justified) { + if (instance) { mp_raise_RuntimeError(translate("Device in use")); + } instance = self; claim_pin(bit_clock); @@ -216,11 +229,11 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, supervisor_enable_tick(); } -bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t *self) { return self->data_pin_number == 0xff; } -void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t *self) { if (common_hal_audiobusio_i2sout_deinited(self)) { return; } @@ -236,8 +249,8 @@ void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { supervisor_disable_tick(); } -void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, - mp_obj_t sample, bool loop) { +void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t *self, + mp_obj_t sample, bool loop) { if (common_hal_audiobusio_i2sout_get_playing(self)) { common_hal_audiobusio_i2sout_stop(self); } @@ -271,7 +284,7 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, */ enum { buffer_length_ms = 16 }; self->buffer_length = sample_rate * buffer_length_ms - * self->bytes_per_sample * self->channel_count / 1000; + * self->bytes_per_sample * self->channel_count / 1000; self->buffer_length = (self->buffer_length + 3) & ~3; self->buffers[0] = m_malloc(self->buffer_length, false); self->buffers[1] = m_malloc(self->buffer_length, false); @@ -297,25 +310,25 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, i2s_background(); } -void common_hal_audiobusio_i2sout_pause(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_pause(audiobusio_i2sout_obj_t *self) { self->paused = true; } -void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t *self) { self->paused = false; } -bool common_hal_audiobusio_i2sout_get_paused(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_get_paused(audiobusio_i2sout_obj_t *self) { return self->paused; } -void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t *self) { NRF_I2S->TASKS_STOP = 1; self->stopping = true; NRF_I2S->INTENCLR = I2S_INTENSET_TXPTRUPD_Msk; } -bool common_hal_audiobusio_i2sout_get_playing(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_get_playing(audiobusio_i2sout_obj_t *self) { if (NRF_I2S->EVENTS_STOPPED) { self->playing = false; NRF_I2S->EVENTS_STOPPED = 0; diff --git a/ports/nrf/common-hal/audiobusio/PDMIn.c b/ports/nrf/common-hal/audiobusio/PDMIn.c index ddd34174b..47d736577 100644 --- a/ports/nrf/common-hal/audiobusio/PDMIn.c +++ b/ports/nrf/common-hal/audiobusio/PDMIn.c @@ -35,13 +35,13 @@ NRF_PDM_Type *nrf_pdm = NRF_PDM; static uint32_t dummy_buffer[4]; // Caller validates that pins are free. -void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, - const mcu_pin_obj_t* clock_pin, - const mcu_pin_obj_t* data_pin, - uint32_t sample_rate, - uint8_t bit_depth, - bool mono, - uint8_t oversample) { +void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t *self, + const mcu_pin_obj_t *clock_pin, + const mcu_pin_obj_t *data_pin, + uint32_t sample_rate, + uint8_t bit_depth, + bool mono, + uint8_t oversample) { claim_pin(clock_pin); claim_pin(data_pin); @@ -68,11 +68,11 @@ void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, nrf_pdm->TASKS_START = 1; } -bool common_hal_audiobusio_pdmin_deinited(audiobusio_pdmin_obj_t* self) { +bool common_hal_audiobusio_pdmin_deinited(audiobusio_pdmin_obj_t *self) { return !self->clock_pin_number; } -void common_hal_audiobusio_pdmin_deinit(audiobusio_pdmin_obj_t* self) { +void common_hal_audiobusio_pdmin_deinit(audiobusio_pdmin_obj_t *self) { nrf_pdm->ENABLE = 0; reset_pin_number(self->clock_pin_number); @@ -81,16 +81,16 @@ void common_hal_audiobusio_pdmin_deinit(audiobusio_pdmin_obj_t* self) { self->data_pin_number = 0; } -uint8_t common_hal_audiobusio_pdmin_get_bit_depth(audiobusio_pdmin_obj_t* self) { +uint8_t common_hal_audiobusio_pdmin_get_bit_depth(audiobusio_pdmin_obj_t *self) { return 16; } -uint32_t common_hal_audiobusio_pdmin_get_sample_rate(audiobusio_pdmin_obj_t* self) { +uint32_t common_hal_audiobusio_pdmin_get_sample_rate(audiobusio_pdmin_obj_t *self) { return 16000; } -uint32_t common_hal_audiobusio_pdmin_record_to_buffer(audiobusio_pdmin_obj_t* self, - uint16_t* output_buffer, uint32_t output_buffer_length) { +uint32_t common_hal_audiobusio_pdmin_record_to_buffer(audiobusio_pdmin_obj_t *self, + uint16_t *output_buffer, uint32_t output_buffer_length) { // Note: Adafruit's module has SELECT pulled to GND, which makes the DATA // valid when the CLK is low, therefore it must be sampled on the rising edge. if (self->mono) { @@ -113,11 +113,11 @@ uint32_t common_hal_audiobusio_pdmin_record_to_buffer(audiobusio_pdmin_obj_t* se // Step 3. wait for PDM to end while (!nrf_pdm->EVENTS_END) { - MICROPY_VM_HOOK_LOOP; + MICROPY_VM_HOOK_LOOP; } // Step 4. They want unsigned - for (uint32_t i=0; i<output_buffer_length; i++) { + for (uint32_t i = 0; i < output_buffer_length; i++) { output_buffer[i] += 32768; } diff --git a/ports/nrf/common-hal/audiopwmio/PWMAudioOut.c b/ports/nrf/common-hal/audiopwmio/PWMAudioOut.c index 802f2bdc2..c3da51945 100644 --- a/ports/nrf/common-hal/audiopwmio/PWMAudioOut.c +++ b/ports/nrf/common-hal/audiopwmio/PWMAudioOut.c @@ -40,7 +40,7 @@ #include "supervisor/shared/translate.h" // TODO: This should be the same size as PWMOut.c:pwms[], but there's no trivial way to accomplish that -STATIC audiopwmio_pwmaudioout_obj_t* active_audio[4]; +STATIC audiopwmio_pwmaudioout_obj_t *active_audio[4]; #define F_TARGET (62500) #define F_PWM (16000000) @@ -55,17 +55,17 @@ STATIC uint32_t calculate_pwm_parameters(uint32_t sample_rate, uint32_t *top_out // the desired frequency is the closest integer multiple of sample_rate not less than F_TARGET uint32_t desired_frequency = (F_TARGET + sample_rate - 1) / sample_rate * sample_rate; // The top value is the PWM frequency divided by the desired frequency (round to nearest) - uint32_t top = (F_PWM + desired_frequency/2) / desired_frequency; + uint32_t top = (F_PWM + desired_frequency / 2) / desired_frequency; // The actual frequency is the PWM frequency divided by the top value (round to nearest) - uint32_t actual_frequency = (F_PWM + top/2) / top; + uint32_t actual_frequency = (F_PWM + top / 2) / top; // The multiplier is the actual frequency divided by the sample rate (round to nearest) - uint32_t multiplier = (actual_frequency + sample_rate/2) / sample_rate; + uint32_t multiplier = (actual_frequency + sample_rate / 2) / sample_rate; *top_out = top; return multiplier - 1; } STATIC void activate_audiopwmout_obj(audiopwmio_pwmaudioout_obj_t *self) { - for (size_t i=0; i < MP_ARRAY_SIZE(active_audio); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(active_audio); i++) { if (!active_audio[i]) { active_audio[i] = self; supervisor_enable_tick(); @@ -76,7 +76,7 @@ STATIC void activate_audiopwmout_obj(audiopwmio_pwmaudioout_obj_t *self) { STATIC void deactivate_audiopwmout_obj(audiopwmio_pwmaudioout_obj_t *self) { // Turn off the interrupts to the CPU. self->pwm->INTENCLR = PWM_INTENSET_SEQSTARTED0_Msk | PWM_INTENSET_SEQSTARTED1_Msk; - for (size_t i=0; i < MP_ARRAY_SIZE(active_audio); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(active_audio); i++) { if (active_audio[i] == self) { active_audio[i] = NULL; supervisor_disable_tick(); @@ -85,7 +85,7 @@ STATIC void deactivate_audiopwmout_obj(audiopwmio_pwmaudioout_obj_t *self) { } void audiopwmout_reset() { - for (size_t i=0; i < MP_ARRAY_SIZE(active_audio); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(active_audio); i++) { if (active_audio[i]) { supervisor_disable_tick(); } @@ -99,7 +99,7 @@ STATIC void fill_buffers(audiopwmio_pwmaudioout_obj_t *self, int buf) { uint32_t buffer_length; audioio_get_buffer_result_t get_buffer_result = audiosample_get_buffer(self->sample, false, 0, - &buffer, &buffer_length); + &buffer, &buffer_length); if (get_buffer_result == GET_BUFFER_ERROR) { common_hal_audiopwmio_pwmaudioout_stop(self); return; @@ -114,23 +114,25 @@ STATIC void fill_buffers(audiopwmio_pwmaudioout_obj_t *self, int buf) { uint8_t rawval = (*buffer++ + offset); uint16_t val = (uint16_t)(((uint32_t)rawval * (uint32_t)scale) >> 8); *dev_buffer++ = val; - if (self->sample_channel_count == 1) + if (self->sample_channel_count == 1) { *dev_buffer++ = val; + } } } else { uint16_t offset = self->signed_to_unsigned ? 0x8000 : 0; uint16_t scale = self->scale; - uint16_t *buffer16 = (uint16_t*)buffer; + uint16_t *buffer16 = (uint16_t *)buffer; while (dev_buffer < end_dev_buffer) { uint16_t rawval = (*buffer16++ + offset); uint16_t val = (uint16_t)((rawval * (uint32_t)scale) >> 16); *dev_buffer++ = val; - if (self->sample_channel_count == 1) + if (self->sample_channel_count == 1) { *dev_buffer++ = val; + } } } self->pwm->SEQ[buf].PTR = (intptr_t)self->buffers[buf]; - self->pwm->SEQ[buf].CNT = num_samples*2; + self->pwm->SEQ[buf].CNT = num_samples * 2; if (self->loop && get_buffer_result == GET_BUFFER_DONE) { audiosample_reset_buffer(self->sample, false, 0); @@ -141,14 +143,16 @@ STATIC void fill_buffers(audiopwmio_pwmaudioout_obj_t *self, int buf) { } STATIC void audiopwmout_background_obj(audiopwmio_pwmaudioout_obj_t *self) { - if (!common_hal_audiopwmio_pwmaudioout_get_playing(self)) + if (!common_hal_audiopwmio_pwmaudioout_get_playing(self)) { return; + } if (self->stopping) { bool stopped = (self->pwm->EVENTS_SEQEND[0] || !self->pwm->EVENTS_SEQSTARTED[0]) && (self->pwm->EVENTS_SEQEND[1] || !self->pwm->EVENTS_SEQSTARTED[1]); - if (stopped) + if (stopped) { self->pwm->TASKS_STOP = 1; + } } else if (!self->paused && !self->single_buffer) { if (self->pwm->EVENTS_SEQSTARTED[0]) { fill_buffers(self, 1); @@ -171,17 +175,19 @@ void audiopwmout_background() { return; } // Check our objects because the PWM could be active for some other reason. - for (size_t i=0; i < MP_ARRAY_SIZE(active_audio); i++) { - if (!active_audio[i]) continue; + for (size_t i = 0; i < MP_ARRAY_SIZE(active_audio); i++) { + if (!active_audio[i]) { + continue; + } audiopwmout_background_obj(active_audio[i]); } } // Caller validates that pins are free. -void common_hal_audiopwmio_pwmaudioout_construct(audiopwmio_pwmaudioout_obj_t* self, - const mcu_pin_obj_t* left_channel, const mcu_pin_obj_t* right_channel, uint16_t quiescent_value) { +void common_hal_audiopwmio_pwmaudioout_construct(audiopwmio_pwmaudioout_obj_t *self, + const mcu_pin_obj_t *left_channel, const mcu_pin_obj_t *right_channel, uint16_t quiescent_value) { self->pwm = pwmout_allocate(256, PWM_PRESCALER_PRESCALER_DIV_1, true, NULL, NULL, - &self->pwm_irq); + &self->pwm_irq); if (!self->pwm) { mp_raise_RuntimeError(translate("All timers in use")); } @@ -197,8 +203,7 @@ void common_hal_audiopwmio_pwmaudioout_construct(audiopwmio_pwmaudioout_obj_t* s self->pwm->PSEL.OUT[0] = self->left_channel_number = left_channel->number; claim_pin(left_channel); - if (right_channel) - { + if (right_channel) { self->pwm->PSEL.OUT[2] = self->right_channel_number = right_channel->number; claim_pin(right_channel); } @@ -209,11 +214,11 @@ void common_hal_audiopwmio_pwmaudioout_construct(audiopwmio_pwmaudioout_obj_t* s // TODO: Ramp from 0 to quiescent value } -bool common_hal_audiopwmio_pwmaudioout_deinited(audiopwmio_pwmaudioout_obj_t* self) { +bool common_hal_audiopwmio_pwmaudioout_deinited(audiopwmio_pwmaudioout_obj_t *self) { return !self->pwm; } -void common_hal_audiopwmio_pwmaudioout_deinit(audiopwmio_pwmaudioout_obj_t* self) { +void common_hal_audiopwmio_pwmaudioout_deinit(audiopwmio_pwmaudioout_obj_t *self) { if (common_hal_audiopwmio_pwmaudioout_deinited(self)) { return; } @@ -222,10 +227,12 @@ void common_hal_audiopwmio_pwmaudioout_deinit(audiopwmio_pwmaudioout_obj_t* self // TODO: ramp the pwm down from quiescent value to 0 self->pwm->ENABLE = 0; - if (self->left_channel_number) + if (self->left_channel_number) { reset_pin_number(self->left_channel_number); - if (self->right_channel_number) + } + if (self->right_channel_number) { reset_pin_number(self->right_channel_number); + } pwmout_free_channel(self->pwm, 0); pwmout_free_channel(self->pwm, 2); @@ -239,7 +246,7 @@ void common_hal_audiopwmio_pwmaudioout_deinit(audiopwmio_pwmaudioout_obj_t* self self->buffers[1] = NULL; } -void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t* self, mp_obj_t sample, bool loop) { +void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t *self, mp_obj_t sample, bool loop) { if (common_hal_audiopwmio_pwmaudioout_get_playing(self)) { common_hal_audiopwmio_pwmaudioout_stop(self); } @@ -261,13 +268,14 @@ void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t* self, } uint16_t buffer_length = (uint16_t)max_buffer_length; self->buffers[0] = m_malloc(buffer_length * 2 * sizeof(uint16_t), false); - if (!self->single_buffer) + if (!self->single_buffer) { self->buffers[1] = m_malloc(buffer_length * 2 * sizeof(uint16_t), false); + } uint32_t top; self->pwm->SEQ[0].REFRESH = self->pwm->SEQ[1].REFRESH = calculate_pwm_parameters(sample_rate, &top); - self->scale = top-1; + self->scale = top - 1; self->pwm->COUNTERTOP = top; self->pwm->LOOP = 1; @@ -291,7 +299,7 @@ void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t* self, self->paused = false; } -void common_hal_audiopwmio_pwmaudioout_stop(audiopwmio_pwmaudioout_obj_t* self) { +void common_hal_audiopwmio_pwmaudioout_stop(audiopwmio_pwmaudioout_obj_t *self) { deactivate_audiopwmout_obj(self); self->pwm->TASKS_STOP = 1; self->stopping = false; @@ -304,7 +312,7 @@ void common_hal_audiopwmio_pwmaudioout_stop(audiopwmio_pwmaudioout_obj_t* self) self->buffers[1] = NULL; } -bool common_hal_audiopwmio_pwmaudioout_get_playing(audiopwmio_pwmaudioout_obj_t* self) { +bool common_hal_audiopwmio_pwmaudioout_get_playing(audiopwmio_pwmaudioout_obj_t *self) { if (!self->paused && self->pwm->EVENTS_STOPPED) { self->playing = false; self->pwm->EVENTS_STOPPED = 0; @@ -328,12 +336,12 @@ bool common_hal_audiopwmio_pwmaudioout_get_playing(audiopwmio_pwmaudioout_obj_t* * feels instant. (This also saves on memory, for long in-memory "single buffer" * samples, since we have to locally take a resampled copy!) */ -void common_hal_audiopwmio_pwmaudioout_pause(audiopwmio_pwmaudioout_obj_t* self) { +void common_hal_audiopwmio_pwmaudioout_pause(audiopwmio_pwmaudioout_obj_t *self) { self->paused = true; self->pwm->SHORTS = NRF_PWM_SHORT_SEQEND1_STOP_MASK; } -void common_hal_audiopwmio_pwmaudioout_resume(audiopwmio_pwmaudioout_obj_t* self) { +void common_hal_audiopwmio_pwmaudioout_resume(audiopwmio_pwmaudioout_obj_t *self) { self->paused = false; self->pwm->SHORTS = NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK; if (self->pwm->EVENTS_STOPPED) { @@ -342,6 +350,6 @@ void common_hal_audiopwmio_pwmaudioout_resume(audiopwmio_pwmaudioout_obj_t* self } } -bool common_hal_audiopwmio_pwmaudioout_get_paused(audiopwmio_pwmaudioout_obj_t* self) { +bool common_hal_audiopwmio_pwmaudioout_get_paused(audiopwmio_pwmaudioout_obj_t *self) { return self->paused; } diff --git a/ports/nrf/common-hal/busio/I2C.c b/ports/nrf/common-hal/busio/I2C.c index 654fa857f..de9417a6c 100644 --- a/ports/nrf/common-hal/busio/I2C.c +++ b/ports/nrf/common-hal/busio/I2C.c @@ -42,24 +42,22 @@ #define I2C_MAX_XFER_LEN ((1UL << TWIM0_EASYDMA_MAXCNT_SIZE) - 1) STATIC twim_peripheral_t twim_peripherals[] = { -#if NRFX_CHECK(NRFX_TWIM0_ENABLED) + #if NRFX_CHECK(NRFX_TWIM0_ENABLED) // SPIM0 and TWIM0 share an address. { .twim = NRFX_TWIM_INSTANCE(0), - .in_use = false - }, -#endif -#if NRFX_CHECK(NRFX_TWIM1_ENABLED) + .in_use = false}, + #endif + #if NRFX_CHECK(NRFX_TWIM1_ENABLED) // SPIM1 and TWIM1 share an address. { .twim = NRFX_TWIM_INSTANCE(1), - .in_use = false - }, -#endif + .in_use = false}, + #endif }; STATIC bool never_reset[MP_ARRAY_SIZE(twim_peripherals)]; void i2c_reset(void) { - for (size_t i = 0 ; i < MP_ARRAY_SIZE(twim_peripherals); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(twim_peripherals); i++) { if (never_reset[i]) { continue; } @@ -69,7 +67,7 @@ void i2c_reset(void) { } void common_hal_busio_i2c_never_reset(busio_i2c_obj_t *self) { - for (size_t i = 0 ; i < MP_ARRAY_SIZE(twim_peripherals); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(twim_peripherals); i++) { if (self->twim_peripheral == &twim_peripherals[i]) { never_reset[i] = true; @@ -82,15 +80,15 @@ void common_hal_busio_i2c_never_reset(busio_i2c_obj_t *self) { static uint8_t twi_error_to_mp(const nrfx_err_t err) { switch (err) { - case NRFX_ERROR_DRV_TWI_ERR_ANACK: - return MP_ENODEV; - case NRFX_ERROR_BUSY: - return MP_EBUSY; - case NRFX_ERROR_DRV_TWI_ERR_DNACK: - case NRFX_ERROR_INVALID_ADDR: - return MP_EIO; - default: - break; + case NRFX_ERROR_DRV_TWI_ERR_ANACK: + return MP_ENODEV; + case NRFX_ERROR_BUSY: + return MP_EBUSY; + case NRFX_ERROR_DRV_TWI_ERR_DNACK: + case NRFX_ERROR_INVALID_ADDR: + return MP_EIO; + default: + break; } return 0; @@ -103,7 +101,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const mcu_pin_obj_t * // Find a free instance. self->twim_peripheral = NULL; - for (size_t i = 0 ; i < MP_ARRAY_SIZE(twim_peripherals); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(twim_peripherals); i++) { if (!twim_peripherals[i].in_use) { self->twim_peripheral = &twim_peripherals[i]; // Mark it as in_use later after other validation is finished. @@ -115,7 +113,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const mcu_pin_obj_t * mp_raise_ValueError(translate("All I2C peripherals are in use")); } -#if CIRCUITPY_REQUIRE_I2C_PULLUPS + #if CIRCUITPY_REQUIRE_I2C_PULLUPS // Test that the pins are in a high state. (Hopefully indicating they are pulled up.) nrf_gpio_cfg_input(scl->number, NRF_GPIO_PIN_PULLDOWN); nrf_gpio_cfg_input(sda->number, NRF_GPIO_PIN_PULLDOWN); @@ -133,19 +131,19 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const mcu_pin_obj_t * reset_pin_number(scl->number); mp_raise_RuntimeError(translate("No pull up found on SDA or SCL; check your wiring")); } -#endif + #endif nrfx_twim_config_t config = NRFX_TWIM_DEFAULT_CONFIG(scl->number, sda->number); -#if defined(TWIM_FREQUENCY_FREQUENCY_K1000) + #if defined(TWIM_FREQUENCY_FREQUENCY_K1000) if (frequency >= 1000000) { config.frequency = NRF_TWIM_FREQ_1000K; } else -#endif + #endif if (frequency >= 400000) { - config.frequency = NRF_TWIM_FREQ_400K; + config.frequency = NRF_TWIM_FREQ_400K; } else if (frequency >= 250000) { - config.frequency = NRF_TWIM_FREQ_250K; + config.frequency = NRF_TWIM_FREQ_250K; } else { config.frequency = NRF_TWIM_FREQ_100K; } @@ -198,11 +196,15 @@ bool common_hal_busio_i2c_probe(busio_i2c_obj_t *self, uint8_t addr) { nrf_twim_task_trigger(reg, NRF_TWIM_TASK_STARTTX); while (nrf_twim_event_check(reg, NRF_TWIM_EVENT_TXSTARTED) == 0 && - nrf_twim_event_check(reg, NRF_TWIM_EVENT_ERROR) == 0); + nrf_twim_event_check(reg, NRF_TWIM_EVENT_ERROR) == 0) { + ; + } nrf_twim_event_clear(reg, NRF_TWIM_EVENT_TXSTARTED); nrf_twim_task_trigger(reg, NRF_TWIM_TASK_STOP); - while (nrf_twim_event_check(reg, NRF_TWIM_EVENT_STOPPED) == 0); + while (nrf_twim_event_check(reg, NRF_TWIM_EVENT_STOPPED) == 0) { + ; + } nrf_twim_event_clear(reg, NRF_TWIM_EVENT_STOPPED); if (nrf_twim_event_check(reg, NRF_TWIM_EVENT_ERROR)) { @@ -237,7 +239,7 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) { } uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, const uint8_t *data, size_t len, bool stopBit) { - if(len == 0) { + if (len == 0) { return common_hal_busio_i2c_probe(self, addr) ? 0 : MP_ENODEV; } @@ -246,12 +248,12 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, const u nrfx_twim_enable(&self->twim_peripheral->twim); // break into MAX_XFER_LEN transaction - while ( len ) { + while (len) { const size_t xact_len = MIN(len, I2C_MAX_XFER_LEN); - nrfx_twim_xfer_desc_t xfer_desc = NRFX_TWIM_XFER_DESC_TX(addr, (uint8_t*) data, xact_len); + nrfx_twim_xfer_desc_t xfer_desc = NRFX_TWIM_XFER_DESC_TX(addr, (uint8_t *)data, xact_len); uint32_t const flags = (stopBit ? 0 : NRFX_TWIM_FLAG_TX_NO_STOP); - if ( NRFX_SUCCESS != (err = nrfx_twim_xfer(&self->twim_peripheral->twim, &xfer_desc, flags)) ) { + if (NRFX_SUCCESS != (err = nrfx_twim_xfer(&self->twim_peripheral->twim, &xfer_desc, flags))) { break; } @@ -265,7 +267,7 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, const u } uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, uint8_t *data, size_t len) { - if(len == 0) { + if (len == 0) { return 0; } @@ -274,11 +276,11 @@ uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, uint8_t nrfx_twim_enable(&self->twim_peripheral->twim); // break into MAX_XFER_LEN transaction - while ( len ) { + while (len) { const size_t xact_len = MIN(len, I2C_MAX_XFER_LEN); nrfx_twim_xfer_desc_t xfer_desc = NRFX_TWIM_XFER_DESC_RX(addr, data, xact_len); - if ( NRFX_SUCCESS != (err = nrfx_twim_xfer(&self->twim_peripheral->twim, &xfer_desc, 0)) ) { + if (NRFX_SUCCESS != (err = nrfx_twim_xfer(&self->twim_peripheral->twim, &xfer_desc, 0))) { break; } diff --git a/ports/nrf/common-hal/busio/I2C.h b/ports/nrf/common-hal/busio/I2C.h index b75d15f00..04bc57868 100644 --- a/ports/nrf/common-hal/busio/I2C.h +++ b/ports/nrf/common-hal/busio/I2C.h @@ -38,7 +38,7 @@ typedef struct { typedef struct { mp_obj_base_t base; - twim_peripheral_t* twim_peripheral; + twim_peripheral_t *twim_peripheral; bool has_lock; uint8_t scl_pin_number; uint8_t sda_pin_number; diff --git a/ports/nrf/common-hal/busio/SPI.c b/ports/nrf/common-hal/busio/SPI.c index 1cf074955..309e1bce1 100644 --- a/ports/nrf/common-hal/busio/SPI.c +++ b/ports/nrf/common-hal/busio/SPI.c @@ -52,45 +52,41 @@ // These are in order from highest available frequency to lowest (32MHz first, then 8MHz). STATIC spim_peripheral_t spim_peripherals[] = { -#if NRFX_CHECK(NRFX_SPIM3_ENABLED) + #if NRFX_CHECK(NRFX_SPIM3_ENABLED) // SPIM3 exists only on nRF52840 and supports 32MHz max. All other SPIM's are only 8MHz max. // Allocate SPIM3 first. { .spim = NRFX_SPIM_INSTANCE(3), .max_frequency = 32000000, - .max_xfer_size = MIN(SPIM3_BUFFER_RAM_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1) - }, -#endif -#if NRFX_CHECK(NRFX_SPIM2_ENABLED) + .max_xfer_size = MIN(SPIM3_BUFFER_RAM_SIZE, (1UL << SPIM3_EASYDMA_MAXCNT_SIZE) - 1)}, + #endif + #if NRFX_CHECK(NRFX_SPIM2_ENABLED) // SPIM2 is not shared with a TWIM, so allocate before the shared ones. { .spim = NRFX_SPIM_INSTANCE(2), .max_frequency = 8000000, - .max_xfer_size = (1UL << SPIM2_EASYDMA_MAXCNT_SIZE) - 1 - }, -#endif -#if NRFX_CHECK(NRFX_SPIM1_ENABLED) + .max_xfer_size = (1UL << SPIM2_EASYDMA_MAXCNT_SIZE) - 1}, + #endif + #if NRFX_CHECK(NRFX_SPIM1_ENABLED) // SPIM1 and TWIM1 share an address. { .spim = NRFX_SPIM_INSTANCE(1), .max_frequency = 8000000, - .max_xfer_size = (1UL << SPIM1_EASYDMA_MAXCNT_SIZE) - 1 - }, -#endif -#if NRFX_CHECK(NRFX_SPIM0_ENABLED) + .max_xfer_size = (1UL << SPIM1_EASYDMA_MAXCNT_SIZE) - 1}, + #endif + #if NRFX_CHECK(NRFX_SPIM0_ENABLED) // SPIM0 and TWIM0 share an address. { .spim = NRFX_SPIM_INSTANCE(0), .max_frequency = 8000000, - .max_xfer_size = (1UL << SPIM0_EASYDMA_MAXCNT_SIZE) - 1 - }, -#endif + .max_xfer_size = (1UL << SPIM0_EASYDMA_MAXCNT_SIZE) - 1}, + #endif }; STATIC bool never_reset[MP_ARRAY_SIZE(spim_peripherals)]; // Separate RAM area for SPIM3 transmit buffer to avoid SPIM3 hardware errata. // https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF52840_Rev2%2FERR%2FnRF52840%2FRev2%2Flatest%2Fanomaly_840_198.html -STATIC uint8_t *spim3_transmit_buffer = (uint8_t *) SPIM3_BUFFER_RAM_START_ADDR; +STATIC uint8_t *spim3_transmit_buffer = (uint8_t *)SPIM3_BUFFER_RAM_START_ADDR; void spi_reset(void) { - for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(spim_peripherals); i++) { if (never_reset[i]) { continue; } @@ -99,7 +95,7 @@ void spi_reset(void) { } void common_hal_busio_spi_never_reset(busio_spi_obj_t *self) { - for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(spim_peripherals); i++) { if (self->spim_peripheral == &spim_peripherals[i]) { never_reset[i] = true; @@ -119,12 +115,12 @@ static nrf_spim_frequency_t baudrate_to_spim_frequency(const uint32_t baudrate) const uint32_t boundary; nrf_spim_frequency_t spim_frequency; } baudrate_map[] = { -#ifdef SPIM_FREQUENCY_FREQUENCY_M32 + #ifdef SPIM_FREQUENCY_FREQUENCY_M32 { 32000000, NRF_SPIM_FREQ_32M }, -#endif -#ifdef SPIM_FREQUENCY_FREQUENCY_M16 + #endif + #ifdef SPIM_FREQUENCY_FREQUENCY_M16 { 16000000, NRF_SPIM_FREQ_16M }, -#endif + #endif { 8000000, NRF_SPIM_FREQ_8M }, { 4000000, NRF_SPIM_FREQ_4M }, { 2000000, NRF_SPIM_FREQ_2M }, @@ -147,10 +143,10 @@ static nrf_spim_frequency_t baudrate_to_spim_frequency(const uint32_t baudrate) return 0; } -void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi, const mcu_pin_obj_t * miso) { +void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, const mcu_pin_obj_t *miso) { // Find a free instance, with most desirable (highest freq and not shared) allocated first. self->spim_peripheral = NULL; - for (size_t i = 0 ; i < MP_ARRAY_SIZE(spim_peripherals); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(spim_peripherals); i++) { if ((spim_peripherals[i].spim.p_reg->ENABLE & SPIM_ENABLE_ENABLE_Msk) == 0) { self->spim_peripheral = &spim_peripherals[i]; break; @@ -162,7 +158,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, const mcu_pin_obj_t * } nrfx_spim_config_t config = NRFX_SPIM_DEFAULT_CONFIG(NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED, - NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED); + NRFX_SPIM_PIN_NOT_USED, NRFX_SPIM_PIN_NOT_USED); config.frequency = baudrate_to_spim_frequency(self->spim_peripheral->max_frequency); @@ -198,8 +194,9 @@ bool common_hal_busio_spi_deinited(busio_spi_obj_t *self) { } void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { - if (common_hal_busio_spi_deinited(self)) + if (common_hal_busio_spi_deinited(self)) { return; + } nrfx_spim_uninit(&self->spim_peripheral->spim); @@ -211,12 +208,12 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { bool common_hal_busio_spi_configure(busio_spi_obj_t *self, uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { // nrf52 does not support 16 bit if (bits != 8) { - return false; + return false; } // Set desired frequency, rounding down, and don't go above available frequency for this SPIM. nrf_spim_frequency_set(self->spim_peripheral->spim.p_reg, - baudrate_to_spim_frequency(MIN(baudrate, self->spim_peripheral->max_frequency))); + baudrate_to_spim_frequency(MIN(baudrate, self->spim_peripheral->max_frequency))); nrf_spim_mode_t mode = NRF_SPIM_MODE_0; if (polarity) { @@ -251,7 +248,7 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) { bool common_hal_busio_spi_write(busio_spi_obj_t *self, const uint8_t *data, size_t len) { const bool is_spim3 = self->spim_peripheral->spim.p_reg == NRF_SPIM3; - uint8_t *next_chunk = (uint8_t *) data; + uint8_t *next_chunk = (uint8_t *)data; while (len > 0) { size_t chunk_size = MIN(len, self->spim_peripheral->max_xfer_size); @@ -301,7 +298,7 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou } const nrfx_spim_xfer_desc_t xfer = NRFX_SPIM_SINGLE_XFER(next_chunk_out, chunk_size, - next_chunk_in, chunk_size); + next_chunk_in, chunk_size); if (nrfx_spim_xfer(&self->spim_peripheral->spim, &xfer, 0) != NRFX_SUCCESS) { return false; } @@ -313,39 +310,39 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou return true; } -uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) { +uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) { switch (self->spim_peripheral->spim.p_reg->FREQUENCY) { - case NRF_SPIM_FREQ_125K: - return 125000; - case NRF_SPIM_FREQ_250K: - return 250000; - case NRF_SPIM_FREQ_500K: - return 500000; - case NRF_SPIM_FREQ_1M: - return 1000000; - case NRF_SPIM_FREQ_2M: - return 2000000; - case NRF_SPIM_FREQ_4M: - return 4000000; - case NRF_SPIM_FREQ_8M: - return 8000000; -#ifdef SPIM_FREQUENCY_FREQUENCY_M16 - case NRF_SPIM_FREQ_16M: - return 16000000; -#endif -#ifdef SPIM_FREQUENCY_FREQUENCY_M32 - case NRF_SPIM_FREQ_32M: - return 32000000; -#endif - default: - return 0; + case NRF_SPIM_FREQ_125K: + return 125000; + case NRF_SPIM_FREQ_250K: + return 250000; + case NRF_SPIM_FREQ_500K: + return 500000; + case NRF_SPIM_FREQ_1M: + return 1000000; + case NRF_SPIM_FREQ_2M: + return 2000000; + case NRF_SPIM_FREQ_4M: + return 4000000; + case NRF_SPIM_FREQ_8M: + return 8000000; + #ifdef SPIM_FREQUENCY_FREQUENCY_M16 + case NRF_SPIM_FREQ_16M: + return 16000000; + #endif + #ifdef SPIM_FREQUENCY_FREQUENCY_M32 + case NRF_SPIM_FREQ_32M: + return 32000000; + #endif + default: + return 0; } } -uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) { return (self->spim_peripheral->spim.p_reg->CONFIG & SPIM_CONFIG_CPHA_Msk) >> SPIM_CONFIG_CPHA_Pos; } -uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) { return (self->spim_peripheral->spim.p_reg->CONFIG & SPIM_CONFIG_CPOL_Msk) >> SPIM_CONFIG_CPOL_Pos; } diff --git a/ports/nrf/common-hal/busio/SPI.h b/ports/nrf/common-hal/busio/SPI.h index ef3ac9531..796ff59f9 100644 --- a/ports/nrf/common-hal/busio/SPI.h +++ b/ports/nrf/common-hal/busio/SPI.h @@ -38,7 +38,7 @@ typedef struct { typedef struct { mp_obj_base_t base; - spim_peripheral_t* spim_peripheral; + spim_peripheral_t *spim_peripheral; bool has_lock; uint8_t clock_pin_number; uint8_t MOSI_pin_number; diff --git a/ports/nrf/common-hal/busio/UART.c b/ports/nrf/common-hal/busio/UART.c index 491e360e4..6436cb4e7 100644 --- a/ports/nrf/common-hal/busio/UART.c +++ b/ports/nrf/common-hal/busio/UART.c @@ -41,23 +41,23 @@ // expression to examine, and return value in case of failing #define _VERIFY_ERR(_exp) \ - do {\ - uint32_t _err = (_exp);\ - if (NRFX_SUCCESS != _err ) {\ - mp_raise_msg_varg(&mp_type_RuntimeError, translate("error = 0x%08lX"), _err);\ - }\ - }while(0) + do { \ + uint32_t _err = (_exp); \ + if (NRFX_SUCCESS != _err) { \ + mp_raise_msg_varg(&mp_type_RuntimeError, translate("error = 0x%08lX"), _err); \ + } \ + } while (0) static nrfx_uarte_t nrfx_uartes[] = { -#if NRFX_CHECK(NRFX_UARTE0_ENABLED) + #if NRFX_CHECK(NRFX_UARTE0_ENABLED) NRFX_UARTE_INSTANCE(0), -#endif -#if NRFX_CHECK(NRFX_UARTE1_ENABLED) + #endif + #if NRFX_CHECK(NRFX_UARTE1_ENABLED) NRFX_UARTE_INSTANCE(1), -#endif + #endif }; -static uint32_t get_nrf_baud (uint32_t baudrate) { +static uint32_t get_nrf_baud(uint32_t baudrate) { static const struct { const uint32_t boundary; @@ -70,9 +70,9 @@ static uint32_t get_nrf_baud (uint32_t baudrate) { { 14400, NRF_UARTE_BAUDRATE_14400 }, { 19200, NRF_UARTE_BAUDRATE_19200 }, { 28800, NRF_UARTE_BAUDRATE_28800 }, - { 31250, NRF_UARTE_BAUDRATE_31250 }, + { 31250, NRF_UARTE_BAUDRATE_31250 }, { 38400, NRF_UARTE_BAUDRATE_38400 }, - { 56000, NRF_UARTE_BAUDRATE_56000 }, + { 56000, NRF_UARTE_BAUDRATE_56000 }, { 57600, NRF_UARTE_BAUDRATE_57600 }, { 76800, NRF_UARTE_BAUDRATE_76800 }, { 115200, NRF_UARTE_BAUDRATE_115200 }, @@ -94,26 +94,26 @@ static uint32_t get_nrf_baud (uint32_t baudrate) { } while (true); } -static void uart_callback_irq (const nrfx_uarte_event_t * event, void * context) { - busio_uart_obj_t* self = (busio_uart_obj_t*) context; +static void uart_callback_irq(const nrfx_uarte_event_t *event, void *context) { + busio_uart_obj_t *self = (busio_uart_obj_t *)context; - switch ( event->type ) { + switch (event->type) { case NRFX_UARTE_EVT_RX_DONE: if (ringbuf_num_empty(&self->ringbuf) >= event->data.rxtx.bytes) { ringbuf_put_n(&self->ringbuf, event->data.rxtx.p_data, event->data.rxtx.bytes); // keep receiving - (void) nrfx_uarte_rx(self->uarte, &self->rx_char, 1); + (void)nrfx_uarte_rx(self->uarte, &self->rx_char, 1); } else { // receive buffer full, suspend self->rx_paused = true; nrf_gpio_pin_write(self->rts_pin_number, true); } - break; + break; case NRFX_UARTE_EVT_TX_DONE: // nothing to do - break; + break; case NRFX_UARTE_EVT_ERROR: // Possible Error source is Overrun, Parity, Framing, Break @@ -122,26 +122,26 @@ static void uart_callback_irq (const nrfx_uarte_event_t * event, void * context) ringbuf_put_n(&self->ringbuf, event->data.error.rxtx.p_data, event->data.error.rxtx.bytes); // Keep receiving - (void) nrfx_uarte_rx(self->uarte, &self->rx_char, 1); - break; + (void)nrfx_uarte_rx(self->uarte, &self->rx_char, 1); + break; default: - break; + break; } } void uart_reset(void) { - for (size_t i = 0 ; i < MP_ARRAY_SIZE(nrfx_uartes); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(nrfx_uartes); i++) { nrfx_uarte_uninit(&nrfx_uartes[i]); } } void common_hal_busio_uart_construct(busio_uart_obj_t *self, - const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx, - const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts, - const mcu_pin_obj_t * rs485_dir, bool rs485_invert, + const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx, + const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts, + const mcu_pin_obj_t *rs485_dir, bool rs485_invert, uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, - mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer, + mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer, bool sigint_enabled) { if (bits != 8) { @@ -154,7 +154,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, // Find a free UART peripheral. self->uarte = NULL; - for (size_t i = 0 ; i < MP_ARRAY_SIZE(nrfx_uartes); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(nrfx_uartes); i++) { if ((nrfx_uartes[i].p_reg->ENABLE & UARTE_ENABLE_ENABLE_Msk) == 0) { self->uarte = &nrfx_uartes[i]; break; @@ -165,15 +165,15 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, mp_raise_ValueError(translate("All UART peripherals are in use")); } - if ( (tx == NULL) && (rx == NULL) ) { + if ((tx == NULL) && (rx == NULL)) { mp_raise_ValueError(translate("tx and rx cannot both be None")); } - if ( receiver_buffer_size == 0 ) { + if (receiver_buffer_size == 0) { mp_raise_ValueError(translate("Invalid buffer size")); } - if ( parity == BUSIO_UART_PARITY_ODD ) { + if (parity == BUSIO_UART_PARITY_ODD) { mp_raise_ValueError(translate("Odd parity is not supported")); } @@ -196,7 +196,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, _VERIFY_ERR(nrfx_uarte_init(self->uarte, &config, uart_callback_irq)); // Init buffer for rx - if ( rx != NULL ) { + if (rx != NULL) { // Initially allocate the UART's buffer in the long-lived part of the // heap. UARTs are generally long-lived objects, but the "make long- // lived" machinery is incapable of moving internal pointers like @@ -213,21 +213,21 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, claim_pin(rx); } - if ( tx != NULL ) { + if (tx != NULL) { self->tx_pin_number = tx->number; claim_pin(tx); } else { self->tx_pin_number = NO_PIN; } - if ( rts != NULL ) { + if (rts != NULL) { self->rts_pin_number = rts->number; claim_pin(rts); } else { self->rts_pin_number = NO_PIN; } - if ( cts != NULL ) { + if (cts != NULL) { self->cts_pin_number = cts->number; claim_pin(cts); } else { @@ -248,7 +248,7 @@ bool common_hal_busio_uart_deinited(busio_uart_obj_t *self) { } void common_hal_busio_uart_deinit(busio_uart_obj_t *self) { - if ( !common_hal_busio_uart_deinited(self) ) { + if (!common_hal_busio_uart_deinited(self)) { nrfx_uarte_uninit(self->uarte); reset_pin_number(self->tx_pin_number); reset_pin_number(self->rx_pin_number); @@ -264,7 +264,7 @@ void common_hal_busio_uart_deinit(busio_uart_obj_t *self) { // Read characters. size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t len, int *errcode) { - if ( nrf_uarte_rx_pin_get(self->uarte->p_reg) == NRF_UARTE_PSEL_DISCONNECTED ) { + if (nrf_uarte_rx_pin_get(self->uarte->p_reg) == NRF_UARTE_PSEL_DISCONNECTED) { mp_raise_ValueError(translate("No RX pin")); } @@ -278,10 +278,10 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t */ // Wait for all bytes received or timeout - while ( (ringbuf_num_filled(&self->ringbuf) < len) && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms) ) { + while ((ringbuf_num_filled(&self->ringbuf) < len) && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms)) { RUN_BACKGROUND_TASKS; // Allow user to break out of a timeout with a KeyboardInterrupt. - if ( mp_hal_is_interrupted() ) { + if (mp_hal_is_interrupted()) { return 0; } } @@ -297,7 +297,7 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t // the character that did not fit in ringbuf is in rx_char ringbuf_put_n(&self->ringbuf, &self->rx_char, 1); // keep receiving - (void) nrfx_uarte_rx(self->uarte, &self->rx_char, 1); + (void)nrfx_uarte_rx(self->uarte, &self->rx_char, 1); nrf_gpio_pin_write(self->rts_pin_number, false); self->rx_paused = false; } @@ -308,18 +308,20 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t } // Write characters. -size_t common_hal_busio_uart_write (busio_uart_obj_t *self, const uint8_t *data, size_t len, int *errcode) { - if ( nrf_uarte_tx_pin_get(self->uarte->p_reg) == NRF_UARTE_PSEL_DISCONNECTED ) { +size_t common_hal_busio_uart_write(busio_uart_obj_t *self, const uint8_t *data, size_t len, int *errcode) { + if (nrf_uarte_tx_pin_get(self->uarte->p_reg) == NRF_UARTE_PSEL_DISCONNECTED) { mp_raise_ValueError(translate("No TX pin")); } - if ( len == 0 ) return 0; + if (len == 0) { + return 0; + } // EasyDMA can only access SRAM - uint8_t * tx_buf = (uint8_t*) data; - if ( !nrfx_is_in_ram(data) ) { + uint8_t *tx_buf = (uint8_t *)data; + if (!nrfx_is_in_ram(data)) { // TODO: If this is not too big, we could allocate it on the stack. - tx_buf = (uint8_t *) gc_alloc(len, false, false); + tx_buf = (uint8_t *)gc_alloc(len, false, false); memcpy(tx_buf, data, len); } @@ -328,11 +330,11 @@ size_t common_hal_busio_uart_write (busio_uart_obj_t *self, const uint8_t *data, (*errcode) = 0; // Wait for write to complete. - while ( nrfx_uarte_tx_in_progress(self->uarte) ) { + while (nrfx_uarte_tx_in_progress(self->uarte)) { RUN_BACKGROUND_TASKS; } - if ( !nrfx_is_in_ram(data) ) { + if (!nrfx_is_in_ram(data)) { gc_free(tx_buf); } @@ -349,7 +351,7 @@ void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrat } mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) { - return (mp_float_t) (self->timeout_ms / 1000.0f); + return (mp_float_t)(self->timeout_ms / 1000.0f); } void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) { diff --git a/ports/nrf/common-hal/digitalio/DigitalInOut.c b/ports/nrf/common-hal/digitalio/DigitalInOut.c index 2a72151b7..b42d7dc70 100644 --- a/ports/nrf/common-hal/digitalio/DigitalInOut.c +++ b/ports/nrf/common-hal/digitalio/DigitalInOut.c @@ -31,12 +31,12 @@ #include "nrf_gpio.h" void common_hal_digitalio_digitalinout_never_reset( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { never_reset_pin_number(self->pin->number); } digitalinout_result_t common_hal_digitalio_digitalinout_construct( - digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { + digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { claim_pin(pin); self->pin = pin; @@ -60,14 +60,14 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self } void common_hal_digitalio_digitalinout_switch_to_input( - digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { nrf_gpio_cfg_input(self->pin->number, NRF_GPIO_PIN_NOPULL); common_hal_digitalio_digitalinout_set_pull(self, pull); } digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( - digitalio_digitalinout_obj_t *self, bool value, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, bool value, + digitalio_drive_mode_t drive_mode) { common_hal_digitalio_digitalinout_set_drive_mode(self, drive_mode); common_hal_digitalio_digitalinout_set_value(self, value); @@ -75,53 +75,53 @@ digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { return (nrf_gpio_pin_dir_get(self->pin->number) == NRF_GPIO_PIN_DIR_INPUT) ? DIRECTION_INPUT : DIRECTION_OUTPUT; } void common_hal_digitalio_digitalinout_set_value( - digitalio_digitalinout_obj_t *self, bool value) { + digitalio_digitalinout_obj_t *self, bool value) { nrf_gpio_pin_write(self->pin->number, value); } bool common_hal_digitalio_digitalinout_get_value( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { return (nrf_gpio_pin_dir_get(self->pin->number) == NRF_GPIO_PIN_DIR_INPUT) ? nrf_gpio_pin_read(self->pin->number) : nrf_gpio_pin_out_read(self->pin->number); } digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( - digitalio_digitalinout_obj_t *self, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, + digitalio_drive_mode_t drive_mode) { nrf_gpio_cfg(self->pin->number, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - NRF_GPIO_PIN_NOPULL, - drive_mode == DRIVE_MODE_OPEN_DRAIN ? NRF_GPIO_PIN_H0D1 : NRF_GPIO_PIN_H0H1, - NRF_GPIO_PIN_NOSENSE); + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + drive_mode == DRIVE_MODE_OPEN_DRAIN ? NRF_GPIO_PIN_H0D1 : NRF_GPIO_PIN_H0H1, + NRF_GPIO_PIN_NOSENSE); return DIGITALINOUT_OK; } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { uint32_t pin = self->pin->number; // Changes pin to be a relative pin number in port. NRF_GPIO_Type *reg = nrf_gpio_pin_port_decode(&pin); switch ((reg->PIN_CNF[pin] & GPIO_PIN_CNF_DRIVE_Msk) >> GPIO_PIN_CNF_DRIVE_Pos) { - case NRF_GPIO_PIN_S0D1: - case NRF_GPIO_PIN_H0D1: - return DRIVE_MODE_OPEN_DRAIN; - default: - return DRIVE_MODE_PUSH_PULL; + case NRF_GPIO_PIN_S0D1: + case NRF_GPIO_PIN_H0D1: + return DRIVE_MODE_OPEN_DRAIN; + default: + return DRIVE_MODE_PUSH_PULL; } } void common_hal_digitalio_digitalinout_set_pull( - digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { nrf_gpio_pin_pull_t hal_pull = NRF_GPIO_PIN_NOPULL; switch (pull) { @@ -140,7 +140,7 @@ void common_hal_digitalio_digitalinout_set_pull( } digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { uint32_t pin = self->pin->number; // Changes pin to be a relative pin number in port. NRF_GPIO_Type *reg = nrf_gpio_pin_port_decode(&pin); diff --git a/ports/nrf/common-hal/displayio/ParallelBus.c b/ports/nrf/common-hal/displayio/ParallelBus.c index 31ee1f48e..1afa6c4d6 100644 --- a/ports/nrf/common-hal/displayio/ParallelBus.c +++ b/ports/nrf/common-hal/displayio/ParallelBus.c @@ -33,9 +33,9 @@ #include "shared-bindings/digitalio/DigitalInOut.h" #include "shared-bindings/microcontroller/__init__.h" -void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* self, - const mcu_pin_obj_t* data0, const mcu_pin_obj_t* command, const mcu_pin_obj_t* chip_select, - const mcu_pin_obj_t* write, const mcu_pin_obj_t* read, const mcu_pin_obj_t* reset) { +void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t *self, + const mcu_pin_obj_t *data0, const mcu_pin_obj_t *command, const mcu_pin_obj_t *chip_select, + const mcu_pin_obj_t *write, const mcu_pin_obj_t *read, const mcu_pin_obj_t *reset) { uint8_t data_pin = data0->number; if (data_pin % 8 != 0) { @@ -59,7 +59,7 @@ void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* sel for (uint8_t i = 0; i < 8; i++) { g->PIN_CNF[data_pin + i] |= NRF_GPIO_PIN_S0S1 << GPIO_PIN_CNF_DRIVE_Pos; } - self->bus = ((uint8_t*) &g->OUT) + (data0->number % num_pins_in_port / 8); + self->bus = ((uint8_t *)&g->OUT) + (data0->number % num_pins_in_port / 8); self->command.base.type = &digitalio_digitalinout_type; common_hal_digitalio_digitalinout_construct(&self->command, command); @@ -106,7 +106,7 @@ void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* sel } } -void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) { +void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t *self) { for (uint8_t i = 0; i < 8; i++) { reset_pin_number(self->data0_pin + i); } @@ -119,7 +119,7 @@ void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) } bool common_hal_displayio_parallelbus_reset(mp_obj_t obj) { - displayio_parallelbus_obj_t* self = MP_OBJ_TO_PTR(obj); + displayio_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj); if (self->reset.base.type == &mp_type_NoneType) { return false; } @@ -135,7 +135,7 @@ bool common_hal_displayio_parallelbus_bus_free(mp_obj_t obj) { } bool common_hal_displayio_parallelbus_begin_transaction(mp_obj_t obj) { - displayio_parallelbus_obj_t* self = MP_OBJ_TO_PTR(obj); + displayio_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj); common_hal_digitalio_digitalinout_set_value(&self->chip_select, false); return true; } @@ -143,10 +143,10 @@ bool common_hal_displayio_parallelbus_begin_transaction(mp_obj_t obj) { // This ignores chip_select behaviour because data is clocked in by the write line toggling. void common_hal_displayio_parallelbus_send(mp_obj_t obj, display_byte_type_t byte_type, display_chip_select_behavior_t chip_select, const uint8_t *data, uint32_t data_length) { - displayio_parallelbus_obj_t* self = MP_OBJ_TO_PTR(obj); + displayio_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj); common_hal_digitalio_digitalinout_set_value(&self->command, byte_type == DISPLAY_DATA); - uint32_t* clear_write = (uint32_t*) &self->write_group->OUTCLR; - uint32_t* set_write = (uint32_t*) &self->write_group->OUTSET; + uint32_t *clear_write = (uint32_t *)&self->write_group->OUTCLR; + uint32_t *set_write = (uint32_t *)&self->write_group->OUTSET; uint32_t mask = self->write_mask; for (uint32_t i = 0; i < data_length; i++) { *clear_write = mask; @@ -156,6 +156,6 @@ void common_hal_displayio_parallelbus_send(mp_obj_t obj, display_byte_type_t byt } void common_hal_displayio_parallelbus_end_transaction(mp_obj_t obj) { - displayio_parallelbus_obj_t* self = MP_OBJ_TO_PTR(obj); + displayio_parallelbus_obj_t *self = MP_OBJ_TO_PTR(obj); common_hal_digitalio_digitalinout_set_value(&self->chip_select, true); } diff --git a/ports/nrf/common-hal/displayio/ParallelBus.h b/ports/nrf/common-hal/displayio/ParallelBus.h index 5c10d3d42..30a0c7e61 100644 --- a/ports/nrf/common-hal/displayio/ParallelBus.h +++ b/ports/nrf/common-hal/displayio/ParallelBus.h @@ -31,14 +31,14 @@ typedef struct { mp_obj_base_t base; - uint8_t* bus; + uint8_t *bus; digitalio_digitalinout_obj_t command; digitalio_digitalinout_obj_t chip_select; digitalio_digitalinout_obj_t reset; digitalio_digitalinout_obj_t write; digitalio_digitalinout_obj_t read; uint8_t data0_pin; - NRF_GPIO_Type* write_group; + NRF_GPIO_Type *write_group; uint32_t write_mask; } displayio_parallelbus_obj_t; diff --git a/ports/nrf/common-hal/microcontroller/Pin.c b/ports/nrf/common-hal/microcontroller/Pin.c index 23d6e23bf..aea4f63ea 100644 --- a/ports/nrf/common-hal/microcontroller/Pin.c +++ b/ports/nrf/common-hal/microcontroller/Pin.c @@ -49,16 +49,16 @@ STATIC uint32_t claimed_pins[GPIO_COUNT]; STATIC uint32_t never_reset_pins[GPIO_COUNT]; STATIC void reset_speaker_enable_pin(void) { -#ifdef SPEAKER_ENABLE_PIN + #ifdef SPEAKER_ENABLE_PIN speaker_enable_in_use = false; nrf_gpio_cfg(SPEAKER_ENABLE_PIN->number, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_H0H1, - NRF_GPIO_PIN_NOSENSE); + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_H0H1, + NRF_GPIO_PIN_NOSENSE); nrf_gpio_pin_write(SPEAKER_ENABLE_PIN->number, false); -#endif + #endif } void reset_all_pins(void) { @@ -129,18 +129,18 @@ void never_reset_pin_number(uint8_t pin_number) { never_reset_pins[nrf_pin_port(pin_number)] |= 1 << nrf_relative_pin_number(pin_number); } -void common_hal_never_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_never_reset_pin(const mcu_pin_obj_t *pin) { never_reset_pin_number(pin->number); } -void common_hal_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_reset_pin(const mcu_pin_obj_t *pin) { if (pin == NULL) { return; } reset_pin_number(pin->number); } -void claim_pin(const mcu_pin_obj_t* pin) { +void claim_pin(const mcu_pin_obj_t *pin) { // Set bit in claimed_pins bitmask. claimed_pins[nrf_pin_port(pin->number)] |= 1 << nrf_relative_pin_number(pin->number); @@ -204,11 +204,11 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { } -uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t* pin) { +uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t *pin) { return pin->number; } -void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { +void common_hal_mcu_pin_claim(const mcu_pin_obj_t *pin) { claim_pin(pin); } diff --git a/ports/nrf/common-hal/microcontroller/Pin.h b/ports/nrf/common-hal/microcontroller/Pin.h index 735ed90cc..888ab6a8c 100644 --- a/ports/nrf/common-hal/microcontroller/Pin.h +++ b/ports/nrf/common-hal/microcontroller/Pin.h @@ -43,7 +43,7 @@ void reset_all_pins(void); // reset_pin_number takes the pin number instead of the pointer so that objects don't // need to store a full pointer. void reset_pin_number(uint8_t pin); -void claim_pin(const mcu_pin_obj_t* pin); +void claim_pin(const mcu_pin_obj_t *pin); bool pin_number_is_free(uint8_t pin_number); void never_reset_pin_number(uint8_t pin_number); diff --git a/ports/nrf/common-hal/microcontroller/Processor.c b/ports/nrf/common-hal/microcontroller/Processor.c index ab5f29b5d..b31c4c12d 100644 --- a/ports/nrf/common-hal/microcontroller/Processor.c +++ b/ports/nrf/common-hal/microcontroller/Processor.c @@ -40,10 +40,10 @@ float common_hal_mcu_processor_get_temperature(void) { int32_t temp = 0; -#ifdef BLUETOOTH_SD + #ifdef BLUETOOTH_SD uint8_t sd_en = 0; - (void) sd_softdevice_is_enabled(&sd_en); + (void)sd_softdevice_is_enabled(&sd_en); if (sd_en) { uint32_t err_code = sd_temp_get(&temp); @@ -52,9 +52,10 @@ float common_hal_mcu_processor_get_temperature(void) { } return temp / 4.0f; } // Fall through if SD not enabled. -#endif + #endif NRF_TEMP->TASKS_START = 1; - while (NRF_TEMP->EVENTS_DATARDY == 0) { } + while (NRF_TEMP->EVENTS_DATARDY == 0) { + } NRF_TEMP->EVENTS_DATARDY = 0; temp = NRF_TEMP->TEMP; NRF_TEMP->TASKS_STOP = 1; @@ -93,15 +94,18 @@ float common_hal_mcu_processor_get_voltage(void) { nrf_saadc_buffer_init(NRF_SAADC, &value, 1); nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_START); - while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STARTED) == 0) { } + while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STARTED) == 0) { + } nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STARTED); nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_SAMPLE); - while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_END) == 0) { } + while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_END) == 0) { + } nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END); nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_STOP); - while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STOPPED) == 0) { } + while (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STOPPED) == 0) { + } nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED); nrf_saadc_disable(NRF_SAADC); @@ -111,14 +115,14 @@ float common_hal_mcu_processor_get_voltage(void) { } // The ADC reading we expect if VDD is 3.3V. -#define NOMINAL_VALUE_3_3 (((3.3f/6)/0.6f)*16383) - return (value/NOMINAL_VALUE_3_3) * 3.3f; +#define NOMINAL_VALUE_3_3 (((3.3f / 6) / 0.6f) * 16383) + return (value / NOMINAL_VALUE_3_3) * 3.3f; } void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { - for (int i=0; i<2; i++) { - ((uint32_t*) raw_id)[i] = NRF_FICR->DEVICEID[i]; + for (int i = 0; i < 2; i++) { + ((uint32_t *)raw_id)[i] = NRF_FICR->DEVICEID[i]; } } diff --git a/ports/nrf/common-hal/microcontroller/__init__.c b/ports/nrf/common-hal/microcontroller/__init__.c index 06aac9409..d84cc5845 100644 --- a/ports/nrf/common-hal/microcontroller/__init__.c +++ b/ports/nrf/common-hal/microcontroller/__init__.c @@ -82,12 +82,14 @@ void common_hal_mcu_enable_interrupts() { void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) { enum { DFU_MAGIC_UF2_RESET = 0x57 }; - if(runmode == RUNMODE_BOOTLOADER) + if (runmode == RUNMODE_BOOTLOADER) { NRF_POWER->GPREGRET = DFU_MAGIC_UF2_RESET; - else + } else { NRF_POWER->GPREGRET = 0; - if(runmode == RUNMODE_SAFE_MODE) + } + if (runmode == RUNMODE_SAFE_MODE) { safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE); + } } void common_hal_mcu_reset(void) { @@ -109,7 +111,7 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .base = { .type = &nvm_bytearray_type, }, - .start_address = (uint8_t*) CIRCUITPY_INTERNAL_NVM_START_ADDR, + .start_address = (uint8_t *)CIRCUITPY_INTERNAL_NVM_START_ADDR, .len = CIRCUITPY_INTERNAL_NVM_SIZE, }; #endif @@ -126,67 +128,67 @@ watchdog_watchdogtimer_obj_t common_hal_mcu_watchdogtimer_obj = { #endif STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_P0_00), MP_ROM_PTR(&pin_P0_00) }, - { MP_ROM_QSTR(MP_QSTR_P0_01), MP_ROM_PTR(&pin_P0_01) }, - { MP_ROM_QSTR(MP_QSTR_P0_02), MP_ROM_PTR(&pin_P0_02) }, - { MP_ROM_QSTR(MP_QSTR_P0_03), MP_ROM_PTR(&pin_P0_03) }, - { MP_ROM_QSTR(MP_QSTR_P0_04), MP_ROM_PTR(&pin_P0_04) }, - { MP_ROM_QSTR(MP_QSTR_P0_05), MP_ROM_PTR(&pin_P0_05) }, - { MP_ROM_QSTR(MP_QSTR_P0_06), MP_ROM_PTR(&pin_P0_06) }, - { MP_ROM_QSTR(MP_QSTR_P0_07), MP_ROM_PTR(&pin_P0_07) }, - { MP_ROM_QSTR(MP_QSTR_P0_08), MP_ROM_PTR(&pin_P0_08) }, - { MP_ROM_QSTR(MP_QSTR_P0_09), MP_ROM_PTR(&pin_P0_09) }, - { MP_ROM_QSTR(MP_QSTR_P0_10), MP_ROM_PTR(&pin_P0_10) }, - { MP_ROM_QSTR(MP_QSTR_P0_11), MP_ROM_PTR(&pin_P0_11) }, - { MP_ROM_QSTR(MP_QSTR_P0_12), MP_ROM_PTR(&pin_P0_12) }, - { MP_ROM_QSTR(MP_QSTR_P0_13), MP_ROM_PTR(&pin_P0_13) }, - { MP_ROM_QSTR(MP_QSTR_P0_14), MP_ROM_PTR(&pin_P0_14) }, - { MP_ROM_QSTR(MP_QSTR_P0_15), MP_ROM_PTR(&pin_P0_15) }, - { MP_ROM_QSTR(MP_QSTR_P0_16), MP_ROM_PTR(&pin_P0_16) }, - { MP_ROM_QSTR(MP_QSTR_P0_17), MP_ROM_PTR(&pin_P0_17) }, - { MP_ROM_QSTR(MP_QSTR_P0_18), MP_ROM_PTR(&pin_P0_18) }, - { MP_ROM_QSTR(MP_QSTR_P0_19), MP_ROM_PTR(&pin_P0_19) }, - { MP_ROM_QSTR(MP_QSTR_P0_20), MP_ROM_PTR(&pin_P0_20) }, - { MP_ROM_QSTR(MP_QSTR_P0_21), MP_ROM_PTR(&pin_P0_21) }, - { MP_ROM_QSTR(MP_QSTR_P0_22), MP_ROM_PTR(&pin_P0_22) }, - { MP_ROM_QSTR(MP_QSTR_P0_23), MP_ROM_PTR(&pin_P0_23) }, - { MP_ROM_QSTR(MP_QSTR_P0_24), MP_ROM_PTR(&pin_P0_24) }, - { MP_ROM_QSTR(MP_QSTR_P0_25), MP_ROM_PTR(&pin_P0_25) }, - { MP_ROM_QSTR(MP_QSTR_P0_26), MP_ROM_PTR(&pin_P0_26) }, - { MP_ROM_QSTR(MP_QSTR_P0_27), MP_ROM_PTR(&pin_P0_27) }, - { MP_ROM_QSTR(MP_QSTR_P0_28), MP_ROM_PTR(&pin_P0_28) }, - { MP_ROM_QSTR(MP_QSTR_P0_29), MP_ROM_PTR(&pin_P0_29) }, - { MP_ROM_QSTR(MP_QSTR_P0_30), MP_ROM_PTR(&pin_P0_30) }, - { MP_ROM_QSTR(MP_QSTR_P0_31), MP_ROM_PTR(&pin_P0_31) }, -#ifdef NRF52840 - { MP_ROM_QSTR(MP_QSTR_P1_00), MP_ROM_PTR(&pin_P1_00) }, - { MP_ROM_QSTR(MP_QSTR_P1_01), MP_ROM_PTR(&pin_P1_01) }, - { MP_ROM_QSTR(MP_QSTR_P1_02), MP_ROM_PTR(&pin_P1_02) }, - { MP_ROM_QSTR(MP_QSTR_P1_03), MP_ROM_PTR(&pin_P1_03) }, - { MP_ROM_QSTR(MP_QSTR_P1_04), MP_ROM_PTR(&pin_P1_04) }, - { MP_ROM_QSTR(MP_QSTR_P1_05), MP_ROM_PTR(&pin_P1_05) }, - { MP_ROM_QSTR(MP_QSTR_P1_06), MP_ROM_PTR(&pin_P1_06) }, - { MP_ROM_QSTR(MP_QSTR_P1_07), MP_ROM_PTR(&pin_P1_07) }, - { MP_ROM_QSTR(MP_QSTR_P1_08), MP_ROM_PTR(&pin_P1_08) }, - { MP_ROM_QSTR(MP_QSTR_P1_09), MP_ROM_PTR(&pin_P1_09) }, - { MP_ROM_QSTR(MP_QSTR_P1_10), MP_ROM_PTR(&pin_P1_10) }, - { MP_ROM_QSTR(MP_QSTR_P1_11), MP_ROM_PTR(&pin_P1_11) }, - { MP_ROM_QSTR(MP_QSTR_P1_12), MP_ROM_PTR(&pin_P1_12) }, - { MP_ROM_QSTR(MP_QSTR_P1_13), MP_ROM_PTR(&pin_P1_13) }, - { MP_ROM_QSTR(MP_QSTR_P1_14), MP_ROM_PTR(&pin_P1_14) }, - { MP_ROM_QSTR(MP_QSTR_P1_15), MP_ROM_PTR(&pin_P1_15) }, -#endif -#ifdef NRF52833 - { MP_ROM_QSTR(MP_QSTR_P1_00), MP_ROM_PTR(&pin_P1_00) }, - { MP_ROM_QSTR(MP_QSTR_P1_01), MP_ROM_PTR(&pin_P1_01) }, - { MP_ROM_QSTR(MP_QSTR_P1_02), MP_ROM_PTR(&pin_P1_02) }, - { MP_ROM_QSTR(MP_QSTR_P1_03), MP_ROM_PTR(&pin_P1_03) }, - { MP_ROM_QSTR(MP_QSTR_P1_04), MP_ROM_PTR(&pin_P1_04) }, - { MP_ROM_QSTR(MP_QSTR_P1_05), MP_ROM_PTR(&pin_P1_05) }, - { MP_ROM_QSTR(MP_QSTR_P1_06), MP_ROM_PTR(&pin_P1_06) }, - { MP_ROM_QSTR(MP_QSTR_P1_07), MP_ROM_PTR(&pin_P1_07) }, - { MP_ROM_QSTR(MP_QSTR_P1_08), MP_ROM_PTR(&pin_P1_08) }, - { MP_ROM_QSTR(MP_QSTR_P1_09), MP_ROM_PTR(&pin_P1_09) }, -#endif + { MP_ROM_QSTR(MP_QSTR_P0_00), MP_ROM_PTR(&pin_P0_00) }, + { MP_ROM_QSTR(MP_QSTR_P0_01), MP_ROM_PTR(&pin_P0_01) }, + { MP_ROM_QSTR(MP_QSTR_P0_02), MP_ROM_PTR(&pin_P0_02) }, + { MP_ROM_QSTR(MP_QSTR_P0_03), MP_ROM_PTR(&pin_P0_03) }, + { MP_ROM_QSTR(MP_QSTR_P0_04), MP_ROM_PTR(&pin_P0_04) }, + { MP_ROM_QSTR(MP_QSTR_P0_05), MP_ROM_PTR(&pin_P0_05) }, + { MP_ROM_QSTR(MP_QSTR_P0_06), MP_ROM_PTR(&pin_P0_06) }, + { MP_ROM_QSTR(MP_QSTR_P0_07), MP_ROM_PTR(&pin_P0_07) }, + { MP_ROM_QSTR(MP_QSTR_P0_08), MP_ROM_PTR(&pin_P0_08) }, + { MP_ROM_QSTR(MP_QSTR_P0_09), MP_ROM_PTR(&pin_P0_09) }, + { MP_ROM_QSTR(MP_QSTR_P0_10), MP_ROM_PTR(&pin_P0_10) }, + { MP_ROM_QSTR(MP_QSTR_P0_11), MP_ROM_PTR(&pin_P0_11) }, + { MP_ROM_QSTR(MP_QSTR_P0_12), MP_ROM_PTR(&pin_P0_12) }, + { MP_ROM_QSTR(MP_QSTR_P0_13), MP_ROM_PTR(&pin_P0_13) }, + { MP_ROM_QSTR(MP_QSTR_P0_14), MP_ROM_PTR(&pin_P0_14) }, + { MP_ROM_QSTR(MP_QSTR_P0_15), MP_ROM_PTR(&pin_P0_15) }, + { MP_ROM_QSTR(MP_QSTR_P0_16), MP_ROM_PTR(&pin_P0_16) }, + { MP_ROM_QSTR(MP_QSTR_P0_17), MP_ROM_PTR(&pin_P0_17) }, + { MP_ROM_QSTR(MP_QSTR_P0_18), MP_ROM_PTR(&pin_P0_18) }, + { MP_ROM_QSTR(MP_QSTR_P0_19), MP_ROM_PTR(&pin_P0_19) }, + { MP_ROM_QSTR(MP_QSTR_P0_20), MP_ROM_PTR(&pin_P0_20) }, + { MP_ROM_QSTR(MP_QSTR_P0_21), MP_ROM_PTR(&pin_P0_21) }, + { MP_ROM_QSTR(MP_QSTR_P0_22), MP_ROM_PTR(&pin_P0_22) }, + { MP_ROM_QSTR(MP_QSTR_P0_23), MP_ROM_PTR(&pin_P0_23) }, + { MP_ROM_QSTR(MP_QSTR_P0_24), MP_ROM_PTR(&pin_P0_24) }, + { MP_ROM_QSTR(MP_QSTR_P0_25), MP_ROM_PTR(&pin_P0_25) }, + { MP_ROM_QSTR(MP_QSTR_P0_26), MP_ROM_PTR(&pin_P0_26) }, + { MP_ROM_QSTR(MP_QSTR_P0_27), MP_ROM_PTR(&pin_P0_27) }, + { MP_ROM_QSTR(MP_QSTR_P0_28), MP_ROM_PTR(&pin_P0_28) }, + { MP_ROM_QSTR(MP_QSTR_P0_29), MP_ROM_PTR(&pin_P0_29) }, + { MP_ROM_QSTR(MP_QSTR_P0_30), MP_ROM_PTR(&pin_P0_30) }, + { MP_ROM_QSTR(MP_QSTR_P0_31), MP_ROM_PTR(&pin_P0_31) }, + #ifdef NRF52840 + { MP_ROM_QSTR(MP_QSTR_P1_00), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_P1_01), MP_ROM_PTR(&pin_P1_01) }, + { MP_ROM_QSTR(MP_QSTR_P1_02), MP_ROM_PTR(&pin_P1_02) }, + { MP_ROM_QSTR(MP_QSTR_P1_03), MP_ROM_PTR(&pin_P1_03) }, + { MP_ROM_QSTR(MP_QSTR_P1_04), MP_ROM_PTR(&pin_P1_04) }, + { MP_ROM_QSTR(MP_QSTR_P1_05), MP_ROM_PTR(&pin_P1_05) }, + { MP_ROM_QSTR(MP_QSTR_P1_06), MP_ROM_PTR(&pin_P1_06) }, + { MP_ROM_QSTR(MP_QSTR_P1_07), MP_ROM_PTR(&pin_P1_07) }, + { MP_ROM_QSTR(MP_QSTR_P1_08), MP_ROM_PTR(&pin_P1_08) }, + { MP_ROM_QSTR(MP_QSTR_P1_09), MP_ROM_PTR(&pin_P1_09) }, + { MP_ROM_QSTR(MP_QSTR_P1_10), MP_ROM_PTR(&pin_P1_10) }, + { MP_ROM_QSTR(MP_QSTR_P1_11), MP_ROM_PTR(&pin_P1_11) }, + { MP_ROM_QSTR(MP_QSTR_P1_12), MP_ROM_PTR(&pin_P1_12) }, + { MP_ROM_QSTR(MP_QSTR_P1_13), MP_ROM_PTR(&pin_P1_13) }, + { MP_ROM_QSTR(MP_QSTR_P1_14), MP_ROM_PTR(&pin_P1_14) }, + { MP_ROM_QSTR(MP_QSTR_P1_15), MP_ROM_PTR(&pin_P1_15) }, + #endif + #ifdef NRF52833 + { MP_ROM_QSTR(MP_QSTR_P1_00), MP_ROM_PTR(&pin_P1_00) }, + { MP_ROM_QSTR(MP_QSTR_P1_01), MP_ROM_PTR(&pin_P1_01) }, + { MP_ROM_QSTR(MP_QSTR_P1_02), MP_ROM_PTR(&pin_P1_02) }, + { MP_ROM_QSTR(MP_QSTR_P1_03), MP_ROM_PTR(&pin_P1_03) }, + { MP_ROM_QSTR(MP_QSTR_P1_04), MP_ROM_PTR(&pin_P1_04) }, + { MP_ROM_QSTR(MP_QSTR_P1_05), MP_ROM_PTR(&pin_P1_05) }, + { MP_ROM_QSTR(MP_QSTR_P1_06), MP_ROM_PTR(&pin_P1_06) }, + { MP_ROM_QSTR(MP_QSTR_P1_07), MP_ROM_PTR(&pin_P1_07) }, + { MP_ROM_QSTR(MP_QSTR_P1_08), MP_ROM_PTR(&pin_P1_08) }, + { MP_ROM_QSTR(MP_QSTR_P1_09), MP_ROM_PTR(&pin_P1_09) }, + #endif }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/nrf/common-hal/neopixel_write/__init__.c b/ports/nrf/common-hal/neopixel_write/__init__.c index 8062937f4..c8aa44cd1 100644 --- a/ports/nrf/common-hal/neopixel_write/__init__.c +++ b/ports/nrf/common-hal/neopixel_write/__init__.c @@ -53,8 +53,8 @@ // need to set the 15th bit on each register. // WS2812 (rev A) timing is 0.35 and 0.7us -//#define MAGIC_T0H 5UL | (0x8000) // 0.3125us -//#define MAGIC_T1H 12UL | (0x8000) // 0.75us +// #define MAGIC_T0H 5UL | (0x8000) // 0.3125us +// #define MAGIC_T1H 12UL | (0x8000) // 0.75us // WS2812B (rev B) timing is 0.4 and 0.8 us #define MAGIC_T0H 6UL | (0x8000) // 0.375us @@ -78,18 +78,18 @@ // ---------- END of Constants for cycle counter implementation -------- // find a free PWM device, which is not enabled and has no connected pins -static NRF_PWM_Type* find_free_pwm (void) { - NRF_PWM_Type* PWM[] = { - NRF_PWM0, NRF_PWM1, NRF_PWM2 -#ifdef NRF_PWM3 - , NRF_PWM3 -#endif +static NRF_PWM_Type *find_free_pwm(void) { + NRF_PWM_Type *PWM[] = { + NRF_PWM0, NRF_PWM1, NRF_PWM2 + #ifdef NRF_PWM3 + , NRF_PWM3 + #endif }; - for ( size_t device = 0; device < ARRAY_SIZE(PWM); device++ ) { - if ( (PWM[device]->ENABLE == 0) && - (PWM[device]->PSEL.OUT[0] & PWM_PSEL_OUT_CONNECT_Msk) && (PWM[device]->PSEL.OUT[1] & PWM_PSEL_OUT_CONNECT_Msk) && - (PWM[device]->PSEL.OUT[2] & PWM_PSEL_OUT_CONNECT_Msk) && (PWM[device]->PSEL.OUT[3] & PWM_PSEL_OUT_CONNECT_Msk) ) { + for (size_t device = 0; device < ARRAY_SIZE(PWM); device++) { + if ((PWM[device]->ENABLE == 0) && + (PWM[device]->PSEL.OUT[0] & PWM_PSEL_OUT_CONNECT_Msk) && (PWM[device]->PSEL.OUT[1] & PWM_PSEL_OUT_CONNECT_Msk) && + (PWM[device]->PSEL.OUT[2] & PWM_PSEL_OUT_CONNECT_Msk) && (PWM[device]->PSEL.OUT[3] & PWM_PSEL_OUT_CONNECT_Msk)) { return PWM[device]; } } @@ -106,7 +106,7 @@ void neopixel_write_reset(void) { uint64_t next_start_raw_ticks = 0; -void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, uint32_t numBytes) { +void common_hal_neopixel_write(const digitalio_digitalinout_obj_t *digitalinout, uint8_t *pixels, uint32_t numBytes) { // To support both the SoftDevice + Neopixels we use the EasyDMA // feature from the NRF52. However this technique implies to // generate a pattern and store it on the memory. The actual @@ -126,22 +126,22 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout // to handle larger NeoPixel rings without malloc'ing. #define STACK_PIXELS 24 uint32_t pattern_size = PATTERN_SIZE(numBytes); - uint16_t* pixels_pattern = NULL; + uint16_t *pixels_pattern = NULL; // Use the stack to store STACK_PIXEL's worth of PWM data. uint32_t to ensure alignment. // It is 3*STACK_PIXELS to handle RGB. // PATTERN_SIZE is a multiple of 4, so we don't need round up to make sure one_pixel is large enough. uint32_t stack_pixels[PATTERN_SIZE(3 * STACK_PIXELS) / sizeof(uint32_t)]; - NRF_PWM_Type* pwm = find_free_pwm(); + NRF_PWM_Type *pwm = find_free_pwm(); // only malloc if there is PWM device available - if ( pwm != NULL ) { + if (pwm != NULL) { if (pattern_size <= sizeof(stack_pixels)) { - pixels_pattern = (uint16_t *) stack_pixels; + pixels_pattern = (uint16_t *)stack_pixels; } else { uint8_t sd_en = 0; - (void) sd_softdevice_is_enabled(&sd_en); + (void)sd_softdevice_is_enabled(&sd_en); if (pixels_pattern_heap_size < pattern_size) { // Current heap buffer is too small. @@ -157,12 +157,12 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout // transmit. This takes a bunch of memory to do so raise an // exception if we can't. MP_STATE_VM(pixels_pattern_heap) = - (uint16_t *) m_realloc(MP_STATE_VM(pixels_pattern_heap), pattern_size); + (uint16_t *)m_realloc(MP_STATE_VM(pixels_pattern_heap), pattern_size); } else { // Might return NULL. MP_STATE_VM(pixels_pattern_heap) = // true means move if necessary. - (uint16_t *) m_realloc_maybe(MP_STATE_VM(pixels_pattern_heap), pattern_size, true); + (uint16_t *)m_realloc_maybe(MP_STATE_VM(pixels_pattern_heap), pattern_size, true); } if (MP_STATE_VM(pixels_pattern_heap)) { pixels_pattern_heap_size = pattern_size; @@ -175,17 +175,18 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout // Wait to make sure we don't append onto the last transmission. This should only be a tick or // two. - while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {} + while (port_get_raw_ticks(NULL) < next_start_raw_ticks) { + } // Use the identified device to choose the implementation // If a PWM device is available and we have a buffer, use DMA. - if ( (pixels_pattern != NULL) && (pwm != NULL) ) { + if ((pixels_pattern != NULL) && (pwm != NULL)) { uint16_t pos = 0; // bit position - for ( uint16_t n = 0; n < numBytes; n++ ) { + for (uint16_t n = 0; n < numBytes; n++) { uint8_t pix = pixels[n]; - for ( uint8_t mask = 0x80; mask > 0; mask >>= 1 ) { + for (uint8_t mask = 0x80; mask > 0; mask >>= 1) { pixels_pattern[pos] = (pix & mask) ? MAGIC_T1H : MAGIC_T0H; pos++; } @@ -227,7 +228,7 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout // pwm->INTEN |= (PWM_INTEN_SEQEND0_Enabled<<PWM_INTEN_SEQEND0_Pos); // PSEL must be configured before enabling PWM - nrf_pwm_pins_set(pwm, (uint32_t[]) {digitalinout->pin->number, 0xFFFFFFFFUL, 0xFFFFFFFFUL, 0xFFFFFFFFUL} ); + nrf_pwm_pins_set(pwm, (uint32_t[]) {digitalinout->pin->number, 0xFFFFFFFFUL, 0xFFFFFFFFUL, 0xFFFFFFFFUL}); // Enable the PWM nrf_pwm_enable(pwm); @@ -238,7 +239,7 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout nrf_pwm_task_trigger(pwm, NRF_PWM_TASK_SEQSTART0); // But we have to wait for the flag to be set. - while ( !nrf_pwm_event_check(pwm, NRF_PWM_EVENT_SEQEND0) ) { + while (!nrf_pwm_event_check(pwm, NRF_PWM_EVENT_SEQEND0)) { RUN_BACKGROUND_TASKS; } @@ -250,7 +251,7 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout // be selected on the next call. // TODO: Check if disabling the device causes performance issues. nrf_pwm_disable(pwm); - nrf_pwm_pins_set(pwm, (uint32_t[]) {0xFFFFFFFFUL, 0xFFFFFFFFUL, 0xFFFFFFFFUL, 0xFFFFFFFFUL} ); + nrf_pwm_pins_set(pwm, (uint32_t[]) {0xFFFFFFFFUL, 0xFFFFFFFFUL, 0xFFFFFFFFUL, 0xFFFFFFFFUL}); } // End of DMA implementation // --------------------------------------------------------------------- @@ -264,9 +265,9 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout __disable_irq(); uint32_t decoded_pin = digitalinout->pin->number; - NRF_GPIO_Type* port = nrf_gpio_pin_port_decode(&decoded_pin); + NRF_GPIO_Type *port = nrf_gpio_pin_port_decode(&decoded_pin); - uint32_t pinMask = ( 1UL << decoded_pin ); + uint32_t pinMask = (1UL << decoded_pin); uint32_t CYCLES_X00 = CYCLES_800; uint32_t CYCLES_X00_T1H = CYCLES_800_T1H; @@ -277,39 +278,43 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; // Tries to re-send the frame if is interrupted by the SoftDevice. - while ( 1 ) { + while (1) { uint8_t *p = pixels; uint32_t cycStart = DWT->CYCCNT; uint32_t cyc = 0; - for ( uint16_t n = 0; n < numBytes; n++ ) { + for (uint16_t n = 0; n < numBytes; n++) { uint8_t pix = *p++; - for ( uint8_t mask = 0x80; mask; mask >>= 1 ) { - while ( DWT->CYCCNT - cyc < CYCLES_X00 ) + for (uint8_t mask = 0x80; mask; mask >>= 1) { + while (DWT->CYCCNT - cyc < CYCLES_X00) { ; + } cyc = DWT->CYCCNT; port->OUTSET |= pinMask; - if ( pix & mask ) { - while ( DWT->CYCCNT - cyc < CYCLES_X00_T1H ) + if (pix & mask) { + while (DWT->CYCCNT - cyc < CYCLES_X00_T1H) { ; + } } else { - while ( DWT->CYCCNT - cyc < CYCLES_X00_T0H ) + while (DWT->CYCCNT - cyc < CYCLES_X00_T0H) { ; + } } port->OUTCLR |= pinMask; } } - while ( DWT->CYCCNT - cyc < CYCLES_X00 ) + while (DWT->CYCCNT - cyc < CYCLES_X00) { ; + } // If total time longer than 25%, resend the whole data. // Since we are likely to be interrupted by SoftDevice - if ( (DWT->CYCCNT - cycStart) < (8 * numBytes * ((CYCLES_X00 * 5) / 4)) ) { + if ((DWT->CYCCNT - cycStart) < (8 * numBytes * ((CYCLES_X00 * 5) / 4))) { break; } diff --git a/ports/nrf/common-hal/nvm/ByteArray.c b/ports/nrf/common-hal/nvm/ByteArray.c index 6b2f04a61..5af2cc563 100644 --- a/ports/nrf/common-hal/nvm/ByteArray.c +++ b/ports/nrf/common-hal/nvm/ByteArray.c @@ -51,9 +51,9 @@ static bool write_page(uint32_t page_addr, uint32_t offset, uint32_t len, uint8_ } bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, - uint32_t start_index, uint8_t* values, uint32_t len) { + uint32_t start_index, uint8_t *values, uint32_t len) { - uint32_t address = (uint32_t) self->start_address + start_index; + uint32_t address = (uint32_t)self->start_address + start_index; uint32_t offset = address % FLASH_PAGE_SIZE; uint32_t page_addr = address - offset; @@ -71,6 +71,6 @@ bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, } void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t *self, - uint32_t start_index, uint32_t len, uint8_t* values) { + uint32_t start_index, uint32_t len, uint8_t *values) { memcpy(values, self->start_address + start_index, len); } diff --git a/ports/nrf/common-hal/nvm/ByteArray.h b/ports/nrf/common-hal/nvm/ByteArray.h index c048d5577..b3609a592 100644 --- a/ports/nrf/common-hal/nvm/ByteArray.h +++ b/ports/nrf/common-hal/nvm/ByteArray.h @@ -31,7 +31,7 @@ typedef struct { mp_obj_base_t base; - uint8_t* start_address; + uint8_t *start_address; uint32_t len; } nvm_bytearray_obj_t; diff --git a/ports/nrf/common-hal/os/__init__.c b/ports/nrf/common-hal/os/__init__.c index b2ad00a5c..5a0f10596 100644 --- a/ports/nrf/common-hal/os/__init__.c +++ b/ports/nrf/common-hal/os/__init__.c @@ -55,16 +55,16 @@ STATIC MP_DEFINE_ATTRTUPLE( (mp_obj_t)&os_uname_info_release_obj, (mp_obj_t)&os_uname_info_version_obj, (mp_obj_t)&os_uname_info_machine_obj -); + ); mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; } bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { -#ifdef BLUETOOTH_SD + #ifdef BLUETOOTH_SD uint8_t sd_en = 0; - (void) sd_softdevice_is_enabled(&sd_en); + (void)sd_softdevice_is_enabled(&sd_en); if (sd_en) { while (length != 0) { @@ -84,13 +84,15 @@ bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { } return true; } -#endif + #endif nrf_rng_event_clear(NRF_RNG, NRF_RNG_EVENT_VALRDY); nrf_rng_task_trigger(NRF_RNG, NRF_RNG_TASK_START); for (uint32_t i = 0; i < length; i++) { - while (nrf_rng_event_check(NRF_RNG, NRF_RNG_EVENT_VALRDY) == 0); + while (nrf_rng_event_check(NRF_RNG, NRF_RNG_EVENT_VALRDY) == 0) { + ; + } nrf_rng_event_clear(NRF_RNG, NRF_RNG_EVENT_VALRDY); buffer[i] = nrf_rng_random_value_get(NRF_RNG); diff --git a/ports/nrf/common-hal/pulseio/PulseIn.c b/ports/nrf/common-hal/pulseio/PulseIn.c index ca44a20b4..f8f877d96 100644 --- a/ports/nrf/common-hal/pulseio/PulseIn.c +++ b/ports/nrf/common-hal/pulseio/PulseIn.c @@ -40,7 +40,7 @@ #include "nrfx_gpiote.h" // obj array to map pin -> self since nrfx hide the mapping -static pulseio_pulsein_obj_t* _objs[GPIOTE_CH_NUM]; +static pulseio_pulsein_obj_t *_objs[GPIOTE_CH_NUM]; // A single timer is shared amongst all PulseIn objects as a common high speed clock reference. static uint8_t refcount = 0; @@ -57,9 +57,9 @@ static void timer_overflow_event_handler(nrf_timer_event_t event_type, void *p_c } // return index of the object in array -static int _find_pulsein_obj(pulseio_pulsein_obj_t* obj) { - for(size_t i = 0; i < NRFX_ARRAY_SIZE(_objs); i++ ) { - if ( _objs[i] == obj) { +static int _find_pulsein_obj(pulseio_pulsein_obj_t *obj) { + for (size_t i = 0; i < NRFX_ARRAY_SIZE(_objs); i++) { + if (_objs[i] == obj) { return i; } } @@ -72,22 +72,24 @@ static void _pulsein_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action uint32_t current_overflow = overflow_count; uint32_t current_count = nrfx_timer_capture(timer, 1); - pulseio_pulsein_obj_t* self = NULL; - for(size_t i = 0; i < NRFX_ARRAY_SIZE(_objs); i++ ) { - if ( _objs[i] && _objs[i]->pin == pin ) { + pulseio_pulsein_obj_t *self = NULL; + for (size_t i = 0; i < NRFX_ARRAY_SIZE(_objs); i++) { + if (_objs[i] && _objs[i]->pin == pin) { self = _objs[i]; break; } } - if ( !self ) return; + if (!self) { + return; + } if (self->first_edge) { // first pulse is opposite state from idle bool state = nrf_gpio_pin_read(self->pin); - if ( self->idle_state != state ) { + if (self->idle_state != state) { self->first_edge = false; } - }else { + } else { uint32_t total_diff = current_count + 0xffff * (current_overflow - self->last_overflow) - self->last_count; // Cap duration at 16 bits. @@ -110,7 +112,7 @@ static void _pulsein_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action } void pulsein_reset(void) { - if ( nrfx_gpiote_is_init() ) { + if (nrfx_gpiote_is_init()) { nrfx_gpiote_uninit(); } nrfx_gpiote_init(NRFX_GPIOTE_CONFIG_IRQ_PRIORITY); @@ -123,14 +125,14 @@ void pulsein_reset(void) { memset(_objs, 0, sizeof(_objs)); } -void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu_pin_obj_t* pin, uint16_t maxlen, bool idle_state) { +void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t *self, const mcu_pin_obj_t *pin, uint16_t maxlen, bool idle_state) { int idx = _find_pulsein_obj(NULL); - if ( idx < 0 ) { + if (idx < 0) { mp_raise_NotImplementedError(NULL); } _objs[idx] = self; - self->buffer = (uint16_t *) m_malloc(maxlen * sizeof(uint16_t), false); + self->buffer = (uint16_t *)m_malloc(maxlen * sizeof(uint16_t), false); if (self->buffer == NULL) { mp_raise_msg_varg(&mp_type_MemoryError, translate("Failed to allocate RX buffer of %d bytes"), maxlen * sizeof(uint16_t)); } @@ -180,11 +182,11 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu nrfx_gpiote_in_event_enable(self->pin, true); } -bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t* self) { - return self->pin == NO_PIN; +bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t *self) { + return self->pin == NO_PIN; } -void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t *self) { if (common_hal_pulseio_pulsein_deinited(self)) { return; } @@ -194,7 +196,7 @@ void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { // mark local array as invalid int idx = _find_pulsein_obj(self); - if ( idx < 0 ) { + if (idx < 0) { mp_raise_NotImplementedError(NULL); } _objs[idx] = NULL; @@ -208,14 +210,14 @@ void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { } } -void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t *self) { nrfx_gpiote_in_event_disable(self->pin); self->paused = true; } -void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, uint16_t trigger_duration) { +void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t *self, uint16_t trigger_duration) { // Make sure we're paused. - if ( !self->paused ) { + if (!self->paused) { common_hal_pulseio_pulsein_pause(self); } @@ -246,21 +248,21 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, uint16_t tri nrfx_gpiote_in_event_enable(self->pin, true); } -void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t* self) { - if ( !self->paused ) { +void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t *self) { + if (!self->paused) { nrfx_gpiote_in_event_disable(self->pin); } self->start = 0; self->len = 0; - if ( !self->paused ) { + if (!self->paused) { nrfx_gpiote_in_event_enable(self->pin, true); } } -uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, int16_t index) { - if ( !self->paused ) { +uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t *self, int16_t index) { + if (!self->paused) { nrfx_gpiote_in_event_disable(self->pin); } @@ -268,26 +270,26 @@ uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, int16_ index += self->len; } if (index < 0 || index >= self->len) { - if ( !self->paused ) { + if (!self->paused) { nrfx_gpiote_in_event_enable(self->pin, true); } mp_raise_IndexError_varg(translate("%q index out of range"), MP_QSTR_PulseIn); } uint16_t value = self->buffer[(self->start + index) % self->maxlen]; - if ( !self->paused ) { + if (!self->paused) { nrfx_gpiote_in_event_enable(self->pin, true); } return value; } -uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t *self) { if (self->len == 0) { mp_raise_IndexError_varg(translate("pop from empty %q"), MP_QSTR_PulseIn); } - if ( !self->paused ) { + if (!self->paused) { nrfx_gpiote_in_event_disable(self->pin); } @@ -295,21 +297,21 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { self->start = (self->start + 1) % self->maxlen; self->len--; - if ( !self->paused ) { + if (!self->paused) { nrfx_gpiote_in_event_enable(self->pin, true); } return value; } -uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t *self) { return self->maxlen; } -bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t *self) { return self->paused; } -uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t *self) { return self->len; } diff --git a/ports/nrf/common-hal/pulseio/PulseIn.h b/ports/nrf/common-hal/pulseio/PulseIn.h index da5263ac9..cdd0e6690 100644 --- a/ports/nrf/common-hal/pulseio/PulseIn.h +++ b/ports/nrf/common-hal/pulseio/PulseIn.h @@ -39,7 +39,7 @@ typedef struct { bool paused; volatile bool first_edge; - uint16_t* buffer; + uint16_t *buffer; uint16_t maxlen; volatile uint16_t start; diff --git a/ports/nrf/common-hal/pulseio/PulseOut.c b/ports/nrf/common-hal/pulseio/PulseOut.c index f40dbea5c..17f498ba8 100644 --- a/ports/nrf/common-hal/pulseio/PulseOut.c +++ b/ports/nrf/common-hal/pulseio/PulseOut.c @@ -66,7 +66,7 @@ static void start_timer(void) { } static void pulseout_event_handler(nrf_timer_event_t event_type, void *p_context) { - pulseio_pulseout_obj_t *pulseout = (pulseio_pulseout_obj_t*) p_context; + pulseio_pulseout_obj_t *pulseout = (pulseio_pulseout_obj_t *)p_context; if (event_type != NRF_TIMER_EVENT_COMPARE0) { // Spurious event. return; @@ -99,11 +99,11 @@ void pulseout_reset() { refcount = 0; } -void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, - const pwmio_pwmout_obj_t* carrier, - const mcu_pin_obj_t* pin, - uint32_t frequency, - uint16_t duty_cycle) { +void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self, + const pwmio_pwmout_obj_t *carrier, + const mcu_pin_obj_t *pin, + uint32_t frequency, + uint16_t duty_cycle) { if (!carrier || pin || frequency) { mp_raise_NotImplementedError(translate("Port does not accept pins or frequency. Construct and pass a PWMOut Carrier instead")); } @@ -128,11 +128,11 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, turn_off(self); } -bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t* self) { +bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t *self) { return self->pwmout == NULL; } -void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { +void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t *self) { if (common_hal_pulseio_pulseout_deinited(self)) { return; } @@ -145,7 +145,7 @@ void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { } } -void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pulses, uint16_t length) { +void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pulses, uint16_t length) { pulse_array = pulses; pulse_array_index = 0; pulse_array_length = length; @@ -156,7 +156,7 @@ void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pu // Count up to the next given value. start_timer(); - while(pulse_array_index < length) { + while (pulse_array_index < length) { // Do other things while we wait. The interrupts will handle sending the // signal. RUN_BACKGROUND_TASKS; diff --git a/ports/nrf/common-hal/pwmio/PWMOut.c b/ports/nrf/common-hal/pwmio/PWMOut.c index a9d896488..e49214631 100644 --- a/ports/nrf/common-hal/pwmio/PWMOut.c +++ b/ports/nrf/common-hal/pwmio/PWMOut.c @@ -36,19 +36,19 @@ #define PWM_MAX_FREQ (16000000) -STATIC NRF_PWM_Type* pwms[] = { -#if NRFX_CHECK(NRFX_PWM0_ENABLED) +STATIC NRF_PWM_Type *pwms[] = { + #if NRFX_CHECK(NRFX_PWM0_ENABLED) NRF_PWM0, -#endif -#if NRFX_CHECK(NRFX_PWM1_ENABLED) + #endif + #if NRFX_CHECK(NRFX_PWM1_ENABLED) NRF_PWM1, -#endif -#if NRFX_CHECK(NRFX_PWM2_ENABLED) + #endif + #if NRFX_CHECK(NRFX_PWM2_ENABLED) NRF_PWM2, -#endif -#if NRFX_CHECK(NRFX_PWM3_ENABLED) + #endif + #if NRFX_CHECK(NRFX_PWM3_ENABLED) NRF_PWM3, -#endif + #endif }; #define CHANNELS_PER_PWM 4 @@ -58,14 +58,17 @@ STATIC uint16_t pwm_seq[MP_ARRAY_SIZE(pwms)][CHANNELS_PER_PWM]; static uint8_t never_reset_pwm[MP_ARRAY_SIZE(pwms)]; STATIC int pwm_idx(NRF_PWM_Type *pwm) { - for(size_t i=0; i < MP_ARRAY_SIZE(pwms); i++) - if(pwms[i] == pwm) return i; + for (size_t i = 0; i < MP_ARRAY_SIZE(pwms); i++) { + if (pwms[i] == pwm) { + return i; + } + } return -1; } void common_hal_pwmio_pwmout_never_reset(pwmio_pwmout_obj_t *self) { - for(size_t i=0; i < MP_ARRAY_SIZE(pwms); i++) { - NRF_PWM_Type* pwm = pwms[i]; + for (size_t i = 0; i < MP_ARRAY_SIZE(pwms); i++) { + NRF_PWM_Type *pwm = pwms[i]; if (pwm == self->pwm) { never_reset_pwm[i] += 1; } @@ -75,8 +78,8 @@ void common_hal_pwmio_pwmout_never_reset(pwmio_pwmout_obj_t *self) { } void common_hal_pwmio_pwmout_reset_ok(pwmio_pwmout_obj_t *self) { - for(size_t i=0; i < MP_ARRAY_SIZE(pwms); i++) { - NRF_PWM_Type* pwm = pwms[i]; + for (size_t i = 0; i < MP_ARRAY_SIZE(pwms); i++) { + NRF_PWM_Type *pwm = pwms[i]; if (pwm == self->pwm) { never_reset_pwm[i] -= 1; } @@ -84,32 +87,32 @@ void common_hal_pwmio_pwmout_reset_ok(pwmio_pwmout_obj_t *self) { } void reset_single_pwmout(uint8_t i) { - NRF_PWM_Type* pwm = pwms[i]; - - pwm->ENABLE = 0; - pwm->MODE = PWM_MODE_UPDOWN_Up; - pwm->DECODER = PWM_DECODER_LOAD_Individual; - pwm->LOOP = 0; - pwm->PRESCALER = PWM_PRESCALER_PRESCALER_DIV_1; // default is 500 hz - pwm->COUNTERTOP = (PWM_MAX_FREQ/500); // default is 500 hz - - pwm->SEQ[0].PTR = (uint32_t) pwm_seq[i]; - pwm->SEQ[0].CNT = CHANNELS_PER_PWM; // default mode is Individual --> count must be 4 - pwm->SEQ[0].REFRESH = 0; + NRF_PWM_Type *pwm = pwms[i]; + + pwm->ENABLE = 0; + pwm->MODE = PWM_MODE_UPDOWN_Up; + pwm->DECODER = PWM_DECODER_LOAD_Individual; + pwm->LOOP = 0; + pwm->PRESCALER = PWM_PRESCALER_PRESCALER_DIV_1; // default is 500 hz + pwm->COUNTERTOP = (PWM_MAX_FREQ / 500); // default is 500 hz + + pwm->SEQ[0].PTR = (uint32_t)pwm_seq[i]; + pwm->SEQ[0].CNT = CHANNELS_PER_PWM; // default mode is Individual --> count must be 4 + pwm->SEQ[0].REFRESH = 0; pwm->SEQ[0].ENDDELAY = 0; - pwm->SEQ[1].PTR = 0; - pwm->SEQ[1].CNT = 0; - pwm->SEQ[1].REFRESH = 0; + pwm->SEQ[1].PTR = 0; + pwm->SEQ[1].CNT = 0; + pwm->SEQ[1].REFRESH = 0; pwm->SEQ[1].ENDDELAY = 0; - for(int ch =0; ch < CHANNELS_PER_PWM; ch++) { + for (int ch = 0; ch < CHANNELS_PER_PWM; ch++) { pwm_seq[i][ch] = (1 << 15); // polarity = 0 } } void pwmout_reset(void) { - for(size_t i=0; i < MP_ARRAY_SIZE(pwms); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(pwms); i++) { if (never_reset_pwm[i] > 0) { continue; } @@ -143,8 +146,8 @@ bool convert_frequency(uint32_t frequency, uint16_t *countertop, nrf_pwm_clk_t * static IRQn_Type pwm_irqs[4] = {PWM0_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn}; NRF_PWM_Type *pwmout_allocate(uint16_t countertop, nrf_pwm_clk_t base_clock, - bool variable_frequency, int8_t *channel_out, bool *pwm_already_in_use_out, - IRQn_Type* irq) { + bool variable_frequency, int8_t *channel_out, bool *pwm_already_in_use_out, + IRQn_Type *irq) { for (size_t pwm_index = 0; pwm_index < MP_ARRAY_SIZE(pwms); pwm_index++) { NRF_PWM_Type *pwm = pwms[pwm_index]; bool pwm_already_in_use = pwm->ENABLE & PWM_ENABLE_ENABLE_Msk; @@ -194,7 +197,7 @@ void pwmout_free_channel(NRF_PWM_Type *pwm, int8_t channel) { // Disconnect pin from channel. pwm->PSEL.OUT[channel] = 0xFFFFFFFF; - for(int i=0; i < CHANNELS_PER_PWM; i++) { + for (int i = 0; i < CHANNELS_PER_PWM; i++) { if (pwm->PSEL.OUT[i] != 0xFFFFFFFF) { // Some channel is still being used, so don't disable. return; @@ -204,11 +207,11 @@ void pwmout_free_channel(NRF_PWM_Type *pwm, int8_t channel) { nrf_pwm_disable(pwm); } -pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, - const mcu_pin_obj_t* pin, - uint16_t duty, - uint32_t frequency, - bool variable_frequency) { +pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, + const mcu_pin_obj_t *pin, + uint16_t duty, + uint32_t frequency, + bool variable_frequency) { // We don't use the nrfx driver here because we want to dynamically allocate channels // as needed in an already-enabled PWM. @@ -255,18 +258,18 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, return PWMOUT_OK; } -bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) { return self->pwm == NULL; } -void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { +void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) { if (common_hal_pwmio_pwmout_deinited(self)) { return; } nrf_gpio_cfg_default(self->pin_number); - NRF_PWM_Type* pwm = self->pwm; + NRF_PWM_Type *pwm = self->pwm; self->pwm = NULL; pwmout_free_channel(pwm, self->channel); @@ -275,20 +278,20 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { self->pin_number = NO_PIN; } -void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t* self, uint16_t duty_cycle) { +void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t duty_cycle) { self->duty_cycle = duty_cycle; - uint16_t* p_value = ((uint16_t*)self->pwm->SEQ[0].PTR) + self->channel; + uint16_t *p_value = ((uint16_t *)self->pwm->SEQ[0].PTR) + self->channel; *p_value = ((duty_cycle * self->pwm->COUNTERTOP) / 0xFFFF) | (1 << 15); self->pwm->TASKS_SEQSTART[0] = 1; } -uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) { +uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) { return self->duty_cycle; } -void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t frequency) { +void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self, uint32_t frequency) { // COUNTERTOP is 3..32767, so highest available frequency is PWM_MAX_FREQ / 3. uint16_t countertop; nrf_pwm_clk_t base_clock; @@ -303,10 +306,10 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t fr common_hal_pwmio_pwmout_set_duty_cycle(self, self->duty_cycle); } -uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) { +uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) { return self->frequency; } -bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) { return self->variable_frequency; } diff --git a/ports/nrf/common-hal/pwmio/PWMOut.h b/ports/nrf/common-hal/pwmio/PWMOut.h index e910baa76..f96c5e4f8 100644 --- a/ports/nrf/common-hal/pwmio/PWMOut.h +++ b/ports/nrf/common-hal/pwmio/PWMOut.h @@ -32,10 +32,10 @@ typedef struct { mp_obj_base_t base; - NRF_PWM_Type* pwm; + NRF_PWM_Type *pwm; uint8_t pin_number; - uint8_t channel: 7; - bool variable_frequency: 1; + uint8_t channel : 7; + bool variable_frequency : 1; uint16_t duty_cycle; uint32_t frequency; } pwmio_pwmout_obj_t; diff --git a/ports/nrf/common-hal/rgbmatrix/RGBMatrix.c b/ports/nrf/common-hal/rgbmatrix/RGBMatrix.c index d8289f56f..238fee976 100644 --- a/ports/nrf/common-hal/rgbmatrix/RGBMatrix.c +++ b/ports/nrf/common-hal/rgbmatrix/RGBMatrix.c @@ -43,7 +43,7 @@ static void rgbmatrix_event_handler(nrf_timer_event_t event_type, void *p_contex _PM_IRQ_HANDLER(); } -void common_hal_rgbmatrix_timer_enable(void* ptr) { +void common_hal_rgbmatrix_timer_enable(void *ptr) { nrfx_timer_t *timer = nrf_peripherals_timer_from_reg(ptr); static const nrfx_timer_config_t timer_config = { .frequency = NRF_TIMER_FREQ_16MHz, @@ -55,12 +55,12 @@ void common_hal_rgbmatrix_timer_enable(void* ptr) { nrfx_timer_init(timer, &timer_config, &rgbmatrix_event_handler); } -void common_hal_rgbmatrix_timer_disable(void* ptr) { +void common_hal_rgbmatrix_timer_disable(void *ptr) { nrfx_timer_t *timer = nrf_peripherals_timer_from_reg(ptr); nrfx_timer_uninit(timer); } -void common_hal_rgbmatrix_timer_free(void* ptr) { +void common_hal_rgbmatrix_timer_free(void *ptr) { nrfx_timer_t *timer = nrf_peripherals_timer_from_reg(ptr); nrf_peripherals_free_timer(timer); } diff --git a/ports/nrf/common-hal/rgbmatrix/RGBMatrix.h b/ports/nrf/common-hal/rgbmatrix/RGBMatrix.h index 6cf7354fc..8101b9c6b 100644 --- a/ports/nrf/common-hal/rgbmatrix/RGBMatrix.h +++ b/ports/nrf/common-hal/rgbmatrix/RGBMatrix.h @@ -30,8 +30,8 @@ #include "shared-module/rgbmatrix/RGBMatrix.h" void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self); -void common_hal_rgbmatrix_timer_enable(void*); -void common_hal_rgbmatrix_timer_disable(void*); -void common_hal_rgbmatrix_timer_free(void*); +void common_hal_rgbmatrix_timer_enable(void *); +void common_hal_rgbmatrix_timer_disable(void *); +void common_hal_rgbmatrix_timer_free(void *); #endif diff --git a/ports/nrf/common-hal/rotaryio/IncrementalEncoder.c b/ports/nrf/common-hal/rotaryio/IncrementalEncoder.c index 28f563da6..ef5e9ee5a 100644 --- a/ports/nrf/common-hal/rotaryio/IncrementalEncoder.c +++ b/ports/nrf/common-hal/rotaryio/IncrementalEncoder.c @@ -36,15 +36,20 @@ static rotaryio_incrementalencoder_obj_t *_objs[NUMBER_OF_PINS]; static void _intr_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { rotaryio_incrementalencoder_obj_t *self = _objs[pin]; - if (!self) return; + if (!self) { + return; + } // reads a state 0 .. 3 *in order*. uint8_t new_state = nrf_gpio_pin_read(self->pin_a); new_state = (new_state << 1) + (new_state ^ nrf_gpio_pin_read(self->pin_b)); uint8_t change = (new_state - self->state) & 0x03; - if (change == 1) self->quarter++; - else if (change == 3) self->quarter--; + if (change == 1) { + self->quarter++; + } else if (change == 3) { + self->quarter--; + } // ignore other state transitions self->state = new_state; @@ -60,8 +65,8 @@ static void _intr_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) { } } -void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencoder_obj_t* self, - const mcu_pin_obj_t* pin_a, const mcu_pin_obj_t* pin_b) { +void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencoder_obj_t *self, + const mcu_pin_obj_t *pin_a, const mcu_pin_obj_t *pin_b) { self->pin_a = pin_a->number; self->pin_b = pin_b->number; @@ -85,11 +90,11 @@ void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencode claim_pin(pin_b); } -bool common_hal_rotaryio_incrementalencoder_deinited(rotaryio_incrementalencoder_obj_t* self) { +bool common_hal_rotaryio_incrementalencoder_deinited(rotaryio_incrementalencoder_obj_t *self) { return self->pin_a == NO_PIN; } -void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_obj_t* self) { +void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_obj_t *self) { if (common_hal_rotaryio_incrementalencoder_deinited(self)) { return; } @@ -106,11 +111,11 @@ void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_o self->pin_b = NO_PIN; } -mp_int_t common_hal_rotaryio_incrementalencoder_get_position(rotaryio_incrementalencoder_obj_t* self) { +mp_int_t common_hal_rotaryio_incrementalencoder_get_position(rotaryio_incrementalencoder_obj_t *self) { return self->position; } -void common_hal_rotaryio_incrementalencoder_set_position(rotaryio_incrementalencoder_obj_t* self, - mp_int_t new_position) { +void common_hal_rotaryio_incrementalencoder_set_position(rotaryio_incrementalencoder_obj_t *self, + mp_int_t new_position) { self->position = new_position; } diff --git a/ports/nrf/common-hal/rtc/RTC.c b/ports/nrf/common-hal/rtc/RTC.c index 93ba007c8..cdffe094a 100644 --- a/ports/nrf/common-hal/rtc/RTC.c +++ b/ports/nrf/common-hal/rtc/RTC.c @@ -49,8 +49,9 @@ __attribute__((section(".uninitialized"))) static uint32_t rtc_offset[3]; void common_hal_rtc_init(void) { // If the prefix and suffix are not valid, zero-initialize the RTC offset. - if ((rtc_offset[0] != RTC_OFFSET_CHECK_PREFIX) || (rtc_offset[2] != RTC_OFFSET_CHECK_SUFFIX)) + if ((rtc_offset[0] != RTC_OFFSET_CHECK_PREFIX) || (rtc_offset[2] != RTC_OFFSET_CHECK_SUFFIX)) { rtc_offset[1] = 0; + } } void common_hal_rtc_get_time(timeutils_struct_time_t *tm) { @@ -62,7 +63,7 @@ void common_hal_rtc_set_time(timeutils_struct_time_t *tm) { uint64_t ticks_s = port_get_raw_ticks(NULL) / 1024; uint32_t epoch_s = timeutils_seconds_since_2000( tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec - ); + ); rtc_offset[1] = epoch_s - ticks_s; // Set the prefix and suffix in order to indicate the time is valid. This diff --git a/ports/nrf/common-hal/supervisor/Runtime.c b/ports/nrf/common-hal/supervisor/Runtime.c index a24e86cdf..f82765178 100755..100644 --- a/ports/nrf/common-hal/supervisor/Runtime.c +++ b/ports/nrf/common-hal/supervisor/Runtime.c @@ -29,9 +29,9 @@ #include "supervisor/serial.h" bool common_hal_supervisor_runtime_get_serial_connected(void) { - return (bool) serial_connected(); + return (bool)serial_connected(); } bool common_hal_supervisor_runtime_get_serial_bytes_available(void) { - return (bool) serial_bytes_available(); + return (bool)serial_bytes_available(); } diff --git a/ports/nrf/common-hal/watchdog/WatchDogTimer.c b/ports/nrf/common-hal/watchdog/WatchDogTimer.c index 539b43e76..3423d3466 100644 --- a/ports/nrf/common-hal/watchdog/WatchDogTimer.c +++ b/ports/nrf/common-hal/watchdog/WatchDogTimer.c @@ -62,11 +62,11 @@ STATIC void watchdogtimer_timer_event_handler(nrf_timer_event_t event_type, void self->mode = WATCHDOGMODE_NONE; mp_obj_exception_clear_traceback(MP_OBJ_FROM_PTR(&mp_watchdog_timeout_exception)); MP_STATE_VM(mp_pending_exception) = &mp_watchdog_timeout_exception; -#if MICROPY_ENABLE_SCHEDULER + #if MICROPY_ENABLE_SCHEDULER if (MP_STATE_VM(sched_state) == MP_SCHED_IDLE) { MP_STATE_VM(sched_state) = MP_SCHED_PENDING; } -#endif + #endif } static void timer_free(void) { diff --git a/ports/nrf/common-hal/watchdog/WatchDogTimer.h b/ports/nrf/common-hal/watchdog/WatchDogTimer.h index 8d6df934e..1ff654c32 100644 --- a/ports/nrf/common-hal/watchdog/WatchDogTimer.h +++ b/ports/nrf/common-hal/watchdog/WatchDogTimer.h @@ -32,9 +32,9 @@ #include "shared-bindings/watchdog/WatchDogTimer.h" struct _watchdog_watchdogtimer_obj_t { - mp_obj_base_t base; - mp_float_t timeout; - watchdog_watchdogmode_t mode; + mp_obj_base_t base; + mp_float_t timeout; + watchdog_watchdogmode_t mode; }; // This needs to be called in order to disable the watchdog if it's set to diff --git a/ports/nrf/device/nrf52/startup_nrf52.c b/ports/nrf/device/nrf52/startup_nrf52.c index 614b8c2d3..81eaa4e32 100644 --- a/ports/nrf/device/nrf52/startup_nrf52.c +++ b/ports/nrf/device/nrf52/startup_nrf52.c @@ -41,19 +41,21 @@ extern void _start(void) __attribute__((noreturn)); extern void SystemInit(void); void Default_Handler(void) { - while (1); + while (1) { + ; + } } void Reset_Handler(void) { - uint32_t * p_src = &_sidata; - uint32_t * p_dest = &_sdata; + uint32_t *p_src = &_sidata; + uint32_t *p_dest = &_sdata; while (p_dest < &_edata) { - *p_dest++ = *p_src++; + *p_dest++ = *p_src++; } - uint32_t * p_bss = &_sbss; - uint32_t * p_bss_end = &_ebss; + uint32_t *p_bss = &_sbss; + uint32_t *p_bss_end = &_ebss; while (p_bss < p_bss_end) { *p_bss++ = 0ul; } @@ -62,55 +64,55 @@ void Reset_Handler(void) { _start(); } -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MemoryManagement_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MemoryManagement_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RADIO_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTE0_UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void NFCT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIOTE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SAADC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TEMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ECB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void CCM_AAR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void QDEC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void COMP_LPCOMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI0_EGU0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI1_EGU1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI2_EGU2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI3_EGU3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI4_EGU4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI5_EGU5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PDM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MWU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void POWER_CLOCK_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RADIO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTE0_UART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void NFCT_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOTE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SAADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TEMP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ECB_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void CCM_AAR_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WDT_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void QDEC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_LPCOMP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI0_EGU0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI1_EGU1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI2_EGU2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI3_EGU3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI4_EGU4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI5_EGU5_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PDM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MWU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM2_SPIS2_SPI2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); const func __Vectors[] __attribute__ ((section(".isr_vector"))) = { - (func)&_estack, + (func) & _estack, Reset_Handler, NMI_Handler, HardFault_Handler, diff --git a/ports/nrf/device/nrf52/startup_nrf52833.c b/ports/nrf/device/nrf52/startup_nrf52833.c index ad875dcee..ad6083952 100644 --- a/ports/nrf/device/nrf52/startup_nrf52833.c +++ b/ports/nrf/device/nrf52/startup_nrf52833.c @@ -41,19 +41,21 @@ extern void _start(void) __attribute__((noreturn)); extern void SystemInit(void); void Default_Handler(void) { - while (1); + while (1) { + ; + } } void Reset_Handler(void) { - uint32_t * p_src = &_sidata; - uint32_t * p_dest = &_sdata; + uint32_t *p_src = &_sidata; + uint32_t *p_dest = &_sdata; while (p_dest < &_edata) { - *p_dest++ = *p_src++; + *p_dest++ = *p_src++; } - uint32_t * p_bss = &_sbss; - uint32_t * p_bss_end = &_ebss; + uint32_t *p_bss = &_sbss; + uint32_t *p_bss_end = &_ebss; while (p_bss < p_bss_end) { *p_bss++ = 0ul; } @@ -62,60 +64,60 @@ void Reset_Handler(void) { _start(); } -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MemoryManagement_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MemoryManagement_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RADIO_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTE0_UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void NFCT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIOTE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SAADC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TEMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ECB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void CCM_AAR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void QDEC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void COMP_LPCOMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI0_EGU0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI1_EGU1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI2_EGU2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI3_EGU3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI4_EGU4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI5_EGU5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PDM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MWU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void USBD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTE1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void POWER_CLOCK_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RADIO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTE0_UART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void NFCT_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOTE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SAADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TEMP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ECB_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void CCM_AAR_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WDT_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void QDEC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_LPCOMP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI0_EGU0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI1_EGU1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI2_EGU2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI3_EGU3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI4_EGU4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI5_EGU5_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PDM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MWU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM2_SPIS2_SPI2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FPU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USBD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTE1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); const func __Vectors[] __attribute__ ((used, section(".isr_vector"))) = { - (func)&_estack, + (func) & _estack, Reset_Handler, NMI_Handler, HardFault_Handler, diff --git a/ports/nrf/device/nrf52/startup_nrf52840.c b/ports/nrf/device/nrf52/startup_nrf52840.c index 8e1c36012..67380303d 100644 --- a/ports/nrf/device/nrf52/startup_nrf52840.c +++ b/ports/nrf/device/nrf52/startup_nrf52840.c @@ -41,19 +41,21 @@ extern void _start(void) __attribute__((noreturn)); extern void SystemInit(void); void Default_Handler(void) { - while (1); + while (1) { + ; + } } void Reset_Handler(void) { - uint32_t * p_src = &_sidata; - uint32_t * p_dest = &_sdata; + uint32_t *p_src = &_sidata; + uint32_t *p_dest = &_sdata; while (p_dest < &_edata) { - *p_dest++ = *p_src++; + *p_dest++ = *p_src++; } - uint32_t * p_bss = &_sbss; - uint32_t * p_bss_end = &_ebss; + uint32_t *p_bss = &_sbss; + uint32_t *p_bss_end = &_ebss; while (p_bss < p_bss_end) { *p_bss++ = 0ul; } @@ -62,62 +64,62 @@ void Reset_Handler(void) { _start(); } -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MemoryManagement_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MemoryManagement_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void POWER_CLOCK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RADIO_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTE0_UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void NFCT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIOTE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SAADC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TEMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RNG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ECB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void CCM_AAR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void QDEC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void COMP_LPCOMP_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI0_EGU0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI1_EGU1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI2_EGU2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI3_EGU3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI4_EGU4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SWI5_EGU5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PDM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MWU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM2_SPIS2_SPI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void USBD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTE1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void QSPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void CRYPTOCELL_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPIM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PWM3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void POWER_CLOCK_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RADIO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTE0_UART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void NFCT_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOTE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SAADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TEMP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RNG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ECB_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void CCM_AAR_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WDT_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void QDEC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void COMP_LPCOMP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI0_EGU0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI1_EGU1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI2_EGU2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI3_EGU3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI4_EGU4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SWI5_EGU5_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PDM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MWU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM2_SPIS2_SPI2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FPU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USBD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTE1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void QSPI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void CRYPTOCELL_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SPIM3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); const func __Vectors[] __attribute__ ((used, section(".isr_vector"))) = { - (func)&_estack, + (func) & _estack, Reset_Handler, NMI_Handler, HardFault_Handler, diff --git a/ports/nrf/examples/ubluepy_eddystone.py b/ports/nrf/examples/ubluepy_eddystone.py index 426a4aa55..96818d01c 100644 --- a/ports/nrf/examples/ubluepy_eddystone.py +++ b/ports/nrf/examples/ubluepy_eddystone.py @@ -1,13 +1,16 @@ from ubluepy import Peripheral, constants -BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE = const(0x02) -BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED = const(0x04) +BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE = const(0x02) +BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED = const(0x04) -BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE = const(BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) +BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE = const( + BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED +) + +EDDYSTONE_FRAME_TYPE_URL = const(0x10) +EDDYSTONE_URL_PREFIX_HTTP_WWW = const(0x00) # "http://www". +EDDYSTONE_URL_SUFFIX_DOT_COM = const(0x01) # ".com" -EDDYSTONE_FRAME_TYPE_URL = const(0x10) -EDDYSTONE_URL_PREFIX_HTTP_WWW = const(0x00) # "http://www". -EDDYSTONE_URL_SUFFIX_DOT_COM = const(0x01) # ".com" def string_to_binarray(text): b = bytearray([]) @@ -15,6 +18,7 @@ def string_to_binarray(text): b.append(ord(c)) return b + def gen_ad_type_content(ad_type, data): b = bytearray(1) b.append(ad_type) @@ -22,6 +26,7 @@ def gen_ad_type_content(ad_type, data): b[0] = len(b) - 1 return b + def generate_eddystone_adv_packet(url): # flags disc_mode = bytearray([BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE]) @@ -29,10 +34,12 @@ def generate_eddystone_adv_packet(url): # 16-bit uuid uuid = bytearray([0xAA, 0xFE]) - packet_uuid16 = gen_ad_type_content(constants.ad_types.AD_TYPE_16BIT_SERVICE_UUID_COMPLETE, uuid) + packet_uuid16 = gen_ad_type_content( + constants.ad_types.AD_TYPE_16BIT_SERVICE_UUID_COMPLETE, uuid + ) # eddystone data - rssi = 0xEE # -18 dB, approx signal strength at 0m. + rssi = 0xEE # -18 dB, approx signal strength at 0m. eddystone_data = bytearray([]) eddystone_data.append(EDDYSTONE_FRAME_TYPE_URL) eddystone_data.append(rssi) @@ -42,7 +49,9 @@ def generate_eddystone_adv_packet(url): # service data service_data = uuid + eddystone_data - packet_service_data = gen_ad_type_content(constants.ad_types.AD_TYPE_SERVICE_DATA, service_data) + packet_service_data = gen_ad_type_content( + constants.ad_types.AD_TYPE_SERVICE_DATA, service_data + ) # generate advertisement packet packet = bytearray([]) @@ -52,6 +61,7 @@ def generate_eddystone_adv_packet(url): return packet + def start(): adv_packet = generate_eddystone_adv_packet("micropython") p = Peripheral() diff --git a/ports/nrf/examples/ubluepy_scan.py b/ports/nrf/examples/ubluepy_scan.py index c0a7d05a3..37daa6c69 100644 --- a/ports/nrf/examples/ubluepy_scan.py +++ b/ports/nrf/examples/ubluepy_scan.py @@ -1,21 +1,24 @@ from ubluepy import Scanner, constants + def bytes_to_str(bytes): string = "" for b in bytes: string += chr(b) return string + def get_device_names(scan_entries): dev_names = [] for e in scan_entries: scan = e.getScanData() if scan: for s in scan: - if s[0] == constants.ad_types.AD_TYPE_COMPLETE_LOCAL_NAME: - dev_names.append((e, bytes_to_str(s[2]))) + if s[0] == constants.ad_types.AD_TYPE_COMPLETE_LOCAL_NAME: + dev_names.append((e, bytes_to_str(s[2]))) return dev_names + def find_device_by_name(name): s = Scanner() scan_res = s.scan(100) @@ -25,6 +28,7 @@ def find_device_by_name(name): if name == dev[1]: return dev[0] + # >>> res = find_device_by_name("micr") # >>> if res: # ... print("address:", res.addr()) diff --git a/ports/nrf/examples/ubluepy_temp.py b/ports/nrf/examples/ubluepy_temp.py index 405f77c4b..c70235c4a 100644 --- a/ports/nrf/examples/ubluepy_temp.py +++ b/ports/nrf/examples/ubluepy_temp.py @@ -26,6 +26,7 @@ from pyb import LED from machine import RTC, Temp from ubluepy import Service, Characteristic, UUID, Peripheral, constants + def event_handler(id, handle, data): global rtc global periph @@ -55,6 +56,7 @@ def event_handler(id, handle, data): # stop low power timer rtc.stop() + def send_temp(timer_id): global notif_enabled global char_temp @@ -62,9 +64,10 @@ def send_temp(timer_id): if notif_enabled: # measure chip temperature temp = Temp.read() - temp = temp * 100 + temp = temp * 100 char_temp.write(bytearray([temp & 0xFF, temp >> 8])) + # start off with LED(1) off LED(1).off() @@ -74,14 +77,14 @@ rtc = RTC(1, period=5, mode=RTC.PERIODIC, callback=send_temp) notif_enabled = False -uuid_env_sense = UUID("0x181A") # Environmental Sensing service -uuid_temp = UUID("0x2A6E") # Temperature characteristic +uuid_env_sense = UUID("0x181A") # Environmental Sensing service +uuid_temp = UUID("0x2A6E") # Temperature characteristic serv_env_sense = Service(uuid_env_sense) temp_props = Characteristic.PROP_NOTIFY | Characteristic.PROP_READ temp_attrs = Characteristic.ATTR_CCCD -char_temp = Characteristic(uuid_temp, props = temp_props, attrs = temp_attrs) +char_temp = Characteristic(uuid_temp, props=temp_props, attrs=temp_attrs) serv_env_sense.addCharacteristic(char_temp) diff --git a/ports/nrf/fatfs_port.c b/ports/nrf/fatfs_port.c index 2b741f993..5347af417 100644 --- a/ports/nrf/fatfs_port.c +++ b/ports/nrf/fatfs_port.c @@ -31,12 +31,12 @@ #include "shared-bindings/time/__init__.h" DWORD get_fattime(void) { -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC timeutils_struct_time_t tm; common_hal_rtc_get_time(&tm); return ((tm.tm_year - 1980) << 25) | (tm.tm_mon << 21) | (tm.tm_mday << 16) | - (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); -#else + (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); + #else return ((2016 - 1980) << 25) | ((9) << 21) | ((1) << 16) | ((16) << 11) | ((43) << 5) | (35 / 2); -#endif + #endif } diff --git a/ports/nrf/freeze/test.py b/ports/nrf/freeze/test.py index e64bbc9f5..ba05ae102 100644 --- a/ports/nrf/freeze/test.py +++ b/ports/nrf/freeze/test.py @@ -1,4 +1,5 @@ import sys + def hello(): print("Hello %s!" % sys.platform) diff --git a/ports/nrf/gccollect.c b/ports/nrf/gccollect.c index 3661daa53..453bc61f2 100644 --- a/ports/nrf/gccollect.c +++ b/ports/nrf/gccollect.c @@ -31,11 +31,10 @@ #include "py/gc.h" #include "gccollect.h" -static inline uint32_t get_msp(void) -{ - register uint32_t result; - __asm volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); +static inline uint32_t get_msp(void) { + register uint32_t result; + __asm volatile ("MRS %0, msp\n" : "=r" (result)); + return result; } void gc_collect(void) { @@ -45,7 +44,7 @@ void gc_collect(void) { mp_uint_t sp = get_msp(); // Get stack pointer // trace the stack, including the registers (since they live on the stack in this function) - gc_collect_root((void**)sp, ((uint32_t)&_ram_end - sp) / sizeof(uint32_t)); + gc_collect_root((void **)sp, ((uint32_t)&_ram_end - sp) / sizeof(uint32_t)); // end the GC gc_collect_end(); diff --git a/ports/nrf/ld_defines.c b/ports/nrf/ld_defines.c index 6e266e4f7..7a59531b0 100644 --- a/ports/nrf/ld_defines.c +++ b/ports/nrf/ld_defines.c @@ -9,44 +9,44 @@ // The next line is a marker to start looking for definitions. Lines above the next line are ignored. // START_LD_DEFINES -/*FLASH_SIZE=*/ FLASH_SIZE; -/*RAM_START_ADDR=*/ RAM_START_ADDR; -/*RAM_SIZE=*/ RAM_SIZE; +/*FLASH_SIZE=*/ FLASH_SIZE; +/*RAM_START_ADDR=*/ RAM_START_ADDR; +/*RAM_SIZE=*/ RAM_SIZE; -/*MBR_START_ADDR=*/ MBR_START_ADDR; -/*MBR_SIZE=*/ MBR_SIZE; +/*MBR_START_ADDR=*/ MBR_START_ADDR; +/*MBR_SIZE=*/ MBR_SIZE; -/*SD_FLASH_START_ADDR=*/ SD_FLASH_START_ADDR; -/*SD_FLASH_SIZE=*/ SD_FLASH_SIZE; +/*SD_FLASH_START_ADDR=*/ SD_FLASH_START_ADDR; +/*SD_FLASH_SIZE=*/ SD_FLASH_SIZE; -/*ISR_START_ADDR=*/ ISR_START_ADDR; -/*ISR_SIZE=*/ ISR_SIZE; +/*ISR_START_ADDR=*/ ISR_START_ADDR; +/*ISR_SIZE=*/ ISR_SIZE; -/*CIRCUITPY_DEFAULT_STACK_SIZE=*/ CIRCUITPY_DEFAULT_STACK_SIZE; +/*CIRCUITPY_DEFAULT_STACK_SIZE=*/ CIRCUITPY_DEFAULT_STACK_SIZE; -/*CIRCUITPY_FIRMWARE_START_ADDR=*/ CIRCUITPY_FIRMWARE_START_ADDR; -/*CIRCUITPY_FIRMWARE_SIZE=*/ CIRCUITPY_FIRMWARE_SIZE; +/*CIRCUITPY_FIRMWARE_START_ADDR=*/ CIRCUITPY_FIRMWARE_START_ADDR; +/*CIRCUITPY_FIRMWARE_SIZE=*/ CIRCUITPY_FIRMWARE_SIZE; -/*CIRCUITPY_BLE_CONFIG_START_ADDR=*/ CIRCUITPY_BLE_CONFIG_START_ADDR; -/*CIRCUITPY_BLE_CONFIG_SIZE=*/ CIRCUITPY_BLE_CONFIG_SIZE; +/*CIRCUITPY_BLE_CONFIG_START_ADDR=*/ CIRCUITPY_BLE_CONFIG_START_ADDR; +/*CIRCUITPY_BLE_CONFIG_SIZE=*/ CIRCUITPY_BLE_CONFIG_SIZE; -/*CIRCUITPY_INTERNAL_NVM_START_ADDR=*/ CIRCUITPY_INTERNAL_NVM_START_ADDR; -/*CIRCUITPY_INTERNAL_NVM_SIZE=*/ CIRCUITPY_INTERNAL_NVM_SIZE; +/*CIRCUITPY_INTERNAL_NVM_START_ADDR=*/ CIRCUITPY_INTERNAL_NVM_START_ADDR; +/*CIRCUITPY_INTERNAL_NVM_SIZE=*/ CIRCUITPY_INTERNAL_NVM_SIZE; /*CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR=*/ CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR; -/*CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE=*/ CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE; +/*CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE=*/ CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE; -/*BOOTLOADER_START_ADDR=*/ BOOTLOADER_START_ADDR; -/*BOOTLOADER_SIZE=*/ BOOTLOADER_SIZE; +/*BOOTLOADER_START_ADDR=*/ BOOTLOADER_START_ADDR; +/*BOOTLOADER_SIZE=*/ BOOTLOADER_SIZE; -/*BOOTLOADER_SETTINGS_START_ADDR=*/ BOOTLOADER_SETTINGS_START_ADDR; -/*BOOTLOADER_SETTINGS_SIZE=*/ BOOTLOADER_SETTINGS_SIZE; +/*BOOTLOADER_SETTINGS_START_ADDR=*/ BOOTLOADER_SETTINGS_START_ADDR; +/*BOOTLOADER_SETTINGS_SIZE=*/ BOOTLOADER_SETTINGS_SIZE; -/*SOFTDEVICE_RAM_START_ADDR=*/ SOFTDEVICE_RAM_START_ADDR; -/*SOFTDEVICE_RAM_SIZE=*/ SOFTDEVICE_RAM_SIZE; +/*SOFTDEVICE_RAM_START_ADDR=*/ SOFTDEVICE_RAM_START_ADDR; +/*SOFTDEVICE_RAM_SIZE=*/ SOFTDEVICE_RAM_SIZE; -/*SPIM3_BUFFER_RAM_START_ADDR=*/ SPIM3_BUFFER_RAM_START_ADDR; -/*SPIM3_BUFFER_RAM_SIZE=*/ SPIM3_BUFFER_RAM_SIZE; +/*SPIM3_BUFFER_RAM_START_ADDR=*/ SPIM3_BUFFER_RAM_START_ADDR; +/*SPIM3_BUFFER_RAM_SIZE=*/ SPIM3_BUFFER_RAM_SIZE; -/*APP_RAM_START_ADDR=*/ APP_RAM_START_ADDR; -/*APP_RAM_SIZE=*/ APP_RAM_SIZE; +/*APP_RAM_START_ADDR=*/ APP_RAM_START_ADDR; +/*APP_RAM_SIZE=*/ APP_RAM_SIZE; diff --git a/ports/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h index 3ac41a5e4..99effcea2 100644 --- a/ports/nrf/mpconfigport.h +++ b/ports/nrf/mpconfigport.h @@ -39,21 +39,21 @@ #define MICROPY_PY_SYS_STDIO_BUFFER (1) // 24kiB stack -#define CIRCUITPY_DEFAULT_STACK_SIZE (24*1024) +#define CIRCUITPY_DEFAULT_STACK_SIZE (24 * 1024) #ifdef NRF52840 #define MICROPY_PY_SYS_PLATFORM "nRF52840" -#define FLASH_SIZE (1024*1024) // 1MiB -#define RAM_SIZE (256*1024) // 256 KiB +#define FLASH_SIZE (1024 * 1024) // 1MiB +#define RAM_SIZE (256 * 1024) // 256 KiB // Special RAM area for SPIM3 transmit buffer, to work around hardware bug. // See common.template.ld. -#define SPIM3_BUFFER_RAM_SIZE (8*1024) // 8 KiB +#define SPIM3_BUFFER_RAM_SIZE (8 * 1024) // 8 KiB #endif #ifdef NRF52833 #define MICROPY_PY_SYS_PLATFORM "nRF52833" -#define FLASH_SIZE (512*1024) // 512 KiB -#define RAM_SIZE (128*1024) // 128 KiB +#define FLASH_SIZE (512 * 1024) // 512 KiB +#define RAM_SIZE (128 * 1024) // 128 KiB // SPIM3 buffer is not needed on nRF52833: the SPIM3 hw bug is not present. #ifndef SPIM3_BUFFER_RAM_SIZE #define SPIM3_BUFFER_RAM_SIZE (0) @@ -68,7 +68,7 @@ // Definitions that might be overriden by mpconfigboard.h #ifndef CIRCUITPY_INTERNAL_NVM_SIZE -#define CIRCUITPY_INTERNAL_NVM_SIZE (8*1024) +#define CIRCUITPY_INTERNAL_NVM_SIZE (8 * 1024) #endif #ifndef BOARD_HAS_32KHZ_XTAL @@ -78,7 +78,7 @@ #if INTERNAL_FLASH_FILESYSTEM #ifndef CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE -#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (256*1024) +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (256 * 1024) #endif #else #define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0) @@ -105,7 +105,7 @@ // SD_FLASH_SIZE is from nrf_sdm.h #define ISR_START_ADDR (SD_FLASH_START_ADDR + SD_FLASH_SIZE) -#define ISR_SIZE (4*1024) // 4kiB +#define ISR_SIZE (4 * 1024) // 4kiB // Smallest unit of flash that can be erased. #define FLASH_ERASE_SIZE FLASH_PAGE_SIZE @@ -116,12 +116,12 @@ // Bootloader values from https://github.com/adafruit/Adafruit_nRF52_Bootloader/blob/master/src/linker/s140_v6.ld #define BOOTLOADER_START_ADDR (FLASH_SIZE - BOOTLOADER_SIZE - BOOTLOADER_SETTINGS_SIZE - BOOTLOADER_MBR_SIZE) -#define BOOTLOADER_MBR_SIZE (4*1024) // 4kib +#define BOOTLOADER_MBR_SIZE (4 * 1024) // 4kib #ifndef BOOTLOADER_SIZE -#define BOOTLOADER_SIZE (40*1024) // 40kiB +#define BOOTLOADER_SIZE (40 * 1024) // 40kiB #endif #define BOOTLOADER_SETTINGS_START_ADDR (FLASH_SIZE - BOOTLOADER_SETTINGS_SIZE) -#define BOOTLOADER_SETTINGS_SIZE (4*1024) // 4kiB +#define BOOTLOADER_SETTINGS_SIZE (4 * 1024) // 4kiB #define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR (BOOTLOADER_START_ADDR - CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE) @@ -133,7 +133,7 @@ // 32kiB for bonding, etc. #ifndef CIRCUITPY_BLE_CONFIG_SIZE -#define CIRCUITPY_BLE_CONFIG_SIZE (32*1024) +#define CIRCUITPY_BLE_CONFIG_SIZE (32 * 1024) #endif #define CIRCUITPY_BLE_CONFIG_START_ADDR (CIRCUITPY_INTERNAL_NVM_START_ADDR - CIRCUITPY_BLE_CONFIG_SIZE) @@ -182,7 +182,7 @@ // high enough to work and then check the mutation of the value done by sd_ble_enable(). // See common.template.ld. #ifndef SOFTDEVICE_RAM_SIZE -#define SOFTDEVICE_RAM_SIZE (56*1024) +#define SOFTDEVICE_RAM_SIZE (56 * 1024) #endif @@ -192,7 +192,7 @@ #define APP_RAM_START_ADDR (SPIM3_BUFFER_RAM_START_ADDR + SPIM3_BUFFER_RAM_SIZE) #define APP_RAM_SIZE (RAM_START_ADDR + RAM_SIZE - APP_RAM_START_ADDR) -#if SPIM3_BUFFER_RAM_SIZE > 0 && SOFTDEVICE_RAM_SIZE + SPIM3_BUFFER_RAM_SIZE > (64*1024) +#if SPIM3_BUFFER_RAM_SIZE > 0 && SOFTDEVICE_RAM_SIZE + SPIM3_BUFFER_RAM_SIZE > (64 * 1024) #error SPIM3 buffer must be in the first 64kB of RAM. #endif @@ -207,8 +207,8 @@ #define MICROPY_PORT_ROOT_POINTERS \ CIRCUITPY_COMMON_ROOT_POINTERS \ - uint16_t* pixels_pattern_heap; \ - ble_drv_evt_handler_entry_t* ble_drv_evt_handler_entries; \ + uint16_t *pixels_pattern_heap; \ + ble_drv_evt_handler_entry_t *ble_drv_evt_handler_entries; \ #endif // NRF5_MPCONFIGPORT_H__ diff --git a/ports/nrf/mphalport.h b/ports/nrf/mphalport.h index 8bb351401..2b13f82db 100644 --- a/ports/nrf/mphalport.h +++ b/ports/nrf/mphalport.h @@ -37,8 +37,8 @@ extern nrfx_uarte_t serial_instance; -#define mp_hal_ticks_ms() ((mp_uint_t) supervisor_ticks_ms32()) -#define mp_hal_delay_us(us) NRFX_DELAY_US((uint32_t) (us)) +#define mp_hal_ticks_ms() ((mp_uint_t)supervisor_ticks_ms32()) +#define mp_hal_delay_us(us) NRFX_DELAY_US((uint32_t)(us)) bool mp_hal_stdin_any(void); diff --git a/ports/nrf/nrfx_config.h b/ports/nrf/nrfx_config.h index 94812d591..2c31263c5 100644 --- a/ports/nrf/nrfx_config.h +++ b/ports/nrf/nrfx_config.h @@ -32,7 +32,7 @@ #endif #if CIRCUITPY_NRF_NUM_I2C != 0 && CIRCUITPY_NRF_NUM_I2C != 1 && CIRCUITPY_NRF_NUM_I2C != 2 -# error CIRCUITPY_NRF_NUM_I2C must be 0, 1, or 2 +#error CIRCUITPY_NRF_NUM_I2C must be 0, 1, or 2 #endif // Enable SPIM1, SPIM2 and SPIM3 (if available) diff --git a/ports/nrf/nrfx_glue.h b/ports/nrf/nrfx_glue.h index 9f91b72a1..c54f8e2c1 100644 --- a/ports/nrf/nrfx_glue.h +++ b/ports/nrf/nrfx_glue.h @@ -60,7 +60,7 @@ extern "C" { void __assert_func(const char *file, int line, const char *func, const char *expr); -//------------------------------------------------------------------------------ +// ------------------------------------------------------------------------------ /** * @brief Macro for placing a runtime assertion. @@ -85,14 +85,14 @@ void __assert_func(const char *file, int line, const char *func, const char *exp #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) #endif -//------------------------------------------------------------------------------ +// ------------------------------------------------------------------------------ #ifdef SOFTDEVICE_PRESENT #define INTERRUPT_PRIORITY_IS_VALID(pri) ((((pri) > 1) && ((pri) < 4)) || \ - (((pri) > 4) && ((pri) < 8))) + (((pri) > 4) && ((pri) < 8))) #else #define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 8) -#endif //SOFTDEVICE_PRESENT +#endif // SOFTDEVICE_PRESENT /** * @brief Macro for setting the priority of a specific IRQ. @@ -103,9 +103,8 @@ void __assert_func(const char *file, int line, const char *func, const char *exp #define NRFX_IRQ_PRIORITY_SET(irq_number, priority) \ _NRFX_IRQ_PRIORITY_SET(irq_number, priority) static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, - uint8_t priority) -{ - //ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); + uint8_t priority) { + // ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); NVIC_SetPriority(irq_number, priority); } @@ -115,8 +114,7 @@ static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, * @param irq_number IRQ number. */ #define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) -static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) -{ +static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) { NVIC_ClearPendingIRQ(irq_number); NVIC_EnableIRQ(irq_number); } @@ -130,8 +128,7 @@ static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) * @retval false Otherwise. */ #define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) -static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) -{ +static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) { return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); } @@ -141,8 +138,7 @@ static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) * @param irq_number IRQ number. */ #define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) -static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) -{ +static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) { NVIC_DisableIRQ(irq_number); } @@ -152,8 +148,7 @@ static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) * @param irq_number IRQ number. */ #define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) -static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) -{ +static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) { NVIC_SetPendingIRQ(irq_number); } @@ -163,8 +158,7 @@ static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) * @param irq_number IRQ number. */ #define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) -static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) -{ +static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) { NVIC_ClearPendingIRQ(irq_number); } @@ -175,9 +169,8 @@ static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) * @retval false Otherwise. */ #define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) -static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) -{ - return (NVIC_GetPendingIRQ(irq_number) == 1); +static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) { + return NVIC_GetPendingIRQ(irq_number) == 1; } void common_hal_mcu_disable_interrupts(void); @@ -192,7 +185,7 @@ void common_hal_mcu_enable_interrupts(void); */ #define NRFX_CRITICAL_SECTION_EXIT() common_hal_mcu_enable_interrupts() -//------------------------------------------------------------------------------ +// ------------------------------------------------------------------------------ /** * @brief When set to a non-zero value, this macro specifies that @@ -206,7 +199,7 @@ void common_hal_mcu_enable_interrupts(void); #define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) -//------------------------------------------------------------------------------ +// ------------------------------------------------------------------------------ /** * @brief When set to a non-zero value, this macro specifies that the @@ -216,7 +209,7 @@ void common_hal_mcu_enable_interrupts(void); */ #define NRFX_CUSTOM_ERROR_CODES 0 -//------------------------------------------------------------------------------ +// ------------------------------------------------------------------------------ /** * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. diff --git a/ports/nrf/peripherals/nrf/clocks.c b/ports/nrf/peripherals/nrf/clocks.c index 269365cc9..aef956f2d 100644 --- a/ports/nrf/peripherals/nrf/clocks.c +++ b/ports/nrf/peripherals/nrf/clocks.c @@ -30,13 +30,14 @@ void nrf_peripherals_clocks_init(void) { -#if BOARD_HAS_32KHZ_XTAL + #if BOARD_HAS_32KHZ_XTAL NRF_CLOCK->LFCLKSRC = (uint32_t)((CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk); -#else + #else NRF_CLOCK->LFCLKSRC = (uint32_t)((CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk); -#endif + #endif NRF_CLOCK->TASKS_LFCLKSTART = 1UL; // Wait for clocks to start. - while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {} + while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { + } } diff --git a/ports/nrf/peripherals/nrf/nrf52833/power.c b/ports/nrf/peripherals/nrf/nrf52833/power.c index d64c536bb..192a49acc 100644 --- a/ports/nrf/peripherals/nrf/nrf52833/power.c +++ b/ports/nrf/peripherals/nrf/nrf52833/power.c @@ -38,10 +38,12 @@ void nrf_peripherals_power_init(void) { // checking which prevents writes to UICR. // Reported: https://devzone.nordicsemi.com/f/nordic-q-a/57243/nrfx_nvmc-h-api-cannot-write-to-uicr NRF_NVMC->CONFIG = NRF_NVMC_MODE_WRITE; - while (!(NRF_NVMC->READY & NVMC_READY_READY_Msk)) {} + while (!(NRF_NVMC->READY & NVMC_READY_READY_Msk)) { + } NRF_UICR->REGOUT0 = UICR_REGOUT0_VOUT_3V3 << UICR_REGOUT0_VOUT_Pos; __DMB(); - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {} + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { + } NRF_NVMC->CONFIG = NRF_NVMC_MODE_READONLY; // Must reset to enable change. diff --git a/ports/nrf/peripherals/nrf/nrf52840/power.c b/ports/nrf/peripherals/nrf/nrf52840/power.c index d64c536bb..192a49acc 100644 --- a/ports/nrf/peripherals/nrf/nrf52840/power.c +++ b/ports/nrf/peripherals/nrf/nrf52840/power.c @@ -38,10 +38,12 @@ void nrf_peripherals_power_init(void) { // checking which prevents writes to UICR. // Reported: https://devzone.nordicsemi.com/f/nordic-q-a/57243/nrfx_nvmc-h-api-cannot-write-to-uicr NRF_NVMC->CONFIG = NRF_NVMC_MODE_WRITE; - while (!(NRF_NVMC->READY & NVMC_READY_READY_Msk)) {} + while (!(NRF_NVMC->READY & NVMC_READY_READY_Msk)) { + } NRF_UICR->REGOUT0 = UICR_REGOUT0_VOUT_3V3 << UICR_REGOUT0_VOUT_Pos; __DMB(); - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {} + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { + } NRF_NVMC->CONFIG = NRF_NVMC_MODE_READONLY; // Must reset to enable change. diff --git a/ports/nrf/peripherals/nrf/nvm.c b/ports/nrf/peripherals/nrf/nvm.c index ce47d73c7..06a642922 100644 --- a/ports/nrf/peripherals/nrf/nvm.c +++ b/ports/nrf/peripherals/nrf/nvm.c @@ -40,9 +40,10 @@ STATIC bool sd_is_enabled(void) { uint8_t sd_en = 0; - if (__get_PRIMASK()) + if (__get_PRIMASK()) { return false; - (void) sd_softdevice_is_enabled(&sd_en); + } + (void)sd_softdevice_is_enabled(&sd_en); return sd_en; } @@ -74,7 +75,7 @@ bool sd_flash_page_erase_sync(uint32_t page_number) { return true; } -bool sd_flash_write_sync(uint32_t *dest_words, uint32_t* src_words, uint32_t num_words) { +bool sd_flash_write_sync(uint32_t *dest_words, uint32_t *src_words, uint32_t num_words) { sd_flash_operation_start(); if (sd_flash_write(dest_words, src_words, num_words) != NRF_SUCCESS) { return false; @@ -95,12 +96,29 @@ bool sd_flash_write_sync(uint32_t *dest_words, uint32_t* src_words, uint32_t num bool nrf_nvm_safe_flash_page_write(uint32_t page_addr, uint8_t *data) { #ifdef BLUETOOTH_SD - if (sd_is_enabled()) { - uint32_t err_code; - sd_flash_operation_status_t status; + if (sd_is_enabled()) { + uint32_t err_code; + sd_flash_operation_status_t status; + + sd_flash_operation_start(); + err_code = sd_flash_page_erase(page_addr / FLASH_PAGE_SIZE); + if (err_code != NRF_SUCCESS) { + return false; + } + status = sd_flash_operation_wait_until_done(); + if (status == SD_FLASH_OPERATION_ERROR) { + return false; + } + // Divide a full page into parts, because writing a full page causes an assertion failure. + // See https://devzone.nordicsemi.com/f/nordic-q-a/40088/sd_flash_write-cause-nrf_fault_id_sd_assert/ + const size_t BLOCK_PARTS = 2; + size_t words_to_write = FLASH_PAGE_SIZE / sizeof(uint32_t) / BLOCK_PARTS; + for (size_t i = 0; i < BLOCK_PARTS; i++) { sd_flash_operation_start(); - err_code = sd_flash_page_erase(page_addr / FLASH_PAGE_SIZE); + err_code = sd_flash_write(((uint32_t *)page_addr) + i * words_to_write, + (uint32_t *)data + i * words_to_write, + words_to_write); if (err_code != NRF_SUCCESS) { return false; } @@ -108,27 +126,10 @@ bool nrf_nvm_safe_flash_page_write(uint32_t page_addr, uint8_t *data) { if (status == SD_FLASH_OPERATION_ERROR) { return false; } - - // Divide a full page into parts, because writing a full page causes an assertion failure. - // See https://devzone.nordicsemi.com/f/nordic-q-a/40088/sd_flash_write-cause-nrf_fault_id_sd_assert/ - const size_t BLOCK_PARTS = 2; - size_t words_to_write = FLASH_PAGE_SIZE / sizeof(uint32_t) / BLOCK_PARTS; - for (size_t i = 0; i < BLOCK_PARTS; i++) { - sd_flash_operation_start(); - err_code = sd_flash_write(((uint32_t *)page_addr) + i * words_to_write, - (uint32_t *)data + i * words_to_write, - words_to_write); - if (err_code != NRF_SUCCESS) { - return false; - } - status = sd_flash_operation_wait_until_done(); - if (status == SD_FLASH_OPERATION_ERROR) { - return false; - } - } - - return true; } + + return true; + } #endif nrfx_nvmc_page_erase(page_addr); diff --git a/ports/nrf/peripherals/nrf/nvm.h b/ports/nrf/peripherals/nrf/nvm.h index 9e144d802..da8080f0a 100644 --- a/ports/nrf/peripherals/nrf/nvm.h +++ b/ports/nrf/peripherals/nrf/nvm.h @@ -29,7 +29,7 @@ #if BLUETOOTH_SD bool sd_flash_page_erase_sync(uint32_t page_number); -bool sd_flash_write_sync(uint32_t *dest_words, uint32_t* src_words, uint32_t num_words); +bool sd_flash_write_sync(uint32_t *dest_words, uint32_t *src_words, uint32_t num_words); #endif bool nrf_nvm_safe_flash_page_write(uint32_t page_addr, uint8_t *data); diff --git a/ports/nrf/peripherals/nrf/pins.h b/ports/nrf/peripherals/nrf/pins.h index efdc8892a..e3f947ca2 100644 --- a/ports/nrf/peripherals/nrf/pins.h +++ b/ports/nrf/peripherals/nrf/pins.h @@ -47,11 +47,11 @@ extern const mp_obj_type_t mcu_pin_type; // Used in device-specific pins.c #define PIN(p_name, p_port, p_pin, p_adc_channel) \ -{ \ - { &mcu_pin_type }, \ - .number = NRF_GPIO_PIN_MAP(p_port, p_pin), \ - .adc_channel = (p_adc_channel), \ -} + { \ + { &mcu_pin_type }, \ + .number = NRF_GPIO_PIN_MAP(p_port, p_pin), \ + .adc_channel = (p_adc_channel), \ + } // Use illegal pin value to mark unassigned pins. #define NO_PIN 0xff diff --git a/ports/nrf/peripherals/nrf/timers.c b/ports/nrf/peripherals/nrf/timers.c index fd814968d..f3a16b7e1 100644 --- a/ports/nrf/peripherals/nrf/timers.c +++ b/ports/nrf/peripherals/nrf/timers.c @@ -36,29 +36,29 @@ #include "py/runtime.h" STATIC nrfx_timer_t nrfx_timers[] = { -#if NRFX_CHECK(NRFX_TIMER0_ENABLED) + #if NRFX_CHECK(NRFX_TIMER0_ENABLED) #error NRFX_TIMER0_ENABLED should not be on: TIMER0 is used by the SoftDevice NRFX_TIMER_INSTANCE(0), -#endif -#if NRFX_CHECK(NRFX_TIMER1_ENABLED) + #endif + #if NRFX_CHECK(NRFX_TIMER1_ENABLED) NRFX_TIMER_INSTANCE(1), -#endif -#if NRFX_CHECK(NRFX_TIMER2_ENABLED) + #endif + #if NRFX_CHECK(NRFX_TIMER2_ENABLED) NRFX_TIMER_INSTANCE(2), -#endif -#if NRFX_CHECK(NRFX_TIMER3_ENABLED) + #endif + #if NRFX_CHECK(NRFX_TIMER3_ENABLED) NRFX_TIMER_INSTANCE(3), -#endif -#if NRFX_CHECK(NRFX_TIMER4_ENABLED) + #endif + #if NRFX_CHECK(NRFX_TIMER4_ENABLED) NRFX_TIMER_INSTANCE(4), -#endif + #endif }; static bool nrfx_timer_allocated[ARRAY_SIZE(nrfx_timers)]; static bool nrfx_timer_never_reset[ARRAY_SIZE(nrfx_timers)]; void timers_reset(void) { - for (size_t i = 0; i < ARRAY_SIZE(nrfx_timers); i ++) { + for (size_t i = 0; i < ARRAY_SIZE(nrfx_timers); i++) { if (nrfx_timer_never_reset[i]) { continue; } @@ -67,18 +67,18 @@ void timers_reset(void) { } } -void nrf_peripherals_timer_never_reset(nrfx_timer_t* timer) { +void nrf_peripherals_timer_never_reset(nrfx_timer_t *timer) { int idx = nrf_peripherals_timer_idx_from_timer(timer); nrfx_timer_never_reset[idx] = true; } -void nrf_peripherals_timer_reset_ok(nrfx_timer_t* timer) { +void nrf_peripherals_timer_reset_ok(nrfx_timer_t *timer) { int idx = nrf_peripherals_timer_idx_from_timer(timer); nrfx_timer_never_reset[idx] = false; } -nrfx_timer_t* nrf_peripherals_timer_from_reg(NRF_TIMER_Type* ptr) { - for (size_t i = 0; i < ARRAY_SIZE(nrfx_timers); i ++) { +nrfx_timer_t *nrf_peripherals_timer_from_reg(NRF_TIMER_Type *ptr) { + for (size_t i = 0; i < ARRAY_SIZE(nrfx_timers); i++) { if (nrfx_timers[i].p_reg == ptr) { return &nrfx_timers[i]; } @@ -86,8 +86,8 @@ nrfx_timer_t* nrf_peripherals_timer_from_reg(NRF_TIMER_Type* ptr) { return NULL; } -size_t nrf_peripherals_timer_idx_from_timer(nrfx_timer_t* ptr) { - for (size_t i = 0; i < ARRAY_SIZE(nrfx_timers); i ++) { +size_t nrf_peripherals_timer_idx_from_timer(nrfx_timer_t *ptr) { + for (size_t i = 0; i < ARRAY_SIZE(nrfx_timers); i++) { if (&nrfx_timers[i] == ptr) { return i; } @@ -99,8 +99,8 @@ size_t nrf_peripherals_timer_idx_from_timer(nrfx_timer_t* ptr) { // Returns a free nrfx_timer instance, and marks it as allocated. // The caller should init as with the desired config. // Returns NULL if no timer is available. -nrfx_timer_t* nrf_peripherals_allocate_timer(void) { - for (size_t i = 0; i < ARRAY_SIZE(nrfx_timers); i ++) { +nrfx_timer_t *nrf_peripherals_allocate_timer(void) { + for (size_t i = 0; i < ARRAY_SIZE(nrfx_timers); i++) { if (!nrfx_timer_allocated[i]) { nrfx_timer_allocated[i] = true; return &nrfx_timers[i]; @@ -109,8 +109,8 @@ nrfx_timer_t* nrf_peripherals_allocate_timer(void) { return NULL; } -nrfx_timer_t* nrf_peripherals_allocate_timer_or_throw(void) { - nrfx_timer_t* result = nrf_peripherals_allocate_timer(); +nrfx_timer_t *nrf_peripherals_allocate_timer_or_throw(void) { + nrfx_timer_t *result = nrf_peripherals_allocate_timer(); if (!result) { mp_raise_RuntimeError(translate("All timers in use")); } @@ -118,7 +118,7 @@ nrfx_timer_t* nrf_peripherals_allocate_timer_or_throw(void) { } // Free a timer, which may or may not have been initialized. -void nrf_peripherals_free_timer(nrfx_timer_t* timer) { +void nrf_peripherals_free_timer(nrfx_timer_t *timer) { size_t idx = nrf_peripherals_timer_idx_from_timer(timer); if (idx != ~(size_t)0) { nrfx_timer_allocated[idx] = false; diff --git a/ports/nrf/peripherals/nrf/timers.h b/ports/nrf/peripherals/nrf/timers.h index cf96c6273..0fb529d73 100644 --- a/ports/nrf/peripherals/nrf/timers.h +++ b/ports/nrf/peripherals/nrf/timers.h @@ -28,10 +28,10 @@ #include "nrfx_timer.h" void timers_reset(void); -nrfx_timer_t* nrf_peripherals_allocate_timer(void); -nrfx_timer_t* nrf_peripherals_allocate_timer_or_throw(void); -void nrf_peripherals_free_timer(nrfx_timer_t* timer); -void nrf_peripherals_timer_never_reset(nrfx_timer_t* timer); -void nrf_peripherals_timer_reset_ok(nrfx_timer_t* timer); -nrfx_timer_t* nrf_peripherals_timer_from_reg(NRF_TIMER_Type* ptr); -size_t nrf_peripherals_timer_idx_from_timer(nrfx_timer_t* ptr); +nrfx_timer_t *nrf_peripherals_allocate_timer(void); +nrfx_timer_t *nrf_peripherals_allocate_timer_or_throw(void); +void nrf_peripherals_free_timer(nrfx_timer_t *timer); +void nrf_peripherals_timer_never_reset(nrfx_timer_t *timer); +void nrf_peripherals_timer_reset_ok(nrfx_timer_t *timer); +nrfx_timer_t *nrf_peripherals_timer_from_reg(NRF_TIMER_Type *ptr); +size_t nrf_peripherals_timer_idx_from_timer(nrfx_timer_t *ptr); diff --git a/ports/nrf/sd_mutex.c b/ports/nrf/sd_mutex.c index b3162e6af..2ae490288 100644 --- a/ports/nrf/sd_mutex.c +++ b/ports/nrf/sd_mutex.c @@ -28,25 +28,25 @@ #include "py/runtime.h" #include "nrf_soc.h" -void sd_mutex_acquire_check(nrf_mutex_t* p_mutex) { +void sd_mutex_acquire_check(nrf_mutex_t *p_mutex) { uint32_t err_code = sd_mutex_acquire(p_mutex); if (err_code != NRF_SUCCESS) { mp_raise_OSError_msg_varg(translate("Failed to acquire mutex, err 0x%04x"), err_code); } } -void sd_mutex_acquire_wait(nrf_mutex_t* p_mutex) { +void sd_mutex_acquire_wait(nrf_mutex_t *p_mutex) { while (sd_mutex_acquire(p_mutex) == NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN) { RUN_BACKGROUND_TASKS; } } -void sd_mutex_acquire_wait_no_vm(nrf_mutex_t* p_mutex) { +void sd_mutex_acquire_wait_no_vm(nrf_mutex_t *p_mutex) { while (sd_mutex_acquire(p_mutex) == NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN) { } } -void sd_mutex_release_check(nrf_mutex_t* p_mutex) { +void sd_mutex_release_check(nrf_mutex_t *p_mutex) { uint32_t err_code = sd_mutex_release(p_mutex); if (err_code != NRF_SUCCESS) { mp_raise_OSError_msg_varg(translate("Failed to release mutex, err 0x%04x"), err_code); diff --git a/ports/nrf/sd_mutex.h b/ports/nrf/sd_mutex.h index ca4691720..2999dc774 100644 --- a/ports/nrf/sd_mutex.h +++ b/ports/nrf/sd_mutex.h @@ -32,15 +32,15 @@ // Helpers for common usage of nrf_mutex. // Try to acquire a mutex right now. Raise exception if we can't get it. -void sd_mutex_acquire_check(nrf_mutex_t* p_mutex); +void sd_mutex_acquire_check(nrf_mutex_t *p_mutex); // Wait for a mutex to become available. Run VM background tasks while waiting. -void sd_mutex_acquire_wait(nrf_mutex_t* p_mutex); +void sd_mutex_acquire_wait(nrf_mutex_t *p_mutex); // Wait for a mutex to become available.. Block VM while waiting. -void sd_mutex_acquire_wait_no_vm(nrf_mutex_t* p_mutex); +void sd_mutex_acquire_wait_no_vm(nrf_mutex_t *p_mutex); // Release a mutex, and raise exception on error. -void sd_mutex_release_check(nrf_mutex_t* p_mutex); +void sd_mutex_release_check(nrf_mutex_t *p_mutex); #endif // MICROPY_INCLUDED_NRF_SD_MUTEX_H diff --git a/ports/nrf/supervisor/bluetooth.c b/ports/nrf/supervisor/bluetooth.c index 8d89d6272..5ce737f6a 100644 --- a/ports/nrf/supervisor/bluetooth.c +++ b/ports/nrf/supervisor/bluetooth.c @@ -29,7 +29,7 @@ // This happens in an interrupt so we need to be quick. bool supervisor_bluetooth_hook(ble_evt_t *ble_evt) { -#if CIRCUITPY_BLE_FILE_SERVICE + #if CIRCUITPY_BLE_FILE_SERVICE // Catch writes to filename or contents. Length is read-only. bool done = false; @@ -49,12 +49,12 @@ bool supervisor_bluetooth_hook(ble_evt_t *ble_evt) { // Event handle must match the handle for my characteristic. if (evt_write->handle == supervisor_ble_contents_characteristic.handle) { // Handle events - //write_to_ringbuf(self, evt_write->data, evt_write->len); + // write_to_ringbuf(self, evt_write->data, evt_write->len); // First packet includes a uint16_t le for length at the start. - uint16_t current_length = ((uint16_t*) current_command)[0]; - memcpy(((uint8_t*) current_command) + current_offset, evt_write->data, evt_write->len); + uint16_t current_length = ((uint16_t *)current_command)[0]; + memcpy(((uint8_t *)current_command) + current_offset, evt_write->data, evt_write->len); current_offset += evt_write->len; - current_length = ((uint16_t*) current_command)[0]; + current_length = ((uint16_t *)current_command)[0]; if (current_offset == current_length) { run_ble_background = true; done = true; @@ -75,7 +75,7 @@ bool supervisor_bluetooth_hook(ble_evt_t *ble_evt) { break; } return done; -#else + #else return false; -#endif + #endif } diff --git a/ports/nrf/supervisor/internal_flash.c b/ports/nrf/supervisor/internal_flash.c index 93de0b2c4..cce48a4c3 100644 --- a/ports/nrf/supervisor/internal_flash.c +++ b/ports/nrf/supervisor/internal_flash.c @@ -45,7 +45,7 @@ #define NO_CACHE 0xffffffff -uint8_t _flash_cache[FLASH_PAGE_SIZE] __attribute__((aligned(4))); +uint8_t _flash_cache[FLASH_PAGE_SIZE] __attribute__((aligned(4))); uint32_t _flash_page_addr = NO_CACHE; @@ -64,11 +64,13 @@ uint32_t supervisor_flash_get_block_size(void) { } uint32_t supervisor_flash_get_block_count(void) { - return CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE ; + return CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE; } void port_internal_flash_flush(void) { - if (_flash_page_addr == NO_CACHE) return; + if (_flash_page_addr == NO_CACHE) { + return; + } // Skip if data is the same if (memcmp(_flash_cache, (void *)_flash_page_addr, FLASH_PAGE_SIZE) != 0) { @@ -83,13 +85,13 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n supervisor_flash_flush(); uint32_t src = lba2addr(block); - memcpy(dest, (uint8_t*) src, FILESYSTEM_BLOCK_SIZE*num_blocks); + memcpy(dest, (uint8_t *)src, FILESYSTEM_BLOCK_SIZE * num_blocks); return 0; // success } mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32_t num_blocks) { while (num_blocks) { - uint32_t const addr = lba2addr(lba); + uint32_t const addr = lba2addr(lba); uint32_t const page_addr = addr & ~(FLASH_PAGE_SIZE - 1); uint32_t count = 8 - (lba % 8); // up to page boundary @@ -109,8 +111,8 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 memcpy(_flash_cache + (addr & (FLASH_PAGE_SIZE - 1)), src, count * FILESYSTEM_BLOCK_SIZE); // adjust for next run - lba += count; - src += count * FILESYSTEM_BLOCK_SIZE; + lba += count; + src += count * FILESYSTEM_BLOCK_SIZE; num_blocks -= count; } diff --git a/ports/nrf/supervisor/port.c b/ports/nrf/supervisor/port.c index 78bb20ce6..9a2acd5ca 100644 --- a/ports/nrf/supervisor/port.c +++ b/ports/nrf/supervisor/port.c @@ -94,7 +94,7 @@ void rtc_handler(nrfx_rtc_int_type_t int_type) { if (int_type == NRFX_RTC_INT_OVERFLOW) { // Our RTC is 24 bits and we're clocking it at 32.768khz which is 32 (2 ** 5) subticks per // tick. - overflow_tracker.overflowed_ticks += (1L<< (24 - 5)); + overflow_tracker.overflowed_ticks += (1L << (24 - 5)); } else if (int_type == NRFX_RTC_INT_TICK && nrfx_rtc_counter_get(&rtc_instance) % 32 == 0) { // Do things common to all ports when the tick occurs supervisor_tick(); @@ -145,13 +145,13 @@ safe_mode_t port_init(void) { // Configure millisecond timer initialization. tick_init(); -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC common_hal_rtc_init(); -#endif + #endif -#if CIRCUITPY_ANALOGIO + #if CIRCUITPY_ANALOGIO analogin_init(); -#endif + #endif // If the board was reset by the WatchDogTimer, we may // need to boot into safe mode. Reset the RESETREAS bit @@ -172,51 +172,51 @@ safe_mode_t port_init(void) { } void reset_port(void) { -#ifdef CIRCUITPY_GAMEPAD_TICKS + #ifdef CIRCUITPY_GAMEPAD_TICKS gamepad_reset(); -#endif + #endif -#if CIRCUITPY_BUSIO + #if CIRCUITPY_BUSIO i2c_reset(); spi_reset(); uart_reset(); -#endif + #endif -#if CIRCUITPY_NEOPIXEL_WRITE + #if CIRCUITPY_NEOPIXEL_WRITE neopixel_write_reset(); -#endif + #endif -#if CIRCUITPY_AUDIOBUSIO + #if CIRCUITPY_AUDIOBUSIO i2s_reset(); -#endif + #endif -#if CIRCUITPY_AUDIOPWMIO + #if CIRCUITPY_AUDIOPWMIO audiopwmout_reset(); -#endif + #endif -#if CIRCUITPY_PULSEIO + #if CIRCUITPY_PULSEIO pulseout_reset(); pulsein_reset(); -#endif + #endif -#if CIRCUITPY_PWMIO + #if CIRCUITPY_PWMIO pwmout_reset(); -#endif + #endif -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC rtc_reset(); -#endif + #endif timers_reset(); -#if CIRCUITPY_BLEIO + #if CIRCUITPY_BLEIO bleio_reset(); -#endif + #endif -#if CIRCUITPY_WATCHDOG + #if CIRCUITPY_WATCHDOG watchdog_reset(); -#endif + #endif reset_all_pins(); } @@ -273,7 +273,7 @@ uint32_t port_get_saved_word(void) { return _saved_word; } -uint64_t port_get_raw_ticks(uint8_t* subticks) { +uint64_t port_get_raw_ticks(uint8_t *subticks) { common_hal_mcu_disable_interrupts(); uint32_t rtc = nrfx_rtc_counter_get(&rtc_instance); uint64_t overflow_count = overflow_tracker.overflowed_ticks; @@ -308,14 +308,14 @@ void port_interrupt_after_ticks(uint32_t ticks) { } void port_idle_until_interrupt(void) { -#if defined(MICROPY_QSPI_CS) + #if defined(MICROPY_QSPI_CS) qspi_disable(); -#endif + #endif // Clear the FPU interrupt because it can prevent us from sleeping. if (NVIC_GetPendingIRQ(FPU_IRQn)) { - __set_FPSCR(__get_FPSCR() & ~(0x9f)); - (void) __get_FPSCR(); + __set_FPSCR(__get_FPSCR() & ~(0x9f)); + (void)__get_FPSCR(); NVIC_ClearPendingIRQ(FPU_IRQn); } uint8_t sd_enabled; @@ -352,6 +352,6 @@ void port_idle_until_interrupt(void) { void HardFault_Handler(void) { reset_into_safe_mode(HARD_CRASH); while (true) { - asm("nop;"); + asm ("nop;"); } } diff --git a/ports/nrf/supervisor/qspi_flash.c b/ports/nrf/supervisor/qspi_flash.c index 7ca27d56c..1386af7c4 100644 --- a/ports/nrf/supervisor/qspi_flash.c +++ b/ports/nrf/supervisor/qspi_flash.c @@ -39,8 +39,7 @@ #include "supervisor/shared/external_flash/qspi_flash.h" // When USB is disconnected, disable QSPI in sleep mode to save energy -void qspi_disable(void) -{ +void qspi_disable(void) { // If VBUS is detected, no need to disable QSPI if (NRF_QSPI->ENABLE && !(NRF_POWER->USBREGSTATUS & POWER_USBREGSTATUS_VBUSDETECT_Msk)) { // Keep CS high when QSPI is diabled @@ -54,8 +53,7 @@ void qspi_disable(void) } } -void qspi_enable(void) -{ +void qspi_enable(void) { if (NRF_QSPI->ENABLE) { return; } @@ -87,7 +85,7 @@ bool spi_flash_command(uint8_t command) { return nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL) == NRFX_SUCCESS; } -bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length) { +bool spi_flash_read_command(uint8_t command, uint8_t *response, uint32_t length) { qspi_enable(); nrf_qspi_cinstr_conf_t cinstr_cfg = { .opcode = command, @@ -101,7 +99,7 @@ bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length) } -bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) { +bool spi_flash_write_command(uint8_t command, uint8_t *data, uint32_t length) { qspi_enable(); nrf_qspi_cinstr_conf_t cinstr_cfg = { .opcode = command, @@ -122,7 +120,7 @@ bool spi_flash_sector_command(uint8_t command, uint32_t address) { return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, address) == NRFX_SUCCESS; } -bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) { +bool spi_flash_write_data(uint32_t address, uint8_t *data, uint32_t length) { qspi_enable(); // TODO: In theory, this also needs to handle unaligned data and // non-multiple-of-4 length. (in practice, I don't think the fat layer @@ -130,17 +128,17 @@ bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) { return nrfx_qspi_write(data, length, address) == NRFX_SUCCESS; } -bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) { +bool spi_flash_read_data(uint32_t address, uint8_t *data, uint32_t length) { qspi_enable(); int misaligned = ((intptr_t)data) & 3; // If the data is misaligned, we need to read 4 bytes // into an aligned buffer, and then copy 1, 2, or 3 bytes from the aligned // buffer to data. - if(misaligned) { + if (misaligned) { int sz = 4 - misaligned; __attribute__((aligned(4))) uint8_t buf[4]; - if(nrfx_qspi_read(buf, 4, address) != NRFX_SUCCESS) { + if (nrfx_qspi_read(buf, 4, address) != NRFX_SUCCESS) { return false; } memcpy(data, buf, sz); @@ -153,7 +151,7 @@ bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) { // signal an error if sz is not a multiple of 4. Read (directly into data) // all but the last 1, 2, or 3 bytes depending on the (remaining) length. uint32_t sz = length & ~(uint32_t)3; - if(nrfx_qspi_read(data, sz, address) != NRFX_SUCCESS) { + if (nrfx_qspi_read(data, sz, address) != NRFX_SUCCESS) { return false; } data += sz; @@ -162,9 +160,9 @@ bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) { // Now, if we have any bytes left over, we must do a final read of 4 // bytes and copy 1, 2, or 3 bytes to data. - if(length) { + if (length) { __attribute__((aligned(4))) uint8_t buf[4]; - if(nrfx_qspi_read(buf, 4, address) != NRFX_SUCCESS) { + if (nrfx_qspi_read(buf, 4, address) != NRFX_SUCCESS) { return false; } memcpy(data, buf, length); @@ -201,23 +199,23 @@ void spi_flash_init(void) { .irq_priority = 7, }; -#if defined(EXTERNAL_FLASH_QSPI_DUAL) + #if defined(EXTERNAL_FLASH_QSPI_DUAL) qspi_cfg.pins.io1_pin = MICROPY_QSPI_DATA1; qspi_cfg.prot_if.readoc = NRF_QSPI_READOC_READ2O; qspi_cfg.prot_if.writeoc = NRF_QSPI_WRITEOC_PP2O; -#else + #else qspi_cfg.pins.io1_pin = MICROPY_QSPI_DATA1; qspi_cfg.pins.io2_pin = MICROPY_QSPI_DATA2; qspi_cfg.pins.io3_pin = MICROPY_QSPI_DATA3; qspi_cfg.prot_if.readoc = NRF_QSPI_READOC_READ4IO; qspi_cfg.prot_if.writeoc = NRF_QSPI_WRITEOC_PP4O; -#endif + #endif // No callback for blocking API nrfx_qspi_init(&qspi_cfg, NULL, NULL); } -void spi_flash_init_device(const external_flash_device* device) { +void spi_flash_init_device(const external_flash_device *device) { check_quad_enable(device); // Switch to single output line if the device doesn't support quad programs. @@ -236,5 +234,5 @@ void spi_flash_init_device(const external_flash_device* device) { sckfreq += 1; } NRF_QSPI->IFCONFIG1 &= ~QSPI_IFCONFIG1_SCKFREQ_Msk; - NRF_QSPI->IFCONFIG1 |= sckfreq << QSPI_IFCONFIG1_SCKFREQ_Pos; + NRF_QSPI->IFCONFIG1 |= sckfreq << QSPI_IFCONFIG1_SCKFREQ_Pos; } diff --git a/ports/nrf/supervisor/serial.c b/ports/nrf/supervisor/serial.c index 2c2c0116f..10bdb2819 100644 --- a/ports/nrf/supervisor/serial.c +++ b/ports/nrf/supervisor/serial.c @@ -47,7 +47,7 @@ bool serial_connected(void) { } char serial_read(void) { - return (char) ble_uart_rx_chr(); + return (char)ble_uart_rx_chr(); } bool serial_bytes_available(void) { @@ -101,7 +101,7 @@ bool serial_bytes_available(void) { return nrf_uarte_event_check(serial_instance.p_reg, NRF_UARTE_EVENT_RXDRDY); } -void serial_write(const char* text) { +void serial_write(const char *text) { serial_write_substring(text, strlen(text)); } @@ -111,15 +111,15 @@ void serial_write_substring(const char *text, uint32_t len) { } // EasyDMA can only access SRAM - uint8_t * tx_buf = (uint8_t*) text; - if ( !nrfx_is_in_ram(text) ) { - tx_buf = (uint8_t *) m_malloc(len, false); + uint8_t *tx_buf = (uint8_t *)text; + if (!nrfx_is_in_ram(text)) { + tx_buf = (uint8_t *)m_malloc(len, false); memcpy(tx_buf, text, len); } nrfx_uarte_tx(&serial_instance, tx_buf, len); - if ( !nrfx_is_in_ram(text) ) { + if (!nrfx_is_in_ram(text)) { m_free(tx_buf); } } diff --git a/ports/nrf/supervisor/usb.c b/ports/nrf/supervisor/usb.c index 771e86ce0..3ca9b8365 100644 --- a/ports/nrf/supervisor/usb.c +++ b/ports/nrf/supervisor/usb.c @@ -53,25 +53,25 @@ void init_usb_hardware(void) { static bool first_call = true; uint32_t usb_reg; -#ifdef SOFTDEVICE_PRESENT + #ifdef SOFTDEVICE_PRESENT uint8_t sd_en = false; - (void) sd_softdevice_is_enabled(&sd_en); + (void)sd_softdevice_is_enabled(&sd_en); - if ( sd_en ) { + if (sd_en) { sd_power_usbdetected_enable(true); sd_power_usbpwrrdy_enable(true); sd_power_usbremoved_enable(true); sd_power_usbregstatus_get(&usb_reg); - }else -#endif + } else + #endif { // Power module init const nrfx_power_config_t pwr_cfg = { 0 }; nrfx_power_init(&pwr_cfg); // Register tusb function as USB power handler - const nrfx_power_usbevt_config_t config = { .handler = (nrfx_power_usb_event_handler_t) tusb_hal_nrf_power_event }; + const nrfx_power_usbevt_config_t config = { .handler = (nrfx_power_usb_event_handler_t)tusb_hal_nrf_power_event }; nrfx_power_usbevt_init(&config); nrfx_power_usbevt_enable(); @@ -79,13 +79,13 @@ void init_usb_hardware(void) { usb_reg = NRF_POWER->USBREGSTATUS; } - if ( first_call ) { + if (first_call) { first_call = false; - if ( usb_reg & POWER_USBREGSTATUS_VBUSDETECT_Msk ) { + if (usb_reg & POWER_USBREGSTATUS_VBUSDETECT_Msk) { tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_DETECTED); } - if ( usb_reg & POWER_USBREGSTATUS_OUTPUTRDY_Msk ) { + if (usb_reg & POWER_USBREGSTATUS_OUTPUTRDY_Msk) { tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_READY); } } diff --git a/ports/raspberrypi/audio_dma.c b/ports/raspberrypi/audio_dma.c index ccf08b1b4..28a80a770 100644 --- a/ports/raspberrypi/audio_dma.c +++ b/ports/raspberrypi/audio_dma.c @@ -49,8 +49,8 @@ void audio_dma_reset(void) { } } -void audio_dma_convert_signed(audio_dma_t* dma, uint8_t* buffer, uint32_t buffer_length, - uint8_t** output_buffer, uint32_t* output_buffer_length) { +void audio_dma_convert_signed(audio_dma_t *dma, uint8_t *buffer, uint32_t buffer_length, + uint8_t **output_buffer, uint32_t *output_buffer_length) { if (dma->first_buffer_free) { *output_buffer = dma->first_buffer; } else { @@ -59,9 +59,9 @@ void audio_dma_convert_signed(audio_dma_t* dma, uint8_t* buffer, uint32_t buffer #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-align" if (dma->signed_to_unsigned || - dma->unsigned_to_signed || - dma->sample_spacing > 1 || - (dma->sample_resolution != dma->output_resolution)) { + dma->unsigned_to_signed || + dma->sample_spacing > 1 || + (dma->sample_resolution != dma->output_resolution)) { *output_buffer_length = buffer_length / dma->sample_spacing; uint32_t out_i = 0; if (dma->sample_resolution <= 8 && dma->output_resolution > 8) { @@ -69,22 +69,22 @@ void audio_dma_convert_signed(audio_dma_t* dma, uint8_t* buffer, uint32_t buffer for (uint32_t i = 0; i < buffer_length; i += dma->sample_spacing) { if (dma->signed_to_unsigned) { - ((uint16_t*) *output_buffer)[out_i] = ((uint16_t) ((int8_t*) buffer)[i] + 0x80) << shift; + ((uint16_t *)*output_buffer)[out_i] = ((uint16_t)((int8_t *)buffer)[i] + 0x80) << shift; } else if (dma->unsigned_to_signed) { - ((int16_t*) *output_buffer)[out_i] = ((int16_t) ((uint8_t*) buffer)[i] - 0x80) << shift; + ((int16_t *)*output_buffer)[out_i] = ((int16_t)((uint8_t *)buffer)[i] - 0x80) << shift; } else { - ((uint16_t*) *output_buffer)[out_i] = ((uint16_t) ((uint8_t*) buffer)[i]) << shift; + ((uint16_t *)*output_buffer)[out_i] = ((uint16_t)((uint8_t *)buffer)[i]) << shift; } out_i += 1; } } else if (dma->sample_resolution <= 8 && dma->output_resolution <= 8) { for (uint32_t i = 0; i < buffer_length; i += dma->sample_spacing) { if (dma->signed_to_unsigned) { - ((uint8_t*) *output_buffer)[out_i] = ((int8_t*) buffer)[i] + 0x80; + ((uint8_t *)*output_buffer)[out_i] = ((int8_t *)buffer)[i] + 0x80; } else if (dma->unsigned_to_signed) { - ((int8_t*) *output_buffer)[out_i] = ((uint8_t*) buffer)[i] - 0x80; + ((int8_t *)*output_buffer)[out_i] = ((uint8_t *)buffer)[i] - 0x80; } else { - ((uint8_t*) *output_buffer)[out_i] = ((uint8_t*) buffer)[i]; + ((uint8_t *)*output_buffer)[out_i] = ((uint8_t *)buffer)[i]; } out_i += 1; } @@ -92,17 +92,17 @@ void audio_dma_convert_signed(audio_dma_t* dma, uint8_t* buffer, uint32_t buffer size_t shift = 16 - dma->output_resolution; for (uint32_t i = 0; i < buffer_length / 2; i += dma->sample_spacing) { if (dma->signed_to_unsigned) { - ((uint16_t*) *output_buffer)[out_i] = ((int16_t*) buffer)[i] + 0x8000; - } else if (dma->unsigned_to_signed) { - ((int16_t*) *output_buffer)[out_i] = ((uint16_t*) buffer)[i] - 0x8000; + ((uint16_t *)*output_buffer)[out_i] = ((int16_t *)buffer)[i] + 0x8000; + } else if (dma->unsigned_to_signed) { + ((int16_t *)*output_buffer)[out_i] = ((uint16_t *)buffer)[i] - 0x8000; } else { - ((uint16_t*) *output_buffer)[out_i] = ((uint16_t*) buffer)[i]; + ((uint16_t *)*output_buffer)[out_i] = ((uint16_t *)buffer)[i]; } if (dma->output_resolution < 16) { if (dma->output_signed) { - ((int16_t*) *output_buffer)[out_i] = ((int16_t*) *output_buffer)[out_i] >> shift; + ((int16_t *)*output_buffer)[out_i] = ((int16_t *)*output_buffer)[out_i] >> shift; } else { - ((uint16_t*) *output_buffer)[out_i] = ((uint16_t*) *output_buffer)[out_i] >> shift; + ((uint16_t *)*output_buffer)[out_i] = ((uint16_t *)*output_buffer)[out_i] >> shift; } } out_i += 1; @@ -116,17 +116,17 @@ void audio_dma_convert_signed(audio_dma_t* dma, uint8_t* buffer, uint32_t buffer dma->first_buffer_free = !dma->first_buffer_free; } -void audio_dma_load_next_block(audio_dma_t* dma) { +void audio_dma_load_next_block(audio_dma_t *dma) { uint8_t dma_channel = dma->channel[1]; if (dma->first_channel_free) { dma_channel = dma->channel[0]; } dma->first_channel_free = !dma->first_channel_free; - uint8_t* output_buffer; + uint8_t *output_buffer; uint32_t output_buffer_length; audioio_get_buffer_result_t get_buffer_result; - uint8_t* buffer; + uint8_t *buffer; uint32_t buffer_length; get_buffer_result = audiosample_get_buffer(dma->sample, dma->single_channel, dma->audio_channel, &buffer, &buffer_length); @@ -151,22 +151,22 @@ void audio_dma_load_next_block(audio_dma_t* dma) { audiosample_reset_buffer(dma->sample, dma->single_channel, dma->audio_channel); } else { // Set channel trigger to ourselves so we don't keep going. - dma_channel_hw_t* c = &dma_hw->ch[dma_channel]; + dma_channel_hw_t *c = &dma_hw->ch[dma_channel]; c->al1_ctrl = (c->al1_ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (dma_channel << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB); } } } // Playback should be shutdown before calling this. -audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, - mp_obj_t sample, - bool loop, - bool single_channel, - uint8_t audio_channel, - bool output_signed, - uint8_t output_resolution, - uint32_t output_register_address, - uint8_t dma_trigger_source) { +audio_dma_result audio_dma_setup_playback(audio_dma_t *dma, + mp_obj_t sample, + bool loop, + bool single_channel, + uint8_t audio_channel, + bool output_signed, + uint8_t output_resolution, + uint32_t output_register_address, + uint8_t dma_trigger_source) { // Use two DMA channels to because the DMA can't wrap to itself without the // buffer being power of two aligned. dma->channel[0] = dma_claim_unused_channel(false); @@ -195,24 +195,24 @@ audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, bool samples_signed; uint32_t max_buffer_length; audiosample_get_buffer_structure(sample, single_channel, &single_buffer, &samples_signed, - &max_buffer_length, &dma->sample_spacing); + &max_buffer_length, &dma->sample_spacing); // Check to see if we have to scale the resolution up. if (dma->sample_resolution <= 8 && dma->output_resolution > 8) { max_buffer_length *= 2; } if (output_signed != samples_signed || - dma->sample_spacing > 1 || - (dma->sample_resolution != dma->output_resolution)) { + dma->sample_spacing > 1 || + (dma->sample_resolution != dma->output_resolution)) { max_buffer_length /= dma->sample_spacing; - dma->first_buffer = (uint8_t*) m_realloc(dma->first_buffer, max_buffer_length); + dma->first_buffer = (uint8_t *)m_realloc(dma->first_buffer, max_buffer_length); if (dma->first_buffer == NULL) { return AUDIO_DMA_MEMORY_ERROR; } dma->first_buffer_free = true; if (!single_buffer) { - dma->second_buffer = (uint8_t*) m_realloc(dma->second_buffer, max_buffer_length); + dma->second_buffer = (uint8_t *)m_realloc(dma->second_buffer, max_buffer_length); if (dma->second_buffer == NULL) { return AUDIO_DMA_MEMORY_ERROR; } @@ -247,7 +247,7 @@ audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, // Chain to the other channel by default. channel_config_set_chain_to(&c, dma->channel[(i + 1) % 2]); dma_channel_set_config(dma->channel[i], &c, false /* trigger */); - dma_channel_set_write_addr(dma->channel[i], (void*) output_register_address, false /* trigger */); + dma_channel_set_write_addr(dma->channel[i], (void *)output_register_address, false /* trigger */); } // We keep the audio_dma_t for internal use and the sample as a root pointer because it @@ -290,7 +290,7 @@ audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, return AUDIO_DMA_OK; } -void audio_dma_stop(audio_dma_t* dma) { +void audio_dma_stop(audio_dma_t *dma) { // Disable our interrupts. dma_hw->inte0 &= ~((1 << dma->channel[0]) | (1 << dma->channel[1])); irq_set_mask_enabled(1 << DMA_IRQ_0, false); @@ -322,12 +322,12 @@ void audio_dma_stop(audio_dma_t* dma) { // To pause we simply stop the DMA. It is the responsibility of the output peripheral // to hold the previous value. -void audio_dma_pause(audio_dma_t* dma) { +void audio_dma_pause(audio_dma_t *dma) { dma_hw->ch[dma->channel[0]].al1_ctrl &= ~DMA_CH0_CTRL_TRIG_EN_BITS; dma_hw->ch[dma->channel[1]].al1_ctrl &= ~DMA_CH0_CTRL_TRIG_EN_BITS; } -void audio_dma_resume(audio_dma_t* dma) { +void audio_dma_resume(audio_dma_t *dma) { // Always re-enable the non-busy channel first so it's ready to continue when the busy channel // finishes and chains to it. (An interrupt could make the time between enables long.) size_t first = 0; @@ -340,7 +340,7 @@ void audio_dma_resume(audio_dma_t* dma) { dma_hw->ch[dma->channel[second]].al1_ctrl |= DMA_CH0_CTRL_TRIG_EN_BITS; } -bool audio_dma_get_paused(audio_dma_t* dma) { +bool audio_dma_get_paused(audio_dma_t *dma) { if (dma->channel[0] >= AUDIO_DMA_CHANNEL_COUNT) { return false; } @@ -349,12 +349,12 @@ bool audio_dma_get_paused(audio_dma_t* dma) { return (control & DMA_CH0_CTRL_TRIG_EN_BITS) == 0; } -void audio_dma_init(audio_dma_t* dma) { +void audio_dma_init(audio_dma_t *dma) { dma->first_buffer = NULL; dma->second_buffer = NULL; } -void audio_dma_deinit(audio_dma_t* dma) { +void audio_dma_deinit(audio_dma_t *dma) { m_free(dma->first_buffer); dma->first_buffer = NULL; @@ -362,7 +362,7 @@ void audio_dma_deinit(audio_dma_t* dma) { dma->second_buffer = NULL; } -bool audio_dma_get_playing(audio_dma_t* dma) { +bool audio_dma_get_playing(audio_dma_t *dma) { if (dma->channel[0] == NUM_DMA_CHANNELS) { return false; } @@ -378,7 +378,7 @@ bool audio_dma_get_playing(audio_dma_t* dma) { // WARN(tannewt): DO NOT print from here, or anything it calls. Printing calls // background tasks such as this and causes a stack overflow. STATIC void dma_callback_fun(void *arg) { - audio_dma_t* dma = arg; + audio_dma_t *dma = arg; if (dma == NULL) { return; } @@ -390,8 +390,8 @@ void isr_dma_0(void) { for (size_t i = 0; i < NUM_DMA_CHANNELS; i++) { uint32_t mask = 1 << i; if ((dma_hw->intr & mask) != 0 && MP_STATE_PORT(playing_audio)[i] != NULL) { - audio_dma_t* dma = MP_STATE_PORT(playing_audio)[i]; - background_callback_add(&dma->callback, dma_callback_fun, (void*)dma); + audio_dma_t *dma = MP_STATE_PORT(playing_audio)[i]; + background_callback_add(&dma->callback, dma_callback_fun, (void *)dma); dma_hw->ints0 = mask; } } diff --git a/ports/raspberrypi/audio_dma.h b/ports/raspberrypi/audio_dma.h index 1f739ff73..faececa8d 100644 --- a/ports/raspberrypi/audio_dma.h +++ b/ports/raspberrypi/audio_dma.h @@ -47,8 +47,8 @@ typedef struct { bool first_buffer_free; uint8_t output_resolution; // in bits uint8_t sample_resolution; // in bits - uint8_t* first_buffer; - uint8_t* second_buffer; + uint8_t *first_buffer; + uint8_t *second_buffer; background_callback_t callback; } audio_dma_t; @@ -59,8 +59,8 @@ typedef enum { } audio_dma_result; -void audio_dma_init(audio_dma_t* dma); -void audio_dma_deinit(audio_dma_t* dma); +void audio_dma_init(audio_dma_t *dma); +void audio_dma_deinit(audio_dma_t *dma); void audio_dma_reset(void); // This sets everything up but doesn't start the timer. @@ -72,20 +72,20 @@ void audio_dma_reset(void); // output_signed is true if the dma'd data should be signed. False and it will be unsigned. // output_register_address is the address to copy data to. // dma_trigger_source is the DMA trigger source which cause another copy -audio_dma_result audio_dma_setup_playback(audio_dma_t* dma, - mp_obj_t sample, - bool loop, - bool single_channel, - uint8_t audio_channel, - bool output_signed, - uint8_t output_resolution, - uint32_t output_register_address, - uint8_t dma_trigger_source); +audio_dma_result audio_dma_setup_playback(audio_dma_t *dma, + mp_obj_t sample, + bool loop, + bool single_channel, + uint8_t audio_channel, + bool output_signed, + uint8_t output_resolution, + uint32_t output_register_address, + uint8_t dma_trigger_source); -void audio_dma_stop(audio_dma_t* dma); -bool audio_dma_get_playing(audio_dma_t* dma); -void audio_dma_pause(audio_dma_t* dma); -void audio_dma_resume(audio_dma_t* dma); -bool audio_dma_get_paused(audio_dma_t* dma); +void audio_dma_stop(audio_dma_t *dma); +bool audio_dma_get_playing(audio_dma_t *dma); +void audio_dma_pause(audio_dma_t *dma); +void audio_dma_resume(audio_dma_t *dma); +bool audio_dma_get_paused(audio_dma_t *dma); #endif // MICROPY_INCLUDED_RASPBERRYPI_AUDIO_DMA_OUT_H diff --git a/ports/raspberrypi/background.c b/ports/raspberrypi/background.c index 52f2e4fb4..4b5190aa2 100644 --- a/ports/raspberrypi/background.c +++ b/ports/raspberrypi/background.c @@ -28,8 +28,10 @@ #include "py/runtime.h" #include "supervisor/port.h" -void port_start_background_task(void) {} -void port_finish_background_task(void) {} +void port_start_background_task(void) { +} +void port_finish_background_task(void) { +} void port_background_task(void) { } diff --git a/ports/raspberrypi/bindings/rp2pio/StateMachine.c b/ports/raspberrypi/bindings/rp2pio/StateMachine.c index 90fd7f95e..946415949 100644 --- a/ports/raspberrypi/bindings/rp2pio/StateMachine.c +++ b/ports/raspberrypi/bindings/rp2pio/StateMachine.c @@ -363,13 +363,13 @@ STATIC mp_obj_t rp2pio_statemachine_write(size_t n_args, const mp_obj_t *pos_arg return mp_const_none; } - uint8_t* original_pointer = bufinfo.buf; + uint8_t *original_pointer = bufinfo.buf; int stride_in_bytes = mp_binary_get_size('@', bufinfo.typecode, NULL); if (stride_in_bytes > 4) { mp_raise_ValueError(translate("Buffer elements must be 4 bytes long or less")); } - bool ok = common_hal_rp2pio_statemachine_write(self, ((uint8_t*)bufinfo.buf) + start, length, stride_in_bytes); + bool ok = common_hal_rp2pio_statemachine_write(self, ((uint8_t *)bufinfo.buf) + start, length, stride_in_bytes); if (mp_hal_is_interrupted()) { return mp_const_none; } @@ -413,13 +413,13 @@ STATIC mp_obj_t rp2pio_statemachine_readinto(size_t n_args, const mp_obj_t *pos_ return mp_const_none; } - uint8_t* original_pointer = bufinfo.buf; + uint8_t *original_pointer = bufinfo.buf; int stride_in_bytes = mp_binary_get_size('@', bufinfo.typecode, NULL); if (stride_in_bytes > 4) { mp_raise_ValueError(translate("Buffer elements must be 4 bytes long or less")); } - bool ok = common_hal_rp2pio_statemachine_readinto(self, ((uint8_t*)bufinfo.buf) + start, length, stride_in_bytes); + bool ok = common_hal_rp2pio_statemachine_readinto(self, ((uint8_t *)bufinfo.buf) + start, length, stride_in_bytes); if (!ok) { mp_raise_OSError(MP_EIO); } @@ -484,12 +484,12 @@ STATIC mp_obj_t rp2pio_statemachine_write_readinto(size_t n_args, const mp_obj_t } bool ok = common_hal_rp2pio_statemachine_write_readinto(self, - ((uint8_t*)buf_out_info.buf) + out_start, - out_length, - out_stride_in_bytes, - ((uint8_t*)buf_in_info.buf) + in_start, - in_length, - in_stride_in_bytes); + ((uint8_t *)buf_out_info.buf) + out_start, + out_length, + out_stride_in_bytes, + ((uint8_t *)buf_in_info.buf) + in_start, + in_length, + in_stride_in_bytes); if (!ok) { mp_raise_OSError(MP_EIO); } @@ -594,10 +594,10 @@ STATIC const mp_rom_map_elem_t rp2pio_statemachine_locals_dict_table[] = { STATIC MP_DEFINE_CONST_DICT(rp2pio_statemachine_locals_dict, rp2pio_statemachine_locals_dict_table); const mp_obj_type_t rp2pio_statemachine_type = { - { &mp_type_type }, - .name = MP_QSTR_StateMachine, - .make_new = rp2pio_statemachine_make_new, - .locals_dict = (mp_obj_dict_t*)&rp2pio_statemachine_locals_dict, + { &mp_type_type }, + .name = MP_QSTR_StateMachine, + .make_new = rp2pio_statemachine_make_new, + .locals_dict = (mp_obj_dict_t *)&rp2pio_statemachine_locals_dict, }; rp2pio_statemachine_obj_t *validate_obj_is_statemachine(mp_obj_t obj) { diff --git a/ports/raspberrypi/bindings/rp2pio/StateMachine.h b/ports/raspberrypi/bindings/rp2pio/StateMachine.h index 3a0d4290d..661bddd81 100644 --- a/ports/raspberrypi/bindings/rp2pio/StateMachine.h +++ b/ports/raspberrypi/bindings/rp2pio/StateMachine.h @@ -37,13 +37,13 @@ extern const mp_obj_type_t rp2pio_statemachine_type; // Construct an underlying SPI object. void common_hal_rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, - const uint16_t* program, size_t program_len, + const uint16_t *program, size_t program_len, size_t frequency, - const uint16_t* init, size_t init_len, - const mcu_pin_obj_t * first_out_pin, uint8_t out_pin_count, uint32_t initial_out_pin_state, uint32_t initial_out_pin_direction, - const mcu_pin_obj_t * first_in_pin, uint8_t in_pin_count, uint32_t pull_pin_up, uint32_t pull_pin_down, - const mcu_pin_obj_t * first_set_pin, uint8_t set_pin_count, uint32_t initial_set_pin_state, uint32_t initial_set_pin_direction, - const mcu_pin_obj_t * first_sideset_pin, uint8_t sideset_pin_count, uint32_t initial_sideset_pin_state, uint32_t initial_sideset_pin_direction, + const uint16_t *init, size_t init_len, + const mcu_pin_obj_t *first_out_pin, uint8_t out_pin_count, uint32_t initial_out_pin_state, uint32_t initial_out_pin_direction, + const mcu_pin_obj_t *first_in_pin, uint8_t in_pin_count, uint32_t pull_pin_up, uint32_t pull_pin_down, + const mcu_pin_obj_t *first_set_pin, uint8_t set_pin_count, uint32_t initial_set_pin_state, uint32_t initial_set_pin_direction, + const mcu_pin_obj_t *first_sideset_pin, uint8_t sideset_pin_count, uint32_t initial_sideset_pin_state, uint32_t initial_sideset_pin_direction, bool exclusive_pin_use, bool auto_pull, uint8_t pull_threshold, bool out_shift_right, bool wait_for_txstall, @@ -60,17 +60,17 @@ void common_hal_rp2pio_statemachine_run(rp2pio_statemachine_obj_t *self, const u bool common_hal_rp2pio_statemachine_write(rp2pio_statemachine_obj_t *self, const uint8_t *data, size_t len, uint8_t stride_in_bytes); bool common_hal_rp2pio_statemachine_readinto(rp2pio_statemachine_obj_t *self, uint8_t *data, size_t len, uint8_t stride_in_bytes); bool common_hal_rp2pio_statemachine_write_readinto(rp2pio_statemachine_obj_t *self, - const uint8_t *data_out, size_t out_len, uint8_t out_stride_in_bytes, - uint8_t *data_in, size_t in_len, uint8_t in_stride_in_bytes); + const uint8_t *data_out, size_t out_len, uint8_t out_stride_in_bytes, + uint8_t *data_in, size_t in_len, uint8_t in_stride_in_bytes); // Return actual state machine frequency. -uint32_t common_hal_rp2pio_statemachine_get_frequency(rp2pio_statemachine_obj_t* self); -void common_hal_rp2pio_statemachine_set_frequency(rp2pio_statemachine_obj_t* self, uint32_t frequency); +uint32_t common_hal_rp2pio_statemachine_get_frequency(rp2pio_statemachine_obj_t *self); +void common_hal_rp2pio_statemachine_set_frequency(rp2pio_statemachine_obj_t *self, uint32_t frequency); -bool common_hal_rp2pio_statemachine_get_rxstall(rp2pio_statemachine_obj_t* self); +bool common_hal_rp2pio_statemachine_get_rxstall(rp2pio_statemachine_obj_t *self); void common_hal_rp2pio_statemachine_clear_rxfifo(rp2pio_statemachine_obj_t *self); size_t common_hal_rp2pio_statemachine_get_in_waiting(rp2pio_statemachine_obj_t *self); -void common_hal_rp2pio_statemachine_set_interrupt_handler(rp2pio_statemachine_obj_t *self, void(*handler)(void*), void *arg, int mask); +void common_hal_rp2pio_statemachine_set_interrupt_handler(rp2pio_statemachine_obj_t *self, void (*handler)(void *), void *arg, int mask); #endif // MICROPY_INCLUDED_RASPBERRYPI_BINDINGS_RP2PIO_STATEMACHINE_H diff --git a/ports/raspberrypi/bindings/rp2pio/__init__.c b/ports/raspberrypi/bindings/rp2pio/__init__.c index 7eab423e9..68f7cf301 100644 --- a/ports/raspberrypi/bindings/rp2pio/__init__.c +++ b/ports/raspberrypi/bindings/rp2pio/__init__.c @@ -56,5 +56,5 @@ STATIC MP_DEFINE_CONST_DICT(rp2pio_module_globals, rp2pio_module_globals_table); const mp_obj_module_t rp2pio_module = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&rp2pio_module_globals, + .globals = (mp_obj_dict_t *)&rp2pio_module_globals, }; diff --git a/ports/raspberrypi/boards/raspberry_pi_pico/board.c b/ports/raspberrypi/boards/raspberry_pi_pico/board.c index 80ec5de32..67486d4c2 100644 --- a/ports/raspberrypi/boards/raspberry_pi_pico/board.c +++ b/ports/raspberrypi/boards/raspberry_pi_pico/board.c @@ -26,8 +26,7 @@ #include "supervisor/board.h" -void board_init(void) -{ +void board_init(void) { } bool board_requests_safe_mode(void) { diff --git a/ports/raspberrypi/common-hal/analogio/AnalogIn.c b/ports/raspberrypi/common-hal/analogio/AnalogIn.c index c51a74929..7db2956b0 100644 --- a/ports/raspberrypi/common-hal/analogio/AnalogIn.c +++ b/ports/raspberrypi/common-hal/analogio/AnalogIn.c @@ -64,7 +64,7 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { uint16_t value = adc_read(); // Map value to from 12 to 16 bits - return (value << 4); + return value << 4; } float common_hal_analogio_analogin_get_reference_voltage(analogio_analogin_obj_t *self) { diff --git a/ports/raspberrypi/common-hal/analogio/AnalogIn.h b/ports/raspberrypi/common-hal/analogio/AnalogIn.h index ee9976e34..c322a6776 100644 --- a/ports/raspberrypi/common-hal/analogio/AnalogIn.h +++ b/ports/raspberrypi/common-hal/analogio/AnalogIn.h @@ -33,7 +33,7 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t * pin; + const mcu_pin_obj_t *pin; } analogio_analogin_obj_t; void analogin_init(void); diff --git a/ports/raspberrypi/common-hal/analogio/AnalogOut.c b/ports/raspberrypi/common-hal/analogio/AnalogOut.c index adafa15d5..7afa773d3 100644 --- a/ports/raspberrypi/common-hal/analogio/AnalogOut.c +++ b/ports/raspberrypi/common-hal/analogio/AnalogOut.c @@ -33,7 +33,7 @@ #include "py/runtime.h" #include "supervisor/shared/translate.h" -void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self, const mcu_pin_obj_t *pin) { mp_raise_RuntimeError(translate("AnalogOut functionality not supported")); } diff --git a/ports/raspberrypi/common-hal/audiobusio/I2SOut.c b/ports/raspberrypi/common-hal/audiobusio/I2SOut.c index fa5852fce..5f77a74a5 100644 --- a/ports/raspberrypi/common-hal/audiobusio/I2SOut.c +++ b/ports/raspberrypi/common-hal/audiobusio/I2SOut.c @@ -101,18 +101,19 @@ void i2sout_reset(void) { } // Caller validates that pins are free. -void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, - const mcu_pin_obj_t* bit_clock, const mcu_pin_obj_t* word_select, - const mcu_pin_obj_t* data, bool left_justified) { +void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t *self, + const mcu_pin_obj_t *bit_clock, const mcu_pin_obj_t *word_select, + const mcu_pin_obj_t *data, bool left_justified) { if (bit_clock->number != word_select->number - 1) { mp_raise_ValueError(translate("Bit clock and word select must be sequential pins")); } - const uint16_t* program = i2s_program; + const uint16_t *program = i2s_program; size_t program_len = sizeof(i2s_program) / sizeof(i2s_program[0]); if (left_justified) { program = i2s_program_left_justified; - program_len = sizeof(i2s_program_left_justified) / sizeof(i2s_program_left_justified[0]);; + program_len = sizeof(i2s_program_left_justified) / sizeof(i2s_program_left_justified[0]); + ; } // Use the state machine to manage pins. @@ -134,11 +135,11 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, audio_dma_init(&self->dma); } -bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_deinited(audiobusio_i2sout_obj_t *self) { return common_hal_rp2pio_statemachine_deinited(&self->state_machine); } -void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t *self) { if (common_hal_audiobusio_i2sout_deinited(self)) { return; } @@ -146,8 +147,8 @@ void common_hal_audiobusio_i2sout_deinit(audiobusio_i2sout_obj_t* self) { common_hal_rp2pio_statemachine_deinit(&self->state_machine); } -void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, - mp_obj_t sample, bool loop) { +void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t *self, + mp_obj_t sample, bool loop) { if (common_hal_audiobusio_i2sout_get_playing(self)) { common_hal_audiobusio_i2sout_stop(self); } @@ -178,7 +179,7 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, 0, // audio channel true, // output signed bits_per_sample, - (uint32_t) &self->state_machine.pio->txf[self->state_machine.state_machine], // output register + (uint32_t)&self->state_machine.pio->txf[self->state_machine.state_machine], // output register self->state_machine.tx_dreq); // data request line if (result == AUDIO_DMA_DMA_BUSY) { @@ -194,21 +195,21 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, self->playing = true; } -void common_hal_audiobusio_i2sout_pause(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_pause(audiobusio_i2sout_obj_t *self) { audio_dma_pause(&self->dma); } -void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t *self) { // Maybe: Clear any overrun/underrun errors audio_dma_resume(&self->dma); } -bool common_hal_audiobusio_i2sout_get_paused(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_get_paused(audiobusio_i2sout_obj_t *self) { return audio_dma_get_paused(&self->dma); } -void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t* self) { +void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t *self) { audio_dma_stop(&self->dma); common_hal_rp2pio_statemachine_stop(&self->state_machine); @@ -216,7 +217,7 @@ void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t* self) { self->playing = false; } -bool common_hal_audiobusio_i2sout_get_playing(audiobusio_i2sout_obj_t* self) { +bool common_hal_audiobusio_i2sout_get_playing(audiobusio_i2sout_obj_t *self) { bool playing = audio_dma_get_playing(&self->dma); if (!playing && self->playing) { common_hal_audiobusio_i2sout_stop(self); diff --git a/ports/raspberrypi/common-hal/audiobusio/PDMIn.c b/ports/raspberrypi/common-hal/audiobusio/PDMIn.c index 883660271..bbcfbb805 100644 --- a/ports/raspberrypi/common-hal/audiobusio/PDMIn.c +++ b/ports/raspberrypi/common-hal/audiobusio/PDMIn.c @@ -50,13 +50,13 @@ const uint16_t pdmin[] = { }; // Caller validates that pins are free. -void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, - const mcu_pin_obj_t* clock_pin, - const mcu_pin_obj_t* data_pin, - uint32_t sample_rate, - uint8_t bit_depth, - bool mono, - uint8_t oversample) { +void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t *self, + const mcu_pin_obj_t *clock_pin, + const mcu_pin_obj_t *data_pin, + uint32_t sample_rate, + uint8_t bit_depth, + bool mono, + uint8_t oversample) { if (!(bit_depth == 16 || bit_depth == 8) || !mono || oversample != OVERSAMPLING) { mp_raise_NotImplementedError(translate("Only 8 or 16 bit mono with " MP_STRINGIFY(OVERSAMPLING) "x oversampling is supported.")); } @@ -77,30 +77,30 @@ void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, false, 32, true); // in settings uint32_t actual_frequency = common_hal_rp2pio_statemachine_get_frequency(&self->state_machine); - if (actual_frequency < MIN_MIC_CLOCK) { + if (actual_frequency < MIN_MIC_CLOCK) { mp_raise_ValueError(translate("sampling rate out of range")); } - self->sample_rate = actual_frequency / oversample; + self->sample_rate = actual_frequency / oversample; self->bit_depth = bit_depth; } -bool common_hal_audiobusio_pdmin_deinited(audiobusio_pdmin_obj_t* self) { +bool common_hal_audiobusio_pdmin_deinited(audiobusio_pdmin_obj_t *self) { return common_hal_rp2pio_statemachine_deinited(&self->state_machine); } -void common_hal_audiobusio_pdmin_deinit(audiobusio_pdmin_obj_t* self) { +void common_hal_audiobusio_pdmin_deinit(audiobusio_pdmin_obj_t *self) { if (common_hal_audiobusio_pdmin_deinited(self)) { return; } return common_hal_rp2pio_statemachine_deinit(&self->state_machine); } -uint8_t common_hal_audiobusio_pdmin_get_bit_depth(audiobusio_pdmin_obj_t* self) { +uint8_t common_hal_audiobusio_pdmin_get_bit_depth(audiobusio_pdmin_obj_t *self) { return self->bit_depth; } -uint32_t common_hal_audiobusio_pdmin_get_sample_rate(audiobusio_pdmin_obj_t* self) { +uint32_t common_hal_audiobusio_pdmin_get_sample_rate(audiobusio_pdmin_obj_t *self) { return self->sample_rate; } @@ -114,7 +114,7 @@ uint32_t common_hal_audiobusio_pdmin_get_sample_rate(audiobusio_pdmin_obj_t* sel // higher sample rate than specified. Then after the audio is // recorded, a more expensive filter non-real-time filter could be // used to down-sample and low-pass. -const uint16_t sinc_filter [OVERSAMPLING] = { +const uint16_t sinc_filter[OVERSAMPLING] = { 0, 2, 9, 21, 39, 63, 94, 132, 179, 236, 302, 379, 467, 565, 674, 792, 920, 1055, 1196, 1341, 1487, 1633, 1776, 1913, @@ -125,20 +125,20 @@ const uint16_t sinc_filter [OVERSAMPLING] = { 94, 63, 39, 21, 9, 2, 0, 0 }; -#define REPEAT_32_TIMES(X) do { X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X } while(0) +#define REPEAT_32_TIMES(X) do { X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X } while (0) static uint16_t filter_sample(uint32_t pdm_samples[2]) { uint16_t running_sum = 0; const uint16_t *filter_ptr = sinc_filter; for (uint8_t i = 0; i < 2; i++) { uint32_t pdm_sample = pdm_samples[i]; - REPEAT_32_TIMES( { - if (pdm_sample & 0x1) { - running_sum += *filter_ptr; - } - filter_ptr++; - pdm_sample >>= 1; + REPEAT_32_TIMES({ + if (pdm_sample & 0x1) { + running_sum += *filter_ptr; } + filter_ptr++; + pdm_sample >>= 1; + } ); } return running_sum; @@ -146,20 +146,20 @@ static uint16_t filter_sample(uint32_t pdm_samples[2]) { // output_buffer may be a byte buffer or a halfword buffer. // output_buffer_length is the number of slots, not the number of bytes. -uint32_t common_hal_audiobusio_pdmin_record_to_buffer(audiobusio_pdmin_obj_t* self, - uint16_t* output_buffer, uint32_t output_buffer_length) { +uint32_t common_hal_audiobusio_pdmin_record_to_buffer(audiobusio_pdmin_obj_t *self, + uint16_t *output_buffer, uint32_t output_buffer_length) { uint32_t samples[2]; size_t output_count = 0; common_hal_rp2pio_statemachine_clear_rxfifo(&self->state_machine); // Do one read to get the mic going and throw it away. - common_hal_rp2pio_statemachine_readinto(&self->state_machine, (uint8_t*) samples, 2 * sizeof(uint32_t), sizeof(uint32_t)); + common_hal_rp2pio_statemachine_readinto(&self->state_machine, (uint8_t *)samples, 2 * sizeof(uint32_t), sizeof(uint32_t)); while (output_count < output_buffer_length && !common_hal_rp2pio_statemachine_get_rxstall(&self->state_machine)) { - common_hal_rp2pio_statemachine_readinto(&self->state_machine, (uint8_t*) samples, 2 * sizeof(uint32_t), sizeof(uint32_t)); + common_hal_rp2pio_statemachine_readinto(&self->state_machine, (uint8_t *)samples, 2 * sizeof(uint32_t), sizeof(uint32_t)); // Call filter_sample just one place so it can be inlined. uint16_t value = filter_sample(samples); if (self->bit_depth == 8) { // Truncate to 8 bits. - ((uint8_t*) output_buffer)[output_count] = value >> 8; + ((uint8_t *)output_buffer)[output_count] = value >> 8; } else { output_buffer[output_count] = value; } @@ -169,6 +169,6 @@ uint32_t common_hal_audiobusio_pdmin_record_to_buffer(audiobusio_pdmin_obj_t* se return output_count; } -void common_hal_audiobusio_pdmin_record_to_file(audiobusio_pdmin_obj_t* self, uint8_t* buffer, uint32_t length) { +void common_hal_audiobusio_pdmin_record_to_file(audiobusio_pdmin_obj_t *self, uint8_t *buffer, uint32_t length) { } diff --git a/ports/raspberrypi/common-hal/audiopwmio/PWMAudioOut.c b/ports/raspberrypi/common-hal/audiopwmio/PWMAudioOut.c index 57605a1fb..4fef53ff0 100644 --- a/ports/raspberrypi/common-hal/audiopwmio/PWMAudioOut.c +++ b/ports/raspberrypi/common-hal/audiopwmio/PWMAudioOut.c @@ -53,8 +53,8 @@ void audiopwmout_reset() { } // Caller validates that pins are free. -void common_hal_audiopwmio_pwmaudioout_construct(audiopwmio_pwmaudioout_obj_t* self, - const mcu_pin_obj_t* left_channel, const mcu_pin_obj_t* right_channel, uint16_t quiescent_value) { +void common_hal_audiopwmio_pwmaudioout_construct(audiopwmio_pwmaudioout_obj_t *self, + const mcu_pin_obj_t *left_channel, const mcu_pin_obj_t *right_channel, uint16_t quiescent_value) { if (left_channel != NULL && right_channel != NULL) { if (pwm_gpio_to_slice_num(left_channel->number) != pwm_gpio_to_slice_num(right_channel->number)) { mp_raise_ValueError(translate("Pins must share PWM slice")); @@ -106,11 +106,11 @@ void common_hal_audiopwmio_pwmaudioout_construct(audiopwmio_pwmaudioout_obj_t* s self->quiescent_value = quiescent_value; } -bool common_hal_audiopwmio_pwmaudioout_deinited(audiopwmio_pwmaudioout_obj_t* self) { +bool common_hal_audiopwmio_pwmaudioout_deinited(audiopwmio_pwmaudioout_obj_t *self) { return common_hal_pwmio_pwmout_deinited(&self->left_pwm); } -void common_hal_audiopwmio_pwmaudioout_deinit(audiopwmio_pwmaudioout_obj_t* self) { +void common_hal_audiopwmio_pwmaudioout_deinit(audiopwmio_pwmaudioout_obj_t *self) { if (common_hal_audiopwmio_pwmaudioout_deinited(self)) { return; } @@ -125,7 +125,7 @@ void common_hal_audiopwmio_pwmaudioout_deinit(audiopwmio_pwmaudioout_obj_t* self audio_dma_deinit(&self->dma); } -void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t* self, mp_obj_t sample, bool loop) { +void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t *self, mp_obj_t sample, bool loop) { if (common_hal_audiopwmio_pwmaudioout_get_playing(self)) { common_hal_audiopwmio_pwmaudioout_stop(self); } @@ -141,7 +141,7 @@ void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t* self, if (pacing_timer == NUM_DMA_TIMERS) { mp_raise_RuntimeError(translate("No DMA pacing timer found")); } - uint32_t tx_register = (uint32_t) &pwm_hw->slice[self->left_pwm.slice].cc; + uint32_t tx_register = (uint32_t)&pwm_hw->slice[self->left_pwm.slice].cc; if (common_hal_pwmio_pwmout_deinited(&self->right_pwm)) { // Shift the destination if we are outputting to the second PWM channel. tx_register += self->left_pwm.channel * sizeof(uint16_t); @@ -157,7 +157,7 @@ void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t* self, 0, // audio channel false, // output signed 10, - (uint32_t) tx_register, // output register + (uint32_t)tx_register, // output register 0x3b + pacing_timer); // data request line if (result == AUDIO_DMA_DMA_BUSY) { @@ -206,14 +206,14 @@ void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t* self, dma_hw->timer[pacing_timer] = best_numerator << 16 | best_denominator; } -void common_hal_audiopwmio_pwmaudioout_stop(audiopwmio_pwmaudioout_obj_t* self) { +void common_hal_audiopwmio_pwmaudioout_stop(audiopwmio_pwmaudioout_obj_t *self) { dma_hw->timer[self->pacing_timer] = 0; self->pacing_timer = NUM_DMA_TIMERS; audio_dma_stop(&self->dma); } -bool common_hal_audiopwmio_pwmaudioout_get_playing(audiopwmio_pwmaudioout_obj_t* self) { +bool common_hal_audiopwmio_pwmaudioout_get_playing(audiopwmio_pwmaudioout_obj_t *self) { bool playing = audio_dma_get_playing(&self->dma); if (!playing && self->pacing_timer < NUM_DMA_TIMERS) { dma_hw->timer[self->pacing_timer] = 0; @@ -222,14 +222,14 @@ bool common_hal_audiopwmio_pwmaudioout_get_playing(audiopwmio_pwmaudioout_obj_t* return playing; } -void common_hal_audiopwmio_pwmaudioout_pause(audiopwmio_pwmaudioout_obj_t* self) { +void common_hal_audiopwmio_pwmaudioout_pause(audiopwmio_pwmaudioout_obj_t *self) { audio_dma_pause(&self->dma); } -void common_hal_audiopwmio_pwmaudioout_resume(audiopwmio_pwmaudioout_obj_t* self) { +void common_hal_audiopwmio_pwmaudioout_resume(audiopwmio_pwmaudioout_obj_t *self) { audio_dma_resume(&self->dma); } -bool common_hal_audiopwmio_pwmaudioout_get_paused(audiopwmio_pwmaudioout_obj_t* self) { +bool common_hal_audiopwmio_pwmaudioout_get_paused(audiopwmio_pwmaudioout_obj_t *self) { return audio_dma_get_paused(&self->dma); } diff --git a/ports/raspberrypi/common-hal/busio/I2C.c b/ports/raspberrypi/common-hal/busio/I2C.c index cb0d73e75..c9f89fadd 100644 --- a/ports/raspberrypi/common-hal/busio/I2C.c +++ b/ports/raspberrypi/common-hal/busio/I2C.c @@ -42,7 +42,7 @@ #define BUS_TIMEOUT_US 1000000 STATIC bool never_reset_i2c[2]; -STATIC i2c_inst_t* i2c[2] = {i2c0, i2c1}; +STATIC i2c_inst_t *i2c[2] = {i2c0, i2c1}; void reset_i2c(void) { for (size_t i = 0; i < 2; i++) { @@ -55,7 +55,7 @@ void reset_i2c(void) { } void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, - const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda, uint32_t frequency, uint32_t timeout) { + const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) { self->peripheral = NULL; // I2C pins have a regular pattern. SCL is always odd and SDA is even. They match up in pairs // so we can divide by two to get the instance. This pattern repeats. @@ -73,7 +73,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, mp_raise_ValueError(translate("Unsupported baudrate")); } -#if CIRCUITPY_REQUIRE_I2C_PULLUPS + #if CIRCUITPY_REQUIRE_I2C_PULLUPS // Test that the pins are in a high state. (Hopefully indicating they are pulled up.) gpio_set_function(sda->number, GPIO_FUNC_SIO); gpio_set_function(scl->number, GPIO_FUNC_SIO); @@ -96,7 +96,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, reset_pin_number(scl->number); mp_raise_RuntimeError(translate("No pull up found on SDA or SCL; check your wiring")); } -#endif + #endif // Create a bitbangio.I2C object to do short writes. // Must be done before setting up the I2C pins, since they will be @@ -104,7 +104,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, // // Sets pins to open drain, high, and input. shared_module_bitbangio_i2c_construct(&self->bitbangio_i2c, scl, sda, - frequency, timeout); + frequency, timeout); self->baudrate = i2c_init(self->peripheral, frequency); @@ -157,7 +157,7 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) { } uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, - const uint8_t *data, size_t len, bool transmit_stop_bit) { + const uint8_t *data, size_t len, bool transmit_stop_bit) { if (len <= 2) { // The RP2040 I2C peripheral will not do writes 2 bytes or less long. // So use bitbangio.I2C to do the write. @@ -170,7 +170,7 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, gpio_put(self->sda_pin, false); uint8_t status = shared_module_bitbangio_i2c_write(&self->bitbangio_i2c, - addr, data, len, transmit_stop_bit); + addr, data, len, transmit_stop_bit); // The pins must be set back to GPIO_FUNC_I2C in the order given here, // SCL first, otherwise reads will hang. @@ -195,7 +195,7 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, } uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, - uint8_t *data, size_t len) { + uint8_t *data, size_t len) { int result = i2c_read_timeout_us(self->peripheral, addr, data, len, false, BUS_TIMEOUT_US); if (result == len) { return 0; diff --git a/ports/raspberrypi/common-hal/busio/I2C.h b/ports/raspberrypi/common-hal/busio/I2C.h index 651054a04..dbaede1f5 100644 --- a/ports/raspberrypi/common-hal/busio/I2C.h +++ b/ports/raspberrypi/common-hal/busio/I2C.h @@ -36,7 +36,7 @@ typedef struct { mp_obj_base_t base; - i2c_inst_t * peripheral; + i2c_inst_t *peripheral; bitbangio_i2c_obj_t bitbangio_i2c; bool has_lock; uint baudrate; diff --git a/ports/raspberrypi/common-hal/busio/SPI.c b/ports/raspberrypi/common-hal/busio/SPI.c index b157ae3eb..0fc71136e 100644 --- a/ports/raspberrypi/common-hal/busio/SPI.c +++ b/ports/raspberrypi/common-hal/busio/SPI.c @@ -41,7 +41,7 @@ #define NO_INSTANCE 0xff STATIC bool never_reset_spi[2]; -STATIC spi_inst_t* spi[2] = {spi0, spi1}; +STATIC spi_inst_t *spi[2] = {spi0, spi1}; void reset_spi(void) { for (size_t i = 0; i < 2; i++) { @@ -54,8 +54,8 @@ void reset_spi(void) { } void common_hal_busio_spi_construct(busio_spi_obj_t *self, - const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi, - const mcu_pin_obj_t * miso) { + const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi, + const mcu_pin_obj_t *miso) { size_t instance_index = NO_INSTANCE; if (clock->number % 4 == 2) { instance_index = (clock->number / 8) % 2; @@ -136,7 +136,7 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { } bool common_hal_busio_spi_configure(busio_spi_obj_t *self, - uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { + uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { if (baudrate == self->target_frequency && polarity == self->polarity && phase == self->phase && @@ -244,7 +244,7 @@ static bool _transfer(busio_spi_obj_t *self, while (!mp_hal_is_interrupted() && (rx_remaining || tx_remaining)) { if (tx_remaining && spi_is_writable(self->peripheral) && rx_remaining - tx_remaining < fifo_depth) { - spi_get_hw(self->peripheral)->dr = (uint32_t) *data_out; + spi_get_hw(self->peripheral)->dr = (uint32_t)*data_out; // Increment only if the buffer is the transfer length. It's 1 otherwise. if (out_len == len) { data_out++; @@ -252,7 +252,7 @@ static bool _transfer(busio_spi_obj_t *self, --tx_remaining; } if (rx_remaining && spi_is_readable(self->peripheral)) { - *data_in = (uint8_t) spi_get_hw(self->peripheral)->dr; + *data_in = (uint8_t)spi_get_hw(self->peripheral)->dr; // Increment only if the buffer is the transfer length. It's 1 otherwise. if (in_len == len) { data_in++; @@ -266,29 +266,29 @@ static bool _transfer(busio_spi_obj_t *self, } bool common_hal_busio_spi_write(busio_spi_obj_t *self, - const uint8_t *data, size_t len) { + const uint8_t *data, size_t len) { uint32_t data_in; - return _transfer(self, data, len, (uint8_t*) &data_in, MIN(len, 4)); + return _transfer(self, data, len, (uint8_t *)&data_in, MIN(len, 4)); } bool common_hal_busio_spi_read(busio_spi_obj_t *self, - uint8_t *data, size_t len, uint8_t write_value) { + uint8_t *data, size_t len, uint8_t write_value) { uint32_t data_out = write_value << 24 | write_value << 16 | write_value << 8 | write_value; - return _transfer(self, (const uint8_t*) &data_out, MIN(4, len), data, len); + return _transfer(self, (const uint8_t *)&data_out, MIN(4, len), data, len); } bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_out, uint8_t *data_in, size_t len) { return _transfer(self, data_out, len, data_in, len); } -uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) { +uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) { return self->real_frequency; } -uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) { return self->phase; } -uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) { return self->polarity; } diff --git a/ports/raspberrypi/common-hal/busio/SPI.h b/ports/raspberrypi/common-hal/busio/SPI.h index 981db46d4..b76dbbf9d 100644 --- a/ports/raspberrypi/common-hal/busio/SPI.h +++ b/ports/raspberrypi/common-hal/busio/SPI.h @@ -35,11 +35,11 @@ typedef struct { mp_obj_base_t base; - spi_inst_t * peripheral; + spi_inst_t *peripheral; bool has_lock; - const mcu_pin_obj_t* clock; - const mcu_pin_obj_t* MOSI; - const mcu_pin_obj_t* MISO; + const mcu_pin_obj_t *clock; + const mcu_pin_obj_t *MOSI; + const mcu_pin_obj_t *MISO; uint32_t target_frequency; int32_t real_frequency; uint8_t polarity; diff --git a/ports/raspberrypi/common-hal/busio/UART.c b/ports/raspberrypi/common-hal/busio/UART.c index 1bc121177..2d8ff099e 100644 --- a/ports/raspberrypi/common-hal/busio/UART.c +++ b/ports/raspberrypi/common-hal/busio/UART.c @@ -61,7 +61,7 @@ void never_reset_uart(uint8_t num) { uart_status[num] = STATUS_NEVER_RESET; } -static uint8_t pin_init(const uint8_t uart, const mcu_pin_obj_t * pin, const uint8_t pin_type) { +static uint8_t pin_init(const uint8_t uart, const mcu_pin_obj_t *pin, const uint8_t pin_type) { if (pin == NULL) { return NO_PIN; } @@ -73,11 +73,11 @@ static uint8_t pin_init(const uint8_t uart, const mcu_pin_obj_t * pin, const uin return pin->number; } -static busio_uart_obj_t* active_uarts[NUM_UARTS]; +static busio_uart_obj_t *active_uarts[NUM_UARTS]; -static void _copy_into_ringbuf(ringbuf_t* r, uart_inst_t* uart) { +static void _copy_into_ringbuf(ringbuf_t *r, uart_inst_t *uart) { while (uart_is_readable(uart) && ringbuf_num_empty(r) > 0) { - ringbuf_put(r, (uint8_t) uart_get_hw(uart)->dr); + ringbuf_put(r, (uint8_t)uart_get_hw(uart)->dr); } } @@ -97,12 +97,12 @@ static void uart1_callback(void) { } void common_hal_busio_uart_construct(busio_uart_obj_t *self, - const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx, - const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts, - const mcu_pin_obj_t * rs485_dir, bool rs485_invert, - uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, - mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer, - bool sigint_enabled) { + const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx, + const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts, + const mcu_pin_obj_t *rs485_dir, bool rs485_invert, + uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, + mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer, + bool sigint_enabled) { if (bits > 8) { mp_raise_ValueError(translate("Invalid word/bit length")); @@ -223,7 +223,7 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t // Check if we still need to read more data. if (len > total_read) { - len-=total_read; + len -= total_read; uint64_t start_ticks = supervisor_ticks_ms64(); // Busy-wait until timeout or until we've read enough chars. while (len > 0 && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms)) { @@ -272,7 +272,7 @@ void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrat } mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) { - return (mp_float_t) (self->timeout_ms / 1000.0f); + return (mp_float_t)(self->timeout_ms / 1000.0f); } void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) { @@ -296,7 +296,7 @@ void common_hal_busio_uart_clear_rx_buffer(busio_uart_obj_t *self) { // Throw away the FIFO contents too. while (uart_is_readable(self->uart)) { - (void) uart_get_hw(self->uart)->dr; + (void)uart_get_hw(self->uart)->dr; } irq_set_enabled(self->uart_irq_id, true); } diff --git a/ports/raspberrypi/common-hal/busio/UART.h b/ports/raspberrypi/common-hal/busio/UART.h index 4c07de240..f6978fd1d 100644 --- a/ports/raspberrypi/common-hal/busio/UART.h +++ b/ports/raspberrypi/common-hal/busio/UART.h @@ -42,7 +42,7 @@ typedef struct { uint8_t uart_irq_id; uint32_t baudrate; uint32_t timeout_ms; - uart_inst_t * uart; + uart_inst_t *uart; ringbuf_t ringbuf; } busio_uart_obj_t; diff --git a/ports/raspberrypi/common-hal/countio/Counter.c b/ports/raspberrypi/common-hal/countio/Counter.c index 69629a084..2dcd1de12 100644 --- a/ports/raspberrypi/common-hal/countio/Counter.c +++ b/ports/raspberrypi/common-hal/countio/Counter.c @@ -11,8 +11,8 @@ #include "src/rp2_common/hardware_irq/include/hardware/irq.h" -void common_hal_countio_counter_construct(countio_counter_obj_t* self, - const mcu_pin_obj_t* pin_a) { +void common_hal_countio_counter_construct(countio_counter_obj_t *self, + const mcu_pin_obj_t *pin_a) { if (pwm_gpio_to_channel(pin_a->number) != PWM_CHAN_B) { mp_raise_RuntimeError(translate("Pin must be on PWM Channel B")); @@ -48,11 +48,11 @@ void common_hal_countio_counter_construct(countio_counter_obj_t* self, pwm_set_enabled(self->slice_num, true); } -bool common_hal_countio_counter_deinited(countio_counter_obj_t* self) { +bool common_hal_countio_counter_deinited(countio_counter_obj_t *self) { return self->pin_a == 0; } -void common_hal_countio_counter_deinit(countio_counter_obj_t* self) { +void common_hal_countio_counter_deinit(countio_counter_obj_t *self) { if (common_hal_countio_counter_deinited(self)) { return; } @@ -69,19 +69,19 @@ void common_hal_countio_counter_deinit(countio_counter_obj_t* self) { self->slice_num = 0; } -mp_int_t common_hal_countio_counter_get_count(countio_counter_obj_t* self) { +mp_int_t common_hal_countio_counter_get_count(countio_counter_obj_t *self) { self->count += pwm_get_counter(self->slice_num); pwm_set_counter(self->slice_num, 0); return self->count; } -void common_hal_countio_counter_set_count(countio_counter_obj_t* self, - mp_int_t new_count) { +void common_hal_countio_counter_set_count(countio_counter_obj_t *self, + mp_int_t new_count) { pwm_set_counter(self->slice_num, 0); self->count = new_count; } -void common_hal_countio_counter_reset(countio_counter_obj_t* self){ +void common_hal_countio_counter_reset(countio_counter_obj_t *self) { pwm_set_counter(self->slice_num, 0); self->count = 0; } @@ -95,7 +95,7 @@ void counter_interrupt_handler() { ++pos; } - countio_counter_obj_t *self = MP_STATE_PORT(counting)[pos-1]; + countio_counter_obj_t *self = MP_STATE_PORT(counting)[pos - 1]; if (self != NULL) { pwm_clear_irq(self->slice_num); self->count += 65536; diff --git a/ports/raspberrypi/common-hal/countio/__init__.c b/ports/raspberrypi/common-hal/countio/__init__.c index b95b20d15..d47de33e5 100644 --- a/ports/raspberrypi/common-hal/countio/__init__.c +++ b/ports/raspberrypi/common-hal/countio/__init__.c @@ -1 +1 @@ -//No countio module functions +// No countio module functions diff --git a/ports/raspberrypi/common-hal/digitalio/DigitalInOut.c b/ports/raspberrypi/common-hal/digitalio/DigitalInOut.c index a1a23b9ab..22a61afa3 100644 --- a/ports/raspberrypi/common-hal/digitalio/DigitalInOut.c +++ b/ports/raspberrypi/common-hal/digitalio/DigitalInOut.c @@ -37,7 +37,7 @@ #include "src/rp2_common/hardware_gpio/include/hardware/gpio.h" digitalinout_result_t common_hal_digitalio_digitalinout_construct( - digitalio_digitalinout_obj_t* self, const mcu_pin_obj_t* pin) { + digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { claim_pin(pin); self->pin = pin; self->output = false; @@ -49,15 +49,15 @@ digitalinout_result_t common_hal_digitalio_digitalinout_construct( } void common_hal_digitalio_digitalinout_never_reset( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { never_reset_pin_number(self->pin->number); } -bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t* self) { +bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t *self) { return self->pin == NULL; } -void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t* self) { +void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self) { if (common_hal_digitalio_digitalinout_deinited(self)) { return; } @@ -66,22 +66,22 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t* self } void common_hal_digitalio_digitalinout_switch_to_input( - digitalio_digitalinout_obj_t* self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { self->output = false; // This also sets direction to input. common_hal_digitalio_digitalinout_set_pull(self, pull); } digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( - digitalio_digitalinout_obj_t* self, bool value, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, bool value, + digitalio_drive_mode_t drive_mode) { const uint8_t pin = self->pin->number; gpio_disable_pulls(pin); // Turn on "strong" pin driving (more current available). hw_write_masked(&padsbank0_hw->io[pin], - PADS_BANK0_GPIO0_DRIVE_VALUE_12MA << PADS_BANK0_GPIO0_DRIVE_LSB, - PADS_BANK0_GPIO0_DRIVE_BITS); + PADS_BANK0_GPIO0_DRIVE_VALUE_12MA << PADS_BANK0_GPIO0_DRIVE_LSB, + PADS_BANK0_GPIO0_DRIVE_BITS); self->output = true; self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN; @@ -92,12 +92,12 @@ digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { return self->output ? DIRECTION_OUTPUT : DIRECTION_INPUT; } void common_hal_digitalio_digitalinout_set_value( - digitalio_digitalinout_obj_t* self, bool value) { + digitalio_digitalinout_obj_t *self, bool value) { const uint8_t pin = self->pin->number; if (self->open_drain && value) { // If true and open-drain, set the direction -before- setting @@ -115,13 +115,13 @@ void common_hal_digitalio_digitalinout_set_value( } bool common_hal_digitalio_digitalinout_get_value( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { return gpio_get(self->pin->number); } digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( - digitalio_digitalinout_obj_t* self, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, + digitalio_drive_mode_t drive_mode) { const uint8_t pin = self->pin->number; bool value = common_hal_digitalio_digitalinout_get_value(self); self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN; @@ -134,7 +134,7 @@ digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { if (self->open_drain) { return DRIVE_MODE_OPEN_DRAIN; } else { @@ -143,14 +143,14 @@ digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( } void common_hal_digitalio_digitalinout_set_pull( - digitalio_digitalinout_obj_t* self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { const uint8_t pin = self->pin->number; gpio_set_pulls(pin, pull == PULL_UP, pull == PULL_DOWN); gpio_set_dir(pin, GPIO_IN); } digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( - digitalio_digitalinout_obj_t* self) { + digitalio_digitalinout_obj_t *self) { uint32_t pin = self->pin->number; if (self->output) { mp_raise_AttributeError(translate("Cannot get pull while in output mode")); diff --git a/ports/raspberrypi/common-hal/digitalio/DigitalInOut.h b/ports/raspberrypi/common-hal/digitalio/DigitalInOut.h index 8b14bbad8..d656f607f 100644 --- a/ports/raspberrypi/common-hal/digitalio/DigitalInOut.h +++ b/ports/raspberrypi/common-hal/digitalio/DigitalInOut.h @@ -32,7 +32,7 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t * pin; + const mcu_pin_obj_t *pin; bool output; bool open_drain; } digitalio_digitalinout_obj_t; diff --git a/ports/raspberrypi/common-hal/displayio/ParallelBus.c b/ports/raspberrypi/common-hal/displayio/ParallelBus.c index 57b2ffc36..6060c4668 100644 --- a/ports/raspberrypi/common-hal/displayio/ParallelBus.c +++ b/ports/raspberrypi/common-hal/displayio/ParallelBus.c @@ -33,20 +33,20 @@ #include "shared-bindings/digitalio/DigitalInOut.h" #include "shared-bindings/microcontroller/__init__.h" -void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* self, - const mcu_pin_obj_t* data0, const mcu_pin_obj_t* command, const mcu_pin_obj_t* chip_select, - const mcu_pin_obj_t* write, const mcu_pin_obj_t* read, const mcu_pin_obj_t* reset) { +void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t *self, + const mcu_pin_obj_t *data0, const mcu_pin_obj_t *command, const mcu_pin_obj_t *chip_select, + const mcu_pin_obj_t *write, const mcu_pin_obj_t *read, const mcu_pin_obj_t *reset) { mp_raise_NotImplementedError(translate("ParallelBus not yet supported")); // TODO: Implement with PIO and DMA. } -void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) { +void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t *self) { } bool common_hal_displayio_parallelbus_reset(mp_obj_t obj) { - return false; + return false; } bool common_hal_displayio_parallelbus_bus_free(mp_obj_t obj) { @@ -59,7 +59,7 @@ bool common_hal_displayio_parallelbus_begin_transaction(mp_obj_t obj) { } void common_hal_displayio_parallelbus_send(mp_obj_t obj, display_byte_type_t byte_type, - display_chip_select_behavior_t chip_select, const uint8_t *data, uint32_t data_length) { + display_chip_select_behavior_t chip_select, const uint8_t *data, uint32_t data_length) { } diff --git a/ports/raspberrypi/common-hal/microcontroller/Pin.c b/ports/raspberrypi/common-hal/microcontroller/Pin.c index ca5cf5a04..271966c2f 100644 --- a/ports/raspberrypi/common-hal/microcontroller/Pin.c +++ b/ports/raspberrypi/common-hal/microcontroller/Pin.c @@ -74,8 +74,8 @@ void reset_pin_number(uint8_t pin_number) { // disabled and both buffers are as well. gpio_init(pin_number); hw_clear_bits(&padsbank0_hw->io[pin_number], PADS_BANK0_GPIO0_IE_BITS | - PADS_BANK0_GPIO0_PUE_BITS | - PADS_BANK0_GPIO0_PDE_BITS); + PADS_BANK0_GPIO0_PUE_BITS | + PADS_BANK0_GPIO0_PDE_BITS); hw_set_bits(&padsbank0_hw->io[pin_number], PADS_BANK0_GPIO0_OD_BITS); #ifdef MICROPY_HW_NEOPIXEL @@ -104,15 +104,15 @@ void reset_pin_number(uint8_t pin_number) { #endif } -void common_hal_never_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_never_reset_pin(const mcu_pin_obj_t *pin) { never_reset_pin_number(pin->number); } -void common_hal_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_reset_pin(const mcu_pin_obj_t *pin) { reset_pin_number(pin->number); } -void claim_pin(const mcu_pin_obj_t* pin) { +void claim_pin(const mcu_pin_obj_t *pin) { #ifdef MICROPY_HW_NEOPIXEL if (pin == MICROPY_HW_NEOPIXEL) { neopixel_in_use = true; @@ -144,7 +144,7 @@ bool pin_number_is_free(uint8_t pin_number) { (pad_state & PADS_BANK0_GPIO0_OD_BITS) != 0; } -bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t* pin) { +bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { #ifdef MICROPY_HW_NEOPIXEL if (pin == MICROPY_HW_NEOPIXEL) { return !neopixel_in_use; @@ -168,11 +168,11 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t* pin) { return pin_number_is_free(pin->number); } -uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t* pin) { +uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t *pin) { return pin->number; } -void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { +void common_hal_mcu_pin_claim(const mcu_pin_obj_t *pin) { return claim_pin(pin); } diff --git a/ports/raspberrypi/common-hal/microcontroller/Pin.h b/ports/raspberrypi/common-hal/microcontroller/Pin.h index 07c321185..7da3a2b88 100644 --- a/ports/raspberrypi/common-hal/microcontroller/Pin.h +++ b/ports/raspberrypi/common-hal/microcontroller/Pin.h @@ -47,7 +47,7 @@ void reset_all_pins(void); // need to store a full pointer. void reset_pin_number(uint8_t pin_number); void never_reset_pin_number(uint8_t pin_number); -void claim_pin(const mcu_pin_obj_t* pin); +void claim_pin(const mcu_pin_obj_t *pin); bool pin_number_is_free(uint8_t pin_number); #endif // MICROPY_INCLUDED_RASPBERRYPI_COMMON_HAL_MICROCONTROLLER_PIN_H diff --git a/ports/raspberrypi/common-hal/microcontroller/__init__.c b/ports/raspberrypi/common-hal/microcontroller/__init__.c index bfea8b2d9..6b5cb9b0d 100644 --- a/ports/raspberrypi/common-hal/microcontroller/__init__.c +++ b/ports/raspberrypi/common-hal/microcontroller/__init__.c @@ -129,7 +129,7 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .type = &nvm_bytearray_type, }, .len = CIRCUITPY_INTERNAL_NVM_SIZE, - .start_address = (uint8_t*) (CIRCUITPY_INTERNAL_NVM_START_ADDR) + .start_address = (uint8_t *)(CIRCUITPY_INTERNAL_NVM_START_ADDR) }; #endif diff --git a/ports/raspberrypi/common-hal/neopixel_write/__init__.c b/ports/raspberrypi/common-hal/neopixel_write/__init__.c index b57cb2bde..d1d872843 100644 --- a/ports/raspberrypi/common-hal/neopixel_write/__init__.c +++ b/ports/raspberrypi/common-hal/neopixel_write/__init__.c @@ -54,7 +54,7 @@ const uint16_t neopixel_program[] = { 0xa142 }; -void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, uint32_t num_bytes) { +void common_hal_neopixel_write(const digitalio_digitalinout_obj_t *digitalinout, uint8_t *pixels, uint32_t num_bytes) { // Set everything up. rp2pio_statemachine_obj_t state_machine; @@ -83,7 +83,8 @@ void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout, // Wait to make sure we don't append onto the last transmission. This should only be a tick or // two. - while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {} + while (port_get_raw_ticks(NULL) < next_start_raw_ticks) { + } common_hal_rp2pio_statemachine_write(&state_machine, pixels, num_bytes, 1 /* stride in bytes */); @@ -92,7 +93,7 @@ void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout, // Reset the pin and release it from the PIO gpio_init(digitalinout->pin->number); - common_hal_digitalio_digitalinout_switch_to_output((digitalio_digitalinout_obj_t*)digitalinout, false, DRIVE_MODE_PUSH_PULL); + common_hal_digitalio_digitalinout_switch_to_output((digitalio_digitalinout_obj_t *)digitalinout, false, DRIVE_MODE_PUSH_PULL); // Update the next start. next_start_raw_ticks = port_get_raw_ticks(NULL) + 1; diff --git a/ports/raspberrypi/common-hal/nvm/ByteArray.c b/ports/raspberrypi/common-hal/nvm/ByteArray.c index fdc2c6080..94d98d686 100644 --- a/ports/raspberrypi/common-hal/nvm/ByteArray.c +++ b/ports/raspberrypi/common-hal/nvm/ByteArray.c @@ -32,44 +32,44 @@ #include "src/rp2_common/hardware_flash/include/hardware/flash.h" extern uint32_t __flash_binary_start; -static const uint32_t flash_binary_start = (uint32_t) &__flash_binary_start; +static const uint32_t flash_binary_start = (uint32_t)&__flash_binary_start; #define RMV_OFFSET(addr) addr - flash_binary_start -uint32_t common_hal_nvm_bytearray_get_length(nvm_bytearray_obj_t* self) { +uint32_t common_hal_nvm_bytearray_get_length(nvm_bytearray_obj_t *self) { return self->len; } -static void write_page(uint32_t page_addr, uint32_t offset, uint32_t len, uint8_t* bytes) { +static void write_page(uint32_t page_addr, uint32_t offset, uint32_t len, uint8_t *bytes) { // Write a whole page to flash, buffering it first and then erasing and rewriting it // since we can only write a whole page at a time. if (offset == 0 && len == FLASH_PAGE_SIZE) { flash_range_program(RMV_OFFSET(page_addr), bytes, FLASH_PAGE_SIZE); } else { uint8_t buffer[FLASH_PAGE_SIZE]; - memcpy(buffer, (uint8_t*) page_addr, FLASH_PAGE_SIZE); + memcpy(buffer, (uint8_t *)page_addr, FLASH_PAGE_SIZE); memcpy(buffer + offset, bytes, len); flash_range_program(RMV_OFFSET(page_addr), buffer, FLASH_PAGE_SIZE); } } -static void erase_and_write_sector(uint32_t address, uint32_t len, uint8_t* bytes) { +static void erase_and_write_sector(uint32_t address, uint32_t len, uint8_t *bytes) { // Write a whole sector to flash, buffering it first and then erasing and rewriting it // since we can only erase a whole sector at a time. uint8_t buffer[FLASH_SECTOR_SIZE]; - memcpy(buffer, (uint8_t*) CIRCUITPY_INTERNAL_NVM_START_ADDR, FLASH_SECTOR_SIZE); + memcpy(buffer, (uint8_t *)CIRCUITPY_INTERNAL_NVM_START_ADDR, FLASH_SECTOR_SIZE); memcpy(buffer + address, bytes, len); flash_range_erase(RMV_OFFSET(CIRCUITPY_INTERNAL_NVM_START_ADDR), FLASH_SECTOR_SIZE); flash_range_program(RMV_OFFSET(CIRCUITPY_INTERNAL_NVM_START_ADDR), buffer, FLASH_SECTOR_SIZE); } -void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t* self, - uint32_t start_index, uint32_t len, uint8_t* values) { +void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t *self, + uint32_t start_index, uint32_t len, uint8_t *values) { memcpy(values, self->start_address + start_index, len); } -bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t* self, - uint32_t start_index, uint8_t* values, uint32_t len) { +bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, + uint32_t start_index, uint8_t *values, uint32_t len) { uint8_t values_in[len]; common_hal_nvm_bytearray_get_bytes(self, start_index, len, values_in); @@ -82,7 +82,7 @@ bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t* self, } if (all_ones) { - uint32_t address = (uint32_t) self->start_address + start_index; + uint32_t address = (uint32_t)self->start_address + start_index; uint32_t offset = address % FLASH_PAGE_SIZE; uint32_t page_addr = address - offset; diff --git a/ports/raspberrypi/common-hal/nvm/ByteArray.h b/ports/raspberrypi/common-hal/nvm/ByteArray.h index a2a904fea..4667e6b23 100644 --- a/ports/raspberrypi/common-hal/nvm/ByteArray.h +++ b/ports/raspberrypi/common-hal/nvm/ByteArray.h @@ -31,7 +31,7 @@ typedef struct { mp_obj_base_t base; - uint8_t * start_address; + uint8_t *start_address; uint32_t len; } nvm_bytearray_obj_t; diff --git a/ports/raspberrypi/common-hal/os/__init__.c b/ports/raspberrypi/common-hal/os/__init__.c index 0df7653d3..3352cef12 100644 --- a/ports/raspberrypi/common-hal/os/__init__.c +++ b/ports/raspberrypi/common-hal/os/__init__.c @@ -56,7 +56,7 @@ STATIC MP_DEFINE_ATTRTUPLE( (mp_obj_t)&os_uname_info_release_obj, (mp_obj_t)&os_uname_info_version_obj, (mp_obj_t)&os_uname_info_machine_obj -); + ); mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; @@ -82,10 +82,10 @@ static BYTE random_state[SHA256_BLOCK_SIZE]; static void seed_random_bits(BYTE out[SHA256_BLOCK_SIZE]) { CRYAL_SHA256_CTX context; sha256_init(&context); - for (int i=0; i<2*RANDOM_SAFETY_MARGIN; i++) { - for(int j=0; j<SHA256_BLOCK_SIZE; j++) { + for (int i = 0; i < 2 * RANDOM_SAFETY_MARGIN; i++) { + for (int j = 0; j < SHA256_BLOCK_SIZE; j++) { out[j] = rosc_hw->randombit & 1; - for(int k=0; k<8; k++) { + for (int k = 0; k < 8; k++) { out[j] = (out[j] << 1) ^ (rosc_hw->randombit & 1); } } @@ -104,12 +104,12 @@ static void get_random_bits(BYTE out[SHA256_BLOCK_SIZE]) { sha256_final(&context, out); } -bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) { +bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { #define ROSC_POWER_SAVE (1) // assume ROSC is not necessarily active all the time -#if ROSC_POWER_SAVE + #if ROSC_POWER_SAVE uint32_t old_rosc_ctrl = rosc_hw->ctrl; rosc_hw->ctrl = (old_rosc_ctrl & ~ROSC_CTRL_ENABLE_BITS) | (ROSC_CTRL_ENABLE_VALUE_ENABLE << 12); -#endif + #endif while (length) { size_t n = MIN(length, SHA256_BLOCK_SIZE); BYTE sha_buf[SHA256_BLOCK_SIZE]; @@ -118,8 +118,8 @@ bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) { buffer += n; length -= n; } -#if ROSC_POWER_SAVE + #if ROSC_POWER_SAVE rosc_hw->ctrl = old_rosc_ctrl; -#endif + #endif return true; } diff --git a/ports/raspberrypi/common-hal/pulseio/PulseIn.c b/ports/raspberrypi/common-hal/pulseio/PulseIn.c index e05b35536..278c0cd66 100644 --- a/ports/raspberrypi/common-hal/pulseio/PulseIn.c +++ b/ports/raspberrypi/common-hal/pulseio/PulseIn.c @@ -36,7 +36,7 @@ #include "bindings/rp2pio/StateMachine.h" #include "common-hal/pulseio/PulseIn.h" -pulseio_pulsein_obj_t* save_self; +pulseio_pulsein_obj_t *save_self; #define NO_PIN 0xff volatile bool last_level; @@ -48,10 +48,10 @@ uint16_t pulsein_program[] = { 0x4001, // 1: in pins, 1 }; -void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, - const mcu_pin_obj_t* pin, uint16_t maxlen, bool idle_state) { +void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t *self, + const mcu_pin_obj_t *pin, uint16_t maxlen, bool idle_state) { - self->buffer = (uint16_t *) m_malloc(maxlen * sizeof(uint16_t), false); + self->buffer = (uint16_t *)m_malloc(maxlen * sizeof(uint16_t), false); if (self->buffer == NULL) { mp_raise_msg_varg(&mp_type_MemoryError, translate("Failed to allocate RX buffer of %d bytes"), maxlen * sizeof(uint16_t)); } @@ -76,10 +76,10 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, NULL, 0, 1, 0, 1 << self->pin, false, true, - false, 8, false, // TX, unused - false, - true, 32, true, // RX auto-push every 32 bits - false); // claim pins + false, 8, false, // TX, unused + false, + true, 32, true, // RX auto-push every 32 bits + false); // claim pins pio_sm_set_enabled(state_machine.pio,state_machine.state_machine, false); self->state_machine.pio = state_machine.pio; self->state_machine.state_machine = state_machine.state_machine; @@ -96,79 +96,79 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, // exec a set pindirs to 0 for input pio_sm_exec(state_machine.pio,state_machine.state_machine,0xe080); - //exec the appropriate wait for pin - if (self->idle_state == true ) { - pio_sm_exec(self->state_machine.pio,self->state_machine.state_machine,0x2020); + // exec the appropriate wait for pin + if (self->idle_state == true) { + pio_sm_exec(self->state_machine.pio,self->state_machine.state_machine,0x2020); } else { - pio_sm_exec(self->state_machine.pio,self->state_machine.state_machine,0x20a0); + pio_sm_exec(self->state_machine.pio,self->state_machine.state_machine,0x20a0); } pio_sm_set_enabled(state_machine.pio, state_machine.state_machine, true); } -bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t *self) { return self->pin == NO_PIN; } -void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t *self) { if (common_hal_pulseio_pulsein_deinited(self)) { return; } pio_sm_set_enabled(self->state_machine.pio, self->state_machine.state_machine, false); - pio_sm_unclaim (self->state_machine.pio, self->state_machine.state_machine); + pio_sm_unclaim(self->state_machine.pio, self->state_machine.state_machine); m_free(self->buffer); self->pin = NO_PIN; } -void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t *self) { pio_sm_set_enabled(self->state_machine.pio, self->state_machine.state_machine, false); } void common_hal_pulseio_pulsein_interrupt() { - pulseio_pulsein_obj_t* self = save_self; + pulseio_pulsein_obj_t *self = save_self; uint32_t rxfifo = 0; rxfifo = pio_sm_get_blocking(self->state_machine.pio, self->state_machine.state_machine); // translate from fifo to buffer for (uint i = 0; i < 32; i++) { bool level = (rxfifo & (1 << i)) >> i; - if (level == last_level ) { - level_count ++; + if (level == last_level) { + level_count++; } else { - result = level_count; - last_level = level; - level_count = 1; - // ignore pulses that are too long and too short - if (result < 4000 && result > 10) { - self->buffer[buf_index] = result; - buf_index++; - self->len++; - } - } - } + result = level_count; + last_level = level; + level_count = 1; + // ignore pulses that are too long and too short + if (result < 4000 && result > 10) { + self->buffer[buf_index] = result; + buf_index++; + self->len++; + } + } + } // check for a pulse thats too long (4000 us) or maxlen reached, and reset - if (( level_count > 4000 ) || (buf_index >= self->maxlen)) { - pio_sm_set_enabled(self->state_machine.pio, self->state_machine.state_machine, false); - pio_sm_init(self->state_machine.pio, self->state_machine.state_machine, self->state_machine.offset, &self->state_machine.sm_config); - pio_sm_restart(self->state_machine.pio,self->state_machine.state_machine); - pio_sm_set_enabled(self->state_machine.pio, self->state_machine.state_machine, true); + if ((level_count > 4000) || (buf_index >= self->maxlen)) { + pio_sm_set_enabled(self->state_machine.pio, self->state_machine.state_machine, false); + pio_sm_init(self->state_machine.pio, self->state_machine.state_machine, self->state_machine.offset, &self->state_machine.sm_config); + pio_sm_restart(self->state_machine.pio,self->state_machine.state_machine); + pio_sm_set_enabled(self->state_machine.pio, self->state_machine.state_machine, true); } } -void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, - uint16_t trigger_duration) { +void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t *self, + uint16_t trigger_duration) { // exec a wait for the selected pin to change state - if (self->idle_state == true ) { - pio_sm_exec(self->state_machine.pio,self->state_machine.state_machine,0x2020); + if (self->idle_state == true) { + pio_sm_exec(self->state_machine.pio,self->state_machine.state_machine,0x2020); } else { - pio_sm_exec(self->state_machine.pio,self->state_machine.state_machine,0x20a0); + pio_sm_exec(self->state_machine.pio,self->state_machine.state_machine,0x20a0); } // Send the trigger pulse. if (trigger_duration > 0) { - gpio_set_function(self->pin ,GPIO_FUNC_SIO); + gpio_set_function(self->pin,GPIO_FUNC_SIO); gpio_set_dir(self->pin,true); gpio_put(self->pin, !self->idle_state); common_hal_mcu_delay_us((uint32_t)trigger_duration); - gpio_set_function(self->pin ,GPIO_FUNC_PIO0); + gpio_set_function(self->pin,GPIO_FUNC_PIO0); common_hal_mcu_delay_us(225); } @@ -177,12 +177,12 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, pio_sm_set_enabled(self->state_machine.pio, self->state_machine.state_machine, true); } -void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t *self) { self->start = 0; self->len = 0; } -uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t *self) { if (self->len == 0) { mp_raise_IndexError_varg(translate("pop from empty %q"), MP_QSTR_PulseIn); } @@ -190,28 +190,28 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { self->start = (self->start + 1) % self->maxlen; self->len--; // if we are empty reset buffer pointer and counters - if (self->len == 0 ) { - self->start = 0; - buf_index = 0; - level_count = 0; + if (self->len == 0) { + self->start = 0; + buf_index = 0; + level_count = 0; } return value; } -uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t *self) { return self->maxlen; } -uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t *self) { return self->len; } -bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t *self) { return true; } -uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, - int16_t index) { +uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t *self, + int16_t index) { if (index < 0) { index += self->len; } diff --git a/ports/raspberrypi/common-hal/pulseio/PulseIn.h b/ports/raspberrypi/common-hal/pulseio/PulseIn.h index c83a86fca..b68a2238d 100644 --- a/ports/raspberrypi/common-hal/pulseio/PulseIn.h +++ b/ports/raspberrypi/common-hal/pulseio/PulseIn.h @@ -36,7 +36,7 @@ typedef struct { mp_obj_base_t base; uint8_t pin; - uint16_t* buffer; + uint16_t *buffer; uint16_t maxlen; bool idle_state; volatile uint16_t start; diff --git a/ports/raspberrypi/common-hal/pulseio/PulseOut.c b/ports/raspberrypi/common-hal/pulseio/PulseOut.c index e284cd46a..c3536af04 100644 --- a/ports/raspberrypi/common-hal/pulseio/PulseOut.c +++ b/ports/raspberrypi/common-hal/pulseio/PulseOut.c @@ -58,12 +58,12 @@ void pulseout_reset() { refcount = 0; } -void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, - const pwmio_pwmout_obj_t* carrier, - const mcu_pin_obj_t* pin, - uint32_t frequency, - uint16_t duty_cycle) { - mp_raise_NotImplementedError(translate("Unsupported operation")); +void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self, + const pwmio_pwmout_obj_t *carrier, + const mcu_pin_obj_t *pin, + uint32_t frequency, + uint16_t duty_cycle) { + mp_raise_NotImplementedError(translate("Unsupported operation")); refcount++; @@ -71,11 +71,11 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, } -bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t* self) { +bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t *self) { return self->pin == NO_PIN; } -void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { +void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t *self) { if (common_hal_pulseio_pulseout_deinited(self)) { return; } @@ -85,7 +85,7 @@ void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { self->pin = NO_PIN; } -void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pulses, uint16_t length) { +void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pulses, uint16_t length) { pulse_buffer = pulses; pulse_index = 0; pulse_length = length; diff --git a/ports/raspberrypi/common-hal/pwmio/PWMOut.c b/ports/raspberrypi/common-hal/pwmio/PWMOut.c index fd85fbf55..9695a8fdf 100644 --- a/ports/raspberrypi/common-hal/pwmio/PWMOut.c +++ b/ports/raspberrypi/common-hal/pwmio/PWMOut.c @@ -154,11 +154,11 @@ pwmout_result_t pwmout_allocate(uint8_t slice, uint8_t channel, bool variable_fr return PWMOUT_OK; } -pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, - const mcu_pin_obj_t* pin, - uint16_t duty, - uint32_t frequency, - bool variable_frequency) { +pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, + const mcu_pin_obj_t *pin, + uint16_t duty, + uint32_t frequency, + bool variable_frequency) { self->pin = pin; self->variable_frequency = variable_frequency; self->duty_cycle = duty; @@ -195,7 +195,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, return PWMOUT_OK; } -bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) { return self->pin == NULL; } @@ -211,7 +211,7 @@ void pwmout_free(uint8_t slice, uint8_t channel) { } } -void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { +void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) { if (common_hal_pwmio_pwmout_deinited(self)) { return; } @@ -220,33 +220,33 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { self->pin = NULL; } -extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t* self, uint16_t duty) { +extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t duty) { self->duty_cycle = duty; // Do arithmetic in 32 bits to prevent overflow. uint16_t compare_count; if (duty == 65535) { // Ensure that 100% duty cycle is 100% full on and not rounded down, // but do MIN() to keep value in range, just in case. - compare_count = MIN(UINT16_MAX, (uint32_t) self->top + 1); + compare_count = MIN(UINT16_MAX, (uint32_t)self->top + 1); } else { - compare_count= ((uint32_t) duty * self->top + MAX_TOP / 2) / MAX_TOP; + compare_count = ((uint32_t)duty * self->top + MAX_TOP / 2) / MAX_TOP; } // compare_count is the CC register value, which should be TOP+1 for 100% duty cycle. pwm_set_chan_level(self->slice, self->channel, compare_count); } -uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) { +uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) { return self->duty_cycle; } -void pwmio_pwmout_set_top(pwmio_pwmout_obj_t* self, uint16_t top) { +void pwmio_pwmout_set_top(pwmio_pwmout_obj_t *self, uint16_t top) { self->actual_frequency = common_hal_mcu_processor_get_frequency() / top; self->top = top; pwm_set_clkdiv_int_frac(self->slice, 1, 0); pwm_set_wrap(self->slice, self->top); } -void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t frequency) { +void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self, uint32_t frequency) { if (frequency == 0 || frequency > (common_hal_mcu_processor_get_frequency() / 2)) { mp_raise_ValueError(translate("Invalid PWM frequency")); } @@ -258,7 +258,7 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t fr // Compute the divisor. It's an 8 bit integer and 4 bit fraction. Therefore, // we compute everything * 16 for the fractional part. // This is 1 << 12 because 4 bits are the * 16. - uint64_t frequency16 = ((uint64_t) clock_get_hz(clk_sys)) / (1 << 12); + uint64_t frequency16 = ((uint64_t)clock_get_hz(clk_sys)) / (1 << 12); uint64_t div16 = frequency16 / frequency; // Round the divisor to try and get closest to the target frequency. We could // also always round up and use TOP to get us closer. We may not need that though. @@ -283,10 +283,10 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t fr common_hal_pwmio_pwmout_set_duty_cycle(self, self->duty_cycle); } -uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) { +uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) { return self->actual_frequency; } -bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) { return self->variable_frequency; } diff --git a/ports/raspberrypi/common-hal/pwmio/PWMOut.h b/ports/raspberrypi/common-hal/pwmio/PWMOut.h index 41da81010..c7707762e 100644 --- a/ports/raspberrypi/common-hal/pwmio/PWMOut.h +++ b/ports/raspberrypi/common-hal/pwmio/PWMOut.h @@ -44,7 +44,7 @@ typedef struct { void pwmout_reset(void); // Private API for AudioPWMOut. -void pwmio_pwmout_set_top(pwmio_pwmout_obj_t* self, uint16_t top); +void pwmio_pwmout_set_top(pwmio_pwmout_obj_t *self, uint16_t top); // Private APIs for RGBMatrix enum pwmout_result_t pwmout_allocate(uint8_t slice, uint8_t channel, bool variable_frequency, uint32_t frequency); void pwmout_free(uint8_t slice, uint8_t channel); diff --git a/ports/raspberrypi/common-hal/rgbmatrix/RGBMatrix.c b/ports/raspberrypi/common-hal/rgbmatrix/RGBMatrix.c index 657c7f0a6..f150422e3 100644 --- a/ports/raspberrypi/common-hal/rgbmatrix/RGBMatrix.c +++ b/ports/raspberrypi/common-hal/rgbmatrix/RGBMatrix.c @@ -38,29 +38,29 @@ void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self) { // Choose a PWM channel based on the first RGB pin uint8_t slice = pwm_gpio_to_slice_num(self->rgb_pins[0]); uint8_t channel = pwm_gpio_to_channel(self->rgb_pins[0]); - int result = pwmout_allocate(slice, channel, true, 125000000/3); + int result = pwmout_allocate(slice, channel, true, 125000000 / 3); if (result == PWMOUT_OK) { // return value must be nonzero (but slice and channel can both be // zero), so set bit 16... pwmout_never_reset(slice, channel); - return (void*)(intptr_t)(slice | (channel << 8) | 0x10000); + return (void *)(intptr_t)(slice | (channel << 8) | 0x10000); } return NULL; } -void common_hal_rgbmatrix_timer_enable(void* ptr) { +void common_hal_rgbmatrix_timer_enable(void *ptr) { int8_t slice = ((intptr_t)ptr) & 0xff; pwm_set_enabled(slice, false); pwm_clear_irq(slice); pwm_set_enabled(slice, true); } -void common_hal_rgbmatrix_timer_disable(void* ptr) { +void common_hal_rgbmatrix_timer_disable(void *ptr) { int8_t slice = ((intptr_t)ptr) & 0xff; pwm_set_enabled(slice, false); } -void common_hal_rgbmatrix_timer_free(void* ptr) { +void common_hal_rgbmatrix_timer_free(void *ptr) { intptr_t value = (intptr_t)ptr; uint8_t slice = value & 0xff; uint8_t channel = value >> 8; diff --git a/ports/raspberrypi/common-hal/rgbmatrix/RGBMatrix.h b/ports/raspberrypi/common-hal/rgbmatrix/RGBMatrix.h index 2378cf173..d14cd9b08 100644 --- a/ports/raspberrypi/common-hal/rgbmatrix/RGBMatrix.h +++ b/ports/raspberrypi/common-hal/rgbmatrix/RGBMatrix.h @@ -30,8 +30,8 @@ #include "shared-module/rgbmatrix/RGBMatrix.h" void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self); -void common_hal_rgbmatrix_timer_enable(void*); -void common_hal_rgbmatrix_timer_disable(void*); -void common_hal_rgbmatrix_timer_free(void*); +void common_hal_rgbmatrix_timer_enable(void *); +void common_hal_rgbmatrix_timer_disable(void *); +void common_hal_rgbmatrix_timer_free(void *); #endif diff --git a/ports/raspberrypi/common-hal/rotaryio/IncrementalEncoder.c b/ports/raspberrypi/common-hal/rotaryio/IncrementalEncoder.c index b2225991d..30b3ac619 100644 --- a/ports/raspberrypi/common-hal/rotaryio/IncrementalEncoder.c +++ b/ports/raspberrypi/common-hal/rotaryio/IncrementalEncoder.c @@ -57,8 +57,8 @@ STATIC const uint16_t encoder_init[] = { STATIC void incrementalencoder_interrupt_handler(void *self_in); -void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencoder_obj_t* self, - const mcu_pin_obj_t* pin_a, const mcu_pin_obj_t* pin_b) { +void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencoder_obj_t *self, + const mcu_pin_obj_t *pin_a, const mcu_pin_obj_t *pin_b) { mp_obj_t pins[] = {MP_OBJ_FROM_PTR(pin_a), MP_OBJ_FROM_PTR(pin_b)}; if (!common_hal_rp2pio_pins_are_sequential(2, pins)) { mp_raise_RuntimeError(translate("Pins must be sequential")); @@ -93,28 +93,28 @@ void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencode common_hal_rp2pio_statemachine_set_interrupt_handler(&self->state_machine, incrementalencoder_interrupt_handler, self, PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS); } -bool common_hal_rotaryio_incrementalencoder_deinited(rotaryio_incrementalencoder_obj_t* self) { +bool common_hal_rotaryio_incrementalencoder_deinited(rotaryio_incrementalencoder_obj_t *self) { return common_hal_rp2pio_statemachine_deinited(&self->state_machine); } -void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_obj_t* self) { +void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_obj_t *self) { if (common_hal_rotaryio_incrementalencoder_deinited(self)) { return; } common_hal_rp2pio_statemachine_deinit(&self->state_machine); } -mp_int_t common_hal_rotaryio_incrementalencoder_get_position(rotaryio_incrementalencoder_obj_t* self) { +mp_int_t common_hal_rotaryio_incrementalencoder_get_position(rotaryio_incrementalencoder_obj_t *self) { return self->position; } -void common_hal_rotaryio_incrementalencoder_set_position(rotaryio_incrementalencoder_obj_t* self, - mp_int_t new_position) { +void common_hal_rotaryio_incrementalencoder_set_position(rotaryio_incrementalencoder_obj_t *self, + mp_int_t new_position) { self->position = new_position; } STATIC void incrementalencoder_interrupt_handler(void *self_in) { - rotaryio_incrementalencoder_obj_t* self = self_in; + rotaryio_incrementalencoder_obj_t *self = self_in; // This table also works for detent both at 11 and 00 // For 11 at detent: // Turning cw: 11->01->00->10->11 diff --git a/ports/raspberrypi/common-hal/rotaryio/IncrementalEncoder.h b/ports/raspberrypi/common-hal/rotaryio/IncrementalEncoder.h index ff5c874c8..83fe97d31 100644 --- a/ports/raspberrypi/common-hal/rotaryio/IncrementalEncoder.h +++ b/ports/raspberrypi/common-hal/rotaryio/IncrementalEncoder.h @@ -34,7 +34,7 @@ typedef struct { mp_obj_base_t base; rp2pio_statemachine_obj_t state_machine; - uint8_t last_state:4; // <old A><old B><new A><new B> - int8_t quarter_count:4; // count intermediate transitions between detents + uint8_t last_state : 4; // <old A><old B><new A><new B> + int8_t quarter_count : 4; // count intermediate transitions between detents mp_int_t position; } rotaryio_incrementalencoder_obj_t; diff --git a/ports/raspberrypi/common-hal/rp2pio/StateMachine.c b/ports/raspberrypi/common-hal/rp2pio/StateMachine.c index 56a7ab668..4e2886eed 100644 --- a/ports/raspberrypi/common-hal/rp2pio/StateMachine.c +++ b/ports/raspberrypi/common-hal/rp2pio/StateMachine.c @@ -53,16 +53,16 @@ STATIC uint32_t _current_pins[NUM_PIOS]; STATIC uint32_t _current_sm_pins[NUM_PIOS][NUM_PIO_STATE_MACHINES]; STATIC PIO pio_instances[2] = {pio0, pio1}; -typedef void (*interrupt_handler_type)(void*); +typedef void (*interrupt_handler_type)(void *); STATIC interrupt_handler_type _interrupt_handler[NUM_PIOS][NUM_PIO_STATE_MACHINES]; STATIC void *_interrupt_arg[NUM_PIOS][NUM_PIO_STATE_MACHINES]; STATIC void rp2pio_statemachine_interrupt_handler(void); static void rp2pio_statemachine_set_pull(uint32_t pull_pin_up, uint32_t pull_pin_down, uint32_t pins_we_use) { - for (int i=0; i<TOTAL_GPIO_COUNT; i++) { + for (int i = 0; i < TOTAL_GPIO_COUNT; i++) { bool used = pins_we_use & (1 << i); - if(used) { + if (used) { bool pull_up = pull_pin_up & (1 << i); bool pull_down = pull_pin_down & (1 << i); gpio_set_pulls(i, pull_up, pull_down); @@ -120,16 +120,16 @@ void reset_rp2pio_statemachine(void) { _reset_statemachine(pio, j, false); } } - for (uint8_t irq=PIO0_IRQ_0; irq <= PIO1_IRQ_1; irq++) { - irq_handler_t int_handler = irq_get_exclusive_handler(irq); - if (int_handler > 0) { - irq_set_enabled (irq, false); - irq_remove_handler(irq,int_handler); - } - } + for (uint8_t irq = PIO0_IRQ_0; irq <= PIO1_IRQ_1; irq++) { + irq_handler_t int_handler = irq_get_exclusive_handler(irq); + if (int_handler > 0) { + irq_set_enabled(irq, false); + irq_remove_handler(irq,int_handler); + } + } } -STATIC uint32_t _check_pins_free(const mcu_pin_obj_t * first_pin, uint8_t pin_count, bool exclusive_pin_use) { +STATIC uint32_t _check_pins_free(const mcu_pin_obj_t *first_pin, uint8_t pin_count, bool exclusive_pin_use) { uint32_t pins_we_use = 0; if (first_pin != NULL) { for (size_t i = 0; i < pin_count; i++) { @@ -137,7 +137,7 @@ STATIC uint32_t _check_pins_free(const mcu_pin_obj_t * first_pin, uint8_t pin_co if (pin_number >= TOTAL_GPIO_COUNT) { mp_raise_ValueError(translate("Pin count too large")); } - const mcu_pin_obj_t * pin = mcu_pin_global_dict_table[pin_number].value; + const mcu_pin_obj_t *pin = mcu_pin_global_dict_table[pin_number].value; if (exclusive_pin_use || _pin_reference_count[pin_number] == 0) { assert_pin_free(pin); } @@ -149,14 +149,14 @@ STATIC uint32_t _check_pins_free(const mcu_pin_obj_t * first_pin, uint8_t pin_co bool rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, - const uint16_t* program, size_t program_len, + const uint16_t *program, size_t program_len, size_t frequency, - const uint16_t* init, size_t init_len, - const mcu_pin_obj_t * first_out_pin, uint8_t out_pin_count, - const mcu_pin_obj_t * first_in_pin, uint8_t in_pin_count, + const uint16_t *init, size_t init_len, + const mcu_pin_obj_t *first_out_pin, uint8_t out_pin_count, + const mcu_pin_obj_t *first_in_pin, uint8_t in_pin_count, uint32_t pull_pin_up, uint32_t pull_pin_down, - const mcu_pin_obj_t * first_set_pin, uint8_t set_pin_count, - const mcu_pin_obj_t * first_sideset_pin, uint8_t sideset_pin_count, + const mcu_pin_obj_t *first_set_pin, uint8_t set_pin_count, + const mcu_pin_obj_t *first_sideset_pin, uint8_t sideset_pin_count, uint32_t initial_pin_state, uint32_t initial_pin_direction, uint32_t pins_we_use, bool tx_fifo, bool rx_fifo, bool auto_pull, uint8_t pull_threshold, bool out_shift_right, @@ -164,13 +164,13 @@ bool rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, bool auto_push, uint8_t push_threshold, bool in_shift_right, bool claim_pins) { // Create a program id that isn't the pointer so we can store it without storing the original object. - uint32_t program_id = ~((uint32_t) program); + uint32_t program_id = ~((uint32_t)program); // Next, find a PIO and state machine to use. size_t pio_index = NUM_PIOS; uint8_t program_offset = 32; pio_program_t program_struct = { - .instructions = (uint16_t*) program, + .instructions = (uint16_t *)program, .length = program_len, .origin = 0 }; @@ -242,7 +242,7 @@ bool rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, continue; } _pin_reference_count[pin_number]++; - const mcu_pin_obj_t * pin = mcu_pin_global_dict_table[pin_number].value; + const mcu_pin_obj_t *pin = mcu_pin_global_dict_table[pin_number].value; // Also claim the pin at the top level when we're the first to grab it. if (_pin_reference_count[pin_number] == 1) { if (claim_pins) { @@ -257,7 +257,7 @@ bool rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, if (frequency == 0) { frequency = clock_get_hz(clk_sys); } - uint64_t frequency256 = ((uint64_t) clock_get_hz(clk_sys)) * 256; + uint64_t frequency256 = ((uint64_t)clock_get_hz(clk_sys)) * 256; uint64_t div256 = frequency256 / frequency; if (frequency256 % div256 > 0) { div256 += 1; @@ -314,21 +314,21 @@ bool rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, return true; } -static uint32_t mask_and_rotate(const mcu_pin_obj_t* first_pin, uint32_t bit_count, uint32_t value) { +static uint32_t mask_and_rotate(const mcu_pin_obj_t *first_pin, uint32_t bit_count, uint32_t value) { value = value & ((1 << bit_count) - 1); uint32_t shift = first_pin->number; return value << shift | value >> (32 - shift); } void common_hal_rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, - const uint16_t* program, size_t program_len, + const uint16_t *program, size_t program_len, size_t frequency, - const uint16_t* init, size_t init_len, - const mcu_pin_obj_t * first_out_pin, uint8_t out_pin_count, uint32_t initial_out_pin_state, uint32_t initial_out_pin_direction, - const mcu_pin_obj_t * first_in_pin, uint8_t in_pin_count, + const uint16_t *init, size_t init_len, + const mcu_pin_obj_t *first_out_pin, uint8_t out_pin_count, uint32_t initial_out_pin_state, uint32_t initial_out_pin_direction, + const mcu_pin_obj_t *first_in_pin, uint8_t in_pin_count, uint32_t pull_pin_up, uint32_t pull_pin_down, - const mcu_pin_obj_t * first_set_pin, uint8_t set_pin_count, uint32_t initial_set_pin_state, uint32_t initial_set_pin_direction, - const mcu_pin_obj_t * first_sideset_pin, uint8_t sideset_pin_count, uint32_t initial_sideset_pin_state, uint32_t initial_sideset_pin_direction, + const mcu_pin_obj_t *first_set_pin, uint8_t set_pin_count, uint32_t initial_set_pin_state, uint32_t initial_set_pin_direction, + const mcu_pin_obj_t *first_sideset_pin, uint8_t sideset_pin_count, uint32_t initial_sideset_pin_state, uint32_t initial_sideset_pin_direction, bool exclusive_pin_use, bool auto_pull, uint8_t pull_threshold, bool out_shift_right, bool wait_for_txstall, @@ -453,7 +453,7 @@ void common_hal_rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, initial_set_pin_state = mask_and_rotate(first_set_pin, set_pin_count, initial_set_pin_state); initial_set_pin_direction = mask_and_rotate(first_set_pin, set_pin_count, initial_set_pin_direction); uint32_t set_out_overlap = mask_and_rotate(first_out_pin, out_pin_count, 0xffffffff) & - mask_and_rotate(first_set_pin, set_pin_count, 0xffffffff); + mask_and_rotate(first_set_pin, set_pin_count, 0xffffffff); // Check that OUT and SET settings agree because we don't have a way of picking one over the other. if ((initial_pin_state & set_out_overlap) != (initial_set_pin_state & set_out_overlap)) { mp_raise_ValueError(translate("Initial set pin state conflicts with initial out pin state")); @@ -517,15 +517,15 @@ void common_hal_rp2pio_statemachine_run(rp2pio_statemachine_obj_t *self, const u } } -uint32_t common_hal_rp2pio_statemachine_get_frequency(rp2pio_statemachine_obj_t* self) { +uint32_t common_hal_rp2pio_statemachine_get_frequency(rp2pio_statemachine_obj_t *self) { return self->actual_frequency; } -void common_hal_rp2pio_statemachine_set_frequency(rp2pio_statemachine_obj_t* self, uint32_t frequency) { +void common_hal_rp2pio_statemachine_set_frequency(rp2pio_statemachine_obj_t *self, uint32_t frequency) { if (frequency == 0) { frequency = clock_get_hz(clk_sys); } - uint64_t frequency256 = ((uint64_t) clock_get_hz(clk_sys)) * 256; + uint64_t frequency256 = ((uint64_t)clock_get_hz(clk_sys)) * 256; uint64_t div256 = frequency256 / frequency; if (frequency256 % div256 > 0) { div256 += 1; @@ -602,16 +602,16 @@ static bool _transfer(rp2pio_statemachine_obj_t *self, chan_rx = dma_claim_unused_channel(false); } } - volatile uint8_t* tx_destination = NULL; - const volatile uint8_t* rx_source = NULL; + volatile uint8_t *tx_destination = NULL; + const volatile uint8_t *rx_source = NULL; if (tx) { - tx_destination = (volatile uint8_t*) &self->pio->txf[self->state_machine]; + tx_destination = (volatile uint8_t *)&self->pio->txf[self->state_machine]; if (!self->out_shift_right) { tx_destination += 4 - out_stride_in_bytes; } } if (rx) { - rx_source = (const volatile uint8_t*) &self->pio->rxf[self->state_machine]; + rx_source = (const volatile uint8_t *)&self->pio->rxf[self->state_machine]; if (self->in_shift_right) { rx_source += 4 - in_stride_in_bytes; } @@ -686,20 +686,20 @@ static bool _transfer(rp2pio_statemachine_obj_t *self, if (out_stride_in_bytes == 1) { *tx_destination = *data_out; } else if (out_stride_in_bytes == 2) { - *((uint16_t*) tx_destination) = *((uint16_t*) data_out); + *((uint16_t *)tx_destination) = *((uint16_t *)data_out); } else if (out_stride_in_bytes == 4) { - *((uint32_t*) tx_destination) = *((uint32_t*) data_out); + *((uint32_t *)tx_destination) = *((uint32_t *)data_out); } data_out += out_stride_in_bytes; --tx_remaining; } while (rx_remaining && !pio_sm_is_rx_fifo_empty(self->pio, self->state_machine)) { if (in_stride_in_bytes == 1) { - *data_in = (uint8_t) *rx_source; + *data_in = (uint8_t)*rx_source; } else if (in_stride_in_bytes == 2) { - *((uint16_t*) data_in) = *((uint16_t*) rx_source); + *((uint16_t *)data_in) = *((uint16_t *)rx_source); } else if (in_stride_in_bytes == 4) { - *((uint32_t*) data_in) = *((uint32_t*) rx_source); + *((uint32_t *)data_in) = *((uint32_t *)rx_source); } data_in += in_stride_in_bytes; --rx_remaining; @@ -744,15 +744,15 @@ bool common_hal_rp2pio_statemachine_readinto(rp2pio_statemachine_obj_t *self, ui } bool common_hal_rp2pio_statemachine_write_readinto(rp2pio_statemachine_obj_t *self, - const uint8_t *data_out, size_t out_len, uint8_t out_stride_in_bytes, - uint8_t *data_in, size_t in_len, uint8_t in_stride_in_bytes) { + const uint8_t *data_out, size_t out_len, uint8_t out_stride_in_bytes, + uint8_t *data_in, size_t in_len, uint8_t in_stride_in_bytes) { if (!self->in || !self->out) { mp_raise_RuntimeError(translate("No in or out in program")); } return _transfer(self, data_out, out_len, out_stride_in_bytes, data_in, in_len, in_stride_in_bytes); } -bool common_hal_rp2pio_statemachine_get_rxstall(rp2pio_statemachine_obj_t* self) { +bool common_hal_rp2pio_statemachine_get_rxstall(rp2pio_statemachine_obj_t *self) { uint32_t stall_mask = 1 << (PIO_FDEBUG_RXSTALL_LSB + self->state_machine); return (self->pio->fdebug & stall_mask) != 0; } @@ -761,7 +761,7 @@ void common_hal_rp2pio_statemachine_clear_rxfifo(rp2pio_statemachine_obj_t *self uint8_t level = pio_sm_get_rx_fifo_level(self->pio, self->state_machine); uint32_t stall_mask = 1 << (PIO_FDEBUG_RXSTALL_LSB + self->state_machine); for (size_t i = 0; i < level; i++) { - (void) self->pio->rxf[self->state_machine]; + (void)self->pio->rxf[self->state_machine]; } self->pio->fdebug = stall_mask; } @@ -771,7 +771,7 @@ size_t common_hal_rp2pio_statemachine_get_in_waiting(rp2pio_statemachine_obj_t * return level; } -void common_hal_rp2pio_statemachine_set_interrupt_handler(rp2pio_statemachine_obj_t *self, void(*handler)(void*), void *arg, int mask) { +void common_hal_rp2pio_statemachine_set_interrupt_handler(rp2pio_statemachine_obj_t *self, void (*handler)(void *), void *arg, int mask) { uint8_t pio_index = pio_get_index(self->pio); uint8_t sm = self->state_machine; diff --git a/ports/raspberrypi/common-hal/rp2pio/StateMachine.h b/ports/raspberrypi/common-hal/rp2pio/StateMachine.h index 15bc2a346..38410a362 100644 --- a/ports/raspberrypi/common-hal/rp2pio/StateMachine.h +++ b/ports/raspberrypi/common-hal/rp2pio/StateMachine.h @@ -37,7 +37,7 @@ typedef struct { uint32_t pins; // Bitmask of what pins this state machine uses. int state_machine; PIO pio; - const uint16_t* init; + const uint16_t *init; size_t init_len; uint32_t initial_pin_state; uint32_t initial_pin_direction; @@ -59,14 +59,14 @@ void reset_rp2pio_statemachine(void); // Minimal internal version that only fails on pin error (not in use) or full PIO. bool rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self, - const uint16_t* program, size_t program_len, + const uint16_t *program, size_t program_len, size_t frequency, - const uint16_t* init, size_t init_len, - const mcu_pin_obj_t * first_out_pin, uint8_t out_pin_count, - const mcu_pin_obj_t * first_in_pin, uint8_t in_pin_count, + const uint16_t *init, size_t init_len, + const mcu_pin_obj_t *first_out_pin, uint8_t out_pin_count, + const mcu_pin_obj_t *first_in_pin, uint8_t in_pin_count, uint32_t pull_pin_up, uint32_t pull_pin_down, - const mcu_pin_obj_t * first_set_pin, uint8_t set_pin_count, - const mcu_pin_obj_t * first_sideset_pin, uint8_t sideset_pin_count, + const mcu_pin_obj_t *first_set_pin, uint8_t set_pin_count, + const mcu_pin_obj_t *first_sideset_pin, uint8_t sideset_pin_count, uint32_t initial_pin_state, uint32_t initial_pin_direction, uint32_t pins_we_use, bool tx_fifo, bool rx_fifo, bool auto_pull, uint8_t pull_threshold, bool out_shift_right, diff --git a/ports/raspberrypi/common-hal/rp2pio/__init__.c b/ports/raspberrypi/common-hal/rp2pio/__init__.c index 5ad52c751..ae4cb93d1 100644 --- a/ports/raspberrypi/common-hal/rp2pio/__init__.c +++ b/ports/raspberrypi/common-hal/rp2pio/__init__.c @@ -29,11 +29,11 @@ #include "bindings/rp2pio/__init__.h" bool common_hal_rp2pio_pins_are_sequential(size_t len, mp_obj_t *items) { - if(len == 0) { + if (len == 0) { return true; } mcu_pin_obj_t *last_pin = validate_obj_is_pin(items[0]); - for(int i=1; i<len; i++) { + for (int i = 1; i < len; i++) { mcu_pin_obj_t *pin = validate_obj_is_pin(items[i]); if (pin->number != last_pin->number + 1) { return false; diff --git a/ports/raspberrypi/common-hal/rtc/RTC.c b/ports/raspberrypi/common-hal/rtc/RTC.c index e6c5d8871..8647fc246 100644 --- a/ports/raspberrypi/common-hal/rtc/RTC.c +++ b/ports/raspberrypi/common-hal/rtc/RTC.c @@ -33,13 +33,13 @@ void common_hal_rtc_init(void) { datetime_t t = { - .year = 2020, - .month = 1, - .day = 1, - .dotw = 3, // 0 is Sunday, so 3 is Wednesday - .hour = 0, - .min = 0, - .sec = 0 + .year = 2020, + .month = 1, + .day = 1, + .dotw = 3, // 0 is Sunday, so 3 is Wednesday + .hour = 0, + .min = 0, + .sec = 0 }; // Start the RTC @@ -53,17 +53,17 @@ void common_hal_rtc_get_time(timeutils_struct_time_t *tm) { rtc_get_datetime(&t); tm->tm_year = t.year; - tm->tm_mon = t.month; + tm->tm_mon = t.month; tm->tm_mday = t.day; tm->tm_wday = t.dotw; tm->tm_hour = t.hour; - tm->tm_min = t.min; - tm->tm_sec = t.sec; + tm->tm_min = t.min; + tm->tm_sec = t.sec; if (tm->tm_wday == 0) { tm->tm_wday = 6; } else { - tm->tm_wday-=1; + tm->tm_wday -= 1; } } @@ -71,17 +71,17 @@ void common_hal_rtc_set_time(timeutils_struct_time_t *tm) { if (tm->tm_wday == 6) { tm->tm_wday = 0; } else { - tm->tm_wday+=1; + tm->tm_wday += 1; } datetime_t t = { - .year = tm->tm_year, - .month = tm->tm_mon, - .day = tm->tm_mday, - .dotw = tm->tm_wday, - .hour = tm->tm_hour, - .min = tm->tm_min, - .sec = tm->tm_sec + .year = tm->tm_year, + .month = tm->tm_mon, + .day = tm->tm_mday, + .dotw = tm->tm_wday, + .hour = tm->tm_hour, + .min = tm->tm_min, + .sec = tm->tm_sec }; rtc_set_datetime(&t); } diff --git a/ports/raspberrypi/common-hal/supervisor/Runtime.c b/ports/raspberrypi/common-hal/supervisor/Runtime.c index 974f26cec..f82765178 100755..100644 --- a/ports/raspberrypi/common-hal/supervisor/Runtime.c +++ b/ports/raspberrypi/common-hal/supervisor/Runtime.c @@ -29,9 +29,9 @@ #include "supervisor/serial.h" bool common_hal_supervisor_runtime_get_serial_connected(void) { - return (bool) serial_connected(); + return (bool)serial_connected(); } bool common_hal_supervisor_runtime_get_serial_bytes_available(void) { - return (bool) serial_bytes_available(); + return (bool)serial_bytes_available(); } diff --git a/ports/raspberrypi/common-hal/watchdog/WatchDogTimer.h b/ports/raspberrypi/common-hal/watchdog/WatchDogTimer.h index ec1e2f659..ce34f0b8a 100644 --- a/ports/raspberrypi/common-hal/watchdog/WatchDogTimer.h +++ b/ports/raspberrypi/common-hal/watchdog/WatchDogTimer.h @@ -32,9 +32,9 @@ #include "shared-bindings/watchdog/WatchDogTimer.h" struct _watchdog_watchdogtimer_obj_t { - mp_obj_base_t base; - mp_float_t timeout; - watchdog_watchdogmode_t mode; + mp_obj_base_t base; + mp_float_t timeout; + watchdog_watchdogmode_t mode; }; // This needs to be called in order to disable the watchdog diff --git a/ports/raspberrypi/fatfs_port.c b/ports/raspberrypi/fatfs_port.c index c65a73a42..e6eee2049 100644 --- a/ports/raspberrypi/fatfs_port.c +++ b/ports/raspberrypi/fatfs_port.c @@ -35,14 +35,14 @@ #endif DWORD get_fattime(void) { -#if CIRCUITPY_RTC + #if CIRCUITPY_RTC timeutils_struct_time_t tm; common_hal_rtc_get_time(&tm); return ((tm.tm_year - 1980) << 25) | (tm.tm_mon << 21) | (tm.tm_mday << 16) | - (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); -#else + (tm.tm_hour << 11) | (tm.tm_min << 5) | (tm.tm_sec >> 1); + #else return ((2016 - 1980) << 25) | ((9) << 21) | ((1) << 16) | ((16) << 11) | ((43) << 5) | (35 / 2); -#endif + #endif } diff --git a/ports/raspberrypi/mpconfigport.h b/ports/raspberrypi/mpconfigport.h index dba008a94..0259ffd02 100644 --- a/ports/raspberrypi/mpconfigport.h +++ b/ports/raspberrypi/mpconfigport.h @@ -31,10 +31,10 @@ #define MICROPY_PY_SYS_PLATFORM "RP2040" -#define CIRCUITPY_INTERNAL_NVM_SIZE (4*1024) +#define CIRCUITPY_INTERNAL_NVM_SIZE (4 * 1024) #define CIRCUITPY_INTERNAL_NVM_START_ADDR (0x100FF000) -#define CIRCUITPY_DEFAULT_STACK_SIZE (24*1024) +#define CIRCUITPY_DEFAULT_STACK_SIZE (24 * 1024) #define MICROPY_USE_INTERNAL_PRINTF (1) diff --git a/ports/raspberrypi/mphalport.h b/ports/raspberrypi/mphalport.h index 8d2d7d51a..6d4753438 100644 --- a/ports/raspberrypi/mphalport.h +++ b/ports/raspberrypi/mphalport.h @@ -34,7 +34,7 @@ #include "supervisor/shared/tick.h" // Global millisecond tick count (driven by SysTick interrupt). -#define mp_hal_ticks_ms() ((mp_uint_t) supervisor_ticks_ms32()) +#define mp_hal_ticks_ms() ((mp_uint_t)supervisor_ticks_ms32()) // Number of bytes in receive buffer extern volatile uint8_t usb_rx_count; diff --git a/ports/raspberrypi/peripherals/pins.c b/ports/raspberrypi/peripherals/pins.c index a2a7b85bd..1b5fe91ca 100644 --- a/ports/raspberrypi/peripherals/pins.c +++ b/ports/raspberrypi/peripherals/pins.c @@ -30,10 +30,10 @@ // This macro is used to simplify pin definition in boards/<board>/pins.c #define PIN(p_number) \ -const mcu_pin_obj_t pin_GPIO## p_number = { \ - { &mcu_pin_type }, \ - .number = p_number \ -} + const mcu_pin_obj_t pin_GPIO##p_number = { \ + { &mcu_pin_type }, \ + .number = p_number \ + } PIN(0); PIN(1); diff --git a/ports/raspberrypi/supervisor/internal_flash.c b/ports/raspberrypi/supervisor/internal_flash.c index e8ee5cf1a..81f26967e 100644 --- a/ports/raspberrypi/supervisor/internal_flash.c +++ b/ports/raspberrypi/supervisor/internal_flash.c @@ -85,8 +85,8 @@ void port_internal_flash_flush(void) { mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) { memcpy(dest, - (void*)(XIP_BASE + RESERVED_FLASH + block * FILESYSTEM_BLOCK_SIZE), - num_blocks * FILESYSTEM_BLOCK_SIZE); + (void *)(XIP_BASE + RESERVED_FLASH + block * FILESYSTEM_BLOCK_SIZE), + num_blocks * FILESYSTEM_BLOCK_SIZE); return 0; } @@ -100,18 +100,18 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32 if (_cache_lba != block_address) { memcpy(_cache, - (void*)(XIP_BASE + RESERVED_FLASH + sector_offset), - SECTOR_SIZE); + (void *)(XIP_BASE + RESERVED_FLASH + sector_offset), + SECTOR_SIZE); _cache_lba = sector_offset; } for (uint8_t b = block_offset; b < blocks_per_sector; b++) { // Stop copying after the last block. if (block >= num_blocks) { - break; + break; } memcpy(_cache + b * FILESYSTEM_BLOCK_SIZE, - src + block * FILESYSTEM_BLOCK_SIZE, - FILESYSTEM_BLOCK_SIZE); + src + block * FILESYSTEM_BLOCK_SIZE, + FILESYSTEM_BLOCK_SIZE); block++; } // Make sure we don't have an interrupt while we do flash operations. diff --git a/ports/raspberrypi/supervisor/port.c b/ports/raspberrypi/supervisor/port.c index 501a0c5ce..cf4c05f81 100644 --- a/ports/raspberrypi/supervisor/port.c +++ b/ports/raspberrypi/supervisor/port.c @@ -128,7 +128,8 @@ void reset_port(void) { void reset_to_bootloader(void) { reset_usb_boot(0, 0); - while (true) {} + while (true) { + } } void reset_cpu(void) { @@ -172,7 +173,7 @@ uint32_t port_get_saved_word(void) { return watchdog_hw->scratch[0]; } -uint64_t port_get_raw_ticks(uint8_t* subticks) { +uint64_t port_get_raw_ticks(uint8_t *subticks) { uint64_t microseconds = time_us_64(); return 1024 * (microseconds / 1000000) + (microseconds % 1000000) / 977; } @@ -210,16 +211,15 @@ void port_idle_until_interrupt(void) { /** * \brief Default interrupt handler for unused IRQs. */ -__attribute__((used)) void HardFault_Handler(void) -{ -#ifdef ENABLE_MICRO_TRACE_BUFFER +__attribute__((used)) void HardFault_Handler(void) { + #ifdef ENABLE_MICRO_TRACE_BUFFER // Turn off the micro trace buffer so we don't fill it up in the infinite // loop below. REG_MTB_MASTER = 0x00000000 + 6; -#endif + #endif reset_into_safe_mode(HARD_CRASH); while (true) { - asm("nop;"); + asm ("nop;"); } } diff --git a/ports/stm/background.c b/ports/stm/background.c index d83a0ccec..dbf5ccee2 100644 --- a/ports/stm/background.c +++ b/ports/stm/background.c @@ -33,6 +33,9 @@ #include "shared-module/displayio/__init__.h" #endif -void port_background_task(void) {} -void port_start_background_task(void) {} -void port_finish_background_task(void) {} +void port_background_task(void) { +} +void port_start_background_task(void) { +} +void port_finish_background_task(void) { +} diff --git a/ports/stm/boards/espruino_pico/mpconfigboard.h b/ports/stm/boards/espruino_pico/mpconfigboard.h index fe4ed6ca2..9a3f93864 100644 --- a/ports/stm/boards/espruino_pico/mpconfigboard.h +++ b/ports/stm/boards/espruino_pico/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Espruino Pico" #define MICROPY_HW_MCU_NAME "STM32F401xD" diff --git a/ports/stm/boards/espruino_wifi/board.c b/ports/stm/boards/espruino_wifi/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/espruino_wifi/board.c +++ b/ports/stm/boards/espruino_wifi/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/espruino_wifi/mpconfigboard.h b/ports/stm/boards/espruino_wifi/mpconfigboard.h index b7f38f69b..b857650d6 100644 --- a/ports/stm/boards/espruino_wifi/mpconfigboard.h +++ b/ports/stm/boards/espruino_wifi/mpconfigboard.h @@ -24,13 +24,13 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Espruino Wifi" #define MICROPY_HW_MCU_NAME "STM32F411xE" -#define FLASH_SIZE (0x80000) //512K -#define FLASH_PAGE_SIZE (0x4000) //16K +#define FLASH_SIZE (0x80000) // 512K +#define FLASH_PAGE_SIZE (0x4000) // 16K #define HSE_VALUE ((uint32_t)8000000) #define LSE_VALUE ((uint32_t)32768) diff --git a/ports/stm/boards/espruino_wifi/pins.c b/ports/stm/boards/espruino_wifi/pins.c index 8800317d5..2d36ae8b9 100644 --- a/ports/stm/boards/espruino_wifi/pins.c +++ b/ports/stm/boards/espruino_wifi/pins.c @@ -1,39 +1,39 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - //P1 - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_B1), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_B10), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_B13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_B14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_B15), MP_ROM_PTR(&pin_PB15) }, + // P1 + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_B1), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_B10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_B13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_B14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_B15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_B0), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_B9), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_B8), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_B7), MP_ROM_PTR(&pin_PB07) }, - { MP_ROM_QSTR(MP_QSTR_B6), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_B5), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_B3), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_B0), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_B9), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_B8), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_B7), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_B6), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_B5), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_B3), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_BTN), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_BTN), MP_ROM_PTR(&pin_PC13) }, - { MP_ROM_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_ESP_GPIO0), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_ESP_CHPD), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_ESP_GPIO13), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_ESP_GPIO0), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_ESP_CHPD), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_ESP_GPIO13), MP_ROM_PTR(&pin_PA15) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h index e69be6cf9..8558edd8c 100644 --- a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h +++ b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "Adafruit Feather STM32F405 Express" #define MICROPY_HW_MCU_NAME "STM32F405RG" @@ -46,7 +46,7 @@ // Bootloader only #ifdef UF2_BOOTLOADER_ENABLED - #define BOARD_VTOR_DEFER (1) //Leave VTOR relocation to bootloader + #define BOARD_VTOR_DEFER (1) // Leave VTOR relocation to bootloader #endif #define DEFAULT_I2C_BUS_SCL (&pin_PB06) diff --git a/ports/stm/boards/meowbit_v121/board.c b/ports/stm/boards/meowbit_v121/board.c index 4a8014a3a..44d125462 100644 --- a/ports/stm/boards/meowbit_v121/board.c +++ b/ports/stm/boards/meowbit_v121/board.c @@ -41,36 +41,36 @@ displayio_fourwire_obj_t board_display_obj; uint8_t display_init_sequence[] = { 0x01, 0 | DELAY, 150, // SWRESET - 0x11, 0 | DELAY, 255, // SLPOUT - 0xb1, 3, 0x01, 0x2C, 0x2D, // _FRMCTR1 - 0xb2, 3, 0x01, 0x2C, 0x2D, // - 0xb3, 6, 0x01, 0x2C, 0x2D, 0x01, 0x2C, 0x2D, - 0xb4, 1, 0x07, // _INVCTR line inversion - 0xc0, 3, 0xa2, 0x02, 0x84, // _PWCTR1 GVDD = 4.7V, 1.0uA - 0xc1, 1, 0xc5, // _PWCTR2 VGH=14.7V, VGL=-7.35V - 0xc2, 2, 0x0a, 0x00, // _PWCTR3 Opamp current small, Boost frequency - 0xc3, 2, 0x8a, 0x2a, - 0xc4, 2, 0x8a, 0xee, - 0xc5, 1, 0x0e, // _VMCTR1 VCOMH = 4V, VOML = -1.1V - 0x20, 0, // _INVOFF //MISMATCh 0x2a vs 0x20 - 0x36, 1, 0x18, // _MADCTL bottom to top refresh - // 1 clk cycle nonoverlap, 2 cycle gate rise, 3 sycle osc equalie, - // fix on VTL - 0x3a, 1, 0x05, // COLMOD - 16bit color - 0xe0, 0x10, 0x02, 0x1c, 0x07, 0x12, - 0x37, 0x32, 0x29, 0x2d, - 0x29, 0x25, 0x2B, 0x39, - 0x00, 0x01, 0x03, 0x10, // _GMCTRP1 Gamma - 0xe1, 0x10, 0x03, 0x1d, 0x07, 0x06, - 0x2E, 0x2C, 0x29, 0x2D, - 0x2E, 0x2E, 0x37, 0x3F, - 0x00, 0x00, 0x02, 0x10, // _GMCTRN1 - 0x13, 0 | DELAY, 10, // _NORON - 0x29, 0 | DELAY, 100, // _DISPON + 0x11, 0 | DELAY, 255, // SLPOUT + 0xb1, 3, 0x01, 0x2C, 0x2D, // _FRMCTR1 + 0xb2, 3, 0x01, 0x2C, 0x2D, // + 0xb3, 6, 0x01, 0x2C, 0x2D, 0x01, 0x2C, 0x2D, + 0xb4, 1, 0x07, // _INVCTR line inversion + 0xc0, 3, 0xa2, 0x02, 0x84, // _PWCTR1 GVDD = 4.7V, 1.0uA + 0xc1, 1, 0xc5, // _PWCTR2 VGH=14.7V, VGL=-7.35V + 0xc2, 2, 0x0a, 0x00, // _PWCTR3 Opamp current small, Boost frequency + 0xc3, 2, 0x8a, 0x2a, + 0xc4, 2, 0x8a, 0xee, + 0xc5, 1, 0x0e, // _VMCTR1 VCOMH = 4V, VOML = -1.1V + 0x20, 0, // _INVOFF //MISMATCh 0x2a vs 0x20 + 0x36, 1, 0x18, // _MADCTL bottom to top refresh + // 1 clk cycle nonoverlap, 2 cycle gate rise, 3 sycle osc equalie, + // fix on VTL + 0x3a, 1, 0x05, // COLMOD - 16bit color + 0xe0, 0x10, 0x02, 0x1c, 0x07, 0x12, + 0x37, 0x32, 0x29, 0x2d, + 0x29, 0x25, 0x2B, 0x39, + 0x00, 0x01, 0x03, 0x10, // _GMCTRP1 Gamma + 0xe1, 0x10, 0x03, 0x1d, 0x07, 0x06, + 0x2E, 0x2C, 0x29, 0x2D, + 0x2E, 0x2E, 0x37, 0x3F, + 0x00, 0x00, 0x02, 0x10, // _GMCTRN1 + 0x13, 0 | DELAY, 10, // _NORON + 0x29, 0 | DELAY, 100, // _DISPON }; void board_init(void) { - displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus; + displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus; bus->base.type = &displayio_fourwire_type; busio_spi_obj_t *internal_spi = &supervisor_flash_spi_bus; common_hal_displayio_fourwire_construct(bus, @@ -82,7 +82,7 @@ void board_init(void) { 0, // Polarity 0); // Phase - displayio_display_obj_t* display = &displays[0].display; + displayio_display_obj_t *display = &displays[0].display; display->base.type = &displayio_display_type; common_hal_displayio_display_construct(display, bus, diff --git a/ports/stm/boards/meowbit_v121/mpconfigboard.h b/ports/stm/boards/meowbit_v121/mpconfigboard.h index be9f2a75f..780743794 100644 --- a/ports/stm/boards/meowbit_v121/mpconfigboard.h +++ b/ports/stm/boards/meowbit_v121/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "MEOWBIT" #define MICROPY_HW_MCU_NAME "STM32F401xE" @@ -39,7 +39,7 @@ #define BOARD_HAS_LOW_SPEED_CRYSTAL (0) #define BOARD_NO_VBUS_SENSE (1) -#define BOARD_VTOR_DEFER (1) //Leave VTOR relocation to bootloader +#define BOARD_VTOR_DEFER (1) // Leave VTOR relocation to bootloader #define BOARD_USE_INTERNAL_SPI // On-board flash diff --git a/ports/stm/boards/meowbit_v121/pins.c b/ports/stm/boards/meowbit_v121/pins.c index af896fad8..d11341145 100644 --- a/ports/stm/boards/meowbit_v121/pins.c +++ b/ports/stm/boards/meowbit_v121/pins.c @@ -55,7 +55,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_P9), MP_ROM_PTR(&pin_PC06) }, { MP_ROM_QSTR(MP_QSTR_P8), MP_ROM_PTR(&pin_PA04) }, { MP_ROM_QSTR(MP_QSTR_P1), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_PA10) }, //in use by USB + { MP_ROM_QSTR(MP_QSTR_P7), MP_ROM_PTR(&pin_PA10) }, // in use by USB { MP_ROM_QSTR(MP_QSTR_P6), MP_ROM_PTR(&pin_PC07) }, { MP_ROM_QSTR(MP_QSTR_P5), MP_ROM_PTR(&pin_PB05) }, { MP_ROM_QSTR(MP_QSTR_P4), MP_ROM_PTR(&pin_PC01) }, diff --git a/ports/stm/boards/nucleo_f746zg/board.c b/ports/stm/boards/nucleo_f746zg/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/nucleo_f746zg/board.c +++ b/ports/stm/boards/nucleo_f746zg/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/nucleo_f746zg/mpconfigboard.h b/ports/stm/boards/nucleo_f746zg/mpconfigboard.h index e2b54335a..ef8f84ceb 100644 --- a/ports/stm/boards/nucleo_f746zg/mpconfigboard.h +++ b/ports/stm/boards/nucleo_f746zg/mpconfigboard.h @@ -25,7 +25,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "NUCLEO STM32F746" #define MICROPY_HW_MCU_NAME "STM32F746" diff --git a/ports/stm/boards/nucleo_f746zg/pins.c b/ports/stm/boards/nucleo_f746zg/pins.c index 7c6a075e2..251ce4bcb 100644 --- a/ports/stm/boards/nucleo_f746zg/pins.c +++ b/ports/stm/boards/nucleo_f746zg/pins.c @@ -1,74 +1,74 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { -{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) }, -{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) }, -{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, -{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) }, -{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) }, -{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) }, -{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, -{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, -{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) }, -{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) }, -{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) }, -{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) }, -{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) }, -{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) }, -{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) }, -{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) }, -{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) }, -{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, -{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, -{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, -{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, -{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, -{ MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) }, -{ MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) }, -{ MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) }, -{ MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) }, -{ MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) }, -{ MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) }, -{ MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) }, -{ MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) }, -{ MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) }, -{ MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) }, -{ MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) }, -{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) }, -{ MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) }, -{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) }, -{ MP_ROM_QSTR(MP_QSTR_TP1), MP_ROM_PTR(&pin_PH02) }, -{ MP_ROM_QSTR(MP_QSTR_TP2), MP_ROM_PTR(&pin_PI08) }, -{ MP_ROM_QSTR(MP_QSTR_TP3), MP_ROM_PTR(&pin_PH15) }, -{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_PD06) }, -{ MP_ROM_QSTR(MP_QSTR_AUDIO_SDA), MP_ROM_PTR(&pin_PH08) }, -{ MP_ROM_QSTR(MP_QSTR_AUDIO_SCL), MP_ROM_PTR(&pin_PH07) }, -{ MP_ROM_QSTR(MP_QSTR_EXT_SDA), MP_ROM_PTR(&pin_PB09) }, -{ MP_ROM_QSTR(MP_QSTR_EXT_SCL), MP_ROM_PTR(&pin_PB08) }, -{ MP_ROM_QSTR(MP_QSTR_EXT_RST), MP_ROM_PTR(&pin_PG03) }, -{ MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PC13) }, -{ MP_ROM_QSTR(MP_QSTR_LCD_BL_CTRL), MP_ROM_PTR(&pin_PK03) }, -{ MP_ROM_QSTR(MP_QSTR_LCD_INT), MP_ROM_PTR(&pin_PI13) }, -{ MP_ROM_QSTR(MP_QSTR_LCD_SDA), MP_ROM_PTR(&pin_PH08) }, -{ MP_ROM_QSTR(MP_QSTR_LCD_SCL), MP_ROM_PTR(&pin_PH07) }, -{ MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PD05) }, -{ MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PD04) }, -{ MP_ROM_QSTR(MP_QSTR_OTG_HS_OVER_CURRENT), MP_ROM_PTR(&pin_PE03) }, -{ MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) }, -{ MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, -{ MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, -{ MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_TP1), MP_ROM_PTR(&pin_PH02) }, + { MP_ROM_QSTR(MP_QSTR_TP2), MP_ROM_PTR(&pin_PI08) }, + { MP_ROM_QSTR(MP_QSTR_TP3), MP_ROM_PTR(&pin_PH15) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_SDA), MP_ROM_PTR(&pin_PH08) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_SCL), MP_ROM_PTR(&pin_PH07) }, + { MP_ROM_QSTR(MP_QSTR_EXT_SDA), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_EXT_SCL), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_EXT_RST), MP_ROM_PTR(&pin_PG03) }, + { MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_LCD_BL_CTRL), MP_ROM_PTR(&pin_PK03) }, + { MP_ROM_QSTR(MP_QSTR_LCD_INT), MP_ROM_PTR(&pin_PI13) }, + { MP_ROM_QSTR(MP_QSTR_LCD_SDA), MP_ROM_PTR(&pin_PH08) }, + { MP_ROM_QSTR(MP_QSTR_LCD_SCL), MP_ROM_PTR(&pin_PH07) }, + { MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_OTG_HS_OVER_CURRENT), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, // As we use these for the debug_console, we won't enable them here. // { MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PD08) }, // { MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PD09) }, -{ MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) }, -{ MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) }, -{ MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) }, -{ MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) }, -{ MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PG14) }, -{ MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PG09) }, -{ MP_ROM_QSTR(MP_QSTR_SPI_B_NSS), MP_ROM_PTR(&pin_PA04) }, -{ MP_ROM_QSTR(MP_QSTR_SPI_B_SCK), MP_ROM_PTR(&pin_PB03) }, -{ MP_ROM_QSTR(MP_QSTR_SPI_B_MOSI), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PG14) }, + { MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PG09) }, + { MP_ROM_QSTR(MP_QSTR_SPI_B_NSS), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_SPI_B_SCK), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_SPI_B_MOSI), MP_ROM_PTR(&pin_PB05) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/nucleo_f767zi/board.c b/ports/stm/boards/nucleo_f767zi/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/nucleo_f767zi/board.c +++ b/ports/stm/boards/nucleo_f767zi/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h index 327651923..8db104e87 100644 --- a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h +++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "NUCLEO STM32F767" #define MICROPY_HW_MCU_NAME "STM32F767" diff --git a/ports/stm/boards/nucleo_f767zi/pins.c b/ports/stm/boards/nucleo_f767zi/pins.c index 9ecc38f01..0373fc4fb 100644 --- a/ports/stm/boards/nucleo_f767zi/pins.c +++ b/ports/stm/boards/nucleo_f767zi/pins.c @@ -1,142 +1,142 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { -{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) }, -{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) }, -{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, -{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) }, -{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) }, -{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) }, -{ MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) }, -{ MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PC02) }, -{ MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PF04) }, -{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, -{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, -{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) }, -{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) }, -{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) }, -{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) }, -{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) }, -{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) }, -{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) }, -{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) }, -{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) }, -{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, -{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, -{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, -{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, -{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, -{ MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) }, -{ MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) }, -{ MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) }, -{ MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) }, -{ MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) }, -{ MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) }, -{ MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) }, -{ MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) }, -{ MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) }, -{ MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) }, -{ MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_PB06) }, -{ MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_PB02) }, -{ MP_ROM_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_PD13) }, -{ MP_ROM_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_PD12) }, -{ MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PD11) }, -{ MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PE02) }, -{ MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA00) }, -{ MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PB00) }, -{ MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_PE00) }, -{ MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_PB11) }, -{ MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_PB10) }, -{ MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_PE15) }, -{ MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_PE14) }, -{ MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_PE12) }, -{ MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_PE10) }, -{ MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_PE07) }, -{ MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_PE08) }, -{ MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_PC08) }, -{ MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_PC09) }, -{ MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_PC10) }, -{ MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_PC11) }, -{ MP_ROM_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_PC12) }, -{ MP_ROM_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_PD02) }, -{ MP_ROM_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_PG02) }, -{ MP_ROM_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_PG03) }, -{ MP_ROM_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_PD07) }, -{ MP_ROM_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_PD06) }, -{ MP_ROM_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_PD05) }, -{ MP_ROM_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_PD04) }, -{ MP_ROM_QSTR(MP_QSTR_D55), MP_ROM_PTR(&pin_PD03) }, -{ MP_ROM_QSTR(MP_QSTR_D56), MP_ROM_PTR(&pin_PE02) }, -{ MP_ROM_QSTR(MP_QSTR_D57), MP_ROM_PTR(&pin_PE04) }, -{ MP_ROM_QSTR(MP_QSTR_D58), MP_ROM_PTR(&pin_PE05) }, -{ MP_ROM_QSTR(MP_QSTR_D59), MP_ROM_PTR(&pin_PE06) }, -{ MP_ROM_QSTR(MP_QSTR_D60), MP_ROM_PTR(&pin_PE03) }, -{ MP_ROM_QSTR(MP_QSTR_D61), MP_ROM_PTR(&pin_PF08) }, -{ MP_ROM_QSTR(MP_QSTR_D62), MP_ROM_PTR(&pin_PF07) }, -{ MP_ROM_QSTR(MP_QSTR_D63), MP_ROM_PTR(&pin_PF09) }, -{ MP_ROM_QSTR(MP_QSTR_D64), MP_ROM_PTR(&pin_PG01) }, -{ MP_ROM_QSTR(MP_QSTR_D65), MP_ROM_PTR(&pin_PG00) }, -{ MP_ROM_QSTR(MP_QSTR_D66), MP_ROM_PTR(&pin_PD01) }, -{ MP_ROM_QSTR(MP_QSTR_D67), MP_ROM_PTR(&pin_PD00) }, -{ MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) }, -{ MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) }, -{ MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) }, -{ MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PA07) }, -{ MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) }, -{ MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) }, -{ MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) }, -{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) }, -{ MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) }, -{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) }, -{ MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) }, -{ MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) }, -{ MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) }, -{ MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) }, -{ MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) }, -{ MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) }, -{ MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PG02) }, -{ MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PG06) }, -{ MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PG07) }, -{ MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) }, -{ MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, -{ MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, -{ MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, -{ MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) }, -{ MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) }, -{ MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) }, -{ MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) }, -{ MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PD08) }, -{ MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PD09) }, -{ MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PD08) }, -{ MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PD09) }, -{ MP_ROM_QSTR(MP_QSTR_UART5_TX), MP_ROM_PTR(&pin_PB06) }, -{ MP_ROM_QSTR(MP_QSTR_UART5_RX), MP_ROM_PTR(&pin_PB12) }, -{ MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PC06) }, -{ MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PC07) }, -{ MP_ROM_QSTR(MP_QSTR_UART7_TX), MP_ROM_PTR(&pin_PF07) }, -{ MP_ROM_QSTR(MP_QSTR_UART7_RX), MP_ROM_PTR(&pin_PF06) }, -{ MP_ROM_QSTR(MP_QSTR_UART8_TX), MP_ROM_PTR(&pin_PE01) }, -{ MP_ROM_QSTR(MP_QSTR_UART8_RX), MP_ROM_PTR(&pin_PE00) }, -{ MP_ROM_QSTR(MP_QSTR_SPI3_NSS), MP_ROM_PTR(&pin_PA04) }, -{ MP_ROM_QSTR(MP_QSTR_SPI3_SCK), MP_ROM_PTR(&pin_PB03) }, -{ MP_ROM_QSTR(MP_QSTR_SPI3_MISO), MP_ROM_PTR(&pin_PB04) }, -{ MP_ROM_QSTR(MP_QSTR_SPI3_MOSI), MP_ROM_PTR(&pin_PB05) }, -{ MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) }, -{ MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PB08) }, -{ MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PF00) }, -{ MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PF01) }, -{ MP_ROM_QSTR(MP_QSTR_I2C4_SCL), MP_ROM_PTR(&pin_PF14) }, -{ MP_ROM_QSTR(MP_QSTR_I2C4_SDA), MP_ROM_PTR(&pin_PF15) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PB13) }, -{ MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA13) }, -{ MP_ROM_QSTR(MP_QSTR_SWDCLK), MP_ROM_PTR(&pin_PA14) } + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PF04) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_PG03) }, + { MP_ROM_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_D55), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_D56), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_D57), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_D58), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_D59), MP_ROM_PTR(&pin_PE06) }, + { MP_ROM_QSTR(MP_QSTR_D60), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_D61), MP_ROM_PTR(&pin_PF08) }, + { MP_ROM_QSTR(MP_QSTR_D62), MP_ROM_PTR(&pin_PF07) }, + { MP_ROM_QSTR(MP_QSTR_D63), MP_ROM_PTR(&pin_PF09) }, + { MP_ROM_QSTR(MP_QSTR_D64), MP_ROM_PTR(&pin_PG01) }, + { MP_ROM_QSTR(MP_QSTR_D65), MP_ROM_PTR(&pin_PG00) }, + { MP_ROM_QSTR(MP_QSTR_D66), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_D67), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) }, + { MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) }, + { MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) }, + { MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PG06) }, + { MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PG07) }, + { MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_UART5_TX), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_UART5_RX), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_UART7_TX), MP_ROM_PTR(&pin_PF07) }, + { MP_ROM_QSTR(MP_QSTR_UART7_RX), MP_ROM_PTR(&pin_PF06) }, + { MP_ROM_QSTR(MP_QSTR_UART8_TX), MP_ROM_PTR(&pin_PE01) }, + { MP_ROM_QSTR(MP_QSTR_UART8_RX), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_SPI3_NSS), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_SPI3_SCK), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_SPI3_MISO), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_SPI3_MOSI), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PF00) }, + { MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PF01) }, + { MP_ROM_QSTR(MP_QSTR_I2C4_SCL), MP_ROM_PTR(&pin_PF14) }, + { MP_ROM_QSTR(MP_QSTR_I2C4_SDA), MP_ROM_PTR(&pin_PF15) }, + { MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_SWDCLK), MP_ROM_PTR(&pin_PA14) } }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/nucleo_h743zi_2/board.c b/ports/stm/boards/nucleo_h743zi_2/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/nucleo_h743zi_2/board.c +++ b/ports/stm/boards/nucleo_h743zi_2/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h index 2ac986701..36c55a26a 100644 --- a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h +++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "NUCLEO STM32H743" #define MICROPY_HW_MCU_NAME "STM32H743" diff --git a/ports/stm/boards/openmv_h7/board.c b/ports/stm/boards/openmv_h7/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/openmv_h7/board.c +++ b/ports/stm/boards/openmv_h7/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/openmv_h7/mpconfigboard.h b/ports/stm/boards/openmv_h7/mpconfigboard.h index 77ae235ec..ffeba28f6 100644 --- a/ports/stm/boards/openmv_h7/mpconfigboard.h +++ b/ports/stm/boards/openmv_h7/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "OPENMV-H7 R1" #define MICROPY_HW_MCU_NAME "STM32H743" diff --git a/ports/stm/boards/pyb_nano_v2/mpconfigboard.h b/ports/stm/boards/pyb_nano_v2/mpconfigboard.h index 7c1ab31e3..0960687d1 100644 --- a/ports/stm/boards/pyb_nano_v2/mpconfigboard.h +++ b/ports/stm/boards/pyb_nano_v2/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "PYB LR Nano V2" #define MICROPY_HW_MCU_NAME "STM32F411CE" diff --git a/ports/stm/boards/pyboard_v11/board.c b/ports/stm/boards/pyboard_v11/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/pyboard_v11/board.c +++ b/ports/stm/boards/pyboard_v11/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/pyboard_v11/mpconfigboard.h b/ports/stm/boards/pyboard_v11/mpconfigboard.h index 50a90c52b..1ce89a59f 100644 --- a/ports/stm/boards/pyboard_v11/mpconfigboard.h +++ b/ports/stm/boards/pyboard_v11/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "PyboardV1_1" #define MICROPY_HW_MCU_NAME "STM32F405RG" diff --git a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h index 435133954..400e7bb2c 100644 --- a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h +++ b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "stm32f411ce-blackpill" #define MICROPY_HW_MCU_NAME "STM32F411CE" diff --git a/ports/stm/boards/stm32f411ce_blackpill/pins.c b/ports/stm/boards/stm32f411ce_blackpill/pins.c index 16946b8be..7e25ad042 100644 --- a/ports/stm/boards/stm32f411ce_blackpill/pins.c +++ b/ports/stm/boards/stm32f411ce_blackpill/pins.c @@ -6,10 +6,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_B14), MP_ROM_PTR(&pin_PB14) }, { MP_ROM_QSTR(MP_QSTR_B15), MP_ROM_PTR(&pin_PB15) }, { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, //USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, // USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, // USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, // USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, // USB (shouldn't be used) { MP_ROM_QSTR(MP_QSTR_A15), MP_ROM_PTR(&pin_PA15) }, { MP_ROM_QSTR(MP_QSTR_B3), MP_ROM_PTR(&pin_PB03) }, { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) }, diff --git a/ports/stm/boards/stm32f411ce_blackpill_with_flash/mpconfigboard.h b/ports/stm/boards/stm32f411ce_blackpill_with_flash/mpconfigboard.h index 65e224e47..a7d56209c 100644 --- a/ports/stm/boards/stm32f411ce_blackpill_with_flash/mpconfigboard.h +++ b/ports/stm/boards/stm32f411ce_blackpill_with_flash/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "stm32f411ce-blackpill-with-flash" #define MICROPY_HW_MCU_NAME "STM32F411CE" diff --git a/ports/stm/boards/stm32f411ce_blackpill_with_flash/pins.c b/ports/stm/boards/stm32f411ce_blackpill_with_flash/pins.c index 16946b8be..7e25ad042 100644 --- a/ports/stm/boards/stm32f411ce_blackpill_with_flash/pins.c +++ b/ports/stm/boards/stm32f411ce_blackpill_with_flash/pins.c @@ -6,10 +6,10 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_B14), MP_ROM_PTR(&pin_PB14) }, { MP_ROM_QSTR(MP_QSTR_B15), MP_ROM_PTR(&pin_PB15) }, { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, //USB (shouldn't be used) - { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, //USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) }, // USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) }, // USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PA11) }, // USB (shouldn't be used) + { MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_PA12) }, // USB (shouldn't be used) { MP_ROM_QSTR(MP_QSTR_A15), MP_ROM_PTR(&pin_PA15) }, { MP_ROM_QSTR(MP_QSTR_B3), MP_ROM_PTR(&pin_PB03) }, { MP_ROM_QSTR(MP_QSTR_B4), MP_ROM_PTR(&pin_PB04) }, diff --git a/ports/stm/boards/stm32f411ve_discovery/board.c b/ports/stm/boards/stm32f411ve_discovery/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/stm32f411ve_discovery/board.c +++ b/ports/stm/boards/stm32f411ve_discovery/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h index 0be43f4fb..ec6e54833 100644 --- a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.h @@ -24,13 +24,13 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "STM32F411E_DISCO" #define MICROPY_HW_MCU_NAME "STM32F411xE" -#define FLASH_SIZE (0x80000) //512K -#define FLASH_PAGE_SIZE (0x4000) //16K +#define FLASH_SIZE (0x80000) // 512K +#define FLASH_PAGE_SIZE (0x4000) // 16K #define HSE_VALUE ((uint32_t)8000000) #define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal diff --git a/ports/stm/boards/stm32f411ve_discovery/pins.c b/ports/stm/boards/stm32f411ve_discovery/pins.c index 673c412d5..626151334 100644 --- a/ports/stm/boards/stm32f411ve_discovery/pins.c +++ b/ports/stm/boards/stm32f411ve_discovery/pins.c @@ -1,106 +1,106 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - //P1 - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, - { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, - { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, - { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, - { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, - { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, - { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, - { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, - { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, - { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, - { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, - { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, - { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, - //P2 - { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) }, - { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) }, - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, - { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, - { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, - { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, - { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, - { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, - { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, - { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, - { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, - { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - //ST LED names - { MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) }, - //more useful LED names - { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) }, - //AnalogIO names - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) }, - //actual LED names - { MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) }, + // P1 + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + // P2 + { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) }, + { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) }, + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + // ST LED names + { MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) }, + // more useful LED names + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) }, + // AnalogIO names + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) }, + // actual LED names + { MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/stm32f412zg_discovery/board.c b/ports/stm/boards/stm32f412zg_discovery/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/stm32f412zg_discovery/board.c +++ b/ports/stm/boards/stm32f412zg_discovery/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h index 6b9ab6467..3ae0761c7 100644 --- a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "STM32F412G_DISCO" #define MICROPY_HW_MCU_NAME "STM32F412xGS" diff --git a/ports/stm/boards/stm32f412zg_discovery/pins.c b/ports/stm/boards/stm32f412zg_discovery/pins.c index ab90b0455..84e646ca7 100644 --- a/ports/stm/boards/stm32f412zg_discovery/pins.c +++ b/ports/stm/boards/stm32f412zg_discovery/pins.c @@ -1,94 +1,94 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, - { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, - { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, - { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, - { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, - { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, - { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, - { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, - { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, - { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PG10) }, - { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PG11) }, - { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PF03) }, - { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PF10) }, - { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG12) }, - { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PF04) }, - { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG13) }, - { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, //USART6 TX - { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, //USART6 RX - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, - { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC05) }, //alt PB09, see F401ZG-DISCO manual - { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB00) }, //alt PB10, see F401ZG-DISCO manual - { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PE01) }, - { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, + { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, + { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, + { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, + { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, + { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, + { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, + { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PG10) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PG11) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PF10) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG12) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PF04) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG13) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, // USART6 TX + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, // USART6 RX + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC05) }, // alt PB09, see F401ZG-DISCO manual + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB00) }, // alt PB10, see F401ZG-DISCO manual + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PE01) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/stm32f4_discovery/board.c b/ports/stm/boards/stm32f4_discovery/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/stm32f4_discovery/board.c +++ b/ports/stm/boards/stm32f4_discovery/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/stm32f4_discovery/mpconfigboard.h b/ports/stm/boards/stm32f4_discovery/mpconfigboard.h index 44ee07378..410c21ec9 100644 --- a/ports/stm/boards/stm32f4_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f4_discovery/mpconfigboard.h @@ -24,7 +24,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "STM32F4_DISCO" #define MICROPY_HW_MCU_NAME "STM32F407VG" diff --git a/ports/stm/boards/stm32f4_discovery/pins.c b/ports/stm/boards/stm32f4_discovery/pins.c index 712932145..ee53fbd78 100644 --- a/ports/stm/boards/stm32f4_discovery/pins.c +++ b/ports/stm/boards/stm32f4_discovery/pins.c @@ -1,107 +1,107 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { - //P1 - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, - { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, - { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, - { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, - { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, - { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, - { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, - { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, - { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, - { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, // Differs from F411 - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, - { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, - { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, - { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, - { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, - //P2 - { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) }, - { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) }, - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, - { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, - { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, - { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, - { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, - { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, - { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, - { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, - { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, - { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - //ST LED names - { MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) }, - //more useful LED names - { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) }, - //AnalogIO names - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) }, - //actual LED names - { MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) }, + // P1 + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, // Differs from F411 + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + // P2 + { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) }, + { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) }, + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + // ST LED names + { MP_ROM_QSTR(MP_QSTR_LD3), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_LD4), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_LD5), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_LD6), MP_ROM_PTR(&pin_PD15) }, + // more useful LED names + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_LED4), MP_ROM_PTR(&pin_PD15) }, + // AnalogIO names + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA05) }, + // actual LED names + { MP_ROM_QSTR(MP_QSTR_LED_ORANGE), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_LED_GREEN), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_LED_RED), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_LED_BLUE), MP_ROM_PTR(&pin_PD15) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/stm32f746g_discovery/board.c b/ports/stm/boards/stm32f746g_discovery/board.c index db2c72727..68bf157b6 100644 --- a/ports/stm/boards/stm32f746g_discovery/board.c +++ b/ports/stm/boards/stm32f746g_discovery/board.c @@ -49,7 +49,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h index 769990a98..afcefe0ce 100644 --- a/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h +++ b/ports/stm/boards/stm32f746g_discovery/mpconfigboard.h @@ -25,7 +25,7 @@ * THE SOFTWARE. */ -//Micropython setup +// Micropython setup #define MICROPY_HW_BOARD_NAME "ST STM32F746G Discovery" #define MICROPY_HW_MCU_NAME "STM32F746" diff --git a/ports/stm/boards/stm32f746g_discovery/pins.c b/ports/stm/boards/stm32f746g_discovery/pins.c index a859c8d19..bd9c1dcb1 100644 --- a/ports/stm/boards/stm32f746g_discovery/pins.c +++ b/ports/stm/boards/stm32f746g_discovery/pins.c @@ -1,110 +1,110 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_module_globals_table[] = { -{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, -{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PF10) }, -{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PF09) }, -{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF08) }, -{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF07) }, -{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF06) }, -{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PC07) }, -{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PC06) }, -{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG06) }, -{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PB04) }, -{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG07) }, -{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA08) }, -{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PH06) }, -{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PI03) }, -{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PI02) }, -{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA15) }, -{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PI00) }, -{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB15) }, -{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PB14) }, -{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PI01) }, -{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, -{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, -{ MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PI01) }, -{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PI11) }, -{ MP_ROM_QSTR(MP_QSTR_TP1), MP_ROM_PTR(&pin_PH02) }, -{ MP_ROM_QSTR(MP_QSTR_TP2), MP_ROM_PTR(&pin_PI08) }, -{ MP_ROM_QSTR(MP_QSTR_TP3), MP_ROM_PTR(&pin_PH15) }, -{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_PD06) }, -{ MP_ROM_QSTR(MP_QSTR_AUDIO_SDA), MP_ROM_PTR(&pin_PH08) }, -{ MP_ROM_QSTR(MP_QSTR_AUDIO_SCL), MP_ROM_PTR(&pin_PH07) }, -{ MP_ROM_QSTR(MP_QSTR_EXT_SDA), MP_ROM_PTR(&pin_PB09) }, -{ MP_ROM_QSTR(MP_QSTR_EXT_SCL), MP_ROM_PTR(&pin_PB08) }, -{ MP_ROM_QSTR(MP_QSTR_EXT_RST), MP_ROM_PTR(&pin_PG03) }, -{ MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) }, -{ MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) }, -{ MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) }, -{ MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) }, -{ MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) }, -{ MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) }, -{ MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PC13) }, -{ MP_ROM_QSTR(MP_QSTR_LCD_BL_CTRL), MP_ROM_PTR(&pin_PK03) }, -{ MP_ROM_QSTR(MP_QSTR_LCD_INT), MP_ROM_PTR(&pin_PI13) }, -{ MP_ROM_QSTR(MP_QSTR_LCD_SDA), MP_ROM_PTR(&pin_PH08) }, -{ MP_ROM_QSTR(MP_QSTR_LCD_SCL), MP_ROM_PTR(&pin_PH07) }, -{ MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PD05) }, -{ MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PD04) }, -{ MP_ROM_QSTR(MP_QSTR_OTG_HS_OVER_CURRENT), MP_ROM_PTR(&pin_PE03) }, -{ MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PJ12) }, -{ MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, -{ MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, -{ MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, -{ MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PA09) }, -{ MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PB07) }, -{ MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_PB13) }, -{ MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_PB12) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXER), MP_ROM_PTR(&pin_PG02) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) }, -{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PG14) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDCKE0), MP_ROM_PTR(&pin_PC03) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDNE0), MP_ROM_PTR(&pin_PH03) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDCLK), MP_ROM_PTR(&pin_PG08) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDNCAS), MP_ROM_PTR(&pin_PG15) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDNRAS), MP_ROM_PTR(&pin_PF11) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_SDNWE), MP_ROM_PTR(&pin_PH05) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_BA0), MP_ROM_PTR(&pin_PG04) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_BA1), MP_ROM_PTR(&pin_PG05) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_NBL0), MP_ROM_PTR(&pin_PE00) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_NBL1), MP_ROM_PTR(&pin_PE01) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A0), MP_ROM_PTR(&pin_PF00) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A1), MP_ROM_PTR(&pin_PF01) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A2), MP_ROM_PTR(&pin_PF02) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A3), MP_ROM_PTR(&pin_PF03) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A4), MP_ROM_PTR(&pin_PF04) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A5), MP_ROM_PTR(&pin_PF05) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A6), MP_ROM_PTR(&pin_PF12) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A7), MP_ROM_PTR(&pin_PF13) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A8), MP_ROM_PTR(&pin_PF14) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A9), MP_ROM_PTR(&pin_PF15) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A10), MP_ROM_PTR(&pin_PG00) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_A11), MP_ROM_PTR(&pin_PG01) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D0), MP_ROM_PTR(&pin_PD14) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D1), MP_ROM_PTR(&pin_PD15) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D2), MP_ROM_PTR(&pin_PD00) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D3), MP_ROM_PTR(&pin_PD01) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D4), MP_ROM_PTR(&pin_PE07) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D5), MP_ROM_PTR(&pin_PE08) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D6), MP_ROM_PTR(&pin_PE09) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D7), MP_ROM_PTR(&pin_PE10) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D8), MP_ROM_PTR(&pin_PE11) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D9), MP_ROM_PTR(&pin_PE12) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D10), MP_ROM_PTR(&pin_PE13) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D11), MP_ROM_PTR(&pin_PE14) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D12), MP_ROM_PTR(&pin_PE15) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D13), MP_ROM_PTR(&pin_PD08) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D14), MP_ROM_PTR(&pin_PD09) }, -{ MP_ROM_QSTR(MP_QSTR_SDRAM_D15), MP_ROM_PTR(&pin_PD10) }, -{ MP_ROM_QSTR(MP_QSTR_I2C3_SDA), MP_ROM_PTR(&pin_PH08) }, -{ MP_ROM_QSTR(MP_QSTR_I2C3_SCL), MP_ROM_PTR(&pin_PH07) }, + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PF10) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PF09) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF08) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF07) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF06) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG06) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PG07) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PH06) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PI03) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PI02) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PI00) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PI01) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PI01) }, + { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PI11) }, + { MP_ROM_QSTR(MP_QSTR_TP1), MP_ROM_PTR(&pin_PH02) }, + { MP_ROM_QSTR(MP_QSTR_TP2), MP_ROM_PTR(&pin_PI08) }, + { MP_ROM_QSTR(MP_QSTR_TP3), MP_ROM_PTR(&pin_PH15) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_SDA), MP_ROM_PTR(&pin_PH08) }, + { MP_ROM_QSTR(MP_QSTR_AUDIO_SCL), MP_ROM_PTR(&pin_PH07) }, + { MP_ROM_QSTR(MP_QSTR_EXT_SDA), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_EXT_SCL), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_EXT_RST), MP_ROM_PTR(&pin_PG03) }, + { MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_LCD_BL_CTRL), MP_ROM_PTR(&pin_PK03) }, + { MP_ROM_QSTR(MP_QSTR_LCD_INT), MP_ROM_PTR(&pin_PI13) }, + { MP_ROM_QSTR(MP_QSTR_LCD_SDA), MP_ROM_PTR(&pin_PH08) }, + { MP_ROM_QSTR(MP_QSTR_LCD_SCL), MP_ROM_PTR(&pin_PH07) }, + { MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_OTG_HS_OVER_CURRENT), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PJ12) }, + { MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXER), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PG14) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_SDCKE0), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_SDNE0), MP_ROM_PTR(&pin_PH03) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_SDCLK), MP_ROM_PTR(&pin_PG08) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_SDNCAS), MP_ROM_PTR(&pin_PG15) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_SDNRAS), MP_ROM_PTR(&pin_PF11) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_SDNWE), MP_ROM_PTR(&pin_PH05) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_BA0), MP_ROM_PTR(&pin_PG04) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_BA1), MP_ROM_PTR(&pin_PG05) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_NBL0), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_NBL1), MP_ROM_PTR(&pin_PE01) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A0), MP_ROM_PTR(&pin_PF00) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A1), MP_ROM_PTR(&pin_PF01) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A2), MP_ROM_PTR(&pin_PF02) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A3), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A4), MP_ROM_PTR(&pin_PF04) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A5), MP_ROM_PTR(&pin_PF05) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A6), MP_ROM_PTR(&pin_PF12) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A7), MP_ROM_PTR(&pin_PF13) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A8), MP_ROM_PTR(&pin_PF14) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A9), MP_ROM_PTR(&pin_PF15) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A10), MP_ROM_PTR(&pin_PG00) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_A11), MP_ROM_PTR(&pin_PG01) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D0), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D1), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D2), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D3), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D4), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D5), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D6), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D7), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D8), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D9), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D10), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D11), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D12), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D13), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D14), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_SDRAM_D15), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_I2C3_SDA), MP_ROM_PTR(&pin_PH08) }, + { MP_ROM_QSTR(MP_QSTR_I2C3_SCL), MP_ROM_PTR(&pin_PH07) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/system_stm32f4xx.c b/ports/stm/boards/system_stm32f4xx.c index d8c745dbb..39dc72705 100644 --- a/ports/stm/boards/system_stm32f4xx.c +++ b/ports/stm/boards/system_stm32f4xx.c @@ -89,11 +89,11 @@ #include "stm32f4xx.h" #include "py/mpconfig.h" -#if !defined (HSE_VALUE) +#if !defined(HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ -#if !defined (HSI_VALUE) +#if !defined(HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -115,15 +115,15 @@ /************************* Miscellaneous Configuration ************************/ /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ - || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) \ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ STM32F412Zx || STM32F412Vx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* #define DATA_IN_ExtSDRAM */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ STM32F479xx */ @@ -150,7 +150,7 @@ /** @addtogroup STM32F4xx_System_Private_Variables * @{ */ - /* This variable is updated in three ways: +/* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency @@ -160,7 +160,7 @@ */ uint32_t SystemCoreClock = 16000000; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} */ @@ -169,8 +169,8 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; * @{ */ -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); +#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM) +static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /** @@ -188,43 +188,42 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; * @param None * @retval None */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; +void SystemInit(void) { + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; - /* Disable all interrupts */ - RCC->CIR = 0x00000000; + /* Disable all interrupts */ + RCC->CIR = 0x00000000; -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - /* Configure the Vector Table location add offset address ------------------*/ -#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already - #ifdef VECT_TAB_SRAM + /* Configure the Vector Table location add offset address ------------------*/ + #if !(BOARD_VTOR_DEFER) // only set VTOR if the bootloader hasn't already + #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ - #else + #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ - #endif -#endif + #endif + #endif } /** @@ -263,57 +262,53 @@ void SystemInit(void) * @param None * @retval None */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; +void SystemCoreClockUpdate(void) { + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } else { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2; + SystemCoreClock = pllvco / pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; } -#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \ + || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. @@ -322,161 +317,157 @@ void SystemCoreClockUpdate(void) * @param None * @retval None */ -void SystemInit_ExtMemCtl(void) -{ - __IO uint32_t tmp = 0x00; - - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; - - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ - RCC->AHB1ENR |= 0x000001F8; - - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x00CCC0CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00CC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0xCCCCCCCC; - GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0xCCCCCCCC; - GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0x00C0CC00; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x00000000; - - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00000000; +void SystemInit_ExtMemCtl(void) { + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; /*-- FMC Configuration -------------------------------------------------------*/ - /* Enable the FMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - - FMC_Bank5_6->SDCR[0] = 0x000019E4; - FMC_Bank5_6->SDTR[0] = 0x01115351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Auto refresh command */ - FMC_Bank5_6->SDCMR = 0x00000073; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; - /* MRD register program */ - FMC_Bank5_6->SDCMR = 0x00046014; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; - FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001011; - FMC_Bank1->BTCR[3] = 0x00000201; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F469xx) || defined(STM32F479xx) - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001091; - FMC_Bank1->BTCR[3] = 0x00110212; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F469xx || STM32F479xx */ - - (void)(tmp); + while ((tmpreg != 0) && (timeout-- > 0)) { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index < 1000; index++) {; + } + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while ((tmpreg != 0) && (timeout-- > 0)) { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while ((tmpreg != 0) && (timeout-- > 0)) { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while ((tmpreg != 0) && (timeout-- > 0)) { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C << 1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; + #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + #if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; + #endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +#elif defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM) /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. @@ -485,293 +476,289 @@ void SystemInit_ExtMemCtl(void) * @param None * @retval None */ -void SystemInit_ExtMemCtl(void) -{ - __IO uint32_t tmp = 0x00; -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -#if defined (DATA_IN_ExtSDRAM) - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; - -#if defined(STM32F446xx) - /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface - clock */ - RCC->AHB1ENR |= 0x0000007D; -#else - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface - clock */ - RCC->AHB1ENR |= 0x000001F8; -#endif /* STM32F446xx */ - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - -#if defined(STM32F446xx) - /* Connect PAx pins to FMC Alternate function */ - GPIOA->AFR[0] |= 0xC0000000; - GPIOA->AFR[1] |= 0x00000000; - /* Configure PDx pins in Alternate function mode */ - GPIOA->MODER |= 0x00008000; - /* Configure PDx pins speed to 50 MHz */ - GPIOA->OSPEEDR |= 0x00008000; - /* Configure PDx pins Output type to push-pull */ - GPIOA->OTYPER |= 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOA->PUPDR |= 0x00000000; - - /* Connect PCx pins to FMC Alternate function */ - GPIOC->AFR[0] |= 0x00CC0000; - GPIOC->AFR[1] |= 0x00000000; - /* Configure PDx pins in Alternate function mode */ - GPIOC->MODER |= 0x00000A00; - /* Configure PDx pins speed to 50 MHz */ - GPIOC->OSPEEDR |= 0x00000A00; - /* Configure PDx pins Output type to push-pull */ - GPIOC->OTYPER |= 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOC->PUPDR |= 0x00000000; -#endif /* STM32F446xx */ - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x000000CC; - GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ - GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ - GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0xCCCCCCCC; - GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0xCCCCCCCC; - GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0x00C0CC00; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x00000000; - - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00000000; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +void SystemInit_ExtMemCtl(void) { + __IO uint32_t tmp = 0x00; + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + #if defined(DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + #if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; + #else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + #endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + #if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; + #endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ /*-- FMC Configuration -------------------------------------------------------*/ - /* Enable the FMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - - /* Configure and enable SDRAM bank1 */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCR[0] = 0x00001954; -#else - FMC_Bank5_6->SDCR[0] = 0x000019E4; -#endif /* STM32F446xx */ - FMC_Bank5_6->SDTR[0] = 0x01115351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); - - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Auto refresh command */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCMR = 0x000000F3; -#else - FMC_Bank5_6->SDCMR = 0x00000073; -#endif /* STM32F446xx */ - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* MRD register program */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCMR = 0x00044014; -#else - FMC_Bank5_6->SDCMR = 0x00046014; -#endif /* STM32F446xx */ - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ + #if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; + #else + FMC_Bank5_6->SDCR[0] = 0x000019E4; + #endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; -#if defined(STM32F446xx) - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); -#else - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); -#endif /* STM32F446xx */ - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; - FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); -#endif /* DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ - || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) - -#if defined(DATA_IN_ExtSRAM) + while ((tmpreg != 0) && (timeout-- > 0)) { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index < 1000; index++) {; + } + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while ((tmpreg != 0) && (timeout-- > 0)) { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + #if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; + #else + FMC_Bank5_6->SDCMR = 0x00000073; + #endif /* STM32F446xx */ + timeout = 0xFFFF; + while ((tmpreg != 0) && (timeout-- > 0)) { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + #if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; + #else + FMC_Bank5_6->SDCMR = 0x00046014; + #endif /* STM32F446xx */ + timeout = 0xFFFF; + while ((tmpreg != 0) && (timeout-- > 0)) { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + #if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C << 1)); + #else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C << 1)); + #endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + #endif /* DATA_IN_ExtSDRAM */ + #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + + #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) \ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) \ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + + #if defined(DATA_IN_ExtSRAM) /*-- GPIOs Configuration -----------------------------------------------------*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR |= 0x00000078; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x00CCC0CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00CC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00085AAA; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000CAFFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; /*-- FMC/FSMC Configuration --------------------------------------------------*/ - /* Enable the FMC/FSMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001011; - FMC_Bank1->BTCR[3] = 0x00000201; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F469xx) || defined(STM32F479xx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001091; - FMC_Bank1->BTCR[3] = 0x00110212; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F469xx || STM32F479xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ - || defined(STM32F412Zx) || defined(STM32F412Vx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001011; - FSMC_Bank1->BTCR[3] = 0x00000201; - FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ - -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; + #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + #if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; + #endif /* STM32F469xx || STM32F479xx */ + #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) \ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; + #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + + #endif /* DATA_IN_ExtSRAM */ + #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ - (void)(tmp); + (void)(tmp); } #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ /** diff --git a/ports/stm/boards/system_stm32f7xx.c b/ports/stm/boards/system_stm32f7xx.c index 4aebc3d35..450283ae5 100644 --- a/ports/stm/boards/system_stm32f7xx.c +++ b/ports/stm/boards/system_stm32f7xx.c @@ -47,11 +47,11 @@ #include "stm32f7xx.h" -#if !defined (HSE_VALUE) +#if !defined(HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ -#if !defined (HSI_VALUE) +#if !defined(HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -96,7 +96,7 @@ * @{ */ - /* This variable is updated in three ways: +/* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency @@ -104,9 +104,9 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 16000000; - const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -131,21 +131,20 @@ * @param None * @retval None */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ -#endif +void SystemInit(void) { + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ + #endif - /* Configure the Vector Table location add offset address ------------------*/ -#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already + /* Configure the Vector Table location add offset address ------------------*/ + #if !(BOARD_VTOR_DEFER) // only set VTOR if the bootloader hasn't already #ifdef VECT_TAB_SRAM - SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif #endif -#endif } @@ -185,52 +184,48 @@ void SystemInit(void) * @param None * @retval None */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; +void SystemCoreClockUpdate(void) { + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } else { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2; + SystemCoreClock = pllvco / pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; } /** diff --git a/ports/stm/boards/system_stm32h7xx.c b/ports/stm/boards/system_stm32h7xx.c index bbb0f821f..8b782e496 100644 --- a/ports/stm/boards/system_stm32h7xx.c +++ b/ports/stm/boards/system_stm32h7xx.c @@ -71,15 +71,15 @@ #include "stm32h7xx.h" #include <math.h> -#if !defined (HSE_VALUE) +#if !defined(HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ -#if !defined (CSI_VALUE) +#if !defined(CSI_VALUE) #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* CSI_VALUE */ -#if !defined (HSI_VALUE) +#if !defined(HSI_VALUE) #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -126,7 +126,7 @@ /** @addtogroup STM32H7xx_System_Private_Variables * @{ */ - /* This variable is updated in three ways: +/* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency @@ -134,9 +134,9 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 64000000; - uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +uint32_t SystemCoreClock = 64000000; +uint32_t SystemD2Clock = 64000000; +const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -161,117 +161,115 @@ * @param None * @retval None */ -void SystemInit (void) -{ -#if defined (DATA_IN_D2_SRAM) - __IO uint32_t tmpreg; -#endif /* DATA_IN_D2_SRAM */ - - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= RCC_CR_HSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ - RCC->CR &= 0xEAF6ED7FU; - -#if defined(D3_SRAM_BASE) - /* Reset D1CFGR register */ - RCC->D1CFGR = 0x00000000; - - /* Reset D2CFGR register */ - RCC->D2CFGR = 0x00000000; - - /* Reset D3CFGR register */ - RCC->D3CFGR = 0x00000000; -#else - /* Reset CDCFGR1 register */ - RCC->CDCFGR1 = 0x00000000; - - /* Reset CDCFGR2 register */ - RCC->CDCFGR2 = 0x00000000; - - /* Reset SRDCFGR register */ - RCC->SRDCFGR = 0x00000000; -#endif - /* Reset PLLCKSELR register */ - RCC->PLLCKSELR = 0x00000000; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00000000; - /* Reset PLL1DIVR register */ - RCC->PLL1DIVR = 0x00000000; - /* Reset PLL1FRACR register */ - RCC->PLL1FRACR = 0x00000000; - - /* Reset PLL2DIVR register */ - RCC->PLL2DIVR = 0x00000000; - - /* Reset PLL2FRACR register */ - - RCC->PLL2FRACR = 0x00000000; - /* Reset PLL3DIVR register */ - RCC->PLL3DIVR = 0x00000000; - - /* Reset PLL3FRACR register */ - RCC->PLL3FRACR = 0x00000000; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - -#if (STM32H7_DEV_ID == 0x450UL) - /* dual core CM7 or single core line */ - if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) - { - /* if stm32h7 revY*/ - /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ - *((__IO uint32_t*)0x51008108) = 0x000000001U; - } -#endif - -#if defined (DATA_IN_D2_SRAM) - /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */ -#if defined(RCC_AHB2ENR_D2SRAM3EN) - RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); -#elif defined(RCC_AHB2ENR_D2SRAM2EN) - RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); -#else - RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); -#endif /* RCC_AHB2ENR_D2SRAM3EN */ - - tmpreg = RCC->AHB2ENR; - (void) tmpreg; -#endif /* DATA_IN_D2_SRAM */ - -#if defined(DUAL_CORE) && defined(CORE_CM4) - /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif /* VECT_TAB_SRAM */ - -#else - - /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ -#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already +void SystemInit(void) { + #if defined(DATA_IN_D2_SRAM) + __IO uint32_t tmpreg; + #endif /* DATA_IN_D2_SRAM */ + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + #if defined(D3_SRAM_BASE) + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; + #else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; + #endif + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x00000000; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00000000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x00000000; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x00000000; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x00000000; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + #if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ + if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t *)0x51008108) = 0x000000001U; + } + #endif + + #if defined(DATA_IN_D2_SRAM) + /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */ + #if defined(RCC_AHB2ENR_D2SRAM3EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); + #elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); + #else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); + #endif /* RCC_AHB2ENR_D2SRAM3EN */ + + tmpreg = RCC->AHB2ENR; + (void)tmpreg; + #endif /* DATA_IN_D2_SRAM */ + + #if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ + #ifdef VECT_TAB_SRAM + SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + #else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif /* VECT_TAB_SRAM */ + + #else + + /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ + #if !(BOARD_VTOR_DEFER) // only set VTOR if the bootloader hasn't already #ifdef VECT_TAB_SRAM - SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ #else - SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif #endif -#endif -#endif /*DUAL_CORE && CORE_CM4*/ + #endif /*DUAL_CORE && CORE_CM4*/ } @@ -312,102 +310,98 @@ void SystemInit (void) * @param None * @retval None */ -void SystemCoreClockUpdate (void) -{ - uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; - uint32_t common_system_clock; - float_t fracn1, pllvco; - - - /* Get SYSCLK source -------------------------------------------------------*/ - - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); - break; - - case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - common_system_clock = CSI_VALUE; - break; - - case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - common_system_clock = HSE_VALUE; - break; +void SystemCoreClockUpdate(void) { + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; - case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; - pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); - fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + /* Get SYSCLK source -------------------------------------------------------*/ - if (pllm != 0U) + switch (RCC->CFGR & RCC_CFGR_SWS) { - switch (pllsource) - { - case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ - - hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; - pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - - break; - - case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; - - case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ - pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; - - default: - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; - } - pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; - common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + + if (pllm != 0U) { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U); + common_system_clock = (uint32_t)(float_t)(pllvco / (float_t)pllp); + } else { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = CSI_VALUE; + break; } - else - { - common_system_clock = 0U; - } - break; - - default: - common_system_clock = CSI_VALUE; - break; - } - /* Compute SystemClock frequency --------------------------------------------------*/ -#if defined (RCC_D1CFGR_D1CPRE) - tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + /* Compute SystemClock frequency --------------------------------------------------*/ + #if defined(RCC_D1CFGR_D1CPRE) + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]; - /* common_system_clock frequency : CM7 CPU frequency */ - common_system_clock >>= tmp; + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; - /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ - SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); -#else - tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + #else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]; - /* common_system_clock frequency : CM7 CPU frequency */ - common_system_clock >>= tmp; + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; - /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ - SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); -#endif + #endif -#if defined(DUAL_CORE) && defined(CORE_CM4) - SystemCoreClock = SystemD2Clock; -#else - SystemCoreClock = common_system_clock; -#endif /* DUAL_CORE && CORE_CM4 */ + #if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; + #else + SystemCoreClock = common_system_clock; + #endif /* DUAL_CORE && CORE_CM4 */ } diff --git a/ports/stm/boards/thunderpack_v11/board.c b/ports/stm/boards/thunderpack_v11/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/thunderpack_v11/board.c +++ b/ports/stm/boards/thunderpack_v11/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/thunderpack_v11/mpconfigboard.h b/ports/stm/boards/thunderpack_v11/mpconfigboard.h index 7d4a8dff3..9c3c116e5 100644 --- a/ports/stm/boards/thunderpack_v11/mpconfigboard.h +++ b/ports/stm/boards/thunderpack_v11/mpconfigboard.h @@ -38,7 +38,7 @@ // Flash config #define FLASH_SIZE (0x80000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_FLASH_SIZE (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000) +#define BOARD_FLASH_SIZE (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE - 0x2000 - 0xC000) #define HSE_VALUE ((uint32_t)24000000U) #define BOARD_OVERWRITE_SWD (1) diff --git a/ports/stm/boards/thunderpack_v12/board.c b/ports/stm/boards/thunderpack_v12/board.c index 781793328..688cfb4de 100644 --- a/ports/stm/boards/thunderpack_v12/board.c +++ b/ports/stm/boards/thunderpack_v12/board.c @@ -30,7 +30,7 @@ void board_init(void) { } bool board_requests_safe_mode(void) { - return false; + return false; } void reset_board(void) { diff --git a/ports/stm/boards/thunderpack_v12/mpconfigboard.h b/ports/stm/boards/thunderpack_v12/mpconfigboard.h index fb5f389a3..34a5795ff 100644 --- a/ports/stm/boards/thunderpack_v12/mpconfigboard.h +++ b/ports/stm/boards/thunderpack_v12/mpconfigboard.h @@ -35,7 +35,7 @@ // Flash config #define FLASH_SIZE (0x80000) #define FLASH_PAGE_SIZE (0x4000) -#define BOARD_FLASH_SIZE (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE- 0x2000 - 0xC000) +#define BOARD_FLASH_SIZE (FLASH_SIZE - CIRCUITPY_INTERNAL_NVM_SIZE - 0x2000 - 0xC000) #define INTERNAL_FLASH_FILESYSTEM_SIZE 0x8000 // On-board flash diff --git a/ports/stm/common-hal/analogio/AnalogIn.c b/ports/stm/common-hal/analogio/AnalogIn.c index 588d687ee..35010ac7c 100644 --- a/ports/stm/common-hal/analogio/AnalogIn.c +++ b/ports/stm/common-hal/analogio/AnalogIn.c @@ -36,8 +36,8 @@ #include "stm32f4xx_ll_adc.h" #include "stm32f4xx_ll_bus.h" -void common_hal_analogio_analogin_construct(analogio_analogin_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogin_construct(analogio_analogin_obj_t *self, + const mcu_pin_obj_t *pin) { // No ADC function on pin if (pin->adc_unit == 0x00) { @@ -76,9 +76,9 @@ void common_hal_analogio_analogin_deinit(analogio_analogin_obj_t *self) { uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { // Something else might have used the ADC in a different way, // so we completely re-initialize it. - ADC_TypeDef * ADCx; + ADC_TypeDef *ADCx; - if(self->pin->adc_unit & 0x01) { + if (self->pin->adc_unit & 0x01) { ADCx = ADC1; } else if (self->pin->adc_unit == 0x04) { #ifdef ADC3 @@ -89,9 +89,9 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { } LL_GPIO_SetPinMode(pin_port(self->pin->port), (uint32_t)pin_mask(self->pin->number), LL_GPIO_MODE_ANALOG); - //LL_GPIO_PIN_0 + // LL_GPIO_PIN_0 - //HAL Implementation + // HAL Implementation ADC_HandleTypeDef AdcHandle; ADC_ChannelConfTypeDef sConfig; @@ -110,9 +110,9 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { AdcHandle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; HAL_ADC_Init(&AdcHandle); - sConfig.Channel = (uint32_t)self->pin->adc_channel; //ADC_CHANNEL_0 <-normal iteration, not mask + sConfig.Channel = (uint32_t)self->pin->adc_channel; // ADC_CHANNEL_0 <-normal iteration, not mask sConfig.Rank = 1; - sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES; //Taken from micropython + sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES; // Taken from micropython HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); HAL_ADC_Start(&AdcHandle); diff --git a/ports/stm/common-hal/analogio/AnalogIn.h b/ports/stm/common-hal/analogio/AnalogIn.h index 910092897..c8e3e0868 100644 --- a/ports/stm/common-hal/analogio/AnalogIn.h +++ b/ports/stm/common-hal/analogio/AnalogIn.h @@ -34,7 +34,7 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t * pin; + const mcu_pin_obj_t *pin; } analogio_analogin_obj_t; static inline uint8_t stm32_adc_units(uint8_t adc_packed) { diff --git a/ports/stm/common-hal/analogio/AnalogOut.c b/ports/stm/common-hal/analogio/AnalogOut.c index 69c1f3e04..1a3817a35 100644 --- a/ports/stm/common-hal/analogio/AnalogOut.c +++ b/ports/stm/common-hal/analogio/AnalogOut.c @@ -39,15 +39,15 @@ #include "stm32f4xx_hal.h" -//DAC is shared between both channels. +// DAC is shared between both channels. #if HAS_DAC DAC_HandleTypeDef handle; #endif STATIC bool dac_on[2]; -void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, - const mcu_pin_obj_t *pin) { +void common_hal_analogio_analogout_construct(analogio_analogout_obj_t *self, + const mcu_pin_obj_t *pin) { #if !(HAS_DAC) mp_raise_ValueError(translate("No DAC on chip")); #else @@ -61,17 +61,16 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, mp_raise_ValueError(translate("Invalid DAC pin supplied")); } - //Only init if the shared DAC is empty or reset + // Only init if the shared DAC is empty or reset if (handle.Instance == NULL || handle.State == HAL_DAC_STATE_RESET) { __HAL_RCC_DAC_CLK_ENABLE(); handle.Instance = DAC; - if (HAL_DAC_Init(&handle) != HAL_OK) - { + if (HAL_DAC_Init(&handle) != HAL_OK) { mp_raise_ValueError(translate("DAC Device Init Error")); } } - //init channel specific pin + // init channel specific pin GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitStruct.Pin = pin_mask(pin->number); GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -100,8 +99,8 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) { self->pin = NULL; dac_on[self->dac_index] = false; - //turn off the DAC if both channels are off - if(dac_on[0] == false && dac_on[1] == false) { + // turn off the DAC if both channels are off + if (dac_on[0] == false && dac_on[1] == false) { __HAL_RCC_DAC_CLK_DISABLE(); HAL_DAC_DeInit(&handle); } @@ -109,7 +108,7 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) { } void common_hal_analogio_analogout_set_value(analogio_analogout_obj_t *self, - uint16_t value) { + uint16_t value) { #if HAS_DAC HAL_DAC_SetValue(&handle, self->channel, DAC_ALIGN_12B_R, value >> 4); HAL_DAC_Start(&handle, self->channel); diff --git a/ports/stm/common-hal/analogio/AnalogOut.h b/ports/stm/common-hal/analogio/AnalogOut.h index 46312b460..3c208a611 100644 --- a/ports/stm/common-hal/analogio/AnalogOut.h +++ b/ports/stm/common-hal/analogio/AnalogOut.h @@ -36,12 +36,12 @@ typedef struct { mp_obj_base_t base; -#if HAS_DAC + #if HAS_DAC DAC_ChannelConfTypeDef ch_handle; -#endif - const mcu_pin_obj_t * pin; + #endif + const mcu_pin_obj_t *pin; uint8_t channel; - uint8_t dac_index:1; + uint8_t dac_index : 1; } analogio_analogout_obj_t; void analogout_reset(void); diff --git a/ports/stm/common-hal/busio/I2C.c b/ports/stm/common-hal/busio/I2C.c index 7726b5e87..db6d86c34 100644 --- a/ports/stm/common-hal/busio/I2C.c +++ b/ports/stm/common-hal/busio/I2C.c @@ -61,11 +61,11 @@ STATIC bool never_reset_i2c[MAX_I2C]; #define ALL_CLOCKS 0xFF STATIC void i2c_clock_enable(uint8_t mask); STATIC void i2c_clock_disable(uint8_t mask); -STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef * I2Cx); +STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef *I2Cx); void i2c_reset(void) { uint16_t never_reset_mask = 0x00; - for(int i = 0; i < MAX_I2C; i++) { + for (int i = 0; i < MAX_I2C; i++) { if (!never_reset_i2c[i]) { reserved_i2c[i] = false; } else { @@ -76,10 +76,10 @@ void i2c_reset(void) { } void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, - const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda, uint32_t frequency, uint32_t timeout) { + const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) { // Match pins to I2C objects - I2C_TypeDef * I2Cx; + I2C_TypeDef *I2Cx; uint8_t sda_len = MP_ARRAY_SIZE(mcu_i2c_sda_list); uint8_t scl_len = MP_ARRAY_SIZE(mcu_i2c_scl_list); bool i2c_taken = false; @@ -107,7 +107,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, } // Handle typedef selection, errors - if (self->sda != NULL && self->scl != NULL ) { + if (self->sda != NULL && self->scl != NULL) { I2Cx = mcu_i2c_banks[self->sda->periph_index - 1]; } else { if (i2c_taken) { @@ -171,8 +171,8 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, self->frame_in_prog = false; - //start the receive interrupt chain - HAL_NVIC_DisableIRQ(self->irq); //prevent handle lock contention + // start the receive interrupt chain + HAL_NVIC_DisableIRQ(self->irq); // prevent handle lock contention HAL_NVIC_SetPriority(self->irq, 1, 0); HAL_NVIC_EnableIRQ(self->irq); } @@ -215,15 +215,15 @@ bool common_hal_busio_i2c_probe(busio_i2c_obj_t *self, uint8_t addr) { bool common_hal_busio_i2c_try_lock(busio_i2c_obj_t *self) { bool grabbed_lock = false; - //Critical section code that may be required at some point. + // Critical section code that may be required at some point. // uint32_t store_primask = __get_PRIMASK(); // __disable_irq(); // __DMB(); - if (!self->has_lock) { - grabbed_lock = true; - self->has_lock = true; - } + if (!self->has_lock) { + grabbed_lock = true; + self->has_lock = true; + } // __DMB(); // __set_PRIMASK(store_primask); @@ -240,7 +240,7 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) { } uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, - const uint8_t *data, size_t len, bool transmit_stop_bit) { + const uint8_t *data, size_t len, bool transmit_stop_bit) { HAL_StatusTypeDef result; if (!transmit_stop_bit) { uint32_t xfer_opt; @@ -251,31 +251,29 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr, xfer_opt = I2C_NEXT_FRAME; } result = HAL_I2C_Master_Seq_Transmit_IT(&(self->handle), - (uint16_t)(addr << 1), (uint8_t *)data, - (uint16_t)len, xfer_opt); - while (HAL_I2C_GetState(&(self->handle)) != HAL_I2C_STATE_READY) - { + (uint16_t)(addr << 1), (uint8_t *)data, + (uint16_t)len, xfer_opt); + while (HAL_I2C_GetState(&(self->handle)) != HAL_I2C_STATE_READY) { RUN_BACKGROUND_TASKS; } self->frame_in_prog = true; } else { result = HAL_I2C_Master_Transmit(&(self->handle), (uint16_t)(addr << 1), - (uint8_t *)data, (uint16_t)len, 500); + (uint8_t *)data, (uint16_t)len, 500); } return result == HAL_OK ? 0 : MP_EIO; } uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, - uint8_t *data, size_t len) { + uint8_t *data, size_t len) { if (!self->frame_in_prog) { - return HAL_I2C_Master_Receive(&(self->handle), (uint16_t)(addr<<1), data, (uint16_t)len, 500) - == HAL_OK ? 0 : MP_EIO; + return HAL_I2C_Master_Receive(&(self->handle), (uint16_t)(addr << 1), data, (uint16_t)len, 500) + == HAL_OK ? 0 : MP_EIO; } else { HAL_StatusTypeDef result = HAL_I2C_Master_Seq_Receive_IT(&(self->handle), - (uint16_t)(addr << 1), (uint8_t *)data, - (uint16_t)len, I2C_LAST_FRAME); - while (HAL_I2C_GetState(&(self->handle)) != HAL_I2C_STATE_READY) - { + (uint16_t)(addr << 1), (uint8_t *)data, + (uint16_t)len, I2C_LAST_FRAME); + while (HAL_I2C_GetState(&(self->handle)) != HAL_I2C_STATE_READY) { RUN_BACKGROUND_TASKS; } self->frame_in_prog = false; @@ -338,7 +336,7 @@ STATIC void i2c_clock_disable(uint8_t mask) { #endif } -STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef * I2Cx) { +STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef *I2Cx) { #ifdef I2C1 if (I2Cx == I2C1) { self->irq = I2C1_EV_IRQn; @@ -362,8 +360,8 @@ STATIC void i2c_assign_irq(busio_i2c_obj_t *self, I2C_TypeDef * I2Cx) { } STATIC void call_hal_irq(int i2c_num) { - //Create casted context pointer - busio_i2c_obj_t * context = (busio_i2c_obj_t*)MP_STATE_PORT(cpy_i2c_obj_all)[i2c_num - 1]; + // Create casted context pointer + busio_i2c_obj_t *context = (busio_i2c_obj_t *)MP_STATE_PORT(cpy_i2c_obj_all)[i2c_num - 1]; if (context != NULL) { HAL_NVIC_ClearPendingIRQ(context->irq); HAL_I2C_EV_IRQHandler(&context->handle); diff --git a/ports/stm/common-hal/busio/SPI.c b/ports/stm/common-hal/busio/SPI.c index 20ee0f6e1..2f26a01cb 100644 --- a/ports/stm/common-hal/busio/SPI.c +++ b/ports/stm/common-hal/busio/SPI.c @@ -39,7 +39,7 @@ // Note that any bugs introduced in this file can cause crashes at startup // for chips using external SPI flash. -//arrays use 0 based numbering: SPI1 is stored at index 0 +// arrays use 0 based numbering: SPI1 is stored at index 0 #define MAX_SPI 6 STATIC bool reserved_spi[MAX_SPI]; @@ -49,28 +49,32 @@ STATIC bool never_reset_spi[MAX_SPI]; STATIC void spi_clock_enable(uint8_t mask); STATIC void spi_clock_disable(uint8_t mask); -STATIC uint32_t get_busclock(SPI_TypeDef * instance) { +STATIC uint32_t get_busclock(SPI_TypeDef *instance) { #if (CPY_STM32H7) - if (instance == SPI1 || instance == SPI2 || instance == SPI3) { - return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123); - } else if (instance == SPI4 || instance == SPI5) { - return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI45); - } else { - return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6); - } + if (instance == SPI1 || instance == SPI2 || instance == SPI3) { + return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123); + } else if (instance == SPI4 || instance == SPI5) { + return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI45); + } else { + return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6); + } #elif (CPY_STM32F4 || CPY_STM32F7) - //SPI2 and 3 are on PCLK1, if they exist. - #ifdef SPI2 - if (instance == SPI2) return HAL_RCC_GetPCLK1Freq(); - #endif - #ifdef SPI3 - if (instance == SPI3) return HAL_RCC_GetPCLK1Freq(); - #endif - return HAL_RCC_GetPCLK2Freq(); + // SPI2 and 3 are on PCLK1, if they exist. + #ifdef SPI2 + if (instance == SPI2) { + return HAL_RCC_GetPCLK1Freq(); + } + #endif + #ifdef SPI3 + if (instance == SPI3) { + return HAL_RCC_GetPCLK1Freq(); + } + #endif + return HAL_RCC_GetPCLK2Freq(); #endif } -STATIC uint32_t stm32_baud_to_spi_div(uint32_t baudrate, uint16_t * prescaler, uint32_t busclock) { +STATIC uint32_t stm32_baud_to_spi_div(uint32_t baudrate, uint16_t *prescaler, uint32_t busclock) { static const uint32_t baud_map[8][2] = { {2,SPI_BAUDRATEPRESCALER_2}, {4,SPI_BAUDRATEPRESCALER_4}, @@ -85,13 +89,13 @@ STATIC uint32_t stm32_baud_to_spi_div(uint32_t baudrate, uint16_t * prescaler, u uint16_t divisor; do { divisor = baud_map[i][0]; - if (baudrate >= (busclock/divisor)) { + if (baudrate >= (busclock / divisor)) { *prescaler = divisor; return baud_map[i][1]; } i++; } while (divisor != 256); - //only gets here if requested baud is lower than minimum + // only gets here if requested baud is lower than minimum *prescaler = 256; return SPI_BAUDRATEPRESCALER_256; } @@ -109,18 +113,18 @@ void spi_reset(void) { } STATIC const mcu_periph_obj_t *find_pin_function(const mcu_periph_obj_t *table, size_t sz, const mcu_pin_obj_t *pin, int periph_index) { - for(size_t i = 0; i<sz; i++, table++) { - if(periph_index == table->periph_index && pin == table->pin ) { + for (size_t i = 0; i < sz; i++, table++) { + if (periph_index == table->periph_index && pin == table->pin) { return table; } } return NULL; } -//match pins to SPI objects +// match pins to SPI objects STATIC int check_pins(busio_spi_obj_t *self, - const mcu_pin_obj_t * sck, const mcu_pin_obj_t * mosi, - const mcu_pin_obj_t * miso) { + const mcu_pin_obj_t *sck, const mcu_pin_obj_t *mosi, + const mcu_pin_obj_t *miso) { bool spi_taken = false; uint8_t sck_len = MP_ARRAY_SIZE(mcu_spi_sck_list); @@ -146,7 +150,7 @@ STATIC int check_pins(busio_spi_obj_t *self, continue; } - if (reserved_spi[periph_index-1]) { + if (reserved_spi[periph_index - 1]) { spi_taken = true; continue; } @@ -166,13 +170,13 @@ STATIC int check_pins(busio_spi_obj_t *self, } void common_hal_busio_spi_construct(busio_spi_obj_t *self, - const mcu_pin_obj_t * sck, const mcu_pin_obj_t * mosi, - const mcu_pin_obj_t * miso) { + const mcu_pin_obj_t *sck, const mcu_pin_obj_t *mosi, + const mcu_pin_obj_t *miso) { int periph_index = check_pins(self, sck, mosi, miso); - SPI_TypeDef * SPIx = mcu_spi_banks[periph_index - 1]; + SPI_TypeDef *SPIx = mcu_spi_banks[periph_index - 1]; - //Start GPIO for each pin + // Start GPIO for each pin GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitStruct.Pin = pin_mask(sck->number); GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -215,8 +219,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, self->handle.Init.TIMode = SPI_TIMODE_DISABLE; self->handle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; self->handle.Init.CRCPolynomial = 10; - if (HAL_SPI_Init(&self->handle) != HAL_OK) - { + if (HAL_SPI_Init(&self->handle) != HAL_OK) { mp_raise_ValueError(translate("SPI Init Error")); } self->baudrate = (get_busclock(SPIx) / 16); @@ -254,7 +257,7 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { if (common_hal_busio_spi_deinited(self)) { return; } - spi_clock_disable(1<<(self->sck->periph_index - 1)); + spi_clock_disable(1 << (self->sck->periph_index - 1)); reserved_spi[self->sck->periph_index - 1] = false; never_reset_spi[self->sck->periph_index - 1] = false; @@ -271,14 +274,14 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { } bool common_hal_busio_spi_configure(busio_spi_obj_t *self, - uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { - //This resets the SPI, so check before updating it redundantly - if (baudrate == self->baudrate && polarity== self->polarity + uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) { + // This resets the SPI, so check before updating it redundantly + if (baudrate == self->baudrate && polarity == self->polarity && phase == self->phase && bits == self->bits) { return true; } - //Deinit SPI + // Deinit SPI HAL_SPI_DeInit(&self->handle); self->handle.Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT; @@ -286,10 +289,9 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self, self->handle.Init.CLKPhase = (phase) ? SPI_PHASE_2EDGE : SPI_PHASE_1EDGE; self->handle.Init.BaudRatePrescaler = stm32_baud_to_spi_div(baudrate, &self->prescaler, - get_busclock(self->handle.Instance)); + get_busclock(self->handle.Instance)); - if (HAL_SPI_Init(&self->handle) != HAL_OK) - { + if (HAL_SPI_Init(&self->handle) != HAL_OK) { mp_raise_ValueError(translate("SPI Re-initialization error")); } @@ -303,7 +305,7 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self, bool common_hal_busio_spi_try_lock(busio_spi_obj_t *self) { bool grabbed_lock = false; - //Critical section code that may be required at some point. + // Critical section code that may be required at some point. // uint32_t store_primask = __get_PRIMASK(); // __disable_irq(); // __DMB(); @@ -328,7 +330,7 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) { } bool common_hal_busio_spi_write(busio_spi_obj_t *self, - const uint8_t *data, size_t len) { + const uint8_t *data, size_t len) { if (self->mosi == NULL) { mp_raise_ValueError(translate("No MOSI Pin")); } @@ -337,7 +339,7 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self, } bool common_hal_busio_spi_read(busio_spi_obj_t *self, - uint8_t *data, size_t len, uint8_t write_value) { + uint8_t *data, size_t len, uint8_t write_value) { if (self->miso == NULL) { mp_raise_ValueError(translate("No MISO Pin")); } @@ -352,26 +354,26 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self, } bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, - const uint8_t *data_out, uint8_t *data_in, size_t len) { + const uint8_t *data_out, uint8_t *data_in, size_t len) { if (self->miso == NULL || self->mosi == NULL) { mp_raise_ValueError(translate("Missing MISO or MOSI Pin")); } HAL_StatusTypeDef result = HAL_SPI_TransmitReceive(&self->handle, - (uint8_t *) data_out, data_in, (uint16_t)len,HAL_MAX_DELAY); + (uint8_t *)data_out, data_in, (uint16_t)len,HAL_MAX_DELAY); return result == HAL_OK; } -uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) { - //returns actual frequency - uint32_t result = HAL_RCC_GetPCLK2Freq()/self->prescaler; +uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) { + // returns actual frequency + uint32_t result = HAL_RCC_GetPCLK2Freq() / self->prescaler; return result; } -uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) { return self->phase; } -uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) { +uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) { return self->polarity; } diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c index b4794a31b..ecaee84d3 100644 --- a/ports/stm/common-hal/busio/UART.c +++ b/ports/stm/common-hal/busio/UART.c @@ -39,19 +39,19 @@ #define ALL_UARTS 0xFFFF -//arrays use 0 based numbering: UART1 is stored at index 0 +// arrays use 0 based numbering: UART1 is stored at index 0 STATIC bool reserved_uart[MAX_UART]; STATIC bool never_reset_uart[MAX_UART]; -int errflag; //Used to restart read halts +int errflag; // Used to restart read halts STATIC void uart_clock_enable(uint16_t mask); STATIC void uart_clock_disable(uint16_t mask); -STATIC void uart_assign_irq(busio_uart_obj_t* self, USART_TypeDef* USARTx); +STATIC void uart_assign_irq(busio_uart_obj_t *self, USART_TypeDef *USARTx); -STATIC USART_TypeDef * assign_uart_or_throw(busio_uart_obj_t* self, bool pin_eval, - int periph_index, bool uart_taken) { +STATIC USART_TypeDef *assign_uart_or_throw(busio_uart_obj_t *self, bool pin_eval, + int periph_index, bool uart_taken) { if (pin_eval) { - //assign a root pointer pointer for IRQ + // assign a root pointer pointer for IRQ MP_STATE_PORT(cpy_uart_obj_all)[periph_index] = self; return mcu_uart_banks[periph_index]; } else { @@ -77,40 +77,40 @@ void uart_reset(void) { } void common_hal_busio_uart_construct(busio_uart_obj_t *self, - const mcu_pin_obj_t * tx, const mcu_pin_obj_t * rx, - const mcu_pin_obj_t * rts, const mcu_pin_obj_t * cts, - const mcu_pin_obj_t * rs485_dir, bool rs485_invert, + const mcu_pin_obj_t *tx, const mcu_pin_obj_t *rx, + const mcu_pin_obj_t *rts, const mcu_pin_obj_t *cts, + const mcu_pin_obj_t *rs485_dir, bool rs485_invert, uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop, - mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer, + mp_float_t timeout, uint16_t receiver_buffer_size, byte *receiver_buffer, bool sigint_enabled) { - //match pins to UART objects - USART_TypeDef * USARTx; + // match pins to UART objects + USART_TypeDef *USARTx; uint8_t tx_len = MP_ARRAY_SIZE(mcu_uart_tx_list); uint8_t rx_len = MP_ARRAY_SIZE(mcu_uart_rx_list); bool uart_taken = false; - uint8_t periph_index = 0; //origin 0 corrected + uint8_t periph_index = 0; // origin 0 corrected if ((rts != NULL) || (cts != NULL) || (rs485_dir != NULL) || (rs485_invert == true)) { mp_raise_ValueError(translate("RTS/CTS/RS485 Not yet supported on this device")); } - //Can have both pins, or either + // Can have both pins, or either if ((tx != NULL) && (rx != NULL)) { - //normal find loop if both pins exist + // normal find loop if both pins exist for (uint i = 0; i < tx_len; i++) { if (mcu_uart_tx_list[i].pin == tx) { - //rx + // rx for (uint j = 0; j < rx_len; j++) { if (mcu_uart_rx_list[j].pin == rx && mcu_uart_rx_list[j].periph_index == mcu_uart_tx_list[i].periph_index) { - //keep looking if the UART is taken, edge case + // keep looking if the UART is taken, edge case if (reserved_uart[mcu_uart_tx_list[i].periph_index - 1]) { uart_taken = true; continue; } - //store pins if not + // store pins if not self->tx = &mcu_uart_tx_list[i]; self->rx = &mcu_uart_rx_list[j]; break; @@ -125,15 +125,15 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, USARTx = assign_uart_or_throw(self, (self->tx != NULL && self->rx != NULL), periph_index, uart_taken); } else if (tx == NULL) { - //If there is no tx, run only rx + // If there is no tx, run only rx for (uint i = 0; i < rx_len; i++) { if (mcu_uart_rx_list[i].pin == rx) { - //keep looking if the UART is taken, edge case + // keep looking if the UART is taken, edge case if (reserved_uart[mcu_uart_rx_list[i].periph_index - 1]) { uart_taken = true; continue; } - //store pins if not + // store pins if not self->rx = &mcu_uart_rx_list[i]; break; } @@ -142,15 +142,15 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, USARTx = assign_uart_or_throw(self, (self->rx != NULL), periph_index, uart_taken); } else if (rx == NULL) { - //If there is no rx, run only tx + // If there is no rx, run only tx for (uint i = 0; i < tx_len; i++) { if (mcu_uart_tx_list[i].pin == tx) { - //keep looking if the UART is taken, edge case + // keep looking if the UART is taken, edge case if (reserved_uart[mcu_uart_tx_list[i].periph_index - 1]) { uart_taken = true; continue; } - //store pins if not + // store pins if not self->tx = &mcu_uart_tx_list[i]; break; } @@ -159,22 +159,22 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, USARTx = assign_uart_or_throw(self, (self->tx != NULL), periph_index, uart_taken); } else { - //both pins cannot be empty + // both pins cannot be empty mp_raise_ValueError(translate("Supply at least one UART pin")); } - //Other errors - if ( receiver_buffer_size == 0 ) { + // Other errors + if (receiver_buffer_size == 0) { mp_raise_ValueError(translate("Invalid buffer size")); } - if ( bits != 8 && bits != 9 ) { + if (bits != 8 && bits != 9) { mp_raise_ValueError(translate("Invalid word/bit length")); } - if ( USARTx == NULL) { //this can only be hit if the periph file is wrong + if (USARTx == NULL) { // this can only be hit if the periph file is wrong mp_raise_ValueError(translate("Internal define error")); } - //GPIO Init + // GPIO Init GPIO_InitTypeDef GPIO_InitStruct = {0}; if (self->tx != NULL) { GPIO_InitStruct.Pin = pin_mask(tx->number); @@ -193,7 +193,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, HAL_GPIO_Init(pin_port(rx->port), &GPIO_InitStruct); } - //reserve uart and enable the peripheral + // reserve uart and enable the peripheral reserved_uart[periph_index] = true; uart_clock_enable(1 << (periph_index)); uart_assign_irq(self, USARTx); @@ -203,15 +203,14 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, self->handle.Init.WordLength = (bits == 9) ? UART_WORDLENGTH_9B : UART_WORDLENGTH_8B; self->handle.Init.StopBits = (stop > 1) ? UART_STOPBITS_2 : UART_STOPBITS_1; self->handle.Init.Parity = (parity == BUSIO_UART_PARITY_ODD) ? UART_PARITY_ODD : - (parity == BUSIO_UART_PARITY_EVEN) ? UART_PARITY_EVEN : - UART_PARITY_NONE; + (parity == BUSIO_UART_PARITY_EVEN) ? UART_PARITY_EVEN : + UART_PARITY_NONE; self->handle.Init.Mode = (self->tx != NULL && self->rx != NULL) ? UART_MODE_TX_RX : - (self->tx != NULL) ? UART_MODE_TX : - UART_MODE_RX; + (self->tx != NULL) ? UART_MODE_TX : + UART_MODE_RX; self->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; self->handle.Init.OverSampling = UART_OVERSAMPLING_16; - if (HAL_UART_Init(&self->handle) != HAL_OK) - { + if (HAL_UART_Init(&self->handle) != HAL_OK) { mp_raise_ValueError(translate("UART Init Error")); } @@ -219,7 +218,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, // Init buffer for rx and claim pins if (self->rx != NULL) { if (receiver_buffer != NULL) { - self->ringbuf = (ringbuf_t){ receiver_buffer, receiver_buffer_size }; + self->ringbuf = (ringbuf_t) { receiver_buffer, receiver_buffer_size }; } else { if (!ringbuf_alloc(&self->ringbuf, receiver_buffer_size, true)) { mp_raise_ValueError(translate("UART Buffer allocation error")); @@ -234,13 +233,13 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, self->timeout_ms = timeout * 1000; self->sigint_enabled = sigint_enabled; - //start the interrupt series + // start the interrupt series if ((HAL_UART_GetState(&self->handle) & HAL_UART_STATE_BUSY_RX) == HAL_UART_STATE_BUSY_RX) { mp_raise_ValueError(translate("Could not start interrupt, RX busy")); } - //start the receive interrupt chain - HAL_NVIC_DisableIRQ(self->irq); //prevent handle lock contention + // start the receive interrupt chain + HAL_NVIC_DisableIRQ(self->irq); // prevent handle lock contention HAL_UART_Receive_IT(&self->handle, &self->rx_char, 1); HAL_NVIC_SetPriority(self->irq, UART_IRQPRI, UART_IRQSUB_PRI); HAL_NVIC_EnableIRQ(self->irq); @@ -260,11 +259,13 @@ void common_hal_busio_uart_never_reset(busio_uart_obj_t *self) { } bool common_hal_busio_uart_deinited(busio_uart_obj_t *self) { - return (self->tx->pin == NULL && self->rx->pin == NULL); + return self->tx->pin == NULL && self->rx->pin == NULL; } void common_hal_busio_uart_deinit(busio_uart_obj_t *self) { - if (common_hal_busio_uart_deinited(self)) return; + if (common_hal_busio_uart_deinited(self)) { + return; + } for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_uart_banks); i++) { if (mcu_uart_banks[i] == self->handle.Instance) { @@ -294,14 +295,14 @@ size_t common_hal_busio_uart_read(busio_uart_obj_t *self, uint8_t *data, size_t uint64_t start_ticks = supervisor_ticks_ms64(); // Wait for all bytes received or timeout, same as nrf - while ( (ringbuf_num_filled(&self->ringbuf) < len) && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms) ) { + while ((ringbuf_num_filled(&self->ringbuf) < len) && (supervisor_ticks_ms64() - start_ticks < self->timeout_ms)) { RUN_BACKGROUND_TASKS; - //restart if it failed in the callback + // restart if it failed in the callback if (errflag != HAL_OK) { errflag = HAL_UART_Receive_IT(&self->handle, &self->rx_char, 1); } // Allow user to break out of a timeout with a KeyboardInterrupt. - if ( mp_hal_is_interrupted() ) { + if (mp_hal_is_interrupted()) { return 0; } } @@ -324,10 +325,10 @@ size_t common_hal_busio_uart_write(busio_uart_obj_t *self, const uint8_t *data, if (self->tx == NULL) { mp_raise_ValueError(translate("No TX pin")); } - bool write_err = false; //write error shouldn't disable interrupts + bool write_err = false; // write error shouldn't disable interrupts HAL_NVIC_DisableIRQ(self->irq); - HAL_StatusTypeDef ret = HAL_UART_Transmit(&self->handle, (uint8_t*)data, len, HAL_MAX_DELAY); + HAL_StatusTypeDef ret = HAL_UART_Transmit(&self->handle, (uint8_t *)data, len, HAL_MAX_DELAY); if (ret != HAL_OK) { write_err = true; } @@ -340,13 +341,12 @@ size_t common_hal_busio_uart_write(busio_uart_obj_t *self, const uint8_t *data, return len; } -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *handle) -{ +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *handle) { for (int i = 0; i < 7; i++) { - //get context pointer and cast it as struct pointer - busio_uart_obj_t * context = (busio_uart_obj_t*)MP_STATE_PORT(cpy_uart_obj_all)[i]; + // get context pointer and cast it as struct pointer + busio_uart_obj_t *context = (busio_uart_obj_t *)MP_STATE_PORT(cpy_uart_obj_all)[i]; if (handle == &context->handle) { - //check if transaction is ongoing + // check if transaction is ongoing if ((HAL_UART_GetState(handle) & HAL_UART_STATE_BUSY_RX) == HAL_UART_STATE_BUSY_RX) { return; } @@ -364,8 +364,7 @@ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *handle) } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle) -{ +void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle) { if (__HAL_UART_GET_FLAG(UartHandle, UART_FLAG_PE) != RESET) { __HAL_UART_CLEAR_PEFLAG(UartHandle); } else if (__HAL_UART_GET_FLAG(UartHandle, UART_FLAG_FE) != RESET) { @@ -375,9 +374,9 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle) } else if (__HAL_UART_GET_FLAG(UartHandle, UART_FLAG_ORE) != RESET) { __HAL_UART_CLEAR_OREFLAG(UartHandle); } - //restart serial read after an error + // restart serial read after an error for (int i = 0; i < 7; i++) { - busio_uart_obj_t * context = (busio_uart_obj_t *)MP_STATE_PORT(cpy_uart_obj_all)[i]; + busio_uart_obj_t *context = (busio_uart_obj_t *)MP_STATE_PORT(cpy_uart_obj_all)[i]; if (UartHandle == &context->handle) { HAL_UART_Receive_IT(UartHandle, &context->rx_char, 1); return; @@ -391,10 +390,12 @@ uint32_t common_hal_busio_uart_get_baudrate(busio_uart_obj_t *self) { } void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrate) { - //Don't reset if it's the same value - if (baudrate == self->baudrate) return; + // Don't reset if it's the same value + if (baudrate == self->baudrate) { + return; + } - //Otherwise de-init and set new rate + // Otherwise de-init and set new rate if (HAL_UART_DeInit(&self->handle) != HAL_OK) { mp_raise_ValueError(translate("UART De-init error")); } @@ -407,7 +408,7 @@ void common_hal_busio_uart_set_baudrate(busio_uart_obj_t *self, uint32_t baudrat } mp_float_t common_hal_busio_uart_get_timeout(busio_uart_obj_t *self) { - return (mp_float_t) (self->timeout_ms / 1000.0f); + return (mp_float_t)(self->timeout_ms / 1000.0f); } void common_hal_busio_uart_set_timeout(busio_uart_obj_t *self, mp_float_t timeout) { @@ -430,8 +431,8 @@ bool common_hal_busio_uart_ready_to_tx(busio_uart_obj_t *self) { } STATIC void call_hal_irq(int uart_num) { - //Create casted context pointer - busio_uart_obj_t * context = (busio_uart_obj_t*)MP_STATE_PORT(cpy_uart_obj_all)[uart_num - 1]; + // Create casted context pointer + busio_uart_obj_t *context = (busio_uart_obj_t *)MP_STATE_PORT(cpy_uart_obj_all)[uart_num - 1]; if (context != NULL) { HAL_NVIC_ClearPendingIRQ(context->irq); HAL_UART_IRQHandler(&context->handle); @@ -609,7 +610,7 @@ STATIC void uart_clock_disable(uint16_t mask) { #endif } -STATIC void uart_assign_irq(busio_uart_obj_t *self, USART_TypeDef * USARTx) { +STATIC void uart_assign_irq(busio_uart_obj_t *self, USART_TypeDef *USARTx) { #ifdef USART1 if (USARTx == USART1) { self->irq = USART1_IRQn; diff --git a/ports/stm/common-hal/canio/CAN.c b/ports/stm/common-hal/canio/CAN.c index 52d5cad1f..091421fd1 100644 --- a/ports/stm/common-hal/canio/CAN.c +++ b/ports/stm/common-hal/canio/CAN.c @@ -38,7 +38,7 @@ STATIC bool reserved_can[MP_ARRAY_SIZE(mcu_can_banks)]; STATIC const mcu_periph_obj_t *find_pin_function(const mcu_periph_obj_t *table, size_t sz, const mcu_pin_obj_t *pin, int periph_index) { - for(size_t i = 0; i<sz; i++, table++) { + for (size_t i = 0; i < sz; i++, table++) { if (periph_index != -1 && periph_index != table->periph_index) { continue; } @@ -50,9 +50,8 @@ STATIC const mcu_periph_obj_t *find_pin_function(const mcu_periph_obj_t *table, } -void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent) -{ -#define DIV_ROUND(a, b) (((a) + (b)/2) / (b)) +void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent) { +#define DIV_ROUND(a, b) (((a) + (b) / 2) / (b)) #define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b)) const uint8_t can_tx_len = MP_ARRAY_SIZE(mcu_can_tx_list); @@ -110,7 +109,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc __HAL_RCC_CAN1_CLK_ENABLE(); - if(hw == CAN2) { + if (hw == CAN2) { __HAL_RCC_CAN2_CLK_ENABLE(); self->start_filter_bank = 14; self->end_filter_bank = 28; @@ -126,9 +125,9 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc .AutoBusOff = ENABLE, .Prescaler = divisor, .Mode = (loopback ? CAN_MODE_LOOPBACK : 0) | (silent ? CAN_MODE_SILENT_LOOPBACK : 0), - .SyncJumpWidth = (sjw-1) << CAN_BTR_SJW_Pos, - .TimeSeg1 = (tq_to_sample-2) << CAN_BTR_TS1_Pos, - .TimeSeg2 = (tq_after_sample-1) << CAN_BTR_TS2_Pos, + .SyncJumpWidth = (sjw - 1) << CAN_BTR_SJW_Pos, + .TimeSeg1 = (tq_to_sample - 2) << CAN_BTR_TS1_Pos, + .TimeSeg2 = (tq_after_sample - 1) << CAN_BTR_TS2_Pos, }; self->periph_index = periph_index; @@ -149,7 +148,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc // Clear every filter enable bit for this can HW uint32_t fa1r = self->filter_hw->FA1R; - for (int i = self->start_filter_bank; i<self->end_filter_bank; i++) { + for (int i = self->start_filter_bank; i < self->end_filter_bank; i++) { fa1r &= ~(1 << i); } self->filter_hw->FA1R = fa1r; @@ -160,23 +159,19 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc reserved_can[periph_index] = true; } -bool common_hal_canio_can_loopback_get(canio_can_obj_t *self) -{ +bool common_hal_canio_can_loopback_get(canio_can_obj_t *self) { return self->loopback; } -int common_hal_canio_can_baudrate_get(canio_can_obj_t *self) -{ +int common_hal_canio_can_baudrate_get(canio_can_obj_t *self) { return self->baudrate; } -int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self) -{ +int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self) { return (self->handle.Instance->ESR & CAN_ESR_TEC) >> CAN_ESR_TEC_Pos; } -int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self) -{ +int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self) { return (self->handle.Instance->ESR & CAN_ESR_REC) >> CAN_ESR_REC_Pos; } @@ -213,15 +208,14 @@ bool common_hal_canio_can_auto_restart_get(canio_can_obj_t *self) { } void common_hal_canio_can_auto_restart_set(canio_can_obj_t *self, bool value) { - if(value) { + if (value) { SET_BIT(self->handle.Instance->MCR, CAN_MCR_ABOM); } else { CLEAR_BIT(self->handle.Instance->MCR, CAN_MCR_ABOM); } } -void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in) -{ +void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in) { canio_message_obj_t *message = message_in; uint32_t mailbox; bool rtr = message->base.type == &canio_remote_transmission_request_type; @@ -278,8 +272,7 @@ void common_hal_canio_can_check_for_deinit(canio_can_obj_t *self) { } } -void common_hal_canio_can_deinit(canio_can_obj_t *self) -{ +void common_hal_canio_can_deinit(canio_can_obj_t *self) { if (self->handle.Instance) { SET_BIT(self->handle.Instance->MCR, CAN_MCR_RESET); while (READ_BIT(self->handle.Instance->MCR, CAN_MCR_RESET)) { @@ -290,7 +283,7 @@ void common_hal_canio_can_deinit(canio_can_obj_t *self) } void common_hal_canio_reset(void) { - for (size_t i=0; i<MP_ARRAY_SIZE(mcu_can_banks); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_can_banks); i++) { SET_BIT(mcu_can_banks[i]->MCR, CAN_MCR_RESET); reserved_can[i] = 0; } diff --git a/ports/stm/common-hal/canio/CAN.h b/ports/stm/common-hal/canio/CAN.h index 3157d0a03..16bb8fd1e 100644 --- a/ports/stm/common-hal/canio/CAN.h +++ b/ports/stm/common-hal/canio/CAN.h @@ -45,12 +45,12 @@ typedef struct canio_can_obj { int baudrate; const mcu_pin_obj_t *rx_pin; const mcu_pin_obj_t *tx_pin; - bool loopback:1; - bool silent:1; - bool auto_restart:1; - bool fifo0_in_use:1; - bool fifo1_in_use:1; - uint8_t periph_index:2; + bool loopback : 1; + bool silent : 1; + bool auto_restart : 1; + bool fifo0_in_use : 1; + bool fifo1_in_use : 1; + uint8_t periph_index : 2; uint8_t cancel_mailbox; uint8_t start_filter_bank; uint8_t end_filter_bank; diff --git a/ports/stm/common-hal/canio/Listener.c b/ports/stm/common-hal/canio/Listener.c index 09456d39d..23634eba6 100644 --- a/ports/stm/common-hal/canio/Listener.c +++ b/ports/stm/common-hal/canio/Listener.c @@ -46,7 +46,7 @@ STATIC void prevent_filter_change(canio_can_obj_t *can) { } STATIC bool filter_in_use(canio_can_obj_t *can, int idx) { - return can->filter_hw->FA1R & (1<<idx); + return can->filter_hw->FA1R & (1 << idx); } // One filter bank can hold: @@ -62,19 +62,19 @@ STATIC size_t num_filters_needed(size_t nmatch, canio_match_obj_t **matches) { } size_t num_extended_mask = 0; size_t num_standard_mask = 1; - for(size_t i=0; i<nmatch; i++) { + for (size_t i = 0; i < nmatch; i++) { if (matches[i]->extended) { num_extended_mask += 1; } else { num_standard_mask += 1; } } - return num_extended_mask + num_standard_mask/2; + return num_extended_mask + num_standard_mask / 2; } STATIC size_t num_filters_available(canio_can_obj_t *can) { size_t available = 0; - for(size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) { + for (size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) { if (!filter_in_use(can, i)) { available++; } @@ -87,9 +87,9 @@ STATIC void clear_filters(canio_listener_obj_t *self) { allow_filter_change(can); uint32_t fa1r = can->filter_hw->FA1R; - for(size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) { + for (size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) { if (((can->filter_hw->FFA1R >> i) & 1) == self->fifo_idx) { - fa1r &= ~(1<<i); + fa1r &= ~(1 << i); } } can->filter_hw->FA1R = fa1r; @@ -98,8 +98,8 @@ STATIC void clear_filters(canio_listener_obj_t *self) { STATIC int next_filter(canio_can_obj_t *can) { uint32_t fa1r = can->filter_hw->FA1R; - for(size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) { - if (!(fa1r & (1<<i))) { + for (size_t i = can->start_filter_bank; i < can->end_filter_bank; i++) { + if (!(fa1r & (1 << i))) { return i; } } @@ -109,8 +109,8 @@ STATIC int next_filter(canio_can_obj_t *can) { // IDE = "extended ID" flag of packet header. We always add this bit to the // mask because a match is always for just one kind of address length -#define FILTER16_IDE (1<<3) -#define FILTER32_IDE (1<<2) +#define FILTER16_IDE (1 << 3) +#define FILTER32_IDE (1 << 2) STATIC void install_standard_filter(canio_listener_obj_t *self, canio_match_obj_t *match1, canio_match_obj_t *match2) { int bank = next_filter(self->can); @@ -201,8 +201,8 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t ** install_all_match_filter(self); } else { canio_match_obj_t *first_match = NULL; - for(size_t i = 0; i<nmatch; i++) { - if(matches[i]->extended) { + for (size_t i = 0; i < nmatch; i++) { + if (matches[i]->extended) { install_extended_filter(self, matches[i]); } else { if (first_match) { diff --git a/ports/stm/common-hal/digitalio/DigitalInOut.c b/ports/stm/common-hal/digitalio/DigitalInOut.c index a676aeb15..fbefdb79a 100644 --- a/ports/stm/common-hal/digitalio/DigitalInOut.c +++ b/ports/stm/common-hal/digitalio/DigitalInOut.c @@ -40,12 +40,12 @@ #endif void common_hal_digitalio_digitalinout_never_reset( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { never_reset_pin_number(self->pin->port, self->pin->number); } digitalinout_result_t common_hal_digitalio_digitalinout_construct( - digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { + digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { common_hal_mcu_pin_claim(pin); self->pin = pin; @@ -74,7 +74,7 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self } void common_hal_digitalio_digitalinout_switch_to_input( - digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitStruct.Pin = pin_mask(self->pin->number); @@ -87,8 +87,8 @@ void common_hal_digitalio_digitalinout_switch_to_input( } digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( - digitalio_digitalinout_obj_t *self, bool value, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, bool value, + digitalio_drive_mode_t drive_mode) { common_hal_digitalio_digitalinout_set_drive_mode(self, drive_mode); common_hal_digitalio_digitalinout_set_value(self, value); @@ -96,27 +96,27 @@ digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output( } digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { return (LL_GPIO_GetPinMode(pin_port(self->pin->port), pin_mask(self->pin->number)) == LL_GPIO_MODE_INPUT) ? DIRECTION_INPUT : DIRECTION_OUTPUT; } void common_hal_digitalio_digitalinout_set_value( - digitalio_digitalinout_obj_t *self, bool value) { + digitalio_digitalinout_obj_t *self, bool value) { HAL_GPIO_WritePin(pin_port(self->pin->port), pin_mask(self->pin->number), value); } bool common_hal_digitalio_digitalinout_get_value( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { return (LL_GPIO_GetPinMode(pin_port(self->pin->port), pin_mask(self->pin->number)) == LL_GPIO_MODE_INPUT) ? HAL_GPIO_ReadPin(pin_port(self->pin->port), pin_mask(self->pin->number)) : LL_GPIO_IsOutputPinSet(pin_port(self->pin->port), pin_mask(self->pin->number)); } digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( - digitalio_digitalinout_obj_t *self, - digitalio_drive_mode_t drive_mode) { + digitalio_digitalinout_obj_t *self, + digitalio_drive_mode_t drive_mode) { GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitStruct.Pin = pin_mask(self->pin->number); GPIO_InitStruct.Mode = (drive_mode == DRIVE_MODE_OPEN_DRAIN ? @@ -128,14 +128,14 @@ digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode( } digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { return LL_GPIO_GetPinOutputType(pin_port(self->pin->port), pin_mask(self->pin->number)) - == LL_GPIO_OUTPUT_OPENDRAIN ? DRIVE_MODE_OPEN_DRAIN : DRIVE_MODE_PUSH_PULL; + == LL_GPIO_OUTPUT_OPENDRAIN ? DRIVE_MODE_OPEN_DRAIN : DRIVE_MODE_PUSH_PULL; } void common_hal_digitalio_digitalinout_set_pull( - digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { switch (pull) { case PULL_UP: @@ -153,7 +153,7 @@ void common_hal_digitalio_digitalinout_set_pull( } digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( - digitalio_digitalinout_obj_t *self) { + digitalio_digitalinout_obj_t *self) { switch (LL_GPIO_GetPinPull(pin_port(self->pin->port), pin_mask(self->pin->number))) { case LL_GPIO_PULL_UP: diff --git a/ports/stm/common-hal/displayio/ParallelBus.c b/ports/stm/common-hal/displayio/ParallelBus.c index fd07d38af..4788deb9b 100644 --- a/ports/stm/common-hal/displayio/ParallelBus.c +++ b/ports/stm/common-hal/displayio/ParallelBus.c @@ -33,19 +33,19 @@ #include "shared-bindings/digitalio/DigitalInOut.h" #include "shared-bindings/microcontroller/__init__.h" -void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t* self, - const mcu_pin_obj_t* data0, const mcu_pin_obj_t* command, const mcu_pin_obj_t* chip_select, - const mcu_pin_obj_t* write, const mcu_pin_obj_t* read, const mcu_pin_obj_t* reset) { +void common_hal_displayio_parallelbus_construct(displayio_parallelbus_obj_t *self, + const mcu_pin_obj_t *data0, const mcu_pin_obj_t *command, const mcu_pin_obj_t *chip_select, + const mcu_pin_obj_t *write, const mcu_pin_obj_t *read, const mcu_pin_obj_t *reset) { mp_raise_NotImplementedError(translate("ParallelBus not yet supported")); } -void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t* self) { +void common_hal_displayio_parallelbus_deinit(displayio_parallelbus_obj_t *self) { } bool common_hal_displayio_parallelbus_reset(mp_obj_t obj) { - return false; + return false; } bool common_hal_displayio_parallelbus_bus_free(mp_obj_t obj) { diff --git a/ports/stm/common-hal/microcontroller/Pin.c b/ports/stm/common-hal/microcontroller/Pin.c index 37c202d86..80cb9defc 100644 --- a/ports/stm/common-hal/microcontroller/Pin.c +++ b/ports/stm/common-hal/microcontroller/Pin.c @@ -41,15 +41,15 @@ bool apa102_mosi_in_use; #endif #if defined(TFBGA216) - GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK}; +GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK}; #elif defined(LQFP144) - GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG}; +GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG}; #elif defined(LQFP100_f4) || (LQFP100_x7) - GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE}; +GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE}; #elif defined(LQFP64) - GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC, GPIOD}; +GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD}; #elif defined(UFQFPN48) - GPIO_TypeDef * ports[] = {GPIOA, GPIOB, GPIOC}; +GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC}; #endif @@ -78,7 +78,7 @@ void reset_all_pins(void) { // Mark pin as free and return it to a quiescent state. void reset_pin_number(uint8_t pin_port, uint8_t pin_number) { - if ( pin_number == NO_PIN ) { + if (pin_number == NO_PIN) { return; } @@ -86,9 +86,9 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number) { return; } // Clear claimed bit & reset - claimed_pins[pin_port] &= ~(1<<pin_number); - never_reset_pins[pin_port] &= ~(1<<pin_number); - HAL_GPIO_DeInit(ports[pin_port], 1<<pin_number); + claimed_pins[pin_port] &= ~(1 << pin_number); + never_reset_pins[pin_port] &= ~(1 << pin_number); + HAL_GPIO_DeInit(ports[pin_port], 1 << pin_number); #ifdef MICROPY_HW_NEOPIXEL if (pin_port == MICROPY_HW_NEOPIXEL->port && pin_number == MICROPY_HW_NEOPIXEL->number) { @@ -101,8 +101,7 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number) { if ( (pin_port == MICROPY_HW_APA102_MOSI->port && pin_number == MICROPY_HW_APA102_MOSI->number) || (pin_port == MICROPY_HW_APA102_SCK->port && pin_number == MICROPY_HW_APA102_MOSI->number) - ) - { + ) { apa102_mosi_in_use = false; apa102_sck_in_use = false; rgb_led_status_init(); @@ -112,19 +111,19 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number) { } void never_reset_pin_number(uint8_t pin_port, uint8_t pin_number) { - if ( pin_number == NO_PIN ) { + if (pin_number == NO_PIN) { return; } - never_reset_pins[pin_port] |= 1<<pin_number; + never_reset_pins[pin_port] |= 1 << pin_number; // Make sure never reset pins are also always claimed - claimed_pins[pin_port] |= 1<<pin_number; + claimed_pins[pin_port] |= 1 << pin_number; } -void common_hal_never_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_never_reset_pin(const mcu_pin_obj_t *pin) { never_reset_pin_number(pin->port, pin->number); } -void common_hal_reset_pin(const mcu_pin_obj_t* pin) { +void common_hal_reset_pin(const mcu_pin_obj_t *pin) { if (pin == NULL) { return; } @@ -133,11 +132,11 @@ void common_hal_reset_pin(const mcu_pin_obj_t* pin) { void claim_pin(uint8_t pin_port, uint8_t pin_number) { // Set bit in claimed_pins bitmask. - claimed_pins[pin_port] |= 1<<pin_number; + claimed_pins[pin_port] |= 1 << pin_number; } bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number) { - return !(claimed_pins[pin_port] & 1<<pin_number); + return !(claimed_pins[pin_port] & 1 << pin_number); } bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { @@ -147,12 +146,10 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { } #endif #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) - if (pin == MICROPY_HW_APA102_MOSI) - { + if (pin == MICROPY_HW_APA102_MOSI) { return !apa102_mosi_in_use; } - if (pin == MICROPY_HW_APA102_SCK) - { + if (pin == MICROPY_HW_APA102_SCK) { return !apa102_sck_in_use; } #endif @@ -160,19 +157,19 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t *pin) { return pin_number_is_free(pin->port, pin->number); } -GPIO_TypeDef * pin_port(uint8_t pin_port) { +GPIO_TypeDef *pin_port(uint8_t pin_port) { return ports[pin_port]; } uint16_t pin_mask(uint8_t pin_number) { - return 1<<pin_number; + return 1 << pin_number; } -uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t* pin) { +uint8_t common_hal_mcu_pin_number(const mcu_pin_obj_t *pin) { return pin->port * 16 + pin->number; } -void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { +void common_hal_mcu_pin_claim(const mcu_pin_obj_t *pin) { claim_pin(pin->port, pin->number); #ifdef MICROPY_HW_NEOPIXEL if (pin == MICROPY_HW_NEOPIXEL) { @@ -180,12 +177,10 @@ void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) { } #endif #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) - if (pin == MICROPY_HW_APA102_MOSI) - { + if (pin == MICROPY_HW_APA102_MOSI) { apa102_mosi_in_use = true; } - if (pin == MICROPY_HW_APA102_SCK) - { + if (pin == MICROPY_HW_APA102_SCK) { apa102_sck_in_use = true; } #endif diff --git a/ports/stm/common-hal/microcontroller/Pin.h b/ports/stm/common-hal/microcontroller/Pin.h index f461d3813..4a3397942 100644 --- a/ports/stm/common-hal/microcontroller/Pin.h +++ b/ports/stm/common-hal/microcontroller/Pin.h @@ -46,7 +46,7 @@ void reset_pin_number(uint8_t pin_port, uint8_t pin_number); void claim_pin(uint8_t pin_port, uint8_t pin_number); bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number); void never_reset_pin_number(uint8_t pin_port, uint8_t pin_number); -GPIO_TypeDef * pin_port(uint8_t pin_port); +GPIO_TypeDef *pin_port(uint8_t pin_port); uint16_t pin_mask(uint8_t pin_number); #endif // MICROPY_INCLUDED_STM32_COMMON_HAL_MICROCONTROLLER_PIN_H diff --git a/ports/stm/common-hal/microcontroller/Processor.c b/ports/stm/common-hal/microcontroller/Processor.c index dd04c56dc..b33d96e73 100644 --- a/ports/stm/common-hal/microcontroller/Processor.c +++ b/ports/stm/common-hal/microcontroller/Processor.c @@ -37,10 +37,10 @@ #define STM32_UUID ((uint32_t *)0x1FFF7A10) -//Factory calibration locations +// Factory calibration locations #define ADC_CAL_ADDRESS (0x1fff7a2a) -#define ADC_CAL1 ((uint16_t*)(ADC_CAL_ADDRESS + 2)) -#define ADC_CAL2 ((uint16_t*)(ADC_CAL_ADDRESS + 4)) +#define ADC_CAL1 ((uint16_t *)(ADC_CAL_ADDRESS + 2)) +#define ADC_CAL2 ((uint16_t *)(ADC_CAL_ADDRESS + 4)) #define VREFIN_CAL ((uint16_t *)ADC_CAL_ADDRESS) // correction factor for reference value @@ -68,7 +68,7 @@ float common_hal_mcu_processor_get_temperature(void) { #if CPY_STM32F4 __HAL_RCC_ADC1_CLK_ENABLE(); - //HAL Implementation + // HAL Implementation ADC_HandleTypeDef AdcHandle; ADC_ChannelConfTypeDef sConfig; set_adc_params(&AdcHandle); @@ -77,7 +77,7 @@ float common_hal_mcu_processor_get_temperature(void) { ADC->CCR |= ADC_CCR_TSVREFE; ADC->CCR &= ~ADC_CCR_VBATE; // If this somehow got turned on, it'll return bad values. - sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; //either 16 or 18, depending on chip + sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; // either 16 or 18, depending on chip sConfig.Rank = 1; sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; // Temp sensor likes 10us minimum HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); @@ -89,7 +89,7 @@ float common_hal_mcu_processor_get_temperature(void) { uint32_t value = (uint32_t)HAL_ADC_GetValue(&AdcHandle); HAL_ADC_Stop(&AdcHandle); - //There's no F4 specific appnote for this but it works the same as the L1 in AN3964 + // There's no F4 specific appnote for this but it works the same as the L1 in AN3964 float core_temp_avg_slope = (*ADC_CAL2 - *ADC_CAL1) / 80.0; return (((float)value * adc_refcor - *ADC_CAL1) / core_temp_avg_slope) + 30.0f; #else @@ -101,7 +101,7 @@ float common_hal_mcu_processor_get_voltage(void) { #if CPY_STM32F4 __HAL_RCC_ADC1_CLK_ENABLE(); - //HAL Implementation + // HAL Implementation ADC_HandleTypeDef AdcHandle; ADC_ChannelConfTypeDef sConfig; set_adc_params(&AdcHandle); @@ -121,7 +121,7 @@ float common_hal_mcu_processor_get_voltage(void) { uint32_t value = (uint32_t)HAL_ADC_GetValue(&AdcHandle); HAL_ADC_Stop(&AdcHandle); - //This value could be used to actively correct ADC values. + // This value could be used to actively correct ADC values. adc_refcor = ((float)(*VREFIN_CAL)) / ((float)value); return adc_refcor * 3.3f; @@ -136,8 +136,8 @@ uint32_t common_hal_mcu_processor_get_frequency(void) { void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { #if CPY_STM32F4 - for (int i=0; i<3; i++) { - ((uint32_t*) raw_id)[i] = STM32_UUID[i]; + for (int i = 0; i < 3; i++) { + ((uint32_t *)raw_id)[i] = STM32_UUID[i]; } #endif } diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c index a827399cc..28e06c913 100644 --- a/ports/stm/common-hal/microcontroller/__init__.c +++ b/ports/stm/common-hal/microcontroller/__init__.c @@ -41,11 +41,12 @@ #include "supervisor/shared/safe_mode.h" void common_hal_mcu_delay_us(uint32_t delay) { - uint32_t ticks_per_us = HAL_RCC_GetSysClockFreq()/1000000; + uint32_t ticks_per_us = HAL_RCC_GetSysClockFreq() / 1000000; delay *= ticks_per_us; SysTick->LOAD = delay; SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; - while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {} + while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) { + } SysTick->CTRL = 0; } @@ -61,7 +62,7 @@ void common_hal_mcu_enable_interrupts(void) { if (nesting_count == 0) { // This is very very bad because it means there was mismatched disable/enables so we // "HardFault". - asm("bkpt"); + asm ("bkpt"); } nesting_count--; if (nesting_count > 0) { @@ -72,12 +73,13 @@ void common_hal_mcu_enable_interrupts(void) { } void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) { - if(runmode == RUNMODE_SAFE_MODE) - safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE); + if (runmode == RUNMODE_SAFE_MODE) { + safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE); + } } void common_hal_mcu_reset(void) { - filesystem_flush(); //TODO: implement as part of flash improvements + filesystem_flush(); // TODO: implement as part of flash improvements NVIC_SystemReset(); } @@ -96,6 +98,6 @@ const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { .type = &nvm_bytearray_type, }, .len = NVM_BYTEARRAY_BUFFER_SIZE, - .start_address = (uint8_t*) (CIRCUITPY_INTERNAL_NVM_START_ADDR) + .start_address = (uint8_t *)(CIRCUITPY_INTERNAL_NVM_START_ADDR) }; #endif diff --git a/ports/stm/common-hal/neopixel_write/__init__.c b/ports/stm/common-hal/neopixel_write/__init__.c index c8852403b..f5dabe7f9 100644 --- a/ports/stm/common-hal/neopixel_write/__init__.c +++ b/ports/stm/common-hal/neopixel_write/__init__.c @@ -36,7 +36,7 @@ uint64_t next_start_raw_ticks = 0; -//sysclock divisors +// sysclock divisors #define MAGIC_800_INT 900000 // ~1.11 us -> 1.2 field #define MAGIC_800_T0H 2800000 // ~0.36 us -> 0.44 field #define MAGIC_800_T1H 1350000 // ~0.74 us -> 0.84 field @@ -44,25 +44,26 @@ uint64_t next_start_raw_ticks = 0; #pragma GCC push_options #pragma GCC optimize ("Os") -void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, - uint32_t numBytes) { +void common_hal_neopixel_write(const digitalio_digitalinout_obj_t *digitalinout, uint8_t *pixels, + uint32_t numBytes) { uint8_t *p = pixels, *end = p + numBytes, pix = *p++, mask = 0x80; uint32_t start = 0; uint32_t cyc = 0; - //assumes 800_000Hz frequency - //Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us - //TODO: try to get dynamic weighting working again + // assumes 800_000Hz frequency + // Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us + // TODO: try to get dynamic weighting working again uint32_t sys_freq = HAL_RCC_GetSysClockFreq(); - uint32_t interval = sys_freq/MAGIC_800_INT; - uint32_t t0 = (sys_freq/MAGIC_800_T0H); - uint32_t t1 = (sys_freq/MAGIC_800_T1H); + uint32_t interval = sys_freq / MAGIC_800_INT; + uint32_t t0 = (sys_freq / MAGIC_800_T0H); + uint32_t t1 = (sys_freq / MAGIC_800_T1H); // Wait to make sure we don't append onto the last transmission. This should only be a tick or // two. - while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {} + while (port_get_raw_ticks(NULL) < next_start_raw_ticks) { + } - GPIO_TypeDef * p_port = pin_port(digitalinout->pin->port); + GPIO_TypeDef *p_port = pin_port(digitalinout->pin->port); uint32_t p_mask = pin_mask(digitalinout->pin->number); __disable_irq(); @@ -71,16 +72,22 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; DWT->CYCCNT = 0; - for(;;) { + for (;;) { cyc = (pix & mask) ? t1 : t0; start = DWT->CYCCNT; LL_GPIO_SetOutputPin(p_port, p_mask); - while((DWT->CYCCNT - start) < cyc); + while ((DWT->CYCCNT - start) < cyc) { + ; + } LL_GPIO_ResetOutputPin(p_port, p_mask); - while((DWT->CYCCNT - start) < interval); - if(!(mask >>= 1)) { - if(p >= end) break; - pix = *p++; + while ((DWT->CYCCNT - start) < interval) { + ; + } + if (!(mask >>= 1)) { + if (p >= end) { + break; + } + pix = *p++; mask = 0x80; } } diff --git a/ports/stm/common-hal/nvm/ByteArray.c b/ports/stm/common-hal/nvm/ByteArray.c index b7a1ff035..6ef2eb392 100644 --- a/ports/stm/common-hal/nvm/ByteArray.c +++ b/ports/stm/common-hal/nvm/ByteArray.c @@ -38,7 +38,7 @@ uint32_t common_hal_nvm_bytearray_get_length(nvm_bytearray_obj_t *self) { } bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, - uint32_t start_index, uint8_t* values, uint32_t len) { + uint32_t start_index, uint8_t *values, uint32_t len) { // Copy flash to buffer uint8_t buffer[self->len]; memcpy(buffer, self->start_address, self->len); @@ -48,7 +48,7 @@ bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, // Erase flash sector HAL_FLASH_Unlock(); - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR ); + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); FLASH_Erase_Sector(CIRCUITPY_INTERNAL_NVM_SECTOR, VOLTAGE_RANGE_3); // Write bytes to flash @@ -68,6 +68,6 @@ bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self, // NVM memory is memory mapped so reading it is easy. void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t *self, - uint32_t start_index, uint32_t len, uint8_t* values) { + uint32_t start_index, uint32_t len, uint8_t *values) { memcpy(values, self->start_address + start_index, len); } diff --git a/ports/stm/common-hal/nvm/ByteArray.h b/ports/stm/common-hal/nvm/ByteArray.h index b6ea36de3..b88d91976 100644 --- a/ports/stm/common-hal/nvm/ByteArray.h +++ b/ports/stm/common-hal/nvm/ByteArray.h @@ -38,7 +38,7 @@ typedef struct { mp_obj_base_t base; - uint8_t* start_address; + uint8_t *start_address; uint32_t len; } nvm_bytearray_obj_t; diff --git a/ports/stm/common-hal/os/__init__.c b/ports/stm/common-hal/os/__init__.c index 8da7243a3..66dfd9f76 100644 --- a/ports/stm/common-hal/os/__init__.c +++ b/ports/stm/common-hal/os/__init__.c @@ -55,7 +55,7 @@ STATIC MP_DEFINE_ATTRTUPLE( (mp_obj_t)&os_uname_info_release_obj, (mp_obj_t)&os_uname_info_version_obj, (mp_obj_t)&os_uname_info_machine_obj -); + ); mp_obj_t common_hal_os_uname(void) { return (mp_obj_t)&os_uname_info_obj; @@ -65,19 +65,23 @@ mp_obj_t common_hal_os_uname(void) { bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { #if (HAS_TRNG) - //init the RNG + // init the RNG __HAL_RCC_RNG_CLK_ENABLE(); RNG_HandleTypeDef handle; handle.Instance = RNG; - if (HAL_RNG_Init(&handle) != HAL_OK) mp_raise_ValueError(translate("RNG Init Error")); + if (HAL_RNG_Init(&handle) != HAL_OK) { + mp_raise_ValueError(translate("RNG Init Error")); + } - //Assign bytes + // Assign bytes uint32_t i = 0; while (i < length) { uint32_t new_random; uint32_t start = HAL_GetTick(); - //the HAL function has a timeout, but it isn't long enough, and isn't adjustable - while(!(__HAL_RNG_GET_FLAG(&handle,RNG_FLAG_DRDY)) && ((HAL_GetTick() - start) < RNG_TIMEOUT)); + // the HAL function has a timeout, but it isn't long enough, and isn't adjustable + while (!(__HAL_RNG_GET_FLAG(&handle,RNG_FLAG_DRDY)) && ((HAL_GetTick() - start) < RNG_TIMEOUT)) { + ; + } if (HAL_RNG_GenerateRandomNumber(&handle, &new_random) != HAL_OK) { mp_raise_ValueError(translate("Random number generation error")); } @@ -88,8 +92,10 @@ bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) { } } - //shut down the peripheral - if (HAL_RNG_DeInit(&handle) != HAL_OK) mp_raise_ValueError(translate("RNG DeInit Error")); + // shut down the peripheral + if (HAL_RNG_DeInit(&handle) != HAL_OK) { + mp_raise_ValueError(translate("RNG DeInit Error")); + } __HAL_RCC_RNG_CLK_DISABLE(); return true; diff --git a/ports/stm/common-hal/pulseio/PulseIn.c b/ports/stm/common-hal/pulseio/PulseIn.c index 015ee8536..ece02f66a 100644 --- a/ports/stm/common-hal/pulseio/PulseIn.c +++ b/ports/stm/common-hal/pulseio/PulseIn.c @@ -38,21 +38,18 @@ #include STM32_HAL_H #define STM32_GPIO_PORT_SIZE 16 -static pulseio_pulsein_obj_t* _objs[STM32_GPIO_PORT_SIZE]; +static pulseio_pulsein_obj_t *_objs[STM32_GPIO_PORT_SIZE]; STATIC TIM_HandleTypeDef tim_handle; static uint32_t overflow_count = 0; STATIC uint8_t refcount = 0; -static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t* self, uint8_t num); +static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t *self, uint8_t num); -void pulsein_timer_event_handler(void) -{ +void pulsein_timer_event_handler(void) { // Detect TIM Update event - if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET) - { + if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET) { + if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(&tim_handle, TIM_IT_UPDATE); overflow_count++; } @@ -67,13 +64,15 @@ static void pulsein_exti_event_handler(uint8_t num) { // Interrupt register must be cleared manually EXTI->PR = 1 << num; - pulseio_pulsein_obj_t* self = _objs[num]; - if ( !self ) return; + pulseio_pulsein_obj_t *self = _objs[num]; + if (!self) { + return; + } if (self->first_edge) { // first pulse is opposite state from idle bool state = HAL_GPIO_ReadPin(pin_port(self->pin->port), pin_mask(self->pin->number)); - if ( self->idle_state != state ) { + if (self->idle_state != state) { self->first_edge = false; } } else { @@ -109,20 +108,20 @@ void pulsein_reset(void) { refcount = 0; } -void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu_pin_obj_t* pin, - uint16_t maxlen, bool idle_state) { +void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t *self, const mcu_pin_obj_t *pin, + uint16_t maxlen, bool idle_state) { // STM32 has one shared EXTI for each pin number, 0-15 uint8_t p_num = pin->number; - if(_objs[p_num]) { + if (_objs[p_num]) { mp_raise_ValueError(translate("Pin number already reserved by EXTI")); } _objs[p_num] = self; // Allocate pulse buffer - self->buffer = (uint16_t *) m_malloc(maxlen * sizeof(uint16_t), false); + self->buffer = (uint16_t *)m_malloc(maxlen * sizeof(uint16_t), false); if (self->buffer == NULL) { mp_raise_msg_varg(&mp_type_MemoryError, translate("Failed to allocate RX buffer of %d bytes"), - maxlen * sizeof(uint16_t)); + maxlen * sizeof(uint16_t)); } // Set internal variables @@ -138,12 +137,12 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu if (HAL_TIM_Base_GetState(&tim_handle) == HAL_TIM_STATE_RESET) { // Find a suitable timer - TIM_TypeDef * tim_instance = stm_peripherals_find_timer(); + TIM_TypeDef *tim_instance = stm_peripherals_find_timer(); stm_peripherals_timer_reserve(tim_instance); // Set ticks to 1us uint32_t source = stm_peripherals_timer_get_source_freq(tim_instance); - uint32_t prescaler = source/1000000; + uint32_t prescaler = source / 1000000; // Enable clocks and IRQ, set callback stm_peripherals_timer_preinit(tim_instance, 4, pulsein_timer_event_handler); @@ -151,7 +150,7 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu // Set the new period tim_handle.Instance = tim_instance; tim_handle.Init.Prescaler = prescaler - 1; - tim_handle.Init.Period = 0x10000 - 1; //65 ms period (maximum) + tim_handle.Init.Period = 0x10000 - 1; // 65 ms period (maximum) HAL_TIM_Base_Init(&tim_handle); // Set registers manually @@ -178,15 +177,15 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, const mcu common_hal_mcu_pin_claim(pin); } -bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t* self) { - return (self->pin == NULL); +bool common_hal_pulseio_pulsein_deinited(pulseio_pulsein_obj_t *self) { + return self->pin == NULL; } -void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t *self) { if (common_hal_pulseio_pulsein_deinited(self)) { return; } - //Remove pulsein slot from shared array + // Remove pulsein slot from shared array _objs[self->pin->number] = NULL; reset_pin_number(self->pin->port, self->pin->number); self->pin = NULL; @@ -197,14 +196,14 @@ void common_hal_pulseio_pulsein_deinit(pulseio_pulsein_obj_t* self) { } } -void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_pause(pulseio_pulsein_obj_t *self) { HAL_NVIC_DisableIRQ(self->irq); self->paused = true; } -void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, uint16_t trigger_duration) { +void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t *self, uint16_t trigger_duration) { // Make sure we're paused. - if ( !self->paused ) { + if (!self->paused) { common_hal_pulseio_pulsein_pause(self); } @@ -235,14 +234,14 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self, uint16_t tri HAL_NVIC_EnableIRQ(self->irq); } -void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t* self) { +void common_hal_pulseio_pulsein_clear(pulseio_pulsein_obj_t *self) { HAL_NVIC_DisableIRQ(self->irq); self->start = 0; self->len = 0; HAL_NVIC_EnableIRQ(self->irq); } -uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, int16_t index) { +uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t *self, int16_t index) { HAL_NVIC_DisableIRQ(self->irq); if (index < 0) { index += self->len; @@ -256,7 +255,7 @@ uint16_t common_hal_pulseio_pulsein_get_item(pulseio_pulsein_obj_t* self, int16_ return value; } -uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t *self) { if (self->len == 0) { mp_raise_IndexError_varg(translate("pop from empty %q"), MP_QSTR_PulseIn); } @@ -269,19 +268,19 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) { return value; } -uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_maxlen(pulseio_pulsein_obj_t *self) { return self->maxlen; } -bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t* self) { +bool common_hal_pulseio_pulsein_get_paused(pulseio_pulsein_obj_t *self) { return self->paused; } -uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t* self) { +uint16_t common_hal_pulseio_pulsein_get_len(pulseio_pulsein_obj_t *self) { return self->len; } -static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t* self, uint8_t num) { +static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t *self, uint8_t num) { if (num == 0) { self->irq = EXTI0_IRQn; } else if (num == 1) { @@ -292,49 +291,42 @@ static void assign_EXTI_Interrupt(pulseio_pulsein_obj_t* self, uint8_t num) { self->irq = EXTI3_IRQn; } else if (num == 4) { self->irq = EXTI4_IRQn; - } else if (num >= 5 && num <= 9 ) { + } else if (num >= 5 && num <= 9) { self->irq = EXTI9_5_IRQn; } else if (num >= 10 && num <= 15) { self->irq = EXTI15_10_IRQn; } } -void EXTI0_IRQHandler(void) -{ +void EXTI0_IRQHandler(void) { pulsein_exti_event_handler(0); } -void EXTI1_IRQHandler(void) -{ +void EXTI1_IRQHandler(void) { pulsein_exti_event_handler(1); } -void EXTI2_IRQHandler(void) -{ +void EXTI2_IRQHandler(void) { pulsein_exti_event_handler(2); } -void EXTI3_IRQHandler(void) -{ +void EXTI3_IRQHandler(void) { pulsein_exti_event_handler(3); } -void EXTI4_IRQHandler(void) -{ +void EXTI4_IRQHandler(void) { pulsein_exti_event_handler(4); } -void EXTI9_5_IRQHandler(void) -{ +void EXTI9_5_IRQHandler(void) { uint32_t pending = EXTI->PR; for (uint i = 5; i <= 9; i++) { - if(pending & (1 << i)) { + if (pending & (1 << i)) { pulsein_exti_event_handler(i); } } } -void EXTI15_10_IRQHandler(void) -{ +void EXTI15_10_IRQHandler(void) { uint32_t pending = EXTI->PR; for (uint i = 10; i <= 15; i++) { - if(pending & (1 << i)) { + if (pending & (1 << i)) { pulsein_exti_event_handler(i); } } diff --git a/ports/stm/common-hal/pulseio/PulseIn.h b/ports/stm/common-hal/pulseio/PulseIn.h index 34d0cc731..8de60b9cd 100644 --- a/ports/stm/common-hal/pulseio/PulseIn.h +++ b/ports/stm/common-hal/pulseio/PulseIn.h @@ -34,13 +34,13 @@ typedef struct { mp_obj_base_t base; - const mcu_pin_obj_t* pin; + const mcu_pin_obj_t *pin; IRQn_Type irq; bool idle_state; bool paused; volatile bool first_edge; - uint16_t* buffer; + uint16_t *buffer; uint16_t maxlen; volatile uint16_t start; diff --git a/ports/stm/common-hal/pulseio/PulseOut.c b/ports/stm/common-hal/pulseio/PulseOut.c index 38027606f..9e28002a6 100644 --- a/ports/stm/common-hal/pulseio/PulseOut.c +++ b/ports/stm/common-hal/pulseio/PulseOut.c @@ -45,7 +45,7 @@ STATIC uint8_t refcount = 0; STATIC uint16_t *pulse_array = NULL; STATIC volatile uint16_t pulse_array_index = 0; STATIC uint16_t pulse_array_length; -//Timer is shared, must be accessible by interrupt +// Timer is shared, must be accessible by interrupt STATIC TIM_HandleTypeDef tim_handle; STATIC pulseio_pulseout_obj_t *curr_pulseout = NULL; @@ -60,7 +60,7 @@ STATIC void turn_off(pulseio_pulseout_obj_t *pulseout) { HAL_TIM_PWM_Stop(&(pulseout->pwmout->handle), pulseout->pwmout->channel); // Make sure pin is low. HAL_GPIO_WritePin(pin_port(pulseout->pwmout->tim->pin->port), - pin_mask(pulseout->pwmout->tim->pin->number), 0); + pin_mask(pulseout->pwmout->tim->pin->number), 0); } STATIC void start_timer(void) { @@ -77,13 +77,11 @@ STATIC void start_timer(void) { STATIC void pulseout_event_handler(void) { // Detect TIM Update event - if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET) - { + if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET) { + if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(&tim_handle, TIM_IT_UPDATE); if (curr_pulseout->pwmout == NULL) { - return; //invalid interrupt + return; // invalid interrupt } pulse_array_index++; @@ -112,27 +110,27 @@ void pulseout_reset() { refcount = 0; } -void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, - const pwmio_pwmout_obj_t* carrier, - const mcu_pin_obj_t* pin, - uint32_t frequency, - uint16_t duty_cycle) { +void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self, + const pwmio_pwmout_obj_t *carrier, + const mcu_pin_obj_t *pin, + uint32_t frequency, + uint16_t duty_cycle) { if (!carrier || pin || frequency) { mp_raise_NotImplementedError(translate("Port does not accept pins or frequency. Construct and pass a PWMOut Carrier instead")); } // Add to active PulseOuts refcount++; - TIM_TypeDef * tim_instance = stm_peripherals_find_timer(); + TIM_TypeDef *tim_instance = stm_peripherals_find_timer(); stm_peripherals_timer_reserve(tim_instance); - //calculate a 1ms period + // calculate a 1ms period uint32_t source = stm_peripherals_timer_get_source_freq(tim_instance); - uint32_t prescaler = source/1000000; //1us intervals + uint32_t prescaler = source / 1000000; // 1us intervals stm_peripherals_timer_preinit(tim_instance, 4, pulseout_event_handler); tim_handle.Instance = tim_instance; - tim_handle.Init.Period = 100; //immediately replaced. + tim_handle.Init.Period = 100; // immediately replaced. tim_handle.Init.Prescaler = prescaler - 1; tim_handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; tim_handle.Init.CounterMode = TIM_COUNTERMODE_UP; @@ -142,15 +140,15 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, tim_handle.Instance->SR = 0; // The HAL can't work with const, recast required. - self->pwmout = (pwmio_pwmout_obj_t*)carrier; + self->pwmout = (pwmio_pwmout_obj_t *)carrier; turn_off(self); } -bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t* self) { +bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t *self) { return self->pwmout == NULL; } -void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { +void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t *self) { if (common_hal_pulseio_pulseout_deinited(self)) { return; } @@ -163,7 +161,7 @@ void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) { } } -void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pulses, uint16_t length) { +void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pulses, uint16_t length) { pulse_array = pulses; pulse_array_index = 0; pulse_array_length = length; @@ -177,7 +175,7 @@ void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pu // Use when debugging, or issues are irrecoverable // uint32_t starttime = supervisor_ticks_ms64(); // uint32_t timeout = 10000; - while(pulse_array_index < length) { + while (pulse_array_index < length) { // Do other things while we wait. The interrupts will handle sending the // signal. RUN_BACKGROUND_TASKS; @@ -187,6 +185,6 @@ void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pu // mp_raise_RuntimeError(translate("Error: Send Timeout")); // } } - //turn off timer counter. + // turn off timer counter. tim_handle.Instance->CR1 &= ~TIM_CR1_CEN; } diff --git a/ports/stm/common-hal/pwmio/PWMOut.c b/ports/stm/common-hal/pwmio/PWMOut.c index 85427185e..c463cac43 100644 --- a/ports/stm/common-hal/pwmio/PWMOut.c +++ b/ports/stm/common-hal/pwmio/PWMOut.c @@ -44,13 +44,13 @@ STATIC uint32_t tim_frequencies[TIM_BANK_ARRAY_LEN]; STATIC bool never_reset_tim[TIM_BANK_ARRAY_LEN]; STATIC uint32_t timer_get_internal_duty(uint16_t duty, uint32_t period) { - //duty cycle is duty/0xFFFF fraction x (number of pulses per period) - return (duty*period) / ((1 << 16) - 1); + // duty cycle is duty/0xFFFF fraction x (number of pulses per period) + return (duty * period) / ((1 << 16) - 1); } -STATIC void timer_get_optimal_divisors(uint32_t*period, uint32_t*prescaler, - uint32_t frequency, uint32_t source_freq) { - //Find the largest possible period supported by this frequency +STATIC void timer_get_optimal_divisors(uint32_t *period, uint32_t *prescaler, + uint32_t frequency, uint32_t source_freq) { + // Find the largest possible period supported by this frequency for (int i = 0; i < (1 << 16); i++) { *period = source_freq / (i * frequency); if (*period < (1 << 16) && *period >= 2) { @@ -75,12 +75,12 @@ void pwmout_reset(void) { } } -pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, - const mcu_pin_obj_t* pin, - uint16_t duty, - uint32_t frequency, - bool variable_frequency) { - TIM_TypeDef * TIMx; +pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, + const mcu_pin_obj_t *pin, + uint16_t duty, + uint32_t frequency, + bool variable_frequency) { + TIM_TypeDef *TIMx; uint8_t tim_num = MP_ARRAY_SIZE(mcu_tim_pin_list); bool tim_taken_internal = false; bool tim_chan_taken = false; @@ -89,47 +89,47 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, bool first_time_setup = true; for (uint i = 0; i < tim_num; i++) { - const mcu_tim_pin_obj_t * l_tim = &mcu_tim_pin_list[i]; + const mcu_tim_pin_obj_t *l_tim = &mcu_tim_pin_list[i]; uint8_t l_tim_index = l_tim->tim_index - 1; uint8_t l_tim_channel = l_tim->channel_index - 1; - //if pin is same + // if pin is same if (l_tim->pin == pin) { - //check if the timer has a channel active, or is reserved by main timer system + // check if the timer has a channel active, or is reserved by main timer system if (l_tim_index < TIM_BANK_ARRAY_LEN && reserved_tim[l_tim_index] != 0) { // Timer has already been reserved by an internal module if (stm_peripherals_timer_is_reserved(mcu_tim_banks[l_tim_index])) { tim_taken_internal = true; - continue; //keep looking + continue; // keep looking } - //is it the same channel? (or all channels reserved by a var-freq) + // is it the same channel? (or all channels reserved by a var-freq) if (reserved_tim[l_tim_index] & 1 << (l_tim_channel)) { tim_chan_taken = true; - continue; //keep looking, might be another viable option + continue; // keep looking, might be another viable option } - //If the frequencies are the same it's ok + // If the frequencies are the same it's ok if (tim_frequencies[l_tim_index] != frequency) { tim_taken_f_mismatch = true; - continue; //keep looking + continue; // keep looking } - //you can't put a variable frequency on a partially reserved timer + // you can't put a variable frequency on a partially reserved timer if (variable_frequency) { var_freq_mismatch = true; - continue; //keep looking + continue; // keep looking } - first_time_setup = false; //skip setting up the timer + first_time_setup = false; // skip setting up the timer } - //No problems taken, so set it up + // No problems taken, so set it up self->tim = l_tim; break; } } - //handle valid/invalid timer instance + // handle valid/invalid timer instance if (self->tim != NULL) { - //create instance + // create instance TIMx = mcu_tim_banks[self->tim->tim_index - 1]; - //reserve timer/channel + // reserve timer/channel if (variable_frequency) { reserved_tim[self->tim->tim_index - 1] = 0x0F; } else { @@ -137,7 +137,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, } tim_frequencies[self->tim->tim_index - 1] = frequency; stm_peripherals_timer_reserve(TIMx); - } else { //no match found + } else { // no match found if (tim_chan_taken) { mp_raise_ValueError(translate("No more timers available on this pin.")); } else if (tim_taken_internal) { @@ -161,15 +161,15 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, tim_clock_enable(1 << (self->tim->tim_index - 1)); - //translate channel into handle value + // translate channel into handle value self->channel = 4 * (self->tim->channel_index - 1); - uint32_t prescaler = 0; //prescaler is 15 bit - uint32_t period = 0; //period is 16 bit + uint32_t prescaler = 0; // prescaler is 15 bit + uint32_t period = 0; // period is 16 bit uint32_t source_freq = stm_peripherals_timer_get_source_freq(TIMx); timer_get_optimal_divisors(&period, &prescaler, frequency, source_freq); - //Timer init + // Timer init self->handle.Instance = TIMx; self->handle.Init.Period = period - 1; self->handle.Init.Prescaler = prescaler - 1; @@ -177,14 +177,14 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self, self->handle.Init.CounterMode = TIM_COUNTERMODE_UP; self->handle.Init.RepetitionCounter = 0; - //only run init if this is the first instance of this timer + // only run init if this is the first instance of this timer if (first_time_setup) { if (HAL_TIM_PWM_Init(&self->handle) != HAL_OK) { mp_raise_ValueError(translate("Could not initialize timer")); } } - //Channel/PWM init + // Channel/PWM init self->chan_handle.OCMode = TIM_OCMODE_PWM1; self->chan_handle.Pulse = timer_get_internal_duty(duty, period); self->chan_handle.OCPolarity = TIM_OCPOLARITY_HIGH; @@ -215,7 +215,7 @@ void common_hal_pwmio_pwmout_never_reset(pwmio_pwmout_obj_t *self) { } void common_hal_pwmio_pwmout_reset_ok(pwmio_pwmout_obj_t *self) { - for(size_t i = 0; i < TIM_BANK_ARRAY_LEN; i++) { + for (size_t i = 0; i < TIM_BANK_ARRAY_LEN; i++) { if (mcu_tim_banks[i] == self->handle.Instance) { never_reset_tim[i] = false; break; @@ -223,15 +223,15 @@ void common_hal_pwmio_pwmout_reset_ok(pwmio_pwmout_obj_t *self) { } } -bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) { return self->tim == NULL; } -void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { +void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) { if (common_hal_pwmio_pwmout_deinited(self)) { return; } - //var freq shuts down entire timer, others just their channel + // var freq shuts down entire timer, others just their channel if (self->variable_frequency) { reserved_tim[self->tim->tim_index - 1] = 0x00; } else { @@ -240,7 +240,7 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { } reset_pin_number(self->tim->pin->port,self->tim->pin->number); - //if reserved timer has no active channels, we can disable it + // if reserved timer has no active channels, we can disable it if (!reserved_tim[self->tim->tim_index - 1]) { tim_frequencies[self->tim->tim_index - 1] = 0x00; stm_peripherals_timer_free(self->handle.Instance); @@ -249,18 +249,18 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) { self->tim = NULL; } -void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t* self, uint16_t duty) { +void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t duty) { uint32_t internal_duty_cycle = timer_get_internal_duty(duty, self->period); __HAL_TIM_SET_COMPARE(&self->handle, self->channel, internal_duty_cycle); self->duty_cycle = duty; } -uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) { +uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) { return self->duty_cycle; } -void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t frequency) { - //don't halt setup for the same frequency +void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self, uint32_t frequency) { + // don't halt setup for the same frequency if (frequency == self->frequency) { return; } @@ -270,14 +270,14 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t fr uint32_t source_freq = stm_peripherals_timer_get_source_freq(self->handle.Instance); timer_get_optimal_divisors(&period, &prescaler, frequency, source_freq); - //shut down + // shut down HAL_TIM_PWM_Stop(&self->handle, self->channel); - //Only change altered values + // Only change altered values self->handle.Init.Period = period - 1; self->handle.Init.Prescaler = prescaler - 1; - //restart everything, adjusting for new speed + // restart everything, adjusting for new speed if (HAL_TIM_PWM_Init(&self->handle) != HAL_OK) { mp_raise_ValueError(translate("Could not re-init timer")); } @@ -296,10 +296,10 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self, uint32_t fr self->period = period; } -uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) { +uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) { return self->frequency; } -bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t* self) { +bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) { return self->variable_frequency; } diff --git a/ports/stm/common-hal/pwmio/PWMOut.h b/ports/stm/common-hal/pwmio/PWMOut.h index 5d8001202..4cf2b1c67 100644 --- a/ports/stm/common-hal/pwmio/PWMOut.h +++ b/ports/stm/common-hal/pwmio/PWMOut.h @@ -39,8 +39,8 @@ typedef struct { TIM_HandleTypeDef handle; TIM_OC_InitTypeDef chan_handle; const mcu_tim_pin_obj_t *tim; - uint8_t channel: 7; - bool variable_frequency: 1; + uint8_t channel : 7; + bool variable_frequency : 1; uint16_t duty_cycle; uint32_t frequency; uint32_t period; diff --git a/ports/stm/common-hal/rgbmatrix/RGBMatrix.c b/ports/stm/common-hal/rgbmatrix/RGBMatrix.c index 36ed6d018..4c0ad94b0 100644 --- a/ports/stm/common-hal/rgbmatrix/RGBMatrix.c +++ b/ports/stm/common-hal/rgbmatrix/RGBMatrix.c @@ -34,24 +34,24 @@ extern void _PM_IRQ_HANDLER(void); void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self) { - TIM_TypeDef * timer = stm_peripherals_find_timer(); + TIM_TypeDef *timer = stm_peripherals_find_timer(); stm_peripherals_timer_reserve(timer); stm_peripherals_timer_never_reset(timer); return timer; } -void common_hal_rgbmatrix_timer_enable(void* ptr) { - TIM_TypeDef *tim = (TIM_TypeDef*)ptr; +void common_hal_rgbmatrix_timer_enable(void *ptr) { + TIM_TypeDef *tim = (TIM_TypeDef *)ptr; HAL_NVIC_EnableIRQ(stm_peripherals_timer_get_irqnum(tim)); } -void common_hal_rgbmatrix_timer_disable(void* ptr) { - TIM_TypeDef *tim = (TIM_TypeDef*)ptr; +void common_hal_rgbmatrix_timer_disable(void *ptr) { + TIM_TypeDef *tim = (TIM_TypeDef *)ptr; tim->DIER &= ~TIM_DIER_UIE; } -void common_hal_rgbmatrix_timer_free(void* ptr) { - TIM_TypeDef *tim = (TIM_TypeDef*)ptr; +void common_hal_rgbmatrix_timer_free(void *ptr) { + TIM_TypeDef *tim = (TIM_TypeDef *)ptr; stm_peripherals_timer_free(tim); common_hal_rgbmatrix_timer_disable(ptr); } diff --git a/ports/stm/common-hal/rgbmatrix/RGBMatrix.h b/ports/stm/common-hal/rgbmatrix/RGBMatrix.h index 2debb6a76..cc4b82da0 100644 --- a/ports/stm/common-hal/rgbmatrix/RGBMatrix.h +++ b/ports/stm/common-hal/rgbmatrix/RGBMatrix.h @@ -30,8 +30,8 @@ #include "shared-module/rgbmatrix/RGBMatrix.h" void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self); -void common_hal_rgbmatrix_timer_enable(void*); -void common_hal_rgbmatrix_timer_disable(void*); -void common_hal_rgbmatrix_timer_free(void*); +void common_hal_rgbmatrix_timer_enable(void *); +void common_hal_rgbmatrix_timer_disable(void *); +void common_hal_rgbmatrix_timer_free(void *); #endif diff --git a/ports/stm/common-hal/sdioio/SDCard.c b/ports/stm/common-hal/sdioio/SDCard.c index de0e8d111..e09e2e1b3 100644 --- a/ports/stm/common-hal/sdioio/SDCard.c +++ b/ports/stm/common-hal/sdioio/SDCard.c @@ -40,18 +40,18 @@ STATIC bool reserved_sdio[MP_ARRAY_SIZE(mcu_sdio_banks)]; STATIC bool never_reset_sdio[MP_ARRAY_SIZE(mcu_sdio_banks)]; STATIC const mcu_periph_obj_t *find_pin_function(const mcu_periph_obj_t *table, size_t sz, const mcu_pin_obj_t *pin, int periph_index) { - for(size_t i = 0; i<sz; i++, table++) { - if(periph_index == table->periph_index && pin == table->pin ) { + for (size_t i = 0; i < sz; i++, table++) { + if (periph_index == table->periph_index && pin == table->pin) { return table; } } return NULL; } -//match pins to SDIO objects +// match pins to SDIO objects STATIC int check_pins(sdioio_sdcard_obj_t *self, - const mcu_pin_obj_t * clock, const mcu_pin_obj_t * command, - uint8_t num_data, mcu_pin_obj_t ** data) { + const mcu_pin_obj_t *clock, const mcu_pin_obj_t *command, + uint8_t num_data, mcu_pin_obj_t **data) { bool sdio_taken = false; const uint8_t sdio_clock_len = MP_ARRAY_SIZE(mcu_sdio_clock_list); @@ -78,26 +78,26 @@ STATIC int check_pins(sdioio_sdcard_obj_t *self, } const mcu_periph_obj_t *mcu_sdio_data0 = NULL; - if(!(mcu_sdio_data0 = find_pin_function(mcu_sdio_data0_list, sdio_data0_len, data[0], periph_index))) { + if (!(mcu_sdio_data0 = find_pin_function(mcu_sdio_data0_list, sdio_data0_len, data[0], periph_index))) { continue; } const mcu_periph_obj_t *mcu_sdio_data1 = NULL; - if(num_data > 1 && !(mcu_sdio_data1 = find_pin_function(mcu_sdio_data1_list, sdio_data1_len, data[1], periph_index))) { + if (num_data > 1 && !(mcu_sdio_data1 = find_pin_function(mcu_sdio_data1_list, sdio_data1_len, data[1], periph_index))) { continue; } const mcu_periph_obj_t *mcu_sdio_data2 = NULL; - if(num_data > 2 && !(mcu_sdio_data2 = find_pin_function(mcu_sdio_data2_list, sdio_data2_len, data[2], periph_index))) { + if (num_data > 2 && !(mcu_sdio_data2 = find_pin_function(mcu_sdio_data2_list, sdio_data2_len, data[2], periph_index))) { continue; } const mcu_periph_obj_t *mcu_sdio_data3 = NULL; - if(num_data > 3 && !(mcu_sdio_data3 = find_pin_function(mcu_sdio_data3_list, sdio_data3_len, data[3], periph_index))) { + if (num_data > 3 && !(mcu_sdio_data3 = find_pin_function(mcu_sdio_data3_list, sdio_data3_len, data[3], periph_index))) { continue; } - if (reserved_sdio[periph_index-1]) { + if (reserved_sdio[periph_index - 1]) { sdio_taken = true; continue; } @@ -121,16 +121,16 @@ STATIC int check_pins(sdioio_sdcard_obj_t *self, void common_hal_sdioio_sdcard_construct(sdioio_sdcard_obj_t *self, - const mcu_pin_obj_t * clock, const mcu_pin_obj_t * command, - uint8_t num_data, mcu_pin_obj_t ** data, uint32_t frequency) { + const mcu_pin_obj_t *clock, const mcu_pin_obj_t *command, + uint8_t num_data, mcu_pin_obj_t **data, uint32_t frequency) { int periph_index = check_pins(self, clock, command, num_data, data); - SDIO_TypeDef * SDIOx = mcu_sdio_banks[periph_index - 1]; + SDIO_TypeDef *SDIOx = mcu_sdio_banks[periph_index - 1]; GPIO_InitTypeDef GPIO_InitStruct = {0}; /* Configure data pins */ - for (int i=0; i<num_data; i++) { + for (int i = 0; i < num_data; i++) { GPIO_InitStruct.Pin = pin_mask(data[i]->number); GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -186,7 +186,7 @@ void common_hal_sdioio_sdcard_construct(sdioio_sdcard_obj_t *self, common_hal_mcu_pin_claim(clock); common_hal_mcu_pin_claim(command); - for (int i=0; i<num_data; i++) { + for (int i = 0; i < num_data; i++) { common_hal_mcu_pin_claim(data[i]); } @@ -217,7 +217,7 @@ STATIC void wait_write_complete(sdioio_sdcard_obj_t *self) { // This waits up to 60s for programming to complete. This seems like // an extremely long time, but this is the timeout that micropython's // implementation uses - for (int i=0; i < 60000 && st == HAL_SD_CARD_PROGRAMMING; i++) { + for (int i = 0; i < 60000 && st == HAL_SD_CARD_PROGRAMMING; i++) { st = HAL_SD_GetCardState(&self->handle); HAL_Delay(1); }; @@ -293,7 +293,7 @@ void common_hal_sdioio_sdcard_deinit(sdioio_sdcard_obj_t *self) { reset_mcu_periph(self->clock); self->command = NULL; - for (size_t i=0; i<MP_ARRAY_SIZE(self->data); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(self->data); i++) { reset_mcu_periph(self->data[i]); self->data[i] = NULL; } @@ -313,13 +313,13 @@ void common_hal_sdioio_sdcard_never_reset(sdioio_sdcard_obj_t *self) { never_reset_mcu_periph(self->command); never_reset_mcu_periph(self->clock); - for (size_t i=0; i<MP_ARRAY_SIZE(self->data); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(self->data); i++) { never_reset_mcu_periph(self->data[i]); } } void sdioio_reset() { - for (size_t i=0; i<MP_ARRAY_SIZE(reserved_sdio); i++) { + for (size_t i = 0; i < MP_ARRAY_SIZE(reserved_sdio); i++) { if (!never_reset_sdio[i]) { reserved_sdio[i] = false; } diff --git a/ports/stm/common-hal/sdioio/SDCard.h b/ports/stm/common-hal/sdioio/SDCard.h index b737b6939..845a5aa5f 100644 --- a/ports/stm/common-hal/sdioio/SDCard.h +++ b/ports/stm/common-hal/sdioio/SDCard.h @@ -36,7 +36,7 @@ typedef struct { mp_obj_base_t base; SD_HandleTypeDef handle; - uint8_t num_data:3, state_programming:1; + uint8_t num_data : 3, state_programming : 1; bool has_lock; const mcu_periph_obj_t *command; const mcu_periph_obj_t *clock; diff --git a/ports/stm/common-hal/supervisor/Runtime.c b/ports/stm/common-hal/supervisor/Runtime.c index 974f26cec..f82765178 100755..100644 --- a/ports/stm/common-hal/supervisor/Runtime.c +++ b/ports/stm/common-hal/supervisor/Runtime.c @@ -29,9 +29,9 @@ #include "supervisor/serial.h" bool common_hal_supervisor_runtime_get_serial_connected(void) { - return (bool) serial_connected(); + return (bool)serial_connected(); } bool common_hal_supervisor_runtime_get_serial_bytes_available(void) { - return (bool) serial_bytes_available(); + return (bool)serial_bytes_available(); } diff --git a/ports/stm/hal_conf/stm32f4xx_hal_conf.h b/ports/stm/hal_conf/stm32f4xx_hal_conf.h index ad8939052..7fb3b77e5 100644 --- a/ports/stm/hal_conf/stm32f4xx_hal_conf.h +++ b/ports/stm/hal_conf/stm32f4xx_hal_conf.h @@ -26,7 +26,7 @@ #define __STM32F4xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -38,11 +38,11 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined(HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ -#if !defined (HSE_STARTUP_TIMEOUT) +#if !defined(HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ @@ -51,14 +51,14 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSI is used as system clock source, directly or through the PLL). */ -#if !defined (HSI_VALUE) +#if !defined(HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined(LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -66,11 +66,11 @@ /** * @brief External Low Speed oscillator (LSE) value. */ -#if !defined (LSE_VALUE) +#if !defined(LSE_VALUE) #define LSE_VALUE 32768 /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) +#if !defined(LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ @@ -80,7 +80,7 @@ * This value is used by the I2S HAL module to compute the I2S clock source * frequency, this source is inserted directly through I2S_CKIN pad. */ -#if !defined (EXTERNAL_CLOCK_VALUE) +#if !defined(EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ @@ -371,7 +371,7 @@ */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); +void assert_failed(uint8_t *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ diff --git a/ports/stm/hal_conf/stm32f7xx_hal_conf.h b/ports/stm/hal_conf/stm32f7xx_hal_conf.h index 3dd368e85..72cb60e44 100644 --- a/ports/stm/hal_conf/stm32f7xx_hal_conf.h +++ b/ports/stm/hal_conf/stm32f7xx_hal_conf.h @@ -26,7 +26,7 @@ #define __STM32F7xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -38,11 +38,11 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined(HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ -#if !defined (HSE_STARTUP_TIMEOUT) +#if !defined(HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ @@ -51,14 +51,14 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSI is used as system clock source, directly or through the PLL). */ -#if !defined (HSI_VALUE) +#if !defined(HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined(LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -66,11 +66,11 @@ /** * @brief External Low Speed oscillator (LSE) value. */ -#if !defined (LSE_VALUE) +#if !defined(LSE_VALUE) #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) +#if !defined(LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ @@ -79,7 +79,7 @@ * This value is used by the I2S HAL module to compute the I2S clock source * frequency, this source is inserted directly through I2S_CKIN pad. */ -#if !defined (EXTERNAL_CLOCK_VALUE) +#if !defined(EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ @@ -376,7 +376,7 @@ */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); +void assert_failed(uint8_t *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ diff --git a/ports/stm/hal_conf/stm32h7xx_hal_conf.h b/ports/stm/hal_conf/stm32h7xx_hal_conf.h index a0328610c..630e63b8f 100644 --- a/ports/stm/hal_conf/stm32h7xx_hal_conf.h +++ b/ports/stm/hal_conf/stm32h7xx_hal_conf.h @@ -24,7 +24,7 @@ #define __STM32H7xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -36,11 +36,11 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined(HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ #endif /* HSE_VALUE */ -#if !defined (HSE_STARTUP_TIMEOUT) +#if !defined(HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ @@ -48,7 +48,7 @@ * @brief Internal oscillator (CSI) default value. * This value is the default CSI value after Reset. */ -#if !defined (CSI_VALUE) +#if !defined(CSI_VALUE) #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* CSI_VALUE */ @@ -57,14 +57,14 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSI is used as system clock source, directly or through the PLL). */ -#if !defined (HSI_VALUE) +#if !defined(HSI_VALUE) #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined(LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -74,11 +74,11 @@ * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */ -#if !defined (LSE_VALUE) +#if !defined(LSE_VALUE) #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) +#if !defined(LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ @@ -87,7 +87,7 @@ * This value is used by the I2S HAL module to compute the I2S clock source * frequency, this source is inserted directly through I2S_CKIN pad. */ -#if !defined (EXTERNAL_CLOCK_VALUE) +#if !defined(EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ @@ -421,7 +421,7 @@ */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); +void assert_failed(uint8_t *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ diff --git a/ports/stm/mpconfigport.h b/ports/stm/mpconfigport.h index 3f64e6565..4ac8c20ea 100644 --- a/ports/stm/mpconfigport.h +++ b/ports/stm/mpconfigport.h @@ -37,7 +37,7 @@ extern uint8_t _ld_default_stack_size; // 24kiB stack // #define CIRCUITPY_DEFAULT_STACK_SIZE 0x6000 -#define CIRCUITPY_DEFAULT_STACK_SIZE ((uint32_t) &_ld_default_stack_size) +#define CIRCUITPY_DEFAULT_STACK_SIZE ((uint32_t)&_ld_default_stack_size) #include "py/circuitpy_mpconfig.h" @@ -60,6 +60,6 @@ extern uint8_t _ld_default_stack_size; #define MICROPY_PORT_ROOT_POINTERS \ void *cpy_uart_obj_all[MAX_UART]; \ void *cpy_i2c_obj_all[MAX_I2C]; \ - CIRCUITPY_COMMON_ROOT_POINTERS + CIRCUITPY_COMMON_ROOT_POINTERS #endif // __INCLUDED_MPCONFIGPORT_H diff --git a/ports/stm/mphalport.h b/ports/stm/mphalport.h index 2c4caf3b2..cf175b526 100644 --- a/ports/stm/mphalport.h +++ b/ports/stm/mphalport.h @@ -35,7 +35,7 @@ // Global millisecond tick count (driven by SysTick interrupt). static inline mp_uint_t mp_hal_ticks_ms(void) { - return supervisor_ticks_ms32(); + return supervisor_ticks_ms32(); } // Number of bytes in receive buffer extern volatile uint8_t usb_rx_count; diff --git a/ports/stm/packages/LQFP100_f4.c b/ports/stm/packages/LQFP100_f4.c index 9136b9495..f1c3cc367 100644 --- a/ports/stm/packages/LQFP100_f4.c +++ b/ports/stm/packages/LQFP100_f4.c @@ -4,114 +4,114 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // Pins 1-25 - { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, - /* VBAT -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - // PC14 OSC32_IN ----------------------------------*/ - // PC15 OSC32_OUT ---------------------------------*/ - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - // PH0 OSC_IN -------------------------------------*/ - // PH1 OSC_OUT ------------------------------------*/ - // NRST -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - // VDD --------------------------------------------*/ - // VSSA -------------------------------------------*/ - // VREF+ ------------------------------------------*/ - // VDDA -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + // VDD --------------------------------------------*/ + // VSSA -------------------------------------------*/ + // VREF+ ------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, // Pins 26-50 - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, - { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, - { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, - { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, - { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, - { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, - { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, - { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, - { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, -#if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx) - { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, -#endif //or VCAP1 -----------------------------------*/ - // VCAP1 or VSS -----------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + #if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx) + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + #endif // or VCAP1 -----------------------------------*/ + // VCAP1 or VSS -----------------------------------*/ + // VDD --------------------------------------------*/ // Pins 51-75 - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, - { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, - { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, - { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, - { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - // VCAP2 ------------------------------------------*/ - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VCAP2 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ // Pins 76-100 - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, - { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, - { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, - { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, - { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, - { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, - { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - // BOOT0 ------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/LQFP100_x7.c b/ports/stm/packages/LQFP100_x7.c index 4d3d5f45a..77a887b0d 100644 --- a/ports/stm/packages/LQFP100_x7.c +++ b/ports/stm/packages/LQFP100_x7.c @@ -4,112 +4,112 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // Pins 1-25 - { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, - /* VBAT -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - // PC14 OSC32_IN ----------------------------------*/ - // PC15 OSC32_OUT ---------------------------------*/ - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - // PH0 OSC_IN -------------------------------------*/ - // PH1 OSC_OUT ------------------------------------*/ - // NRST -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - // VSSA -------------------------------------------*/ - // VREF+ ------------------------------------------*/ - // VDDA -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + // VSSA -------------------------------------------*/ + // VREF+ ------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, // Pins 26-50 - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, - { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, - { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, - { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, - { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, - { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, - { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, - { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, - { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, - // VCAP1 ------------------------------------------*/ - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + // VCAP1 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ // Pins 51-75 - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, - { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, - { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, - { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, - { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - // VCAP2 ------------------------------------------*/ - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VCAP2 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ // Pins 76-100 - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, - { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, - { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, - { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, - { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, - { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, - { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - // BOOT0 ------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/LQFP144.c b/ports/stm/packages/LQFP144.c index 5e0d743d7..a08d16086 100644 --- a/ports/stm/packages/LQFP144.c +++ b/ports/stm/packages/LQFP144.c @@ -4,156 +4,156 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // Pins 1-36 - { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, - /* VBAT -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - // PC14 OSC32_IN ----------------------------------*/ - // PC15 OSC32_OUT ---------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) }, - { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) }, - { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, - { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, - { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) }, - { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) }, - { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) }, - { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) }, - { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) }, - { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, - // PH0 OSC_IN -------------------------------------*/ - // PH1 OSC_OUT ------------------------------------*/ - // NRST -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - // VDD --------------------------------------------*/ - // VSSA -------------------------------------------*/ - // VREF+ ------------------------------------------*/ - // VDDA -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) }, + { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) }, + { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, + { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) }, + { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) }, + { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) }, + { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) }, + { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) }, + { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + // VDD --------------------------------------------*/ + // VSSA -------------------------------------------*/ + // VREF+ ------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, // Pins 37-72 - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, - { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, - { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) }, - { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) }, - { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) }, - { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) }, - { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, - { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, - { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, - { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, - { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, - { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, - { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, - { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, - // VCAP1 ------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, + { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, + { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) }, + { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) }, + { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) }, + { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + // VCAP1 ------------------------------------------*/ + // VDD --------------------------------------------*/ // Pins 73-108 - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, - { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, - { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, - { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, - { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, - { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, - { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) }, - { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) }, - { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) }, - { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) }, - { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) }, - { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) }, - // VSS --------------------------------------------*/ - // VDD or VDD_USB (F412, F446) --------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - // VCAP2 ------------------------------------------*/ - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) }, + { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) }, + { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) }, + { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) }, + { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) }, + { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) }, + // VSS --------------------------------------------*/ + // VDD or VDD_USB (F412, F446) --------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VCAP2 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ // Pins 109-144 - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, - { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, - { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, - { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, - { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, - { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, - { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, - { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, - { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, - { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, - { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, - { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - // BOOT0 ------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, - // PDR_ON -----------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, + { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, + { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, + { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, + { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, + { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + // PDR_ON -----------------------------------------*/ + // VDD --------------------------------------------*/ }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/LQFP64.c b/ports/stm/packages/LQFP64.c index 52ca27cd9..71e8be978 100644 --- a/ports/stm/packages/LQFP64.c +++ b/ports/stm/packages/LQFP64.c @@ -4,78 +4,78 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // Pins 1-16 - /* VBAT -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - // PC14 OSC32_IN ----------------------------------*/ - // PC15 OSC32_OUT ---------------------------------*/ - // PH0 OSC_IN -------------------------------------*/ - // PH1 OSC_OUT ------------------------------------*/ - // NRST -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - // VSSA -------------------------------------------*/ - // VDDA -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + // VSSA -------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, // Pins 17-32 - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, -#if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx) - { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, -#endif //or VCAP1 -----------------------------------*/ - // VCAP1 or VSS -----------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + #if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx) + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + #endif // or VCAP1 -----------------------------------*/ + // VCAP1 or VSS -----------------------------------*/ + // VDD --------------------------------------------*/ // Pins 33-48 - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - // VSS or VCAP (F405) -----------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VSS or VCAP (F405) -----------------------------*/ + // VDD --------------------------------------------*/ // Pins 49-64 - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, - { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - // BOOT0 ------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/TFBGA216.c b/ports/stm/packages/TFBGA216.c index af91e70ae..ebcae5f2d 100644 --- a/ports/stm/packages/TFBGA216.c +++ b/ports/stm/packages/TFBGA216.c @@ -31,201 +31,201 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // Row A - { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, - { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, - { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, - { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, // Row B - { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, - { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) }, - { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, - { MP_ROM_QSTR(MP_QSTR_PJ13), MP_ROM_PTR(&pin_PJ13) }, - { MP_ROM_QSTR(MP_QSTR_PJ12), MP_ROM_PTR(&pin_PJ12) }, - { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, - { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) }, + { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, + { MP_ROM_QSTR(MP_QSTR_PJ13), MP_ROM_PTR(&pin_PJ13) }, + { MP_ROM_QSTR(MP_QSTR_PJ12), MP_ROM_PTR(&pin_PJ12) }, + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, // Row C - { MP_ROM_QSTR(MP_QSTR_PI08), MP_ROM_PTR(&pin_PI08) }, - { MP_ROM_QSTR(MP_QSTR_PI04), MP_ROM_PTR(&pin_PI04) }, - { MP_ROM_QSTR(MP_QSTR_PK07), MP_ROM_PTR(&pin_PK07) }, - { MP_ROM_QSTR(MP_QSTR_PK06), MP_ROM_PTR(&pin_PK06) }, - { MP_ROM_QSTR(MP_QSTR_PK05), MP_ROM_PTR(&pin_PK05) }, - { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, - { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, - { MP_ROM_QSTR(MP_QSTR_PJ14), MP_ROM_PTR(&pin_PJ14) }, - { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, - { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, - { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, - { MP_ROM_QSTR(MP_QSTR_PI03), MP_ROM_PTR(&pin_PI03) }, - { MP_ROM_QSTR(MP_QSTR_PI02), MP_ROM_PTR(&pin_PI02) }, - { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PI08), MP_ROM_PTR(&pin_PI08) }, + { MP_ROM_QSTR(MP_QSTR_PI04), MP_ROM_PTR(&pin_PI04) }, + { MP_ROM_QSTR(MP_QSTR_PK07), MP_ROM_PTR(&pin_PK07) }, + { MP_ROM_QSTR(MP_QSTR_PK06), MP_ROM_PTR(&pin_PK06) }, + { MP_ROM_QSTR(MP_QSTR_PK05), MP_ROM_PTR(&pin_PK05) }, + { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, + { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, + { MP_ROM_QSTR(MP_QSTR_PJ14), MP_ROM_PTR(&pin_PJ14) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PI03), MP_ROM_PTR(&pin_PI03) }, + { MP_ROM_QSTR(MP_QSTR_PI02), MP_ROM_PTR(&pin_PI02) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, // Row D - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) }, - { MP_ROM_QSTR(MP_QSTR_PI05), MP_ROM_PTR(&pin_PI05) }, - { MP_ROM_QSTR(MP_QSTR_PI07), MP_ROM_PTR(&pin_PI07) }, - { MP_ROM_QSTR(MP_QSTR_PI10), MP_ROM_PTR(&pin_PI10) }, - { MP_ROM_QSTR(MP_QSTR_PI06), MP_ROM_PTR(&pin_PI06) }, - { MP_ROM_QSTR(MP_QSTR_PK04), MP_ROM_PTR(&pin_PK04) }, - { MP_ROM_QSTR(MP_QSTR_PK03), MP_ROM_PTR(&pin_PK03) }, - { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, - { MP_ROM_QSTR(MP_QSTR_PJ15), MP_ROM_PTR(&pin_PJ15) }, - { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, - { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_PH15), MP_ROM_PTR(&pin_PH15) }, - { MP_ROM_QSTR(MP_QSTR_PI01), MP_ROM_PTR(&pin_PI01) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) }, + { MP_ROM_QSTR(MP_QSTR_PI05), MP_ROM_PTR(&pin_PI05) }, + { MP_ROM_QSTR(MP_QSTR_PI07), MP_ROM_PTR(&pin_PI07) }, + { MP_ROM_QSTR(MP_QSTR_PI10), MP_ROM_PTR(&pin_PI10) }, + { MP_ROM_QSTR(MP_QSTR_PI06), MP_ROM_PTR(&pin_PI06) }, + { MP_ROM_QSTR(MP_QSTR_PK04), MP_ROM_PTR(&pin_PK04) }, + { MP_ROM_QSTR(MP_QSTR_PK03), MP_ROM_PTR(&pin_PK03) }, + { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, + { MP_ROM_QSTR(MP_QSTR_PJ15), MP_ROM_PTR(&pin_PJ15) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PH15), MP_ROM_PTR(&pin_PH15) }, + { MP_ROM_QSTR(MP_QSTR_PI01), MP_ROM_PTR(&pin_PI01) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, // Row E - // { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) }, // OSC32_IN - { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) }, - { MP_ROM_QSTR(MP_QSTR_PI12), MP_ROM_PTR(&pin_PI12) }, - { MP_ROM_QSTR(MP_QSTR_PI09), MP_ROM_PTR(&pin_PI09) }, - { MP_ROM_QSTR(MP_QSTR_PH13), MP_ROM_PTR(&pin_PH13) }, - { MP_ROM_QSTR(MP_QSTR_PH14), MP_ROM_PTR(&pin_PH14) }, - { MP_ROM_QSTR(MP_QSTR_PI00), MP_ROM_PTR(&pin_PI00) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + // { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) }, // OSC32_IN + { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) }, + { MP_ROM_QSTR(MP_QSTR_PI12), MP_ROM_PTR(&pin_PI12) }, + { MP_ROM_QSTR(MP_QSTR_PI09), MP_ROM_PTR(&pin_PI09) }, + { MP_ROM_QSTR(MP_QSTR_PH13), MP_ROM_PTR(&pin_PH13) }, + { MP_ROM_QSTR(MP_QSTR_PH14), MP_ROM_PTR(&pin_PH14) }, + { MP_ROM_QSTR(MP_QSTR_PI00), MP_ROM_PTR(&pin_PI00) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, // Row F - // { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) }, // OSC32_OUT - { MP_ROM_QSTR(MP_QSTR_PK01), MP_ROM_PTR(&pin_PK01) }, - { MP_ROM_QSTR(MP_QSTR_PK02), MP_ROM_PTR(&pin_PK02) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + // { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) }, // OSC32_OUT + { MP_ROM_QSTR(MP_QSTR_PK01), MP_ROM_PTR(&pin_PK01) }, + { MP_ROM_QSTR(MP_QSTR_PK02), MP_ROM_PTR(&pin_PK02) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, // Row G - // { MP_ROM_QSTR(MP_QSTR_PH00), MP_ROM_PTR(&pin_PH00) }, // OSC_IN - { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, - { MP_ROM_QSTR(MP_QSTR_PI13), MP_ROM_PTR(&pin_PI13) }, - { MP_ROM_QSTR(MP_QSTR_PI15), MP_ROM_PTR(&pin_PI15) }, - { MP_ROM_QSTR(MP_QSTR_PJ11), MP_ROM_PTR(&pin_PJ11) }, - { MP_ROM_QSTR(MP_QSTR_PK00), MP_ROM_PTR(&pin_PK00) }, - { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + // { MP_ROM_QSTR(MP_QSTR_PH00), MP_ROM_PTR(&pin_PH00) }, // OSC_IN + { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, + { MP_ROM_QSTR(MP_QSTR_PI13), MP_ROM_PTR(&pin_PI13) }, + { MP_ROM_QSTR(MP_QSTR_PI15), MP_ROM_PTR(&pin_PI15) }, + { MP_ROM_QSTR(MP_QSTR_PJ11), MP_ROM_PTR(&pin_PJ11) }, + { MP_ROM_QSTR(MP_QSTR_PK00), MP_ROM_PTR(&pin_PK00) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, // Row H - // { MP_ROM_QSTR(MP_QSTR_PH01), MP_ROM_PTR(&pin_PH01) }, // OSC_OUT - { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, - { MP_ROM_QSTR(MP_QSTR_PI14), MP_ROM_PTR(&pin_PI14) }, - { MP_ROM_QSTR(MP_QSTR_PH04), MP_ROM_PTR(&pin_PH04) }, - { MP_ROM_QSTR(MP_QSTR_PJ08), MP_ROM_PTR(&pin_PJ08) }, - { MP_ROM_QSTR(MP_QSTR_PJ10), MP_ROM_PTR(&pin_PJ10) }, - { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) }, - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + // { MP_ROM_QSTR(MP_QSTR_PH01), MP_ROM_PTR(&pin_PH01) }, // OSC_OUT + { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_PI14), MP_ROM_PTR(&pin_PI14) }, + { MP_ROM_QSTR(MP_QSTR_PH04), MP_ROM_PTR(&pin_PH04) }, + { MP_ROM_QSTR(MP_QSTR_PJ08), MP_ROM_PTR(&pin_PJ08) }, + { MP_ROM_QSTR(MP_QSTR_PJ10), MP_ROM_PTR(&pin_PJ10) }, + { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, // Row J - { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) }, - { MP_ROM_QSTR(MP_QSTR_PH05), MP_ROM_PTR(&pin_PH05) }, - { MP_ROM_QSTR(MP_QSTR_PH03), MP_ROM_PTR(&pin_PH03) }, - { MP_ROM_QSTR(MP_QSTR_PJ07), MP_ROM_PTR(&pin_PJ07) }, - { MP_ROM_QSTR(MP_QSTR_PJ09), MP_ROM_PTR(&pin_PJ09) }, - { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) }, - { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) }, + { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) }, + { MP_ROM_QSTR(MP_QSTR_PH05), MP_ROM_PTR(&pin_PH05) }, + { MP_ROM_QSTR(MP_QSTR_PH03), MP_ROM_PTR(&pin_PH03) }, + { MP_ROM_QSTR(MP_QSTR_PJ07), MP_ROM_PTR(&pin_PJ07) }, + { MP_ROM_QSTR(MP_QSTR_PJ09), MP_ROM_PTR(&pin_PJ09) }, + { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) }, + { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) }, // Row K - { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) }, - { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) }, - { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) }, - { MP_ROM_QSTR(MP_QSTR_PH02), MP_ROM_PTR(&pin_PH02) }, - { MP_ROM_QSTR(MP_QSTR_PJ06), MP_ROM_PTR(&pin_PJ06) }, - { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) }, + { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) }, + { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) }, + { MP_ROM_QSTR(MP_QSTR_PH02), MP_ROM_PTR(&pin_PH02) }, + { MP_ROM_QSTR(MP_QSTR_PJ06), MP_ROM_PTR(&pin_PJ06) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, // Row L - { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, - { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) }, - { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, - { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, + { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) }, + { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, // Row M - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) }, - { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) }, - { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) }, - { MP_ROM_QSTR(MP_QSTR_PJ04), MP_ROM_PTR(&pin_PJ04) }, - { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) }, - { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, - { MP_ROM_QSTR(MP_QSTR_PJ05), MP_ROM_PTR(&pin_PJ05) }, - { MP_ROM_QSTR(MP_QSTR_PH12), MP_ROM_PTR(&pin_PH12) }, + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) }, + { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) }, + { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) }, + { MP_ROM_QSTR(MP_QSTR_PJ04), MP_ROM_PTR(&pin_PJ04) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) }, + { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_PJ05), MP_ROM_PTR(&pin_PJ05) }, + { MP_ROM_QSTR(MP_QSTR_PH12), MP_ROM_PTR(&pin_PH12) }, // Row N - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, - { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) }, - { MP_ROM_QSTR(MP_QSTR_PJ03), MP_ROM_PTR(&pin_PJ03) }, - { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, - { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, - { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) }, - { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) }, - { MP_ROM_QSTR(MP_QSTR_PH07), MP_ROM_PTR(&pin_PH07) }, - { MP_ROM_QSTR(MP_QSTR_PH09), MP_ROM_PTR(&pin_PH09) }, - { MP_ROM_QSTR(MP_QSTR_PH11), MP_ROM_PTR(&pin_PH11) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, + { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) }, + { MP_ROM_QSTR(MP_QSTR_PJ03), MP_ROM_PTR(&pin_PJ03) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) }, + { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) }, + { MP_ROM_QSTR(MP_QSTR_PH07), MP_ROM_PTR(&pin_PH07) }, + { MP_ROM_QSTR(MP_QSTR_PH09), MP_ROM_PTR(&pin_PH09) }, + { MP_ROM_QSTR(MP_QSTR_PH11), MP_ROM_PTR(&pin_PH11) }, // Row P - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) }, - { MP_ROM_QSTR(MP_QSTR_PJ02), MP_ROM_PTR(&pin_PJ02) }, - { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, - { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, - { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, - { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, - { MP_ROM_QSTR(MP_QSTR_PH06), MP_ROM_PTR(&pin_PH06) }, - { MP_ROM_QSTR(MP_QSTR_PH08), MP_ROM_PTR(&pin_PH08) }, - { MP_ROM_QSTR(MP_QSTR_PH10), MP_ROM_PTR(&pin_PH10) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) }, + { MP_ROM_QSTR(MP_QSTR_PJ02), MP_ROM_PTR(&pin_PJ02) }, + { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_PH06), MP_ROM_PTR(&pin_PH06) }, + { MP_ROM_QSTR(MP_QSTR_PH08), MP_ROM_PTR(&pin_PH08) }, + { MP_ROM_QSTR(MP_QSTR_PH10), MP_ROM_PTR(&pin_PH10) }, // Row R - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PJ00), MP_ROM_PTR(&pin_PJ00) }, - { MP_ROM_QSTR(MP_QSTR_PJ01), MP_ROM_PTR(&pin_PJ01) }, - { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, - { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, - { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, - { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, - { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, - { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PJ00), MP_ROM_PTR(&pin_PJ00) }, + { MP_ROM_QSTR(MP_QSTR_PJ01), MP_ROM_PTR(&pin_PJ01) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/UFQFPN48.c b/ports/stm/packages/UFQFPN48.c index 5304482ec..b45fc9c98 100644 --- a/ports/stm/packages/UFQFPN48.c +++ b/ports/stm/packages/UFQFPN48.c @@ -4,60 +4,60 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // Pins 1-12 - /* VBAT -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, - // PC14 OSC32_IN ----------------------------------*/ - // PC15 OSC32_OUT ---------------------------------*/ - // PH0 OSC_IN -------------------------------------*/ - // PH1 OSC_OUT ------------------------------------*/ - // NRST -------------------------------------------*/ - // VSSA -------------------------------------------*/ - // VDDA -------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + // VSSA -------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, // Pins 13-24 - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, - // VCAP1 ------------------------------------------*/ - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + // VCAP1 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ // Pins 25-36 - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ // Pins 37-48 - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - // BOOT0 ------------------------------------------*/ - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, - // VSS --------------------------------------------*/ - // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index 34089c849..488541d09 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -36,34 +36,34 @@ // Comm Peripherals typedef struct { - uint8_t periph_index:4; // Index of the peripheral instance - uint8_t altfn_index:4; // Index of the altfn for this pin (0 to 15) - const mcu_pin_obj_t * pin; // Pin Object + uint8_t periph_index : 4; // Index of the peripheral instance + uint8_t altfn_index : 4; // Index of the altfn for this pin (0 to 15) + const mcu_pin_obj_t *pin; // Pin Object } mcu_periph_obj_t; #define PERIPH(index, alt, p_pin) \ -{ \ - .periph_index = index, \ - .altfn_index = alt, \ - .pin = p_pin, \ -} + { \ + .periph_index = index, \ + .altfn_index = alt, \ + .pin = p_pin, \ + } // Timer Peripheral typedef struct { - uint8_t tim_index:4; - uint8_t altfn_index:4; - uint8_t channel_index:4; - const mcu_pin_obj_t * pin; + uint8_t tim_index : 4; + uint8_t altfn_index : 4; + uint8_t channel_index : 4; + const mcu_pin_obj_t *pin; } mcu_tim_pin_obj_t; #define TIM(index, alt, channel, tim_pin) \ -{ \ - .tim_index = index, \ - .altfn_index = alt, \ - .channel_index = channel, \ - .pin = tim_pin, \ -} + { \ + .tim_index = index, \ + .altfn_index = alt, \ + .channel_index = channel, \ + .pin = tim_pin, \ + } // F4 Series // Access Lines diff --git a/ports/stm/peripherals/pins.h b/ports/stm/peripherals/pins.h index 358313f56..4a516864b 100644 --- a/ports/stm/peripherals/pins.h +++ b/ports/stm/peripherals/pins.h @@ -37,21 +37,21 @@ typedef struct { mp_obj_base_t base; - uint8_t port:4; - uint8_t number:4; - uint8_t adc_unit:3; - uint8_t adc_channel:5; + uint8_t port : 4; + uint8_t number : 4; + uint8_t adc_unit : 3; + uint8_t adc_channel : 5; } mcu_pin_obj_t; -//Standard stm32 adc unit combinations +// Standard stm32 adc unit combinations #define ADC_1 1 #define ADC_12 3 #define ADC_123 7 #define ADC_3 4 -//STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin, -//but all 3 ADCs will share the same input number per pin. -//F4 family has 3 ADC max, 24 channels max. +// STM32 ADC pins can have a combination of 1, 2 or all 3 ADCs on a single pin, +// but all 3 ADCs will share the same input number per pin. +// F4 family has 3 ADC max, 24 channels max. #define ADC_INPUT(mask, number) \ .adc_unit = mask, \ .adc_channel = number, @@ -65,12 +65,12 @@ extern const mp_obj_type_t mcu_pin_type; // STM32 can have up to 9 ports, each restricted to 16 pins // We split the pin/port evenly, in contrast to nrf. #define PIN(p_port, p_number, p_adc) \ -{ \ - { &mcu_pin_type }, \ - .port = p_port, \ - .number = p_number, \ - p_adc \ -} + { \ + { &mcu_pin_type }, \ + .port = p_port, \ + .number = p_number, \ + p_adc \ + } // Use illegal pin value to mark unassigned pins. #define NO_PIN 0xff diff --git a/ports/stm/peripherals/stm32f4/clocks.c b/ports/stm/peripherals/stm32f4/clocks.c index c2d0a452a..a98b38946 100644 --- a/ports/stm/peripherals/stm32f4/clocks.c +++ b/ports/stm/peripherals/stm32f4/clocks.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the Micro Python project, http://micropython.org/ * * The MIT License (MIT) @@ -66,7 +66,7 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000; RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; @@ -74,10 +74,12 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.PLL.PLLR = 2; // Unused but required by HAL #endif - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { // Clock issues are too problematic to even attempt recovery. // If you end up here, check whether your LSE settings match your board. - while(1); + while (1) { + ; + } } // Configure bus clock sources and divisors @@ -98,7 +100,7 @@ void stm32_peripherals_clocks_init(void) { #endif #if (CPY_CLK_USB_USES_AUDIOPLL) // Not supported by all lines. Should always result in 48M. - PeriphClkInitStruct.PLLI2S.PLLI2SM = HSE_VALUE/1000000; + PeriphClkInitStruct.PLLI2S.PLLI2SM = HSE_VALUE / 1000000; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_CK48; diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h index d157d944a..72efe82eb 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.h @@ -1,4 +1,4 @@ - /* +/* * This file is part of the Micro Python project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c b/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c index d10fcbb6f..86634cf6c 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c @@ -36,9 +36,9 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); - //Never reset pins - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK + // Never reset pins + never_reset_pin_number(2,14); // PC14 OSC32_IN + never_reset_pin_number(2,15); // PC15 OSC32_OUT + never_reset_pin_number(0,13); // PA13 SWDIO + never_reset_pin_number(0,14); // PA14 SWCLK } diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c index 868945ecc..23664999b 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -31,7 +31,7 @@ // I2C -I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; +I2C_TypeDef *mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; const mcu_periph_obj_t mcu_i2c_sda_list[5] = { PERIPH(1, 4, &pin_PB07), @@ -50,7 +50,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[4] = { // SPI -SPI_TypeDef * mcu_spi_banks[4] = {SPI1, SPI2, SPI3, SPI4}; +SPI_TypeDef *mcu_spi_banks[4] = {SPI1, SPI2, SPI3, SPI4}; const mcu_periph_obj_t mcu_spi_sck_list[9] = { PERIPH(1, 5, &pin_PA05), @@ -99,7 +99,7 @@ const mcu_periph_obj_t mcu_spi_nss_list[9] = { PERIPH(4, 5, &pin_PE11), }; -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6}; +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, false, false, false, true}; const mcu_periph_obj_t mcu_uart_tx_list[6] = { @@ -120,12 +120,12 @@ const mcu_periph_obj_t mcu_uart_rx_list[6] = { PERIPH(2, 7, &pin_PD06), }; -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, TIM10, - TIM11, NULL, NULL, NULL}; +// Timers +// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, TIM10, + TIM11, NULL, NULL, NULL}; -//#define TIM(index, alt, channel, tim_pin) +// #define TIM(index, alt, channel, tim_pin) const mcu_tim_pin_obj_t mcu_tim_pin_list[44] = { TIM(2,1,1,&pin_PA00), TIM(5,2,1,&pin_PA00), diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h index c38e9ea98..9bc47b8bf 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h @@ -27,31 +27,31 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H -//I2C -extern I2C_TypeDef * mcu_i2c_banks[3]; +// I2C +extern I2C_TypeDef *mcu_i2c_banks[3]; extern const mcu_periph_obj_t mcu_i2c_sda_list[5]; extern const mcu_periph_obj_t mcu_i2c_scl_list[4]; -//SPI -extern SPI_TypeDef * mcu_spi_banks[4]; +// SPI +extern SPI_TypeDef *mcu_spi_banks[4]; extern const mcu_periph_obj_t mcu_spi_sck_list[9]; extern const mcu_periph_obj_t mcu_spi_mosi_list[9]; extern const mcu_periph_obj_t mcu_spi_miso_list[8]; extern const mcu_periph_obj_t mcu_spi_nss_list[9]; -//UART -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +// UART +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; extern const mcu_periph_obj_t mcu_uart_tx_list[6]; extern const mcu_periph_obj_t mcu_uart_rx_list[6]; -//Timers +// Timers #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 44 -extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; #endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c index ed89f0de6..a155970bb 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -34,9 +34,9 @@ const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); -const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp -const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN -const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); // anti-tamp +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); // OSC32_IN +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); // OSC32_OUT const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10)); const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11)); @@ -94,9 +94,9 @@ const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); -const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); //SWDIO -const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); //SWCLK -const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); //JTDI +const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); // SWDIO +const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); // SWCLK +const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); // JTDI const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC); const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h index c836df69a..ef804ba09 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h @@ -27,13 +27,13 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PINS_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PINS_H -//Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only -//pg 38 +// Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only +// pg 38 extern const mcu_pin_obj_t pin_PE02; extern const mcu_pin_obj_t pin_PE03; extern const mcu_pin_obj_t pin_PE04; extern const mcu_pin_obj_t pin_PE05; -//pg 39 +// pg 39 extern const mcu_pin_obj_t pin_PE06; extern const mcu_pin_obj_t pin_PC13; extern const mcu_pin_obj_t pin_PC14; @@ -42,7 +42,7 @@ extern const mcu_pin_obj_t pin_PC00; extern const mcu_pin_obj_t pin_PC01; extern const mcu_pin_obj_t pin_PC02; extern const mcu_pin_obj_t pin_PC03; -//pg 40 +// pg 40 extern const mcu_pin_obj_t pin_PA00; extern const mcu_pin_obj_t pin_PA01; extern const mcu_pin_obj_t pin_PA02; @@ -51,7 +51,7 @@ extern const mcu_pin_obj_t pin_PA04; extern const mcu_pin_obj_t pin_PA05; extern const mcu_pin_obj_t pin_PA06; extern const mcu_pin_obj_t pin_PA07; -//pg 41 +// pg 41 extern const mcu_pin_obj_t pin_PC04; extern const mcu_pin_obj_t pin_PC05; extern const mcu_pin_obj_t pin_PB00; @@ -66,7 +66,7 @@ extern const mcu_pin_obj_t pin_PE12; extern const mcu_pin_obj_t pin_PE13; extern const mcu_pin_obj_t pin_PE14; extern const mcu_pin_obj_t pin_PE15; -//pg 42 +// pg 42 extern const mcu_pin_obj_t pin_PB10; extern const mcu_pin_obj_t pin_PB12; extern const mcu_pin_obj_t pin_PB13; @@ -77,7 +77,7 @@ extern const mcu_pin_obj_t pin_PD09; extern const mcu_pin_obj_t pin_PD10; extern const mcu_pin_obj_t pin_PD11; extern const mcu_pin_obj_t pin_PD12; -//pg 43 +// pg 43 extern const mcu_pin_obj_t pin_PD13; extern const mcu_pin_obj_t pin_PD14; extern const mcu_pin_obj_t pin_PD15; @@ -87,7 +87,7 @@ extern const mcu_pin_obj_t pin_PC08; extern const mcu_pin_obj_t pin_PC09; extern const mcu_pin_obj_t pin_PA08; extern const mcu_pin_obj_t pin_PA09; -//pg 44 +// pg 44 extern const mcu_pin_obj_t pin_PA10; extern const mcu_pin_obj_t pin_PA11; extern const mcu_pin_obj_t pin_PA12; @@ -97,7 +97,7 @@ extern const mcu_pin_obj_t pin_PA15; extern const mcu_pin_obj_t pin_PC10; extern const mcu_pin_obj_t pin_PC11; extern const mcu_pin_obj_t pin_PC12; -//pg 45 +// pg 45 extern const mcu_pin_obj_t pin_PD00; extern const mcu_pin_obj_t pin_PD01; extern const mcu_pin_obj_t pin_PD02; @@ -110,7 +110,7 @@ extern const mcu_pin_obj_t pin_PB03; extern const mcu_pin_obj_t pin_PB04; extern const mcu_pin_obj_t pin_PB05; extern const mcu_pin_obj_t pin_PB06; -//pg 46 +// pg 46 extern const mcu_pin_obj_t pin_PB07; extern const mcu_pin_obj_t pin_PB08; extern const mcu_pin_obj_t pin_PB09; diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h index 87faec035..4239e3318 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.h @@ -1,4 +1,4 @@ - /* +/* * This file is part of the Micro Python project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c index 03fba6289..385766623 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c @@ -28,7 +28,7 @@ #include "common-hal/microcontroller/Pin.h" void stm32_peripherals_gpio_init(void) { - //Enable all GPIO for now + // Enable all GPIO for now __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); @@ -37,12 +37,12 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - //Never reset pins - never_reset_pin_number(2,13); //PC13 anti tamp - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK + // Never reset pins + never_reset_pin_number(2,13); // PC13 anti tamp + never_reset_pin_number(2,14); // PC14 OSC32_IN + never_reset_pin_number(2,15); // PC15 OSC32_OUT + never_reset_pin_number(0,13); // PA13 SWDIO + never_reset_pin_number(0,14); // PA14 SWCLK // never_reset_pin_number(0,15); //PA15 JTDI // never_reset_pin_number(1,3); //PB3 JTDO // never_reset_pin_number(1,4); //PB4 JTRST diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c index 2f9accbf1..451e4220c 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -29,7 +29,7 @@ #include "peripherals/pins.h" #include "peripherals/periph.h" -I2C_TypeDef * mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3}; +I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3}; const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN] = { PERIPH(1, 4, &pin_PB07), @@ -50,7 +50,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN] = { PERIPH(3, 4, &pin_PH07), }; -SPI_TypeDef * mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3}; +SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3}; const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN] = { PERIPH(1, 5, &pin_PA05), @@ -88,7 +88,7 @@ const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN] = { PERIPH(3, 6, &pin_PA15), }; -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6}; +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN] = { @@ -120,10 +120,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN] = { PERIPH(6, 8, &pin_PG09), }; -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, - TIM11, TIM12, TIM13, TIM14}; +// Timers +// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, + TIM11, TIM12, TIM13, TIM14}; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = { TIM(2, 1, 1, &pin_PA00), @@ -195,8 +195,8 @@ const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = { TIM(8, 3, 3, &pin_PI07), }; -//SDIO -SDIO_TypeDef * mcu_sdio_banks[1] = {SDIO}; +// SDIO +SDIO_TypeDef *mcu_sdio_banks[1] = {SDIO}; const mcu_periph_obj_t mcu_sdio_clock_list[1] = { PERIPH(1, 12, &pin_PC12), @@ -217,8 +217,8 @@ const mcu_periph_obj_t mcu_sdio_data3_list[1] = { PERIPH(1, 12, &pin_PC11), }; -//CAN -CAN_TypeDef * mcu_can_banks[2] = {CAN1, CAN2}; +// CAN +CAN_TypeDef *mcu_can_banks[2] = {CAN1, CAN2}; const mcu_periph_obj_t mcu_can_tx_list[6] = { PERIPH(1, 9, &pin_PA11), diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h index 03198af55..d5433f995 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h @@ -27,42 +27,42 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H -//I2C +// I2C #define I2C_BANK_ARRAY_LEN 3 #define I2C_SDA_ARRAY_LEN 7 #define I2C_SCL_ARRAY_LEN 7 -extern I2C_TypeDef * mcu_i2c_banks[I2C_BANK_ARRAY_LEN]; +extern I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN]; -//SPI +// SPI #define SPI_BANK_ARRAY_LEN 3 #define SPI_SCK_ARRAY_LEN 7 #define SPI_MOSI_ARRAY_LEN 7 #define SPI_MISO_ARRAY_LEN 7 #define SPI_NSS_ARRAY_LEN 6 -extern SPI_TypeDef * mcu_spi_banks[SPI_BANK_ARRAY_LEN]; +extern SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_spi_mosi_list[SPI_MOSI_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_spi_miso_list[SPI_MISO_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN]; -//UART +// UART #define UART_TX_ARRAY_LEN 12 #define UART_RX_ARRAY_LEN 12 -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; extern const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN]; -//Timers +// Timers #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 67 -extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -//SDIO -extern SDIO_TypeDef * mcu_sdio_banks[1]; +// SDIO +extern SDIO_TypeDef *mcu_sdio_banks[1]; extern const mcu_periph_obj_t mcu_sdio_clock_list[1]; extern const mcu_periph_obj_t mcu_sdio_command_list[1]; @@ -72,7 +72,7 @@ extern const mcu_periph_obj_t mcu_sdio_data2_list[1]; extern const mcu_periph_obj_t mcu_sdio_data3_list[1]; // CAN -extern CAN_TypeDef * mcu_can_banks[2]; +extern CAN_TypeDef *mcu_can_banks[2]; extern const mcu_periph_obj_t mcu_can_tx_list[6]; extern const mcu_periph_obj_t mcu_can_rx_list[6]; diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c index 62acb1955..9fef433ea 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h index 5894b4ae8..28d48e5c1 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.h @@ -1,4 +1,4 @@ - /* +/* * This file is part of the Micro Python project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c index 03fba6289..385766623 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c @@ -28,7 +28,7 @@ #include "common-hal/microcontroller/Pin.h" void stm32_peripherals_gpio_init(void) { - //Enable all GPIO for now + // Enable all GPIO for now __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); @@ -37,12 +37,12 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - //Never reset pins - never_reset_pin_number(2,13); //PC13 anti tamp - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK + // Never reset pins + never_reset_pin_number(2,13); // PC13 anti tamp + never_reset_pin_number(2,14); // PC14 OSC32_IN + never_reset_pin_number(2,15); // PC15 OSC32_OUT + never_reset_pin_number(0,13); // PA13 SWDIO + never_reset_pin_number(0,14); // PA14 SWCLK // never_reset_pin_number(0,15); //PA15 JTDI // never_reset_pin_number(1,3); //PB3 JTDO // never_reset_pin_number(1,4); //PB4 JTRST diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c index 2f9accbf1..451e4220c 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -29,7 +29,7 @@ #include "peripherals/pins.h" #include "peripherals/periph.h" -I2C_TypeDef * mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3}; +I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2, I2C3}; const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN] = { PERIPH(1, 4, &pin_PB07), @@ -50,7 +50,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN] = { PERIPH(3, 4, &pin_PH07), }; -SPI_TypeDef * mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3}; +SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1, SPI2, SPI3}; const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN] = { PERIPH(1, 5, &pin_PA05), @@ -88,7 +88,7 @@ const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN] = { PERIPH(3, 6, &pin_PA15), }; -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6}; +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN] = { @@ -120,10 +120,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN] = { PERIPH(6, 8, &pin_PG09), }; -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, - TIM11, TIM12, TIM13, TIM14}; +// Timers +// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, + TIM11, TIM12, TIM13, TIM14}; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = { TIM(2, 1, 1, &pin_PA00), @@ -195,8 +195,8 @@ const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = { TIM(8, 3, 3, &pin_PI07), }; -//SDIO -SDIO_TypeDef * mcu_sdio_banks[1] = {SDIO}; +// SDIO +SDIO_TypeDef *mcu_sdio_banks[1] = {SDIO}; const mcu_periph_obj_t mcu_sdio_clock_list[1] = { PERIPH(1, 12, &pin_PC12), @@ -217,8 +217,8 @@ const mcu_periph_obj_t mcu_sdio_data3_list[1] = { PERIPH(1, 12, &pin_PC11), }; -//CAN -CAN_TypeDef * mcu_can_banks[2] = {CAN1, CAN2}; +// CAN +CAN_TypeDef *mcu_can_banks[2] = {CAN1, CAN2}; const mcu_periph_obj_t mcu_can_tx_list[6] = { PERIPH(1, 9, &pin_PA11), diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h index e6d4526b6..481a8376d 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h @@ -27,42 +27,42 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H -//I2C +// I2C #define I2C_BANK_ARRAY_LEN 3 #define I2C_SDA_ARRAY_LEN 7 #define I2C_SCL_ARRAY_LEN 7 -extern I2C_TypeDef * mcu_i2c_banks[I2C_BANK_ARRAY_LEN]; +extern I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN]; -//SPI +// SPI #define SPI_BANK_ARRAY_LEN 3 #define SPI_SCK_ARRAY_LEN 7 #define SPI_MOSI_ARRAY_LEN 7 #define SPI_MISO_ARRAY_LEN 7 #define SPI_NSS_ARRAY_LEN 6 -extern SPI_TypeDef * mcu_spi_banks[SPI_BANK_ARRAY_LEN]; +extern SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_spi_mosi_list[SPI_MOSI_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_spi_miso_list[SPI_MISO_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN]; -//UART +// UART #define UART_TX_ARRAY_LEN 12 #define UART_RX_ARRAY_LEN 12 -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; extern const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN]; extern const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN]; -//Timers +// Timers #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 67 -extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -//SDIO -extern SDIO_TypeDef * mcu_sdio_banks[1]; +// SDIO +extern SDIO_TypeDef *mcu_sdio_banks[1]; extern const mcu_periph_obj_t mcu_sdio_clock_list[1]; extern const mcu_periph_obj_t mcu_sdio_command_list[1]; @@ -72,7 +72,7 @@ extern const mcu_periph_obj_t mcu_sdio_data2_list[1]; extern const mcu_periph_obj_t mcu_sdio_data3_list[1]; // CAN -extern CAN_TypeDef * mcu_can_banks[2]; +extern CAN_TypeDef *mcu_can_banks[2]; extern const mcu_periph_obj_t mcu_can_tx_list[6]; extern const mcu_periph_obj_t mcu_can_rx_list[6]; diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c index 62acb1955..9fef433ea 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h index a2fb7bd54..0b38d610c 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.h @@ -1,4 +1,4 @@ - /* +/* * This file is part of the Micro Python project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c b/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c index 08c6b55cd..351607a70 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c @@ -29,7 +29,7 @@ #include "common-hal/microcontroller/Pin.h" void stm32_peripherals_gpio_init(void) { - //* GPIO Ports Clock Enable */ + // * GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); @@ -37,15 +37,15 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - //Never reset pins + // Never reset pins // TODO: Move this out of peripherals. These helpers shouldn't reference anything CircuitPython // specific. - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT + never_reset_pin_number(2,14); // PC14 OSC32_IN + never_reset_pin_number(2,15); // PC15 OSC32_OUT #if !(BOARD_OVERWRITE_SWD) - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK + never_reset_pin_number(0,13); // PA13 SWDIO + never_reset_pin_number(0,14); // PA14 SWCLK #endif // Port H is not included in GPIO port array @@ -53,6 +53,6 @@ void stm32_peripherals_gpio_init(void) { // never_reset_pin_number(5,1); //PH1 JTRST } -//LEDs are inverted on F411 DISCO +// LEDs are inverted on F411 DISCO void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { } diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c index 085663749..dd9cb3d84 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -31,7 +31,7 @@ // I2C -I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; +I2C_TypeDef *mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; const mcu_periph_obj_t mcu_i2c_sda_list[7] = { PERIPH(1, 4, &pin_PB07), @@ -52,7 +52,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[4] = { // SPI -SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5}; +SPI_TypeDef *mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5}; const mcu_periph_obj_t mcu_spi_sck_list[15] = { PERIPH(1, 5, &pin_PA05), @@ -119,7 +119,7 @@ const mcu_periph_obj_t mcu_spi_nss_list[12] = { PERIPH(5, 6, &pin_PE11) }; -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6}; +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, false, false, false, true}; const mcu_periph_obj_t mcu_uart_tx_list[7] = { @@ -142,10 +142,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[7] = { PERIPH(2, 7, &pin_PD06), }; -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, TIM10, - TIM11, NULL, NULL, NULL}; +// Timers +// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, NULL, TIM9, TIM10, + TIM11, NULL, NULL, NULL}; const mcu_tim_pin_obj_t mcu_tim_pin_list[44] = { TIM(2,1,1,&pin_PA00), diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h index f78cb57a7..52fc1961a 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h @@ -27,31 +27,31 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H -//I2C -extern I2C_TypeDef * mcu_i2c_banks[3]; +// I2C +extern I2C_TypeDef *mcu_i2c_banks[3]; extern const mcu_periph_obj_t mcu_i2c_sda_list[7]; extern const mcu_periph_obj_t mcu_i2c_scl_list[4]; -//SPI -extern SPI_TypeDef * mcu_spi_banks[5]; +// SPI +extern SPI_TypeDef *mcu_spi_banks[5]; extern const mcu_periph_obj_t mcu_spi_sck_list[15]; extern const mcu_periph_obj_t mcu_spi_mosi_list[14]; extern const mcu_periph_obj_t mcu_spi_miso_list[12]; extern const mcu_periph_obj_t mcu_spi_nss_list[12]; -//UART -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +// UART +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; extern const mcu_periph_obj_t mcu_uart_tx_list[7]; extern const mcu_periph_obj_t mcu_uart_rx_list[7]; -//Timers +// Timers #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 44 -extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; #endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c index ed89f0de6..a155970bb 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -34,9 +34,9 @@ const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); -const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp -const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN -const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); // anti-tamp +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); // OSC32_IN +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); // OSC32_OUT const mcu_pin_obj_t pin_PC00 = PIN(2, 0, ADC_INPUT(ADC_1,10)); const mcu_pin_obj_t pin_PC01 = PIN(2, 1, ADC_INPUT(ADC_1,11)); @@ -94,9 +94,9 @@ const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); -const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); //SWDIO -const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); //SWCLK -const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); //JTDI +const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); // SWDIO +const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); // SWCLK +const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); // JTDI const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC); const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h index b6c18b02e..00e7cf1b4 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h @@ -27,13 +27,13 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PINS_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PINS_H -//Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only -//pg 38 +// Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only +// pg 38 extern const mcu_pin_obj_t pin_PE02; extern const mcu_pin_obj_t pin_PE03; extern const mcu_pin_obj_t pin_PE04; extern const mcu_pin_obj_t pin_PE05; -//pg 39 +// pg 39 extern const mcu_pin_obj_t pin_PE06; extern const mcu_pin_obj_t pin_PC13; extern const mcu_pin_obj_t pin_PC14; @@ -42,7 +42,7 @@ extern const mcu_pin_obj_t pin_PC00; extern const mcu_pin_obj_t pin_PC01; extern const mcu_pin_obj_t pin_PC02; extern const mcu_pin_obj_t pin_PC03; -//pg 40 +// pg 40 extern const mcu_pin_obj_t pin_PA00; extern const mcu_pin_obj_t pin_PA01; extern const mcu_pin_obj_t pin_PA02; @@ -51,7 +51,7 @@ extern const mcu_pin_obj_t pin_PA04; extern const mcu_pin_obj_t pin_PA05; extern const mcu_pin_obj_t pin_PA06; extern const mcu_pin_obj_t pin_PA07; -//pg 41 +// pg 41 extern const mcu_pin_obj_t pin_PC04; extern const mcu_pin_obj_t pin_PC05; extern const mcu_pin_obj_t pin_PB00; @@ -66,7 +66,7 @@ extern const mcu_pin_obj_t pin_PE12; extern const mcu_pin_obj_t pin_PE13; extern const mcu_pin_obj_t pin_PE14; extern const mcu_pin_obj_t pin_PE15; -//pg 42 +// pg 42 extern const mcu_pin_obj_t pin_PB10; extern const mcu_pin_obj_t pin_PB12; extern const mcu_pin_obj_t pin_PB13; @@ -77,7 +77,7 @@ extern const mcu_pin_obj_t pin_PD09; extern const mcu_pin_obj_t pin_PD10; extern const mcu_pin_obj_t pin_PD11; extern const mcu_pin_obj_t pin_PD12; -//pg 43 +// pg 43 extern const mcu_pin_obj_t pin_PD13; extern const mcu_pin_obj_t pin_PD14; extern const mcu_pin_obj_t pin_PD15; @@ -87,7 +87,7 @@ extern const mcu_pin_obj_t pin_PC08; extern const mcu_pin_obj_t pin_PC09; extern const mcu_pin_obj_t pin_PA08; extern const mcu_pin_obj_t pin_PA09; -//pg 44 +// pg 44 extern const mcu_pin_obj_t pin_PA10; extern const mcu_pin_obj_t pin_PA11; extern const mcu_pin_obj_t pin_PA12; @@ -97,7 +97,7 @@ extern const mcu_pin_obj_t pin_PA15; extern const mcu_pin_obj_t pin_PC10; extern const mcu_pin_obj_t pin_PC11; extern const mcu_pin_obj_t pin_PC12; -//pg 45 +// pg 45 extern const mcu_pin_obj_t pin_PD00; extern const mcu_pin_obj_t pin_PD01; extern const mcu_pin_obj_t pin_PD02; @@ -110,7 +110,7 @@ extern const mcu_pin_obj_t pin_PB03; extern const mcu_pin_obj_t pin_PB04; extern const mcu_pin_obj_t pin_PB05; extern const mcu_pin_obj_t pin_PB06; -//pg 46 +// pg 46 extern const mcu_pin_obj_t pin_PB07; extern const mcu_pin_obj_t pin_PB08; extern const mcu_pin_obj_t pin_PB09; diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h index e1355c8f3..acd353793 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.h @@ -1,4 +1,4 @@ - /* +/* * This file is part of the Micro Python project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index 5ca4667a4..6fe7bbb9c 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -38,15 +38,15 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - //Never reset pins - never_reset_pin_number(2,13); //PC13 anti tamp - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK - //never_reset_pin_number(0,15); //PA15 JTDI - //never_reset_pin_number(1,3); //PB3 JTDO - //never_reset_pin_number(1,4); //PB4 JTRST + // Never reset pins + never_reset_pin_number(2,13); // PC13 anti tamp + never_reset_pin_number(2,14); // PC14 OSC32_IN + never_reset_pin_number(2,15); // PC15 OSC32_OUT + never_reset_pin_number(0,13); // PA13 SWDIO + never_reset_pin_number(0,14); // PA14 SWCLK + // never_reset_pin_number(0,15); //PA15 JTDI + // never_reset_pin_number(1,3); //PB3 JTDO + // never_reset_pin_number(1,4); //PB4 JTRST // Port H is not included in GPIO port array // never_reset_pin_number(5,0); //PH0 JTDO diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c index e92c88ce5..8cd61fd49 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -31,12 +31,12 @@ // I2C -I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; +I2C_TypeDef *mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; const mcu_periph_obj_t mcu_i2c_sda_list[8] = { PERIPH(1, 4, &pin_PB07), PERIPH(1, 4, &pin_PB09), - PERIPH(2, 4, &pin_PB11), //not on LQFP100 + PERIPH(2, 4, &pin_PB11), // not on LQFP100 PERIPH(2, 9, &pin_PB09), PERIPH(2, 9, &pin_PB03), PERIPH(3, 4, &pin_PC09), @@ -53,7 +53,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[4] = { // SPI -SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5}; +SPI_TypeDef *mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5}; const mcu_periph_obj_t mcu_spi_sck_list[15] = { PERIPH(1, 5, &pin_PA05), @@ -120,9 +120,9 @@ const mcu_periph_obj_t mcu_spi_nss_list[12] = { PERIPH(5, 6, &pin_PE11) }; -//UART +// UART -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, NULL, NULL, USART6}; +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, NULL, NULL, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; const mcu_periph_obj_t mcu_uart_tx_list[11] = { @@ -154,10 +154,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[12] = { PERIPH(6, 8, &pin_PG09), }; -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, - TIM11, TIM12, TIM13, TIM14}; +// Timers +// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, + TIM11, TIM12, TIM13, TIM14}; const mcu_tim_pin_obj_t mcu_tim_pin_list[60] = { TIM(2,1,1,&pin_PA00), diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h index 40afd27f4..4e861da5d 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h @@ -27,32 +27,32 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H -//I2C -extern I2C_TypeDef * mcu_i2c_banks[3]; +// I2C +extern I2C_TypeDef *mcu_i2c_banks[3]; extern const mcu_periph_obj_t mcu_i2c_sda_list[8]; extern const mcu_periph_obj_t mcu_i2c_scl_list[4]; -//SPI -extern SPI_TypeDef * mcu_spi_banks[5]; +// SPI +extern SPI_TypeDef *mcu_spi_banks[5]; extern const mcu_periph_obj_t mcu_spi_sck_list[15]; extern const mcu_periph_obj_t mcu_spi_mosi_list[14]; extern const mcu_periph_obj_t mcu_spi_miso_list[12]; extern const mcu_periph_obj_t mcu_spi_nss_list[12]; -//UART -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +// UART +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; extern const mcu_periph_obj_t mcu_uart_tx_list[11]; extern const mcu_periph_obj_t mcu_uart_rx_list[12]; -//Timers +// Timers #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 60 -extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; #endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c index c1b624f4d..4fa70b5bd 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -34,9 +34,9 @@ const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); -const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); //anti-tamp -const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); //OSC32_IN -const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); //OSC32_OUT +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); // anti-tamp +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); // OSC32_IN +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); // OSC32_OUT const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); // 144 only const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); // 144 only diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h index 8914530d2..18e25f3f5 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h @@ -27,7 +27,7 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PINS_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PINS_H -//pg 50 +// pg 50 extern const mcu_pin_obj_t pin_PE02; extern const mcu_pin_obj_t pin_PE03; extern const mcu_pin_obj_t pin_PE04; @@ -35,7 +35,7 @@ extern const mcu_pin_obj_t pin_PE05; extern const mcu_pin_obj_t pin_PE06; extern const mcu_pin_obj_t pin_PC13; extern const mcu_pin_obj_t pin_PC14; -//pg 51 +// pg 51 extern const mcu_pin_obj_t pin_PC15; extern const mcu_pin_obj_t pin_PF00; // 144 only extern const mcu_pin_obj_t pin_PF01; // 144 only @@ -48,7 +48,7 @@ extern const mcu_pin_obj_t pin_PF07; // 144 only extern const mcu_pin_obj_t pin_PF08; // 144 only extern const mcu_pin_obj_t pin_PF09; // 144 only extern const mcu_pin_obj_t pin_PF10; // 144 only -//pg 52 +// pg 52 extern const mcu_pin_obj_t pin_PC00; extern const mcu_pin_obj_t pin_PC01; extern const mcu_pin_obj_t pin_PC02; @@ -56,14 +56,14 @@ extern const mcu_pin_obj_t pin_PC03; extern const mcu_pin_obj_t pin_PA00; extern const mcu_pin_obj_t pin_PA01; extern const mcu_pin_obj_t pin_PA02; -//pg 53 +// pg 53 extern const mcu_pin_obj_t pin_PA03; extern const mcu_pin_obj_t pin_PA04; extern const mcu_pin_obj_t pin_PA05; extern const mcu_pin_obj_t pin_PA06; extern const mcu_pin_obj_t pin_PA07; extern const mcu_pin_obj_t pin_PC04; -//pg 54 +// pg 54 extern const mcu_pin_obj_t pin_PC05; extern const mcu_pin_obj_t pin_PB00; extern const mcu_pin_obj_t pin_PB01; @@ -75,7 +75,7 @@ extern const mcu_pin_obj_t pin_PF14; // 144 only extern const mcu_pin_obj_t pin_PF15; // 144 only extern const mcu_pin_obj_t pin_PG00; // 144 only extern const mcu_pin_obj_t pin_PG01; // 144 only -//pg 55 +// pg 55 extern const mcu_pin_obj_t pin_PE07; extern const mcu_pin_obj_t pin_PE08; extern const mcu_pin_obj_t pin_PE09; @@ -84,13 +84,13 @@ extern const mcu_pin_obj_t pin_PE11; extern const mcu_pin_obj_t pin_PE12; extern const mcu_pin_obj_t pin_PE13; extern const mcu_pin_obj_t pin_PE14; -//pg 56 +// pg 56 extern const mcu_pin_obj_t pin_PE15; extern const mcu_pin_obj_t pin_PB10; extern const mcu_pin_obj_t pin_PB11; // 144 only extern const mcu_pin_obj_t pin_PB12; extern const mcu_pin_obj_t pin_PB13; -//pg 57 +// pg 57 extern const mcu_pin_obj_t pin_PB14; extern const mcu_pin_obj_t pin_PB15; extern const mcu_pin_obj_t pin_PD08; @@ -98,7 +98,7 @@ extern const mcu_pin_obj_t pin_PD09; extern const mcu_pin_obj_t pin_PD10; extern const mcu_pin_obj_t pin_PD11; extern const mcu_pin_obj_t pin_PD12; -//pg 58 +// pg 58 extern const mcu_pin_obj_t pin_PD13; extern const mcu_pin_obj_t pin_PD14; extern const mcu_pin_obj_t pin_PD15; @@ -109,7 +109,7 @@ extern const mcu_pin_obj_t pin_PG05; // 144 only extern const mcu_pin_obj_t pin_PG06; // 144 only extern const mcu_pin_obj_t pin_PG07; // 144 only extern const mcu_pin_obj_t pin_PG08; // 144 only -//pg 59 +// pg 59 extern const mcu_pin_obj_t pin_PC06; extern const mcu_pin_obj_t pin_PC07; extern const mcu_pin_obj_t pin_PC08; @@ -117,7 +117,7 @@ extern const mcu_pin_obj_t pin_PC09; extern const mcu_pin_obj_t pin_PA08; extern const mcu_pin_obj_t pin_PA09; extern const mcu_pin_obj_t pin_PA10; -//pg 60 +// pg 60 extern const mcu_pin_obj_t pin_PA11; extern const mcu_pin_obj_t pin_PA12; extern const mcu_pin_obj_t pin_PA13; @@ -125,7 +125,7 @@ extern const mcu_pin_obj_t pin_PA14; extern const mcu_pin_obj_t pin_PA15; extern const mcu_pin_obj_t pin_PC10; extern const mcu_pin_obj_t pin_PC11; -//pg 61 +// pg 61 extern const mcu_pin_obj_t pin_PC12; extern const mcu_pin_obj_t pin_PD00; extern const mcu_pin_obj_t pin_PD01; @@ -135,7 +135,7 @@ extern const mcu_pin_obj_t pin_PD04; extern const mcu_pin_obj_t pin_PD05; extern const mcu_pin_obj_t pin_PD06; extern const mcu_pin_obj_t pin_PD07; -//pg 62 +// pg 62 extern const mcu_pin_obj_t pin_PG09; // 144 only extern const mcu_pin_obj_t pin_PG10; // 144 only extern const mcu_pin_obj_t pin_PG11; // 144 only @@ -145,7 +145,7 @@ extern const mcu_pin_obj_t pin_PG14; // 144 only extern const mcu_pin_obj_t pin_PG15; // 144 only extern const mcu_pin_obj_t pin_PB03; extern const mcu_pin_obj_t pin_PB04; -//pg 63 +// pg 63 extern const mcu_pin_obj_t pin_PB05; extern const mcu_pin_obj_t pin_PB06; extern const mcu_pin_obj_t pin_PB07; diff --git a/ports/stm/peripherals/stm32f7/clocks.c b/ports/stm/peripherals/stm32f7/clocks.c index f13088782..3767d223c 100644 --- a/ports/stm/peripherals/stm32f7/clocks.c +++ b/ports/stm/peripherals/stm32f7/clocks.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the Micro Python project, http://micropython.org/ * * The MIT License (MIT) @@ -61,15 +61,17 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000; RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { // Clock issues are too problematic to even attempt recovery. // If you end up here, check whether your LSE settings match your board. - while(1); + while (1) { + ; + } } /* Activate the OverDrive to reach the 216 MHz Frequency */ diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c b/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c index ca64428eb..b7cc0aad6 100644 --- a/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c +++ b/ports/stm/peripherals/stm32f7/stm32f746xx/gpio.c @@ -29,7 +29,7 @@ #include "common-hal/microcontroller/Pin.h" void stm32_peripherals_gpio_init(void) { - //Enable all GPIO for now + // Enable all GPIO for now __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); @@ -42,11 +42,11 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOJ_CLK_ENABLE(); __HAL_RCC_GPIOK_CLK_ENABLE(); - //Never reset pins - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK - never_reset_pin_number(7,0); //PH0 OSC_IN - never_reset_pin_number(7,1); //PH1 OSC_OUT + // Never reset pins + never_reset_pin_number(2,14); // PC14 OSC32_IN + never_reset_pin_number(2,15); // PC15 OSC32_OUT + never_reset_pin_number(0,13); // PA13 SWDIO + never_reset_pin_number(0,14); // PA14 SWCLK + never_reset_pin_number(7,0); // PH0 OSC_IN + never_reset_pin_number(7,1); // PH1 OSC_OUT } diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/periph.c b/ports/stm/peripherals/stm32f7/stm32f746xx/periph.c index 0c3391239..89cd7e27e 100644 --- a/ports/stm/peripherals/stm32f7/stm32f746xx/periph.c +++ b/ports/stm/peripherals/stm32f7/stm32f746xx/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -32,7 +32,7 @@ // I2C -I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4}; +I2C_TypeDef *mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4}; const mcu_periph_obj_t mcu_i2c_sda_list[10] = { PERIPH(1, 4, &pin_PB07), @@ -59,9 +59,9 @@ const mcu_periph_obj_t mcu_i2c_scl_list[10] = { PERIPH(4, 4, &pin_PH11), }; -//SPI +// SPI -SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; +SPI_TypeDef *mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; const mcu_periph_obj_t mcu_spi_sck_list[14] = { PERIPH(1, 5, &pin_PA05), @@ -111,9 +111,9 @@ const mcu_periph_obj_t mcu_spi_miso_list[12] = { PERIPH(2, 5, &pin_PI02), }; -//UART +// UART -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8}; +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true}; const mcu_periph_obj_t mcu_uart_tx_list[15] = { @@ -151,10 +151,10 @@ const mcu_periph_obj_t mcu_uart_rx_list[15] = { PERIPH(6, 8, &pin_PG09), }; -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, - TIM11, TIM12, TIM13, TIM14}; +// Timers +// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, TIM9, TIM10, + TIM11, TIM12, TIM13, TIM14}; const mcu_tim_pin_obj_t mcu_tim_pin_list[55] = { TIM(2, 1, 1, &pin_PA00), diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/periph.h b/ports/stm/peripherals/stm32f7/stm32f746xx/periph.h index f20896e22..425221f64 100644 --- a/ports/stm/peripherals/stm32f7/stm32f746xx/periph.h +++ b/ports/stm/peripherals/stm32f7/stm32f746xx/periph.h @@ -28,30 +28,30 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F746XX_PERIPH_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F746XX_PERIPH_H -//I2C -extern I2C_TypeDef * mcu_i2c_banks[4]; +// I2C +extern I2C_TypeDef *mcu_i2c_banks[4]; extern const mcu_periph_obj_t mcu_i2c_sda_list[10]; extern const mcu_periph_obj_t mcu_i2c_scl_list[10]; -//SPI -extern SPI_TypeDef * mcu_spi_banks[6]; +// SPI +extern SPI_TypeDef *mcu_spi_banks[6]; extern const mcu_periph_obj_t mcu_spi_sck_list[14]; extern const mcu_periph_obj_t mcu_spi_mosi_list[15]; extern const mcu_periph_obj_t mcu_spi_miso_list[12]; -//UART -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +// UART +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; extern const mcu_periph_obj_t mcu_uart_tx_list[15]; extern const mcu_periph_obj_t mcu_uart_rx_list[15]; -//Timers +// Timers #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 55 -extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; diff --git a/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c b/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c index ae940c1a0..0a2682528 100644 --- a/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c +++ b/ports/stm/peripherals/stm32f7/stm32f746xx/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c b/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c index 1189948c7..f89af2714 100644 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c @@ -28,7 +28,7 @@ #include "common-hal/microcontroller/Pin.h" void stm32_peripherals_gpio_init(void) { - //Enable all GPIO for now + // Enable all GPIO for now __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); @@ -38,9 +38,9 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - //Never reset pins - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK + // Never reset pins + never_reset_pin_number(2,14); // PC14 OSC32_IN + never_reset_pin_number(2,15); // PC15 OSC32_OUT + never_reset_pin_number(0,13); // PA13 SWDIO + never_reset_pin_number(0,14); // PA14 SWCLK } diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c index 07d226db3..b1ac71248 100644 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -31,7 +31,7 @@ // I2C -I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4}; +I2C_TypeDef *mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4}; const mcu_periph_obj_t mcu_i2c_sda_list[12] = { PERIPH(1, 4, &pin_PB07), @@ -62,9 +62,9 @@ const mcu_periph_obj_t mcu_i2c_scl_list[12] = { PERIPH(4, 4, &pin_PH11), }; -//SPI +// SPI -SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; +SPI_TypeDef *mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; const mcu_periph_obj_t mcu_spi_sck_list[18] = { PERIPH(1, 5, &pin_PA05), @@ -124,9 +124,9 @@ const mcu_periph_obj_t mcu_spi_miso_list[15] = { PERIPH(2, 5, &pin_PI02), }; -//UART +// UART -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8}; +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true}; const mcu_periph_obj_t mcu_uart_tx_list[24] = { @@ -183,11 +183,11 @@ const mcu_periph_obj_t mcu_uart_rx_list[25] = { PERIPH(4, 8, &pin_PI09), }; -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -//TODO: H7 has more timers than this, but are they tied to pins? -TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL, - NULL, TIM12, TIM13, TIM14}; +// Timers +// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +// TODO: H7 has more timers than this, but are they tied to pins? +TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL, + NULL, TIM12, TIM13, TIM14}; const mcu_tim_pin_obj_t mcu_tim_pin_list[55] = { TIM(2, 1, 1, &pin_PA00), diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h index 70f03f258..ea4797634 100644 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h @@ -27,30 +27,30 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H -//I2C -extern I2C_TypeDef * mcu_i2c_banks[4]; +// I2C +extern I2C_TypeDef *mcu_i2c_banks[4]; extern const mcu_periph_obj_t mcu_i2c_sda_list[12]; extern const mcu_periph_obj_t mcu_i2c_scl_list[12]; -//SPI -extern SPI_TypeDef * mcu_spi_banks[6]; +// SPI +extern SPI_TypeDef *mcu_spi_banks[6]; extern const mcu_periph_obj_t mcu_spi_sck_list[18]; extern const mcu_periph_obj_t mcu_spi_mosi_list[18]; extern const mcu_periph_obj_t mcu_spi_miso_list[15]; -//UART -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +// UART +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; extern const mcu_periph_obj_t mcu_uart_tx_list[24]; extern const mcu_periph_obj_t mcu_uart_rx_list[25]; -//Timers +// Timers #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 55 -extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c index 5c9daea98..67814c6b7 100644 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/stm32h7/clocks.c b/ports/stm/peripherals/stm32h7/clocks.c index a088f78bf..5fde5af6c 100644 --- a/ports/stm/peripherals/stm32h7/clocks.c +++ b/ports/stm/peripherals/stm32h7/clocks.c @@ -41,7 +41,8 @@ void stm32_peripherals_clocks_init(void) { // Set voltage scaling in accordance with system clock speed HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); __HAL_PWR_VOLTAGESCALING_CONFIG(CPY_CLK_VSCALE); - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) { + } // Configure LSE Drive HAL_PWR_EnableBkUpAccess(); @@ -63,7 +64,7 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/2000000; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 2000000; RCC_OscInitStruct.PLL.PLLN = CPY_CLK_PLLN; RCC_OscInitStruct.PLL.PLLP = CPY_CLK_PLLP; RCC_OscInitStruct.PLL.PLLQ = CPY_CLK_PLLQ; @@ -71,16 +72,18 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { // Clock issues are too problematic to even attempt recovery. // If you end up here, check whether your LSE settings match your board. - while(1); + while (1) { + ; + } } // Configure bus clock sources and divisors - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = CPY_CLK_AHBDIV; @@ -92,8 +95,8 @@ void stm32_peripherals_clocks_init(void) { // Set up non-bus peripherals // TODO: I2S settings go here - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART3 - |RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 + | RCC_PERIPHCLK_USB; #if (BOARD_HAS_LOW_SPEED_CRYSTAL) PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; #else diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c b/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c index 1189948c7..f89af2714 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c @@ -28,7 +28,7 @@ #include "common-hal/microcontroller/Pin.h" void stm32_peripherals_gpio_init(void) { - //Enable all GPIO for now + // Enable all GPIO for now __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); @@ -38,9 +38,9 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - //Never reset pins - never_reset_pin_number(2,14); //PC14 OSC32_IN - never_reset_pin_number(2,15); //PC15 OSC32_OUT - never_reset_pin_number(0,13); //PA13 SWDIO - never_reset_pin_number(0,14); //PA14 SWCLK + // Never reset pins + never_reset_pin_number(2,14); // PC14 OSC32_IN + never_reset_pin_number(2,15); // PC15 OSC32_OUT + never_reset_pin_number(0,13); // PA13 SWDIO + never_reset_pin_number(0,14); // PA14 SWCLK } diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c index 892164600..bf8248f76 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) @@ -31,7 +31,7 @@ // I2C -I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4}; +I2C_TypeDef *mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4}; const mcu_periph_obj_t mcu_i2c_sda_list[12] = { PERIPH(1, 4, &pin_PB07), @@ -65,7 +65,7 @@ const mcu_periph_obj_t mcu_i2c_scl_list[12] = { // SPI -SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; +SPI_TypeDef *mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; const mcu_periph_obj_t mcu_spi_sck_list[19] = { PERIPH(1, 5, &pin_PA05), @@ -130,9 +130,9 @@ const mcu_periph_obj_t mcu_spi_miso_list[16] = { PERIPH(5, 5, &pin_PJ11), }; -//UART +// UART -USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8}; +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true}; const mcu_periph_obj_t mcu_uart_tx_list[25] = { @@ -192,11 +192,11 @@ const mcu_periph_obj_t mcu_uart_rx_list[26] = { PERIPH(8, 8, &pin_PJ09), }; -//Timers -//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins -//TODO: H7 has more timers than this, but are they tied to pins? -TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL, - NULL, TIM12, TIM13, TIM14}; +// Timers +// TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +// TODO: H7 has more timers than this, but are they tied to pins? +TIM_TypeDef *mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL, + NULL, TIM12, TIM13, TIM14}; const mcu_tim_pin_obj_t mcu_tim_pin_list[58] = { TIM(2, 1, 1, &pin_PA00), diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h index e3902e7c7..3716a0f82 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h @@ -27,29 +27,29 @@ #ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H #define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H -//I2C -extern I2C_TypeDef * mcu_i2c_banks[4]; +// I2C +extern I2C_TypeDef *mcu_i2c_banks[4]; extern const mcu_periph_obj_t mcu_i2c_sda_list[12]; extern const mcu_periph_obj_t mcu_i2c_scl_list[12]; -//SPI -extern SPI_TypeDef * mcu_spi_banks[6]; +// SPI +extern SPI_TypeDef *mcu_spi_banks[6]; extern const mcu_periph_obj_t mcu_spi_sck_list[19]; extern const mcu_periph_obj_t mcu_spi_mosi_list[19]; extern const mcu_periph_obj_t mcu_spi_miso_list[16]; -//UART -extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +// UART +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; extern const mcu_periph_obj_t mcu_uart_tx_list[25]; extern const mcu_periph_obj_t mcu_uart_rx_list[26]; -//Timers +// Timers #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 58 -extern TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; #endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c index 7484781c2..baad62274 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c @@ -1,4 +1,4 @@ - /* +/* * This file is part of the MicroPython project, http://micropython.org/ * * The MIT License (MIT) diff --git a/ports/stm/peripherals/timers.c b/ports/stm/peripherals/timers.c index 7bc5ea495..6121deab1 100644 --- a/ports/stm/peripherals/timers.c +++ b/ports/stm/peripherals/timers.c @@ -41,8 +41,8 @@ static bool stm_timer_reserved[MP_ARRAY_SIZE(mcu_tim_banks)]; static bool stm_timer_never_reset[MP_ARRAY_SIZE(mcu_tim_banks)]; -static void (*stm_timer_callback[MP_ARRAY_SIZE(mcu_tim_banks)])(void); -static size_t irq_map[] = { +static void (*stm_timer_callback[MP_ARRAY_SIZE (mcu_tim_banks)])(void); + static size_t irq_map[] = { #ifdef TIM1 TIM1_CC_IRQn, #else @@ -69,11 +69,11 @@ static size_t irq_map[] = { NULL_IRQ, #endif #ifdef TIM6 - #if !defined(DAC_BASE) && !defined(DAC1_BASE) - TIM6_IRQn, - #else - TIM6_DAC_IRQn, - #endif + #if !defined(DAC_BASE) && !defined(DAC1_BASE) + TIM6_IRQn, + #else + TIM6_DAC_IRQn, + #endif #else NULL_IRQ, #endif @@ -139,7 +139,7 @@ static size_t irq_map[] = { // If the APB prescaler is 1, then the timer clock is equal to its respective // APB clock. Otherwise (APB prescaler > 1) the timer clock is twice its // respective APB clock. See DM00031020 Rev 4, page 115. -uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef * timer) { + uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef *timer) { size_t tim_id = stm_peripherals_timer_get_index(timer); uint32_t source, clk_div; if (tim_id == 1 || (8 <= tim_id && tim_id <= 11)) { @@ -158,12 +158,12 @@ uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef * timer) { return source; } -size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef * instance) { + size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef *instance) { size_t tim_id = stm_peripherals_timer_get_index(instance); return irq_map[tim_id]; } -void timers_reset(void) { + void timers_reset(void) { uint16_t never_reset_mask = 0x00; for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) { if (!stm_timer_never_reset[i]) { @@ -175,18 +175,18 @@ void timers_reset(void) { tim_clock_disable(ALL_CLOCKS & ~(never_reset_mask)); } -TIM_TypeDef * stm_peripherals_find_timer(void) { + TIM_TypeDef *stm_peripherals_find_timer(void) { // Check for timers on pins outside the package size for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) { bool timer_in_package = false; // Find each timer instance on the given bank for (size_t j = 0; j < MP_ARRAY_SIZE(mcu_tim_pin_list); j++) { // If a pin is claimed, we skip it - if ( (mcu_tim_pin_list[j].tim_index == i + 1) - && (common_hal_mcu_pin_is_free(mcu_tim_pin_list[j].pin) == true) ) { + if ((mcu_tim_pin_list[j].tim_index == i + 1) + && (common_hal_mcu_pin_is_free(mcu_tim_pin_list[j].pin) == true)) { // Search whether any pins in the package array match it for (size_t k = 0; k < mcu_pin_globals.map.alloc; k++) { - if ( (mcu_tim_pin_list[j].pin == (mcu_pin_obj_t*)(mcu_pin_globals.map.table[k].value)) ) { + if ((mcu_tim_pin_list[j].pin == (mcu_pin_obj_t *)(mcu_pin_globals.map.table[k].value))) { timer_in_package = true; } } @@ -198,7 +198,7 @@ TIM_TypeDef * stm_peripherals_find_timer(void) { return mcu_tim_banks[i]; } } - //TODO: secondary search for timers outside the pins in the board profile + // TODO: secondary search for timers outside the pins in the board profile // Work backwards - higher index timers have fewer pin allocations for (size_t i = (MP_ARRAY_SIZE(mcu_tim_banks) - 1); i >= 0; i--) { @@ -210,7 +210,7 @@ TIM_TypeDef * stm_peripherals_find_timer(void) { return NULL; } -void stm_peripherals_timer_preinit(TIM_TypeDef * instance, uint8_t prio, void (*callback)(void)) { + void stm_peripherals_timer_preinit(TIM_TypeDef *instance, uint8_t prio, void (*callback)(void)) { size_t tim_idx = stm_peripherals_timer_get_index(instance); stm_timer_callback[tim_idx] = callback; tim_clock_enable(1 << tim_idx); @@ -218,16 +218,16 @@ void stm_peripherals_timer_preinit(TIM_TypeDef * instance, uint8_t prio, void (* HAL_NVIC_EnableIRQ(irq_map[tim_idx]); } -void stm_peripherals_timer_reserve(TIM_TypeDef * instance) { + void stm_peripherals_timer_reserve(TIM_TypeDef *instance) { size_t tim_idx = stm_peripherals_timer_get_index(instance); stm_timer_reserved[tim_idx] = true; } -void stm_peripherals_timer_set_callback(void(*callback)(void), TIM_TypeDef * timer) { + void stm_peripherals_timer_set_callback(void (*callback)(void), TIM_TypeDef *timer) { stm_timer_callback[stm_peripherals_timer_get_index(timer)] = callback; } -void stm_peripherals_timer_free(TIM_TypeDef * instance) { + void stm_peripherals_timer_free(TIM_TypeDef *instance) { size_t tim_idx = stm_peripherals_timer_get_index(instance); HAL_NVIC_DisableIRQ(irq_map[tim_idx]); stm_timer_callback[tim_idx] = NULL; @@ -236,24 +236,24 @@ void stm_peripherals_timer_free(TIM_TypeDef * instance) { stm_timer_never_reset[tim_idx] = false; } -void stm_peripherals_timer_never_reset(TIM_TypeDef * instance) { + void stm_peripherals_timer_never_reset(TIM_TypeDef *instance) { size_t tim_idx = stm_peripherals_timer_get_index(instance); stm_timer_never_reset[tim_idx] = true; } -void stm_peripherals_timer_reset_ok(TIM_TypeDef * instance) { + void stm_peripherals_timer_reset_ok(TIM_TypeDef *instance) { size_t tim_idx = stm_peripherals_timer_get_index(instance); stm_timer_never_reset[tim_idx] = false; } -bool stm_peripherals_timer_is_never_reset(TIM_TypeDef * instance){ + bool stm_peripherals_timer_is_never_reset(TIM_TypeDef *instance) { size_t tim_idx = stm_peripherals_timer_get_index(instance); return stm_timer_never_reset[tim_idx]; } -bool stm_peripherals_timer_is_reserved(TIM_TypeDef * instance) { + bool stm_peripherals_timer_is_reserved(TIM_TypeDef *instance) { size_t tim_idx = stm_peripherals_timer_get_index(instance); return stm_timer_reserved[tim_idx]; } -size_t stm_peripherals_timer_get_index(TIM_TypeDef * instance) { + size_t stm_peripherals_timer_get_index(TIM_TypeDef *instance) { for (size_t i = 0; i < MP_ARRAY_SIZE(mcu_tim_banks); i++) { if (instance == mcu_tim_banks[i]) { return i; @@ -262,7 +262,7 @@ size_t stm_peripherals_timer_get_index(TIM_TypeDef * instance) { return ~(size_t)0; } -void tim_clock_enable(uint16_t mask) { + void tim_clock_enable(uint16_t mask) { #ifdef TIM1 if (mask & (1 << 0)) { __HAL_RCC_TIM1_CLK_ENABLE(); @@ -288,7 +288,7 @@ void tim_clock_enable(uint16_t mask) { __HAL_RCC_TIM5_CLK_ENABLE(); } #endif - //6 and 7 are reserved ADC timers + // 6 and 7 are reserved ADC timers #ifdef TIM8 if (mask & (1 << 7)) { __HAL_RCC_TIM8_CLK_ENABLE(); @@ -326,7 +326,7 @@ void tim_clock_enable(uint16_t mask) { #endif } -void tim_clock_disable(uint16_t mask) { + void tim_clock_disable(uint16_t mask) { #ifdef TIM1 if (mask & (1 << 0)) { __HAL_RCC_TIM1_CLK_DISABLE(); @@ -352,7 +352,7 @@ void tim_clock_disable(uint16_t mask) { __HAL_RCC_TIM5_CLK_DISABLE(); } #endif - //6 and 7 are reserved ADC timers + // 6 and 7 are reserved ADC timers #ifdef TIM8 if (mask & (1 << 7)) { __HAL_RCC_TIM8_CLK_DISABLE(); @@ -390,65 +390,65 @@ void tim_clock_disable(uint16_t mask) { #endif } -STATIC void callback_router(size_t index) { + STATIC void callback_router(size_t index) { if (stm_timer_callback[index - 1]) { (*stm_timer_callback[index - 1])(); } } -void TIM1_CC_IRQHandler(void) { // Advanced timer + void TIM1_CC_IRQHandler(void) { // Advanced timer callback_router(1); } -void TIM2_IRQHandler(void) { + void TIM2_IRQHandler(void) { callback_router(2); } -void TIM3_IRQHandler(void) { + void TIM3_IRQHandler(void) { callback_router(3); } -void TIM4_IRQHandler(void) { + void TIM4_IRQHandler(void) { callback_router(4); } -void TIM5_IRQHandler(void) { + void TIM5_IRQHandler(void) { callback_router(5); } -void TIM6_DAC_IRQHandler(void) { // Basic timer (DAC) + void TIM6_DAC_IRQHandler(void) { // Basic timer (DAC) callback_router(6); } -void TIM7_IRQHandler(void) { // Basic timer + void TIM7_IRQHandler(void) { // Basic timer callback_router(7); } -void TIM8_CC_IRQHandler(void) { // Advanced timer + void TIM8_CC_IRQHandler(void) { // Advanced timer callback_router(8); } // Advanced timer interrupts are currently unused. -void TIM1_BRK_TIM9_IRQHandler(void) { + void TIM1_BRK_TIM9_IRQHandler(void) { callback_router(9); } -void TIM1_UP_TIM10_IRQHandler(void) { + void TIM1_UP_TIM10_IRQHandler(void) { callback_router(10); } -void TIM1_TRG_COM_TIM11_IRQHandler(void) { + void TIM1_TRG_COM_TIM11_IRQHandler(void) { callback_router(11); } -void TIM8_BRK_TIM12_IRQHandler(void) { + void TIM8_BRK_TIM12_IRQHandler(void) { callback_router(12); } -void TIM8_UP_TIM13_IRQHandler(void) { + void TIM8_UP_TIM13_IRQHandler(void) { callback_router(13); } -void TIM8_TRG_COM_TIM14_IRQHandler(void) { + void TIM8_TRG_COM_TIM14_IRQHandler(void) { callback_router(14); } #if (CPY_STM32H7) -void TIM15_IRQHandler(void) { + void TIM15_IRQHandler(void) { callback_router(15); } -void TIM16_IRQHandler(void) { + void TIM16_IRQHandler(void) { callback_router(16); } -void TIM17_IRQHandler(void) { + void TIM17_IRQHandler(void) { callback_router(17); } #endif diff --git a/ports/stm/peripherals/timers.h b/ports/stm/peripherals/timers.h index c4b6c6367..26cba88a0 100644 --- a/ports/stm/peripherals/timers.h +++ b/ports/stm/peripherals/timers.h @@ -32,15 +32,15 @@ void tim_clock_enable(uint16_t mask); void tim_clock_disable(uint16_t mask); -uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef * timer); -size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef * instance); +uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef *timer); +size_t stm_peripherals_timer_get_irqnum(TIM_TypeDef *instance); void timers_reset(void); -TIM_TypeDef * stm_peripherals_find_timer(void); -void stm_peripherals_timer_preinit(TIM_TypeDef * instance, uint8_t prio, void (*callback)(void)); -void stm_peripherals_timer_reserve(TIM_TypeDef * instance); -void stm_peripherals_timer_free(TIM_TypeDef * instance); -void stm_peripherals_timer_never_reset(TIM_TypeDef * instance); -void stm_peripherals_timer_reset_ok(TIM_TypeDef * instance); -bool stm_peripherals_timer_is_never_reset(TIM_TypeDef * instance); -bool stm_peripherals_timer_is_reserved(TIM_TypeDef * instance); -size_t stm_peripherals_timer_get_index(TIM_TypeDef * instance); +TIM_TypeDef *stm_peripherals_find_timer(void); +void stm_peripherals_timer_preinit(TIM_TypeDef *instance, uint8_t prio, void (*callback)(void)); +void stm_peripherals_timer_reserve(TIM_TypeDef *instance); +void stm_peripherals_timer_free(TIM_TypeDef *instance); +void stm_peripherals_timer_never_reset(TIM_TypeDef *instance); +void stm_peripherals_timer_reset_ok(TIM_TypeDef *instance); +bool stm_peripherals_timer_is_never_reset(TIM_TypeDef *instance); +bool stm_peripherals_timer_is_reserved(TIM_TypeDef *instance); +size_t stm_peripherals_timer_get_index(TIM_TypeDef *instance); diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 78ee4f3e6..560081013 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -52,47 +52,47 @@ typedef struct { #if defined(STM32F4) - STATIC const flash_layout_t flash_layout[] = { - { 0x08000000, 0x04000, 4 }, - { 0x08010000, 0x10000, 1 }, - { 0x08020000, 0x20000, 3 }, - #if defined(FLASH_SECTOR_8) - { 0x08080000, 0x20000, 4 }, - #endif - #if defined(FLASH_SECTOR_12) - { 0x08100000, 0x04000, 4 }, - { 0x08110000, 0x10000, 1 }, - { 0x08120000, 0x20000, 7 }, - #endif - }; - STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); +STATIC const flash_layout_t flash_layout[] = { + { 0x08000000, 0x04000, 4 }, + { 0x08010000, 0x10000, 1 }, + { 0x08020000, 0x20000, 3 }, + #if defined(FLASH_SECTOR_8) + { 0x08080000, 0x20000, 4 }, + #endif + #if defined(FLASH_SECTOR_12) + { 0x08100000, 0x04000, 4 }, + { 0x08110000, 0x10000, 1 }, + { 0x08120000, 0x20000, 7 }, + #endif +}; +STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); #elif defined(STM32F7) - // FLASH_FLAG_PGSERR (Programming Sequence Error) was renamed to - // FLASH_FLAG_ERSERR (Erasing Sequence Error) in STM32F7 +// FLASH_FLAG_PGSERR (Programming Sequence Error) was renamed to +// FLASH_FLAG_ERSERR (Erasing Sequence Error) in STM32F7 #define FLASH_FLAG_PGSERR FLASH_FLAG_ERSERR #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) - static const flash_layout_t flash_layout[] = { - { 0x08000000, 0x04000, 4 }, - { 0x08010000, 0x10000, 1 }, - { 0x08020000, 0x20000, 3 }, - }; - STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); +static const flash_layout_t flash_layout[] = { + { 0x08000000, 0x04000, 4 }, + { 0x08010000, 0x10000, 1 }, + { 0x08020000, 0x20000, 3 }, +}; +STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); #else - static const flash_layout_t flash_layout[] = { - { 0x08000000, 0x08000, 4 }, - { 0x08020000, 0x20000, 1 }, - { 0x08040000, 0x40000, 3 }, - }; - STATIC uint8_t _flash_cache[0x8000] __attribute__((aligned(4))); +static const flash_layout_t flash_layout[] = { + { 0x08000000, 0x08000, 4 }, + { 0x08020000, 0x20000, 1 }, + { 0x08040000, 0x40000, 3 }, +}; +STATIC uint8_t _flash_cache[0x8000] __attribute__((aligned(4))); #endif #elif defined(STM32H7) - STATIC const flash_layout_t flash_layout[] = { - { 0x08000000, 0x20000, 16 }, - }; - STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4))); +STATIC const flash_layout_t flash_layout[] = { + { 0x08000000, 0x20000, 16 }, +}; +STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4))); #else #error Unsupported processor @@ -125,7 +125,7 @@ STATIC uint32_t get_bank(uint32_t addr) { } #endif -//Return the sector of a given flash address. +// Return the sector of a given flash address. uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) { if (addr >= flash_layout[0].base_address) { uint32_t sector_index = 0; @@ -162,13 +162,15 @@ uint32_t supervisor_flash_get_block_count(void) { } void port_internal_flash_flush(void) { - if (_cache_flash_addr == NO_CACHE) return; + if (_cache_flash_addr == NO_CACHE) { + return; + } #if defined(STM32H7) __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK2); #else __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); #endif // set up for erase @@ -200,13 +202,13 @@ void port_internal_flash_flush(void) { reset_into_safe_mode(FLASH_WRITE_FAIL); } - uint32_t * cache_addr = (uint32_t*)_flash_cache; + uint32_t *cache_addr = (uint32_t *)_flash_cache; #if defined(STM32H7) for (uint32_t i = 0; i < (sector_size / 32); i++) { // Note that the STM32H7 HAL interface differs by taking an address, not 64 bit data if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, sector_start_addr, - (uint32_t)cache_addr) != HAL_OK) { + (uint32_t)cache_addr) != HAL_OK) { // error occurred during flash write HAL_FLASH_Lock(); // lock the flash reset_into_safe_mode(FLASH_WRITE_FAIL); @@ -220,7 +222,7 @@ void port_internal_flash_flush(void) { // program the flash word by word for (uint32_t i = 0; i < sector_size / 4; i++) { if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, sector_start_addr, - (uint64_t)*cache_addr) != HAL_OK) { + (uint64_t)*cache_addr) != HAL_OK) { // error occurred during flash write HAL_FLASH_Lock(); // lock the flash reset_into_safe_mode(FLASH_WRITE_FAIL); @@ -257,17 +259,17 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n uint32_t sector_start_addr; flash_get_sector_info(src, §or_start_addr, §or_size); // Count how many blocks are left in the sector - uint32_t count = (sector_size - (src - sector_start_addr))/FILESYSTEM_BLOCK_SIZE; + uint32_t count = (sector_size - (src - sector_start_addr)) / FILESYSTEM_BLOCK_SIZE; count = MIN(num_blocks, count); if (count < num_blocks && _cache_flash_addr == sector_start_addr) { // Read is contained in the cache, so just read cache - memcpy(dest, (_flash_cache + (src-sector_start_addr)), FILESYSTEM_BLOCK_SIZE*num_blocks); + memcpy(dest, (_flash_cache + (src - sector_start_addr)), FILESYSTEM_BLOCK_SIZE * num_blocks); } else { // The read spans multiple sectors or is in another sector // Must write out anything in cache before trying to read. supervisor_flash_flush(); - memcpy(dest, (uint8_t*) src, FILESYSTEM_BLOCK_SIZE*num_blocks); + memcpy(dest, (uint8_t *)src, FILESYSTEM_BLOCK_SIZE * num_blocks); } return 0; // success @@ -294,7 +296,7 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, } // Find how many blocks are left in the sector - uint32_t count = (sector_size - (dest - sector_start_addr))/FILESYSTEM_BLOCK_SIZE; + uint32_t count = (sector_size - (dest - sector_start_addr)) / FILESYSTEM_BLOCK_SIZE; count = MIN(num_blocks, count); if (_cache_flash_addr != sector_start_addr) { @@ -308,11 +310,11 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, } // Overwrite part or all of the sector cache with the src data. - memcpy(_flash_cache + (dest-sector_start_addr), src, count * FILESYSTEM_BLOCK_SIZE); + memcpy(_flash_cache + (dest - sector_start_addr), src, count * FILESYSTEM_BLOCK_SIZE); // adjust for next run - block_num += count; - src += count * FILESYSTEM_BLOCK_SIZE; + block_num += count; + src += count * FILESYSTEM_BLOCK_SIZE; num_blocks -= count; } diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 19ae03e0b..106ff6c54 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -34,15 +34,15 @@ #include "py/mpconfig.h" #ifdef STM32F401xE -#define STM32_FLASH_SIZE 0x80000 //512KiB -#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define STM32_FLASH_SIZE 0x80000 // 512KiB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 #endif #ifdef STM32F411xE -#define STM32_FLASH_SIZE 0x80000 //512KiB +#define STM32_FLASH_SIZE 0x80000 // 512KiB #ifndef INTERNAL_FLASH_FILESYSTEM_SIZE - #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB + #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB #endif #ifndef INTERNAL_FLASH_FILESYSTEM_START_ADDR #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 @@ -50,45 +50,45 @@ #endif #ifdef STM32F412Zx -#define STM32_FLASH_SIZE 0x100000 //1MB -#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define STM32_FLASH_SIZE 0x100000 // 1MB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 #endif #ifdef STM32F405xx -#define STM32_FLASH_SIZE 0x100000 //1MB -#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define STM32_FLASH_SIZE 0x100000 // 1MB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 #endif #ifdef STM32F407xx -#define STM32_FLASH_SIZE 0x100000 //1MB -#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define STM32_FLASH_SIZE 0x100000 // 1MB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 #endif /* Note this applies to STM32F769xG only, STM32F746xE has 512KB */ #ifdef STM32F746xx -#define STM32_FLASH_SIZE 0x100000 //1MB -#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 //96KiB +#define STM32_FLASH_SIZE 0x100000 // 1MB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 // 96KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08008000 #endif #ifdef STM32F767xx -#define STM32_FLASH_SIZE 0x200000 //2MB -#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 //96KiB +#define STM32_FLASH_SIZE 0x200000 // 2MB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 // 96KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08008000 #endif #ifdef STM32H743xx -#define STM32_FLASH_SIZE 0x200000 //2MB -#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x60000 //384KiB +#define STM32_FLASH_SIZE 0x200000 // 2MB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x60000 // 384KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08020000 #endif #define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) -#define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location +#define STM32_FLASH_OFFSET 0x8000000 // All STM32 chips map to this flash location #define INTERNAL_FLASH_SYSTICK_MASK (0x1ff) // 512ms #define INTERNAL_FLASH_IDLE_TICK(tick) (((tick) & INTERNAL_FLASH_SYSTICK_MASK) == 2) diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index 3103a0716..4a7583eb2 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -98,14 +98,14 @@ extern void SystemInit(void); // This replaces the Reset_Handler in gcc/startup_*.s, calls SystemInit from system_*.c __attribute__((used, naked)) void Reset_Handler(void) { __disable_irq(); - __set_MSP((uint32_t) &_ld_stack_top); + __set_MSP((uint32_t)&_ld_stack_top); /* Disable MPU */ ARM_MPU_Disable(); // Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write // protect it. - for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_itcm_size) / 4; i++) { (&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i]; } @@ -133,22 +133,22 @@ __attribute__((used, naked)) void Reset_Handler(void) { ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); // Copy all of the data to run from DTCM. - for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_data_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_data_size) / 4; i++) { (&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i]; } // Clear DTCM bss. - for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_bss_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_bss_size) / 4; i++) { (&_ld_dtcm_bss_start)[i] = 0; } // Copy all of the data to run from D1 RAM. - for (uint32_t i = 0; i < ((size_t) &_ld_d1_ram_data_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_d1_ram_data_size) / 4; i++) { (&_ld_d1_ram_data_destination)[i] = (&_ld_d1_ram_data_flash_copy)[i]; } // Clear D1 RAM bss. - for (uint32_t i = 0; i < ((size_t) &_ld_d1_ram_bss_size) / 4; i++) { + for (uint32_t i = 0; i < ((size_t)&_ld_d1_ram_bss_size) / 4; i++) { (&_ld_d1_ram_bss_start)[i] = 0; } @@ -156,7 +156,7 @@ __attribute__((used, naked)) void Reset_Handler(void) { __enable_irq(); main(); } -#endif //end H7 specific code +#endif // end H7 specific code // Low power clock variables static volatile uint32_t systick_ms; @@ -173,7 +173,7 @@ safe_mode_t port_init(void) { __HAL_RCC_SYSCFG_CLK_ENABLE(); #if (CPY_STM32F4) - __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); #endif stm32_peripherals_clocks_init(); @@ -229,24 +229,24 @@ void SysTick_Handler(void) { void reset_port(void) { reset_all_pins(); -#if CIRCUITPY_BUSIO + #if CIRCUITPY_BUSIO i2c_reset(); spi_reset(); uart_reset(); -#endif -#if CIRCUITPY_SDIOIO + #endif + #if CIRCUITPY_SDIOIO sdioio_reset(); -#endif -#if CIRCUITPY_PULSEIO || CIRCUITPY_PWMIO + #endif + #if CIRCUITPY_PULSEIO || CIRCUITPY_PWMIO timers_reset(); -#endif -#if CIRCUITPY_PULSEIO + #endif + #if CIRCUITPY_PULSEIO pulseout_reset(); pulsein_reset(); -#endif -#if CIRCUITPY_PWMIO + #endif + #if CIRCUITPY_PWMIO pwmout_reset(); -#endif + #endif } void reset_to_bootloader(void) { @@ -290,35 +290,31 @@ uint32_t port_get_saved_word(void) { return _ebss; } -__attribute__((used)) void MemManage_Handler(void) -{ +__attribute__((used)) void MemManage_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } -__attribute__((used)) void BusFault_Handler(void) -{ +__attribute__((used)) void BusFault_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } -__attribute__((used)) void UsageFault_Handler(void) -{ +__attribute__((used)) void UsageFault_Handler(void) { reset_into_safe_mode(MEM_MANAGE); while (true) { - asm("nop;"); + asm ("nop;"); } } -__attribute__((used)) void HardFault_Handler(void) -{ +__attribute__((used)) void HardFault_Handler(void) { reset_into_safe_mode(HARD_CRASH); while (true) { - asm("nop;"); + asm ("nop;"); } } @@ -328,7 +324,7 @@ volatile uint32_t seconds_to_date = 0; volatile uint32_t cached_date = 0; volatile uint32_t seconds_to_minute = 0; volatile uint32_t cached_hours_minutes = 0; -uint64_t port_get_raw_ticks(uint8_t* subticks) { +uint64_t port_get_raw_ticks(uint8_t *subticks) { // Disable IRQs to ensure we read all of the RTC registers as close in time as possible. Read // SSR twice to make sure we didn't read across a tick. __disable_irq(); @@ -372,7 +368,7 @@ uint64_t port_get_raw_ticks(uint8_t* subticks) { *subticks = subseconds % 32; } - uint64_t raw_ticks = ((uint64_t) 1024) * (seconds_to_date + seconds_to_minute + seconds) + subseconds / 32; + uint64_t raw_ticks = ((uint64_t)1024) * (seconds_to_date + seconds_to_minute + seconds) + subseconds / 32; return raw_ticks; } @@ -424,7 +420,7 @@ void port_interrupt_after_ticks(uint32_t ticks) { } alarm.AlarmTime.SubSeconds = rtc_clock_frequency - 1 - - ((raw_ticks % 1024) * 32); + ((raw_ticks % 1024) * 32); alarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; alarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_SET; // Masking here means that the bits are ignored so we set none of them. @@ -438,9 +434,9 @@ void port_interrupt_after_ticks(uint32_t ticks) { void port_idle_until_interrupt(void) { // Clear the FPU interrupt because it can prevent us from sleeping. - if (__get_FPSCR() & ~(0x9f)) { - __set_FPSCR(__get_FPSCR() & ~(0x9f)); - (void) __get_FPSCR(); + if (__get_FPSCR() & ~(0x9f)) { + __set_FPSCR(__get_FPSCR() & ~(0x9f)); + (void)__get_FPSCR(); } if (alarmed_already) { return; @@ -450,7 +446,6 @@ void port_idle_until_interrupt(void) { // Required by __libc_init_array in startup code if we are compiling using // -nostdlib/-nostartfiles. -void _init(void) -{ +void _init(void) { } diff --git a/ports/stm/supervisor/qspi_flash.c b/ports/stm/supervisor/qspi_flash.c index f3915273b..330e27dbd 100644 --- a/ports/stm/supervisor/qspi_flash.c +++ b/ports/stm/supervisor/qspi_flash.c @@ -31,9 +31,9 @@ #include <string.h> #include "py/mpconfig.h" // for EXTERNAL_FLASH_QSPI_DUAL -//#include "nrfx_qspi.h" +// #include "nrfx_qspi.h" -//#include "shared-bindings/microcontroller/__init__.h" +// #include "shared-bindings/microcontroller/__init__.h" #include "supervisor/shared/external_flash/common_commands.h" #include "supervisor/shared/external_flash/qspi_flash.h" @@ -47,10 +47,10 @@ bool spi_flash_command(uint8_t command) { // .wipwait = false, // .wren = false // }; - return false; //nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL) == NRFX_SUCCESS; + return false; // nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL) == NRFX_SUCCESS; } -bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length) { +bool spi_flash_read_command(uint8_t command, uint8_t *response, uint32_t length) { // nrf_qspi_cinstr_conf_t cinstr_cfg = { // .opcode = command, // .length = length + 1, @@ -64,7 +64,7 @@ bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length) } -bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) { +bool spi_flash_write_command(uint8_t command, uint8_t *data, uint32_t length) { // nrf_qspi_cinstr_conf_t cinstr_cfg = { // .opcode = command, // .length = length + 1, @@ -85,12 +85,12 @@ bool spi_flash_sector_command(uint8_t command, uint32_t address) { return false; } -bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) { +bool spi_flash_write_data(uint32_t address, uint8_t *data, uint32_t length) { // return nrfx_qspi_write(data, length, address) == NRFX_SUCCESS; return false; } -bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) { +bool spi_flash_read_data(uint32_t address, uint8_t *data, uint32_t length) { // return nrfx_qspi_read(data, length, address) == NRFX_SUCCESS; return false; } @@ -139,7 +139,7 @@ void spi_flash_init(void) { // nrfx_qspi_init(&qspi_cfg, NULL, NULL); } -void spi_flash_init_device(const external_flash_device* device) { +void spi_flash_init_device(const external_flash_device *device) { // check_quad_enable(device); // // Switch to single output line if the device doesn't support quad programs. diff --git a/ports/stm/supervisor/serial.c b/ports/stm/supervisor/serial.c index 3a058ed2e..ac6f69bbb 100644 --- a/ports/stm/supervisor/serial.c +++ b/ports/stm/supervisor/serial.c @@ -42,8 +42,7 @@ void serial_init(void) { huart2.Init.Mode = UART_MODE_TX_RX; huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; huart2.Init.OverSampling = UART_OVERSAMPLING_16; - if (HAL_UART_Init(&huart2) == HAL_OK) - { + if (HAL_UART_Init(&huart2) == HAL_OK) { stm32f4_peripherals_status_led(1,1); } } @@ -62,7 +61,7 @@ bool serial_bytes_available(void) { return __HAL_UART_GET_FLAG(&huart2, UART_FLAG_RXNE); } -void serial_write(const char* text) { +void serial_write(const char *text) { serial_write_substring(text, strlen(text)); } @@ -70,5 +69,5 @@ void serial_write_substring(const char *text, uint32_t len) { if (len == 0) { return; } - HAL_UART_Transmit(&huart2, (uint8_t*)text, len, 5000); + HAL_UART_Transmit(&huart2, (uint8_t *)text, len, 5000); } diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index c0e012cc6..906d07f73 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -37,33 +37,33 @@ STATIC void init_usb_vbus_sense(void) { -#if (BOARD_NO_VBUS_SENSE) + #if (BOARD_NO_VBUS_SENSE) // Disable VBUS sensing #ifdef USB_OTG_GCCFG_VBDEN - // Deactivate VBUS Sensing B - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + // Deactivate VBUS Sensing B + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; - // B-peripheral session valid override enable - USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + // B-peripheral session valid override enable + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; #else - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; #endif -#else + #else // Enable VBUS hardware sensing #ifdef USB_OTG_GCCFG_VBDEN - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; #else - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // B Device sense + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // B Device sense + #endif #endif -#endif } void init_usb_hardware(void) { - //TODO: if future chips overload this with options, move to peripherals management. + // TODO: if future chips overload this with options, move to peripherals management. GPIO_InitTypeDef GPIO_InitStruct = {0}; /**USB_OTG_FS GPIO Configuration @@ -73,7 +73,7 @@ void init_usb_hardware(void) { */ __HAL_RCC_GPIOA_CLK_ENABLE(); - /* Configure DM DP Pins */ + /* Configure DM DP Pins */ GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -135,5 +135,5 @@ void init_usb_hardware(void) { } void OTG_FS_IRQHandler(void) { - usb_irq_handler(); + usb_irq_handler(); } diff --git a/ports/stm/tools/parse_af_csv.py b/ports/stm/tools/parse_af_csv.py index 06af3bf1e..38608b5da 100644 --- a/ports/stm/tools/parse_af_csv.py +++ b/ports/stm/tools/parse_af_csv.py @@ -36,40 +36,43 @@ import sys def evaluate_periph(inper, inlist, periph, subtype, altfn, pin): # ex) SPI1_SCK,SPI3_SCK/I2S3_CK # Clean anything after a '\' due to SPI/I2S mixing - if not inper.find('/') == -1: - inper = inper[:inper.find('/')] + if not inper.find("/") == -1: + inper = inper[: inper.find("/")] + + if inper[: len(periph)] == periph and inper[-len(subtype) :] == subtype: + inlist.append([inper[len(periph) : len(periph) + 1], altfn, pin]) - if inper[:len(periph)] == periph and inper[-len(subtype):] == subtype: - inlist.append([inper[len(periph):len(periph)+1], altfn, pin]) # Timers (TIM) are a special case with 4 values # timer index, alt function, channel, pin string def evaluate_tim(inper, inlist, altfn, pin): # ex) TIM2_CH1/TIM2_ETR, TIM5_CH1 # Clean anything after a '\' to filter ETR - if not inper.find('/') == -1: - inper = inper[:inper.find('/')] + if not inper.find("/") == -1: + inper = inper[: inper.find("/")] + + if inper[:3] == "TIM" and inper[5:7] == "CH" and inper[-1:] != "N": + inlist.append([inper[3:4], altfn, inper[-1:], pin]) + elif inper[:3] == "TIM" and inper[6:8] == "CH" and inper[-1:] != "N": + inlist.append([inper[3:5], altfn, inper[-1:], pin]) - if inper[:3] == "TIM" and inper[5:7] == "CH" and inper[-1:] != 'N': - inlist.append([inper[3:4],altfn,inper[-1:],pin]) - elif inper[:3] == "TIM" and inper[6:8] == "CH" and inper[-1:] != 'N': - inlist.append([inper[3:5],altfn,inper[-1:],pin]) # Open target file with open(sys.argv[1]) as csv_file: - csv_reader = csv.reader(csv_file, delimiter=',') + csv_reader = csv.reader(csv_file, delimiter=",") line_count = 0 if sys.argv[2] != "-pins-only": # List of peripheral pin types to read todo = [ - ["I2C","SDA"], - ["I2C","SCL"], - ["SPI","SCK"], - ["SPI","MOSI"], - ["SPI","MISO"], - ["UART","TX"], - ["UART","RX"]] + ["I2C", "SDA"], + ["I2C", "SCL"], + ["SPI", "SCK"], + ["SPI", "MOSI"], + ["SPI", "MISO"], + ["UART", "TX"], + ["UART", "RX"], + ] # Make a list of empty lists to populate outlist = [] @@ -85,7 +88,7 @@ with open(sys.argv[1]) as csv_file: altfn = 0 pin = row[1] if len(pin) < 4: - pin = pin[:2] + '0' + pin[2:] + pin = pin[:2] + "0" + pin[2:] for col in row: array_index = 0 # Evaluate the string for every possible todo entry @@ -93,7 +96,9 @@ with open(sys.argv[1]) as csv_file: evaluate_periph(col, outlist[array_index], item[0], item[1], altfn - 2, pin) # UART special case, run again for USART variant if item[0] == "UART": - evaluate_periph(col, outlist[array_index], "USART", item[1], altfn - 2, pin) + evaluate_periph( + col, outlist[array_index], "USART", item[1], altfn - 2, pin + ) array_index += 1 # TIM special case evaluate_tim(col, outlist[-1], altfn - 2, pin) @@ -102,7 +107,7 @@ with open(sys.argv[1]) as csv_file: # Print formatted output for i in range(len(todo)): - ins = (todo[i][0]).lower() + '_' + (todo[i][1]).lower() + '_' + ins = (todo[i][0]).lower() + "_" + (todo[i][1]).lower() + "_" # const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4] = { print("const mcu_periph_obj_t mcu_" + ins + "list[" + str(len(outlist[i])) + "] = {") for row in outlist[i]: @@ -112,7 +117,17 @@ with open(sys.argv[1]) as csv_file: # Timer special case: print("const mcu_tim_pin_obj_t mcu_tim_pin_list[" + str(len(outlist[-1])) + "] = {") for row in outlist[-1]: - print(" TIM(" + row[0] + ", " + str(row[1]) + ", " + str(row[2]) + ", &pin_" + row[3] + "),") + print( + " TIM(" + + row[0] + + ", " + + str(row[1]) + + ", " + + str(row[2]) + + ", &pin_" + + row[3] + + ")," + ) print("};") else: @@ -126,14 +141,22 @@ with open(sys.argv[1]) as csv_file: altfn = 0 pin = row[1] if len(pin) < 4: - pin = pin[:2] + '0' + pin[2:] + pin = pin[:2] + "0" + pin[2:] outlist.append([pin, str(ord(row[1][1:2]) - 65), row[1][2:4]]) line_count += 1 for line in outlist: - print("const mcu_pin_obj_t pin_" + line[0] + " = PIN(" + line[1] + ", " + line[2] + ", NO_ADC);") + print( + "const mcu_pin_obj_t pin_" + + line[0] + + " = PIN(" + + line[1] + + ", " + + line[2] + + ", NO_ADC);" + ) for line in outlist: print("extern const mcu_pin_obj_t pin_" + line[0] + ";") - print(f'Processed {line_count} lines.') + print(f"Processed {line_count} lines.") diff --git a/ports/stm/tools/parse_pins_csv.py b/ports/stm/tools/parse_pins_csv.py index 68f6db586..972c6b6a8 100644 --- a/ports/stm/tools/parse_pins_csv.py +++ b/ports/stm/tools/parse_pins_csv.py @@ -33,7 +33,7 @@ import sys # Open target file with open(sys.argv[1]) as csv_file: - csv_reader = csv.reader(csv_file, delimiter=',') + csv_reader = csv.reader(csv_file, delimiter=",") line_count = 0 print("STATIC const mp_rom_map_elem_t board_module_globals_table[] = {") @@ -42,8 +42,8 @@ with open(sys.argv[1]) as csv_file: label = row[0] pin = row[1] if len(pin) < 4: - pin = pin[:2] + '0' + pin[2:] + pin = pin[:2] + "0" + pin[2:] print("{ MP_ROM_QSTR(MP_QSTR_" + label + "), MP_ROM_PTR(&pin_" + pin + ") },") line_count += 1 - print(f'Processed {line_count} lines.') + print(f"Processed {line_count} lines.") diff --git a/ports/unix/alloc.c b/ports/unix/alloc.c index ca12d025b..7fe7b4dba 100644 --- a/ports/unix/alloc.c +++ b/ports/unix/alloc.c @@ -69,7 +69,7 @@ void mp_unix_free_exec(void *ptr, size_t size) { munmap(ptr, size); // unlink the mmap'd region from the list - for (mmap_region_t **rg = (mmap_region_t**)&MP_STATE_VM(mmap_region_head); *rg != NULL; *rg = (*rg)->next) { + for (mmap_region_t **rg = (mmap_region_t **)&MP_STATE_VM(mmap_region_head); *rg != NULL; *rg = (*rg)->next) { if ((*rg)->ptr == ptr) { mmap_region_t *next = (*rg)->next; m_del_obj(mmap_region_t, *rg); diff --git a/ports/unix/coverage.c b/ports/unix/coverage.c index 849820fff..2d377bc8f 100644 --- a/ports/unix/coverage.c +++ b/ports/unix/coverage.c @@ -105,7 +105,7 @@ STATIC const mp_stream_p_t fileio_stream_p = { STATIC const mp_obj_type_t mp_type_stest_fileio = { { &mp_type_type }, .protocol = &fileio_stream_p, - .locals_dict = (mp_obj_dict_t*)&rawfile_locals_dict, + .locals_dict = (mp_obj_dict_t *)&rawfile_locals_dict, }; // stream read returns non-blocking error @@ -133,12 +133,12 @@ STATIC const mp_stream_p_t textio_stream_p2 = { STATIC const mp_obj_type_t mp_type_stest_textio2 = { { &mp_type_type }, .protocol = &textio_stream_p2, - .locals_dict = (mp_obj_dict_t*)&rawfile_locals_dict2, + .locals_dict = (mp_obj_dict_t *)&rawfile_locals_dict2, }; // str/bytes objects without a valid hash -STATIC const mp_obj_str_t str_no_hash_obj = {{&mp_type_str}, 0, 10, (const byte*)"0123456789"}; -STATIC const mp_obj_str_t bytes_no_hash_obj = {{&mp_type_bytes}, 0, 10, (const byte*)"0123456789"}; +STATIC const mp_obj_str_t str_no_hash_obj = {{&mp_type_str}, 0, 10, (const byte *)"0123456789"}; +STATIC const mp_obj_str_t bytes_no_hash_obj = {{&mp_type_bytes}, 0, 10, (const byte *)"0123456789"}; // function to run extra tests for things that can't be checked by scripts STATIC mp_obj_t extra_coverage(void) { @@ -380,10 +380,10 @@ STATIC mp_obj_t extra_coverage(void) { // call mp_execute_bytecode with invalide bytecode (should raise NotImplementedError) mp_obj_fun_bc_t fun_bc; - fun_bc.bytecode = (const byte*)"\x01"; // just needed for n_state + fun_bc.bytecode = (const byte *)"\x01"; // just needed for n_state mp_code_state_t *code_state = m_new_obj_var(mp_code_state_t, mp_obj_t, 1); code_state->fun_bc = &fun_bc; - code_state->ip = (const byte*)"\x00"; // just needed for an invalid opcode + code_state->ip = (const byte *)"\x00"; // just needed for an invalid opcode code_state->sp = &code_state->state[0]; code_state->exc_sp = NULL; code_state->old_globals = NULL; diff --git a/ports/unix/file.c b/ports/unix/file.c index 222dca462..892457ed5 100644 --- a/ports/unix/file.c +++ b/ports/unix/file.c @@ -104,7 +104,7 @@ STATIC mp_uint_t fdfile_ioctl(mp_obj_t o_in, mp_uint_t request, uintptr_t arg, i check_fd_is_open(o); switch (request) { case MP_STREAM_SEEK: { - struct mp_stream_seek_t *s = (struct mp_stream_seek_t*)arg; + struct mp_stream_seek_t *s = (struct mp_stream_seek_t *)arg; off_t off = lseek(o->fd, s->offset, s->whence); if (off == (off_t)-1) { *errcode = errno; @@ -175,7 +175,7 @@ STATIC mp_obj_t fdfile_open(const mp_obj_type_t *type, mp_arg_val_t *args) { case '+': mode_rw = O_RDWR; break; - #if MICROPY_PY_IO_FILEIO + #if MICROPY_PY_IO_FILEIO // If we don't have io.FileIO, then files are in text mode implicitly case 'b': type = &mp_type_fileio; @@ -183,7 +183,7 @@ STATIC mp_obj_t fdfile_open(const mp_obj_type_t *type, mp_arg_val_t *args) { case 't': type = &mp_type_textio; break; - #endif + #endif } } @@ -244,7 +244,7 @@ const mp_obj_type_t mp_type_fileio = { .getiter = mp_identity_getiter, .iternext = mp_stream_unbuffered_iter, .protocol = &fileio_stream_p, - .locals_dict = (mp_obj_dict_t*)&rawfile_locals_dict, + .locals_dict = (mp_obj_dict_t *)&rawfile_locals_dict, }; #endif @@ -264,7 +264,7 @@ const mp_obj_type_t mp_type_textio = { .getiter = mp_identity_getiter, .iternext = mp_stream_unbuffered_iter, .protocol = &textio_stream_p, - .locals_dict = (mp_obj_dict_t*)&rawfile_locals_dict, + .locals_dict = (mp_obj_dict_t *)&rawfile_locals_dict, }; // Factory function for I/O stream classes @@ -276,7 +276,7 @@ mp_obj_t mp_builtin_open(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) } MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open); -const mp_obj_fdfile_t mp_sys_stdin_obj = { .base = {&mp_type_textio}, .fd = STDIN_FILENO }; +const mp_obj_fdfile_t mp_sys_stdin_obj = { .base = {&mp_type_textio}, .fd = STDIN_FILENO }; const mp_obj_fdfile_t mp_sys_stdout_obj = { .base = {&mp_type_textio}, .fd = STDOUT_FILENO }; const mp_obj_fdfile_t mp_sys_stderr_obj = { .base = {&mp_type_textio}, .fd = STDERR_FILENO }; diff --git a/ports/unix/gccollect.c b/ports/unix/gccollect.c index 7cd74ec13..45ad1e043 100644 --- a/ports/unix/gccollect.c +++ b/ports/unix/gccollect.c @@ -49,20 +49,20 @@ STATIC void gc_helper_get_regs(regs_t arr) { register long r13 asm ("r13"); register long r14 asm ("r14"); register long r15 asm ("r15"); -#ifdef __clang__ + #ifdef __clang__ // TODO: // This is dirty workaround for Clang. It tries to get around // uncompliant (wrt to GCC) behavior of handling register variables. // Application of this patch here is random, and done only to unbreak // MacOS build. Better, cross-arch ways to deal with Clang issues should // be found. - asm("" : "=r"(rbx)); - asm("" : "=r"(rbp)); - asm("" : "=r"(r12)); - asm("" : "=r"(r13)); - asm("" : "=r"(r14)); - asm("" : "=r"(r15)); -#endif + asm ("" : "=r" (rbx)); + asm ("" : "=r" (rbp)); + asm ("" : "=r" (r12)); + asm ("" : "=r" (r13)); + asm ("" : "=r" (r14)); + asm ("" : "=r" (r15)); + #endif arr[0] = rbx; arr[1] = rbp; arr[2] = r12; @@ -80,18 +80,18 @@ STATIC void gc_helper_get_regs(regs_t arr) { register long esi asm ("esi"); register long edi asm ("edi"); register long ebp asm ("ebp"); -#ifdef __clang__ + #ifdef __clang__ // TODO: // This is dirty workaround for Clang. It tries to get around // uncompliant (wrt to GCC) behavior of handling register variables. // Application of this patch here is random, and done only to unbreak // MacOS build. Better, cross-arch ways to deal with Clang issues should // be found. - asm("" : "=r"(ebx)); - asm("" : "=r"(esi)); - asm("" : "=r"(edi)); - asm("" : "=r"(ebp)); -#endif + asm ("" : "=r" (ebx)); + asm ("" : "=r" (esi)); + asm ("" : "=r" (edi)); + asm ("" : "=r" (ebp)); + #endif arr[0] = ebx; arr[1] = esi; arr[2] = edi; @@ -155,12 +155,12 @@ void gc_collect_regs_and_stack(void) { regs_t regs; gc_helper_get_regs(regs); // GC stack (and regs because we captured them) - void **regs_ptr = (void**)(void*)®s; + void **regs_ptr = (void **)(void *)®s; gc_collect_root(regs_ptr, ((uintptr_t)MP_STATE_THREAD(stack_top) - (uintptr_t)®s) / sizeof(uintptr_t)); } void gc_collect(void) { - //gc_dump_info(); + // gc_dump_info(); gc_collect_start(); gc_collect_regs_and_stack(); @@ -172,8 +172,8 @@ void gc_collect(void) { #endif gc_collect_end(); - //printf("-----\n"); - //gc_dump_info(); + // printf("-----\n"); + // gc_dump_info(); } -#endif //MICROPY_ENABLE_GC +#endif // MICROPY_ENABLE_GC diff --git a/ports/unix/input.c b/ports/unix/input.c index b661ce3e2..6fbb8513a 100644 --- a/ports/unix/input.c +++ b/ports/unix/input.c @@ -59,7 +59,7 @@ char *prompt(char *p) { #endif void prompt_read_history(void) { -#if MICROPY_USE_READLINE_HISTORY + #if MICROPY_USE_READLINE_HISTORY #if MICROPY_USE_READLINE == 1 readline_init0(); // will clear history pointers char *home = getenv("HOME"); @@ -91,11 +91,11 @@ void prompt_read_history(void) { vstr_clear(&vstr); } #endif -#endif + #endif } void prompt_write_history(void) { -#if MICROPY_USE_READLINE_HISTORY + #if MICROPY_USE_READLINE_HISTORY #if MICROPY_USE_READLINE == 1 char *home = getenv("HOME"); if (home != NULL) { @@ -117,5 +117,5 @@ void prompt_write_history(void) { } } #endif -#endif + #endif } diff --git a/ports/unix/main.c b/ports/unix/main.c index 5a3cbaf47..eb7f7521f 100644 --- a/ports/unix/main.c +++ b/ports/unix/main.c @@ -59,7 +59,7 @@ STATIC uint emit_opt = MP_EMIT_OPT_NONE; #if MICROPY_ENABLE_GC // Heap size of GC heap (if enabled) // Make it larger on a 64 bit machine, because pointers are larger. -long heap_size = 1024*1024 * (sizeof(mp_uint_t) / 4); +long heap_size = 1024 * 1024 * (sizeof(mp_uint_t) / 4); #endif STATIC void stderr_print_strn(void *env, const char *str, size_t len) { @@ -114,7 +114,7 @@ STATIC int execute_from_lexer(int source_kind, const void *source, mp_parse_inpu const vstr_t *vstr = source; lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, vstr->buf, vstr->len, false); } else if (source_kind == LEX_SRC_FILENAME) { - lex = mp_lexer_new_from_file((const char*)source); + lex = mp_lexer_new_from_file((const char *)source); } else { // LEX_SRC_STDIN lex = mp_lexer_new_from_fd(MP_QSTR__lt_stdin_gt_, 0, false); } @@ -303,25 +303,25 @@ STATIC int do_str(const char *str) { STATIC int usage(char **argv) { printf( -"usage: %s [<opts>] [-X <implopt>] [-c <command>] [<filename>]\n" -"Options:\n" -"-v : verbose (trace various operations); can be multiple\n" -"-O[N] : apply bytecode optimizations of level N\n" -"\n" -"Implementation specific options (-X):\n", argv[0] -); + "usage: %s [<opts>] [-X <implopt>] [-c <command>] [<filename>]\n" + "Options:\n" + "-v : verbose (trace various operations); can be multiple\n" + "-O[N] : apply bytecode optimizations of level N\n" + "\n" + "Implementation specific options (-X):\n", argv[0] + ); int impl_opts_cnt = 0; printf( -" compile-only -- parse and compile only\n" -" emit={bytecode,native,viper} -- set the default code emitter\n" -); + " compile-only -- parse and compile only\n" + " emit={bytecode,native,viper} -- set the default code emitter\n" + ); impl_opts_cnt++; -#if MICROPY_ENABLE_GC + #if MICROPY_ENABLE_GC printf( -" heapsize=<n>[w][K|M] -- set the heap size for the GC (default %ld)\n" -, heap_size); + " heapsize=<n>[w][K|M] -- set the heap size for the GC (default %ld)\n" + , heap_size); impl_opts_cnt++; -#endif + #endif if (impl_opts_cnt == 0) { printf(" (none)\n"); @@ -347,7 +347,7 @@ STATIC void pre_process_options(int argc, char **argv) { emit_opt = MP_EMIT_OPT_NATIVE_PYTHON; } else if (strcmp(argv[a + 1], "emit=viper") == 0) { emit_opt = MP_EMIT_OPT_VIPER; -#if MICROPY_ENABLE_GC + #if MICROPY_ENABLE_GC } else if (strncmp(argv[a + 1], "heapsize=", sizeof("heapsize=") - 1) == 0) { char *end; heap_size = strtol(argv[a + 1] + sizeof("heapsize=") - 1, &end, 0); @@ -380,9 +380,9 @@ STATIC void pre_process_options(int argc, char **argv) { if (heap_size < 700) { goto invalid_arg; } -#endif + #endif } else { -invalid_arg: + invalid_arg: printf("Invalid option\n"); exit(usage(argv)); } @@ -438,10 +438,10 @@ MP_NOINLINE int main_(int argc, char **argv) { pre_process_options(argc, argv); -#if MICROPY_ENABLE_GC + #if MICROPY_ENABLE_GC char *heap = malloc(heap_size); gc_init(heap, heap + heap_size); -#endif + #endif #if MICROPY_ENABLE_PYSTACK static mp_obj_t pystack[1024]; @@ -457,7 +457,7 @@ MP_NOINLINE int main_(int argc, char **argv) { mp_type_vfs_posix.make_new(&mp_type_vfs_posix, 0, 0, NULL), MP_OBJ_NEW_QSTR(MP_QSTR__slash_), }; - mp_vfs_mount(2, args, (mp_map_t*)&mp_const_empty_map); + mp_vfs_mount(2, args, (mp_map_t *)&mp_const_empty_map); MP_STATE_VM(vfs_cur) = MP_STATE_VM(vfs_mount_table); } #endif @@ -490,25 +490,25 @@ MP_NOINLINE int main_(int argc, char **argv) { // Frozen modules are in their own pseudo-dir, e.g., ".frozen". path_items[1] = MP_OBJ_NEW_QSTR(MP_FROZEN_FAKE_DIR_QSTR); { - char *p = path; - for (mp_uint_t i = builtin_path_count; i < path_num; i++) { - char *p1 = strchr(p, PATHLIST_SEP_CHAR); - if (p1 == NULL) { - p1 = p + strlen(p); - } - if (p[0] == '~' && p[1] == '/' && home != NULL) { - // Expand standalone ~ to $HOME - int home_l = strlen(home); - vstr_t vstr; - vstr_init(&vstr, home_l + (p1 - p - 1) + 1); - vstr_add_strn(&vstr, home, home_l); - vstr_add_strn(&vstr, p + 1, p1 - p - 1); - path_items[i] = mp_obj_new_str_from_vstr(&mp_type_str, &vstr); - } else { - path_items[i] = mp_obj_new_str_via_qstr(p, p1 - p); + char *p = path; + for (mp_uint_t i = builtin_path_count; i < path_num; i++) { + char *p1 = strchr(p, PATHLIST_SEP_CHAR); + if (p1 == NULL) { + p1 = p + strlen(p); + } + if (p[0] == '~' && p[1] == '/' && home != NULL) { + // Expand standalone ~ to $HOME + int home_l = strlen(home); + vstr_t vstr; + vstr_init(&vstr, home_l + (p1 - p - 1) + 1); + vstr_add_strn(&vstr, home, home_l); + vstr_add_strn(&vstr, p + 1, p1 - p - 1); + path_items[i] = mp_obj_new_str_from_vstr(&mp_type_str, &vstr); + } else { + path_items[i] = mp_obj_new_str_via_qstr(p, p1 - p); + } + p = p1 + 1; } - p = p1 + 1; - } } @@ -613,7 +613,8 @@ MP_NOINLINE int main_(int argc, char **argv) { MP_STATE_VM(mp_optimise_value) = argv[a][2] & 0xf; } else { MP_STATE_VM(mp_optimise_value) = 0; - for (char *p = argv[a] + 1; *p && *p == 'O'; p++, MP_STATE_VM(mp_optimise_value)++); + for (char *p = argv[a] + 1; *p && *p == 'O'; p++, MP_STATE_VM(mp_optimise_value)++) {; + } } } else { return usage(argv); @@ -661,13 +662,13 @@ MP_NOINLINE int main_(int argc, char **argv) { mp_deinit(); -#if MICROPY_ENABLE_GC && !defined(NDEBUG) + #if MICROPY_ENABLE_GC && !defined(NDEBUG) // We don't really need to free memory since we are about to exit the // process, but doing so helps to find memory leaks. free(heap); -#endif + #endif - //printf("total bytes = %d\n", m_get_total_bytes_allocated()); + // printf("total bytes = %d\n", m_get_total_bytes_allocated()); return ret & 0xff; } diff --git a/ports/unix/modffi.c b/ports/unix/modffi.c index c750f2eb7..a64d4a7b2 100644 --- a/ports/unix/modffi.c +++ b/ports/unix/modffi.c @@ -93,39 +93,50 @@ typedef struct _mp_obj_fficallback_t { ffi_type *params[]; } mp_obj_fficallback_t; -//STATIC const mp_obj_type_t opaque_type; +// STATIC const mp_obj_type_t opaque_type; STATIC const mp_obj_type_t ffimod_type; STATIC const mp_obj_type_t ffifunc_type; STATIC const mp_obj_type_t fficallback_type; STATIC const mp_obj_type_t ffivar_type; -STATIC ffi_type *char2ffi_type(char c) -{ +STATIC ffi_type *char2ffi_type(char c) { switch (c) { - case 'b': return &ffi_type_schar; - case 'B': return &ffi_type_uchar; - case 'h': return &ffi_type_sshort; - case 'H': return &ffi_type_ushort; - case 'i': return &ffi_type_sint; - case 'I': return &ffi_type_uint; - case 'l': return &ffi_type_slong; - case 'L': return &ffi_type_ulong; + case 'b': + return &ffi_type_schar; + case 'B': + return &ffi_type_uchar; + case 'h': + return &ffi_type_sshort; + case 'H': + return &ffi_type_ushort; + case 'i': + return &ffi_type_sint; + case 'I': + return &ffi_type_uint; + case 'l': + return &ffi_type_slong; + case 'L': + return &ffi_type_ulong; #if MICROPY_PY_BUILTINS_FLOAT - case 'f': return &ffi_type_float; - case 'd': return &ffi_type_double; + case 'f': + return &ffi_type_float; + case 'd': + return &ffi_type_double; #endif case 'O': // mp_obj_t case 'C': // (*)() case 'P': // const void* case 'p': // void* - case 's': return &ffi_type_pointer; - case 'v': return &ffi_type_void; - default: return NULL; + case 's': + return &ffi_type_pointer; + case 'v': + return &ffi_type_void; + default: + return NULL; } } -STATIC ffi_type *get_ffi_type(mp_obj_t o_in) -{ +STATIC ffi_type *get_ffi_type(mp_obj_t o_in) { if (MP_OBJ_IS_STR(o_in)) { const char *s = mp_obj_str_get_str(o_in); ffi_type *t = char2ffi_type(*s); @@ -138,8 +149,7 @@ STATIC ffi_type *get_ffi_type(mp_obj_t o_in) mp_raise_TypeError(translate("Unknown type")); } -STATIC mp_obj_t return_ffi_value(ffi_arg val, char type) -{ +STATIC mp_obj_t return_ffi_value(ffi_arg val, char type) { switch (type) { case 's': { const char *s = (const char *)(intptr_t)val; @@ -152,11 +162,13 @@ STATIC mp_obj_t return_ffi_value(ffi_arg val, char type) return mp_const_none; #if MICROPY_PY_BUILTINS_FLOAT case 'f': { - union { ffi_arg ffi; float flt; } val_union = { .ffi = val }; - return mp_obj_new_float((mp_float_t) val_union.flt); + union { ffi_arg ffi; + float flt; + } val_union = { .ffi = val }; + return mp_obj_new_float((mp_float_t)val_union.flt); } case 'd': { - double *p = (double*)&val; + double *p = (double *)&val; return mp_obj_new_float(*p); } #endif @@ -187,7 +199,7 @@ STATIC mp_obj_t make_func(mp_obj_t rettype_in, void *func, mp_obj_t argtypes_in) const char *argtypes = mp_obj_str_get_str(argtypes_in); mp_int_t nparams = MP_OBJ_SMALL_INT_VALUE(mp_obj_len_maybe(argtypes_in)); - mp_obj_ffifunc_t *o = m_new_obj_var(mp_obj_ffifunc_t, ffi_type*, nparams); + mp_obj_ffifunc_t *o = m_new_obj_var(mp_obj_ffifunc_t, ffi_type *, nparams); o->base.type = &ffifunc_type; o->func = func; @@ -224,20 +236,20 @@ STATIC mp_obj_t ffimod_func(size_t n_args, const mp_obj_t *args) { MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(ffimod_func_obj, 4, 4, ffimod_func); STATIC mp_obj_t mod_ffi_func(mp_obj_t rettype, mp_obj_t addr_in, mp_obj_t argtypes) { - void *addr = (void*)MP_OBJ_TO_PTR(mp_obj_int_get_truncated(addr_in)); + void *addr = (void *)MP_OBJ_TO_PTR(mp_obj_int_get_truncated(addr_in)); return make_func(rettype, addr, argtypes); } MP_DEFINE_CONST_FUN_OBJ_3(mod_ffi_func_obj, mod_ffi_func); -STATIC void call_py_func(ffi_cif *cif, void *ret, void** args, void *func) { +STATIC void call_py_func(ffi_cif *cif, void *ret, void **args, void *func) { mp_obj_t pyargs[cif->nargs]; for (uint i = 0; i < cif->nargs; i++) { - pyargs[i] = mp_obj_new_int(*(mp_int_t*)args[i]); + pyargs[i] = mp_obj_new_int(*(mp_int_t *)args[i]); } mp_obj_t res = mp_call_function_n_kw(MP_OBJ_FROM_PTR(func), cif->nargs, 0, pyargs); if (res != mp_const_none) { - *(ffi_arg*)ret = mp_obj_int_get_truncated(res); + *(ffi_arg *)ret = mp_obj_int_get_truncated(res); } } @@ -245,7 +257,7 @@ STATIC mp_obj_t mod_ffi_callback(mp_obj_t rettype_in, mp_obj_t func_in, mp_obj_t const char *rettype = mp_obj_str_get_str(rettype_in); mp_int_t nparams = MP_OBJ_SMALL_INT_VALUE(mp_obj_len_maybe(paramtypes_in)); - mp_obj_fficallback_t *o = m_new_obj_var(mp_obj_fficallback_t, ffi_type*, nparams); + mp_obj_fficallback_t *o = m_new_obj_var(mp_obj_fficallback_t, ffi_type *, nparams); o->base.type = &fficallback_type; o->clo = ffi_closure_alloc(sizeof(ffi_closure), &o->func); @@ -337,7 +349,7 @@ STATIC const mp_obj_type_t ffimod_type = { .name = MP_QSTR_ffimod, .print = ffimod_print, .make_new = ffimod_make_new, - .locals_dict = (mp_obj_dict_t*)&ffimod_locals_dict, + .locals_dict = (mp_obj_dict_t *)&ffimod_locals_dict, }; // FFI function @@ -362,10 +374,10 @@ STATIC mp_obj_t ffifunc_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const values[i] = (ffi_arg)(intptr_t)a; #if MICROPY_PY_BUILTINS_FLOAT } else if (*argtype == 'f') { - float *p = (float*)&values[i]; + float *p = (float *)&values[i]; *p = mp_obj_get_float(a); } else if (*argtype == 'd') { - double *p = (double*)&values[i]; + double *p = (double *)&values[i]; *p = mp_obj_get_float(a); #endif } else if (a == mp_const_none) { @@ -375,8 +387,8 @@ STATIC mp_obj_t ffifunc_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const } else if (MP_OBJ_IS_STR(a)) { const char *s = mp_obj_str_get_str(a); values[i] = (ffi_arg)(intptr_t)s; - } else if (((mp_obj_base_t*)MP_OBJ_TO_PTR(a))->type->buffer_p.get_buffer != NULL) { - mp_obj_base_t *o = (mp_obj_base_t*)MP_OBJ_TO_PTR(a); + } else if (((mp_obj_base_t *)MP_OBJ_TO_PTR(a))->type->buffer_p.get_buffer != NULL) { + mp_obj_base_t *o = (mp_obj_base_t *)MP_OBJ_TO_PTR(a); mp_buffer_info_t bufinfo; int ret = o->type->buffer_p.get_buffer(MP_OBJ_FROM_PTR(o), &bufinfo, MP_BUFFER_READ); // TODO: MP_BUFFER_READ? if (ret != 0) { @@ -440,7 +452,7 @@ STATIC void ffivar_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kin (void)kind; mp_obj_ffivar_t *self = MP_OBJ_TO_PTR(self_in); // Variable value printed as cast to int - mp_printf(print, "<ffivar @%p: 0x%x>", self->var, *(int*)self->var); + mp_printf(print, "<ffivar @%p: 0x%x>", self->var, *(int *)self->var); } STATIC mp_obj_t ffivar_get(mp_obj_t self_in) { @@ -467,7 +479,7 @@ STATIC const mp_obj_type_t ffivar_type = { { &mp_type_type }, .name = MP_QSTR_ffivar, .print = ffivar_print, - .locals_dict = (mp_obj_dict_t*)&ffivar_locals_dict, + .locals_dict = (mp_obj_dict_t *)&ffivar_locals_dict, }; // Generic opaque storage object (unused) @@ -486,7 +498,7 @@ STATIC mp_obj_t mod_ffi_open(size_t n_args, const mp_obj_t *args) { MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mod_ffi_open_obj, 1, 2, mod_ffi_open); STATIC mp_obj_t mod_ffi_as_bytearray(mp_obj_t ptr, mp_obj_t size) { - return mp_obj_new_bytearray_by_ref(mp_obj_int_get_truncated(size), (void*)(uintptr_t)mp_obj_int_get_truncated(ptr)); + return mp_obj_new_bytearray_by_ref(mp_obj_int_get_truncated(size), (void *)(uintptr_t)mp_obj_int_get_truncated(ptr)); } MP_DEFINE_CONST_FUN_OBJ_2(mod_ffi_as_bytearray_obj, mod_ffi_as_bytearray); @@ -502,5 +514,5 @@ STATIC MP_DEFINE_CONST_DICT(mp_module_ffi_globals, mp_module_ffi_globals_table); const mp_obj_module_t mp_module_ffi = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_ffi_globals, + .globals = (mp_obj_dict_t *)&mp_module_ffi_globals, }; diff --git a/ports/unix/modjni.c b/ports/unix/modjni.c index 82d1ccd55..a0d0cb1de 100644 --- a/ports/unix/modjni.c +++ b/ports/unix/modjni.c @@ -98,7 +98,7 @@ STATIC bool is_object_type(const char *jtypesig) { STATIC void check_exception(void) { jobject exc = JJ1(ExceptionOccurred); if (exc) { - //JJ1(ExceptionDescribe); + // JJ1(ExceptionDescribe); mp_obj_t py_e = new_jobject(exc); JJ1(ExceptionClear); if (JJ(IsInstanceOf, exc, IndexException_class)) { @@ -142,7 +142,7 @@ STATIC void jclass_attr(mp_obj_t self_in, qstr attr_in, mp_obj_t *dest) { dest[0] = new_jobject(obj); return; } - //JJ1(ExceptionDescribe); + // JJ1(ExceptionDescribe); JJ1(ExceptionClear); mp_obj_jmethod_t *o = m_new_obj(mp_obj_jmethod_t); @@ -179,7 +179,7 @@ STATIC const mp_obj_type_t jclass_type = { .print = jclass_print, .attr = jclass_attr, .call = jclass_call, - .locals_dict = (mp_obj_dict_t*)&jclass_locals_dict, + .locals_dict = (mp_obj_dict_t *)&jclass_locals_dict, }; STATIC mp_obj_t new_jclass(jclass jc) { @@ -220,7 +220,7 @@ STATIC void jobject_attr(mp_obj_t self_in, qstr attr_in, mp_obj_t *dest) { dest[0] = new_jobject(obj); return; } - //JJ1(ExceptionDescribe); + // JJ1(ExceptionDescribe); JJ1(ExceptionClear); mp_obj_jmethod_t *o = m_new_obj(mp_obj_jmethod_t); @@ -246,7 +246,7 @@ STATIC mp_obj_t jobject_subscr(mp_obj_t self_in, mp_obj_t index, mp_obj_t value) mp_uint_t idx = mp_obj_get_int(index); char class_name[64]; get_jclass_name(self->obj, class_name); - //printf("class: %s\n", class_name); + // printf("class: %s\n", class_name); if (class_name[0] == '[') { if (class_name[1] == 'L' || class_name[1] == '[') { @@ -288,7 +288,7 @@ STATIC mp_obj_t jobject_subscr(mp_obj_t self_in, mp_obj_t index, mp_obj_t value) } -return MP_OBJ_NULL; + return MP_OBJ_NULL; } STATIC mp_obj_t jobject_unary_op(mp_unary_op_t op, mp_obj_t self_in) { @@ -364,10 +364,10 @@ STATIC void jmethod_print(const mp_print_t *print, mp_obj_t self_in, mp_print_ki #define IMATCH(s, static) ((!strncmp(s, static, sizeof(static) - 1)) && (s += sizeof(static) - 1)) #define CHECK_TYPE(java_type_name) \ - if (strncmp(arg_type, java_type_name, sizeof(java_type_name) - 1) != 0) { \ - return false; \ - } \ - arg_type += sizeof(java_type_name) - 1; + if (strncmp(arg_type, java_type_name, sizeof(java_type_name) - 1) != 0) { \ + return false; \ + } \ + arg_type += sizeof(java_type_name) - 1; STATIC const char *strprev(const char *s, char c) { while (*s != c) { @@ -412,7 +412,7 @@ STATIC bool py2jvalue(const char **jtypesig, mp_obj_t arg, jvalue *out) { if (!MATCH(expected_type, "java.lang.Object")) { char class_name[64]; get_jclass_name(jo->obj, class_name); - //printf("Arg class: %s\n", class_name); + // printf("Arg class: %s\n", class_name); if (strcmp(class_name, expected_type) != 0) { return false; } @@ -425,7 +425,7 @@ STATIC bool py2jvalue(const char **jtypesig, mp_obj_t arg, jvalue *out) { return false; } } else if (arg == mp_const_none) { - //printf("TODO: Check java arg type!!\n"); + // printf("TODO: Check java arg type!!\n"); while (isalpha(*arg_type) || *arg_type == '.') { arg_type++; } @@ -470,7 +470,7 @@ STATIC mp_obj_t call_method(jobject obj, const char *name, jarray methods, bool jobject name_o = JJ(CallObjectMethod, meth, Object_toString_mid); const char *decl = JJ(GetStringUTFChars, name_o, NULL); const char *arg_types = strchr(decl, '(') + 1; - //const char *arg_types_end = strchr(arg_types, ')'); + // const char *arg_types_end = strchr(arg_types, ')'); // printf("method[%d]=%p %s\n", i, meth, decl); const char *meth_name = NULL; @@ -481,7 +481,7 @@ STATIC mp_obj_t call_method(jobject obj, const char *name, jarray methods, bool ret_type = strprev(ret_type, ' ') + 1; int name_len = strlen(name); - if (strncmp(name, meth_name, name_len/*arg_types - meth_name - 1*/) || meth_name[name_len] != '('/*(*/) { + if (strncmp(name, meth_name, name_len /*arg_types - meth_name - 1*/) || meth_name[name_len] != '(' /*(*/) { goto next_method; } } @@ -542,7 +542,7 @@ STATIC mp_obj_t call_method(jobject obj, const char *name, jarray methods, bool } } -next_method: + next_method: JJ(ReleaseStringUTFChars, name_o, decl); JJ(DeleteLocalRef, name_o); JJ(DeleteLocalRef, meth); @@ -602,9 +602,9 @@ STATIC void create_jvm() { if (!libjvm) { mp_raise_msg(&mp_type_OSError, "unable to load libjvm.so, use LD_LIBRARY_PATH"); } - int (*_JNI_CreateJavaVM)(void*, void**, void*) = dlsym(libjvm, "JNI_CreateJavaVM"); + int (*_JNI_CreateJavaVM)(void *, void **, void *) = dlsym(libjvm, "JNI_CreateJavaVM"); - int st = _JNI_CreateJavaVM(&jvm, (void**)&env, &args); + int st = _JNI_CreateJavaVM(&jvm, (void **)&env, &args); if (st < 0 || !env) { mp_raise_msg(&mp_type_OSError, "unable to create JVM"); } @@ -615,26 +615,26 @@ STATIC void create_jvm() { jclass Object_class = JJ(FindClass, "java/lang/Object"); Object_toString_mid = JJ(GetMethodID, Object_class, "toString", - "()Ljava/lang/String;"); + "()Ljava/lang/String;"); Class_getName_mid = (*env)->GetMethodID(env, Class_class, "getName", - "()Ljava/lang/String;"); + "()Ljava/lang/String;"); Class_getField_mid = (*env)->GetMethodID(env, Class_class, "getField", - "(Ljava/lang/String;)Ljava/lang/reflect/Field;"); + "(Ljava/lang/String;)Ljava/lang/reflect/Field;"); Class_getMethods_mid = (*env)->GetMethodID(env, Class_class, "getMethods", - "()[Ljava/lang/reflect/Method;"); + "()[Ljava/lang/reflect/Method;"); Class_getConstructors_mid = (*env)->GetMethodID(env, Class_class, "getConstructors", - "()[Ljava/lang/reflect/Constructor;"); + "()[Ljava/lang/reflect/Constructor;"); Method_getName_mid = (*env)->GetMethodID(env, method_class, "getName", - "()Ljava/lang/String;"); + "()Ljava/lang/String;"); List_class = JJ(FindClass, "java/util/List"); List_get_mid = JJ(GetMethodID, List_class, "get", - "(I)Ljava/lang/Object;"); + "(I)Ljava/lang/Object;"); List_set_mid = JJ(GetMethodID, List_class, "set", - "(ILjava/lang/Object;)Ljava/lang/Object;"); + "(ILjava/lang/Object;)Ljava/lang/Object;"); List_size_mid = JJ(GetMethodID, List_class, "size", - "()I"); + "()I"); IndexException_class = JJ(FindClass, "java/lang/IndexOutOfBoundsException"); } @@ -716,5 +716,5 @@ STATIC MP_DEFINE_CONST_DICT(mp_module_jni_globals, mp_module_jni_globals_table); const mp_obj_module_t mp_module_jni = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_jni_globals, + .globals = (mp_obj_dict_t *)&mp_module_jni_globals, }; diff --git a/ports/unix/modmachine.c b/ports/unix/modmachine.c index 61697cfb6..af3a9d88f 100644 --- a/ports/unix/modmachine.c +++ b/ports/unix/modmachine.c @@ -95,7 +95,7 @@ STATIC MP_DEFINE_CONST_DICT(machine_module_globals, machine_module_globals_table const mp_obj_module_t mp_module_machine = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&machine_module_globals, + .globals = (mp_obj_dict_t *)&machine_module_globals, }; #endif // MICROPY_PY_MACHINE diff --git a/ports/unix/modos.c b/ports/unix/modos.c index 252b19a50..57e00fa0c 100644 --- a/ports/unix/modos.c +++ b/ports/unix/modos.c @@ -230,5 +230,5 @@ STATIC MP_DEFINE_CONST_DICT(mp_module_os_globals, mp_module_os_globals_table); const mp_obj_module_t mp_module_os = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_os_globals, + .globals = (mp_obj_dict_t *)&mp_module_os_globals, }; diff --git a/ports/unix/modtermios.c b/ports/unix/modtermios.c index fe19aac83..bd723085d 100644 --- a/ports/unix/modtermios.c +++ b/ports/unix/modtermios.c @@ -58,7 +58,7 @@ STATIC mp_obj_t mod_termios_tcgetattr(mp_obj_t fd_in) { // but no way unicode chars could be there, if c_cc is defined to be a // a "char". But it's type is actually cc_t, which can be anything. // TODO: For now, we still deal with it like that. - cc->items[i] = mp_obj_new_bytes((byte*)&term.c_cc[i], 1); + cc->items[i] = mp_obj_new_bytes((byte *)&term.c_cc[i], 1); } } return MP_OBJ_FROM_PTR(r); @@ -129,7 +129,7 @@ STATIC const mp_rom_map_elem_t mp_module_termios_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_tcsetattr), MP_ROM_PTR(&mod_termios_tcsetattr_obj) }, { MP_ROM_QSTR(MP_QSTR_setraw), MP_ROM_PTR(&mod_termios_setraw_obj) }, -#define C(name) { MP_ROM_QSTR(MP_QSTR_ ## name), MP_ROM_INT(name) } +#define C(name) { MP_ROM_QSTR(MP_QSTR_##name), MP_ROM_INT(name) } C(TCSANOW), C(B9600), @@ -146,5 +146,5 @@ STATIC MP_DEFINE_CONST_DICT(mp_module_termios_globals, mp_module_termios_globals const mp_obj_module_t mp_module_termios = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_termios_globals, + .globals = (mp_obj_dict_t *)&mp_module_termios_globals, }; diff --git a/ports/unix/modtime.c b/ports/unix/modtime.c index cc9b4a337..94ae8d2f1 100644 --- a/ports/unix/modtime.c +++ b/ports/unix/modtime.c @@ -60,38 +60,38 @@ static inline int msec_sleep_tv(struct timeval *tv) { #endif #if defined(MP_CLOCKS_PER_SEC) -#define CLOCK_DIV (mp_float_t) (MP_CLOCKS_PER_SEC / 1000.0F) +#define CLOCK_DIV (mp_float_t)(MP_CLOCKS_PER_SEC / 1000.0F) #else #error Unsupported clock() implementation #endif STATIC mp_obj_t mod_time_time(void) { -#if MICROPY_PY_BUILTINS_FLOAT + #if MICROPY_PY_BUILTINS_FLOAT struct timeval tv; gettimeofday(&tv, NULL); mp_float_t val = tv.tv_sec + (mp_float_t)tv.tv_usec / 1000000; return mp_obj_new_float(val); -#else + #else return mp_obj_new_int((mp_int_t)time(NULL)); -#endif + #endif } STATIC MP_DEFINE_CONST_FUN_OBJ_0(mod_time_time_obj, mod_time_time); // Note: this is deprecated since CPy3.3, but pystone still uses it. STATIC mp_obj_t mod_time_clock(void) { -#if MICROPY_PY_BUILTINS_FLOAT + #if MICROPY_PY_BUILTINS_FLOAT // float cannot represent full range of int32 precisely, so we pre-divide // int to reduce resolution, and then actually do float division hoping // to preserve integer part resolution. return mp_obj_new_float((mp_float_t)(clock() / 1000) / CLOCK_DIV); -#else + #else return mp_obj_new_int((mp_int_t)clock()); -#endif + #endif } STATIC MP_DEFINE_CONST_FUN_OBJ_0(mod_time_clock_obj, mod_time_clock); STATIC mp_obj_t mod_time_sleep(mp_obj_t arg) { -#if MICROPY_PY_BUILTINS_FLOAT + #if MICROPY_PY_BUILTINS_FLOAT struct timeval tv; mp_float_t val = mp_obj_get_float(arg); double ipart; @@ -109,18 +109,18 @@ STATIC mp_obj_t mod_time_sleep(mp_obj_t arg) { break; } mp_handle_pending(); - //printf("select: EINTR: %ld:%ld\n", tv.tv_sec, tv.tv_usec); + // printf("select: EINTR: %ld:%ld\n", tv.tv_sec, tv.tv_usec); #else break; #endif } RAISE_ERRNO(res, errno); -#else + #else // TODO: Handle EINTR MP_THREAD_GIL_EXIT(); sleep(mp_obj_get_int(arg)); MP_THREAD_GIL_ENTER(); -#endif + #endif return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_1(mod_time_sleep_obj, mod_time_sleep); @@ -179,7 +179,7 @@ STATIC MP_DEFINE_CONST_DICT(mp_module_time_globals, mp_module_time_globals_table const mp_obj_module_t mp_module_time = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_time_globals, + .globals = (mp_obj_dict_t *)&mp_module_time_globals, }; #endif // MICROPY_PY_UTIME diff --git a/ports/unix/moduos_vfs.c b/ports/unix/moduos_vfs.c index b45d4485b..bb2f370d9 100644 --- a/ports/unix/moduos_vfs.c +++ b/ports/unix/moduos_vfs.c @@ -77,7 +77,7 @@ STATIC MP_DEFINE_CONST_DICT(uos_vfs_module_globals, uos_vfs_module_globals_table const mp_obj_module_t mp_module_uos_vfs = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&uos_vfs_module_globals, + .globals = (mp_obj_dict_t *)&uos_vfs_module_globals, }; #endif // MICROPY_VFS diff --git a/ports/unix/moduselect.c b/ports/unix/moduselect.c index dbda5e110..4d0fa37c1 100644 --- a/ports/unix/moduselect.c +++ b/ports/unix/moduselect.c @@ -315,7 +315,7 @@ STATIC const mp_obj_type_t mp_type_poll = { .name = MP_QSTR_poll, .getiter = mp_identity_getiter, .iternext = poll_iternext, - .locals_dict = (void*)&poll_locals_dict, + .locals_dict = (void *)&poll_locals_dict, }; STATIC mp_obj_t select_poll(size_t n_args, const mp_obj_t *args) { @@ -348,7 +348,7 @@ STATIC MP_DEFINE_CONST_DICT(mp_module_select_globals, mp_module_select_globals_t const mp_obj_module_t mp_module_uselect = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_select_globals, + .globals = (mp_obj_dict_t *)&mp_module_select_globals, }; #endif // MICROPY_PY_USELECT_POSIX diff --git a/ports/unix/modusocket.c b/ports/unix/modusocket.c index 90651a19e..89480c0cc 100644 --- a/ports/unix/modusocket.c +++ b/ports/unix/modusocket.c @@ -168,10 +168,10 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_listen_obj, socket_listen); STATIC mp_obj_t socket_accept(mp_obj_t self_in) { mp_obj_socket_t *self = MP_OBJ_TO_PTR(self_in); // sockaddr_storage isn't stack-friendly (129 bytes or so) - //struct sockaddr_storage addr; + // struct sockaddr_storage addr; byte addr[32]; socklen_t addr_len = sizeof(addr); - int fd = accept(self->fd, (struct sockaddr*)&addr, &addr_len); + int fd = accept(self->fd, (struct sockaddr *)&addr, &addr_len); RAISE_ERRNO(fd, errno); mp_obj_tuple_t *t = MP_OBJ_TO_PTR(mp_obj_new_tuple(2, NULL)); @@ -217,7 +217,7 @@ STATIC mp_obj_t socket_recvfrom(size_t n_args, const mp_obj_t *args) { socklen_t addr_len = sizeof(addr); byte *buf = m_new(byte, sz); - int out_sz = recvfrom(self->fd, buf, sz, flags, (struct sockaddr*)&addr, &addr_len); + int out_sz = recvfrom(self->fd, buf, sz, flags, (struct sockaddr *)&addr, &addr_len); RAISE_ERRNO(out_sz, errno); mp_obj_t buf_o = mp_obj_new_str_of_type(&mp_type_bytes, buf, out_sz); @@ -225,7 +225,7 @@ STATIC mp_obj_t socket_recvfrom(size_t n_args, const mp_obj_t *args) { mp_obj_tuple_t *t = MP_OBJ_TO_PTR(mp_obj_new_tuple(2, NULL)); t->items[0] = buf_o; - t->items[1] = mp_obj_from_sockaddr((struct sockaddr*)&addr, addr_len); + t->items[1] = mp_obj_from_sockaddr((struct sockaddr *)&addr, addr_len); return MP_OBJ_FROM_PTR(t); } @@ -265,7 +265,7 @@ STATIC mp_obj_t socket_sendto(size_t n_args, const mp_obj_t *args) { mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_READ); mp_get_buffer_raise(dst_addr, &addr_bi, MP_BUFFER_READ); int out_sz = sendto(self->fd, bufinfo.buf, bufinfo.len, flags, - (struct sockaddr *)addr_bi.buf, addr_bi.len); + (struct sockaddr *)addr_bi.buf, addr_bi.len); RAISE_ERRNO(out_sz, errno); return MP_OBJ_NEW_SMALL_INT(out_sz); @@ -321,7 +321,7 @@ STATIC mp_obj_t socket_makefile(size_t n_args, const mp_obj_t *args) { mp_obj_t *new_args = alloca(n_args * sizeof(mp_obj_t)); memcpy(new_args + 1, args + 1, (n_args - 1) * sizeof(mp_obj_t)); new_args[0] = MP_OBJ_NEW_SMALL_INT(self->fd); - return mp_builtin_open(n_args, new_args, (mp_map_t*)&mp_const_empty_map); + return mp_builtin_open(n_args, new_args, (mp_map_t *)&mp_const_empty_map); } STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(socket_makefile_obj, 1, 3, socket_makefile); @@ -388,7 +388,7 @@ const mp_obj_type_t mp_type_socket = { .getiter = NULL, .iternext = NULL, .protocol = &usocket_stream_p, - .locals_dict = (mp_obj_dict_t*)&usocket_locals_dict, + .locals_dict = (mp_obj_dict_t *)&usocket_locals_dict, }; #define BINADDR_MAX_LEN sizeof(struct in6_addr) @@ -442,10 +442,10 @@ STATIC mp_obj_t mod_socket_getaddrinfo(size_t n_args, const mp_obj_t *args) { snprintf(buf, sizeof(buf), "%u", port); serv = buf; hints.ai_flags = AI_NUMERICSERV; -#ifdef __UCLIBC_MAJOR__ -#if __UCLIBC_MAJOR__ == 0 && (__UCLIBC_MINOR__ < 9 || (__UCLIBC_MINOR__ == 9 && __UCLIBC_SUBLEVEL__ <= 32)) + #ifdef __UCLIBC_MAJOR__ + #if __UCLIBC_MAJOR__ == 0 && (__UCLIBC_MINOR__ < 9 || (__UCLIBC_MINOR__ == 9 && __UCLIBC_SUBLEVEL__ <= 32)) // "warning" requires -Wno-cpp which is a relatively new gcc option, so we choose not to use it. -//#warning Working around uClibc bug with numeric service name +// #warning Working around uClibc bug with numeric service name // Older versions og uClibc have bugs when numeric ports in service // arg require also hints.ai_socktype (or hints.ai_protocol) != 0 // This actually was fixed in 0.9.32.1, but uClibc doesn't allow to @@ -454,8 +454,8 @@ STATIC mp_obj_t mod_socket_getaddrinfo(size_t n_args, const mp_obj_t *args) { // Note that this is crude workaround, precluding UDP socket addresses // to be returned. TODO: set only if not set by Python args. hints.ai_socktype = SOCK_STREAM; -#endif -#endif + #endif + #endif } else { serv = mp_obj_str_get_str(args[1]); } @@ -500,30 +500,30 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mod_socket_getaddrinfo_obj, 2, 4, mod STATIC mp_obj_t mod_socket_sockaddr(mp_obj_t sockaddr_in) { mp_buffer_info_t bufinfo; mp_get_buffer_raise(sockaddr_in, &bufinfo, MP_BUFFER_READ); - switch (((struct sockaddr*)bufinfo.buf)->sa_family) { + switch (((struct sockaddr *)bufinfo.buf)->sa_family) { case AF_INET: { - struct sockaddr_in *sa = (struct sockaddr_in*)bufinfo.buf; + struct sockaddr_in *sa = (struct sockaddr_in *)bufinfo.buf; mp_obj_tuple_t *t = MP_OBJ_TO_PTR(mp_obj_new_tuple(3, NULL)); t->items[0] = MP_OBJ_NEW_SMALL_INT(AF_INET); - t->items[1] = mp_obj_new_bytes((byte*)&sa->sin_addr, sizeof(sa->sin_addr)); + t->items[1] = mp_obj_new_bytes((byte *)&sa->sin_addr, sizeof(sa->sin_addr)); t->items[2] = MP_OBJ_NEW_SMALL_INT(ntohs(sa->sin_port)); return MP_OBJ_FROM_PTR(t); } case AF_INET6: { - struct sockaddr_in6 *sa = (struct sockaddr_in6*)bufinfo.buf; + struct sockaddr_in6 *sa = (struct sockaddr_in6 *)bufinfo.buf; mp_obj_tuple_t *t = MP_OBJ_TO_PTR(mp_obj_new_tuple(5, NULL)); t->items[0] = MP_OBJ_NEW_SMALL_INT(AF_INET6); - t->items[1] = mp_obj_new_bytes((byte*)&sa->sin6_addr, sizeof(sa->sin6_addr)); + t->items[1] = mp_obj_new_bytes((byte *)&sa->sin6_addr, sizeof(sa->sin6_addr)); t->items[2] = MP_OBJ_NEW_SMALL_INT(ntohs(sa->sin6_port)); t->items[3] = MP_OBJ_NEW_SMALL_INT(ntohl(sa->sin6_flowinfo)); t->items[4] = MP_OBJ_NEW_SMALL_INT(ntohl(sa->sin6_scope_id)); return MP_OBJ_FROM_PTR(t); } default: { - struct sockaddr *sa = (struct sockaddr*)bufinfo.buf; + struct sockaddr *sa = (struct sockaddr *)bufinfo.buf; mp_obj_tuple_t *t = MP_OBJ_TO_PTR(mp_obj_new_tuple(2, NULL)); t->items[0] = MP_OBJ_NEW_SMALL_INT(sa->sa_family); - t->items[1] = mp_obj_new_bytes((byte*)sa->sa_data, bufinfo.len - offsetof(struct sockaddr, sa_data)); + t->items[1] = mp_obj_new_bytes((byte *)sa->sa_data, bufinfo.len - offsetof(struct sockaddr, sa_data)); return MP_OBJ_FROM_PTR(t); } } @@ -539,7 +539,7 @@ STATIC const mp_rom_map_elem_t mp_module_socket_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_inet_ntop), MP_ROM_PTR(&mod_socket_inet_ntop_obj) }, { MP_ROM_QSTR(MP_QSTR_sockaddr), MP_ROM_PTR(&mod_socket_sockaddr_obj) }, -#define C(name) { MP_ROM_QSTR(MP_QSTR_ ## name), MP_ROM_INT(name) } +#define C(name) { MP_ROM_QSTR(MP_QSTR_##name), MP_ROM_INT(name) } C(AF_UNIX), C(AF_INET), C(AF_INET6), @@ -563,5 +563,5 @@ STATIC MP_DEFINE_CONST_DICT(mp_module_socket_globals, mp_module_socket_globals_t const mp_obj_module_t mp_module_socket = { .base = { &mp_type_module }, - .globals = (mp_obj_dict_t*)&mp_module_socket_globals, + .globals = (mp_obj_dict_t *)&mp_module_socket_globals, }; diff --git a/ports/unix/mpconfigport.h b/ports/unix/mpconfigport.h index d6bbad9ce..464c4ce11 100644 --- a/ports/unix/mpconfigport.h +++ b/ports/unix/mpconfigport.h @@ -36,7 +36,7 @@ #endif #if !defined(MICROPY_EMIT_THUMB) && defined(__thumb2__) #define MICROPY_EMIT_THUMB (1) - #define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1)) + #define MICROPY_MAKE_POINTER_CALLABLE(p) ((void *)((mp_uint_t)(p) | 1)) #endif // Some compilers define __thumb2__ and __arm__ at the same time, let // autodetected thumb2 emitter have priority. @@ -250,7 +250,7 @@ typedef long long mp_off_t; typedef long mp_off_t; #endif -void mp_unix_alloc_exec(size_t min_size, void** ptr, size_t *size); +void mp_unix_alloc_exec(size_t min_size, void **ptr, size_t *size); void mp_unix_free_exec(void *ptr, size_t size); void mp_unix_mark_exec(void); #define MP_PLAT_ALLOC_EXEC(min_size, ptr, size) mp_unix_alloc_exec(min_size, ptr, size) diff --git a/ports/unix/mphalport.h b/ports/unix/mphalport.h index 4e459ffca..d852b78c0 100644 --- a/ports/unix/mphalport.h +++ b/ports/unix/mphalport.h @@ -51,10 +51,14 @@ static inline int mp_hal_readline(vstr_t *vstr, const char *p) { // TODO: POSIX et al. define usleep() as guaranteedly capable only of 1s sleep: // "The useconds argument shall be less than one million." -static inline void mp_hal_delay_ms(mp_uint_t ms) { usleep((ms) * 1000); } -static inline void mp_hal_delay_us(mp_uint_t us) { usleep(us); } +static inline void mp_hal_delay_ms(mp_uint_t ms) { + usleep((ms) * 1000); +} +static inline void mp_hal_delay_us(mp_uint_t us) { + usleep(us); +} #define mp_hal_ticks_cpu() 0 #define RAISE_ERRNO(err_flag, error_val) \ { if (err_flag == -1) \ - { mp_raise_OSError(error_val); } } + { mp_raise_OSError(error_val); } } diff --git a/ports/unix/mpthreadport.c b/ports/unix/mpthreadport.c index 3641745bc..864cf795e 100644 --- a/ports/unix/mpthreadport.c +++ b/ports/unix/mpthreadport.c @@ -65,10 +65,10 @@ STATIC void mp_thread_gc(int signo, siginfo_t *info, void *context) { // We have access to the context (regs, stack) of the thread but it seems // that we don't need the extra information, enough is captured by the // gc_collect_regs_and_stack function above - //gc_collect_root((void**)context, sizeof(ucontext_t) / sizeof(uintptr_t)); + // gc_collect_root((void**)context, sizeof(ucontext_t) / sizeof(uintptr_t)); #if MICROPY_ENABLE_PYSTACK - void **ptrs = (void**)(void*)MP_STATE_THREAD(pystack_start); - gc_collect_root(ptrs, (MP_STATE_THREAD(pystack_cur) - MP_STATE_THREAD(pystack_start)) / sizeof(void*)); + void **ptrs = (void **)(void *)MP_STATE_THREAD(pystack_start); + gc_collect_root(ptrs, (MP_STATE_THREAD(pystack_cur) - MP_STATE_THREAD(pystack_start)) / sizeof(void *)); #endif thread_signal_done = 1; } @@ -119,7 +119,7 @@ void mp_thread_gc_others(void) { } mp_state_thread_t *mp_thread_get_state(void) { - return (mp_state_thread_t*)pthread_getspecific(tls_key); + return (mp_state_thread_t *)pthread_getspecific(tls_key); } void mp_thread_set_state(void *state) { @@ -137,7 +137,7 @@ void mp_thread_start(void) { pthread_mutex_unlock(&thread_mutex); } -void mp_thread_create(void *(*entry)(void*), void *arg, size_t *stack_size) { +void mp_thread_create(void *(*entry)(void *), void *arg, size_t *stack_size) { // default stack size is 8k machine-words if (*stack_size == 0) { *stack_size = 8192 * BYTES_PER_WORD; diff --git a/ports/unix/unix_mphal.c b/ports/unix/unix_mphal.c index 77deb3152..ab9c08f51 100644 --- a/ports/unix/unix_mphal.c +++ b/ports/unix/unix_mphal.c @@ -130,7 +130,7 @@ static int call_dupterm_read(size_t idx) { return -1; } nlr_pop(); - return *(byte*)bufinfo.buf; + return *(byte *)bufinfo.buf; } else { // Temporarily disable dupterm to avoid infinite recursion mp_obj_t save_term = MP_STATE_VM(dupterm_objs[idx]); @@ -146,12 +146,12 @@ static int call_dupterm_read(size_t idx) { int mp_hal_stdin_rx_chr(void) { unsigned char c; -#if MICROPY_PY_OS_DUPTERM + #if MICROPY_PY_OS_DUPTERM // TODO only support dupterm one slot at the moment if (MP_STATE_VM(dupterm_objs[0]) != MP_OBJ_NULL) { int c; do { - c = call_dupterm_read(0); + c = call_dupterm_read(0); } while (c == -2); if (c == -1) { goto main_term; @@ -161,18 +161,18 @@ int mp_hal_stdin_rx_chr(void) { } return c; } else { - main_term:; -#endif - int ret = read(0, &c, 1); - if (ret == 0) { - c = 4; // EOF, ctrl-D - } else if (c == '\n') { - c = '\r'; - } - return c; -#if MICROPY_PY_OS_DUPTERM + main_term:; + #endif + int ret = read(0, &c, 1); + if (ret == 0) { + c = 4; // EOF, ctrl-D + } else if (c == '\n') { + c = '\r'; } -#endif + return c; + #if MICROPY_PY_OS_DUPTERM +} + #endif } void mp_hal_stdout_tx_strn(const char *str, size_t len) { |