diff options
Diffstat (limited to 'ports')
42 files changed, 13255 insertions, 152 deletions
diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile index 8eb24e836..5f901a199 100644 --- a/ports/atmel-samd/Makefile +++ b/ports/atmel-samd/Makefile @@ -86,17 +86,27 @@ INC += -I. \ # NDEBUG disables assert() statements. This reduces code size pretty dramatically, per tannewt. ifeq ($(CHIP_FAMILY), samd21) +PERIPHERALS_CHIP_FAMILY=samd21 CFLAGS += -Os -DNDEBUG # TinyUSB defines CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD21 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=128 -DCFG_TUD_MSC_BUFSIZE=512 endif ifeq ($(CHIP_FAMILY), samd51) +PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x CFLAGS += -Os -DNDEBUG # TinyUSB defines CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD51 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024 endif +ifeq ($(CHIP_FAMILY), same54) +PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x +CFLAGS += -Os -DNDEBUG +# TinyUSB defines +CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD51 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024 +endif + +$(echo PERIPHERALS_CHIP_FAMILY=$(PERIPHERALS_CHIP_FAMILY)) #Debugging/Optimization ifeq ($(DEBUG), 1) CFLAGS += -ggdb @@ -152,7 +162,16 @@ CFLAGS += \ -mcpu=cortex-m4 \ -mfloat-abi=hard \ -mfpu=fpv4-sp-d16 \ - -DSAMD51 + -DSAM_D5X_E5X -DSAMD51 +endif +ifeq ($(CHIP_FAMILY), same54) +CFLAGS += \ + -mthumb \ + -mabi=aapcs-linux \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -DSAM_D5X_E5X -DSAME54 endif @@ -171,6 +190,9 @@ BOOTLOADER_SIZE := 0x2000 else ifeq ($(CHIP_FAMILY), samd51) LDFLAGS += -mthumb -mcpu=cortex-m4 BOOTLOADER_SIZE := 0x4000 +else ifeq ($(CHIP_FAMILY), same54) +LDFLAGS += -mthumb -mcpu=cortex-m4 +BOOTLOADER_SIZE := 0x4000 endif SRC_ASF := \ @@ -213,6 +235,15 @@ SRC_ASF += \ hpl/oscctrl/hpl_oscctrl.c \ hpl/trng/hpl_trng.c \ +else ifeq ($(CHIP_FAMILY), same54) +SRC_ASF += \ + hal/src/hal_rand_sync.c \ + hpl/core/hpl_core_m4.c \ + hpl/mclk/hpl_mclk.c \ + hpl/osc32kctrl/hpl_osc32kctrl.c \ + hpl/oscctrl/hpl_oscctrl.c \ + hpl/trng/hpl_trng.c \ + endif SRC_ASF := $(addprefix asf4/$(CHIP_FAMILY)/, $(SRC_ASF)) @@ -240,15 +271,15 @@ SRC_C = \ lib/utils/stdout_helpers.c \ lib/utils/sys_stdio_mphal.c \ mphalport.c \ - peripherals/samd/$(CHIP_FAMILY)/adc.c \ - peripherals/samd/$(CHIP_FAMILY)/cache.c \ - peripherals/samd/$(CHIP_FAMILY)/clocks.c \ - peripherals/samd/$(CHIP_FAMILY)/dma.c \ - peripherals/samd/$(CHIP_FAMILY)/events.c \ - peripherals/samd/$(CHIP_FAMILY)/external_interrupts.c \ - peripherals/samd/$(CHIP_FAMILY)/pins.c \ - peripherals/samd/$(CHIP_FAMILY)/sercom.c \ - peripherals/samd/$(CHIP_FAMILY)/timers.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/adc.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/cache.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/dma.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/events.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/external_interrupts.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/pins.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/sercom.c \ + peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/timers.c \ peripherals/samd/clocks.c \ peripherals/samd/dma.c \ peripherals/samd/events.c \ @@ -288,7 +319,7 @@ endif # The smallest SAMD51 packages don't have I2S. Everything else does. ifeq ($(CIRCUITPY_AUDIOBUSIO),1) -SRC_C += peripherals/samd/i2s.c peripherals/samd/$(CHIP_FAMILY)/i2s.c +SRC_C += peripherals/samd/i2s.c peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/i2s.c endif SRC_COMMON_HAL_EXPANDED = $(addprefix shared-bindings/, $(SRC_COMMON_HAL)) \ @@ -317,7 +348,7 @@ OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o)) SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED) # Sources that only hold QSTRs after pre-processing. -SRC_QSTR_PREPROCESSOR += peripherals/samd/$(CHIP_FAMILY)/clocks.c +SRC_QSTR_PREPROCESSOR += peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c all: $(BUILD)/firmware.bin $(BUILD)/firmware.uf2 diff --git a/ports/atmel-samd/asf4 b/ports/atmel-samd/asf4 -Subproject 039b5f3bbc3f4ba4421e581db290560d59fef62 +Subproject c0eef7b75124fc946af5f75e12d82d6d01315ab diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_adc_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_adc_config.h new file mode 100644 index 000000000..13d815102 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_adc_config.h @@ -0,0 +1,303 @@ +/* Auto-generated config file hpl_adc_config.h */ +#ifndef HPL_ADC_CONFIG_H +#define HPL_ADC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_ADC_0_ENABLE +#define CONF_ADC_0_ENABLE 1 +#endif + +// <h> Basic Configuration + +// <o> Conversion Result Resolution +// <0x0=>12-bit +// <0x1=>16-bit (averaging must be enabled) +// <0x2=>10-bit +// <0x3=>8-bit +// <i> Defines the bit resolution for the ADC sample values (RESSEL) +// <id> adc_resolution +#ifndef CONF_ADC_0_RESSEL +#define CONF_ADC_0_RESSEL 0x0 +#endif + +// <o> Reference Selection +// <0x0=>Internal bandgap reference +// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V) +// <0x3=>VDDANA +// <0x4=>External reference A +// <0x5=>External reference B +// <0x6=>External reference C +// <i> Select the reference for the ADC (REFSEL) +// <id> adc_reference +#ifndef CONF_ADC_0_REFSEL +#define CONF_ADC_0_REFSEL 0x0 +#endif + +// <o> Prescaler configuration +// <0x0=>Peripheral clock divided by 2 +// <0x1=>Peripheral clock divided by 4 +// <0x2=>Peripheral clock divided by 8 +// <0x3=>Peripheral clock divided by 16 +// <0x4=>Peripheral clock divided by 32 +// <0x5=>Peripheral clock divided by 64 +// <0x6=>Peripheral clock divided by 128 +// <0x7=>Peripheral clock divided by 256 +// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER) +// <id> adc_prescaler +#ifndef CONF_ADC_0_PRESCALER +#define CONF_ADC_0_PRESCALER 0x3 +#endif + +// <q> Free Running Mode +// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN) +// <id> adc_freerunning_mode +#ifndef CONF_ADC_0_FREERUN +#define CONF_ADC_0_FREERUN 0 +#endif + +// <q> Differential Mode +// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE) +// <id> adc_differential_mode +#ifndef CONF_ADC_0_DIFFMODE +#define CONF_ADC_0_DIFFMODE 0 +#endif + +// <o> Positive Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x08=>ADC AIN8 pin +// <0x09=>ADC AIN9 pin +// <0x0A=>ADC AIN10 pin +// <0x0B=>ADC AIN11 pin +// <0x0C=>ADC AIN12 pin +// <0x0D=>ADC AIN13 pin +// <0x0E=>ADC AIN14 pin +// <0x0F=>ADC AIN15 pin +// <0x18=>1/4 scaled core supply +// <0x19=>1/4 Scaled VBAT Supply +// <0x1A=>1/4 scaled I/O supply +// <0x1B=>Bandgap voltage +// <0x1C=>Temperature reference (PTAT) +// <0x1D=>Temperature reference (CTAT) +// <0x1E=>DAC Output +// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS) +// <id> adc_pinmux_positive +#ifndef CONF_ADC_0_MUXPOS +#define CONF_ADC_0_MUXPOS 0x0 +#endif + +// <o> Negative Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x18=>Internal ground +// <0x19=>I/O ground +// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG) +// <id> adc_pinmux_negative +#ifndef CONF_ADC_0_MUXNEG +#define CONF_ADC_0_MUXNEG 0x0 +#endif + +// </h> + +// <e> Advanced Configuration +// <id> adc_advanced_settings +#ifndef CONF_ADC_0_ADVANCED +#define CONF_ADC_0_ADVANCED 0 +#endif + +// <q> Run in standby +// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY) +// <id> adc_arch_runstdby +#ifndef CONF_ADC_0_RUNSTDBY +#define CONF_ADC_0_RUNSTDBY 0 +#endif + +// <q>Debug Run +// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN) +// <id> adc_arch_dbgrun +#ifndef CONF_ADC_0_DBGRUN +#define CONF_ADC_0_DBGRUN 0 +#endif + +// <q> On Demand Control +// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND) +// <id> adc_arch_ondemand +#ifndef CONF_ADC_0_ONDEMAND +#define CONF_ADC_0_ONDEMAND 0 +#endif + +// <q> Left-Adjusted Result +// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ) +// <id> adc_arch_leftadj +#ifndef CONF_ADC_0_LEFTADJ +#define CONF_ADC_0_LEFTADJ 0 +#endif + +// <q> Reference Buffer Offset Compensation Enable +// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP) +// <id> adc_arch_refcomp +#ifndef CONF_ADC_0_REFCOMP +#define CONF_ADC_0_REFCOMP 0 +#endif + +// <q>Comparator Offset Compensation Enable +// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP) +// <id> adc_arch_offcomp +#ifndef CONF_ADC_0_OFFCOMP +#define CONF_ADC_0_OFFCOMP 0 +#endif + +// <q> Digital Correction Logic Enabled +// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN) +// <id> adc_arch_corren +#ifndef CONF_ADC_0_CORREN +#define CONF_ADC_0_CORREN 0 +#endif + +// <o> Offset Correction Value <0-4095> +// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR) +// <id> adc_arch_offsetcorr +#ifndef CONF_ADC_0_OFFSETCORR +#define CONF_ADC_0_OFFSETCORR 0 +#endif + +// <o> Gain Correction Value <0-4095> +// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR) +// <id> adc_arch_gaincorr +#ifndef CONF_ADC_0_GAINCORR +#define CONF_ADC_0_GAINCORR 0 +#endif + +// <o> Adjusting Result / Division Coefficient <0-7> +// <i> These bits define the division coefficient in 2n steps. (ADJRES) +// <id> adc_arch_adjres +#ifndef CONF_ADC_0_ADJRES +#define CONF_ADC_0_ADJRES 0x0 +#endif + +// <o.0..10> Number of Samples to be Collected +// <0x0=>1 sample +// <0x1=>2 samples +// <0x2=>4 samples +// <0x3=>8 samples +// <0x4=>16 samples +// <0x5=>32 samples +// <0x6=>64 samples +// <0x7=>128 samples +// <0x8=>256 samples +// <0x9=>512 samples +// <0xA=>1024 samples +// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM) +// <id> adc_arch_samplenum +#ifndef CONF_ADC_0_SAMPLENUM +#define CONF_ADC_0_SAMPLENUM 0x0 +#endif + +// <o> Sampling Time Length <0-63> +// <i> These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) +// <id> adc_arch_samplen +#ifndef CONF_ADC_0_SAMPLEN +#define CONF_ADC_0_SAMPLEN 0 +#endif + +// <o> Window Monitor Mode +// <0x0=>No window mode +// <0x1=>Mode 1: RESULT above lower threshold +// <0x2=>Mode 2: RESULT beneath upper threshold +// <0x3=>Mode 3: RESULT inside lower and upper threshold +// <0x4=>Mode 4: RESULT outside lower and upper threshold +// <i> These bits enable and define the window monitor mode. (WINMODE) +// <id> adc_arch_winmode +#ifndef CONF_ADC_0_WINMODE +#define CONF_ADC_0_WINMODE 0x0 +#endif + +// <o> Window Monitor Lower Threshold <0-65535> +// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT) +// <id> adc_arch_winlt +#ifndef CONF_ADC_0_WINLT +#define CONF_ADC_0_WINLT 0 +#endif + +// <o> Window Monitor Upper Threshold <0-65535> +// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT) +// <id> adc_arch_winut +#ifndef CONF_ADC_0_WINUT +#define CONF_ADC_0_WINUT 0 +#endif + +// <o> Bitmask for positive input sequence <0-4294967295> +// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device). +// <id> adc_arch_seqen +#ifndef CONF_ADC_0_SEQEN +#define CONF_ADC_0_SEQEN 0x0 +#endif + +// </e> + +// <e> Event Control +// <id> adc_arch_event_settings +#ifndef CONF_ADC_0_EVENT_CONTROL +#define CONF_ADC_0_EVENT_CONTROL 0 +#endif + +// <q> Window Monitor Event Out +// <i> Enables event output on window event (WINMONEO) +// <id> adc_arch_winmoneo +#ifndef CONF_ADC_0_WINMONEO +#define CONF_ADC_0_WINMONEO 0 +#endif + +// <q> Result Ready Event Out +// <i> Enables event output on result ready event (RESRDEO) +// <id> adc_arch_resrdyeo +#ifndef CONF_ADC_0_RESRDYEO +#define CONF_ADC_0_RESRDYEO 0 +#endif + +// <q> Invert flush Event Signal +// <i> Invert the flush event input signal (FLUSHINV) +// <id> adc_arch_flushinv +#ifndef CONF_ADC_0_FLUSHINV +#define CONF_ADC_0_FLUSHINV 0 +#endif + +// <q> Trigger Flush On Event +// <i> Trigger an ADC pipeline flush on event (FLUSHEI) +// <id> adc_arch_flushei +#ifndef CONF_ADC_0_FLUSHEI +#define CONF_ADC_0_FLUSHEI 0 +#endif + +// <q> Invert Start Conversion Event Signal +// <i> Invert the start conversion event input signal (STARTINV) +// <id> adc_arch_startinv +#ifndef CONF_ADC_0_STARTINV +#define CONF_ADC_0_STARTINV 0 +#endif + +// <q> Trigger Conversion On Event +// <i> Trigger a conversion on event. (STARTEI) +// <id> adc_arch_startei +#ifndef CONF_ADC_0_STARTEI +#define CONF_ADC_0_STARTEI 0 +#endif + +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_ADC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_dac_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_dac_config.h new file mode 100644 index 000000000..c46f99b7d --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_dac_config.h @@ -0,0 +1,169 @@ +/* Auto-generated config file hpl_dac_config.h */ +#ifndef HPL_DAC_CONFIG_H +#define HPL_DAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Basic configuration +// <o> Reference Selection +// <0x00=> Unbuffered external voltage reference +// <0x01=> Voltage supply +// <0x02=> Buffered external voltage reference +// <0x03=> Internal bandgap reference +// <id> dac_arch_refsel +#ifndef CONF_DAC_REFSEL +#define CONF_DAC_REFSEL 0 +#endif + +// <q> Differential mode +// <i> Indicates whether the differential mode is enabled or not +// <id> dac_arch_diff +#ifndef CONF_DAC_DIFF +#define CONF_DAC_DIFF 0 +#endif +// </h> + +// <e> Advanced Configuration +// <id> dac_advanced_settings +#ifndef CONF_DAC_ADVANCED_CONFIG +#define CONF_DAC_ADVANCED_CONFIG 0 +#endif + +// <q> Debug Run +// <i> Indicate whether running when CPU is halted +// <id> adc_arch_dbgrun +#ifndef CONF_DAC_DBGRUN +#define CONF_DAC_DBGRUN 1 +#endif + +// <h> Channel 0 configuration +// <q> Left Adjusted Data +// <i> Indicate how the data is adjusted in the Data and Data Buffer register +// <id> dac0_arch_leftadj +#ifndef CONF_DAC0_LEFTADJ +#define CONF_DAC0_LEFTADJ 1 +#endif + +// <o> Current control +// <0=> GCLK_DAC <= 1.2MHz (100kSPS) +// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) +// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) +// <i> This defines the current in output buffer according to conversion rate +// <id> dac0_arch_cctrl +#ifndef CONF_DAC0_CCTRL +#define CONF_DAC0_CCTRL 0 +#endif + +// <q> Run in standby +// <i> Indicates whether the DAC channel will continue running in standby sleep mode or not +// <id> dac0_arch_runstdby +#ifndef CONF_DAC0_RUNSTDBY +#define CONF_DAC0_RUNSTDBY 0 +#endif + +// <q> Dithering Mode +// <i> Indicate whether dithering mode is enabled +// <id> dac0_arch_ditrher +#ifndef CONF_DAC0_DITHER +#define CONF_DAC0_DITHER 0 +#endif + +// <o> Refresh period <0x00-0xFF> +// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us +// <id> dac0_arch_refresh +#ifndef CONF_DAC0_REFRESH +#define CONF_DAC0_REFRESH 2 +#endif +// </h> +// <h> Channel 1 configuration +// <q> Left Adjusted Data +// <i> Indicate how the data is adjusted in the Data and Data Buffer register +// <id> dac1_arch_leftadj +#ifndef CONF_DAC1_LEFTADJ +#define CONF_DAC1_LEFTADJ 1 +#endif + +// <o> Current control +// <0=> GCLK_DAC <= 1.2MHz (100kSPS) +// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) +// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) +// <i> This defines the current in output buffer according to conversion rate +// <id> dac1_arch_cctrl +#ifndef CONF_DAC1_CCTRL +#define CONF_DAC1_CCTRL 0 +#endif + +// <q> Run in standby +// <i> Indicates whether the DAC channel will continue running in standby sleep mode or not +// <id> dac1_arch_runstdby +#ifndef CONF_DAC1_RUNSTDBY +#define CONF_DAC1_RUNSTDBY 0 +#endif + +// <q> Dithering Mode +// <i> Indicate whether dithering mode is enabled +// <id> dac1_arch_ditrher +#ifndef CONF_DAC1_DITHER +#define CONF_DAC1_DITHER 0 +#endif + +// <o> Refresh period <0x00-0xFF> +// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us +// <id> dac1_arch_refresh +#ifndef CONF_DAC1_REFRESH +#define CONF_DAC1_REFRESH 2 +#endif +// </h> + +// <h> Event configuration +// <o> Inversion of DAC 0 event +// <0=> Detection on rising edge pf the input event +// <1=> Detection on falling edge pf the input event +// <i> This defines the edge detection of the input event +// <id> dac_arch_invei0 +#ifndef CONF_DAC_INVEI0 +#define CONF_DAC_INVEI0 0 +#endif + +// <q> Data Buffer of DAC 0 Empty Event Output +// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// <id> dac_arch_emptyeo_0 +#ifndef CONF_DAC_EMPTYEO0 +#define CONF_DAC_EMPTYEO0 0 +#endif + +// <q> Start Conversion Event Input DAC 0 +// <i> Indicate whether Start input event is enabled +// <id> dac_arch_startei_0 +#ifndef CONF_DAC_STARTEI0 +#define CONF_DAC_STARTEI0 0 +#endif +// <o> Inversion of DAC 1 event +// <0=> Detection on rising edge pf the input event +// <1=> Detection on falling edge pf the input event +// <i> This defines the edge detection of the input event +// <id> dac_arch_invei1 +#ifndef CONF_DAC_INVEI1 +#define CONF_DAC_INVEI1 0 +#endif + +// <q> Data Buffer of DAC 1 Empty Event Output +// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// <id> dac_arch_emptyeo_1 +#ifndef CONF_DAC_EMPTYEO1 +#define CONF_DAC_EMPTYEO1 0 +#endif + +// <q> Start Conversion Event Input DAC 1 +// <i> Indicate whether Start input event is enabled +// <id> dac_arch_startei_1 +#ifndef CONF_DAC_STARTEI1 +#define CONF_DAC_STARTEI1 0 +#endif + +// </h> +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_DAC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_dmac_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_dmac_config.h new file mode 100644 index 000000000..90499fc27 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_dmac_config.h @@ -0,0 +1,7277 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <e> DMAC enable +// <i> Indicates whether dmac is enabled or not +// <id> dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// <q> Priority Level 0 +// <i> Indicates whether Priority Level 0 is enabled or not +// <id> dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// <o> Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// <i> Defines Level 0 Arbitration for DMA channels +// <id> dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// <o> Level 0 Channel Priority Number <0x00-0xFF> +// <id> dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif +// <q> Priority Level 1 +// <i> Indicates whether Priority Level 1 is enabled or not +// <id> dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// <o> Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// <i> Defines Level 1 Arbitration for DMA channels +// <id> dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// <o> Level 1 Channel Priority Number <0x00-0xFF> +// <id> dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif +// <q> Priority Level 2 +// <i> Indicates whether Priority Level 2 is enabled or not +// <id> dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 1 +#endif + +// <o> Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// <i> Defines Level 2 Arbitration for DMA channels +// <id> dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// <o> Level 2 Channel Priority Number <0x00-0xFF> +// <id> dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif +// <q> Priority Level 3 +// <i> Indicates whether Priority Level 3 is enabled or not +// <id> dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 1 +#endif + +// <o> Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// <i> Defines Level 3 Arbitration for DMA channels +// <id> dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// <o> Level 3 Channel Priority Number <0x00-0xFF> +// <id> dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif +// <q> Debug Run +// <i> Indicates whether Debug Run is enabled or not +// <id> dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// <e> Channel 0 settings +// <id> dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 0 is running in standby mode or not +// <id> dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// </e> + +// <e> Channel 1 settings +// <id> dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 1 is running in standby mode or not +// <id> dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// </e> + +// <e> Channel 2 settings +// <id> dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 2 is running in standby mode or not +// <id> dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// </e> + +// <e> Channel 3 settings +// <id> dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 3 is running in standby mode or not +// <id> dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// </e> + +// <e> Channel 4 settings +// <id> dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 4 is running in standby mode or not +// <id> dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// </e> + +// <e> Channel 5 settings +// <id> dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 5 is running in standby mode or not +// <id> dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// </e> + +// <e> Channel 6 settings +// <id> dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 6 is running in standby mode or not +// <id> dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// </e> + +// <e> Channel 7 settings +// <id> dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 7 is running in standby mode or not +// <id> dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// </e> + +// <e> Channel 8 settings +// <id> dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 8 is running in standby mode or not +// <id> dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// </e> + +// <e> Channel 9 settings +// <id> dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 9 is running in standby mode or not +// <id> dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// </e> + +// <e> Channel 10 settings +// <id> dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 10 is running in standby mode or not +// <id> dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// </e> + +// <e> Channel 11 settings +// <id> dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 11 is running in standby mode or not +// <id> dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// </e> + +// <e> Channel 12 settings +// <id> dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 12 is running in standby mode or not +// <id> dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// </e> + +// <e> Channel 13 settings +// <id> dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 13 is running in standby mode or not +// <id> dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// </e> + +// <e> Channel 14 settings +// <id> dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 14 is running in standby mode or not +// <id> dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// </e> + +// <e> Channel 15 settings +// <id> dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 15 is running in standby mode or not +// <id> dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// </e> + +// <e> Channel 16 settings +// <id> dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 16 is running in standby mode or not +// <id> dmac_runstdby_16 +#ifndef CONF_DMAC_RUNSTDBY_16 +#define CONF_DMAC_RUNSTDBY_16 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_16 +#ifndef CONF_DMAC_TRIGACT_16 +#define CONF_DMAC_TRIGACT_16 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_16 +#ifndef CONF_DMAC_LVL_16 +#define CONF_DMAC_LVL_16 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_16 +#ifndef CONF_DMAC_EVOE_16 +#define CONF_DMAC_EVOE_16 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_16 +#ifndef CONF_DMAC_EVIE_16 +#define CONF_DMAC_EVIE_16 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_16 +#ifndef CONF_DMAC_EVACT_16 +#define CONF_DMAC_EVACT_16 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_16 +#ifndef CONF_DMAC_STEPSIZE_16 +#define CONF_DMAC_STEPSIZE_16 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_16 +#ifndef CONF_DMAC_STEPSEL_16 +#define CONF_DMAC_STEPSEL_16 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_16 +#ifndef CONF_DMAC_BLOCKACT_16 +#define CONF_DMAC_BLOCKACT_16 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_16 +#ifndef CONF_DMAC_EVOSEL_16 +#define CONF_DMAC_EVOSEL_16 0 +#endif +// </e> + +// <e> Channel 17 settings +// <id> dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 17 is running in standby mode or not +// <id> dmac_runstdby_17 +#ifndef CONF_DMAC_RUNSTDBY_17 +#define CONF_DMAC_RUNSTDBY_17 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_17 +#ifndef CONF_DMAC_TRIGACT_17 +#define CONF_DMAC_TRIGACT_17 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_17 +#ifndef CONF_DMAC_LVL_17 +#define CONF_DMAC_LVL_17 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_17 +#ifndef CONF_DMAC_EVOE_17 +#define CONF_DMAC_EVOE_17 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_17 +#ifndef CONF_DMAC_EVIE_17 +#define CONF_DMAC_EVIE_17 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_17 +#ifndef CONF_DMAC_EVACT_17 +#define CONF_DMAC_EVACT_17 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_17 +#ifndef CONF_DMAC_STEPSIZE_17 +#define CONF_DMAC_STEPSIZE_17 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_17 +#ifndef CONF_DMAC_STEPSEL_17 +#define CONF_DMAC_STEPSEL_17 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_17 +#ifndef CONF_DMAC_BLOCKACT_17 +#define CONF_DMAC_BLOCKACT_17 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_17 +#ifndef CONF_DMAC_EVOSEL_17 +#define CONF_DMAC_EVOSEL_17 0 +#endif +// </e> + +// <e> Channel 18 settings +// <id> dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 18 is running in standby mode or not +// <id> dmac_runstdby_18 +#ifndef CONF_DMAC_RUNSTDBY_18 +#define CONF_DMAC_RUNSTDBY_18 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_18 +#ifndef CONF_DMAC_TRIGACT_18 +#define CONF_DMAC_TRIGACT_18 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_18 +#ifndef CONF_DMAC_LVL_18 +#define CONF_DMAC_LVL_18 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_18 +#ifndef CONF_DMAC_EVOE_18 +#define CONF_DMAC_EVOE_18 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_18 +#ifndef CONF_DMAC_EVIE_18 +#define CONF_DMAC_EVIE_18 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_18 +#ifndef CONF_DMAC_EVACT_18 +#define CONF_DMAC_EVACT_18 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_18 +#ifndef CONF_DMAC_STEPSIZE_18 +#define CONF_DMAC_STEPSIZE_18 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_18 +#ifndef CONF_DMAC_STEPSEL_18 +#define CONF_DMAC_STEPSEL_18 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_18 +#ifndef CONF_DMAC_BLOCKACT_18 +#define CONF_DMAC_BLOCKACT_18 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_18 +#ifndef CONF_DMAC_EVOSEL_18 +#define CONF_DMAC_EVOSEL_18 0 +#endif +// </e> + +// <e> Channel 19 settings +// <id> dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 19 is running in standby mode or not +// <id> dmac_runstdby_19 +#ifndef CONF_DMAC_RUNSTDBY_19 +#define CONF_DMAC_RUNSTDBY_19 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_19 +#ifndef CONF_DMAC_TRIGACT_19 +#define CONF_DMAC_TRIGACT_19 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_19 +#ifndef CONF_DMAC_LVL_19 +#define CONF_DMAC_LVL_19 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_19 +#ifndef CONF_DMAC_EVOE_19 +#define CONF_DMAC_EVOE_19 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_19 +#ifndef CONF_DMAC_EVIE_19 +#define CONF_DMAC_EVIE_19 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_19 +#ifndef CONF_DMAC_EVACT_19 +#define CONF_DMAC_EVACT_19 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_19 +#ifndef CONF_DMAC_STEPSIZE_19 +#define CONF_DMAC_STEPSIZE_19 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_19 +#ifndef CONF_DMAC_STEPSEL_19 +#define CONF_DMAC_STEPSEL_19 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_19 +#ifndef CONF_DMAC_BLOCKACT_19 +#define CONF_DMAC_BLOCKACT_19 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_19 +#ifndef CONF_DMAC_EVOSEL_19 +#define CONF_DMAC_EVOSEL_19 0 +#endif +// </e> + +// <e> Channel 20 settings +// <id> dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 20 is running in standby mode or not +// <id> dmac_runstdby_20 +#ifndef CONF_DMAC_RUNSTDBY_20 +#define CONF_DMAC_RUNSTDBY_20 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_20 +#ifndef CONF_DMAC_TRIGACT_20 +#define CONF_DMAC_TRIGACT_20 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_20 +#ifndef CONF_DMAC_LVL_20 +#define CONF_DMAC_LVL_20 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_20 +#ifndef CONF_DMAC_EVOE_20 +#define CONF_DMAC_EVOE_20 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_20 +#ifndef CONF_DMAC_EVIE_20 +#define CONF_DMAC_EVIE_20 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_20 +#ifndef CONF_DMAC_EVACT_20 +#define CONF_DMAC_EVACT_20 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_20 +#ifndef CONF_DMAC_STEPSIZE_20 +#define CONF_DMAC_STEPSIZE_20 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_20 +#ifndef CONF_DMAC_STEPSEL_20 +#define CONF_DMAC_STEPSEL_20 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_20 +#ifndef CONF_DMAC_BLOCKACT_20 +#define CONF_DMAC_BLOCKACT_20 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_20 +#ifndef CONF_DMAC_EVOSEL_20 +#define CONF_DMAC_EVOSEL_20 0 +#endif +// </e> + +// <e> Channel 21 settings +// <id> dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 21 is running in standby mode or not +// <id> dmac_runstdby_21 +#ifndef CONF_DMAC_RUNSTDBY_21 +#define CONF_DMAC_RUNSTDBY_21 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_21 +#ifndef CONF_DMAC_TRIGACT_21 +#define CONF_DMAC_TRIGACT_21 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_21 +#ifndef CONF_DMAC_LVL_21 +#define CONF_DMAC_LVL_21 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_21 +#ifndef CONF_DMAC_EVOE_21 +#define CONF_DMAC_EVOE_21 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_21 +#ifndef CONF_DMAC_EVIE_21 +#define CONF_DMAC_EVIE_21 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_21 +#ifndef CONF_DMAC_EVACT_21 +#define CONF_DMAC_EVACT_21 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_21 +#ifndef CONF_DMAC_STEPSIZE_21 +#define CONF_DMAC_STEPSIZE_21 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_21 +#ifndef CONF_DMAC_STEPSEL_21 +#define CONF_DMAC_STEPSEL_21 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_21 +#ifndef CONF_DMAC_BLOCKACT_21 +#define CONF_DMAC_BLOCKACT_21 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_21 +#ifndef CONF_DMAC_EVOSEL_21 +#define CONF_DMAC_EVOSEL_21 0 +#endif +// </e> + +// <e> Channel 22 settings +// <id> dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 22 is running in standby mode or not +// <id> dmac_runstdby_22 +#ifndef CONF_DMAC_RUNSTDBY_22 +#define CONF_DMAC_RUNSTDBY_22 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_22 +#ifndef CONF_DMAC_TRIGACT_22 +#define CONF_DMAC_TRIGACT_22 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_22 +#ifndef CONF_DMAC_LVL_22 +#define CONF_DMAC_LVL_22 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_22 +#ifndef CONF_DMAC_EVOE_22 +#define CONF_DMAC_EVOE_22 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_22 +#ifndef CONF_DMAC_EVIE_22 +#define CONF_DMAC_EVIE_22 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_22 +#ifndef CONF_DMAC_EVACT_22 +#define CONF_DMAC_EVACT_22 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_22 +#ifndef CONF_DMAC_STEPSIZE_22 +#define CONF_DMAC_STEPSIZE_22 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_22 +#ifndef CONF_DMAC_STEPSEL_22 +#define CONF_DMAC_STEPSEL_22 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_22 +#ifndef CONF_DMAC_BLOCKACT_22 +#define CONF_DMAC_BLOCKACT_22 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_22 +#ifndef CONF_DMAC_EVOSEL_22 +#define CONF_DMAC_EVOSEL_22 0 +#endif +// </e> + +// <e> Channel 23 settings +// <id> dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 23 is running in standby mode or not +// <id> dmac_runstdby_23 +#ifndef CONF_DMAC_RUNSTDBY_23 +#define CONF_DMAC_RUNSTDBY_23 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_23 +#ifndef CONF_DMAC_TRIGACT_23 +#define CONF_DMAC_TRIGACT_23 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_23 +#ifndef CONF_DMAC_LVL_23 +#define CONF_DMAC_LVL_23 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_23 +#ifndef CONF_DMAC_EVOE_23 +#define CONF_DMAC_EVOE_23 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_23 +#ifndef CONF_DMAC_EVIE_23 +#define CONF_DMAC_EVIE_23 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_23 +#ifndef CONF_DMAC_EVACT_23 +#define CONF_DMAC_EVACT_23 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_23 +#ifndef CONF_DMAC_STEPSIZE_23 +#define CONF_DMAC_STEPSIZE_23 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_23 +#ifndef CONF_DMAC_STEPSEL_23 +#define CONF_DMAC_STEPSEL_23 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_23 +#ifndef CONF_DMAC_BLOCKACT_23 +#define CONF_DMAC_BLOCKACT_23 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_23 +#ifndef CONF_DMAC_EVOSEL_23 +#define CONF_DMAC_EVOSEL_23 0 +#endif +// </e> + +// <e> Channel 24 settings +// <id> dmac_channel_24_settings +#ifndef CONF_DMAC_CHANNEL_24_SETTINGS +#define CONF_DMAC_CHANNEL_24_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 24 is running in standby mode or not +// <id> dmac_runstdby_24 +#ifndef CONF_DMAC_RUNSTDBY_24 +#define CONF_DMAC_RUNSTDBY_24 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_24 +#ifndef CONF_DMAC_TRIGACT_24 +#define CONF_DMAC_TRIGACT_24 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_24 +#ifndef CONF_DMAC_TRIGSRC_24 +#define CONF_DMAC_TRIGSRC_24 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_24 +#ifndef CONF_DMAC_LVL_24 +#define CONF_DMAC_LVL_24 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_24 +#ifndef CONF_DMAC_EVOE_24 +#define CONF_DMAC_EVOE_24 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_24 +#ifndef CONF_DMAC_EVIE_24 +#define CONF_DMAC_EVIE_24 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_24 +#ifndef CONF_DMAC_EVACT_24 +#define CONF_DMAC_EVACT_24 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_24 +#ifndef CONF_DMAC_STEPSIZE_24 +#define CONF_DMAC_STEPSIZE_24 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_24 +#ifndef CONF_DMAC_STEPSEL_24 +#define CONF_DMAC_STEPSEL_24 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_24 +#ifndef CONF_DMAC_SRCINC_24 +#define CONF_DMAC_SRCINC_24 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_24 +#ifndef CONF_DMAC_DSTINC_24 +#define CONF_DMAC_DSTINC_24 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_24 +#ifndef CONF_DMAC_BEATSIZE_24 +#define CONF_DMAC_BEATSIZE_24 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_24 +#ifndef CONF_DMAC_BLOCKACT_24 +#define CONF_DMAC_BLOCKACT_24 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_24 +#ifndef CONF_DMAC_EVOSEL_24 +#define CONF_DMAC_EVOSEL_24 0 +#endif +// </e> + +// <e> Channel 25 settings +// <id> dmac_channel_25_settings +#ifndef CONF_DMAC_CHANNEL_25_SETTINGS +#define CONF_DMAC_CHANNEL_25_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 25 is running in standby mode or not +// <id> dmac_runstdby_25 +#ifndef CONF_DMAC_RUNSTDBY_25 +#define CONF_DMAC_RUNSTDBY_25 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_25 +#ifndef CONF_DMAC_TRIGACT_25 +#define CONF_DMAC_TRIGACT_25 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_25 +#ifndef CONF_DMAC_TRIGSRC_25 +#define CONF_DMAC_TRIGSRC_25 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_25 +#ifndef CONF_DMAC_LVL_25 +#define CONF_DMAC_LVL_25 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_25 +#ifndef CONF_DMAC_EVOE_25 +#define CONF_DMAC_EVOE_25 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_25 +#ifndef CONF_DMAC_EVIE_25 +#define CONF_DMAC_EVIE_25 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_25 +#ifndef CONF_DMAC_EVACT_25 +#define CONF_DMAC_EVACT_25 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_25 +#ifndef CONF_DMAC_STEPSIZE_25 +#define CONF_DMAC_STEPSIZE_25 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_25 +#ifndef CONF_DMAC_STEPSEL_25 +#define CONF_DMAC_STEPSEL_25 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_25 +#ifndef CONF_DMAC_SRCINC_25 +#define CONF_DMAC_SRCINC_25 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_25 +#ifndef CONF_DMAC_DSTINC_25 +#define CONF_DMAC_DSTINC_25 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_25 +#ifndef CONF_DMAC_BEATSIZE_25 +#define CONF_DMAC_BEATSIZE_25 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_25 +#ifndef CONF_DMAC_BLOCKACT_25 +#define CONF_DMAC_BLOCKACT_25 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_25 +#ifndef CONF_DMAC_EVOSEL_25 +#define CONF_DMAC_EVOSEL_25 0 +#endif +// </e> + +// <e> Channel 26 settings +// <id> dmac_channel_26_settings +#ifndef CONF_DMAC_CHANNEL_26_SETTINGS +#define CONF_DMAC_CHANNEL_26_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 26 is running in standby mode or not +// <id> dmac_runstdby_26 +#ifndef CONF_DMAC_RUNSTDBY_26 +#define CONF_DMAC_RUNSTDBY_26 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_26 +#ifndef CONF_DMAC_TRIGACT_26 +#define CONF_DMAC_TRIGACT_26 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_26 +#ifndef CONF_DMAC_TRIGSRC_26 +#define CONF_DMAC_TRIGSRC_26 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_26 +#ifndef CONF_DMAC_LVL_26 +#define CONF_DMAC_LVL_26 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_26 +#ifndef CONF_DMAC_EVOE_26 +#define CONF_DMAC_EVOE_26 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_26 +#ifndef CONF_DMAC_EVIE_26 +#define CONF_DMAC_EVIE_26 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_26 +#ifndef CONF_DMAC_EVACT_26 +#define CONF_DMAC_EVACT_26 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_26 +#ifndef CONF_DMAC_STEPSIZE_26 +#define CONF_DMAC_STEPSIZE_26 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_26 +#ifndef CONF_DMAC_STEPSEL_26 +#define CONF_DMAC_STEPSEL_26 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_26 +#ifndef CONF_DMAC_SRCINC_26 +#define CONF_DMAC_SRCINC_26 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_26 +#ifndef CONF_DMAC_DSTINC_26 +#define CONF_DMAC_DSTINC_26 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_26 +#ifndef CONF_DMAC_BEATSIZE_26 +#define CONF_DMAC_BEATSIZE_26 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_26 +#ifndef CONF_DMAC_BLOCKACT_26 +#define CONF_DMAC_BLOCKACT_26 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_26 +#ifndef CONF_DMAC_EVOSEL_26 +#define CONF_DMAC_EVOSEL_26 0 +#endif +// </e> + +// <e> Channel 27 settings +// <id> dmac_channel_27_settings +#ifndef CONF_DMAC_CHANNEL_27_SETTINGS +#define CONF_DMAC_CHANNEL_27_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 27 is running in standby mode or not +// <id> dmac_runstdby_27 +#ifndef CONF_DMAC_RUNSTDBY_27 +#define CONF_DMAC_RUNSTDBY_27 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_27 +#ifndef CONF_DMAC_TRIGACT_27 +#define CONF_DMAC_TRIGACT_27 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_27 +#ifndef CONF_DMAC_TRIGSRC_27 +#define CONF_DMAC_TRIGSRC_27 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_27 +#ifndef CONF_DMAC_LVL_27 +#define CONF_DMAC_LVL_27 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_27 +#ifndef CONF_DMAC_EVOE_27 +#define CONF_DMAC_EVOE_27 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_27 +#ifndef CONF_DMAC_EVIE_27 +#define CONF_DMAC_EVIE_27 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_27 +#ifndef CONF_DMAC_EVACT_27 +#define CONF_DMAC_EVACT_27 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_27 +#ifndef CONF_DMAC_STEPSIZE_27 +#define CONF_DMAC_STEPSIZE_27 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_27 +#ifndef CONF_DMAC_STEPSEL_27 +#define CONF_DMAC_STEPSEL_27 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_27 +#ifndef CONF_DMAC_SRCINC_27 +#define CONF_DMAC_SRCINC_27 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_27 +#ifndef CONF_DMAC_DSTINC_27 +#define CONF_DMAC_DSTINC_27 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_27 +#ifndef CONF_DMAC_BEATSIZE_27 +#define CONF_DMAC_BEATSIZE_27 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_27 +#ifndef CONF_DMAC_BLOCKACT_27 +#define CONF_DMAC_BLOCKACT_27 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_27 +#ifndef CONF_DMAC_EVOSEL_27 +#define CONF_DMAC_EVOSEL_27 0 +#endif +// </e> + +// <e> Channel 28 settings +// <id> dmac_channel_28_settings +#ifndef CONF_DMAC_CHANNEL_28_SETTINGS +#define CONF_DMAC_CHANNEL_28_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 28 is running in standby mode or not +// <id> dmac_runstdby_28 +#ifndef CONF_DMAC_RUNSTDBY_28 +#define CONF_DMAC_RUNSTDBY_28 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_28 +#ifndef CONF_DMAC_TRIGACT_28 +#define CONF_DMAC_TRIGACT_28 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_28 +#ifndef CONF_DMAC_TRIGSRC_28 +#define CONF_DMAC_TRIGSRC_28 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_28 +#ifndef CONF_DMAC_LVL_28 +#define CONF_DMAC_LVL_28 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_28 +#ifndef CONF_DMAC_EVOE_28 +#define CONF_DMAC_EVOE_28 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_28 +#ifndef CONF_DMAC_EVIE_28 +#define CONF_DMAC_EVIE_28 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_28 +#ifndef CONF_DMAC_EVACT_28 +#define CONF_DMAC_EVACT_28 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_28 +#ifndef CONF_DMAC_STEPSIZE_28 +#define CONF_DMAC_STEPSIZE_28 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_28 +#ifndef CONF_DMAC_STEPSEL_28 +#define CONF_DMAC_STEPSEL_28 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_28 +#ifndef CONF_DMAC_SRCINC_28 +#define CONF_DMAC_SRCINC_28 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_28 +#ifndef CONF_DMAC_DSTINC_28 +#define CONF_DMAC_DSTINC_28 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_28 +#ifndef CONF_DMAC_BEATSIZE_28 +#define CONF_DMAC_BEATSIZE_28 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_28 +#ifndef CONF_DMAC_BLOCKACT_28 +#define CONF_DMAC_BLOCKACT_28 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_28 +#ifndef CONF_DMAC_EVOSEL_28 +#define CONF_DMAC_EVOSEL_28 0 +#endif +// </e> + +// <e> Channel 29 settings +// <id> dmac_channel_29_settings +#ifndef CONF_DMAC_CHANNEL_29_SETTINGS +#define CONF_DMAC_CHANNEL_29_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 29 is running in standby mode or not +// <id> dmac_runstdby_29 +#ifndef CONF_DMAC_RUNSTDBY_29 +#define CONF_DMAC_RUNSTDBY_29 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_29 +#ifndef CONF_DMAC_TRIGACT_29 +#define CONF_DMAC_TRIGACT_29 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_29 +#ifndef CONF_DMAC_TRIGSRC_29 +#define CONF_DMAC_TRIGSRC_29 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_29 +#ifndef CONF_DMAC_LVL_29 +#define CONF_DMAC_LVL_29 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_29 +#ifndef CONF_DMAC_EVOE_29 +#define CONF_DMAC_EVOE_29 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_29 +#ifndef CONF_DMAC_EVIE_29 +#define CONF_DMAC_EVIE_29 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_29 +#ifndef CONF_DMAC_EVACT_29 +#define CONF_DMAC_EVACT_29 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_29 +#ifndef CONF_DMAC_STEPSIZE_29 +#define CONF_DMAC_STEPSIZE_29 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_29 +#ifndef CONF_DMAC_STEPSEL_29 +#define CONF_DMAC_STEPSEL_29 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_29 +#ifndef CONF_DMAC_SRCINC_29 +#define CONF_DMAC_SRCINC_29 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_29 +#ifndef CONF_DMAC_DSTINC_29 +#define CONF_DMAC_DSTINC_29 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_29 +#ifndef CONF_DMAC_BEATSIZE_29 +#define CONF_DMAC_BEATSIZE_29 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_29 +#ifndef CONF_DMAC_BLOCKACT_29 +#define CONF_DMAC_BLOCKACT_29 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_29 +#ifndef CONF_DMAC_EVOSEL_29 +#define CONF_DMAC_EVOSEL_29 0 +#endif +// </e> + +// <e> Channel 30 settings +// <id> dmac_channel_30_settings +#ifndef CONF_DMAC_CHANNEL_30_SETTINGS +#define CONF_DMAC_CHANNEL_30_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 30 is running in standby mode or not +// <id> dmac_runstdby_30 +#ifndef CONF_DMAC_RUNSTDBY_30 +#define CONF_DMAC_RUNSTDBY_30 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_30 +#ifndef CONF_DMAC_TRIGACT_30 +#define CONF_DMAC_TRIGACT_30 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_30 +#ifndef CONF_DMAC_TRIGSRC_30 +#define CONF_DMAC_TRIGSRC_30 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_30 +#ifndef CONF_DMAC_LVL_30 +#define CONF_DMAC_LVL_30 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_30 +#ifndef CONF_DMAC_EVOE_30 +#define CONF_DMAC_EVOE_30 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_30 +#ifndef CONF_DMAC_EVIE_30 +#define CONF_DMAC_EVIE_30 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_30 +#ifndef CONF_DMAC_EVACT_30 +#define CONF_DMAC_EVACT_30 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_30 +#ifndef CONF_DMAC_STEPSIZE_30 +#define CONF_DMAC_STEPSIZE_30 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_30 +#ifndef CONF_DMAC_STEPSEL_30 +#define CONF_DMAC_STEPSEL_30 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_30 +#ifndef CONF_DMAC_SRCINC_30 +#define CONF_DMAC_SRCINC_30 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_30 +#ifndef CONF_DMAC_DSTINC_30 +#define CONF_DMAC_DSTINC_30 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_30 +#ifndef CONF_DMAC_BEATSIZE_30 +#define CONF_DMAC_BEATSIZE_30 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_30 +#ifndef CONF_DMAC_BLOCKACT_30 +#define CONF_DMAC_BLOCKACT_30 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_30 +#ifndef CONF_DMAC_EVOSEL_30 +#define CONF_DMAC_EVOSEL_30 0 +#endif +// </e> + +// <e> Channel 31 settings +// <id> dmac_channel_31_settings +#ifndef CONF_DMAC_CHANNEL_31_SETTINGS +#define CONF_DMAC_CHANNEL_31_SETTINGS 0 +#endif + +// <q> Channel Run in Standby +// <i> Indicates whether channel 31 is running in standby mode or not +// <id> dmac_runstdby_31 +#ifndef CONF_DMAC_RUNSTDBY_31 +#define CONF_DMAC_RUNSTDBY_31 0 +#endif + +// <o> Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// <i> Defines the trigger action used for a transfer +// <id> dmac_trigact_31 +#ifndef CONF_DMAC_TRIGACT_31 +#define CONF_DMAC_TRIGACT_31 0 +#endif + +// <o> Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// <i> Defines the peripheral trigger which is source of the transfer +// <id> dmac_trifsrc_31 +#ifndef CONF_DMAC_TRIGSRC_31 +#define CONF_DMAC_TRIGSRC_31 0 +#endif + +// <o> Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// <i> Defines the arbitration level for this channel +// <id> dmac_lvl_31 +#ifndef CONF_DMAC_LVL_31 +#define CONF_DMAC_LVL_31 0 +#endif + +// <q> Channel Event Output +// <i> Indicates whether channel event generation is enabled or not +// <id> dmac_evoe_31 +#ifndef CONF_DMAC_EVOE_31 +#define CONF_DMAC_EVOE_31 0 +#endif + +// <q> Channel Event Input +// <i> Indicates whether channel event reception is enabled or not +// <id> dmac_evie_31 +#ifndef CONF_DMAC_EVIE_31 +#define CONF_DMAC_EVIE_31 0 +#endif + +// <o> Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// <i> Defines the event input action +// <id> dmac_evact_31 +#ifndef CONF_DMAC_EVACT_31 +#define CONF_DMAC_EVACT_31 0 +#endif + +// <o> Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// <i> Defines the address increment step size, applies to source or destination address +// <id> dmac_stepsize_31 +#ifndef CONF_DMAC_STEPSIZE_31 +#define CONF_DMAC_STEPSIZE_31 0 +#endif + +// <o> Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// <i> Defines whether source or destination addresses are using the step size settings +// <id> dmac_stepsel_31 +#ifndef CONF_DMAC_STEPSEL_31 +#define CONF_DMAC_STEPSEL_31 0 +#endif + +// <q> Source Address Increment +// <i> Indicates whether the source address incrementation is enabled or not +// <id> dmac_srcinc_31 +#ifndef CONF_DMAC_SRCINC_31 +#define CONF_DMAC_SRCINC_31 0 +#endif + +// <q> Destination Address Increment +// <i> Indicates whether the destination address incrementation is enabled or not +// <id> dmac_dstinc_31 +#ifndef CONF_DMAC_DSTINC_31 +#define CONF_DMAC_DSTINC_31 0 +#endif + +// <o> Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// <i> Defines the size of one beat +// <id> dmac_beatsize_31 +#ifndef CONF_DMAC_BEATSIZE_31 +#define CONF_DMAC_BEATSIZE_31 0 +#endif + +// <o> Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// <i> Defines the the DMAC should take after a block transfer has completed +// <id> dmac_blockact_31 +#ifndef CONF_DMAC_BLOCKACT_31 +#define CONF_DMAC_BLOCKACT_31 0 +#endif + +// <o> Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// <i> Defines the event output selection +// <id> dmac_evosel_31 +#ifndef CONF_DMAC_EVOSEL_31 +#define CONF_DMAC_EVOSEL_31 0 +#endif +// </e> + +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h new file mode 100644 index 000000000..6f4f01a7e --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h @@ -0,0 +1,924 @@ +// Circuit Python SAMD51 clock tree: +// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5, GCLK6 +// GCLK1 (48MHz) -> 48 MHz peripherals +// GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0 +// DPLL0 (multiplied up to 120 MHz) -> GCLK0, GCLK4 (output for monitoring) +// GCLK6 (48 MHz divided down to 12 MHz) -> DAC + +// We'd like to use XOSC32K as a ref for DFLL48M on boards with a 32kHz crystal, +// but haven't figured that out yet. + +// Used in hpl/core/hpl_init.c to define which clocks should be initialized first. +// Not clear why all these need to be specified, but it doesn't work properly otherwise. + +//#define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5) +#define CIRCUITPY_GCLK_INIT_1ST 0xffff + +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <e> Generic clock generator 0 configuration +// <i> Indicates whether generic clock 0 configuration is enabled or not +// <id> enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 0 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 0 +// <id> gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 1 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 0 division <0x0000-0xFFFF> +// <id> gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// </h> +// </e> + +// <e> Generic clock generator 1 configuration +// <i> Indicates whether generic clock 1 configuration is enabled or not +// <id> enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 1 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 1 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 1 +// <id> gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 1 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 1 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 1 division <0x0000-0xFFFF> +// <id> gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// </h> +// </e> + +// <e> Generic clock generator 2 configuration +// <i> Indicates whether generic clock 2 configuration is enabled or not +// <id> enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 1 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 2 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 2 +// <id> gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 1 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 1 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 2 division <0x0000-0xFFFF> +// <id> gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 4 +#endif +// </h> +// </e> + +// <e> Generic clock generator 3 configuration +// <i> Indicates whether generic clock 3 configuration is enabled or not +// <id> enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 3 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 3 +// <id> gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 3 division <0x0000-0xFFFF> +// <id> gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// </h> +// </e> + +// <e> Generic clock generator 4 configuration +// <i> Indicates whether generic clock 4 configuration is enabled or not +// <id> enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 1 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 4 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 4 +// <id> gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 1 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 1 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 4 division <0x0000-0xFFFF> +// <id> gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// </h> +// </e> + +// <e> Generic clock generator 5 configuration +// <i> Indicates whether generic clock 5 configuration is enabled or not +// <id> enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 1 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 5 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 5 +// <id> gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 1 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 1 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 5 division <0x0000-0xFFFF> +// <id> gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 24 +#endif +// </h> +// </e> + +// <e> Generic clock generator 6 configuration +// <i> Indicates whether generic clock 6 configuration is enabled or not +// <id> enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 1 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 6 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 6 +// <id> gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 1 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 1 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 6 division <0x0000-0xFFFF> +// <id> gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 4 +#endif +// </h> +// </e> + +// <e> Generic clock generator 7 configuration +// <i> Indicates whether generic clock 7 configuration is enabled or not +// <id> enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 7 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 7 +// <id> gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 7 division <0x0000-0xFFFF> +// <id> gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// </h> +// </e> + +// <e> Generic clock generator 8 configuration +// <i> Indicates whether generic clock 8 configuration is enabled or not +// <id> enable_gclk_gen_8 +#ifndef CONF_GCLK_GENERATOR_8_CONFIG +#define CONF_GCLK_GENERATOR_8_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 8 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 8 +// <id> gclk_gen_8_oscillator +#ifndef CONF_GCLK_GEN_8_SOURCE +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_8_runstdby +#ifndef CONF_GCLK_GEN_8_RUNSTDBY +#define CONF_GCLK_GEN_8_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_8_div_sel +#ifndef CONF_GCLK_GEN_8_DIVSEL +#define CONF_GCLK_GEN_8_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_8_oe +#ifndef CONF_GCLK_GEN_8_OE +#define CONF_GCLK_GEN_8_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_8_oov +#ifndef CONF_GCLK_GEN_8_OOV +#define CONF_GCLK_GEN_8_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_8_idc +#ifndef CONF_GCLK_GEN_8_IDC +#define CONF_GCLK_GEN_8_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_8_enable +#ifndef CONF_GCLK_GEN_8_GENEN +#define CONF_GCLK_GEN_8_GENEN 0 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 8 division <0x0000-0xFFFF> +// <id> gclk_gen_8_div +#ifndef CONF_GCLK_GEN_8_DIV +#define CONF_GCLK_GEN_8_DIV 1 +#endif +// </h> +// </e> + +// <e> Generic clock generator 9 configuration +// <i> Indicates whether generic clock 9 configuration is enabled or not +// <id> enable_gclk_gen_9 +#ifndef CONF_GCLK_GENERATOR_9_CONFIG +#define CONF_GCLK_GENERATOR_9_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 9 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 9 +// <id> gclk_gen_9_oscillator +#ifndef CONF_GCLK_GEN_9_SOURCE +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_9_runstdby +#ifndef CONF_GCLK_GEN_9_RUNSTDBY +#define CONF_GCLK_GEN_9_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_9_div_sel +#ifndef CONF_GCLK_GEN_9_DIVSEL +#define CONF_GCLK_GEN_9_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_9_oe +#ifndef CONF_GCLK_GEN_9_OE +#define CONF_GCLK_GEN_9_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_9_oov +#ifndef CONF_GCLK_GEN_9_OOV +#define CONF_GCLK_GEN_9_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_9_idc +#ifndef CONF_GCLK_GEN_9_IDC +#define CONF_GCLK_GEN_9_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_9_enable +#ifndef CONF_GCLK_GEN_9_GENEN +#define CONF_GCLK_GEN_9_GENEN 0 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 9 division <0x0000-0xFFFF> +// <id> gclk_gen_9_div +#ifndef CONF_GCLK_GEN_9_DIV +#define CONF_GCLK_GEN_9_DIV 1 +#endif +// </h> +// </e> + +// <e> Generic clock generator 10 configuration +// <i> Indicates whether generic clock 10 configuration is enabled or not +// <id> enable_gclk_gen_10 +#ifndef CONF_GCLK_GENERATOR_10_CONFIG +#define CONF_GCLK_GENERATOR_10_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 10 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 10 +// <id> gclk_gen_10_oscillator +#ifndef CONF_GCLK_GEN_10_SOURCE +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_10_runstdby +#ifndef CONF_GCLK_GEN_10_RUNSTDBY +#define CONF_GCLK_GEN_10_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_10_div_sel +#ifndef CONF_GCLK_GEN_10_DIVSEL +#define CONF_GCLK_GEN_10_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_10_oe +#ifndef CONF_GCLK_GEN_10_OE +#define CONF_GCLK_GEN_10_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_10_oov +#ifndef CONF_GCLK_GEN_10_OOV +#define CONF_GCLK_GEN_10_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_10_idc +#ifndef CONF_GCLK_GEN_10_IDC +#define CONF_GCLK_GEN_10_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_10_enable +#ifndef CONF_GCLK_GEN_10_GENEN +#define CONF_GCLK_GEN_10_GENEN 0 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 10 division <0x0000-0xFFFF> +// <id> gclk_gen_10_div +#ifndef CONF_GCLK_GEN_10_DIV +#define CONF_GCLK_GEN_10_DIV 1 +#endif +// </h> +// </e> + +// <e> Generic clock generator 11 configuration +// <i> Indicates whether generic clock 11 configuration is enabled or not +// <id> enable_gclk_gen_11 +#ifndef CONF_GCLK_GENERATOR_11_CONFIG +#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#endif + +// <h> Generic Clock Generator Control +// <y> Generic clock generator 11 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad +// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M) +// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0) +// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1) +// <i> This defines the clock source for generic clock generator 11 +// <id> gclk_gen_11_oscillator +#ifndef CONF_GCLK_GEN_11_SOURCE +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> gclk_arch_gen_11_runstdby +#ifndef CONF_GCLK_GEN_11_RUNSTDBY +#define CONF_GCLK_GEN_11_RUNSTDBY 0 +#endif + +// <q> Divide Selection +// <i> Indicates whether Divide Selection is enabled or not +//<id> gclk_gen_11_div_sel +#ifndef CONF_GCLK_GEN_11_DIVSEL +#define CONF_GCLK_GEN_11_DIVSEL 0 +#endif + +// <q> Output Enable +// <i> Indicates whether Output Enable is enabled or not +// <id> gclk_arch_gen_11_oe +#ifndef CONF_GCLK_GEN_11_OE +#define CONF_GCLK_GEN_11_OE 0 +#endif + +// <q> Output Off Value +// <i> Indicates whether Output Off Value is enabled or not +// <id> gclk_arch_gen_11_oov +#ifndef CONF_GCLK_GEN_11_OOV +#define CONF_GCLK_GEN_11_OOV 0 +#endif + +// <q> Improve Duty Cycle +// <i> Indicates whether Improve Duty Cycle is enabled or not +// <id> gclk_arch_gen_11_idc +#ifndef CONF_GCLK_GEN_11_IDC +#define CONF_GCLK_GEN_11_IDC 0 +#endif + +// <q> Generic Clock Generator Enable +// <i> Indicates whether Generic Clock Generator Enable is enabled or not +// <id> gclk_arch_gen_11_enable +#ifndef CONF_GCLK_GEN_11_GENEN +#define CONF_GCLK_GEN_11_GENEN 0 +#endif +// </h> + +//<h> Generic Clock Generator Division +//<o> Generic clock generator 11 division <0x0000-0xFFFF> +// <id> gclk_gen_11_div +#ifndef CONF_GCLK_GEN_11_DIV +#define CONF_GCLK_GEN_11_DIV 1 +#endif +// </h> +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_mclk_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_mclk_config.h new file mode 100644 index 000000000..a5a7de53c --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_mclk_config.h @@ -0,0 +1,104 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include <peripheral_clk_config.h> + +// <e> System Configuration +// <i> Indicates whether configuration for system is enabled or not +// <id> enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// <h> Basic settings +// <y> CPU Clock source +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 +// <i> This defines the clock source for the CPU +// <id> cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// <y> CPU Clock Division Factor +// <MCLK_CPUDIV_DIV_DIV1_Val"> 1 +// <MCLK_CPUDIV_DIV_DIV2_Val"> 2 +// <MCLK_CPUDIV_DIV_DIV4_Val"> 4 +// <MCLK_CPUDIV_DIV_DIV8_Val"> 8 +// <MCLK_CPUDIV_DIV_DIV16_Val"> 16 +// <MCLK_CPUDIV_DIV_DIV32_Val"> 32 +// <MCLK_CPUDIV_DIV_DIV64_Val"> 64 +// <MCLK_CPUDIV_DIV_DIV128_Val"> 128 +// <i> Prescalar for CPU clock +// <id> cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val +#endif +// <y> Low Power Clock Division +// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1 +// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2 +// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4 +// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8 +// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16 +// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32 +// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64 +// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128 +// <id> mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// <y> Backup Clock Division +// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1 +// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2 +// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4 +// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8 +// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16 +// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32 +// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64 +// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128 +// <id> mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// <y> High-Speed Clock Division +// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1 +// <id> mclk_arch_hsdiv +#ifndef CONF_MCLK_HSDIV +#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val +#endif +// </h> + +// <h> NVM Settings +// <o> NVM Wait States +// <i> These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// <id> nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// </h> + +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_nvmctrl_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_nvmctrl_config.h new file mode 100644 index 000000000..53fcb593a --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_nvmctrl_config.h @@ -0,0 +1,36 @@ +/* Auto-generated config file hpl_nvmctrl_config.h */ +#ifndef HPL_NVMCTRL_CONFIG_H +#define HPL_NVMCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Basic Settings + +// <o> Power Reduction Mode During Sleep +// <0x00=> Wake On Access +// <0x01=> Wake Up Instant +// <0x03=> Disabled +// <id> nvm_arch_sleepprm +#ifndef CONF_NVM_SLEEPPRM +#define CONF_NVM_SLEEPPRM 0 +#endif + +// <q> AHB0 Cache Disable +// <i> Indicate whether AHB0 cache is disable or not +// <id> nvm_arch_cache0 +#ifndef CONF_NVM_CACHE0 +#define CONF_NVM_CACHE0 1 +#endif + +// <q> AHB1 Cache Disable +// <i> Indicate whether AHB1 cache is disable or not +// <id> nvm_arch_cache1 +#ifndef CONF_NVM_CACHE1 +#define CONF_NVM_CACHE1 1 +#endif + +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_NVMCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_osc32kctrl_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_osc32kctrl_config.h new file mode 100644 index 000000000..d93cbf922 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_osc32kctrl_config.h @@ -0,0 +1,163 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <e> RTC Source configuration +// <id> enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// <h> RTC source control +// <y> RTC Clock Source Selection +// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <i> This defines the clock source for RTC +// <id> rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// <q> Use 1 kHz output +// <id> rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ +#define CONF_RTCCTRL_1KHZ 1 +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// </h> +// </e> + +// <e> 32kHz External Crystal Oscillator Configuration +// <i> Indicates whether configuration for External 32K Osc is enabled or not +// <id> enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 1 +#endif + +// <h> 32kHz External Crystal Oscillator Control +// <q> Oscillator enable +// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not +// <id> xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 1 +#endif + +// <o> Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// <id> xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// <q> On Demand Control +// <i> Indicates whether On Demand Control is enabled or not +// <id> xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// <q> 1kHz Output Enable +// <i> Indicates whether 1kHz Output is enabled or not +// <id> xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// <q> 32kHz Output Enable +// <i> Indicates whether 32kHz Output is enabled or not +// <id> xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// <q> Clock Switch Back +// <i> Indicates whether Clock Switch Back is enabled or not +// <id> xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// <q> Clock Failure Detector +// <i> Indicates whether Clock Failure Detector is enabled or not +// <id> xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// <q> Clock Failure Detector Event Out +// <i> Indicates whether Clock Failure Detector Event Out is enabled or not +// <id> xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// <q> Crystal connected to XIN32/XOUT32 Enable +// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// <id> xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 0 +#endif + +// <o> Control Gain Mode +// <0x0=>Low Power mode +// <0x1=>Standard mode +// <0x2=>High Speed mode +// <id> xosc32k_arch_cgm +#ifndef CONF_XOSC32K_CGM +#define CONF_XOSC32K_CGM 0x1 +#endif + +// </h> +// </e> + +// <e> 32kHz Ultra Low Power Internal Oscillator Configuration +// <i> Indicates whether configuration for OSCULP32K is enabled or not +// <id> enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// <h> 32kHz Ultra Low Power Internal Oscillator Control + +// <q> Oscillator Calibration Control +// <i> Indicates whether Oscillator Calibration is enabled or not +// <id> osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// <o> Oscillator Calibration <0x0-0x3F> +// <id> osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// </h> +// </e> + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_oscctrl_config.h new file mode 100644 index 000000000..cd1186605 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_oscctrl_config.h @@ -0,0 +1,634 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <e> External Multipurpose Crystal Oscillator Configuration +// <i> Indicates whether configuration for XOSC0 is enabled or not +// <id> enable_xosc0 +#ifndef CONF_XOSC0_CONFIG +#define CONF_XOSC0_CONFIG 0 +#endif + +// <o> Frequency <8000000-48000000> +// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// <id> xosc0_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC0_FREQUENCY 12000000 +#endif + +// <h> External Multipurpose Crystal Oscillator Control +// <q> Oscillator enable +// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// <id> xosc0_arch_enable +#ifndef CONF_XOSC0_ENABLE +#define CONF_XOSC0_ENABLE 0 +#endif + +// <o> Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// <id> xosc0_arch_startup +#ifndef CONF_XOSC0_STARTUP +#define CONF_XOSC0_STARTUP 0 +#endif + +// <q> Clock Switch Back +// <i> Indicates whether Clock Switch Back is enabled or not +// <id> xosc0_arch_swben +#ifndef CONF_XOSC0_SWBEN +#define CONF_XOSC0_SWBEN 0 +#endif + +// <q> Clock Failure Detector +// <i> Indicates whether Clock Failure Detector is enabled or not +// <id> xosc0_arch_cfden +#ifndef CONF_XOSC0_CFDEN +#define CONF_XOSC0_CFDEN 0 +#endif + +// <q> Automatic Loop Control Enable +// <i> Indicates whether Automatic Loop Control is enabled or not +// <id> xosc0_arch_enalc +#ifndef CONF_XOSC0_ENALC +#define CONF_XOSC0_ENALC 0 +#endif + +// <q> Low Buffer Gain Enable +// <i> Indicates whether Low Buffer Gain is enabled or not +// <id> xosc0_arch_lowbufgain +#ifndef CONF_XOSC0_LOWBUFGAIN +#define CONF_XOSC0_LOWBUFGAIN 0 +#endif + +// <q> On Demand Control +// <i> Indicates whether On Demand Control is enabled or not +// <id> xosc0_arch_ondemand +#ifndef CONF_XOSC0_ONDEMAND +#define CONF_XOSC0_ONDEMAND 0 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> xosc0_arch_runstdby +#ifndef CONF_XOSC0_RUNSTDBY +#define CONF_XOSC0_RUNSTDBY 0 +#endif + +// <q> Crystal connected to XIN/XOUT Enable +// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// <id> xosc0_arch_xtalen +#ifndef CONF_XOSC0_XTALEN +#define CONF_XOSC0_XTALEN 0 +#endif +//</h> +//</e> + +#if CONF_XOSC0_FREQUENCY >= 32000000 +#define CONF_XOSC0_CFDPRESC 0x0 +#define CONF_XOSC0_IMULT 0x7 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 24000000 +#define CONF_XOSC0_CFDPRESC 0x1 +#define CONF_XOSC0_IMULT 0x6 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 16000000 +#define CONF_XOSC0_CFDPRESC 0x2 +#define CONF_XOSC0_IMULT 0x5 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 8000000 +#define CONF_XOSC0_CFDPRESC 0x3 +#define CONF_XOSC0_IMULT 0x4 +#define CONF_XOSC0_IPTAT 0x3 +#endif + +// <e> External Multipurpose Crystal Oscillator Configuration +// <i> Indicates whether configuration for XOSC1 is enabled or not +// <id> enable_xosc1 +#ifndef CONF_XOSC1_CONFIG +#define CONF_XOSC1_CONFIG 0 +#endif + +// <o> Frequency <8000000-48000000> +// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// <id> xosc1_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC1_FREQUENCY 12000000 +#endif + +// <h> External Multipurpose Crystal Oscillator Control +// <q> Oscillator enable +// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// <id> xosc1_arch_enable +#ifndef CONF_XOSC1_ENABLE +#define CONF_XOSC1_ENABLE 0 +#endif + +// <o> Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// <id> xosc1_arch_startup +#ifndef CONF_XOSC1_STARTUP +#define CONF_XOSC1_STARTUP 0 +#endif + +// <q> Clock Switch Back +// <i> Indicates whether Clock Switch Back is enabled or not +// <id> xosc1_arch_swben +#ifndef CONF_XOSC1_SWBEN +#define CONF_XOSC1_SWBEN 0 +#endif + +// <q> Clock Failure Detector +// <i> Indicates whether Clock Failure Detector is enabled or not +// <id> xosc1_arch_cfden +#ifndef CONF_XOSC1_CFDEN +#define CONF_XOSC1_CFDEN 0 +#endif + +// <q> Automatic Loop Control Enable +// <i> Indicates whether Automatic Loop Control is enabled or not +// <id> xosc1_arch_enalc +#ifndef CONF_XOSC1_ENALC +#define CONF_XOSC1_ENALC 0 +#endif + +// <q> Low Buffer Gain Enable +// <i> Indicates whether Low Buffer Gain is enabled or not +// <id> xosc1_arch_lowbufgain +#ifndef CONF_XOSC1_LOWBUFGAIN +#define CONF_XOSC1_LOWBUFGAIN 0 +#endif + +// <q> On Demand Control +// <i> Indicates whether On Demand Control is enabled or not +// <id> xosc1_arch_ondemand +#ifndef CONF_XOSC1_ONDEMAND +#define CONF_XOSC1_ONDEMAND 0 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> xosc1_arch_runstdby +#ifndef CONF_XOSC1_RUNSTDBY +#define CONF_XOSC1_RUNSTDBY 0 +#endif + +// <q> Crystal connected to XIN/XOUT Enable +// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// <id> xosc1_arch_xtalen +#ifndef CONF_XOSC1_XTALEN +#define CONF_XOSC1_XTALEN 0 +#endif +//</h> +//</e> + +#if CONF_XOSC1_FREQUENCY >= 32000000 +#define CONF_XOSC1_CFDPRESC 0x0 +#define CONF_XOSC1_IMULT 0x7 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 24000000 +#define CONF_XOSC1_CFDPRESC 0x1 +#define CONF_XOSC1_IMULT 0x6 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 16000000 +#define CONF_XOSC1_CFDPRESC 0x2 +#define CONF_XOSC1_IMULT 0x5 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 8000000 +#define CONF_XOSC1_CFDPRESC 0x3 +#define CONF_XOSC1_IMULT 0x4 +#define CONF_XOSC1_IPTAT 0x3 +#endif + +// <e> DFLL Configuration +// <i> Indicates whether configuration for DFLL is enabled or not +// <id> enable_dfll +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// <y> Reference Clock Source +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 +// <i> Select the clock source +// <id> dfll_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// <h> Digital Frequency Locked Loop Control +// <q> DFLL Enable +// <i> Indicates whether DFLL is enabled or not +// <id> dfll_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 1 +#endif + +// <q> On Demand Control +// <i> Indicates whether On Demand Control is enabled or not +// <id> dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// <q> USB Clock Recovery Mode +// <i> Indicates whether USB Clock Recovery Mode is enabled or not +// <id> dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 1 +#endif + +// <q> Wait Lock +// <i> Indicates whether Wait Lock is enabled or not +// <id> dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 1 +#endif + +// <q> Bypass Coarse Lock +// <i> Indicates whether Bypass Coarse Lock is enabled or not +// <id> dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// <q> Quick Lock Disable +// <i> Indicates whether Quick Lock Disable is enabled or not +// <id> dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// <q> Chill Cycle Disable +// <i> Indicates whether Chill Cycle Disable is enabled or not +// <id> dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 1 +#endif + +// <q> Lose Lock After Wake +// <i> Indicates whether Lose Lock After Wake is enabled or not +// <id> dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// <q> Stable DFLL Frequency +// <i> Indicates whether Stable DFLL Frequency is enabled or not +// <id> dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// <o> Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// <id> dfll_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0x0 +#endif + +// <o> Coarse Maximum Step <0x0-0x1F> +// <id> dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 0x1 +#endif + +// <o> Fine Maximum Step <0x0-0xFF> +// <id> dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 0x1 +#endif + +// <o> DFLL Multiply Factor <0x0-0xFFFF> +// <id> dfll_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0x0 +#endif + +// <e> DFLL Calibration Overwrite +// <i> Indicates whether Overwrite Calibration value of DFLL +// <id> dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// <o> Coarse Value <0x0-0x3F> +// <id> dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// <o> Fine Value <0x0-0xFF> +// <id> dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x80) +#endif + +//</e> + +//</h> + +//</e> + +// <e> FDPLL0 Configuration +// <i> Indicates whether configuration for FDPLL0 is enabled or not +// <id> enable_fdpll0 +#ifndef CONF_FDPLL0_CONFIG +#define CONF_FDPLL0_CONFIG 1 +#endif + +// <y> Reference Clock Source +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 +// <i> Select the clock source. +// <id> fdpll0_ref_clock +#ifndef CONF_FDPLL0_GCLK +#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK5_Val +#endif + +// <h> Digital Phase Locked Loop Control +// <q> Enable +// <i> Indicates whether Digital Phase Locked Loop is enabled or not +// <id> fdpll0_arch_enable +#ifndef CONF_FDPLL0_ENABLE +#define CONF_FDPLL0_ENABLE 1 +#endif + +// <q> On Demand Control +// <i> Indicates whether On Demand Control is enabled or not +// <id> fdpll0_arch_ondemand +#ifndef CONF_FDPLL0_ONDEMAND +#define CONF_FDPLL0_ONDEMAND 0 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> fdpll0_arch_runstdby +#ifndef CONF_FDPLL0_RUNSTDBY +#define CONF_FDPLL0_RUNSTDBY 0 +#endif + +// <o> Loop Divider Ratio Fractional Part <0x0-0x1F> +// <id> fdpll0_ldrfrac +#ifndef CONF_FDPLL0_LDRFRAC +#define CONF_FDPLL0_LDRFRAC 0x0 +#endif + +// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF> +// <id> fdpll0_ldr +#ifndef CONF_FDPLL0_LDR +#define CONF_FDPLL0_LDR 59 +#endif + +// <o> Clock Divider <0x0-0x7FF> +// <id> fdpll0_clock_div +#ifndef CONF_FDPLL0_DIV +#define CONF_FDPLL0_DIV 0x0 +#endif + +// <q> DCO Filter Enable +// <i> Indicates whether DCO Filter Enable is enabled or not +// <id> fdpll0_arch_dcoen +#ifndef CONF_FDPLL0_DCOEN +#define CONF_FDPLL0_DCOEN 0 +#endif + +// <o> Sigma-Delta DCO Filter Selection <0x0-0x7> +// <id> fdpll0_clock_dcofilter +#ifndef CONF_FDPLL0_DCOFILTER +#define CONF_FDPLL0_DCOFILTER 0x0 +#endif + +// <q> Lock Bypass +// <i> Indicates whether Lock Bypass is enabled or not +// <id> fdpll0_arch_lbypass +#ifndef CONF_FDPLL0_LBYPASS +#define CONF_FDPLL0_LBYPASS 0 +#endif + +// <o> Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// <id> fdpll0_arch_ltime +#ifndef CONF_FDPLL0_LTIME +#define CONF_FDPLL0_LTIME 0x0 +#endif + +// <o> Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// <id> fdpll0_arch_refclk +#ifndef CONF_FDPLL0_REFCLK +#define CONF_FDPLL0_REFCLK 0x0 +#endif + +// <q> Wake Up Fast +// <i> Indicates whether Wake Up Fast is enabled or not +// <id> fdpll0_arch_wuf +#ifndef CONF_FDPLL0_WUF +#define CONF_FDPLL0_WUF 0 +#endif + +// <o> Proportional Integral Filter Selection <0x0-0xF> +// <id> fdpll0_arch_filter +#ifndef CONF_FDPLL0_FILTER +#define CONF_FDPLL0_FILTER 0x0 +#endif + +//</h> +//</e> +// <e> FDPLL1 Configuration +// <i> Indicates whether configuration for FDPLL1 is enabled or not +// <id> enable_fdpll1 +#ifndef CONF_FDPLL1_CONFIG +#define CONF_FDPLL1_CONFIG 0 +#endif + +// <y> Reference Clock Source +// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) +// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0) +// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1) +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 +// <i> Select the clock source. +// <id> fdpll1_ref_clock +#ifndef CONF_FDPLL1_GCLK +#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// <h> Digital Phase Locked Loop Control +// <q> Enable +// <i> Indicates whether Digital Phase Locked Loop is enabled or not +// <id> fdpll1_arch_enable +#ifndef CONF_FDPLL1_ENABLE +#define CONF_FDPLL1_ENABLE 0 +#endif + +// <q> On Demand Control +// <i> Indicates whether On Demand Control is enabled or not +// <id> fdpll1_arch_ondemand +#ifndef CONF_FDPLL1_ONDEMAND +#define CONF_FDPLL1_ONDEMAND 0 +#endif + +// <q> Run in Standby +// <i> Indicates whether Run in Standby is enabled or not +// <id> fdpll1_arch_runstdby +#ifndef CONF_FDPLL1_RUNSTDBY +#define CONF_FDPLL1_RUNSTDBY 0 +#endif + +// <o> Loop Divider Ratio Fractional Part <0x0-0x1F> +// <id> fdpll1_ldrfrac +#ifndef CONF_FDPLL1_LDRFRAC +#define CONF_FDPLL1_LDRFRAC 0xd +#endif + +// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF> +// <id> fdpll1_ldr +#ifndef CONF_FDPLL1_LDR +#define CONF_FDPLL1_LDR 0x5b7 +#endif + +// <o> Clock Divider <0x0-0x7FF> +// <id> fdpll1_clock_div +#ifndef CONF_FDPLL1_DIV +#define CONF_FDPLL1_DIV 0x0 +#endif + +// <q> DCO Filter Enable +// <i> Indicates whether DCO Filter Enable is enabled or not +// <id> fdpll1_arch_dcoen +#ifndef CONF_FDPLL1_DCOEN +#define CONF_FDPLL1_DCOEN 0 +#endif + +// <o> Sigma-Delta DCO Filter Selection <0x0-0x7> +// <id> fdpll1_clock_dcofilter +#ifndef CONF_FDPLL1_DCOFILTER +#define CONF_FDPLL1_DCOFILTER 0x0 +#endif + +// <q> Lock Bypass +// <i> Indicates whether Lock Bypass is enabled or not +// <id> fdpll1_arch_lbypass +#ifndef CONF_FDPLL1_LBYPASS +#define CONF_FDPLL1_LBYPASS 0 +#endif + +// <o> Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// <id> fdpll1_arch_ltime +#ifndef CONF_FDPLL1_LTIME +#define CONF_FDPLL1_LTIME 0x0 +#endif + +// <o> Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// <id> fdpll1_arch_refclk +#ifndef CONF_FDPLL1_REFCLK +#define CONF_FDPLL1_REFCLK 0x1 +#endif + +// <q> Wake Up Fast +// <i> Indicates whether Wake Up Fast is enabled or not +// <id> fdpll1_arch_wuf +#ifndef CONF_FDPLL1_WUF +#define CONF_FDPLL1_WUF 0 +#endif + +// <o> Proportional Integral Filter Selection <0x0-0xF> +// <id> fdpll1_arch_filter +#ifndef CONF_FDPLL1_FILTER +#define CONF_FDPLL1_FILTER 0x0 +#endif + +//</h> +//</e> + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_rtc_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_rtc_config.h new file mode 100644 index 000000000..2b0b6712e --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_rtc_config.h @@ -0,0 +1,145 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// <q> Force reset RTC on initialization +// <i> Force RTC to reset on initialization. +// <i> Note that the previous power down data in RTC is lost if it's enabled. +// <id> rtc_arch_init_reset +#ifndef CONF_RTC_INIT_RESET +#define CONF_RTC_INIT_RESET 0 +#endif + +// <o> Prescaler configuration +// <0x0=>OFF(Peripheral clock divided by 1) +// <0x1=>Peripheral clock divided by 1 +// <0x2=>Peripheral clock divided by 2 +// <0x3=>Peripheral clock divided by 4 +// <0x4=>Peripheral clock divided by 8 +// <0x5=>Peripheral clock divided by 16 +// <0x6=>Peripheral clock divided by 32 +// <0x7=>Peripheral clock divided by 64 +// <0x8=>Peripheral clock divided by 128 +// <0x9=>Peripheral clock divided by 256 +// <0xA=>Peripheral clock divided by 512 +// <0xB=>Peripheral clock divided by 1024 +// <i> These bits define the RTC clock relative to the peripheral clock +// <id> rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER +#define CONF_RTC_PRESCALER 0xb + +#endif + +// <o> Compare Value <1-4294967295> +// <i> These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), +// <i> by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms. +// <id> rtc_arch_comp_val + +#ifndef CONF_RTC_COMP_VAL +#define CONF_RTC_COMP_VAL 1 + +#endif + +// <e> Event control +// <id> rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// <q> Periodic Interval 0 Event Output +// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated +// <id> rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// <q> Periodic Interval 1 Event Output +// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated +// <id> rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// <q> Periodic Interval 2 Event Output +// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated +// <id> rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// <q> Periodic Interval 3 Event Output +// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated +// <id> rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// <q> Periodic Interval 4 Event Output +// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated +// <id> rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// <q> Periodic Interval 5 Event Output +// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated +// <id> rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// <q> Periodic Interval 6 Event Output +// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated +// <id> rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// <q> Periodic Interval 7 Event Output +// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated +// <id> rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// <q> Compare 0 Event Output +// <i> This bit indicates whether Compare O event is enabled and will be generated +// <id> rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// <q> Compare 1 Event Output +// <i> This bit indicates whether Compare 1 event is enabled and will be generated +// <id> rtc_cmpeo1 +#ifndef CONF_RTC_COMPE1 +#define CONF_RTC_COMPE1 0 +#endif +// <q> Overflow Event Output +// <i> This bit indicates whether Overflow event is enabled and will be generated +// <id> rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// <q> Tamper Event Output +// <i> This bit indicates whether Tamper event output is enabled and will be generated +// <id> rtc_tampereo +#ifndef CONF_RTC_TAMPEREO +#define CONF_RTC_TAMPEREO 0 +#endif + +// <q> Tamper Event Input +// <i> This bit indicates whether Tamper event input is enabled and will be generated +// <id> rtc_tampevei +#ifndef CONF_RTC_TAMPEVEI +#define CONF_RTC_TAMPEVEI 0 +#endif +// </e> + +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_sercom_config.h new file mode 100644 index 000000000..cd411154c --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_sercom_config.h @@ -0,0 +1,751 @@ +// For CircuitPython, use SERCOM settings as prototypes to set +// the default settings. This file defines these SERCOMs +// +// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous +// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous +// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous +// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA + +#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0 +#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY + +#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1 + +#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2 +#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY + +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include <peripheral_clk_config.h> + +// Enable configuration of module +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_0_SPI_MODE +#define CONF_SERCOM_0_SPI_MODE 0x03 +#endif + +// <h> Basic Configuration + +// <q> Receive buffer enable +// <i> Enable receive buffer to receive data from slave (RXEN) +// <id> spi_master_rx_enable +#ifndef CONF_SERCOM_0_SPI_RXEN +#define CONF_SERCOM_0_SPI_RXEN 0x1 +#endif + +// <o> Character Size +// <i> Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// <id> spi_master_character_size +#ifndef CONF_SERCOM_0_SPI_CHSIZE +#define CONF_SERCOM_0_SPI_CHSIZE 0x0 +#endif + +// <o> Baud rate <1-12000000> +// <i> The SPI data transfer rate +// <id> spi_master_baud_rate +#ifndef CONF_SERCOM_0_SPI_BAUD +#define CONF_SERCOM_0_SPI_BAUD 50000 +#endif + +// </h> + +// <e> Advanced Configuration +// <id> spi_master_advanced +#ifndef CONF_SERCOM_0_SPI_ADVANCED +#define CONF_SERCOM_0_SPI_ADVANCED 1 +#endif + +// <o> Dummy byte <0x00-0x1ff> +// <id> spi_master_dummybyte +// <i> Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE +#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff +#endif + +// <o> Data Order +// <0=>MSB first +// <1=>LSB first +// <i> I least significant or most significant bit is shifted out first (DORD) +// <id> spi_master_arch_dord +#ifndef CONF_SERCOM_0_SPI_DORD +#define CONF_SERCOM_0_SPI_DORD 0x0 +#endif + +// <o> Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// <id> spi_master_arch_cpol +#ifndef CONF_SERCOM_0_SPI_CPOL +#define CONF_SERCOM_0_SPI_CPOL 0x0 +#endif + +// <o> Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// <id> spi_master_arch_cpha +#ifndef CONF_SERCOM_0_SPI_CPHA +#define CONF_SERCOM_0_SPI_CPHA 0x0 +#endif + +// <o> Immediate Buffer Overflow Notification +// <i> Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// <id> spi_master_arch_ibon +#ifndef CONF_SERCOM_0_SPI_IBON +#define CONF_SERCOM_0_SPI_IBON 0x0 +#endif + +// <q> Run in stand-by +// <i> Module stays active in stand-by sleep mode. (RUNSTDBY) +// <id> spi_master_arch_runstdby +#ifndef CONF_SERCOM_0_SPI_RUNSTDBY +#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0 +#endif + +// <o> Debug Stop Mode +// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// <id> spi_master_arch_dbgstop +#ifndef CONF_SERCOM_0_SPI_DBGSTOP +#define CONF_SERCOM_0_SPI_DBGSTOP 0 +#endif + +// </e> + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_0_SPI_AMODE_EN +#define CONF_SERCOM_0_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_AMODE +#define CONF_SERCOM_0_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDR +#define CONF_SERCOM_0_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDRMASK +#define CONF_SERCOM_0_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_SSDE +#define CONF_SERCOM_0_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_MSSEN +#define CONF_SERCOM_0_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_0_SPI_PLOADEN +#define CONF_SERCOM_0_SPI_PLOADEN 0 +#endif + +// <o> Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// <id> spi_master_rxpo +#ifndef CONF_SERCOM_0_SPI_RXPO +#define CONF_SERCOM_0_SPI_RXPO 2 +#endif + +// <o> Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// <id> spi_master_txpo +#ifndef CONF_SERCOM_0_SPI_TXPO +#define CONF_SERCOM_0_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_0_SPI_BAUD_RATE +#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1 +#endif + +#include <peripheral_clk_config.h> + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 1 +#endif + +// <h> Basic + +// <o> I2C Bus clock speed (Hz) <1-400000> +// <i> I2C Bus clock (SCL) speed measured in Hz +// <id> i2c_master_baud_rate +#ifndef CONF_SERCOM_1_I2CM_BAUD +#define CONF_SERCOM_1_I2CM_BAUD 100000 +#endif + +// </h> + +// <e> Advanced +// <id> i2c_master_advanced +#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 1 +#endif + +// <o> TRise (ns) <0-300> +// <i> Determined by the bus impedance, check electric characteristics in the datasheet +// <i> Standard Fast Mode: typical 215ns, max 300ns +// <i> Fast Mode +: typical 60ns, max 100ns +// <i> High Speed Mode: typical 20ns, max 40ns +// <id> i2c_master_arch_trise + +#ifndef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// <q> Master SCL Low Extended Time-Out (MEXTTOEN) +// <i> This enables the master SCL low extend time-out +// <id> i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN +#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 +#endif + +// <q> Slave SCL Low Extend Time-Out (SEXTTOEN) +// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// <id> i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN +#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 +#endif + +// <q> SCL Low Time-Out (LOWTOUT) +// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// <id> i2c_master_arch_lowtout +#ifndef CONF_SERCOM_1_I2CM_LOWTOUT +#define CONF_SERCOM_1_I2CM_LOWTOUT 0 +#endif + +// <o> Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be +// <id> i2c_master_arch_inactout +#ifndef CONF_SERCOM_1_I2CM_INACTOUT +#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 +#endif + +// <o> SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// <i> Defines the SDA hold time with respect to the negative edge of SCL +// <id> i2c_master_arch_sdahold +#ifndef CONF_SERCOM_1_I2CM_SDAHOLD +#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 +#endif + +// <q> Run in stand-by +// <i> Determine if the module shall run in standby sleep mode +// <id> i2c_master_arch_runstdby +#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY +#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 +#endif + +// <o> Debug Stop Mode +// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// <id> i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 +#endif + +// </e> + +#ifndef CONF_SERCOM_1_I2CM_SPEED +#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10)) +#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE +#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_1_I2CM_BAUD_RATE \ + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include <peripheral_clk_config.h> + +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 +#endif + +// <h> Basic Configuration + +// <q> Receive buffer enable +// <i> Enable input buffer in SERCOM module +// <id> usart_rx_enable +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 +#endif + +// <q> Transmitt buffer enable +// <i> Enable output buffer in SERCOM module +// <id> usart_tx_enable +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 +#endif + +// <o> Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// <i> Parity bit mode for USART frame +// <id> usart_parity +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 +#endif + +// <o> Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// <i> Data character size in USART frame +// <id> usart_character_size +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#endif + +// <o> Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// <i> Number of stop bits in USART frame +// <id> usart_stop_bit +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 +#endif + +// <o> Baud rate <1-3000000> +// <i> USART baud rate setting +// <id> usart_baud_rate +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 9600 +#endif + +// </h> + +// <e> Advanced configuration +// <id> usart_advanced +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 1 +#endif + +// <q> Run in stand-by +// <i> Keep the module running in standby sleep mode +// <id> usart_arch_runstdby +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#endif + +// <q> Immediate Buffer Overflow Notification +// <i> Controls when the BUFOVF status bit is asserted +// <id> usart_arch_ibon +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 +#endif + +// <q> Start of Frame Detection Enable +// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// <id> usart_arch_sfde +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 +#endif + +// <q> Collision Detection Enable +// <i> Collision detection enable +// <id> usart_arch_cloden +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 +#endif + +// <o> Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// <id> usart_arch_clock_mode +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 +#endif + +// <o> Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x3=>3x +// <i> How many over-sampling bits used when samling data state +// <id> usart_arch_sampr +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 +#endif + +// <o> Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// <i> Adjust which samples to use for data sampling in asynchronous mode +// <id> usart_arch_sampa +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 +#endif + +// <o> Fractional Part <0-7> +// <i> Fractional part of the baud rate if baud rate generator is in fractional mode +// <id> usart_arch_fractional +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#endif + +// <o> Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// <i> Data order of the data bits in the frame +// <id> usart_arch_dord +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_2_USART_CPOL 0 + +// <o> Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// <id> usart_arch_enc +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 +#endif + +// <o> Debug Stop Mode +// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// <id> usart_arch_dbgstop +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#endif + +// </e> + +#ifndef CONF_SERCOM_2_USART_INACK +#define CONF_SERCOM_2_USART_INACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_DSNACK +#define CONF_SERCOM_2_USART_DSNACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_MAXITER +#define CONF_SERCOM_2_USART_MAXITER 0x7 +#endif + +#ifndef CONF_SERCOM_2_USART_GTIME +#define CONF_SERCOM_2_USART_GTIME 0x2 +#endif + +#define CONF_SERCOM_2_USART_RXINV 0x0 +#define CONF_SERCOM_2_USART_TXINV 0x0 + +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA08 */ +#endif + +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA09 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +#include <peripheral_clk_config.h> + +// Enable configuration of module +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 1 +#endif + +//<o> SPI DMA TX Channel <0-32> +//<i> This defines DMA channel to be used +//<id> spi_master_dma_tx_channel +#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL +#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0 +#endif + +// <e> SPI RX Channel Enable +// <id> spi_master_rx_channel +#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL +#define CONF_SERCOM_3_SPI_RX_CHANNEL 1 +#endif + +//<o> DMA Channel <0-32> +//<i> This defines DMA channel to be used +//<id> spi_master_dma_rx_channel +#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL +#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1 +#endif + +// </e> + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_3_SPI_MODE +#define CONF_SERCOM_3_SPI_MODE 0x03 +#endif + +// <h> Basic Configuration + +// <q> Receive buffer enable +// <i> Enable receive buffer to receive data from slave (RXEN) +// <id> spi_master_rx_enable +#ifndef CONF_SERCOM_3_SPI_RXEN +#define CONF_SERCOM_3_SPI_RXEN 0x1 +#endif + +// <o> Character Size +// <i> Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// <id> spi_master_character_size +#ifndef CONF_SERCOM_3_SPI_CHSIZE +#define CONF_SERCOM_3_SPI_CHSIZE 0x0 +#endif + +// <o> Baud rate <1-12000000> +// <i> The SPI data transfer rate +// <id> spi_master_baud_rate +#ifndef CONF_SERCOM_3_SPI_BAUD +#define CONF_SERCOM_3_SPI_BAUD 50000 +#endif + +// </h> + +// <e> Advanced Configuration +// <id> spi_master_advanced +#ifndef CONF_SERCOM_3_SPI_ADVANCED +#define CONF_SERCOM_3_SPI_ADVANCED 0 +#endif + +// <o> Dummy byte <0x00-0x1ff> +// <id> spi_master_dummybyte +// <i> Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE +#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff +#endif + +// <o> Data Order +// <0=>MSB first +// <1=>LSB first +// <i> I least significant or most significant bit is shifted out first (DORD) +// <id> spi_master_arch_dord +#ifndef CONF_SERCOM_3_SPI_DORD +#define CONF_SERCOM_3_SPI_DORD 0x0 +#endif + +// <o> Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// <id> spi_master_arch_cpol +#ifndef CONF_SERCOM_3_SPI_CPOL +#define CONF_SERCOM_3_SPI_CPOL 0x0 +#endif + +// <o> Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// <id> spi_master_arch_cpha +#ifndef CONF_SERCOM_3_SPI_CPHA +#define CONF_SERCOM_3_SPI_CPHA 0x0 +#endif + +// <o> Immediate Buffer Overflow Notification +// <i> Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// <id> spi_master_arch_ibon +#ifndef CONF_SERCOM_3_SPI_IBON +#define CONF_SERCOM_3_SPI_IBON 0x0 +#endif + +// <q> Run in stand-by +// <i> Module stays active in stand-by sleep mode. (RUNSTDBY) +// <id> spi_master_arch_runstdby +#ifndef CONF_SERCOM_3_SPI_RUNSTDBY +#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0 +#endif + +// <o> Debug Stop Mode +// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// <id> spi_master_arch_dbgstop +#ifndef CONF_SERCOM_3_SPI_DBGSTOP +#define CONF_SERCOM_3_SPI_DBGSTOP 0 +#endif + +// </e> + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_3_SPI_AMODE_EN +#define CONF_SERCOM_3_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_AMODE +#define CONF_SERCOM_3_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_ADDR +#define CONF_SERCOM_3_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_ADDRMASK +#define CONF_SERCOM_3_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_SSDE +#define CONF_SERCOM_3_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_MSSEN +#define CONF_SERCOM_3_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_3_SPI_PLOADEN +#define CONF_SERCOM_3_SPI_PLOADEN 0 +#endif + +// <o> Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// <id> spi_master_rxpo +#ifndef CONF_SERCOM_3_SPI_RXPO +#define CONF_SERCOM_3_SPI_RXPO 2 +#endif + +// <o> Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// <id> spi_master_txpo +#ifndef CONF_SERCOM_3_SPI_TXPO +#define CONF_SERCOM_3_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_3_SPI_BAUD_RATE +#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1 +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_systick_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_systick_config.h new file mode 100644 index 000000000..a7f2f3620 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Advanced settings +// <q> SysTick exception request +// <i> Indicates whether the generation of SysTick exception is enabled or not +// <id> systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_tc_config.h new file mode 100644 index 000000000..38d48e9b6 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_tc_config.h @@ -0,0 +1,209 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include <peripheral_clk_config.h> + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +// <h> Basic settings +// <o> Prescaler +// <0=> No division +// <1=> Divide by 2 +// <2=> Divide by 4 +// <3=> Divide by 8 +// <4=> Divide by 16 +// <5=> Divide by 64 +// <6=> Divide by 256 +// <7=> Divide by 1024 +// <i> This defines the prescaler value +// <id> tc_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0 +#endif +// </h> + +// <h> PWM Waveform Output settings +// <o> Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// <i> The unit of this value is us. +// <id> tc_arch_wave_per_val +#ifndef CONF_TC0_WAVE_PER_VAL +#define CONF_TC0_WAVE_PER_VAL 0x3e8 +#endif + +// <o> Waveform Duty Value (0.1%) <0x00-0x03E8> +// <i> The unit of this value is 1/1000. +// <id> tc_arch_wave_duty_val +#ifndef CONF_TC0_WAVE_DUTY_VAL +#define CONF_TC0_WAVE_DUTY_VAL 0x1f4 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 \ + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 64000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 256000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1024000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) +#endif + +// </h> + +// <h> Advanced settings +// <y> Mode +// <TC_CTRLA_MODE_COUNT16_Val"> Counter in 16-bit mode +// <TC_CTRLA_MODE_COUNT32_Val"> Counter in 32-bit mode +// <i> These bits mode +// <id> tc_mode +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT16_Val +#endif + +// <o> Period Value <0x00000000-0xFFFFFFFF> +// <id> tc_per +#ifndef CONF_TC0_PER +#define CONF_TC0_PER 0x32 +#endif +// </h> + +// <h> Advanced settings +// <y> Prescaler and Counter Synchronization Selection +// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK +// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock +// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter +// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// <id> tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// <q> Run in standby +// <i> Indicates whether the will continue running in standby sleep mode or not +// <id> tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// <q> On-Demand +// <i> Indicates whether the TC0's on-demand mode is on or not +// <id> tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// <o> Auto Lock +// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event +// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event +// <id> tc_arch_alock +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CAPTEN0 0 +//#define CONF_TC0_CAPTEN1 0 +//#define CONF_TC0_COPEN0 0 +//#define CONF_TC0_COPEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_DIR 0 +//#define CONF_TC0_ONESHOT 0 +//#define CONF_TC0_LUPD 0 + +// <q> Debug Running Mode +// <i> Indicates whether the Debug Running Mode is enabled or not +// <id> tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// <e> Event control +// <id> timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 0 +#endif + +// <q> Output Event On Match or Capture on Channel 0 +// <i> Enable output of event on timer tick +// <id> tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// <q> Output Event On Match or Capture on Channel 1 +// <i> Enable output of event on timer tick +// <id> tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// <q> Output Event On Timer Tick +// <i> Enable output of event on timer tick +// <id> tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// <q> Event Input +// <i> Enable asynchronous input events +// <id> tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// <q> Inverted Event Input +// <i> Invert the asynchronous input events +// <id> tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// <o> Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// <i> Event which will be performed on an event +//<id> tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// </e> + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_INVEN0 0 +//#define CONF_TC0_INVEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_PERBUF 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CCBUF0 0 +//#define CONF_TC0_CCBUF1 0 + +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_trng_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_trng_config.h new file mode 100644 index 000000000..ba9014989 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_trng_config.h @@ -0,0 +1,27 @@ +/* Auto-generated config file hpl_trng_config.h */ +#ifndef HPL_TRNG_CONFIG_H +#define HPL_TRNG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <h> Advanced configurations + +// <q> Run In Standby +// <i> Indicates whether the TRNG works in standby mode +// <id> trng_runstdby +#ifndef CONF_TRNG_RUNSTDBY +#define CONF_TRNG_RUNSTDBY 0 +#endif + +// <q> Data Ready Event Output Enable +// <i> Indicates whether the TRNG generates event on Data Ready +// <id> trng_datardyeo +#ifndef CONF_TRNG_DATARDYEO +#define CONF_TRNG_DATARDYEO 0 +#endif + +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_TRNG_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_usb_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_usb_config.h new file mode 100644 index 000000000..d1bb42fe4 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/hpl_usb_config.h @@ -0,0 +1,413 @@ +/* Auto-generated config file hpl_usb_config.h */ +#ifndef HPL_USB_CONFIG_H +#define HPL_USB_CONFIG_H + +// CIRCUITPY: + +// Use 64-byte USB buffers for endpoint directions that are in use. They're set to 0 below otherwise. + +#include "genhdr/autogen_usb_descriptor.h" + +#if defined(USB_ENDPOINT_1_OUT_USED) && USB_ENDPOINT_1_OUT_USED +#define CONF_USB_EP1_CACHE 64 +#endif +#if defined(USB_ENDPOINT_1_IN_USED) && USB_ENDPOINT_1_IN_USED +#define CONF_USB_EP1_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_2_OUT_USED) && USB_ENDPOINT_2_OUT_USED +#define CONF_USB_EP2_CACHE 64 +#endif +#if defined(USB_ENDPOINT_2_IN_USED) && USB_ENDPOINT_2_IN_USED +#define CONF_USB_EP2_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_3_OUT_USED) && USB_ENDPOINT_3_OUT_USED +#define CONF_USB_EP3_CACHE 64 +#endif +#if defined(USB_ENDPOINT_3_IN_USED) && USB_ENDPOINT_3_IN_USED +#define CONF_USB_EP3_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_4_OUT_USED) && USB_ENDPOINT_4_OUT_USED +#define CONF_USB_EP4_CACHE 64 +#endif +#if defined(USB_ENDPOINT_4_IN_USED) && USB_ENDPOINT_4_IN_USED +#define CONF_USB_EP4_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_5_OUT_USED) && USB_ENDPOINT_5_OUT_USED +#define CONF_USB_EP5_CACHE 64 +#endif +#if defined(USB_ENDPOINT_5_IN_USED) && USB_ENDPOINT_5_IN_USED +#define CONF_USB_EP5_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_6_OUT_USED) && USB_ENDPOINT_6_OUT_USED +#define CONF_USB_EP6_CACHE 64 +#endif +#if defined(USB_ENDPOINT_6_IN_USED) && USB_ENDPOINT_6_IN_USED +#define CONF_USB_EP6_I_CACHE 64 +#endif + +#if defined(USB_ENDPOINT_7_OUT_USED) && USB_ENDPOINT_7_OUT_USED +#define CONF_USB_EP7_CACHE 64 +#endif +#if defined(USB_ENDPOINT_7_IN_USED) && USB_ENDPOINT_7_IN_USED +#define CONF_USB_EP7_I_CACHE 64 +#endif + + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_USB_N_0 0 +#define CONF_USB_N_1 1 +#define CONF_USB_N_2 2 +#define CONF_USB_N_3 3 +#define CONF_USB_N_4 4 +#define CONF_USB_N_5 5 +#define CONF_USB_N_6 6 +#define CONF_USB_N_7 7 +#define CONF_USB_N_8 8 +#define CONF_USB_N_9 9 +#define CONF_USB_N_10 10 +#define CONF_USB_N_11 11 +#define CONF_USB_N_12 12 +#define CONF_USB_N_13 13 +#define CONF_USB_N_14 14 +#define CONF_USB_N_15 15 + +#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) +#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) + +// <h> USB Device HAL Configuration + +// <y> Max number of endpoints supported +// <i> Limits the number of endpoints (described by EP address) can be used in app. +// NOTE(tannewt): This not only limits the number of endpoints but also the +// addresses. In other words, even if you use endpoint 6 you need to set this to 11. +// <CONF_USB_N_1"> 1 (EP0 only) +// <CONF_USB_N_2"> 2 (EP0 + 1 endpoint) +// <CONF_USB_N_3"> 3 (EP0 + 2 endpoints) +// <CONF_USB_N_4"> 4 (EP0 + 3 endpoints) +// <CONF_USB_N_5"> 5 (EP0 + 4 endpoints) +// <CONF_USB_N_6"> 6 (EP0 + 5 endpoints) +// <CONF_USB_N_7"> 7 (EP0 + 6 endpoints) +// <CONF_USB_N_8"> 8 (EP0 + 7 endpoints) +// <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config) +// <id> usbd_num_ep_sp +#ifndef CONF_USB_D_NUM_EP_SP +#define CONF_USB_D_NUM_EP_SP CONF_USB_D_N_EP_MAX +#endif + +// </h> + +// <y> Max Endpoint Number supported +// <i> Limits the max endpoint number. +// <i> USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. +// <i> Reduce the value according to specific device design, to cut-off memory usage. +// <CONF_USB_N_0"> 0 (only EP0) +// <CONF_USB_N_1"> 1 (EP 0x81 or 0x01) +// <CONF_USB_N_2"> 2 (EP 0x82 or 0x02) +// <CONF_USB_N_3"> 3 (EP 0x83 or 0x03) +// <CONF_USB_N_4"> 4 (EP 0x84 or 0x04) +// <CONF_USB_N_5"> 5 (EP 0x85 or 0x05) +// <CONF_USB_N_6"> 6 (EP 0x86 or 0x06) +// <CONF_USB_N_7"> 7 (EP 0x87 or 0x07) +// <CONF_USB_EP_N_MAX"> Max possible (by HW) +// <i> The number of physical endpoints - 1 +// <id> usbd_arch_max_ep_n +#ifndef CONF_USB_D_MAX_EP_N +#define CONF_USB_D_MAX_EP_N CONF_USB_D_EP_N_MAX +#endif + +// <y> USB Speed Limit +// <i> Limits the working speed of the device. +// <USB_SPEED_FS"> Full speed +// <USB_SPEED_LS"> Low Speed +// <id> usbd_arch_speed +#ifndef CONF_USB_D_SPEED +#define CONF_USB_D_SPEED USB_SPEED_FS +#endif + +// <o> Cache buffer size for EP0 +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <id> usb_arch_ep0_cache +#ifndef CONF_USB_EP0_CACHE +#define CONF_USB_EP0_CACHE 64 +#endif + +// <h> Cache configuration EP1 +// <o> Cache buffer size for EP1 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep1_cache +#ifndef CONF_USB_EP1_CACHE +#define CONF_USB_EP1_CACHE 0 +#endif + +// <o> Cache buffer size for EP1 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep1_I_CACHE +#ifndef CONF_USB_EP1_I_CACHE +#define CONF_USB_EP1_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP2 +// <o> Cache buffer size for EP2 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep2_cache +#ifndef CONF_USB_EP2_CACHE +#define CONF_USB_EP2_CACHE 0 +#endif + +// <o> Cache buffer size for EP2 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep2_I_CACHE +#ifndef CONF_USB_EP2_I_CACHE +#define CONF_USB_EP2_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP3 +// <o> Cache buffer size for EP3 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep3_cache +#ifndef CONF_USB_EP3_CACHE +#define CONF_USB_EP3_CACHE 0 +#endif + +// <o> Cache buffer size for EP3 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep3_I_CACHE +#ifndef CONF_USB_EP3_I_CACHE +#define CONF_USB_EP3_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP4 +// <o> Cache buffer size for EP4 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep4_cache +#ifndef CONF_USB_EP4_CACHE +#define CONF_USB_EP4_CACHE 0 +#endif + +// <o> Cache buffer size for EP4 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep4_I_CACHE +#ifndef CONF_USB_EP4_I_CACHE +#define CONF_USB_EP4_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP5 +// <o> Cache buffer size for EP5 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep5_cache +#ifndef CONF_USB_EP5_CACHE +#define CONF_USB_EP5_CACHE 0 +#endif + +// <o> Cache buffer size for EP5 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep5_I_CACHE +#ifndef CONF_USB_EP5_I_CACHE +#define CONF_USB_EP5_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP6 +// <o> Cache buffer size for EP6 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep6_cache +#ifndef CONF_USB_EP6_CACHE +#define CONF_USB_EP6_CACHE 0 +#endif + +// <o> Cache buffer size for EP6 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep6_I_CACHE +#ifndef CONF_USB_EP6_I_CACHE +#define CONF_USB_EP6_I_CACHE 0 +#endif +// </h> + +// <h> Cache configuration EP7 +// <o> Cache buffer size for EP7 OUT +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_arch_ep7_cache +#ifndef CONF_USB_EP7_CACHE +#define CONF_USB_EP7_CACHE 0 +#endif + +// <o> Cache buffer size for EP7 IN +// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint. +// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// <id> usb_ep7_I_CACHE +#ifndef CONF_USB_EP7_I_CACHE +#define CONF_USB_EP7_I_CACHE 0 +#endif +// </h> + +// <<< end of configuration section >>> + +#endif // HPL_USB_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h new file mode 100644 index 000000000..030a90a7a --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h @@ -0,0 +1,1006 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <y> ADC Clock Source +// <id> adc_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for ADC. +#ifndef CONF_GCLK_ADC0_SRC +#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_ADC0_FREQUENCY + * \brief ADC0's Clock frequency + */ +#ifndef CONF_GCLK_ADC0_FREQUENCY +#define CONF_GCLK_ADC0_FREQUENCY 48000000 +#endif + +// <y> DAC Clock Source + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <id> dac_gclk_selection +// <i> Select the clock source for DAC. +#ifndef CONF_GCLK_DAC_SRC +#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK6_Val +#endif + +/** + * \def CONF_GCLK_DAC_FREQUENCY + * \brief DAC's Clock frequency + */ +#ifndef CONF_GCLK_DAC_FREQUENCY +#define CONF_GCLK_DAC_FREQUENCY 2000000 +#endif + +// <y> EVSYS Channel 0 Clock Source +// <id> evsys_clk_selection_0 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 0. +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC +#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 1 Clock Source +// <id> evsys_clk_selection_1 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 1. +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC +#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 2 Clock Source +// <id> evsys_clk_selection_2 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 2. +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC +#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 3 Clock Source +// <id> evsys_clk_selection_3 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 3. +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC +#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 4 Clock Source +// <id> evsys_clk_selection_4 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 4. +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC +#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 5 Clock Source +// <id> evsys_clk_selection_5 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 5. +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC +#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 6 Clock Source +// <id> evsys_clk_selection_6 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 6. +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC +#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 7 Clock Source +// <id> evsys_clk_selection_7 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 7. +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC +#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 8 Clock Source +// <id> evsys_clk_selection_8 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 8. +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC +#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 9 Clock Source +// <id> evsys_clk_selection_9 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 9. +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC +#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 10 Clock Source +// <id> evsys_clk_selection_10 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 10. +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC +#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 48000000.0 +#endif + +// <y> EVSYS Channel 11 Clock Source +// <id> evsys_clk_selection_11 + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for channel 11. +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC +#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 48000000.0 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 120000000 +#endif + +// <y> RTC Clock Source +// <id> rtc_clk_selection +// <RTC_CLOCK_SOURCE"> RTC source +// <i> Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 1024 +#endif + +// <y> Core Clock Source +// <id> core_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +// <y> Slow Clock Source +// <id> slow_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 +#endif + +// <y> Core Clock Source +// <id> core_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +// <y> Slow Clock Source +// <id> slow_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 +#endif + +// <y> Core Clock Source +// <id> core_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +// <y> Slow Clock Source +// <id> slow_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 +#endif + +// <y> Core Clock Source +// <id> core_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +// <y> Slow Clock Source +// <id> slow_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 +#endif + +// <y> TC Clock Source +// <id> tc_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for TC. +#ifndef CONF_GCLK_TC0_SRC +#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_TC0_FREQUENCY + * \brief TC0's Clock frequency + */ +#ifndef CONF_GCLK_TC0_FREQUENCY +#define CONF_GCLK_TC0_FREQUENCY 48000000 +#endif + +// <y> USB Clock Source +// <id> usb_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 + +// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 + +// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 + +// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8 + +// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9 + +// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10 + +// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 + +// <i> Select the clock source for USB. +#ifndef CONF_GCLK_USB_SRC +#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val + +#endif + +/** + * \def CONF_GCLK_USB_FREQUENCY + * \brief USB's Clock frequency + */ +#ifndef CONF_GCLK_USB_FREQUENCY +#define CONF_GCLK_USB_FREQUENCY 48000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/same54/usbd_config.h b/ports/atmel-samd/asf4_conf/same54/usbd_config.h new file mode 100644 index 000000000..be1fa3c9e --- /dev/null +++ b/ports/atmel-samd/asf4_conf/same54/usbd_config.h @@ -0,0 +1,850 @@ +/* Auto-generated config file usbd_config.h */ +#ifndef USBD_CONFIG_H +#define USBD_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ---- USB Device Stack Core Options ---- + +// <q> High Speed Support +// <i> Enable high speed specific descriptors support, e.g., DeviceQualifierDescriptor and OtherSpeedConfiguration Descriptor. +// <i> High speed support require descriptors description array on start, for LS/FS and HS support in first and second place. +// <id> usbd_hs_sp +#ifndef CONF_USBD_HS_SP +#define CONF_USBD_HS_SP 0 +#endif + +// ---- USB Device Stack Composite Options ---- + +// <e> Enable String Descriptors +// <id> usb_composite_str_en +#ifndef CONF_USB_COMPOSITE_STR_EN +#define CONF_USB_COMPOSITE_STR_EN 0 +#endif +// <s> Language IDs +// <i> Language IDs in c format, split by comma (E.g., 0x0409 ...) +// <id> usb_composite_langid +#ifndef CONF_USB_COMPOSITE_LANGID +#define CONF_USB_COMPOSITE_LANGID "0x0409" +#endif + +#ifndef CONF_USB_COMPOSITE_LANGID_DESC +#define CONF_USB_COMPOSITE_LANGID_DESC +#endif +// </e> + +// <h> Composite Device Descriptor + +// <o> bcdUSB +// <0x0200=> USB 2.0 version +// <0x0210=> USB 2.1 version +// <id> usb_composite_bcdusb +#ifndef CONF_USB_COMPOSITE_BCDUSB +#define CONF_USB_COMPOSITE_BCDUSB 0x200 +#endif + +// <o> bMaxPackeSize0 +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <id> usb_composite_bmaxpksz0 +#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 +#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 +#endif + +// <o> idVender <0x0000-0xFFFF> +// <id> usb_composite_idvender +#ifndef CONF_USB_COMPOSITE_IDVENDER +#define CONF_USB_COMPOSITE_IDVENDER 0x3eb +#endif + +// <o> idProduct <0x0000-0xFFFF> +// <id> usb_composite_idproduct +#ifndef CONF_USB_COMPOSITE_IDPRODUCT +#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421 +#endif + +// <o> bcdDevice <0x0000-0xFFFF> +// <id> usb_composite_bcddevice +#ifndef CONF_USB_COMPOSITE_BCDDEVICE +#define CONF_USB_COMPOSITE_BCDDEVICE 0x100 +#endif + +// <e> Enable string descriptor of iManufact +// <id> usb_composite_imanufact_en +#ifndef CONF_USB_COMPOSITE_IMANUFACT_EN +#define CONF_USB_COMPOSITE_IMANUFACT_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_IMANUFACT +#define CONF_USB_COMPOSITE_IMANUFACT (CONF_USB_COMPOSITE_IMANUFACT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN)) +#endif + +// <s> Unicode string of iManufact +// <id> usb_composite_imanufact_str +#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR +#define CONF_USB_COMPOSITE_IMANUFACT_STR "Atmel" +#endif + +#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR_DESC +#define CONF_USB_COMPOSITE_IMANUFACT_STR_DESC +#endif + +// </e> + +// <e> Enable string descriptor of iProduct +// <id> usb_composite_iproduct_en +#ifndef CONF_USB_COMPOSITE_IPRODUCT_EN +#define CONF_USB_COMPOSITE_IPRODUCT_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_IPRODUCT +#define CONF_USB_COMPOSITE_IPRODUCT \ + (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) +#endif + +// <s> Unicode string of iProduct +// <id> usb_composite_iproduct_str +#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR +#define CONF_USB_COMPOSITE_IPRODUCT_STR "Composite Demo" +#endif + +#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR_DESC +#define CONF_USB_COMPOSITE_IPRODUCT_STR_DESC +#endif + +// </e> + +// <e> Enable string descriptor of iSerialNum +// <id> usb_composite_iserialnum_en +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_EN +#define CONF_USB_COMPOSITE_ISERIALNUM_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_ISERIALNUM +#define CONF_USB_COMPOSITE_ISERIALNUM \ + (CONF_USB_COMPOSITE_ISERIALNUM_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) +#endif + +// <s> Unicode string of iSerialNum +// <id> usb_composite_iserialnum_str +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR +#define CONF_USB_COMPOSITE_ISERIALNUM_STR "123456789ABCDEF" +#endif + +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC +#define CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC +#endif + +// </e> + +// <o> bNumConfigurations <0x01-0xFF> +// <id> usb_composite_bnumconfig +#ifndef CONF_USB_COMPOSITE_BNUMCONFIG +#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1 +#endif + +// </h> + +// <h> Composite Configuration Descriptor +// <o> bConfigurationValue <0x01-0xFF> +// <id> usb_composite_bconfigval +#ifndef CONF_USB_COMPOSITE_BCONFIGVAL +#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1 +#endif +// <e> Enable string descriptor of iConfig +// <id> usb_composite_iconfig_en +#ifndef CONF_USB_COMPOSITE_ICONFIG_EN +#define CONF_USB_COMPOSITE_ICONFIG_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_ICONFIG +#define CONF_USB_COMPOSITE_ICONFIG \ + (CONF_USB_COMPOSITE_ICONFIG_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ + + CONF_USB_COMPOSITE_ICONFIG_EN)) +#endif + +// <s> Unicode string of iConfig +// <id> usb_composite_iconfig_str +#ifndef CONF_USB_COMPOSITE_ICONFIG_STR +#define CONF_USB_COMPOSITE_ICONFIG_STR "" +#endif + +#ifndef CONF_USB_COMPOSITE_ICONFIG_STR_DESC +#define CONF_USB_COMPOSITE_ICONFIG_STR_DESC +#endif + +// </e> + +// <o> bmAttributes +// <0x80=> Bus power supply, not support for remote wakeup +// <0xA0=> Bus power supply, support for remote wakeup +// <0xC0=> Self powered, not support for remote wakeup +// <0xE0=> Self powered, support for remote wakeup +// <id> usb_composite_bmattri +#ifndef CONF_USB_COMPOSITE_BMATTRI +#define CONF_USB_COMPOSITE_BMATTRI 0x80 +#endif + +// <o> bMaxPower <0x00-0xFF> +// <id> usb_composite_bmaxpower +#ifndef CONF_USB_COMPOSITE_BMAXPOWER +#define CONF_USB_COMPOSITE_BMAXPOWER 0x32 +#endif +// </h> + +// <e> CDC ACM Support +// <id> usb_composite_cdc_acm_support +#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN +#define CONF_USB_COMPOSITE_CDC_ACM_EN 0 +#endif + +// <o> CDC ACM Comm Interrupt IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// <id> usb_composite_cdc_acm_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 +#endif + +// <o> CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// <id> usb_composite_cdc_acm_comm_int_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 +#endif + +// <o> CDC ACM Data BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// <id> usb_composite_cdc_acm_data_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 +#endif + +// <o> CDC ACM Data BULK IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// <id> usb_composite_cdc_acm_data_builin_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 +#endif + +// <o> CDC ACM Data BULK IN Endpoint wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// <id> usb_composite_cdc_acm_data_builin_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS 0x200 +#endif + +// <o> CDC ACM Data BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// <id> usb_composite_cdc_acm_data_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 +#endif + +// <o> CDC ACM Data BULK OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// <id> usb_composite_cdc_acm_data_buckout_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 +#endif + +// <o> CDC ACM Data BULK OUT Endpoint wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// <id> usb_composite_cdc_acm_data_buckout_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS 0x200 +#endif + +// <q> CDC ACM Echo Demo generation +// <id> conf_usb_composite_cdc_echo_demo +// <i> Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo. +// <i> Buf is packet buffer for data receive and echo back. +// <i> The buffer is 4 byte aligned to support DMA. +#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO +#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0 +#endif + +// </e> + +// <e> HID Mouse Support +// <id> usb_composite_hid_mouse_support +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN +#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0 +#endif + +// <o> HID Mouse INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// <id> usb_composite_hid_mouse_intin_epaddr +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83 +#endif + +// <o> HID Mouse INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// <id> usb_composite_hid_mouse_intin_maxpksz +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 +#endif + +// <q> HID Mouse Move Demo generation +// <id> conf_usb_composite_hid_mouse_demo +// <i> Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// <i> Button1 and button3 are the pins used for mouse moving left and right. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO +#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0 +#endif + +// </e> + +// <e> HID Keyboard Support +// <id> usb_composite_hid_keyboard_support +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN +#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0 +#endif + +// <o> HID Keyboard INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// <id> usb_composite_hid_keyboard_intin_epaddr +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84 +#endif + +// <o> HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// <id> usb_composite_hid_keyboard_intin_maxpksz +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8 +#endif + +// <o> HID Keyboard INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// <id> usb_composite_hid_keyboard_intout_epaddr +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2 +#endif + +// <o> HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// <id> usb_composite_hid_keyboard_intout_maxpksz +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 +#endif + +// <q> HID Keyboard Caps Lock Demo generation +// <id> conf_usb_composite_hid_keyboard_demo +// <i> Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// <i> Buffon2 is the pin used for keyboard CAPS LOCK simulation. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO +#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0 +#endif + +// </e> + +// <e> HID Generic Support +// <id> usb_composite_hid_generic_support +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN +#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 +#endif + +// <o> HID Generic INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// <id> usb_composite_hid_generic_intin_epaddr +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85 +#endif + +// <o> HID Generic INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// <id> usb_composite_hid_generic_intin_maxpksz +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40 +#endif + +// <o> HID Generic INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// <id> usb_composite_hid_generic_intout_epaddr +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3 +#endif + +// <o> HID Generic INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <id> usb_composite_hid_generic_intout_maxpksz +// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40 +#endif + +// </e> + +// <e> MSC Support +// <id> usb_composite_msc_support +#ifndef CONF_USB_COMPOSITE_MSC_EN +#define CONF_USB_COMPOSITE_MSC_EN 0 +#endif + +// <o> MSC BULK Endpoints wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// <id> usb_composite_msc_bulk_maxpksz +#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ +#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x40 +#endif + +// <o> MSC BULK Endpoints wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// <id> usb_composite_msc_bulk_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS 0x200 +#endif + +// <o> MSC BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// <id> usb_composite_msc_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86 +#endif + +// <o> MSC BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// <id> usb_composite_msc_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x4 +#endif + +// <e> Enable Demo code for Disk LUN handling +// <id> usb_composite_msc_demo_en +#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO +#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1 +#endif + +// <o> Disk access cache/buffer of sectors if non-RAM disk (e.g., SD/MMC) enabled <1-64> +// <id> conf_usb_msc_lun_buf_sectors +#ifndef CONF_USB_MSC_LUN_BUF_SECTORS +#define CONF_USB_MSC_LUN_BUF_SECTORS 4 +#endif + +// <e> Enable Demo for RAM Disk +// <id> conf_usb_msc_lun0_enable +#ifndef CONF_USB_MSC_LUN0_ENABLE +#define CONF_USB_MSC_LUN0_ENABLE 1 +#endif + +#ifndef CONF_USB_MSC_LUN0_TYPE +#define CONF_USB_MSC_LUN0_TYPE 0x00 +#endif + +// <q> The disk is removable +// <id> conf_usb_msc_lun0_rmb +#ifndef CONF_USB_MSC_LUN0_RMB +#define CONF_USB_MSC_LUN0_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN0_ISO +#define CONF_USB_MSC_LUN0_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ECMA +#define CONF_USB_MSC_LUN0_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ANSI +#define CONF_USB_MSC_LUN0_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_REPO +#define CONF_USB_MSC_LUN0_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN0_FACTORY +#define CONF_USB_MSC_LUN0_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT +#define CONF_USB_MSC_LUN0_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT_VERSION +#define CONF_USB_MSC_LUN0_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// <o> Disk Size (in KB) <0x1-0xFFFFFFFF> +// <i> Windows will not show disk less than 20K, so 22K is used to reserve more RAM for APP +// <id> conf_usb_msc_lun0_capacity + +#ifndef CONF_USB_MSC_LUN0_CAPACITY +#define CONF_USB_MSC_LUN0_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN0_BLOCK_SIZE +#define CONF_USB_MSC_LUN0_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) +#endif + +// </e> + +// <e> Enable Demo for SD/MMC Disk +// <i> SD/MMC stack must be added before enable SD/MMC demo +// <i> SD/MMC insert/eject not supported by this simple demo +// <id> conf_usb_msc_lun1_enable +#ifndef CONF_USB_MSC_LUN1_ENABLE +#define CONF_USB_MSC_LUN1_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN1_TYPE +#define CONF_USB_MSC_LUN1_TYPE 0x00 +#endif + +// <q> The disk is removable +// <i> SD/MMC stack must be added before enable SD/MMC demo +// <i> SD/MMC insert/eject not supported by this simple demo +// <id> conf_usb_msc_lun1_rmb +#ifndef CONF_USB_MSC_LUN1_RMB +#define CONF_USB_MSC_LUN1_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN1_ISO +#define CONF_USB_MSC_LUN1_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ECMA +#define CONF_USB_MSC_LUN1_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ANSI +#define CONF_USB_MSC_LUN1_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_REPO +#define CONF_USB_MSC_LUN1_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN1_FACTORY +#define CONF_USB_MSC_LUN1_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT +#define CONF_USB_MSC_LUN1_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT_VERSION +#define CONF_USB_MSC_LUN1_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_CAPACITY +#define CONF_USB_MSC_LUN1_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN1_BLOCK_SIZE +#define CONF_USB_MSC_LUN1_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) +#endif + +// </e> + +// <e> Enable Demo for LUN 2 +// <id> conf_usb_msc_lun2_enable +#ifndef CONF_USB_MSC_LUN2_ENABLE +#define CONF_USB_MSC_LUN2_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN2_TYPE +#define CONF_USB_MSC_LUN2_TYPE 0x00 +#endif + +// <q> The disk is removable +// <id> conf_usb_msc_lun2_rmb +#ifndef CONF_USB_MSC_LUN2_RMB +#define CONF_USB_MSC_LUN2_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN2_ISO +#define CONF_USB_MSC_LUN2_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_ECMA +#define CONF_USB_MSC_LUN2_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_ANSI +#define CONF_USB_MSC_LUN2_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_REPO +#define CONF_USB_MSC_LUN2_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN2_FACTORY +#define CONF_USB_MSC_LUN2_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_PRODUCT +#define CONF_USB_MSC_LUN2_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_PRODUCT_VERSION +#define CONF_USB_MSC_LUN2_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// <o> Disk Size (in KB) <0x1-0xFFFFFFFF> +// <id> conf_usb_msc_lun2_capacity + +#ifndef CONF_USB_MSC_LUN2_CAPACITY +#define CONF_USB_MSC_LUN2_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN2_BLOCK_SIZE +#define CONF_USB_MSC_LUN2_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) +#endif + +// </e> + +// <e> Enable Demo for LUN 3 +// <id> conf_usb_msc_lun3_enable +#ifndef CONF_USB_MSC_LUN3_ENABLE +#define CONF_USB_MSC_LUN3_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN3_TYPE +#define CONF_USB_MSC_LUN3_TYPE 0x00 +#endif + +// <q> The disk is removable +// <id> conf_usb_msc_lun3_rmb +#ifndef CONF_USB_MSC_LUN3_RMB +#define CONF_USB_MSC_LUN3_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN3_ISO +#define CONF_USB_MSC_LUN3_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_ECMA +#define CONF_USB_MSC_LUN3_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_ANSI +#define CONF_USB_MSC_LUN3_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_REPO +#define CONF_USB_MSC_LUN3_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN3_FACTORY +#define CONF_USB_MSC_LUN3_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_PRODUCT +#define CONF_USB_MSC_LUN3_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_PRODUCT_VERSION +#define CONF_USB_MSC_LUN3_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// <o> Disk Size (in KB) <0x1-0xFFFFFFFF> +// <id> conf_usb_msc_lun3_capacity + +#ifndef CONF_USB_MSC_LUN3_CAPACITY +#define CONF_USB_MSC_LUN3_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN3_BLOCK_SIZE +#define CONF_USB_MSC_LUN3_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) +#endif + +// </e> + +// </e> +// </e> + +// <<< end of configuration section >>> + +#endif // USBD_CONFIG_H diff --git a/ports/atmel-samd/bindings/samd/Clock.c b/ports/atmel-samd/bindings/samd/Clock.c index 24e425e8c..e1022c52f 100644 --- a/ports/atmel-samd/bindings/samd/Clock.c +++ b/ports/atmel-samd/bindings/samd/Clock.c @@ -272,7 +272,7 @@ MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table); #endif // SAMD21 -#ifdef SAMD51 +#ifdef SAM_D5X_E5X diff --git a/ports/atmel-samd/common-hal/_pew/PewPew.c b/ports/atmel-samd/common-hal/_pew/PewPew.c index 568dc6425..cfdfe75d8 100644 --- a/ports/atmel-samd/common-hal/_pew/PewPew.c +++ b/ports/atmel-samd/common-hal/_pew/PewPew.c @@ -88,7 +88,7 @@ void pew_init() { #ifdef SAMD21 turn_on_clocks(true, index, 0); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X turn_on_clocks(true, index, 1); #endif @@ -98,7 +98,7 @@ void pew_init() { TC_CTRLA_PRESCALER_DIV64 | TC_CTRLA_WAVEGEN_MFRQ; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc_reset(tc); tc_set_enable(tc, false); tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 diff --git a/ports/atmel-samd/common-hal/analogio/AnalogOut.c b/ports/atmel-samd/common-hal/analogio/AnalogOut.c index 9ac1f7bd1..e69a24071 100644 --- a/ports/atmel-samd/common-hal/analogio/AnalogOut.c +++ b/ports/atmel-samd/common-hal/analogio/AnalogOut.c @@ -50,7 +50,7 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, mp_raise_NotImplementedError(translate("No DAC on chip")); #else if (pin->number != PIN_PA02 - #ifdef SAMD51 + #ifdef SAM_D5X_E5X && pin->number != PIN_PA05 #endif ) { @@ -59,13 +59,13 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, } self->channel = 0; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (pin->number == PIN_PA05) { self->channel = 1; } #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X hri_mclk_set_APBDMASK_DAC_bit(MCLK); #endif @@ -80,16 +80,16 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self, // Don't double init the DAC on the SAMD51 when both outputs are in use. We use the free state // of each output pin to determine DAC state. int32_t result = ERR_NONE; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (!common_hal_mcu_pin_is_free(&pin_PA02) || !common_hal_mcu_pin_is_free(&pin_PA05)) { #endif // Fake the descriptor if the DAC is already initialized. self->descriptor.device.hw = DAC; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X } else { #endif result = dac_sync_init(&self->descriptor, DAC); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X } #endif if (result != ERR_NONE) { @@ -109,18 +109,18 @@ bool common_hal_analogio_analogout_deinited(analogio_analogout_obj_t *self) { } void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) { - #if (defined(SAMD21) && defined(PIN_PA02)) || defined(SAMD51) + #if (defined(SAMD21) && defined(PIN_PA02)) || defined(SAM_D5X_E5X) if (common_hal_analogio_analogout_deinited(self)) { return; } dac_sync_disable_channel(&self->descriptor, self->channel); reset_pin_number(PIN_PA02); // Only deinit the DAC on the SAMD51 if both outputs are free. - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (common_hal_mcu_pin_is_free(&pin_PA02) && common_hal_mcu_pin_is_free(&pin_PA05)) { #endif dac_sync_deinit(&self->descriptor); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X } #endif self->deinited = true; @@ -147,7 +147,7 @@ void analogout_reset(void) { #ifdef SAMD21 while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {} #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X while (DAC->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) {} #endif DAC->CTRLA.reg |= DAC_CTRLA_SWRST; diff --git a/ports/atmel-samd/common-hal/audiobusio/I2SOut.c b/ports/atmel-samd/common-hal/audiobusio/I2SOut.c index 8f827e7fb..20fa624ed 100644 --- a/ports/atmel-samd/common-hal/audiobusio/I2SOut.c +++ b/ports/atmel-samd/common-hal/audiobusio/I2SOut.c @@ -59,13 +59,13 @@ #define SERCTRL(name) I2S_SERCTRL_ ## name #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X #define SERCTRL(name) I2S_TXCTRL_ ## name #endif void i2sout_reset(void) { // Make sure the I2S peripheral is running so we can see if the resources we need are free. - #ifdef SAMD51 + #ifdef SAM_D5X_E5X // Connect the clock units to the 2mhz clock. It can't disable without it. connect_gclk_to_peripheral(5, I2S_GCLK_ID_0); connect_gclk_to_peripheral(5, I2S_GCLK_ID_1); @@ -76,7 +76,7 @@ void i2sout_reset(void) { } // Make sure the I2S peripheral is running so we can see if the resources we need are free. - #ifdef SAMD51 + #ifdef SAM_D5X_E5X // Connect the clock units to the 2mhz clock by default. They can't reset without it. disconnect_gclk_from_peripheral(5, I2S_GCLK_ID_0); disconnect_gclk_from_peripheral(5, I2S_GCLK_ID_1); @@ -132,7 +132,7 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, serializer = 1; } #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X // Only clock unit 0 can be used for transmission. if (bit_clock == &pin_PA10 || bit_clock == &pin_PB16) { // I2S SCK[0] bc_clock_unit = 0; @@ -170,14 +170,14 @@ void common_hal_audiobusio_i2sout_construct(audiobusio_i2sout_obj_t* self, mp_raise_RuntimeError(translate("Serializer in use")); } #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (I2S->CTRLA.bit.TXEN == 1) { mp_raise_RuntimeError(translate("Serializer in use")); } #endif } - #ifdef SAMD51 + #ifdef SAM_D5X_E5X #define GPIO_I2S_FUNCTION GPIO_PIN_FUNCTION_J #endif #ifdef SAMD21 @@ -254,7 +254,7 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, #ifdef SAMD21 uint32_t serctrl = (self->clock_unit << I2S_SERCTRL_CLKSEL_Pos) | SERCTRL(SERMODE_TX) | I2S_SERCTRL_TXSAME_SAME | I2S_SERCTRL_EXTEND_MSBIT | I2S_SERCTRL_TXDEFAULT_ONE | I2S_SERCTRL_SLOTADJ_LEFT; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X uint32_t serctrl = (self->clock_unit << I2S_RXCTRL_CLKSEL_Pos) | I2S_TXCTRL_TXSAME_SAME; #endif if (audiosample_channel_count(sample) == 1) { @@ -277,7 +277,7 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, #ifdef SAMD21 I2S->SERCTRL[self->serializer].reg = serctrl; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X I2S->TXCTRL.reg = serctrl; #endif @@ -291,7 +291,7 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, uint32_t tx_register = (uint32_t) &I2S->DATA[self->serializer].reg; uint8_t dmac_id = I2S_DMAC_ID_TX_0 + self->serializer; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X uint32_t tx_register = (uint32_t) &I2S->TXDATA.reg; uint8_t dmac_id = I2S_DMAC_ID_TX_0; #endif @@ -316,7 +316,7 @@ void common_hal_audiobusio_i2sout_play(audiobusio_i2sout_obj_t* self, I2S->CTRLA.vec.SEREN = 1 << self->serializer; while ((I2S->SYNCBUSY.vec.SEREN & (1 << self->serializer)) != 0) {} #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X I2S->CTRLA.bit.TXEN = 1; while (I2S->SYNCBUSY.bit.TXEN == 1) {} #endif @@ -333,7 +333,7 @@ void common_hal_audiobusio_i2sout_resume(audiobusio_i2sout_obj_t* self) { #ifdef SAMD21 I2S->INTFLAG.reg = I2S_INTFLAG_TXUR0 << self->serializer; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X I2S->INTFLAG.reg = I2S_INTFLAG_TXUR0 | I2S_INTFLAG_TXUR1; #endif @@ -351,7 +351,7 @@ void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t* self) { I2S->CTRLA.vec.SEREN &= ~(1 << self->serializer); while ((I2S->SYNCBUSY.vec.SEREN & (1 << self->serializer)) != 0) {} #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X I2S->CTRLA.bit.TXEN = 0; while (I2S->SYNCBUSY.bit.TXEN == 1) {} #endif @@ -368,7 +368,7 @@ void common_hal_audiobusio_i2sout_stop(audiobusio_i2sout_obj_t* self) { disconnect_gclk_from_peripheral(self->gclk, I2S_GCLK_ID_0 + self->clock_unit); disable_clock_generator(self->gclk); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X connect_gclk_to_peripheral(5, I2S_GCLK_ID_0 + self->clock_unit); #endif diff --git a/ports/atmel-samd/common-hal/audiobusio/PDMIn.c b/ports/atmel-samd/common-hal/audiobusio/PDMIn.c index a1e35a1dc..474512f5e 100644 --- a/ports/atmel-samd/common-hal/audiobusio/PDMIn.c +++ b/ports/atmel-samd/common-hal/audiobusio/PDMIn.c @@ -60,7 +60,7 @@ #define SERCTRL(name) I2S_SERCTRL_ ## name #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X #define SERCTRL(name) I2S_RXCTRL_ ## name #endif @@ -94,7 +94,7 @@ void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, self->clock_unit = 1; #endif #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (clock_pin == &pin_PA10 || clock_pin == &pin_PB16) { self->clock_unit = 0; } else if (clock_pin == &pin_PB12 @@ -122,7 +122,7 @@ void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, #endif self->serializer = 1; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (data_pin == &pin_PB10 || data_pin == &pin_PA22) { self->serializer = 1; #endif @@ -145,13 +145,13 @@ void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, mp_raise_RuntimeError(translate("Serializer in use")); } #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (I2S->CTRLA.bit.RXEN == 1) { mp_raise_RuntimeError(translate("Serializer in use")); } #endif } - #ifdef SAMD51 + #ifdef SAM_D5X_E5X #define GPIO_I2S_FUNCTION GPIO_PIN_FUNCTION_J #endif #ifdef SAMD21 @@ -185,7 +185,7 @@ void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, #ifdef SAMD21 uint32_t serctrl = (self->clock_unit << I2S_SERCTRL_CLKSEL_Pos) | SERCTRL(SERMODE_PDM2) | SERCTRL(DATASIZE_32); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X uint32_t serctrl = (self->clock_unit << I2S_RXCTRL_CLKSEL_Pos) | SERCTRL(SERMODE_PDM2) | SERCTRL(DATASIZE_32); #endif @@ -196,7 +196,7 @@ void common_hal_audiobusio_pdmin_construct(audiobusio_pdmin_obj_t* self, #ifdef SAMD21 I2S->SERCTRL[self->serializer].reg = serctrl; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X I2S->RXCTRL.reg = serctrl; #endif @@ -274,7 +274,7 @@ static void setup_dma(audiobusio_pdmin_obj_t* self, uint32_t length, #ifdef SAMD21 descriptor->SRCADDR.reg = (uint32_t)&I2S->DATA[self->serializer]; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X descriptor->SRCADDR.reg = (uint32_t)&I2S->RXDATA; #endif @@ -295,7 +295,7 @@ static void setup_dma(audiobusio_pdmin_obj_t* self, uint32_t length, #ifdef SAMD21 second_descriptor->SRCADDR.reg = (uint32_t)&I2S->DATA[self->serializer]; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X second_descriptor->SRCADDR.reg = (uint32_t)&I2S->RXDATA; #endif second_descriptor->BTCTRL.reg = DMAC_BTCTRL_VALID | @@ -400,7 +400,7 @@ uint32_t common_hal_audiobusio_pdmin_record_to_buffer(audiobusio_pdmin_obj_t* se #ifdef SAMD21 #define MAX_WAIT_COUNTS 1000 #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X #define MAX_WAIT_COUNTS 6000 #endif // If wait_counts exceeds the max count, buffer has probably stopped filling; diff --git a/ports/atmel-samd/common-hal/audioio/AudioOut.c b/ports/atmel-samd/common-hal/audioio/AudioOut.c index 75621b361..5cefba56f 100644 --- a/ports/atmel-samd/common-hal/audioio/AudioOut.c +++ b/ports/atmel-samd/common-hal/audioio/AudioOut.c @@ -74,7 +74,7 @@ static void ramp_value(uint16_t start, uint16_t end) { } #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X static void ramp_value(uint16_t start, uint16_t end) { int32_t diff = (int32_t) end - start; int32_t step = 49; @@ -104,7 +104,7 @@ void audioout_reset(void) { #ifdef SAMD21 while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {} #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X while (DAC->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) {} #endif if (DAC->CTRLA.bit.ENABLE) { @@ -118,7 +118,7 @@ void audioout_reset(void) { // Caller validates that pins are free. void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, const mcu_pin_obj_t* left_channel, const mcu_pin_obj_t* right_channel, uint16_t quiescent_value) { - #ifdef SAMD51 + #ifdef SAM_D5X_E5X bool dac_clock_enabled = hri_mclk_get_APBDMASK_DAC_bit(MCLK); #endif @@ -138,7 +138,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, } claim_pin(left_channel); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X self->right_channel = NULL; if (left_channel != &pin_PA02 && left_channel != &pin_PA05) { mp_raise_ValueError(translate("Invalid pin for left channel")); @@ -159,7 +159,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, self->left_channel = left_channel; audio_dma_init(&self->left_dma); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X hri_mclk_set_APBDMASK_DAC_bit(MCLK); #endif @@ -176,12 +176,12 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, DAC->CTRLA.bit.SWRST = 1; while (DAC->CTRLA.bit.SWRST == 1) {} // Make sure there are no outstanding access errors. (Reading DATA can cause this.) - #ifdef SAMD51 + #ifdef SAM_D5X_E5X PAC->INTFLAGD.reg = PAC_INTFLAGD_DAC; #endif bool channel0_enabled = true; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X channel0_enabled = self->left_channel == &pin_PA02 || self->right_channel == &pin_PA02; bool channel1_enabled = self->left_channel == &pin_PA05 || self->right_channel == &pin_PA05; #endif @@ -195,7 +195,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, DAC_CTRLB_EOEN | DAC_CTRLB_VPD; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; DAC->DACCTRL[0].reg = DAC_DACCTRL_CCTRL_CC100K | DAC_DACCTRL_ENABLE | @@ -203,7 +203,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU; #endif } - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (channel1_enabled) { DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; DAC->DACCTRL[1].reg = DAC_DACCTRL_CCTRL_CC100K | @@ -218,7 +218,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, #ifdef SAMD21 while (DAC->STATUS.bit.SYNCBUSY == 1) {} #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X while (DAC->SYNCBUSY.bit.ENABLE == 1) {} while (channel0_enabled && DAC->STATUS.bit.READY0 == 0) {} while (channel1_enabled && DAC->STATUS.bit.READY1 == 0) {} @@ -243,7 +243,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, // Use the 48mhz clocks on both the SAMD21 and 51 because we will be going much slower. uint8_t tc_gclk = 0; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc_gclk = 1; #endif @@ -253,7 +253,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, // Don't bother setting the period. We set it before you playback anything. tc_set_enable(t, false); tc_reset(t); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X t->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MFRQ; #endif #ifdef SAMD21 @@ -268,7 +268,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, #ifdef SAMD21 #define FIRST_TC_GEN_ID EVSYS_ID_GEN_TC3_OVF #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X #define FIRST_TC_GEN_ID EVSYS_ID_GEN_TC0_OVF #endif uint8_t tc_gen_id = FIRST_TC_GEN_ID + 3 * tc_index; @@ -282,7 +282,7 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self, mp_raise_RuntimeError(translate("All event channels in use")); } - #ifdef SAMD51 + #ifdef SAM_D5X_E5X connect_event_user_to_channel(EVSYS_ID_USER_DAC_START_1, channel); if (right_channel != NULL) { gpio_set_pin_function(self->right_channel->number, GPIO_PIN_FUNCTION_B); @@ -322,7 +322,7 @@ void common_hal_audioio_audioout_deinit(audioio_audioout_obj_t* self) { #ifdef SAMD21 while (DAC->STATUS.bit.SYNCBUSY == 1) {} #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X while (DAC->SYNCBUSY.bit.ENABLE == 1) {} #endif @@ -332,7 +332,7 @@ void common_hal_audioio_audioout_deinit(audioio_audioout_obj_t* self) { reset_pin_number(self->left_channel->number); self->left_channel = NULL; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X reset_pin_number(self->right_channel->number); self->right_channel = NULL; #endif @@ -369,7 +369,7 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self, #ifdef SAMD21 uint32_t max_sample_rate = 350000; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X uint32_t max_sample_rate = 1000000; #endif if (sample_rate > max_sample_rate) { @@ -382,7 +382,7 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self, DAC_DMAC_ID_EMPTY); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X uint32_t left_channel_reg = (uint32_t) &DAC->DATABUF[0].reg; uint8_t tc_trig_id = TC0_DMAC_ID_OVF + 3 * self->tc_index; uint8_t left_channel_trigger = tc_trig_id; @@ -416,7 +416,7 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self, #endif if (result != AUDIO_DMA_OK) { audio_dma_stop(&self->left_dma); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X audio_dma_stop(&self->right_dma); #endif if (result == AUDIO_DMA_DMA_BUSY) { @@ -434,7 +434,7 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self, void common_hal_audioio_audioout_pause(audioio_audioout_obj_t* self) { audio_dma_pause(&self->left_dma); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X audio_dma_pause(&self->right_dma); #endif } @@ -444,12 +444,12 @@ void common_hal_audioio_audioout_resume(audioio_audioout_obj_t* self) { #ifdef SAMD21 DAC->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X DAC->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_UNDERRUN1; #endif audio_dma_resume(&self->left_dma); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X audio_dma_resume(&self->right_dma); #endif } @@ -462,7 +462,7 @@ void common_hal_audioio_audioout_stop(audioio_audioout_obj_t* self) { Tc* timer = tc_insts[self->tc_index]; timer->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_STOP; audio_dma_stop(&self->left_dma); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X audio_dma_stop(&self->right_dma); #endif // Ramp the DAC to default. The start is ignored when the current value can be readback. diff --git a/ports/atmel-samd/common-hal/audioio/AudioOut.h b/ports/atmel-samd/common-hal/audioio/AudioOut.h index 56b6b75c8..956839969 100644 --- a/ports/atmel-samd/common-hal/audioio/AudioOut.h +++ b/ports/atmel-samd/common-hal/audioio/AudioOut.h @@ -36,7 +36,7 @@ typedef struct { mp_obj_base_t base; const mcu_pin_obj_t *left_channel; audio_dma_t left_dma; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X const mcu_pin_obj_t *right_channel; audio_dma_t right_dma; #endif diff --git a/ports/atmel-samd/common-hal/busio/UART.c b/ports/atmel-samd/common-hal/busio/UART.c index 9f740dc8a..b587eaaef 100644 --- a/ports/atmel-samd/common-hal/busio/UART.c +++ b/ports/atmel-samd/common-hal/busio/UART.c @@ -105,7 +105,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, continue; } #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X if (potential_sercom->USART.CTRLA.bit.ENABLE != 0 || !(tx->sercom[i].pad == 0)) { continue; diff --git a/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c b/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c index fcb3c0ce7..1952df563 100644 --- a/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c +++ b/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c @@ -54,7 +54,7 @@ static frequencyio_frequencyin_obj_t *active_frequencyins[TC_INST_NUM]; volatile uint8_t reference_tc = 0xff; -#ifdef SAMD51 +#ifdef SAM_D5X_E5X static uint8_t dpll_gclk; #endif @@ -67,7 +67,7 @@ void frequencyin_emergency_cancel_capture(uint8_t index) { NVIC_DisableIRQ(EIC_IRQn); NVIC_ClearPendingIRQ(EIC_IRQn); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X NVIC_DisableIRQ(EIC_0_IRQn + self->channel); NVIC_ClearPendingIRQ(EIC_0_IRQn + self->channel); #endif @@ -78,7 +78,7 @@ void frequencyin_emergency_cancel_capture(uint8_t index) { #ifdef SAMD21 NVIC_EnableIRQ(EIC_IRQn); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X NVIC_EnableIRQ(EIC_0_IRQn + self->channel); #endif mp_raise_RuntimeError(translate("Frequency captured is above capability. Capture Paused.")); @@ -107,7 +107,7 @@ void frequencyin_interrupt_handler(uint8_t index) { self->factor = (uint32_t) (current_ns - self->last_ns) / 1000000.0; self->last_ns = current_ns; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc->COUNT16.CTRLBSET.bit.CMD = TC_CTRLBSET_CMD_READSYNC_Val; while ((tc->COUNT16.SYNCBUSY.bit.COUNT == 1) || (tc->COUNT16.CTRLBSET.bit.CMD == TC_CTRLBSET_CMD_READSYNC_Val)) { @@ -121,7 +121,7 @@ void frequencyin_interrupt_handler(uint8_t index) { } self->frequency = new_freq; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc->COUNT16.CTRLBSET.bit.CMD = TC_CTRLBSET_CMD_RETRIGGER_Val; while ((tc->COUNT16.SYNCBUSY.bit.COUNT == 1) || (tc->COUNT16.CTRLBSET.bit.CMD == TC_CTRLBSET_CMD_RETRIGGER_Val)) { @@ -151,7 +151,7 @@ void frequencyin_reference_tc_init() { #endif // use the DPLL we setup so that the reference_tc and freqin_tc(s) // are using the same clock frequency. - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (dpll_gclk == 0xff) { frequencyin_samd51_start_dpll(); } @@ -168,7 +168,7 @@ void frequencyin_reference_tc_init() { tc->COUNT16.INTENSET.bit.OVF = 1; NVIC_EnableIRQ(TC3_IRQn + reference_tc); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 | TC_CTRLA_PRESCALER_DIV1; tc->COUNT16.INTENSET.bit.OVF = 1; @@ -192,7 +192,7 @@ void frequencyin_reference_tc_enable(bool enable) { tc_set_enable(tc, enable); } -#ifdef SAMD51 +#ifdef SAM_D5X_E5X void frequencyin_samd51_start_dpll() { if (clock_get_enabled(0, GCLK_SOURCE_DPLL1)) { return; @@ -259,7 +259,7 @@ void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t* #ifdef SAMD21 ((EIC->INTENSET.vec.EXTINT & mask) != 0 || (EIC->EVCTRL.vec.EXTINTEO & mask) != 0)) { #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X ((EIC->INTENSET.bit.EXTINT & mask) != 0 || (EIC->EVCTRL.bit.EXTINTEO & mask) != 0)) { #endif mp_raise_RuntimeError(translate("EXTINT channel already in use")); @@ -280,7 +280,7 @@ void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t* #ifdef SAMD21 self->TC_IRQ = TC3_IRQn + timer_index; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X self->TC_IRQ = TC0_IRQn + timer_index; #endif @@ -292,7 +292,7 @@ void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t* set_timer_handler(timer_index, 0, TC_HANDLER_NO_INTERRUPT); turn_on_clocks(true, timer_index, 0); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X frequencyin_samd51_start_dpll(); if (dpll_gclk == 0xff && !clock_get_enabled(0, GCLK_SOURCE_DPLL1)) { common_hal_frequencyio_frequencyin_deinit(self); @@ -318,7 +318,7 @@ void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t* masked_value = EIC->EVCTRL.vec.EXTINTEO; EIC->EVCTRL.vec.EXTINTEO = masked_value | (1 << self->channel); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X masked_value = EIC->EVCTRL.bit.EXTINTEO; EIC->EVCTRL.bit.EXTINTEO = masked_value | (1 << self->channel); EIC->ASYNCH.bit.ASYNCH = 1; @@ -334,7 +334,7 @@ void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t* #ifdef SAMD21 connect_event_user_to_channel((EVSYS_ID_USER_TC3_EVU + timer_index), evsys_channel); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X connect_event_user_to_channel((EVSYS_ID_USER_TC0_EVU + timer_index), evsys_channel); #endif init_async_event_channel(evsys_channel, (EVSYS_ID_GEN_EIC_EXTINT_0 + self->channel)); @@ -349,7 +349,7 @@ void common_hal_frequencyio_frequencyin_construct(frequencyio_frequencyin_obj_t* tc->COUNT16.EVCTRL.bit.EVACT = TC_EVCTRL_EVACT_COUNT_Val; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc->COUNT16.EVCTRL.reg = TC_EVCTRL_EVACT(TC_EVCTRL_EVACT_COUNT_Val) | TC_EVCTRL_TCEI; tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 | TC_CTRLA_PRESCALER_DIV1; @@ -393,7 +393,7 @@ void common_hal_frequencyio_frequencyin_deinit(frequencyio_frequencyin_obj_t* se uint32_t masked_value = EIC->EVCTRL.vec.EXTINTEO; EIC->EVCTRL.vec.EXTINTEO = masked_value ^ (1 << self->channel); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X disable_event_user(EVSYS_ID_USER_TC0_EVU + self->tc_index); uint32_t masked_value = EIC->EVCTRL.bit.EXTINTEO; EIC->EVCTRL.bit.EXTINTEO = masked_value ^ (1 << self->channel); @@ -427,7 +427,7 @@ void common_hal_frequencyio_frequencyin_deinit(frequencyio_frequencyin_obj_t* se if (!check_active) { frequencyin_reference_tc_enable(false); reference_tc = 0xff; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X frequencyin_samd51_stop_dpll(); #endif } @@ -438,7 +438,7 @@ uint32_t common_hal_frequencyio_frequencyin_get_item(frequencyio_frequencyin_obj #ifdef SAMD21 NVIC_DisableIRQ(EIC_IRQn); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X NVIC_DisableIRQ(EIC_0_IRQn + self->channel); #endif @@ -462,7 +462,7 @@ uint32_t common_hal_frequencyio_frequencyin_get_item(frequencyio_frequencyin_obj NVIC_ClearPendingIRQ(EIC_IRQn); NVIC_EnableIRQ(EIC_IRQn); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X NVIC_ClearPendingIRQ(EIC_0_IRQn + self->channel); NVIC_EnableIRQ(EIC_0_IRQn + self->channel); #endif @@ -481,7 +481,7 @@ void common_hal_frequencyio_frequencyin_pause(frequencyio_frequencyin_obj_t* sel uint32_t masked_value = EIC->EVCTRL.vec.EXTINTEO; EIC->EVCTRL.vec.EXTINTEO = masked_value ^ (1 << self->channel); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X uint32_t masked_value = EIC->EVCTRL.bit.EXTINTEO; EIC->EVCTRL.bit.EXTINTEO = masked_value ^ (1 << self->channel); #endif @@ -499,7 +499,7 @@ void common_hal_frequencyio_frequencyin_resume(frequencyio_frequencyin_obj_t* se uint32_t masked_value = EIC->EVCTRL.vec.EXTINTEO; EIC->EVCTRL.vec.EXTINTEO = masked_value | (1 << self->channel); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X uint32_t masked_value = EIC->EVCTRL.bit.EXTINTEO; EIC->EVCTRL.bit.EXTINTEO = masked_value | (1 << self->channel); #endif @@ -512,7 +512,7 @@ void common_hal_frequencyio_frequencyin_clear(frequencyio_frequencyin_obj_t* sel #ifdef SAMD21 NVIC_DisableIRQ(EIC_IRQn); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X NVIC_DisableIRQ(EIC_0_IRQn + self->channel); #endif @@ -524,7 +524,7 @@ void common_hal_frequencyio_frequencyin_clear(frequencyio_frequencyin_obj_t* sel NVIC_ClearPendingIRQ(EIC_IRQn); NVIC_EnableIRQ(EIC_IRQn); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X NVIC_ClearPendingIRQ(EIC_0_IRQn + self->channel); NVIC_EnableIRQ(EIC_0_IRQn + self->channel); #endif diff --git a/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.h b/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.h index 461fb661f..53b9f2d2d 100644 --- a/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.h +++ b/ports/atmel-samd/common-hal/frequencyio/FrequencyIn.h @@ -50,7 +50,7 @@ void frequencyin_emergency_cancel_capture(uint8_t index); void frequencyin_reference_tc_init(void); void frequencyin_reference_tc_enable(bool enable); bool frequencyin_reference_tc_enabled(void); -#ifdef SAMD51 +#ifdef SAM_D5X_E5X void frequencyin_samd51_start_dpll(void); void frequencyin_samd51_stop_dpll(void); #endif diff --git a/ports/atmel-samd/common-hal/microcontroller/Pin.c b/ports/atmel-samd/common-hal/microcontroller/Pin.c index 3c214a9f4..5ce077eb8 100644 --- a/ports/atmel-samd/common-hal/microcontroller/Pin.c +++ b/ports/atmel-samd/common-hal/microcontroller/Pin.c @@ -45,7 +45,7 @@ bool speaker_enable_in_use; #define PORT_COUNT (PORT_BITS / 32 + 1) -#ifdef SAMD51 +#ifdef SAM_D5X_E5X #define SWD_MUX GPIO_PIN_FUNCTION_H #endif #ifdef SAMD21 @@ -80,7 +80,7 @@ void reset_all_pins(void) { // Configure SWD. SWDIO will be automatically switched on PA31 when a signal is input on // SWCLK. - #ifdef SAMD51 + #ifdef SAM_D5X_E5X gpio_set_pin_function(PIN_PA30, MUX_PA30H_CM4_SWCLK); #endif #ifdef SAMD21 @@ -136,7 +136,7 @@ void reset_pin_number(uint8_t pin_number) { #endif if (pin_number == PIN_PA30 - #ifdef SAMD51 + #ifdef SAM_D5X_E5X ) { #endif #ifdef SAMD21 @@ -199,7 +199,7 @@ bool pin_number_is_free(uint8_t pin_number) { return false; } if (pin_number == PIN_PA30 - #ifdef SAMD51 + #ifdef SAM_D5X_E5X ) { #endif #ifdef SAMD21 diff --git a/ports/atmel-samd/common-hal/microcontroller/Processor.c b/ports/atmel-samd/common-hal/microcontroller/Processor.c index 2ca3ab30b..199f19354 100644 --- a/ports/atmel-samd/common-hal/microcontroller/Processor.c +++ b/ports/atmel-samd/common-hal/microcontroller/Processor.c @@ -163,7 +163,7 @@ STATIC float calculate_temperature(uint16_t raw_value) { } #endif // SAMD21 -#ifdef SAMD51 +#ifdef SAM_D5X_E5X STATIC float calculate_temperature(uint16_t TP, uint16_t TC) { uint32_t TLI = (*(uint32_t *)FUSES_ROOM_TEMP_VAL_INT_ADDR & FUSES_ROOM_TEMP_VAL_INT_Msk) >> FUSES_ROOM_TEMP_VAL_INT_Pos; uint32_t TLD = (*(uint32_t *)FUSES_ROOM_TEMP_VAL_DEC_ADDR & FUSES_ROOM_TEMP_VAL_DEC_Msk) >> FUSES_ROOM_TEMP_VAL_DEC_Pos; @@ -231,7 +231,7 @@ float common_hal_mcu_processor_get_temperature(void) { return calculate_temperature(value); #endif // SAMD21 -#ifdef SAMD51 +#ifdef SAM_D5X_E5X adc_sync_set_resolution(&adc, ADC_CTRLB_RESSEL_12BIT_Val); // Using INTVCC0 as the reference voltage. // INTVCC1 seems to read a little high. @@ -285,7 +285,7 @@ float common_hal_mcu_processor_get_voltage(void) { adc_sync_set_reference(&adc, ADC_REFCTRL_REFSEL_INT1V_Val); #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X hri_supc_set_VREF_SEL_bf(SUPC, SUPC_VREF_SEL_1V0_Val); hri_supc_set_VREF_VREFOE_bit(SUPC); @@ -332,7 +332,7 @@ void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { uint32_t* id_addresses[4] = {(uint32_t *) 0x0080A00C, (uint32_t *) 0x0080A040, (uint32_t *) 0x0080A044, (uint32_t *) 0x0080A048}; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X uint32_t* id_addresses[4] = {(uint32_t *) 0x008061FC, (uint32_t *) 0x00806010, (uint32_t *) 0x00806014, (uint32_t *) 0x00806018}; #endif diff --git a/ports/atmel-samd/common-hal/neopixel_write/__init__.c b/ports/atmel-samd/common-hal/neopixel_write/__init__.c index 5c79f72a4..43c8575cb 100644 --- a/ports/atmel-samd/common-hal/neopixel_write/__init__.c +++ b/ports/atmel-samd/common-hal/neopixel_write/__init__.c @@ -31,7 +31,10 @@ #include "supervisor/port.h" -#ifdef SAMD51 +#if defined(SAME54) +#include "hri/hri_cmcc_e54.h" +#include "hri/hri_nvmctrl_e54.h" +#elif defined(SAMD51) #include "hri/hri_cmcc_d51.h" #include "hri/hri_nvmctrl_d51.h" #endif @@ -53,7 +56,7 @@ static void neopixel_send_buffer_core(volatile uint32_t *clraddr, uint32_t pinMa #ifdef SAMD21 " movs r6, #3; d2: sub r6, #1; bne d2;" // delay 3 #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X " movs r6, #3; d2: subs r6, #1; bne d2;" // delay 3 #endif " tst r4, r5;" // mask&r5 @@ -63,14 +66,14 @@ static void neopixel_send_buffer_core(volatile uint32_t *clraddr, uint32_t pinMa #ifdef SAMD21 " movs r6, #6; d0: sub r6, #1; bne d0;" // delay 6 #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X " movs r6, #6; d0: subs r6, #1; bne d0;" // delay 6 #endif " str r1, [r0, #0];" // clr (possibly again, doesn't matter) #ifdef SAMD21 " asr r4, r4, #1;" // mask >>= 1 #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X " asrs r4, r4, #1;" // mask >>= 1 #endif " beq nextbyte;" @@ -78,7 +81,7 @@ static void neopixel_send_buffer_core(volatile uint32_t *clraddr, uint32_t pinMa #ifdef SAMD21 " movs r6, #2; d1: sub r6, #1; bne d1;" // delay 2 #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X " movs r6, #2; d1: subs r6, #1; bne d1;" // delay 2 #endif " b loopBit;" @@ -108,7 +111,7 @@ void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout, mp_hal_disable_all_interrupts(); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X // When this routine is positioned at certain addresses, the timing logic // below can be too fast by about 2.5x. This is some kind of (un)fortunate code // positioning with respect to a cache line. @@ -135,7 +138,7 @@ void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout, volatile uint32_t *clr = &(port->OUTCLR.reg); neopixel_send_buffer_core(clr, pinMask, pixels, numBytes); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X // Turn instruction, data, and NVM caches back on. hri_cmcc_clear_CFG_reg(CMCC, CMCC_CFG_DCDIS | CMCC_CFG_ICDIS); hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(NVMCTRL); diff --git a/ports/atmel-samd/common-hal/os/__init__.c b/ports/atmel-samd/common-hal/os/__init__.c index eeba29dfa..c151b105a 100644 --- a/ports/atmel-samd/common-hal/os/__init__.c +++ b/ports/atmel-samd/common-hal/os/__init__.c @@ -30,7 +30,7 @@ #include "py/objtuple.h" #include "py/qstr.h" -#ifdef SAMD51 +#ifdef SAM_D5X_E5X #include "hal/include/hal_rand_sync.h" #endif @@ -42,7 +42,7 @@ STATIC const qstr os_uname_info_fields[] = { STATIC const MP_DEFINE_STR_OBJ(os_uname_info_sysname_obj, "samd21"); STATIC const MP_DEFINE_STR_OBJ(os_uname_info_nodename_obj, "samd21"); #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X STATIC const MP_DEFINE_STR_OBJ(os_uname_info_sysname_obj, "samd51"); STATIC const MP_DEFINE_STR_OBJ(os_uname_info_nodename_obj, "samd51"); #endif @@ -67,7 +67,7 @@ mp_obj_t common_hal_os_uname(void) { } bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) { - #ifdef SAMD51 + #ifdef SAM_D5X_E5X hri_mclk_set_APBCMASK_TRNG_bit(MCLK); struct rand_sync_desc random; rand_sync_init(&random, TRNG); diff --git a/ports/atmel-samd/common-hal/pulseio/PWMOut.c b/ports/atmel-samd/common-hal/pulseio/PWMOut.c index b627dadc5..752f6c214 100644 --- a/ports/atmel-samd/common-hal/pulseio/PWMOut.c +++ b/ports/atmel-samd/common-hal/pulseio/PWMOut.c @@ -55,7 +55,7 @@ uint8_t tcc_refcount[TCC_INST_NUM]; #ifdef SAMD21 uint8_t tcc_channels[3]; // Set by pwmout_reset() to {0xf0, 0xfc, 0xfc} initially. #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X uint8_t tcc_channels[5]; // Set by pwmout_reset() to {0xc0, 0xf0, 0xf8, 0xfc, 0xfc} initially. #endif @@ -148,7 +148,7 @@ pwmout_result_t common_hal_pulseio_pwmout_construct(pulseio_pwmout_obj_t* self, if (pin->timer[0].index >= TC_INST_NUM && pin->timer[1].index >= TCC_INST_NUM -#ifdef SAMD51 +#ifdef SAM_D5X_E5X && pin->timer[2].index >= TCC_INST_NUM #endif ) { @@ -260,7 +260,7 @@ pwmout_result_t common_hal_pulseio_pwmout_construct(pulseio_pwmout_obj_t* self, TC_CTRLA_WAVEGEN_MPWM; tc->COUNT16.CC[0].reg = top; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc->COUNT16.CTRLA.bit.SWRST = 1; while (tc->COUNT16.CTRLA.bit.SWRST == 1) { @@ -345,7 +345,7 @@ extern void common_hal_pulseio_pwmout_set_duty_cycle(pulseio_pwmout_obj_t* self, #ifdef SAMD21 tc_insts[t->index]->COUNT16.CC[t->wave_output].reg = adjusted_duty; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X Tc* tc = tc_insts[t->index]; while (tc->COUNT16.SYNCBUSY.bit.CC1 != 0) {} tc->COUNT16.CCBUF[1].reg = adjusted_duty; @@ -366,7 +366,7 @@ extern void common_hal_pulseio_pwmout_set_duty_cycle(pulseio_pwmout_obj_t* self, #ifdef SAMD21 tcc->CCB[channel].reg = adjusted_duty; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tcc->CCBUF[channel].reg = adjusted_duty; #endif tcc->CTRLBCLR.bit.LUPD = 1; @@ -396,7 +396,7 @@ uint16_t common_hal_pulseio_pwmout_get_duty_cycle(pulseio_pwmout_obj_t* self) { cv = tcc->CC[channel].reg; } #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if ((tcc->STATUS.vec.CCBUFV & (1 << channel)) != 0) { cv = tcc->CCBUF[channel].reg; } else { @@ -444,7 +444,7 @@ void common_hal_pulseio_pwmout_set_frequency(pulseio_pwmout_obj_t* self, #ifdef SAMD21 tc->COUNT16.CC[0].reg = new_top; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X while (tc->COUNT16.SYNCBUSY.reg != 0) {} tc->COUNT16.CCBUF[0].reg = new_top; #endif @@ -461,7 +461,7 @@ void common_hal_pulseio_pwmout_set_frequency(pulseio_pwmout_obj_t* self, #ifdef SAMD21 tcc->PERB.bit.PERB = new_top; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tcc->PERBUF.bit.PERBUF = new_top; #endif } diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c index 508ee8d38..7ea20321b 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c @@ -79,7 +79,7 @@ void pulsein_interrupt_handler(uint8_t channel) { // Grab the current time first. uint32_t current_overflow = overflow_count; Tc* tc = tc_insts[pulsein_tc_index]; - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC; while (tc->COUNT16.SYNCBUSY.bit.COUNT == 1 || tc->COUNT16.CTRLBSET.bit.CMD == TC_CTRLBSET_CMD_READSYNC_Val) {} @@ -173,7 +173,7 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, // We use GCLK0 for SAMD21 which is 48MHz. We prescale it to 3MHz. turn_on_clocks(true, index, 0); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X // We use GCLK5 for SAMD51 because it runs at 2MHz and we can use it for a 1MHz clock, // 1us per tick. turn_on_clocks(true, index, 5); @@ -185,7 +185,7 @@ void common_hal_pulseio_pulsein_construct(pulseio_pulsein_obj_t* self, TC_CTRLA_PRESCALER_DIV16 | TC_CTRLA_WAVEGEN_NFRQ; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc_reset(tc); tc_set_enable(tc, false); tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 | TC_CTRLA_PRESCALER_DIV2; diff --git a/ports/atmel-samd/common-hal/pulseio/PulseOut.c b/ports/atmel-samd/common-hal/pulseio/PulseOut.c index 8b8bc6dc6..5c829f84d 100644 --- a/ports/atmel-samd/common-hal/pulseio/PulseOut.c +++ b/ports/atmel-samd/common-hal/pulseio/PulseOut.c @@ -119,7 +119,7 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, #ifdef SAMD21 turn_on_clocks(true, index, 0); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X turn_on_clocks(true, index, 1); #endif @@ -129,7 +129,7 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self, TC_CTRLA_PRESCALER_DIV64 | TC_CTRLA_WAVEGEN_NFRQ; #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X tc_reset(tc); tc_set_enable(tc, false); tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 | TC_CTRLA_PRESCALER_DIV64; diff --git a/ports/atmel-samd/mpconfigport.h b/ports/atmel-samd/mpconfigport.h index 1aa305cd3..354097ce4 100644 --- a/ports/atmel-samd/mpconfigport.h +++ b/ports/atmel-samd/mpconfigport.h @@ -65,13 +65,17 @@ //////////////////////////////////////////////////////////////////////////////////////////////////// -#ifdef SAMD51 +#ifdef SAM_D5X_E5X -// HSRAM_SIZE is defined in the ASF4 include files for each SAMD51 chip. +// HSRAM_SIZE is defined in the ASF4 include files for each SAM_D5X_E5X chip. #define RAM_SIZE HSRAM_SIZE #define BOOTLOADER_SIZE (16*1024) #define CIRCUITPY_MCU_FAMILY samd51 +#ifdef SAMD51 #define MICROPY_PY_SYS_PLATFORM "MicroChip SAMD51" +#elif defined(SAME54) +#define MICROPY_PY_SYS_PLATFORM "MicroChip SAME54" +#endif #define SPI_FLASH_MAX_BAUDRATE 24000000 #define MICROPY_PY_BUILTINS_NOTIMPLEMENTED (1) #define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1) @@ -81,7 +85,7 @@ #define MICROPY_PY_UJSON (1) // MICROPY_PY_UERRNO_LIST - Use the default -#endif // SAMD51 +#endif // SAM_D5X_E5X //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -115,7 +119,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////////// -#ifdef SAMD51 +#ifdef SAM_D5X_E5X #ifndef CIRCUITPY_INTERNAL_NVM_SIZE #define CIRCUITPY_INTERNAL_NVM_SIZE (8192) @@ -137,7 +141,7 @@ #define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0) #endif -#endif // SAMD51 +#endif // SAM_D5X_E5X //////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/ports/atmel-samd/mphalport.c b/ports/atmel-samd/mphalport.c index 23a9b4330..b497b89cd 100644 --- a/ports/atmel-samd/mphalport.c +++ b/ports/atmel-samd/mphalport.c @@ -58,7 +58,7 @@ extern uint32_t common_hal_mcu_processor_get_frequency(void); #ifdef SAMD21 #define DELAY_LOOP_ITERATIONS_PER_US ( (10U*48000000U) / common_hal_mcu_processor_get_frequency()) #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X #define DELAY_LOOP_ITERATIONS_PER_US ( (30U*120000000U) / common_hal_mcu_processor_get_frequency()) #endif diff --git a/ports/atmel-samd/peripherals b/ports/atmel-samd/peripherals -Subproject 6b531fc923d9f02b14bd731a5f584ddf716e877 +Subproject e4161d7d6d98d78eddcccb82128856af4baf7e5 diff --git a/ports/atmel-samd/supervisor/internal_flash.c b/ports/atmel-samd/supervisor/internal_flash.c index 9c8ff990e..091959c4e 100644 --- a/ports/atmel-samd/supervisor/internal_flash.c +++ b/ports/atmel-samd/supervisor/internal_flash.c @@ -39,6 +39,12 @@ #ifdef SAMD21 #include "hpl/pm/hpl_pm_base.h" #endif +#ifdef SAME54 +#include "hri/hri_mclk_e54.h" +#endif +#ifdef SAMD51 +#include "hri/hri_mclk_d51.h" +#endif #include "hal/include/hal_flash.h" #include "supervisor/flash.h" @@ -57,7 +63,7 @@ void supervisor_flash_init(void) { port_pin_set_output_level(MICROPY_HW_LED_MSC, false); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X hri_mclk_set_AHBMASK_NVMCTRL_bit(MCLK); #endif #ifdef SAMD21 diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 74c984997..48bd3211b 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -40,11 +40,14 @@ #include "hpl/gclk/hpl_gclk_base.h" #include "hpl/pm/hpl_pm_base.h" -#ifdef SAMD21 +#if defined(SAMD21) #include "hri/hri_pm_d21.h" -#endif -#ifdef SAMD51 +#elif defined(SAME54) +#include "hri/hri_rstc_e54.h" +#elif defined(SAMD51) #include "hri/hri_rstc_d51.h" +#else +#error Unknown chip family #endif #include "common-hal/analogio/AnalogIn.h" @@ -146,7 +149,7 @@ static void rtc_init(void) { RTC_MODE0_CTRL_MODE_COUNT32 | RTC_MODE0_CTRL_PRESCALER_DIV2; #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X hri_mclk_set_APBAMASK_RTC_bit(MCLK); RTC->MODE0.CTRLA.bit.SWRST = true; while (RTC->MODE0.SYNCBUSY.bit.SWRST != 0) {} @@ -169,7 +172,7 @@ static void rtc_init(void) { NVIC_SetPriority(USB_IRQn, 1); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X NVIC_SetPriority(USB_0_IRQn, 1); NVIC_SetPriority(USB_1_IRQn, 1); NVIC_SetPriority(USB_2_IRQn, 1); @@ -204,7 +207,7 @@ safe_mode_t port_init(void) { #endif #endif -#if defined(SAMD51) +#if defined(SAM_D5X_E5X) // Set brownout detection to ~2.7V. Default from factory is 1.7V, // which is too low for proper operation of external SPI flash chips (they are 2.7-3.6V). // Disable while changing level. @@ -283,7 +286,7 @@ safe_mode_t port_init(void) { return BROWNOUT; } #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X if (RSTC->RCAUSE.bit.BODVDD == 1 || RSTC->RCAUSE.bit.BODCORE == 1) { return BROWNOUT; } @@ -341,7 +344,7 @@ void reset_port(void) { // Output clocks for debugging. // not supported by SAMD51G; uncomment for SAMD51J or update for 51G - // #ifdef SAMD51 + // #ifdef SAM_D5X_E5X // gpio_set_pin_function(PIN_PA10, GPIO_PIN_FUNCTION_M); // GCLK4, D3 // gpio_set_pin_function(PIN_PA11, GPIO_PIN_FUNCTION_M); // GCLK5, A4 // gpio_set_pin_function(PIN_PB14, GPIO_PIN_FUNCTION_M); // GCLK0, D5 @@ -388,7 +391,7 @@ uint32_t *port_heap_get_top(void) { #ifdef SAMD21 uint32_t* safe_word = (uint32_t*) (HMCRAMC0_ADDR + HMCRAMC0_SIZE - 0x2000); #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X uint32_t* safe_word = (uint32_t*) (HSRAM_ADDR + HSRAM_SIZE - 0x2000); #endif @@ -412,7 +415,7 @@ void RTC_Handler(void) { // Our RTC is 32 bits and we're clocking it at 16.384khz which is 16 (2 ** 4) subticks per // tick. overflowed_ticks += (1L<< (32 - 4)); - #ifdef SAMD51 + #ifdef SAM_D5X_E5X } else if (intflag & RTC_MODE0_INTFLAG_PER2) { RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; // Do things common to all ports when the tick occurs @@ -431,14 +434,14 @@ void RTC_Handler(void) { } } #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X RTC->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0; #endif } } static uint32_t _get_count(void) { - #ifdef SAMD51 + #ifdef SAM_D5X_E5X while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) {} #endif #ifdef SAMD21 @@ -459,7 +462,7 @@ uint64_t port_get_raw_ticks(uint8_t* subticks) { // Enable 1/1024 second tick. void port_enable_tick(void) { - #ifdef SAMD51 + #ifdef SAM_D5X_E5X // PER2 will generate an interrupt every 32 ticks of the source 32.768 clock. RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; #endif @@ -471,7 +474,7 @@ void port_enable_tick(void) { // Disable 1/1024 second tick. void port_disable_tick(void) { - #ifdef SAMD51 + #ifdef SAM_D5X_E5X RTC->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_PER2; #endif #ifdef SAMD21 @@ -492,7 +495,7 @@ void port_interrupt_after_ticks(uint32_t ticks) { } void port_sleep_until_interrupt(void) { - #ifdef SAMD51 + #ifdef SAM_D5X_E5X // Clear the FPU interrupt because it can prevent us from sleeping. if (__get_FPSCR() & ~(0x9f)) { __set_FPSCR(__get_FPSCR() & ~(0x9f)); diff --git a/ports/atmel-samd/supervisor/same54_cpu.s b/ports/atmel-samd/supervisor/same54_cpu.s new file mode 100755 index 000000000..9e6807a5e --- /dev/null +++ b/ports/atmel-samd/supervisor/same54_cpu.s @@ -0,0 +1,27 @@ +.syntax unified +.cpu cortex-m4 +.thumb +.text +.align 2 + +@ uint cpu_get_regs_and_sp(r0=uint regs[10]) +.global cpu_get_regs_and_sp +.thumb +.thumb_func +.type cpu_get_regs_and_sp, %function +cpu_get_regs_and_sp: +@ store registers into given array +str r4, [r0], #4 +str r5, [r0], #4 +str r6, [r0], #4 +str r7, [r0], #4 +str r8, [r0], #4 +str r9, [r0], #4 +str r10, [r0], #4 +str r11, [r0], #4 +str r12, [r0], #4 +str r13, [r0], #4 + +@ return the sp +mov r0, sp +bx lr diff --git a/ports/atmel-samd/supervisor/usb.c b/ports/atmel-samd/supervisor/usb.c index b8a94790d..650ed6a39 100644 --- a/ports/atmel-samd/supervisor/usb.c +++ b/ports/atmel-samd/supervisor/usb.c @@ -37,7 +37,7 @@ void init_usb_hardware(void) { _gclk_enable_channel(USB_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); hri_mclk_set_AHBMASK_USB_bit(MCLK); hri_mclk_set_APBBMASK_USB_bit(MCLK); @@ -53,7 +53,7 @@ void init_usb_hardware(void) { gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); #endif - #ifdef SAMD51 + #ifdef SAM_D5X_E5X gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM); gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP); #endif @@ -65,7 +65,7 @@ void USB_Handler(void) { } #endif -#ifdef SAMD51 +#ifdef SAM_D5X_E5X void USB_0_Handler (void) { tud_int_handler(0); } |