diff options
Diffstat (limited to 'supervisor/shared/external_flash')
| -rw-r--r-- | supervisor/shared/external_flash/common_commands.h | 1 | ||||
| -rw-r--r-- | supervisor/shared/external_flash/devices.h | 249 | ||||
| -rw-r--r-- | supervisor/shared/external_flash/external_flash.c | 139 | ||||
| -rw-r--r-- | supervisor/shared/external_flash/external_flash.h | 2 | ||||
| -rw-r--r-- | supervisor/shared/external_flash/spi_flash.c | 34 |
5 files changed, 362 insertions, 63 deletions
diff --git a/supervisor/shared/external_flash/common_commands.h b/supervisor/shared/external_flash/common_commands.h index cc0da2175..2eaa84833 100644 --- a/supervisor/shared/external_flash/common_commands.h +++ b/supervisor/shared/external_flash/common_commands.h @@ -43,5 +43,6 @@ #define CMD_QUAD_READ 0x6b #define CMD_ENABLE_RESET 0x66 #define CMD_RESET 0x99 +#define CMD_WAKE 0xab #endif // MICROPY_INCLUDED_ATMEL_SAMD_EXTERNAL_FLASH_COMMON_COMMANDS_H diff --git a/supervisor/shared/external_flash/devices.h b/supervisor/shared/external_flash/devices.h index 8d8574c47..466ab49eb 100644 --- a/supervisor/shared/external_flash/devices.h +++ b/supervisor/shared/external_flash/devices.h @@ -64,9 +64,18 @@ typedef struct { // True when the status register is a single byte. This implies the Quad Enable bit is in the // first byte and the Read Status Register 2 command (0x35) is unsupported. bool single_status_byte: 1; + + // Does not support using a ready bit within the status register + bool no_ready_bit: 1; + + // Does not support the erase command (0x20) + bool no_erase_cmd: 1; + + // Device does not have a reset command + bool no_reset_cmd: 1; } external_flash_device; -// Settings for the Adesto Tech AT25DF081A 1MiB SPI flash. Its on the SAMD21 +// Settings for the Adesto Tech AT25DF081A 1MiB SPI flash. It's on the SAMD21 // Xplained board. // Datasheet: https://www.adestotech.com/wp-content/uploads/doc8715.pdf #define AT25DF081A {\ @@ -85,6 +94,45 @@ typedef struct { .single_status_byte = false, \ } +// Settings for the Adesto Tech AT25SF161-SSHD-T 2MiB SPI flash +// for the StringCar M0 (SAMD21) Express board. +// Source: https://www.digikey.com/product-detail/en/adesto-technologies/AT25SF161-SDHD-T/1265-1230-1-ND/ +// Datasheet: https://www.adestotech.com/wpo-content/uploads/jDS-AT25SF161_046.pdf +#define AT25SF161 {\ + .total_size = (1 << 21), /* 2 MiB */ \ + .start_up_time_us = 10000, \ + .manufacturer_id = 0x1f, \ + .memory_type = 0x86, \ + .capacity = 0x01, \ + .max_clock_speed_mhz = 85, \ + .quad_enable_bit_mask = 0x00, \ + .has_sector_protection = true, \ + .supports_fast_read = true, \ + .supports_qspi = false, \ + .supports_qspi_writes = false, \ + .write_status_register_split = false, \ + .single_status_byte = false, \ +} + +// Settings for the Adesto Tech AT25SF041 1MiB SPI flash. It's on the SparkFun +// SAMD51 Thing Plus board +// Datasheet: https://www.adestotech.com/wp-content/uploads/DS-AT25SF041_044.pdf +#define AT25SF041A {\ + .total_size = (1 << 19), /* 512 KiB */ \ + .start_up_time_us = 10000, \ + .manufacturer_id = 0x1f, \ + .memory_type = 0x84, \ + .capacity = 0x01, \ + .max_clock_speed_mhz = 85, \ + .quad_enable_bit_mask = 0x00, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = false, \ + .supports_qspi_writes = false, \ + .write_status_register_split = false, \ + .single_status_byte = false, \ +} + // Settings for the Gigadevice GD25Q16C 2MiB SPI flash. // Datasheet: http://www.gigadevice.com/datasheet/gd25q16c/ #define GD25Q16C {\ @@ -103,6 +151,24 @@ typedef struct { .single_status_byte = false, \ } +// Settings for the Gigadevice GD25Q32C 4MiB SPI flash. +// Datasheet: http://www.elm-tech.com/en/products/spi-flash-memory/gd25q32/gd25q32.pdf +#define GD25Q32C {\ + .total_size = (1 << 22), /* 4 MiB */ \ + .start_up_time_us = 5000, \ + .manufacturer_id = 0xc8, \ + .memory_type = 0x40, \ + .capacity = 0x16, \ + .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \ + .quad_enable_bit_mask = 0x02, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = true, \ + .write_status_register_split = true, \ + .single_status_byte = false, \ +} + // Settings for the Gigadevice GD25Q64C 8MiB SPI flash. // Datasheet: http://www.elm-tech.com/en/products/spi-flash-memory/gd25q64/gd25q64.pdf #define GD25Q64C {\ @@ -121,6 +187,24 @@ typedef struct { .single_status_byte = false, \ } +// Settings for the Gigadevice GD25S512MD 64MiB SPI flash. +// Datasheet: http://www.gigadevice.com/datasheet/gd25s512md/ +#define GD25S512MD {\ + .total_size = (1 << 26), /* 64 MiB */ \ + .start_up_time_us = 5000, \ + .manufacturer_id = 0xc8, \ + .memory_type = 0x40, \ + .capacity = 0x19, \ + .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \ + .quad_enable_bit_mask = 0x02, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = true, \ + .write_status_register_split = true, \ + .single_status_byte = false, \ +} + // Settings for the Cypress (was Spansion) S25FL064L 8MiB SPI flash. // Datasheet: http://www.cypress.com/file/316661/download #define S25FL064L {\ @@ -262,6 +346,23 @@ typedef struct { .write_status_register_split = false, \ } +// Settings for the Winbond W25Q32JV-IQ 4MiB SPI flash. +// Datasheet: https://www.mouser.com/datasheet/2/949/w25q32jv_revg_03272018_plus-1489806.pdf +#define W25Q32JV_IQ {\ + .total_size = (1 << 22), /* 4 MiB */ \ + .start_up_time_us = 5000, \ + .manufacturer_id = 0xef, \ + .memory_type = 0x40, \ + .capacity = 0x16, \ + .max_clock_speed_mhz = 133, \ + .quad_enable_bit_mask = 0x02, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = true, \ + .write_status_register_split = false, \ +} + // Settings for the Winbond W25Q64JV-IM 8MiB SPI flash. Note that JV-IQ has a different .memory_type (0x40) // Datasheet: http://www.winbond.com/resource-files/w25q64jv%20revj%2003272018%20plus.pdf #define W25Q64JV_IM {\ @@ -316,6 +417,23 @@ typedef struct { .single_status_byte = false, \ } +// Settings for the Winbond W25Q80DV 1MiB SPI flash.. Note that W25Q80DL has a different memory type (0x60) +// Datasheet: https://www.winbond.com/resource-files/w25q80dv%20dl_revh_10022015.pdf +#define W25Q80DV {\ + .total_size = (1 << 20), /* 1 MiB */ \ + .start_up_time_us = 5000, \ + .manufacturer_id = 0xef, \ + .memory_type = 0x40, \ + .capacity = 0x14, \ + .max_clock_speed_mhz = 104, \ + .quad_enable_bit_mask = 0x02, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = false, \ + .write_status_register_split = false, \ + .single_status_byte = false, \ +} // Settings for the Winbond W25Q128JV-SQ 16MiB SPI flash. Note that JV-IM has a different .memory_type (0x70) // Datasheet: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf @@ -335,6 +453,63 @@ typedef struct { .single_status_byte = false, \ } +// Settings for the Everspin MR20H40 / MR25H40 magnetic non-volatile RAM +// Datasheet: https://www.everspin.com/supportdocs/MR25H40CDFR +#define MR2xH40 {\ + .total_size = (1 << 22), /* 4 MiB */ \ + .start_up_time_us = 10000, \ + .manufacturer_id = 0xef, /*no JDEC*/ \ + .memory_type = 0x40, /*no JDEC*/ \ + .capacity = 0x14, /*no JDEC*/ \ + .max_clock_speed_mhz = 10, \ + .quad_enable_bit_mask = 0x00, \ + .has_sector_protection = false, \ + .supports_fast_read = false, \ + .supports_qspi = false, \ + .supports_qspi_writes = false, \ + .write_status_register_split = false, \ + .single_status_byte = true, \ + .no_ready_bit = true, \ + .no_erase_cmd = true, \ + .no_reset_cmd = true, \ +} + +// Settings for the Macronix MX25L1606 2MiB SPI flash. +// Datasheet: +#define MX25L1606 {\ + .total_size = (1 << 21), /* 2 MiB */ \ + .start_up_time_us = 5000, \ + .manufacturer_id = 0xc2, \ + .memory_type = 0x20, \ + .capacity = 0x15, \ + .max_clock_speed_mhz = 8, \ + .quad_enable_bit_mask = 0x40, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = true, \ + .write_status_register_split = false, \ + .single_status_byte = true, \ +} + +// Settings for the Macronix MX25L3233F 4MiB SPI flash. +// Datasheet: http://www.macronix.com/Lists/Datasheet/Attachments/7426/MX25L3233F,%203V,%2032Mb,%20v1.6.pdf +#define MX25L3233F {\ + .total_size = (1 << 22), /* 4 MiB */ \ + .start_up_time_us = 5000, \ + .manufacturer_id = 0xc2, \ + .memory_type = 0x20, \ + .capacity = 0x16, \ + .max_clock_speed_mhz = 133, \ + .quad_enable_bit_mask = 0x40, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = true, \ + .write_status_register_split = false, \ + .single_status_byte = true, \ +} + // Settings for the Macronix MX25R6435F 8MiB SPI flash. // Datasheet: http://www.macronix.com/Lists/Datasheet/Attachments/7428/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.4.pdf // By default its in lower power mode which can only do 8mhz. In high power mode it can do 80mhz. @@ -354,6 +529,43 @@ typedef struct { .single_status_byte = true, \ } +// Settings for the Macronix MX25R1635F 8MiB SPI flash. +// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7595/MX25R1635F,%20Wide%20Range,%2016Mb,%20v1.6.pdf +// In low power mode, quad operations can only run at 8 MHz. +#define MX25R1635F {\ + .total_size = (1 << 21), /* 2 MiB */ \ + .start_up_time_us = 800, \ + .manufacturer_id = 0xc2, \ + .memory_type = 0x28, \ + .capacity = 0x18, \ + .max_clock_speed_mhz = 33, /* 8 mhz for dual/quad */ \ + .quad_enable_bit_mask = 0x80, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = true, \ + .write_status_register_split = false, \ + .single_status_byte = true, \ +} + +// Settings for the Macronix MX25L51245G 64MiB SPI flash. +// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7437/MX25L51245G,%203V,%20512Mb,%20v1.6.pdf +#define MX25L51245G {\ + .total_size = (1 << 26), /* 64 MiB */ \ + .start_up_time_us = 5000, \ + .manufacturer_id = 0xc2, \ + .memory_type = 0x20, \ + .capacity = 0x1a, \ + .max_clock_speed_mhz = 133, \ + .quad_enable_bit_mask = 0x40, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = true, \ + .write_status_register_split = false, \ + .single_status_byte = true, \ +} + // Settings for the Winbond W25Q128JV-PM 16MiB SPI flash. Note that JV-IM has a different .memory_type (0x70) // Datasheet: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf #define W25Q128JV_PM {\ @@ -371,4 +583,39 @@ typedef struct { .write_status_register_split = false, \ } +// Settings for the Winbond W25Q32FV 4MiB SPI flash. +// Datasheet:http://www.winbond.com/resource-files/w25q32fv%20revj%2006032016.pdf?__locale=en +#define W25Q32FV {\ + .total_size = (1 << 22), /* 4 MiB */ \ + .start_up_time_us = 5000, \ + .manufacturer_id = 0xef, \ + .memory_type = 0x40, \ + .capacity = 0x16, \ + .max_clock_speed_mhz = 104, \ + .quad_enable_bit_mask = 0x00, \ + .has_sector_protection = false, \ + .supports_fast_read = true, \ + .supports_qspi = false, \ + .supports_qspi_writes = false, \ + .write_status_register_split = false, \ + .single_status_byte = false, \ +} + +// Settings for the ISSI IS25LP128F 16MiB SPI flash. +// Datasheet: http://www.issi.com/WW/pdf/25LP-WP128F.pdf +#define IS25LP128F {\ + .total_size = (1 << 24), /* 16 MiB */ \ + .start_up_time_us = 10000, \ + .manufacturer_id = 0x9d, \ + .memory_type = 0x60, \ + .capacity = 0x18, \ + .max_clock_speed_mhz = 133, \ + .quad_enable_bit_mask = 0x02, \ + .has_sector_protection = true, \ + .supports_fast_read = true, \ + .supports_qspi = true, \ + .supports_qspi_writes = true, \ + .write_status_register_split = false, \ + .single_status_byte = true, \ +} #endif // MICROPY_INCLUDED_ATMEL_SAMD_EXTERNAL_FLASH_DEVICES_H diff --git a/supervisor/shared/external_flash/external_flash.c b/supervisor/shared/external_flash/external_flash.c index 73b7f7f91..5bde7fd48 100644 --- a/supervisor/shared/external_flash/external_flash.c +++ b/supervisor/shared/external_flash/external_flash.c @@ -23,11 +23,11 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include "external_flash.h" +#include "supervisor/shared/external_flash/external_flash.h" #include <stdint.h> #include <string.h> - +#include "supervisor/flash.h" #include "supervisor/spi_flash_api.h" #include "supervisor/shared/external_flash/common_commands.h" #include "extmod/vfs.h" @@ -57,9 +57,13 @@ static supervisor_allocation* supervisor_cache = NULL; // Wait until both the write enable and write in progress bits have cleared. static bool wait_for_flash_ready(void) { - uint8_t read_status_response[1] = {0x00}; bool ok = true; // Both the write enable and write in progress bits should be low. + if (flash_device->no_ready_bit){ + // For NVM without a ready bit in status register + return ok; + } + uint8_t read_status_response[1] = {0x00}; do { ok = spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1); } while (ok && (read_status_response[0] & 0x3) != 0); @@ -91,15 +95,18 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len } // Don't bother writing if the data is all 1s. Thats equivalent to the flash // state after an erase. - bool all_ones = true; - for (uint16_t i = 0; i < data_length; i++) { - if (data[i] != 0xff) { - all_ones = false; - break; + if (!flash_device->no_erase_cmd){ + // Only do this if the device has an erase command + bool all_ones = true; + for (uint16_t i = 0; i < data_length; i++) { + if (data[i] != 0xff) { + all_ones = false; + break; + } + } + if (all_ones) { + return true; } - } - if (all_ones) { - return true; } for (uint32_t bytes_written = 0; @@ -120,6 +127,10 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len static bool page_erased(uint32_t sector_address) { // Check the first few bytes to catch the common case where there is data // without using a bunch of memory. + if (flash_device->no_erase_cmd){ + // skip this if device doesn't have an erase command. + return true; + } uint8_t short_buffer[4]; if (read_flash(sector_address, short_buffer, 4)) { for (uint16_t i = 0; i < 4; i++) { @@ -150,10 +161,16 @@ static bool page_erased(uint32_t sector_address) { static bool erase_sector(uint32_t sector_address) { // Before we erase the sector we need to wait for any writes to finish and // and then enable the write again. + if (flash_device->no_erase_cmd){ + // skip this if device doesn't have an erase command. + return true; + } if (!wait_for_flash_ready() || !write_enable()) { return false; } - + if (flash_device->no_erase_cmd) { + return true; + } spi_flash_sector_command(CMD_SECTOR_ERASE, sector_address); return true; } @@ -191,25 +208,33 @@ void supervisor_flash_init(void) { spi_flash_init(); +#ifdef EXTERNAL_FLASH_NO_JEDEC + // For NVM that don't have JEDEC response + spi_flash_command(CMD_WAKE); + for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) { + const external_flash_device* possible_device = &possible_devices[i]; + flash_device = possible_device; + break; + } +#else // The response will be 0xff if the flash needs more time to start up. uint8_t jedec_id_response[3] = {0xff, 0xff, 0xff}; while (jedec_id_response[0] == 0xff) { spi_flash_read_command(CMD_READ_JEDEC_ID, jedec_id_response, 3); } - - for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) { - const external_flash_device* possible_device = &possible_devices[i]; - if (jedec_id_response[0] == possible_device->manufacturer_id && - jedec_id_response[1] == possible_device->memory_type && - jedec_id_response[2] == possible_device->capacity) { - flash_device = possible_device; - break; + for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) { + const external_flash_device* possible_device = &possible_devices[i]; + if (jedec_id_response[0] == possible_device->manufacturer_id && + jedec_id_response[1] == possible_device->memory_type && + jedec_id_response[2] == possible_device->capacity) { + flash_device = possible_device; + break; + } + } +#endif + if (flash_device == NULL) { + return; } - } - - if (flash_device == NULL) { - return; - } // We don't know what state the flash is in so wait for any remaining writes and then reset. uint8_t read_status_response[1] = {0x00}; @@ -217,14 +242,17 @@ void supervisor_flash_init(void) { do { spi_flash_read_command(CMD_READ_STATUS, read_status_response, 1); } while ((read_status_response[0] & 0x1) != 0); - // The suspended write/erase bit should be low. - do { - spi_flash_read_command(CMD_READ_STATUS2, read_status_response, 1); - } while ((read_status_response[0] & 0x80) != 0); - + if (!flash_device->single_status_byte) { + // The suspended write/erase bit should be low. + do { + spi_flash_read_command(CMD_READ_STATUS2, read_status_response, 1); + } while ((read_status_response[0] & 0x80) != 0); + } - spi_flash_command(CMD_ENABLE_RESET); - spi_flash_command(CMD_RESET); + if (!(flash_device->no_reset_cmd)){ + spi_flash_command(CMD_ENABLE_RESET); + spi_flash_command(CMD_RESET); + } // Wait 30us for the reset common_hal_mcu_delay_us(30); @@ -272,6 +300,9 @@ uint32_t supervisor_flash_get_block_count(void) { // Flush the cache that was written to the scratch portion of flash. Only used // when ram is tight. static bool flush_scratch_flash(void) { + if (current_sector == NO_SECTOR_LOADED) { + return true; + } // First, copy out any blocks that we haven't touched from the sector we've // cached. bool copy_to_scratch_ok = true; @@ -321,6 +352,10 @@ static bool allocate_ram_cache(void) { return true; } + if (MP_STATE_MEM(gc_pool_start) == 0) { + return false; + } + MP_STATE_VM(flash_ram_cache) = m_malloc_maybe(blocks_per_sector * pages_per_block * sizeof(uint32_t), false); if (MP_STATE_VM(flash_ram_cache) == NULL) { return false; @@ -360,9 +395,25 @@ static bool allocate_ram_cache(void) { return success; } +static void release_ram_cache(void) { + if (supervisor_cache != NULL) { + free_memory(supervisor_cache); + supervisor_cache = NULL; + } else if (MP_STATE_MEM(gc_pool_start)) { + m_free(MP_STATE_VM(flash_ram_cache)); + } + MP_STATE_VM(flash_ram_cache) = NULL; +} + // Flush the cached sector from ram onto the flash. We'll free the cache unless // keep_cache is true. static bool flush_ram_cache(bool keep_cache) { + if (current_sector == NO_SECTOR_LOADED) { + if (!keep_cache) { + release_ram_cache(); + } + return true; + } // First, copy out any blocks that we haven't touched from the sector // we've cached. If we don't do this we'll erase the data during the sector // erase below. @@ -396,29 +447,21 @@ static bool flush_ram_cache(bool keep_cache) { write_flash(current_sector + (i * pages_per_block + j) * SPI_FLASH_PAGE_SIZE, MP_STATE_VM(flash_ram_cache)[i * pages_per_block + j], SPI_FLASH_PAGE_SIZE); - if (!keep_cache && supervisor_cache == NULL) { + if (!keep_cache && supervisor_cache == NULL && MP_STATE_MEM(gc_pool_start)) { m_free(MP_STATE_VM(flash_ram_cache)[i * pages_per_block + j]); } } } // We're done with the cache for now so give it back. if (!keep_cache) { - if (supervisor_cache != NULL) { - free_memory(supervisor_cache); - supervisor_cache = NULL; - } else { - m_free(MP_STATE_VM(flash_ram_cache)); - } - MP_STATE_VM(flash_ram_cache) = NULL; + release_ram_cache(); } return true; } // Delegates to the correct flash flush method depending on the existing cache. +// TODO Don't blink the status indicator if we don't actually do any writing (hard to tell right now). static void spi_flash_flush_keep_cache(bool keep_cache) { - if (current_sector == NO_SECTOR_LOADED) { - return; - } #ifdef MICROPY_HW_LED_MSC port_pin_set_output_level(MICROPY_HW_LED_MSC, true); #endif @@ -436,9 +479,11 @@ static void spi_flash_flush_keep_cache(bool keep_cache) { #endif } -// External flash function used. If called externally we assume we won't need -// the cache after. -void supervisor_flash_flush(void) { +void supervisor_external_flash_flush(void) { + spi_flash_flush_keep_cache(true); +} + +void supervisor_flash_release_cache(void) { spi_flash_flush_keep_cache(false); } @@ -502,7 +547,7 @@ bool external_flash_write_block(const uint8_t *data, uint32_t block) { return write_flash(address, data, FILESYSTEM_BLOCK_SIZE); } if (current_sector != NO_SECTOR_LOADED) { - spi_flash_flush_keep_cache(true); + supervisor_flash_flush(); } if (MP_STATE_VM(flash_ram_cache) == NULL && !allocate_ram_cache()) { erase_sector(flash_device->total_size - SPI_FLASH_ERASE_SIZE); diff --git a/supervisor/shared/external_flash/external_flash.h b/supervisor/shared/external_flash/external_flash.h index 72b619a2a..db5c677eb 100644 --- a/supervisor/shared/external_flash/external_flash.h +++ b/supervisor/shared/external_flash/external_flash.h @@ -45,4 +45,6 @@ #define SPI_FLASH_MAX_BAUDRATE 8000000 #endif +void supervisor_external_flash_flush(void); + #endif // MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_EXTERNAL_FLASH_H diff --git a/supervisor/shared/external_flash/spi_flash.c b/supervisor/shared/external_flash/spi_flash.c index ec7101bc9..67e64c970 100644 --- a/supervisor/shared/external_flash/spi_flash.c +++ b/supervisor/shared/external_flash/spi_flash.c @@ -36,33 +36,33 @@ #include "py/mpconfig.h" digitalio_digitalinout_obj_t cs_pin; -busio_spi_obj_t spi; +busio_spi_obj_t supervisor_flash_spi_bus; const external_flash_device* flash_device; uint32_t spi_flash_baudrate; // Enable the flash over SPI. static void flash_enable(void) { - while (!common_hal_busio_spi_try_lock(&spi)) {} + while (!common_hal_busio_spi_try_lock(&supervisor_flash_spi_bus)) {} common_hal_digitalio_digitalinout_set_value(&cs_pin, false); } // Disable the flash over SPI. static void flash_disable(void) { common_hal_digitalio_digitalinout_set_value(&cs_pin, true); - common_hal_busio_spi_unlock(&spi); + common_hal_busio_spi_unlock(&supervisor_flash_spi_bus); } static bool transfer(uint8_t* command, uint32_t command_length, uint8_t* data_in, uint8_t* data_out, uint32_t data_length) { flash_enable(); - bool status = common_hal_busio_spi_write(&spi, command, command_length); + bool status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, command, command_length); if (status) { if (data_in != NULL && data_out != NULL) { - status = common_hal_busio_spi_transfer(&spi, data_out, data_in, data_length); + status = common_hal_busio_spi_transfer(&supervisor_flash_spi_bus, data_out, data_in, data_length); } else if (data_out != NULL) { - status = common_hal_busio_spi_read(&spi, data_out, data_length, 0xff); + status = common_hal_busio_spi_read(&supervisor_flash_spi_bus, data_out, data_length, 0xff); } else if (data_in != NULL) { - status = common_hal_busio_spi_write(&spi, data_in, data_length); + status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, data_in, data_length); } } flash_disable(); @@ -103,10 +103,10 @@ bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t data_length) // Write the SPI flash write address into the bytes following the command byte. address_to_bytes(address, request + 1); flash_enable(); - common_hal_busio_spi_configure(&spi, spi_flash_baudrate, 0, 0, 8); - bool status = common_hal_busio_spi_write(&spi, request, 4); + common_hal_busio_spi_configure(&supervisor_flash_spi_bus, spi_flash_baudrate, 0, 0, 8); + bool status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, request, 4); if (status) { - status = common_hal_busio_spi_write(&spi, data, data_length); + status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, data, data_length); } flash_disable(); return status; @@ -122,23 +122,27 @@ bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t data_length) // Write the SPI flash write address into the bytes following the command byte. address_to_bytes(address, request + 1); flash_enable(); - common_hal_busio_spi_configure(&spi, spi_flash_baudrate, 0, 0, 8); - bool status = common_hal_busio_spi_write(&spi, request, command_length); + common_hal_busio_spi_configure(&supervisor_flash_spi_bus, spi_flash_baudrate, 0, 0, 8); + bool status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, request, command_length); if (status) { - status = common_hal_busio_spi_read(&spi, data, data_length, 0xff); + status = common_hal_busio_spi_read(&supervisor_flash_spi_bus, data, data_length, 0xff); } flash_disable(); return status; } void spi_flash_init(void) { + cs_pin.base.type = &digitalio_digitalinout_type; common_hal_digitalio_digitalinout_construct(&cs_pin, SPI_FLASH_CS_PIN); + // Set CS high (disabled). common_hal_digitalio_digitalinout_switch_to_output(&cs_pin, true, DRIVE_MODE_PUSH_PULL); + common_hal_digitalio_digitalinout_never_reset(&cs_pin); - common_hal_busio_spi_construct(&spi, SPI_FLASH_SCK_PIN, SPI_FLASH_MOSI_PIN, SPI_FLASH_MISO_PIN); - common_hal_busio_spi_never_reset(&spi); + supervisor_flash_spi_bus.base.type = &busio_spi_type; + common_hal_busio_spi_construct(&supervisor_flash_spi_bus, SPI_FLASH_SCK_PIN, SPI_FLASH_MOSI_PIN, SPI_FLASH_MISO_PIN); + common_hal_busio_spi_never_reset(&supervisor_flash_spi_bus); } void spi_flash_init_device(const external_flash_device* device) { |