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-rw-r--r--supervisor/shared/external_flash/devices.h994
-rw-r--r--supervisor/shared/external_flash/external_flash.c86
-rw-r--r--supervisor/shared/external_flash/external_flash_root_pointers.h2
-rw-r--r--supervisor/shared/external_flash/qspi_flash.c2
-rw-r--r--supervisor/shared/external_flash/qspi_flash.h2
-rw-r--r--supervisor/shared/external_flash/spi_flash.c21
6 files changed, 554 insertions, 553 deletions
diff --git a/supervisor/shared/external_flash/devices.h b/supervisor/shared/external_flash/devices.h
index c8c941adf..edc6419ef 100644
--- a/supervisor/shared/external_flash/devices.h
+++ b/supervisor/shared/external_flash/devices.h
@@ -55,662 +55,662 @@ typedef struct {
// Supports the quad input page program command 0x32. This is known as 1-1-4 because it only
// uses all four lines for data.
- bool supports_qspi_writes: 1;
+ bool supports_qspi_writes : 1;
// Requires a separate command 0x31 to write to the second byte of the status register.
// Otherwise two byte are written via 0x01.
- bool write_status_register_split: 1;
+ bool write_status_register_split : 1;
// True when the status register is a single byte. This implies the Quad Enable bit is in the
// first byte and the Read Status Register 2 command (0x35) is unsupported.
- bool single_status_byte: 1;
+ bool single_status_byte : 1;
// Does not support using a ready bit within the status register
- bool no_ready_bit: 1;
+ bool no_ready_bit : 1;
// Does not support the erase command (0x20)
- bool no_erase_cmd: 1;
+ bool no_erase_cmd : 1;
// Device does not have a reset command
- bool no_reset_cmd: 1;
+ bool no_reset_cmd : 1;
} external_flash_device;
// Settings for the Adesto Tech AT25DF081A 1MiB SPI flash. It's on the SAMD21
// Xplained board.
// Datasheet: https://www.adestotech.com/wp-content/uploads/doc8715.pdf
-#define AT25DF081A {\
- .total_size = (1 << 20), /* 1 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0x1f, \
- .memory_type = 0x45, \
- .capacity = 0x01, \
- .max_clock_speed_mhz = 85, \
- .quad_enable_bit_mask = 0x00, \
- .has_sector_protection = true, \
- .supports_fast_read = true, \
- .supports_qspi = false, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define AT25DF081A { \
+ .total_size = (1 << 20), /* 1 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0x1f, \
+ .memory_type = 0x45, \
+ .capacity = 0x01, \
+ .max_clock_speed_mhz = 85, \
+ .quad_enable_bit_mask = 0x00, \
+ .has_sector_protection = true, \
+ .supports_fast_read = true, \
+ .supports_qspi = false, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Adesto Tech AT25DF641-SSHD-T 8MiB SPI flash
// for the Oak Dev Tech Icy Tree M0 (SAMD21) feather board.
// Source: https://www.digikey.com/product-detail/en/adesto-technologies/AT25SF641-SDHD-T/1265-1180-1-ND/
// Datasheet: https://www.adestotech.com/wp-content/uploads/doc8693.pdf
-#define AT25DF641A {\
- .total_size = (1 << 23), /* 8 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0x1f, \
- .memory_type = 0x48, \
- .capacity = 0x00, \
- .max_clock_speed_mhz = 85, \
- .quad_enable_bit_mask = 0x00, \
- .has_sector_protection = true, \
- .supports_fast_read = true, \
- .supports_qspi = false, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define AT25DF641A { \
+ .total_size = (1 << 23), /* 8 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0x1f, \
+ .memory_type = 0x48, \
+ .capacity = 0x00, \
+ .max_clock_speed_mhz = 85, \
+ .quad_enable_bit_mask = 0x00, \
+ .has_sector_protection = true, \
+ .supports_fast_read = true, \
+ .supports_qspi = false, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Adesto Tech AT25SF161-SSHD-T 2MiB SPI flash
// for the StringCar M0 (SAMD21) Express board.
// Source: https://www.digikey.com/product-detail/en/adesto-technologies/AT25SF161-SDHD-T/1265-1230-1-ND/
// Datasheet: https://www.adestotech.com/wpo-content/uploads/jDS-AT25SF161_046.pdf
-#define AT25SF161 {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0x1f, \
- .memory_type = 0x86, \
- .capacity = 0x01, \
- .max_clock_speed_mhz = 85, \
- .quad_enable_bit_mask = 0x00, \
- .has_sector_protection = true, \
- .supports_fast_read = true, \
- .supports_qspi = false, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define AT25SF161 { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0x1f, \
+ .memory_type = 0x86, \
+ .capacity = 0x01, \
+ .max_clock_speed_mhz = 85, \
+ .quad_enable_bit_mask = 0x00, \
+ .has_sector_protection = true, \
+ .supports_fast_read = true, \
+ .supports_qspi = false, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Adesto Tech AT25SF041 1MiB SPI flash. It's on the SparkFun
// SAMD51 Thing Plus board
// Datasheet: https://www.adestotech.com/wp-content/uploads/DS-AT25SF041_044.pdf
-#define AT25SF041A {\
- .total_size = (1 << 19), /* 512 KiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0x1f, \
- .memory_type = 0x84, \
- .capacity = 0x01, \
- .max_clock_speed_mhz = 85, \
- .quad_enable_bit_mask = 0x00, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = false, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define AT25SF041A { \
+ .total_size = (1 << 19), /* 512 KiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0x1f, \
+ .memory_type = 0x84, \
+ .capacity = 0x01, \
+ .max_clock_speed_mhz = 85, \
+ .quad_enable_bit_mask = 0x00, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = false, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Gigadevice GD25Q16C 2MiB SPI flash.
// Datasheet: http://www.gigadevice.com/datasheet/gd25q16c/
-#define GD25Q16C {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc8, \
- .memory_type = 0x40, \
- .capacity = 0x15, \
- .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define GD25Q16C { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc8, \
+ .memory_type = 0x40, \
+ .capacity = 0x15, \
+ .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Gigadevice GD25Q32C 4MiB SPI flash.
// Datasheet: http://www.elm-tech.com/en/products/spi-flash-memory/gd25q32/gd25q32.pdf
-#define GD25Q32C {\
- .total_size = (1 << 22), /* 4 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc8, \
- .memory_type = 0x40, \
- .capacity = 0x16, \
- .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = true, \
- .single_status_byte = false, \
+#define GD25Q32C { \
+ .total_size = (1 << 22), /* 4 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc8, \
+ .memory_type = 0x40, \
+ .capacity = 0x16, \
+ .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = true, \
+ .single_status_byte = false, \
}
// Settings for the Gigadevice GD25Q64C 8MiB SPI flash.
// Datasheet: http://www.elm-tech.com/en/products/spi-flash-memory/gd25q64/gd25q64.pdf
-#define GD25Q64C {\
- .total_size = (1 << 23), /* 8 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc8, \
- .memory_type = 0x40, \
- .capacity = 0x17, \
- .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = true, \
- .single_status_byte = false, \
+#define GD25Q64C { \
+ .total_size = (1 << 23), /* 8 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc8, \
+ .memory_type = 0x40, \
+ .capacity = 0x17, \
+ .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = true, \
+ .single_status_byte = false, \
}
// Settings for the Gigadevice GD25S512MD 64MiB SPI flash.
// Datasheet: http://www.gigadevice.com/datasheet/gd25s512md/
-#define GD25S512MD {\
- .total_size = (1 << 26), /* 64 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc8, \
- .memory_type = 0x40, \
- .capacity = 0x19, \
- .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = true, \
- .single_status_byte = false, \
+#define GD25S512MD { \
+ .total_size = (1 << 26), /* 64 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc8, \
+ .memory_type = 0x40, \
+ .capacity = 0x19, \
+ .max_clock_speed_mhz = 104, /* if we need 120 then we can turn on high performance mode */ \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = true, \
+ .single_status_byte = false, \
}
// Settings for the Cypress (was Spansion) S25FL064L 8MiB SPI flash.
// Datasheet: http://www.cypress.com/file/316661/download
-#define S25FL064L {\
- .total_size = (1 << 23), /* 8 MiB */ \
- .start_up_time_us = 300, \
- .manufacturer_id = 0x01, \
- .memory_type = 0x60, \
- .capacity = 0x17, \
- .max_clock_speed_mhz = 108, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define S25FL064L { \
+ .total_size = (1 << 23), /* 8 MiB */ \
+ .start_up_time_us = 300, \
+ .manufacturer_id = 0x01, \
+ .memory_type = 0x60, \
+ .capacity = 0x17, \
+ .max_clock_speed_mhz = 108, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Cypress (was Spansion) S25FL116K 2MiB SPI flash.
// Datasheet: http://www.cypress.com/file/196886/download
-#define S25FL116K {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0x01, \
- .memory_type = 0x40, \
- .capacity = 0x15, \
- .max_clock_speed_mhz = 108, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define S25FL116K { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0x01, \
+ .memory_type = 0x40, \
+ .capacity = 0x15, \
+ .max_clock_speed_mhz = 108, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Cypress (was Spansion) S25FL216K 2MiB SPI flash.
// Datasheet: http://www.cypress.com/file/197346/download
-#define S25FL216K {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0x01, \
- .memory_type = 0x40, \
- .capacity = 0x15, \
- .max_clock_speed_mhz = 65, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = false, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define S25FL216K { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0x01, \
+ .memory_type = 0x40, \
+ .capacity = 0x15, \
+ .max_clock_speed_mhz = 65, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = false, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q16FW 2MiB SPI flash.
// Datasheet: https://www.winbond.com/resource-files/w25q16fw%20revj%2005182017%20sfdp.pdf
-#define W25Q16FW {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x60, \
- .capacity = 0x15, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q16FW { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x60, \
+ .capacity = 0x15, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q16JV-IQ 2MiB SPI flash. Note that JV-IM has a different .memory_type (0x70)
// Datasheet: https://www.winbond.com/resource-files/w25q16jv%20spi%20revf%2005092017.pdf
-#define W25Q16JV_IQ {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x40, \
- .capacity = 0x15, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q16JV_IQ { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x40, \
+ .capacity = 0x15, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q16JV-IM 2MiB SPI flash. Note that JV-IQ has a different .memory_type (0x40)
// Datasheet: https://www.winbond.com/resource-files/w25q16jv%20spi%20revf%2005092017.pdf
-#define W25Q16JV_IM {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x70, \
- .capacity = 0x15, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
+#define W25Q16JV_IM { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x70, \
+ .capacity = 0x15, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
}
// Settings for the Winbond W25Q32BV 4MiB SPI flash.
// Datasheet: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
-#define W25Q32BV {\
- .total_size = (1 << 22), /* 4 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x60, \
- .capacity = 0x16, \
- .max_clock_speed_mhz = 104, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q32BV { \
+ .total_size = (1 << 22), /* 4 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x60, \
+ .capacity = 0x16, \
+ .max_clock_speed_mhz = 104, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q32JV-IM 4MiB SPI flash.
// Datasheet: https://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf
-#define W25Q32JV_IM {\
- .total_size = (1 << 22), /* 4 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x70, \
- .capacity = 0x16, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
+#define W25Q32JV_IM { \
+ .total_size = (1 << 22), /* 4 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x70, \
+ .capacity = 0x16, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
}
// Settings for the Winbond W25Q32JV-IQ 4MiB SPI flash.
// Datasheet: https://www.mouser.com/datasheet/2/949/w25q32jv_revg_03272018_plus-1489806.pdf
-#define W25Q32JV_IQ {\
- .total_size = (1 << 22), /* 4 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x40, \
- .capacity = 0x16, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
+#define W25Q32JV_IQ { \
+ .total_size = (1 << 22), /* 4 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x40, \
+ .capacity = 0x16, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
}
// Settings for the Winbond W25Q64FV 8MiB SPI flash.
// Datasheet: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-#define W25Q64FV {\
- .total_size = (1 << 23), /* 8 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x40, \
- .capacity = 0x17, \
- .max_clock_speed_mhz = 104, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q64FV { \
+ .total_size = (1 << 23), /* 8 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x40, \
+ .capacity = 0x17, \
+ .max_clock_speed_mhz = 104, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q64JV-IM 8MiB SPI flash. Note that JV-IQ has a different .memory_type (0x40)
// Datasheet: http://www.winbond.com/resource-files/w25q64jv%20revj%2003272018%20plus.pdf
-#define W25Q64JV_IM {\
- .total_size = (1 << 23), /* 8 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x70, \
- .capacity = 0x17, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q64JV_IM { \
+ .total_size = (1 << 23), /* 8 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x70, \
+ .capacity = 0x17, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q64JV-IQ 8MiB SPI flash. Note that JV-IM has a different .memory_type (0x70)
// Datasheet: http://www.winbond.com/resource-files/w25q64jv%20revj%2003272018%20plus.pdf
-#define W25Q64JV_IQ {\
- .total_size = (1 << 23), /* 8 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x40, \
- .capacity = 0x17, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q64JV_IQ { \
+ .total_size = (1 << 23), /* 8 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x40, \
+ .capacity = 0x17, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q80DL 1MiB SPI flash.
// Datasheet: https://www.winbond.com/resource-files/w25q80dv%20dl_revh_10022015.pdf
-#define W25Q80DL {\
- .total_size = (1 << 20), /* 1 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x60, \
- .capacity = 0x14, \
- .max_clock_speed_mhz = 104, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q80DL { \
+ .total_size = (1 << 20), /* 1 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x60, \
+ .capacity = 0x14, \
+ .max_clock_speed_mhz = 104, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q80DV 1MiB SPI flash.. Note that W25Q80DL has a different memory type (0x60)
// Datasheet: https://www.winbond.com/resource-files/w25q80dv%20dl_revh_10022015.pdf
-#define W25Q80DV {\
- .total_size = (1 << 20), /* 1 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x40, \
- .capacity = 0x14, \
- .max_clock_speed_mhz = 104, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q80DV { \
+ .total_size = (1 << 20), /* 1 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x40, \
+ .capacity = 0x14, \
+ .max_clock_speed_mhz = 104, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Winbond W25Q128JV-SQ 16MiB SPI flash. Note that JV-IM has a different .memory_type (0x70)
// Datasheet: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
-#define W25Q128JV_SQ {\
- .total_size = (1 << 24), /* 16 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x40, \
- .capacity = 0x18, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q128JV_SQ { \
+ .total_size = (1 << 24), /* 16 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x40, \
+ .capacity = 0x18, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the Everspin MR20H40 / MR25H40 magnetic non-volatile RAM
// Datasheet: https://www.everspin.com/supportdocs/MR25H40CDFR
-#define MR2xH40 {\
- .total_size = (1 << 22), /* 4 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0xef, /*no JDEC*/ \
- .memory_type = 0x40, /*no JDEC*/ \
- .capacity = 0x14, /*no JDEC*/ \
- .max_clock_speed_mhz = 10, \
- .quad_enable_bit_mask = 0x00, \
- .has_sector_protection = false, \
- .supports_fast_read = false, \
- .supports_qspi = false, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
- .no_ready_bit = true, \
- .no_erase_cmd = true, \
- .no_reset_cmd = true, \
+#define MR2xH40 { \
+ .total_size = (1 << 22), /* 4 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0xef, /*no JDEC*/ \
+ .memory_type = 0x40, /*no JDEC*/ \
+ .capacity = 0x14, /*no JDEC*/ \
+ .max_clock_speed_mhz = 10, \
+ .quad_enable_bit_mask = 0x00, \
+ .has_sector_protection = false, \
+ .supports_fast_read = false, \
+ .supports_qspi = false, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
+ .no_ready_bit = true, \
+ .no_erase_cmd = true, \
+ .no_reset_cmd = true, \
}
// Settings for the Macronix MX25L1606 2MiB SPI flash.
// Datasheet:
-#define MX25L1606 {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc2, \
- .memory_type = 0x20, \
- .capacity = 0x15, \
- .max_clock_speed_mhz = 8, \
- .quad_enable_bit_mask = 0x40, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
+#define MX25L1606 { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc2, \
+ .memory_type = 0x20, \
+ .capacity = 0x15, \
+ .max_clock_speed_mhz = 8, \
+ .quad_enable_bit_mask = 0x40, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
}
// Settings for the Macronix MX25L3233F 4MiB SPI flash.
// Datasheet: http://www.macronix.com/Lists/Datasheet/Attachments/7426/MX25L3233F,%203V,%2032Mb,%20v1.6.pdf
-#define MX25L3233F {\
- .total_size = (1 << 22), /* 4 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc2, \
- .memory_type = 0x20, \
- .capacity = 0x16, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x40, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
+#define MX25L3233F { \
+ .total_size = (1 << 22), /* 4 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc2, \
+ .memory_type = 0x20, \
+ .capacity = 0x16, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x40, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
}
// Settings for the Macronix MX25R6435F 8MiB SPI flash.
// Datasheet: http://www.macronix.com/Lists/Datasheet/Attachments/7428/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.4.pdf
// By default its in lower power mode which can only do 8mhz. In high power mode it can do 80mhz.
-#define MX25R6435F {\
- .total_size = (1 << 23), /* 8 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc2, \
- .memory_type = 0x28, \
- .capacity = 0x17, \
- .max_clock_speed_mhz = 8, \
- .quad_enable_bit_mask = 0x40, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
+#define MX25R6435F { \
+ .total_size = (1 << 23), /* 8 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc2, \
+ .memory_type = 0x28, \
+ .capacity = 0x17, \
+ .max_clock_speed_mhz = 8, \
+ .quad_enable_bit_mask = 0x40, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
}
// Settings for the Macronix MX25R1635F 8MiB SPI flash.
// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7595/MX25R1635F,%20Wide%20Range,%2016Mb,%20v1.6.pdf
// In low power mode, quad operations can only run at 8 MHz.
-#define MX25R1635F {\
- .total_size = (1 << 21), /* 2 MiB */ \
- .start_up_time_us = 800, \
- .manufacturer_id = 0xc2, \
- .memory_type = 0x28, \
- .capacity = 0x15, \
- .max_clock_speed_mhz = 33, /* 8 mhz for dual/quad */ \
- .quad_enable_bit_mask = 0x80, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
+#define MX25R1635F { \
+ .total_size = (1 << 21), /* 2 MiB */ \
+ .start_up_time_us = 800, \
+ .manufacturer_id = 0xc2, \
+ .memory_type = 0x28, \
+ .capacity = 0x15, \
+ .max_clock_speed_mhz = 33, /* 8 mhz for dual/quad */ \
+ .quad_enable_bit_mask = 0x80, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
}
// Settings for the Macronix MX25L51245G 64MiB SPI flash.
// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7437/MX25L51245G,%203V,%20512Mb,%20v1.6.pdf
-#define MX25L51245G {\
- .total_size = (1 << 26), /* 64 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc2, \
- .memory_type = 0x20, \
- .capacity = 0x1a, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x40, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
+#define MX25L51245G { \
+ .total_size = (1 << 26), /* 64 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc2, \
+ .memory_type = 0x20, \
+ .capacity = 0x1a, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x40, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
}
// Settings for the Macronix MX25L51245G 64MiB SPI flash.
// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7437/MX25L51245G,%203V,%20512Mb,%20v1.6.pdf
-#define MX25L25645G {\
- .total_size = (1 << 25), /* 32 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0x9f, \
- .memory_type = 0xab, \
- .capacity = 0x90, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0xaf, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
+#define MX25L25645G { \
+ .total_size = (1 << 25), /* 32 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0x9f, \
+ .memory_type = 0xab, \
+ .capacity = 0x90, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0xaf, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
}
// Settings for the Macronix MX25L12833F 16MiB SPI flash
// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7447/MX25L12833F,%203V,%20128Mb,%20v1.0.pdf
-#define MX25L12833F {\
- .total_size = (1UL << 24), /* 16 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xc2, \
- .memory_type = 0x20, \
- .capacity = 0x18, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x40, \
- .has_sector_protection = true, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
- }
+#define MX25L12833F { \
+ .total_size = (1UL << 24), /* 16 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xc2, \
+ .memory_type = 0x20, \
+ .capacity = 0x18, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x40, \
+ .has_sector_protection = true, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
+}
// Settings for the Winbond W25Q128JV-PM 16MiB SPI flash. Note that JV-IM has a different .memory_type (0x70)
// Datasheet: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
-#define W25Q128JV_PM {\
- .total_size = (1 << 24), /* 16 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x70, \
- .capacity = 0x18, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
+#define W25Q128JV_PM { \
+ .total_size = (1 << 24), /* 16 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x70, \
+ .capacity = 0x18, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
}
// Settings for the Winbond W25Q32FV 4MiB SPI flash.
// Datasheet:http://www.winbond.com/resource-files/w25q32fv%20revj%2006032016.pdf?__locale=en
-#define W25Q32FV {\
- .total_size = (1 << 22), /* 4 MiB */ \
- .start_up_time_us = 5000, \
- .manufacturer_id = 0xef, \
- .memory_type = 0x40, \
- .capacity = 0x16, \
- .max_clock_speed_mhz = 104, \
- .quad_enable_bit_mask = 0x00, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = false, \
- .supports_qspi_writes = false, \
- .write_status_register_split = false, \
- .single_status_byte = false, \
+#define W25Q32FV { \
+ .total_size = (1 << 22), /* 4 MiB */ \
+ .start_up_time_us = 5000, \
+ .manufacturer_id = 0xef, \
+ .memory_type = 0x40, \
+ .capacity = 0x16, \
+ .max_clock_speed_mhz = 104, \
+ .quad_enable_bit_mask = 0x00, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = false, \
+ .supports_qspi_writes = false, \
+ .write_status_register_split = false, \
+ .single_status_byte = false, \
}
// Settings for the ISSI IS25LP128F 16MiB SPI flash.
// Datasheet: http://www.issi.com/WW/pdf/25LP-WP128F.pdf
-#define IS25LP128F {\
- .total_size = (1 << 24), /* 16 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0x9d, \
- .memory_type = 0x60, \
- .capacity = 0x18, \
- .max_clock_speed_mhz = 133, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = true, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
+#define IS25LP128F { \
+ .total_size = (1 << 24), /* 16 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0x9d, \
+ .memory_type = 0x60, \
+ .capacity = 0x18, \
+ .max_clock_speed_mhz = 133, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = true, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
}
// Settings for the Micron N25Q256A 256Mb (32MiB) QSPI flash.
// Datasheet: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
-#define N25Q256A {\
- /* .total_size = (1 << 25), 32 MiB does not work at this time, as assumptions about 3-byte addresses abound */ \
- .total_size = (1 << 24), /* 16 MiB */ \
- .start_up_time_us = 10000, \
- .manufacturer_id = 0x20, \
- .memory_type = 0xBA, \
- .capacity = 0x19, \
- .max_clock_speed_mhz = 108, \
- .quad_enable_bit_mask = 0x02, \
- .has_sector_protection = false, \
- .supports_fast_read = true, \
- .supports_qspi = true, \
- .supports_qspi_writes = true, \
- .write_status_register_split = false, \
- .single_status_byte = true, \
+#define N25Q256A { \
+ /* .total_size = (1 << 25), 32 MiB does not work at this time, as assumptions about 3-byte addresses abound */ \
+ .total_size = (1 << 24), /* 16 MiB */ \
+ .start_up_time_us = 10000, \
+ .manufacturer_id = 0x20, \
+ .memory_type = 0xBA, \
+ .capacity = 0x19, \
+ .max_clock_speed_mhz = 108, \
+ .quad_enable_bit_mask = 0x02, \
+ .has_sector_protection = false, \
+ .supports_fast_read = true, \
+ .supports_qspi = true, \
+ .supports_qspi_writes = true, \
+ .write_status_register_split = false, \
+ .single_status_byte = true, \
}
#endif // MICROPY_INCLUDED_ATMEL_SAMD_EXTERNAL_FLASH_DEVICES_H
diff --git a/supervisor/shared/external_flash/external_flash.c b/supervisor/shared/external_flash/external_flash.c
index 23727e7e7..f8054a9fe 100644
--- a/supervisor/shared/external_flash/external_flash.c
+++ b/supervisor/shared/external_flash/external_flash.c
@@ -48,19 +48,19 @@ static uint32_t current_sector;
STATIC const external_flash_device possible_devices[] = {EXTERNAL_FLASH_DEVICES};
#define EXTERNAL_FLASH_DEVICE_COUNT MP_ARRAY_SIZE(possible_devices)
-static const external_flash_device* flash_device = NULL;
+static const external_flash_device *flash_device = NULL;
// Track which blocks (up to 32) in the current sector currently live in the
// cache.
static uint32_t dirty_mask;
-static supervisor_allocation* supervisor_cache = NULL;
+static supervisor_allocation *supervisor_cache = NULL;
// Wait until both the write enable and write in progress bits have cleared.
static bool wait_for_flash_ready(void) {
bool ok = true;
// Both the write enable and write in progress bits should be low.
- if (flash_device->no_ready_bit){
+ if (flash_device->no_ready_bit) {
// For NVM without a ready bit in status register
return ok;
}
@@ -77,7 +77,7 @@ static bool write_enable(void) {
}
// Read data_length's worth of bytes starting at address into data.
-static bool read_flash(uint32_t address, uint8_t* data, uint32_t data_length) {
+static bool read_flash(uint32_t address, uint8_t *data, uint32_t data_length) {
if (flash_device == NULL) {
return false;
}
@@ -90,13 +90,13 @@ static bool read_flash(uint32_t address, uint8_t* data, uint32_t data_length) {
// Writes data_length's worth of bytes starting at address from data. Assumes
// that the sector that address resides in has already been erased. So make sure
// to run erase_sector.
-static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_length) {
+static bool write_flash(uint32_t address, const uint8_t *data, uint32_t data_length) {
if (flash_device == NULL) {
return false;
}
// Don't bother writing if the data is all 1s. Thats equivalent to the flash
// state after an erase.
- if (!flash_device->no_erase_cmd){
+ if (!flash_device->no_erase_cmd) {
// Only do this if the device has an erase command
bool all_ones = true;
for (uint16_t i = 0; i < data_length; i++) {
@@ -111,14 +111,14 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len
}
for (uint32_t bytes_written = 0;
- bytes_written < data_length;
- bytes_written += SPI_FLASH_PAGE_SIZE) {
+ bytes_written < data_length;
+ bytes_written += SPI_FLASH_PAGE_SIZE) {
if (!wait_for_flash_ready() || !write_enable()) {
return false;
}
- if (!spi_flash_write_data(address + bytes_written, (uint8_t*) data + bytes_written,
- SPI_FLASH_PAGE_SIZE)) {
+ if (!spi_flash_write_data(address + bytes_written, (uint8_t *)data + bytes_written,
+ SPI_FLASH_PAGE_SIZE)) {
return false;
}
}
@@ -128,7 +128,7 @@ static bool write_flash(uint32_t address, const uint8_t* data, uint32_t data_len
static bool page_erased(uint32_t sector_address) {
// Check the first few bytes to catch the common case where there is data
// without using a bunch of memory.
- if (flash_device->no_erase_cmd){
+ if (flash_device->no_erase_cmd) {
// skip this if device doesn't have an erase command.
return true;
}
@@ -162,7 +162,7 @@ static bool page_erased(uint32_t sector_address) {
static bool erase_sector(uint32_t sector_address) {
// Before we erase the sector we need to wait for any writes to finish and
// and then enable the write again.
- if (flash_device->no_erase_cmd){
+ if (flash_device->no_erase_cmd) {
// skip this if device doesn't have an erase command.
return true;
}
@@ -209,33 +209,33 @@ void supervisor_flash_init(void) {
spi_flash_init();
-#ifdef EXTERNAL_FLASH_NO_JEDEC
+ #ifdef EXTERNAL_FLASH_NO_JEDEC
// For NVM that don't have JEDEC response
spi_flash_command(CMD_WAKE);
for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
- const external_flash_device* possible_device = &possible_devices[i];
+ const external_flash_device *possible_device = &possible_devices[i];
flash_device = possible_device;
break;
}
-#else
+ #else
// The response will be 0xff if the flash needs more time to start up.
uint8_t jedec_id_response[3] = {0xff, 0xff, 0xff};
while (jedec_id_response[0] == 0xff) {
spi_flash_read_command(CMD_READ_JEDEC_ID, jedec_id_response, 3);
}
- for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
- const external_flash_device* possible_device = &possible_devices[i];
- if (jedec_id_response[0] == possible_device->manufacturer_id &&
- jedec_id_response[1] == possible_device->memory_type &&
- jedec_id_response[2] == possible_device->capacity) {
- flash_device = possible_device;
- break;
- }
- }
-#endif
- if (flash_device == NULL) {
- return;
+ for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
+ const external_flash_device *possible_device = &possible_devices[i];
+ if (jedec_id_response[0] == possible_device->manufacturer_id &&
+ jedec_id_response[1] == possible_device->memory_type &&
+ jedec_id_response[2] == possible_device->capacity) {
+ flash_device = possible_device;
+ break;
}
+ }
+ #endif
+ if (flash_device == NULL) {
+ return;
+ }
// We don't know what state the flash is in so wait for any remaining writes and then reset.
uint8_t read_status_response[1] = {0x00};
@@ -250,7 +250,7 @@ void supervisor_flash_init(void) {
} while ((read_status_response[0] & 0x80) != 0);
}
- if (!(flash_device->no_reset_cmd)){
+ if (!(flash_device->no_reset_cmd)) {
spi_flash_command(CMD_ENABLE_RESET);
spi_flash_command(CMD_RESET);
}
@@ -261,14 +261,14 @@ void supervisor_flash_init(void) {
spi_flash_init_device(flash_device);
// Activity LED for flash writes.
-#ifdef MICROPY_HW_LED_MSC
+ #ifdef MICROPY_HW_LED_MSC
gpio_set_pin_function(SPI_FLASH_CS_PIN, GPIO_PIN_FUNCTION_OFF);
gpio_set_pin_direction(MICROPY_HW_LED_MSC, GPIO_DIRECTION_OUT);
// There's already a pull-up on the board.
gpio_set_pin_level(MICROPY_HW_LED_MSC, false);
-#endif
+ #endif
- if (flash_device->has_sector_protection) {
+ if (flash_device->has_sector_protection) {
write_enable();
// Turn off sector protection
@@ -312,7 +312,7 @@ static bool flush_scratch_flash(void) {
if ((dirty_mask & (1 << i)) == 0) {
copy_to_scratch_ok = copy_to_scratch_ok &&
copy_block(current_sector + i * FILESYSTEM_BLOCK_SIZE,
- scratch_sector + i * FILESYSTEM_BLOCK_SIZE);
+ scratch_sector + i * FILESYSTEM_BLOCK_SIZE);
}
}
if (!copy_to_scratch_ok) {
@@ -325,7 +325,7 @@ static bool flush_scratch_flash(void) {
// Finally, copy the new version into it.
for (uint8_t i = 0; i < SPI_FLASH_ERASE_SIZE / FILESYSTEM_BLOCK_SIZE; i++) {
copy_block(scratch_sector + i * FILESYSTEM_BLOCK_SIZE,
- current_sector + i * FILESYSTEM_BLOCK_SIZE);
+ current_sector + i * FILESYSTEM_BLOCK_SIZE);
}
return true;
}
@@ -341,8 +341,8 @@ static bool allocate_ram_cache(void) {
// Attempt to allocate outside the heap first.
supervisor_cache = allocate_memory(table_size + SPI_FLASH_ERASE_SIZE, false, false);
if (supervisor_cache != NULL) {
- MP_STATE_VM(flash_ram_cache) = (uint8_t **) supervisor_cache->ptr;
- uint8_t* page_start = (uint8_t *) supervisor_cache->ptr + table_size;
+ MP_STATE_VM(flash_ram_cache) = (uint8_t **)supervisor_cache->ptr;
+ uint8_t *page_start = (uint8_t *)supervisor_cache->ptr + table_size;
for (uint8_t i = 0; i < blocks_per_sector; i++) {
for (uint8_t j = 0; j < pages_per_block; j++) {
@@ -446,8 +446,8 @@ static bool flush_ram_cache(bool keep_cache) {
for (uint8_t i = 0; i < SPI_FLASH_ERASE_SIZE / FILESYSTEM_BLOCK_SIZE; i++) {
for (uint8_t j = 0; j < pages_per_block; j++) {
write_flash(current_sector + (i * pages_per_block + j) * SPI_FLASH_PAGE_SIZE,
- MP_STATE_VM(flash_ram_cache)[i * pages_per_block + j],
- SPI_FLASH_PAGE_SIZE);
+ MP_STATE_VM(flash_ram_cache)[i * pages_per_block + j],
+ SPI_FLASH_PAGE_SIZE);
if (!keep_cache && supervisor_cache == NULL && MP_STATE_MEM(gc_pool_start)) {
m_free(MP_STATE_VM(flash_ram_cache)[i * pages_per_block + j]);
}
@@ -464,7 +464,7 @@ static bool flush_ram_cache(bool keep_cache) {
// TODO Don't blink the status indicator if we don't actually do any writing (hard to tell right now).
static void spi_flash_flush_keep_cache(bool keep_cache) {
#ifdef MICROPY_HW_LED_MSC
- port_pin_set_output_level(MICROPY_HW_LED_MSC, true);
+ port_pin_set_output_level(MICROPY_HW_LED_MSC, true);
#endif
temp_status_color(ACTIVE_WRITE);
// If we've cached to the flash itself flush from there.
@@ -476,7 +476,7 @@ static void spi_flash_flush_keep_cache(bool keep_cache) {
current_sector = NO_SECTOR_LOADED;
clear_temp_status();
#ifdef MICROPY_HW_LED_MSC
- port_pin_set_output_level(MICROPY_HW_LED_MSC, false);
+ port_pin_set_output_level(MICROPY_HW_LED_MSC, false);
#endif
}
@@ -514,8 +514,8 @@ bool external_flash_read_block(uint8_t *dest, uint32_t block) {
uint8_t pages_per_block = FILESYSTEM_BLOCK_SIZE / SPI_FLASH_PAGE_SIZE;
for (int i = 0; i < pages_per_block; i++) {
memcpy(dest + i * SPI_FLASH_PAGE_SIZE,
- MP_STATE_VM(flash_ram_cache)[block_index * pages_per_block + i],
- SPI_FLASH_PAGE_SIZE);
+ MP_STATE_VM(flash_ram_cache)[block_index * pages_per_block + i],
+ SPI_FLASH_PAGE_SIZE);
}
return true;
} else {
@@ -563,8 +563,8 @@ bool external_flash_write_block(const uint8_t *data, uint32_t block) {
uint8_t pages_per_block = FILESYSTEM_BLOCK_SIZE / SPI_FLASH_PAGE_SIZE;
for (int i = 0; i < pages_per_block; i++) {
memcpy(MP_STATE_VM(flash_ram_cache)[block_index * pages_per_block + i],
- data + i * SPI_FLASH_PAGE_SIZE,
- SPI_FLASH_PAGE_SIZE);
+ data + i * SPI_FLASH_PAGE_SIZE,
+ SPI_FLASH_PAGE_SIZE);
}
return true;
} else {
diff --git a/supervisor/shared/external_flash/external_flash_root_pointers.h b/supervisor/shared/external_flash/external_flash_root_pointers.h
index cb1b86d19..0613c9a57 100644
--- a/supervisor/shared/external_flash/external_flash_root_pointers.h
+++ b/supervisor/shared/external_flash/external_flash_root_pointers.h
@@ -30,6 +30,6 @@
// We use this when we can allocate the whole cache in RAM.
#define FLASH_ROOT_POINTERS \
- uint8_t** flash_ram_cache; \
+ uint8_t **flash_ram_cache; \
#endif // MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_EXTERNAL_FLASH_ROOT_POINTERS_H
diff --git a/supervisor/shared/external_flash/qspi_flash.c b/supervisor/shared/external_flash/qspi_flash.c
index 48266540c..dc16f3465 100644
--- a/supervisor/shared/external_flash/qspi_flash.c
+++ b/supervisor/shared/external_flash/qspi_flash.c
@@ -28,7 +28,7 @@
#include "supervisor/shared/external_flash/common_commands.h"
-void check_quad_enable(const external_flash_device* device) {
+void check_quad_enable(const external_flash_device *device) {
if (device->quad_enable_bit_mask == 0x00) {
return;
}
diff --git a/supervisor/shared/external_flash/qspi_flash.h b/supervisor/shared/external_flash/qspi_flash.h
index b72e37b26..c0c089ee0 100644
--- a/supervisor/shared/external_flash/qspi_flash.h
+++ b/supervisor/shared/external_flash/qspi_flash.h
@@ -26,6 +26,6 @@
#ifndef MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_QSPI_FLASH_H
#define MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_QSPI_FLASH_H
-void check_quad_enable(const external_flash_device* device);
+void check_quad_enable(const external_flash_device *device);
#endif // MICROPY_INCLUDED_SUPERVISOR_SHARED_EXTERNAL_FLASH_QSPI_FLASH_H
diff --git a/supervisor/shared/external_flash/spi_flash.c b/supervisor/shared/external_flash/spi_flash.c
index 67e64c970..3ddd92b5e 100644
--- a/supervisor/shared/external_flash/spi_flash.c
+++ b/supervisor/shared/external_flash/spi_flash.c
@@ -38,12 +38,13 @@
digitalio_digitalinout_obj_t cs_pin;
busio_spi_obj_t supervisor_flash_spi_bus;
-const external_flash_device* flash_device;
+const external_flash_device *flash_device;
uint32_t spi_flash_baudrate;
// Enable the flash over SPI.
static void flash_enable(void) {
- while (!common_hal_busio_spi_try_lock(&supervisor_flash_spi_bus)) {}
+ while (!common_hal_busio_spi_try_lock(&supervisor_flash_spi_bus)) {
+ }
common_hal_digitalio_digitalinout_set_value(&cs_pin, false);
}
@@ -53,7 +54,7 @@ static void flash_disable(void) {
common_hal_busio_spi_unlock(&supervisor_flash_spi_bus);
}
-static bool transfer(uint8_t* command, uint32_t command_length, uint8_t* data_in, uint8_t* data_out, uint32_t data_length) {
+static bool transfer(uint8_t *command, uint32_t command_length, uint8_t *data_in, uint8_t *data_out, uint32_t data_length) {
flash_enable();
bool status = common_hal_busio_spi_write(&supervisor_flash_spi_bus, command, command_length);
if (status) {
@@ -69,7 +70,7 @@ static bool transfer(uint8_t* command, uint32_t command_length, uint8_t* data_in
return status;
}
-static bool transfer_command(uint8_t command, uint8_t* data_in, uint8_t* data_out, uint32_t data_length) {
+static bool transfer_command(uint8_t command, uint8_t *data_in, uint8_t *data_out, uint32_t data_length) {
return transfer(&command, 1, data_in, data_out, data_length);
}
@@ -77,16 +78,16 @@ bool spi_flash_command(uint8_t command) {
return transfer_command(command, NULL, NULL, 0);
}
-bool spi_flash_read_command(uint8_t command, uint8_t* data, uint32_t data_length) {
+bool spi_flash_read_command(uint8_t command, uint8_t *data, uint32_t data_length) {
return transfer_command(command, NULL, data, data_length);
}
-bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t data_length) {
+bool spi_flash_write_command(uint8_t command, uint8_t *data, uint32_t data_length) {
return transfer_command(command, data, NULL, data_length);
}
// Pack the low 24 bits of the address into a uint8_t array.
-static void address_to_bytes(uint32_t address, uint8_t* bytes) {
+static void address_to_bytes(uint32_t address, uint8_t *bytes) {
bytes[0] = (address >> 16) & 0xff;
bytes[1] = (address >> 8) & 0xff;
bytes[2] = address & 0xff;
@@ -98,7 +99,7 @@ bool spi_flash_sector_command(uint8_t command, uint32_t address) {
return transfer(request, 4, NULL, NULL, 0);
}
-bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t data_length) {
+bool spi_flash_write_data(uint32_t address, uint8_t *data, uint32_t data_length) {
uint8_t request[4] = {CMD_PAGE_PROGRAM, 0x00, 0x00, 0x00};
// Write the SPI flash write address into the bytes following the command byte.
address_to_bytes(address, request + 1);
@@ -112,7 +113,7 @@ bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t data_length)
return status;
}
-bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t data_length) {
+bool spi_flash_read_data(uint32_t address, uint8_t *data, uint32_t data_length) {
uint8_t request[5] = {CMD_READ_DATA, 0x00, 0x00, 0x00};
uint8_t command_length = 4;
if (flash_device->supports_fast_read) {
@@ -145,7 +146,7 @@ void spi_flash_init(void) {
common_hal_busio_spi_never_reset(&supervisor_flash_spi_bus);
}
-void spi_flash_init_device(const external_flash_device* device) {
+void spi_flash_init_device(const external_flash_device *device) {
flash_device = device;
spi_flash_baudrate = device->max_clock_speed_mhz * 1000000;
if (spi_flash_baudrate > SPI_FLASH_MAX_BAUDRATE) {
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-08 14:28:53 +0000