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path: root/ports/esp8266/esp_mphal.h
AgeCommit message (Collapse)Author
2019-10-13remove ports/esp8266Dan Halbert
2018-07-28merge finishedDan Halbert
2018-05-21esp8266: Change UART(0) to attach to REPL via uos.dupterm interface.Damien George
This patch makes it so that UART(0) can by dynamically attached to and detached from the REPL by using the uos.dupterm function. Since WebREPL uses dupterm slot 0 the UART uses dupterm slot 1 (a slot which is newly introduced by this patch). UART(0) must now be attached manually in boot.py (or otherwise) and inisetup.py is changed to provide code to do this. For example, to attach use: import uos, machine uart = machine.UART(0, 115200) uos.dupterm(uart, 1) and to detach use: uos.dupterm(None, 1) When attached, all incoming chars on UART(0) go straight to stdin so uart.read() will always return None. Use sys.stdin.read() if it's needed to read characters from the UART(0) while it's also used for the REPL (or detach, read, then reattach). When detached the UART(0) can be used for other purposes. If there are no objects in any of the dupterm slots when the REPL is started (on hard or soft reset) then UART(0) is automatically attached. Without this, the only way to recover a board without a REPL would be to completely erase and reflash (which would install the default boot.py which attaches the REPL).
2018-03-12esp8266/esp_mphal.h: Fix I2C glitching by using input mode for od_high.Damien George
Certain pins (eg 4 and 5) seem to behave differently at the hardware level when in open-drain mode: they glitch when set "high" and drive the pin active high for a brief period before disabling the output driver. To work around this make the pin an input to let it float high.
2017-09-06all: Update Makefiles and others to build with new ports/ dir layout.Damien George
Also renames "stmhal" to "stm32" in documentation and everywhere else.
2017-09-06ports: Make new ports/ sub-directory and move all ports there.Damien George
This is to keep the top-level directory clean, to make it clear what is core and what is a port, and to allow the repository to grow with new ports in a sustainable way.