Initial Commit

18 files changed, 5565 insertions, 0 deletions

diff --git a/.cproject b/.cproject
new file mode 100644
index 0000000..4562a04
--- /dev/null
+++ b/.cproject
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>

+<?fileVersion 4.0.0?>

+

+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">

+	<storageModule moduleId="org.eclipse.cdt.core.settings">

+		<cconfiguration id="0.1403721915">

+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.1403721915" moduleId="org.eclipse.cdt.core.settings" name="Default">

+				<externalSettings/>

+				<extensions>

+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>

+					<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+				</extensions>

+			</storageModule>

+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">

+				<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.1403721915" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">

+					<folderInfo id="0.1403721915." name="/" resourcePath="">

+						<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1000277985" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">

+							<targetPlatform binaryParser="org.eclipse.cdt.core.GNU_ELF" id="org.eclipse.cdt.build.core.prefbase.toolchain.1000277985.872523937" name=""/>

+							<builder autoBuildTarget="all" cleanBuildTarget="clean" command="cs-make" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.814047191" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelizationNumber="1" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>

+							<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1912091070" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>

+							<tool id="org.eclipse.cdt.build.core.settings.holder.242947640" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">

+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1867917682" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>

+							</tool>

+							<tool id="org.eclipse.cdt.build.core.settings.holder.1754976794" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">

+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.948692194" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>

+							</tool>

+							<tool id="org.eclipse.cdt.build.core.settings.holder.11694915" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">

+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.323225267" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>

+							</tool>

+						</toolChain>

+					</folderInfo>

+				</configuration>

+			</storageModule>

+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>

+		</cconfiguration>

+	</storageModule>

+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">

+		<project id="lpc1114_blink_led.null.749871675" name="lpc1114_blink_led"/>

+	</storageModule>

+	<storageModule moduleId="refreshScope" versionNumber="1">

+		<resource resourceType="PROJECT" workspacePath="/lpc1114_blink_led"/>

+	</storageModule>

+	<storageModule moduleId="scannerConfiguration">

+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>

+		<scannerConfigBuildInfo instanceId="0.1403721915">

+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>

+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">

+				<buildOutputProvider>

+					<openAction enabled="true" filePath=""/>

+					<parser enabled="true"/>

+				</buildOutputProvider>

+				<scannerInfoProvider id="specsFile">

+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="arm-none-eabi-gcc" useDefault="true"/>

+					<parser enabled="true"/>

+				</scannerInfoProvider>

+			</profile>

+		</scannerConfigBuildInfo>

+	</storageModule>

+</cproject>

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..1533b36
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,19 @@
+# Object files
+*.o
+
+# Libraries
+*.lib
+*.a
+
+# Shared objects (inc. Windows DLLs)
+*.dll
+*.so
+*.so.*
+*.dylib
+
+# Executables
+*.exe
+*.out
+*.app
+
+out/
\ No newline at end of file
diff --git a/.project b/.project
new file mode 100644
index 0000000..2a239a0
--- /dev/null
+++ b/.project
@@ -0,0 +1,78 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<projectDescription>

+	<name>lpc1114_blink_led</name>

+	<comment></comment>

+	<projects>

+	</projects>

+	<buildSpec>

+		<buildCommand>

+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>

+			<triggers>clean,full,incremental,</triggers>

+			<arguments>

+				<dictionary>

+					<key>?name?</key>

+					<value></value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.append_environment</key>

+					<value>true</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>

+					<value>all</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.buildArguments</key>

+					<value></value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.buildCommand</key>

+					<value>cs-make</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>

+					<value>clean</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.contents</key>

+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>

+					<value>false</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>

+					<value>true</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>

+					<value>true</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>

+					<value>all</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.stopOnError</key>

+					<value>true</value>

+				</dictionary>

+				<dictionary>

+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>

+					<value>false</value>

+				</dictionary>

+			</arguments>

+		</buildCommand>

+		<buildCommand>

+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>

+			<triggers>full,incremental,</triggers>

+			<arguments>

+			</arguments>

+		</buildCommand>

+	</buildSpec>

+	<natures>

+		<nature>org.eclipse.cdt.core.cnature</nature>

+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>

+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>

+	</natures>

+</projectDescription>

diff --git a/LPC11x14_30x_rom.ld b/LPC11x14_30x_rom.ld
new file mode 100644
index 0000000..6aff0f1
--- /dev/null
+++ b/LPC11x14_30x_rom.ld
@@ -0,0 +1,260 @@
+/******************************************************************************

+* author: Freddie Chopin, http://www.freddiechopin.info/

+* file: LPC11x14_30x_rom.ld

+* last change: 2012-01-08

+*

+* chip: LPC11(C)14/30x

+* compiler: arm-none-eabi-gcc (Sourcery CodeBench Lite 2011.09-69) 4.6.1

+*

+* description:

+* Linker script for LPC11(C)14/30x (32kB Flash, 8kB SRAM).

+******************************************************************************/

+

+SEARCH_DIR(.);

+

+/*

++=============================================================================+

+| format configurations

++=============================================================================+

+*/

+

+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm");

+OUTPUT_ARCH(arm);

+

+/*

++=============================================================================+

+| stacks sizes

++=============================================================================+

+*/

+

+/* Handler mode (core exceptions / interrupts) can use only main stack */

+/* Thread mode can use main stack (default) or process stack - selected in CONTROL special register */

+

+__main_stack_size = 0;

+__process_stack_size = 1024;

+

+PROVIDE(__main_stack_size = __main_stack_size);

+PROVIDE(__process_stack_size = __process_stack_size);

+

+/*

++=============================================================================+

+| available memories definitions

++=============================================================================+

+*/

+

+MEMORY

+{

+	rom (rx)	: org = 0x00000000, len = 32k

+	ram (rwx)	: org = 0x10000000, len = 8k

+}

+

+__rom_start = ORIGIN(rom);

+__rom_size = LENGTH(rom);

+__rom_end = __rom_start + __rom_size;

+

+__ram_start = ORIGIN(ram);

+__ram_size = LENGTH(ram);

+__ram_end = __ram_start + __ram_size;

+

+PROVIDE(__rom_start = __rom_start);

+PROVIDE(__rom_size = __rom_size);

+PROVIDE(__rom_end = __rom_end);

+

+PROVIDE(__ram_start = __ram_start);

+PROVIDE(__ram_size = __ram_size);

+PROVIDE(__ram_end = __ram_end);

+

+/*

++=============================================================================+

+| entry point

++=============================================================================+

+*/

+

+ENTRY(Reset_Handler);

+

+/*

++=============================================================================+

+| put data in sections

++=============================================================================+

+*/

+

+SECTIONS

+{

+	.text :

+	{

+		. = ALIGN(4);

+		__text_start = .;

+		PROVIDE(__text_start = __text_start);

+

+		. = ALIGN(4);

+		KEEP(*(.vectors));

+		. = ALIGN(4);

+		*(.text .text.* .gnu.linkonce.t.*);

+		. = ALIGN(4);

+		*(.glue_7t .glue_7);

+		. = ALIGN(4);

+		*(.rodata .rodata.* .gnu.linkonce.r.*);

+

+		. = ALIGN(4);

+		*(.ARM.extab* .gnu.linkonce.armextab.*);	/* exception unwinding information */

+		. = ALIGN(4);

+		*(.gcc_except_table);						/* information used for stack unwinding during exception */

+		. = ALIGN(4);

+		*(.eh_frame_hdr);							/* additional information about .ex_frame section */

+		. = ALIGN(4);

+		*(.eh_frame);								/* information used for stack unwinding during exception */

+

+		. = ALIGN(4);

+		KEEP(*(.init));

+		. = ALIGN(4);

+		__preinit_array_start = .;

+		KEEP(*(.preinit_array));

+		. = ALIGN(4);

+		__preinit_array_end = .;

+		__init_array_start = .;

+		KEEP(*(SORT(.init_array.*)));

+		. = ALIGN(4);

+		KEEP(*(.init_array));

+		. = ALIGN(4);

+		__init_array_end = .;

+		KEEP(*(.fini));

+		. = ALIGN(4);

+		__fini_array_start = .;

+		KEEP(*(.fini_array));

+		. = ALIGN(4);

+		KEEP(*(SORT(.fini_array.*)));

+		. = ALIGN(4);

+		__fini_array_end = .;

+

+		. = ALIGN(4);

+		__text_end = .;

+		PROVIDE(__text_end = __text_end);

+	} > rom AT > rom

+

+	. = ALIGN(4);

+	__exidx_start = .;

+	PROVIDE(__exidx_start = __exidx_start);

+

+	.ARM.exidx :

+	{

+		*(.ARM.exidx* .gnu.linkonce.armexidx.*);

+	} > rom AT > rom								/* index entries for section unwinding */

+

+	. = ALIGN(4);

+	__exidx_end = .;

+	PROVIDE(__exidx_end = __exidx_end);

+

+	.data :

+	{

+		. = ALIGN(4);

+		__data_init_start = LOADADDR (.data);

+		PROVIDE(__data_init_start = __data_init_start);

+		__data_start = .;

+		PROVIDE(__data_start = __data_start);

+

+		. = ALIGN(4);

+		*(.data .data.* .gnu.linkonce.d.*)

+

+		. = ALIGN(4);

+		__data_end = .;

+		PROVIDE(__data_end = __data_end);

+	} > ram AT > rom

+

+	.bss :

+	{

+		. = ALIGN(4);

+		__bss_start = .;

+		PROVIDE(__bss_start = __bss_start);

+

+		. = ALIGN(4);

+		*(.bss .bss.* .gnu.linkonce.b.*)

+		. = ALIGN(4);

+		*(COMMON);

+

+		. = ALIGN(4);

+		__bss_end = .;

+		PROVIDE(__bss_end = __bss_end);

+	} > ram AT > ram

+

+	.stack :

+	{

+		. = ALIGN(8);

+		__stack_start = .;

+		PROVIDE(__stack_start = __stack_start);

+

+		. = ALIGN(8);

+		__main_stack_start = .;

+		PROVIDE(__main_stack_start = __main_stack_start);

+

+		. += __main_stack_size;

+

+		. = ALIGN(8);

+		__main_stack_end = .;

+		PROVIDE(__main_stack_end = __main_stack_end);

+

+		. = ALIGN(8);

+		__process_stack_start = .;

+		PROVIDE(__process_stack_start = __process_stack_start);

+

+		. += __process_stack_size;

+

+		. = ALIGN(8);

+		__process_stack_end = .;

+		PROVIDE(__process_stack_end = __process_stack_end);

+

+		. = ALIGN(8);

+		__stack_end = .;

+		PROVIDE(__stack_end = __stack_end);

+	} > ram AT > ram

+

+	. = ALIGN(4);

+	__heap_start = .;

+	PROVIDE(__heap_start = __heap_start);

+

+	. = ALIGN(4);

+	__heap_end = __ram_end;

+	PROVIDE(__heap_end = __heap_end);

+

+	.stab 				0 (NOLOAD) : { *(.stab) }

+	.stabstr 			0 (NOLOAD) : { *(.stabstr) }

+	/* DWARF debug sections.

+	* Symbols in the DWARF debugging sections are relative to the beginning

+	* of the section so we begin them at 0. */

+	/* DWARF 1 */

+	.debug				0 : { *(.debug) }

+	.line				0 : { *(.line) }

+	/* GNU DWARF 1 extensions */

+	.debug_srcinfo		0 : { *(.debug_srcinfo) }

+	.debug_sfnames		0 : { *(.debug_sfnames) }

+	/* DWARF 1.1 and DWARF 2 */

+	.debug_aranges		0 : { *(.debug_aranges) }

+	.debug_pubnames		0 : { *(.debug_pubnames) }

+	/* DWARF 2 */

+	.debug_info			0 : { *(.debug_info .gnu.linkonce.wi.*) }

+	.debug_abbrev		0 : { *(.debug_abbrev) }

+	.debug_line			0 : { *(.debug_line) }

+	.debug_frame		0 : { *(.debug_frame) }

+	.debug_str			0 : { *(.debug_str) }

+	.debug_loc			0 : { *(.debug_loc) }

+	.debug_macinfo		0 : { *(.debug_macinfo) }

+	/* SGI/MIPS DWARF 2 extensions */

+	.debug_weaknames	0 : { *(.debug_weaknames) }

+	.debug_funcnames	0 : { *(.debug_funcnames) }

+	.debug_typenames	0 : { *(.debug_typenames) }

+	.debug_varnames		0 : { *(.debug_varnames) }

+

+	.note.gnu.arm.ident	0 : { KEEP(*(.note.gnu.arm.ident)) }

+	.ARM.attributes		0 : { KEEP(*(.ARM.attributes)) }

+	/DISCARD/				: { *(.note.GNU-stack) }

+}

+

+PROVIDE(__text_size = __text_end - __text_start);

+PROVIDE(__exidx_size = __exidx_end - __exidx_start);

+PROVIDE(__data_size = __data_end - __data_start);

+PROVIDE(__bss_size = __bss_end - __bss_start);

+PROVIDE(__stack_size = __stack_end - __stack_start);

+PROVIDE(__heap_size = __heap_end - __heap_start);

+

+/******************************************************************************

+* END OF FILE

+******************************************************************************/

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..2bc32f1
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,307 @@
+#=============================================================================#

+# ARM makefile

+#

+# author: Freddie Chopin, http://www.freddiechopin.info/

+# last change: 2012-01-08

+#

+# this makefile is based strongly on many examples found in the network

+#=============================================================================#

+

+#=============================================================================#

+# toolchain configuration

+#=============================================================================#

+

+TOOLCHAIN = arm-none-eabi-

+

+CXX = $(TOOLCHAIN)g++

+CC = $(TOOLCHAIN)gcc

+AS = $(TOOLCHAIN)gcc -x assembler-with-cpp

+OBJCOPY = $(TOOLCHAIN)objcopy

+OBJDUMP = $(TOOLCHAIN)objdump

+SIZE = $(TOOLCHAIN)size

+RM = cs-rm -f

+

+#=============================================================================#

+# project configuration

+#=============================================================================#

+

+# project name

+PROJECT = lpc1114_blink_led

+

+# core type

+CORE = cortex-m0

+

+# linker script

+LD_SCRIPT = LPC11x14_30x_rom.ld

+

+# output folder (absolute or relative path, leave empty for in-tree compilation)

+OUT_DIR = out

+

+# C++ definitions (e.g. "-Dsymbol_with_value=0xDEAD -Dsymbol_without_value")

+CXX_DEFS =

+

+# C definitions

+C_DEFS =

+

+# ASM definitions

+AS_DEFS =

+

+# include directories (absolute or relative paths to additional folders with

+# headers, current folder is always included)

+INC_DIRS =

+

+# library directories (absolute or relative paths to additional folders with

+# libraries)

+LIB_DIRS =

+

+# libraries (additional libraries for linking, e.g. "-lm -lsome_name" to link

+# math library libm.a and libsome_name.a)

+LIBS =

+

+# additional directories with source files (absolute or relative paths to

+# folders with source files, current folder is always included)

+SRCS_DIRS =

+

+# extension of C++ files

+CXX_EXT = cpp

+

+# wildcard for C++ source files (all files with CXX_EXT extension found in

+# current folder and SRCS_DIRS folders will be compiled and linked)

+CXX_SRCS = $(wildcard $(patsubst %, %/*.$(CXX_EXT), . $(SRCS_DIRS)))

+

+# extension of C files

+C_EXT = c

+

+# wildcard for C source files (all files with C_EXT extension found in current

+# folder and SRCS_DIRS folders will be compiled and linked)

+C_SRCS = $(wildcard $(patsubst %, %/*.$(C_EXT), . $(SRCS_DIRS)))

+

+# extension of ASM files

+AS_EXT = S

+

+# wildcard for ASM source files (all files with AS_EXT extension found in

+# current folder and SRCS_DIRS folders will be compiled and linked)

+AS_SRCS = $(wildcard $(patsubst %, %/*.$(AS_EXT), . $(SRCS_DIRS)))

+

+# optimization flags ("-O0" - no optimization, "-O1" - optimize, "-O2" -

+# optimize even more, "-Os" - optimize for size or "-O3" - optimize yet more) 

+OPTIMIZATION = -O0

+

+# set to 1 to optimize size by removing unused code and data during link phase

+REMOVE_UNUSED = 1

+

+# set to 1 to compile and link additional code required for C++

+USES_CXX = 0

+

+# define warning options here

+CXX_WARNINGS = -Wall -Wextra

+C_WARNINGS = -Wall -Wstrict-prototypes -Wextra

+

+# C++ language standard ("c++98", "gnu++98" - default, "c++0x", "gnu++0x")

+CXX_STD = gnu++98

+

+# C language standard ("c89" / "iso9899:1990", "iso9899:199409",

+# "c99" / "iso9899:1999", "gnu89" - default, "gnu99")

+C_STD = gnu89

+

+#=============================================================================#

+# set the VPATH according to SRCS_DIRS

+#=============================================================================#

+

+VPATH = $(SRCS_DIRS)

+

+#=============================================================================#

+# when using output folder, append trailing slash to its name

+#=============================================================================#

+

+ifeq ($(strip $(OUT_DIR)), )

+	OUT_DIR_F =

+else

+	OUT_DIR_F = $(strip $(OUT_DIR))/

+endif

+

+#=============================================================================#

+# various compilation flags

+#=============================================================================#

+

+# core flags

+CORE_FLAGS = -mcpu=$(CORE) -mthumb

+

+# flags for C++ compiler

+CXX_FLAGS = -std=$(CXX_STD) -g -ggdb3 -fno-rtti -fno-exceptions -fverbose-asm -Wa,-ahlms=$(OUT_DIR_F)$(notdir $(<:.$(CXX_EXT)=.lst))

+

+# flags for C compiler

+C_FLAGS = -std=$(C_STD) -g -ggdb3 -fverbose-asm -Wa,-ahlms=$(OUT_DIR_F)$(notdir $(<:.$(C_EXT)=.lst))

+

+# flags for assembler

+AS_FLAGS = -g -ggdb3 -Wa,-amhls=$(OUT_DIR_F)$(notdir $(<:.$(AS_EXT)=.lst))

+

+# flags for linker

+LD_FLAGS = -T$(LD_SCRIPT) -g -Wl,-Map=$(OUT_DIR_F)$(PROJECT).map,--cref,--no-warn-mismatch

+

+# process option for removing unused code

+ifeq ($(REMOVE_UNUSED), 1)

+	LD_FLAGS += -Wl,--gc-sections

+	OPTIMIZATION += -ffunction-sections -fdata-sections

+endif

+

+# if __USES_CXX is defined for ASM then code for global/static constructors /

+# destructors is compiled; if -nostartfiles option for linker is added then C++

+# initialization / finalization code is not linked

+ifeq ($(USES_CXX), 1)

+	AS_DEFS += -D__USES_CXX

+else

+	LD_FLAGS += -nostartfiles

+endif

+

+#=============================================================================#

+# do some formatting

+#=============================================================================#

+

+CXX_OBJS = $(addprefix $(OUT_DIR_F), $(notdir $(CXX_SRCS:.$(CXX_EXT)=.o)))

+C_OBJS = $(addprefix $(OUT_DIR_F), $(notdir $(C_SRCS:.$(C_EXT)=.o)))

+AS_OBJS = $(addprefix $(OUT_DIR_F), $(notdir $(AS_SRCS:.$(AS_EXT)=.o)))

+OBJS = $(AS_OBJS) $(C_OBJS) $(CXX_OBJS) $(USER_OBJS)

+DEPS = $(OBJS:.o=.d)

+INC_DIRS_F = -I. $(patsubst %, -I%, $(INC_DIRS))

+LIB_DIRS_F = $(patsubst %, -L%, $(LIB_DIRS))

+

+ELF = $(OUT_DIR_F)$(PROJECT).elf

+HEX = $(OUT_DIR_F)$(PROJECT).hex

+BIN = $(OUT_DIR_F)$(PROJECT).bin

+LSS = $(OUT_DIR_F)$(PROJECT).lss

+DMP = $(OUT_DIR_F)$(PROJECT).dmp

+

+# format final flags for tools, request dependancies for C++, C and asm

+CXX_FLAGS_F = $(CORE_FLAGS) $(OPTIMIZATION) $(CXX_WARNINGS) $(CXX_FLAGS)  $(CXX_DEFS) -MD -MP -MF $(OUT_DIR_F)$(@F:.o=.d) $(INC_DIRS_F)

+C_FLAGS_F = $(CORE_FLAGS) $(OPTIMIZATION) $(C_WARNINGS) $(C_FLAGS) $(C_DEFS) -MD -MP -MF $(OUT_DIR_F)$(@F:.o=.d) $(INC_DIRS_F)

+AS_FLAGS_F = $(CORE_FLAGS) $(AS_FLAGS) $(AS_DEFS) -MD -MP -MF $(OUT_DIR_F)$(@F:.o=.d) $(INC_DIRS_F)

+LD_FLAGS_F = $(CORE_FLAGS) $(LD_FLAGS) $(LIB_DIRS_F)

+

+#contents of output directory

+GENERATED = $(wildcard $(patsubst %, $(OUT_DIR_F)*.%, bin d dmp elf hex lss lst map o))

+

+#=============================================================================#

+# make all

+#=============================================================================#

+

+all : make_output_dir $(ELF) $(LSS) $(DMP) $(HEX) $(BIN) print_size

+

+# make object files dependent on Makefile

+$(OBJS) : Makefile

+# make .elf file dependent on linker script

+$(ELF) : $(LD_SCRIPT)

+

+#-----------------------------------------------------------------------------#

+# linking - objects -> elf

+#-----------------------------------------------------------------------------#

+

+$(ELF) : $(OBJS)

+	@echo 'Linking target: $(ELF)'

+	$(CXX) $(LD_FLAGS_F) $(OBJS) $(LIBS) -o $@

+	@echo ' '

+

+#-----------------------------------------------------------------------------#

+# compiling - C++ source -> objects

+#-----------------------------------------------------------------------------#

+

+$(OUT_DIR_F)%.o : %.$(CXX_EXT)

+	@echo 'Compiling file: $<'

+	$(CXX) -c $(CXX_FLAGS_F) $< -o $@

+	@echo ' '

+

+#-----------------------------------------------------------------------------#

+# compiling - C source -> objects

+#-----------------------------------------------------------------------------#

+

+$(OUT_DIR_F)%.o : %.$(C_EXT)

+	@echo 'Compiling file: $<'

+	$(CC) -c $(C_FLAGS_F) $< -o $@

+	@echo ' '

+

+#-----------------------------------------------------------------------------#

+# assembling - ASM source -> objects

+#-----------------------------------------------------------------------------#

+

+$(OUT_DIR_F)%.o : %.$(AS_EXT)

+	@echo 'Assembling file: $<'

+	$(AS) -c $(AS_FLAGS_F) $< -o $@

+	@echo ' '

+

+#-----------------------------------------------------------------------------#

+# memory images - elf -> hex, elf -> bin

+#-----------------------------------------------------------------------------#

+

+$(HEX) : $(ELF)

+	@echo 'Creating IHEX image: $(HEX)'

+	$(OBJCOPY) -O ihex $< $@

+	@echo ' '

+

+$(BIN) : $(ELF)

+	@echo 'Creating binary image: $(BIN)'

+	$(OBJCOPY) -O binary $< $@

+	@echo ' '

+

+#-----------------------------------------------------------------------------#

+# memory dump - elf -> dmp

+#-----------------------------------------------------------------------------#

+

+$(DMP) : $(ELF)

+	@echo 'Creating memory dump: $(DMP)'

+	$(OBJDUMP) -x --syms $< > $@

+	@echo ' '

+

+#-----------------------------------------------------------------------------#

+# extended listing - elf -> lss

+#-----------------------------------------------------------------------------#

+

+$(LSS) : $(ELF)

+	@echo 'Creating extended listing: $(LSS)'

+	$(OBJDUMP) -S $< > $@

+	@echo ' '

+

+#-----------------------------------------------------------------------------#

+# print the size of the objects and the .elf file

+#-----------------------------------------------------------------------------#

+

+print_size :

+	@echo 'Size of modules:'

+	$(SIZE) -B -t --common $(OBJS) $(USER_OBJS)

+	@echo ' '

+	@echo 'Size of target .elf file:'

+	$(SIZE) -B $(ELF)

+	@echo ' '

+

+#-----------------------------------------------------------------------------#

+# create the desired output directory

+#-----------------------------------------------------------------------------#

+

+make_output_dir :

+	$(shell mkdir $(OUT_DIR_F) 2>/dev/null)

+

+#=============================================================================#

+# make clean

+#=============================================================================#

+

+clean:

+ifeq ($(strip $(OUT_DIR_F)), )

+	@echo 'Removing all generated output files'

+else

+	@echo 'Removing all generated output files from output directory: $(OUT_DIR_F)'

+endif

+ifneq ($(strip $(GENERATED)), )

+	$(RM) $(GENERATED)

+else

+	@echo 'Nothing to remove...'

+endif

+

+#=============================================================================#

+# global exports

+#=============================================================================#

+

+.PHONY: all clean dependents

+

+.SECONDARY:

+

+# include dependancy files

+-include $(DEPS)

diff --git a/config.h b/config.h
new file mode 100644
index 0000000..a107314
--- /dev/null
+++ b/config.h
@@ -0,0 +1,57 @@
+/** \file config.h

+ * \brief Basic configuration of the project

+ * \author Freddie Chopin, http://www.freddiechopin.info/

+ * \date 2012-01-08

+ */

+

+/******************************************************************************

+* project: lpc1114_blink_led

+* chip: LPC1114

+* compiler: arm-none-eabi-gcc (Sourcery CodeBench Lite 2011.09-69) 4.6.1

+******************************************************************************/

+

+#ifndef CONFIG_H_

+#define CONFIG_H_

+

+#include "hdr/hdr_gpio_masked_access.h"

+

+/*

++=============================================================================+

+| global definitions

++=============================================================================+

+*/

+

+#define CRYSTAL								12000000	///< quartz crystal resonator which is connected to the chip

+#define FREQUENCY							50000000	///< desired target frequency of the core

+

+#define LED_GPIO							LPC_GPIO1	///< GPIO port to which the LED is connected

+

+#define LED_pin								8			///< pin number of the LED

+

+#define LED									(1 << LED_pin)

+

+/// "variable" to manipulate the pin directly via GPIO masked access

+#define LED_gma								gpio_masked_access_t GPIO_MASKED_ACCESS(LED_GPIO, LED_pin)

+

+/*

++=============================================================================+

+| strange variables

++=============================================================================+

+*/

+

+/*

++=============================================================================+

+| global variables

++=============================================================================+

+*/

+

+/*

++=============================================================================+

+| global functions' declarations

++=============================================================================+

+*/

+

+/******************************************************************************

+* END OF FILE

+******************************************************************************/

+#endif /* CONFIG_H_ */

diff --git a/hdr/hdr_gpio_masked_access.h b/hdr/hdr_gpio_masked_access.h
new file mode 100644
index 0000000..3920af5
--- /dev/null
+++ b/hdr/hdr_gpio_masked_access.h
@@ -0,0 +1,75 @@
+/** \file hdr_gpio_masked_access.h

+ * \brief Header for GPIO masked access in LPC11xx

+ * \details This header contains definitions necessary for using GPIO masked

+ * access feature of LPC11xx chips. GPIO masked access gives you the ability to

+ * set the state of single GPIO pin (or group of pins) without affecting other

+ * pins of the same port, avoiding possible read-modify-store problems. It is

+ * also possible to use GPIO masked access to get the state of single GPIO pin

+ * (or group of pins) without any masking (single read operation).

+ *

+ * To use this mechanism in an convenient way add three definitions to your

+ * code (in the example PIO1_5 (port 1, pin 5) is used):

+ * - #define SOMETHING_GPIO LPC_GPIO1 // GPIO port of the pin

+ * - #define SOMETHING_pin 5 // number of the pin

+ * - #define SOMETHING (1 << SOMETHING_pin) // bit mask

+ *

+ * Then you can define a GPIO masked access "variable" using the macros from

+ * this header:

+ * - #define SOMETHING_gma gpio_masked_access_t GPIO_MASKED_ACCESS(SOMETHING_GPIO, SOMETHING_pin)

+ *

+ * Changing the state of the pin is then very simple:

+ * - SOMETHING_gma = 0;			// pin state == 0

+ * - SOMETHING_gma = SOMETHING;	// pin state == 1

+ *

+ * To set pin state to 0 you can actually write any number that has binary 0 on

+ * SOMETHING_pin bit, so these are equivalent:

+ * - SOMETHING_gma = 0;

+ * - SOMETHING_gma = ANYTHING & ~(SOMETHING);

+ * - SOMETHING_gma = 0xFFFFFFFF & ~(SOMETHING);

+ * - ...

+ *

+ * The same is true for setting pin state to 1, so these are also equivalent:

+ * - SOMETHING_gma = SOMETHING;

+ * - SOMETHING_gma = SOMETHING | ANYTHING;

+ * - SOMETHING_gma = 0xFFFFFFFF;

+ * - ...

+ *

+ * You can also get the state of the pin by reading this "variable":

+ * - uint32_t state_of_pin = SOMETHING_gma; // if pin state == 0, state_of_pin == 0, otherwise state_of_pin == SOMETHING

+ *

+ * \author Freddie Chopin, http://www.freddiechopin.info/

+ * \date 2012-01-08

+ */

+

+/******************************************************************************

+* chip: LPC11xx

+* compiler: arm-none-eabi-gcc (Sourcery CodeBench Lite 2011.09-69) 4.6.1

+******************************************************************************/

+

+#ifndef HDR_GPIO_MASKED_ACCESS_H_

+#define HDR_GPIO_MASKED_ACCESS_H_

+

+#include <stdint.h>

+

+/*

++=============================================================================+

+| strange variables

++=============================================================================+

+*/

+

+/// GPIO masked access "variable" type

+#define gpio_masked_access_t				*(volatile uint32_t*)

+

+/*

++=============================================================================+

+| macros

++=============================================================================+

+*/

+

+/// macro used to calculate the address on the bus that is used to access selected pin

+#define GPIO_MASKED_ACCESS(gpio, pin)		((uint32_t)gpio + (1 << (pin + 2)))

+

+/******************************************************************************

+* END OF FILE

+******************************************************************************/

+#endif /* HDR_GPIO_MASKED_ACCESS_H_ */

diff --git a/hdr/hdr_special_registers.h b/hdr/hdr_special_registers.h
new file mode 100644
index 0000000..d4328b7
--- /dev/null
+++ b/hdr/hdr_special_registers.h
@@ -0,0 +1,38 @@
+/** \file hdr_special_registers.h

+ * \brief Header with definition of bits in special registers in ARMv6-M core

+ * \author Freddie Chopin, http://www.freddiechopin.info/

+ * \date 2012-01-08

+ */

+

+/******************************************************************************

+* chip: ARMv6-M (Cortex-M0)

+* compiler: arm-none-eabi-gcc (Sourcery CodeBench Lite 2011.09-69) 4.6.1

+******************************************************************************/

+

+#ifndef HDR_SPECIAL_REGISTERS_H_

+#define HDR_SPECIAL_REGISTERS_H_

+

+/*

++-----------------------------------------------------------------------------+

+| PRIMASK - Register to mask out configurable exceptions

++-----------------------------------------------------------------------------+

+*/

+

+#define PRIMASK_MASK_EXCEPTIONS_bit			0

+

+#define PRIMASK_MASK_EXCEPTIONS				(1 << PRIMASK_MASK_EXCEPTIONS_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| CONTROL - The special-purpose control register

++-----------------------------------------------------------------------------+

+*/

+

+#define CONTROL_ALTERNATE_STACK_bit			1

+

+#define CONTROL_ALTERNATE_STACK				(1 << CONTROL_ALTERNATE_STACK_bit)

+

+/******************************************************************************

+* END OF FILE

+******************************************************************************/

+#endif /* HDR_SPECIAL_REGISTERS_H_ */

diff --git a/hdr/hdr_syscon.h b/hdr/hdr_syscon.h
new file mode 100644
index 0000000..f74ebf5
--- /dev/null
+++ b/hdr/hdr_syscon.h
@@ -0,0 +1,1159 @@
+/** \file hdr_syscon.h

+ * \brief Header with definition of bits in system configuration registers

+ * \author Freddie Chopin, http://www.freddiechopin.info/

+ * \date 2012-01-08

+ */

+

+/******************************************************************************

+* chip: LPC11xx

+* compiler: arm-none-eabi-gcc (Sourcery CodeBench Lite 2011.09-69) 4.6.1

+******************************************************************************/

+

+#ifndef HDR_SYSCON_H_

+#define HDR_SYSCON_H_

+

+/*

++-----------------------------------------------------------------------------+

+| SYSMEMREMAP - System memory remap register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSMEMREMAP_MAP_bit					0

+#define SYSMEMREMAP_MAP_0_bit				0

+#define SYSMEMREMAP_MAP_1_bit				1

+

+#define SYSMEMREMAP_MAP_0					(1 << SYSMEMREMAP_MAP_0_bit)

+#define SYSMEMREMAP_MAP_1					(1 << SYSMEMREMAP_MAP_1_bit)

+

+#define SYSMEMREMAP_MAP_BOOT_value			0

+#define SYSMEMREMAP_MAP_RAM_value			1

+#define SYSMEMREMAP_MAP_FLASH_value			2

+#define SYSMEMREMAP_MAP_mask				3

+

+#define SYSMEMREMAP_MAP_BOOT				(SYSMEMREMAP_MAP_BOOT_value << SYSMEMREMAP_MAP_bit)

+#define SYSMEMREMAP_MAP_RAM					(SYSMEMREMAP_MAP_RAM_value << SYSMEMREMAP_MAP_bit)

+#define SYSMEMREMAP_MAP_FLASH				(SYSMEMREMAP_MAP_FLASH_value << SYSMEMREMAP_MAP_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| PRESETCTRL - Peripheral reset control register

++-----------------------------------------------------------------------------+

+*/

+

+#define PRESETCTRL_SSP0_RST_N_bit			0

+#define PRESETCTRL_I2C_RST_N_bit			1

+#define PRESETCTRL_SSP1_RST_N_bit			2

+#define PRESETCTRL_CAN_RST_N_bit			3

+

+#define PRESETCTRL_SSP0_RST_N				(1 << PRESETCTRL_SSP0_RST_N_bit)

+#define PRESETCTRL_I2C_RST_N				(1 << PRESETCTRL_I2C_RST_N_bit)

+#define PRESETCTRL_SSP1_RST_N				(1 << PRESETCTRL_SSP1_RST_N_bit)

+#define PRESETCTRL_CAN_RST_N				(1 << PRESETCTRL_CAN_RST_N_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSPLLCTRL - System PLL control register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSPLLCTRL_MSEL_bit					0

+#define SYSPLLCTRL_MSEL_0_bit				0

+#define SYSPLLCTRL_MSEL_1_bit				1

+#define SYSPLLCTRL_MSEL_2_bit				2

+#define SYSPLLCTRL_MSEL_3_bit				3

+#define SYSPLLCTRL_MSEL_4_bit				4

+#define SYSPLLCTRL_PSEL_bit					5

+#define SYSPLLCTRL_PSEL_0_bit				5

+#define SYSPLLCTRL_PSEL_1_bit				6

+

+#define SYSPLLCTRL_MSEL_0					(1 << SYSPLLCTRL_MSEL_0_bit)

+#define SYSPLLCTRL_MSEL_1					(1 << SYSPLLCTRL_MSEL_1_bit)

+#define SYSPLLCTRL_MSEL_2					(1 << SYSPLLCTRL_MSEL_2_bit)

+#define SYSPLLCTRL_MSEL_3					(1 << SYSPLLCTRL_MSEL_3_bit)

+#define SYSPLLCTRL_MSEL_4					(1 << SYSPLLCTRL_MSEL_4_bit)

+#define SYSPLLCTRL_PSEL_0					(1 << SYSPLLCTRL_PSEL_0_bit)

+#define SYSPLLCTRL_PSEL_1					(1 << SYSPLLCTRL_PSEL_1_bit)

+

+#define SYSPLLCTRL_MSEL_1_value				0

+#define SYSPLLCTRL_MSEL_2_value				1

+#define SYSPLLCTRL_MSEL_3_value				2

+#define SYSPLLCTRL_MSEL_4_value				3

+#define SYSPLLCTRL_MSEL_5_value				4

+#define SYSPLLCTRL_MSEL_6_value				5

+#define SYSPLLCTRL_MSEL_7_value				6

+#define SYSPLLCTRL_MSEL_8_value				7

+#define SYSPLLCTRL_MSEL_9_value				8

+#define SYSPLLCTRL_MSEL_10_value			9

+#define SYSPLLCTRL_MSEL_11_value			10

+#define SYSPLLCTRL_MSEL_12_value			11

+#define SYSPLLCTRL_MSEL_13_value			12

+#define SYSPLLCTRL_MSEL_14_value			13

+#define SYSPLLCTRL_MSEL_15_value			14

+#define SYSPLLCTRL_MSEL_16_value			15

+#define SYSPLLCTRL_MSEL_17_value			16

+#define SYSPLLCTRL_MSEL_18_value			17

+#define SYSPLLCTRL_MSEL_19_value			18

+#define SYSPLLCTRL_MSEL_20_value			19

+#define SYSPLLCTRL_MSEL_21_value			20

+#define SYSPLLCTRL_MSEL_22_value			21

+#define SYSPLLCTRL_MSEL_23_value			22

+#define SYSPLLCTRL_MSEL_24_value			23

+#define SYSPLLCTRL_MSEL_25_value			24

+#define SYSPLLCTRL_MSEL_26_value			25

+#define SYSPLLCTRL_MSEL_27_value			26

+#define SYSPLLCTRL_MSEL_28_value			27

+#define SYSPLLCTRL_MSEL_29_value			28

+#define SYSPLLCTRL_MSEL_30_value			29

+#define SYSPLLCTRL_MSEL_31_value			30

+#define SYSPLLCTRL_MSEL_32_value			31

+#define SYSPLLCTRL_MSEL_mask				31

+

+#define SYSPLLCTRL_PSEL_1_value				0

+#define SYSPLLCTRL_PSEL_2_value				1

+#define SYSPLLCTRL_PSEL_4_value				2

+#define SYSPLLCTRL_PSEL_8_value				3

+#define SYSPLLCTRL_PSEL_mask				3

+

+// underscores removed to avoid redefinition

+

+#define SYSPLLCTRL_MSEL1					(SYSPLLCTRL_MSEL_1_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL2					(SYSPLLCTRL_MSEL_2_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL3					(SYSPLLCTRL_MSEL_3_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL4					(SYSPLLCTRL_MSEL_4_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL5					(SYSPLLCTRL_MSEL_5_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL6					(SYSPLLCTRL_MSEL_6_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL7					(SYSPLLCTRL_MSEL_7_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL8					(SYSPLLCTRL_MSEL_8_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL9					(SYSPLLCTRL_MSEL_9_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL10					(SYSPLLCTRL_MSEL_10_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL11					(SYSPLLCTRL_MSEL_11_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL12					(SYSPLLCTRL_MSEL_12_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL13					(SYSPLLCTRL_MSEL_13_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL14					(SYSPLLCTRL_MSEL_14_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL15					(SYSPLLCTRL_MSEL_15_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL16					(SYSPLLCTRL_MSEL_16_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL17					(SYSPLLCTRL_MSEL_17_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL18					(SYSPLLCTRL_MSEL_18_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL19					(SYSPLLCTRL_MSEL_19_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL20					(SYSPLLCTRL_MSEL_20_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL21					(SYSPLLCTRL_MSEL_21_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL22					(SYSPLLCTRL_MSEL_22_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL23					(SYSPLLCTRL_MSEL_23_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL24					(SYSPLLCTRL_MSEL_24_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL25					(SYSPLLCTRL_MSEL_25_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL26					(SYSPLLCTRL_MSEL_26_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL27					(SYSPLLCTRL_MSEL_27_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL28					(SYSPLLCTRL_MSEL_28_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL29					(SYSPLLCTRL_MSEL_29_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL30					(SYSPLLCTRL_MSEL_30_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL31					(SYSPLLCTRL_MSEL_31_value << SYSPLLCTRL_MSEL_bit)

+#define SYSPLLCTRL_MSEL32					(SYSPLLCTRL_MSEL_32_value << SYSPLLCTRL_MSEL_bit)

+

+// underscores removed to avoid redefinition

+

+#define SYSPLLCTRL_PSEL1					(SYSPLLCTRL_PSEL_1_value << SYSPLLCTRL_PSEL_bit)

+#define SYSPLLCTRL_PSEL2					(SYSPLLCTRL_PSEL_2_value << SYSPLLCTRL_PSEL_bit)

+#define SYSPLLCTRL_PSEL4					(SYSPLLCTRL_PSEL_4_value << SYSPLLCTRL_PSEL_bit)

+#define SYSPLLCTRL_PSEL8					(SYSPLLCTRL_PSEL_8_value << SYSPLLCTRL_PSEL_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSPLLSTAT - System PLL status register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSPLLSTAT_LOCK_bit					0

+

+#define SYSPLLSTAT_LOCK						(1 << SYSPLLSTAT_LOCK_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSOSCCTRL - System oscillator control register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSOSCCTRL_BYPASS_bit				0

+#define SYSOSCCTRL_FREQRANGE_bit			1

+

+#define SYSOSCCTRL_BYPASS					(1 << SYSOSCCTRL_BYPASS_bit)

+#define SYSOSCCTRL_FREQRANGE				(1 << SYSOSCCTRL_FREQRANGE_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| WDTOSCCTRL - Watchdog oscillator control register

++-----------------------------------------------------------------------------+

+*/

+

+#define WDTOSCCTRL_DIVSEL_bit				0

+#define WDTOSCCTRL_DIVSEL_0_bit				0

+#define WDTOSCCTRL_DIVSEL_1_bit				1

+#define WDTOSCCTRL_DIVSEL_2_bit				2

+#define WDTOSCCTRL_DIVSEL_3_bit				3

+#define WDTOSCCTRL_DIVSEL_4_bit				4

+#define WDTOSCCTRL_FREQSEL_bit				5

+#define WDTOSCCTRL_FREQSEL_0_bit			5

+#define WDTOSCCTRL_FREQSEL_1_bit			6

+#define WDTOSCCTRL_FREQSEL_2_bit			7

+#define WDTOSCCTRL_FREQSEL_3_bit			8

+

+#define WDTOSCCTRL_DIVSEL_0					(1 << WDTOSCCTRL_DIVSEL_0_bit)

+#define WDTOSCCTRL_DIVSEL_1					(1 << WDTOSCCTRL_DIVSEL_1_bit)

+#define WDTOSCCTRL_DIVSEL_2					(1 << WDTOSCCTRL_DIVSEL_2_bit)

+#define WDTOSCCTRL_DIVSEL_3					(1 << WDTOSCCTRL_DIVSEL_3_bit)

+#define WDTOSCCTRL_DIVSEL_4					(1 << WDTOSCCTRL_DIVSEL_4_bit)

+#define WDTOSCCTRL_FREQSEL_0				(1 << WDTOSCCTRL_FREQSEL_0_bit)

+#define WDTOSCCTRL_FREQSEL_1				(1 << WDTOSCCTRL_FREQSEL_1_bit)

+#define WDTOSCCTRL_FREQSEL_2				(1 << WDTOSCCTRL_FREQSEL_2_bit)

+#define WDTOSCCTRL_FREQSEL_3				(1 << WDTOSCCTRL_FREQSEL_3_bit)

+

+#define WDTOSCCTRL_DIVSEL_2_value			0

+#define WDTOSCCTRL_DIVSEL_4_value			1

+#define WDTOSCCTRL_DIVSEL_6_value			2

+#define WDTOSCCTRL_DIVSEL_8_value			3

+#define WDTOSCCTRL_DIVSEL_10_value			4

+#define WDTOSCCTRL_DIVSEL_12_value			5

+#define WDTOSCCTRL_DIVSEL_14_value			6

+#define WDTOSCCTRL_DIVSEL_16_value			7

+#define WDTOSCCTRL_DIVSEL_18_value			8

+#define WDTOSCCTRL_DIVSEL_20_value			9

+#define WDTOSCCTRL_DIVSEL_22_value			10

+#define WDTOSCCTRL_DIVSEL_24_value			11

+#define WDTOSCCTRL_DIVSEL_26_value			12

+#define WDTOSCCTRL_DIVSEL_28_value			13

+#define WDTOSCCTRL_DIVSEL_30_value			14

+#define WDTOSCCTRL_DIVSEL_32_value			15

+#define WDTOSCCTRL_DIVSEL_34_value			16

+#define WDTOSCCTRL_DIVSEL_36_value			17

+#define WDTOSCCTRL_DIVSEL_38_value			18

+#define WDTOSCCTRL_DIVSEL_40_value			19

+#define WDTOSCCTRL_DIVSEL_42_value			20

+#define WDTOSCCTRL_DIVSEL_44_value			21

+#define WDTOSCCTRL_DIVSEL_46_value			22

+#define WDTOSCCTRL_DIVSEL_48_value			23

+#define WDTOSCCTRL_DIVSEL_50_value			24

+#define WDTOSCCTRL_DIVSEL_52_value			25

+#define WDTOSCCTRL_DIVSEL_54_value			26

+#define WDTOSCCTRL_DIVSEL_56_value			27

+#define WDTOSCCTRL_DIVSEL_58_value			28

+#define WDTOSCCTRL_DIVSEL_60_value			29

+#define WDTOSCCTRL_DIVSEL_62_value			30

+#define WDTOSCCTRL_DIVSEL_64_value			31

+#define WDTOSCCTRL_DIVSEL_mask				31

+

+#define WDTOSCCTRL_FREQSEL_500kHz_value		1

+#define WDTOSCCTRL_FREQSEL_800kHz_value		2

+#define WDTOSCCTRL_FREQSEL_1100kHz_value	3

+#define WDTOSCCTRL_FREQSEL_1400kHz_value	4

+#define WDTOSCCTRL_FREQSEL_1600kHz_value	5

+#define WDTOSCCTRL_FREQSEL_1800kHz_value	6

+#define WDTOSCCTRL_FREQSEL_2000kHz_value	7

+#define WDTOSCCTRL_FREQSEL_2200kHz_value	8

+#define WDTOSCCTRL_FREQSEL_2400kHz_value	9

+#define WDTOSCCTRL_FREQSEL_2600kHz_value	10

+#define WDTOSCCTRL_FREQSEL_2700kHz_value	11

+#define WDTOSCCTRL_FREQSEL_2900kHz_value	12

+#define WDTOSCCTRL_FREQSEL_3100kHz_value	13

+#define WDTOSCCTRL_FREQSEL_3200kHz_value	14

+#define WDTOSCCTRL_FREQSEL_3400kHz_value	15

+#define WDTOSCCTRL_FREQSEL_mask				15

+

+// underscores removed to avoid redefinition

+

+#define WDTOSCCTRL_DIVSEL2					(WDTOSCCTRL_DIVSEL_2_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL4					(WDTOSCCTRL_DIVSEL_4_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL6					(WDTOSCCTRL_DIVSEL_6_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL8					(WDTOSCCTRL_DIVSEL_8_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL10					(WDTOSCCTRL_DIVSEL_10_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL12					(WDTOSCCTRL_DIVSEL_12_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL14					(WDTOSCCTRL_DIVSEL_14_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL16					(WDTOSCCTRL_DIVSEL_16_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL18					(WDTOSCCTRL_DIVSEL_18_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL20					(WDTOSCCTRL_DIVSEL_20_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL22					(WDTOSCCTRL_DIVSEL_22_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL24					(WDTOSCCTRL_DIVSEL_24_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL26					(WDTOSCCTRL_DIVSEL_26_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL28					(WDTOSCCTRL_DIVSEL_28_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL30					(WDTOSCCTRL_DIVSEL_30_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL32					(WDTOSCCTRL_DIVSEL_32_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL34					(WDTOSCCTRL_DIVSEL_34_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL36					(WDTOSCCTRL_DIVSEL_36_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL38					(WDTOSCCTRL_DIVSEL_38_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL40					(WDTOSCCTRL_DIVSEL_40_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL42					(WDTOSCCTRL_DIVSEL_42_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL44					(WDTOSCCTRL_DIVSEL_44_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL46					(WDTOSCCTRL_DIVSEL_46_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL48					(WDTOSCCTRL_DIVSEL_48_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL50					(WDTOSCCTRL_DIVSEL_50_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL52					(WDTOSCCTRL_DIVSEL_52_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL54					(WDTOSCCTRL_DIVSEL_54_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL56					(WDTOSCCTRL_DIVSEL_56_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL58					(WDTOSCCTRL_DIVSEL_58_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL60					(WDTOSCCTRL_DIVSEL_60_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL62					(WDTOSCCTRL_DIVSEL_62_value << WDTOSCCTRL_DIVSEL_bit)

+#define WDTOSCCTRL_DIVSEL64					(WDTOSCCTRL_DIVSEL_64_value << WDTOSCCTRL_DIVSEL_bit)

+

+#define WDTOSCCTRL_FREQSEL_500kHz			(WDTOSCCTRL_FREQSEL_500kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_800kHz			(WDTOSCCTRL_FREQSEL_800kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_1100kHz			(WDTOSCCTRL_FREQSEL_1100kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_1400kHz			(WDTOSCCTRL_FREQSEL_1400kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_1600kHz			(WDTOSCCTRL_FREQSEL_1600kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_1800kHz			(WDTOSCCTRL_FREQSEL_1800kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_2000kHz			(WDTOSCCTRL_FREQSEL_2000kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_2200kHz			(WDTOSCCTRL_FREQSEL_2200kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_2400kHz			(WDTOSCCTRL_FREQSEL_2400kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_2600kHz			(WDTOSCCTRL_FREQSEL_2600kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_2700kHz			(WDTOSCCTRL_FREQSEL_2700kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_2900kHz			(WDTOSCCTRL_FREQSEL_2900kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_3100kHz			(WDTOSCCTRL_FREQSEL_3100kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_3200kHz			(WDTOSCCTRL_FREQSEL_3200kHz_value << WDTOSCCTRL_FREQSEL_bit)

+#define WDTOSCCTRL_FREQSEL_3400kHz			(WDTOSCCTRL_FREQSEL_3400kHz_value << WDTOSCCTRL_FREQSEL_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| IRCCTRL - Internal resonant crystal control register

++-----------------------------------------------------------------------------+

+*/

+

+#define IRCCTRL_TRIM_bit					0

+#define IRCCTRL_TRIM_0_bit					0

+#define IRCCTRL_TRIM_1_bit					1

+#define IRCCTRL_TRIM_2_bit					2

+#define IRCCTRL_TRIM_3_bit					3

+#define IRCCTRL_TRIM_4_bit					4

+#define IRCCTRL_TRIM_5_bit					5

+#define IRCCTRL_TRIM_6_bit					6

+#define IRCCTRL_TRIM_7_bit					7

+

+#define IRCCTRL_TRIM_0						(1 << IRCCTRL_TRIM_0_bit)

+#define IRCCTRL_TRIM_1						(1 << IRCCTRL_TRIM_1_bit)

+#define IRCCTRL_TRIM_2						(1 << IRCCTRL_TRIM_2_bit)

+#define IRCCTRL_TRIM_3						(1 << IRCCTRL_TRIM_3_bit)

+#define IRCCTRL_TRIM_4						(1 << IRCCTRL_TRIM_4_bit)

+#define IRCCTRL_TRIM_5						(1 << IRCCTRL_TRIM_5_bit)

+#define IRCCTRL_TRIM_6						(1 << IRCCTRL_TRIM_6_bit)

+#define IRCCTRL_TRIM_7						(1 << IRCCTRL_TRIM_7_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSRSTSTAT - System reset status register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSRSTSTAT_POR_bit					0

+#define SYSRSTSTAT_EXTRST_bit				1

+#define SYSRSTSTAT_WDT_bit					2

+#define SYSRSTSTAT_BOD_bit					3

+#define SYSRSTSTAT_SYSRST_bit				4

+

+#define SYSRSTSTAT_POR						(1 << SYSRSTSTAT_POR_bit)

+#define SYSRSTSTAT_EXTRST					(1 << SYSRSTSTAT_EXTRST_bit)

+#define SYSRSTSTAT_WDT						(1 << SYSRSTSTAT_WDT_bit)

+#define SYSRSTSTAT_BOD						(1 << SYSRSTSTAT_BOD_bit)

+#define SYSRSTSTAT_SYSRST					(1 << SYSRSTSTAT_SYSRST_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSPLLCLKSEL - System PLL clock source select register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSPLLCLKSEL_SEL_bit				0

+#define SYSPLLCLKSEL_SEL_0_bit				0

+#define SYSPLLCLKSEL_SEL_1_bit				1

+

+#define SYSPLLCLKSEL_SEL_0					(1 << SYSPLLCLKSEL_SEL_0_bit)

+#define SYSPLLCLKSEL_SEL_1					(1 << SYSPLLCLKSEL_SEL_1_bit)

+

+#define SYSPLLCLKSEL_SEL_IRC_value			0

+#define SYSPLLCLKSEL_SEL_SYSOSC_value		1

+#define SYSPLLCLKSEL_SEL_mask				3

+

+#define SYSPLLCLKSEL_SEL_IRC				(SYSPLLCLKSEL_SEL_IRC_value	<< SYSPLLCLKSEL_SEL_bit)

+#define SYSPLLCLKSEL_SEL_SYSOSC				(SYSPLLCLKSEL_SEL_SYSOSC_value	<< SYSPLLCLKSEL_SEL_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSPLLUEN - System PLL clock source update enable register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSPLLUEN_ENA_bit					0

+

+#define SYSPLLUEN_ENA						(1 << SYSPLLUEN_ENA_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| MAINCLKSEL - Main clock source select register

++-----------------------------------------------------------------------------+

+*/

+

+#define MAINCLKSEL_SEL_bit					0

+#define MAINCLKSEL_SEL_0_bit				0

+#define MAINCLKSEL_SEL_1_bit				1

+

+#define MAINCLKSEL_SEL_0					(1 << MAINCLKSEL_SEL_0_bit)

+#define MAINCLKSEL_SEL_1					(1 << MAINCLKSEL_SEL_1_bit)

+

+#define MAINCLKSEL_SEL_IRC_value			0

+#define MAINCLKSEL_SEL_PLLIN_value			1

+#define MAINCLKSEL_SEL_WDT_value			2

+#define MAINCLKSEL_SEL_PLLOUT_value			3

+#define MAINCLKSEL_SEL_mask					3

+

+#define MAINCLKSEL_SEL_IRC					(MAINCLKSEL_SEL_IRC_value << MAINCLKSEL_SEL_bit)

+#define MAINCLKSEL_SEL_PLLIN				(MAINCLKSEL_SEL_PLLIN_value << MAINCLKSEL_SEL_bit)

+#define MAINCLKSEL_SEL_WDT					(MAINCLKSEL_SEL_WDT_value << MAINCLKSEL_SEL_bit)

+#define MAINCLKSEL_SEL_PLLOUT				(MAINCLKSEL_SEL_PLLOUT_value << MAINCLKSEL_SEL_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| MAINCLKUEN - Main clock source update enable register

++-----------------------------------------------------------------------------+

+*/

+

+#define MAINCLKUEN_ENA_bit					0

+

+#define MAINCLKUEN_ENA						(1 << MAINCLKUEN_ENA_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSAHBCLKDIV - System AHB clock divider register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSAHBCLKDIV_DIV_bit				0

+#define SYSAHBCLKDIV_DIV_0_bit				0

+#define SYSAHBCLKDIV_DIV_1_bit				1

+#define SYSAHBCLKDIV_DIV_2_bit				2

+#define SYSAHBCLKDIV_DIV_3_bit				3

+#define SYSAHBCLKDIV_DIV_4_bit				4

+#define SYSAHBCLKDIV_DIV_5_bit				5

+#define SYSAHBCLKDIV_DIV_6_bit				6

+#define SYSAHBCLKDIV_DIV_7_bit				7

+

+#define SYSAHBCLKDIV_DIV_0					(1 << SYSAHBCLKDIV_DIV_0_bit)

+#define SYSAHBCLKDIV_DIV_1					(1 << SYSAHBCLKDIV_DIV_1_bit)

+#define SYSAHBCLKDIV_DIV_2					(1 << SYSAHBCLKDIV_DIV_2_bit)

+#define SYSAHBCLKDIV_DIV_3					(1 << SYSAHBCLKDIV_DIV_3_bit)

+#define SYSAHBCLKDIV_DIV_4					(1 << SYSAHBCLKDIV_DIV_4_bit)

+#define SYSAHBCLKDIV_DIV_5					(1 << SYSAHBCLKDIV_DIV_5_bit)

+#define SYSAHBCLKDIV_DIV_6					(1 << SYSAHBCLKDIV_DIV_6_bit)

+#define SYSAHBCLKDIV_DIV_7					(1 << SYSAHBCLKDIV_DIV_7_bit)

+

+#define SYSAHBCLKDIV_DIV_CLKDISABLED_value	0

+#define SYSAHBCLKDIV_DIV_mask				255

+

+#define SYSAHBCLKDIV_DIV_CLKDISABLED		(SYSAHBCLKDIV_DIV_CLKDISABLED_value << SYSAHBCLKDIV_DIV_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSAHBCLKCTRL - System AHB clock control register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSAHBCLKCTRL_SYS_bit				0

+#define SYSAHBCLKCTRL_ROM_bit				1

+#define SYSAHBCLKCTRL_RAM_bit				2

+#define SYSAHBCLKCTRL_FLASHREG_bit			3

+#define SYSAHBCLKCTRL_FLASHARRAY_bit		4

+#define SYSAHBCLKCTRL_I2C_bit				5

+#define SYSAHBCLKCTRL_GPIO_bit				6

+#define SYSAHBCLKCTRL_CT16B0_bit			7

+#define SYSAHBCLKCTRL_CT16B1_bit			8

+#define SYSAHBCLKCTRL_CT32B0_bit			9

+#define SYSAHBCLKCTRL_CT32B1_bit			10

+#define SYSAHBCLKCTRL_SSP0_bit				11

+#define SYSAHBCLKCTRL_UART_bit				12

+#define SYSAHBCLKCTRL_ADC_bit				13

+#define SYSAHBCLKCTRL_WDT_bit				15

+#define SYSAHBCLKCTRL_IOCON_bit				16

+#define SYSAHBCLKCTRL_CAN_bit				17

+#define SYSAHBCLKCTRL_SSP1_bit				18

+

+#define SYSAHBCLKCTRL_SYS					(1 << SYSAHBCLKCTRL_SYS_bit)

+#define SYSAHBCLKCTRL_ROM					(1 << SYSAHBCLKCTRL_ROM_bit)

+#define SYSAHBCLKCTRL_RAM					(1 << SYSAHBCLKCTRL_RAM_bit)

+#define SYSAHBCLKCTRL_FLASHREG				(1 << SYSAHBCLKCTRL_FLASHREG_bit)

+#define SYSAHBCLKCTRL_FLASHARRAY			(1 << SYSAHBCLKCTRL_FLASHARRAY_bit)

+#define SYSAHBCLKCTRL_I2C					(1 << SYSAHBCLKCTRL_I2C_bit)

+#define SYSAHBCLKCTRL_GPIO					(1 << SYSAHBCLKCTRL_GPIO_bit)

+#define SYSAHBCLKCTRL_CT16B0				(1 << SYSAHBCLKCTRL_CT16B0_bit)

+#define SYSAHBCLKCTRL_CT16B1				(1 << SYSAHBCLKCTRL_CT16B1_bit)

+#define SYSAHBCLKCTRL_CT32B0				(1 << SYSAHBCLKCTRL_CT32B0_bit)

+#define SYSAHBCLKCTRL_CT32B1				(1 << SYSAHBCLKCTRL_CT32B1_bit)

+#define SYSAHBCLKCTRL_SSP0					(1 << SYSAHBCLKCTRL_SSP0_bit)

+#define SYSAHBCLKCTRL_UART					(1 << SYSAHBCLKCTRL_UART_bit)

+#define SYSAHBCLKCTRL_ADC					(1 << SYSAHBCLKCTRL_ADC_bit)

+#define SYSAHBCLKCTRL_WDT					(1 << SYSAHBCLKCTRL_WDT_bit)

+#define SYSAHBCLKCTRL_IOCON					(1 << SYSAHBCLKCTRL_IOCON_bit)

+#define SYSAHBCLKCTRL_CAN					(1 << SYSAHBCLKCTRL_CAN_bit)

+#define SYSAHBCLKCTRL_SSP1					(1 << SYSAHBCLKCTRL_SSP1_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SSP0CLKDIV - SPI0 clock divider register

++-----------------------------------------------------------------------------+

+*/

+

+#define SSP0CLKDIV_DIV_bit					0

+#define SSP0CLKDIV_DIV_0_bit				0

+#define SSP0CLKDIV_DIV_1_bit				1

+#define SSP0CLKDIV_DIV_2_bit				2

+#define SSP0CLKDIV_DIV_3_bit				3

+#define SSP0CLKDIV_DIV_4_bit				4

+#define SSP0CLKDIV_DIV_5_bit				5

+#define SSP0CLKDIV_DIV_6_bit				6

+#define SSP0CLKDIV_DIV_7_bit				7

+

+#define SSP0CLKDIV_DIV_0					(1 << SSP0CLKDIV_DIV_0_bit)

+#define SSP0CLKDIV_DIV_1					(1 << SSP0CLKDIV_DIV_1_bit)

+#define SSP0CLKDIV_DIV_2					(1 << SSP0CLKDIV_DIV_2_bit)

+#define SSP0CLKDIV_DIV_3					(1 << SSP0CLKDIV_DIV_3_bit)

+#define SSP0CLKDIV_DIV_4					(1 << SSP0CLKDIV_DIV_4_bit)

+#define SSP0CLKDIV_DIV_5					(1 << SSP0CLKDIV_DIV_5_bit)

+#define SSP0CLKDIV_DIV_6					(1 << SSP0CLKDIV_DIV_6_bit)

+#define SSP0CLKDIV_DIV_7					(1 << SSP0CLKDIV_DIV_7_bit)

+

+#define SSP0CLKDIV_DIV_CLKDISABLED_value	0

+#define SSP0CLKDIV_DIV_mask					255

+

+#define SSP0CLKDIV_DIV_CLKDISABLED			(SSP0CLKDIV_DIV_CLKDISABLED_value << SSP0CLKDIV_DIV_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| UARTCLKDIV - UART clock divider register

++-----------------------------------------------------------------------------+

+*/

+

+#define UARTCLKDIV_DIV_bit					0

+#define UARTCLKDIV_DIV_0_bit				0

+#define UARTCLKDIV_DIV_1_bit				1

+#define UARTCLKDIV_DIV_2_bit				2

+#define UARTCLKDIV_DIV_3_bit				3

+#define UARTCLKDIV_DIV_4_bit				4

+#define UARTCLKDIV_DIV_5_bit				5

+#define UARTCLKDIV_DIV_6_bit				6

+#define UARTCLKDIV_DIV_7_bit				7

+

+#define UARTCLKDIV_DIV_0					(1 << UARTCLKDIV_DIV_0_bit)

+#define UARTCLKDIV_DIV_1					(1 << UARTCLKDIV_DIV_1_bit)

+#define UARTCLKDIV_DIV_2					(1 << UARTCLKDIV_DIV_2_bit)

+#define UARTCLKDIV_DIV_3					(1 << UARTCLKDIV_DIV_3_bit)

+#define UARTCLKDIV_DIV_4					(1 << UARTCLKDIV_DIV_4_bit)

+#define UARTCLKDIV_DIV_5					(1 << UARTCLKDIV_DIV_5_bit)

+#define UARTCLKDIV_DIV_6					(1 << UARTCLKDIV_DIV_6_bit)

+#define UARTCLKDIV_DIV_7					(1 << UARTCLKDIV_DIV_7_bit)

+

+#define UARTCLKDIV_DIV_CLKDISABLED_value	0

+#define UARTCLKDIV_DIV_mask					255

+

+#define UARTCLKDIV_DIV_CLKDISABLED			(UARTCLKDIV_DIV_CLKDISABLED_value << UARTCLKDIV_DIV_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SSP1CLKDIV - SPI1 clock divider register

++-----------------------------------------------------------------------------+

+*/

+

+#define SSP1CLKDIV_DIV_bit					0

+#define SSP1CLKDIV_DIV_0_bit				0

+#define SSP1CLKDIV_DIV_1_bit				1

+#define SSP1CLKDIV_DIV_2_bit				2

+#define SSP1CLKDIV_DIV_3_bit				3

+#define SSP1CLKDIV_DIV_4_bit				4

+#define SSP1CLKDIV_DIV_5_bit				5

+#define SSP1CLKDIV_DIV_6_bit				6

+#define SSP1CLKDIV_DIV_7_bit				7

+

+#define SSP1CLKDIV_DIV_0					(1 << SSP1CLKDIV_DIV_0_bit)

+#define SSP1CLKDIV_DIV_1					(1 << SSP1CLKDIV_DIV_1_bit)

+#define SSP1CLKDIV_DIV_2					(1 << SSP1CLKDIV_DIV_2_bit)

+#define SSP1CLKDIV_DIV_3					(1 << SSP1CLKDIV_DIV_3_bit)

+#define SSP1CLKDIV_DIV_4					(1 << SSP1CLKDIV_DIV_4_bit)

+#define SSP1CLKDIV_DIV_5					(1 << SSP1CLKDIV_DIV_5_bit)

+#define SSP1CLKDIV_DIV_6					(1 << SSP1CLKDIV_DIV_6_bit)

+#define SSP1CLKDIV_DIV_7					(1 << SSP1CLKDIV_DIV_7_bit)

+

+#define SSP1CLKDIV_DIV_CLKDISABLED_value	0

+#define SSP1CLKDIV_DIV_mask					255

+

+#define SSP1CLKDIV_DIV_CLKDISABLED			(SSP1CLKDIV_DIV_CLKDISABLED_value << SSP1CLKDIV_DIV_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| WDTCLKSEL - WDT clock source select register

++-----------------------------------------------------------------------------+

+*/

+

+#define WDTCLKSEL_SEL_bit					0

+#define WDTCLKSEL_SEL_0_bit					0

+#define WDTCLKSEL_SEL_1_bit					1

+

+#define WDTCLKSEL_SEL_0						(1 << WDTCLKSEL_SEL_0_bit)

+#define WDTCLKSEL_SEL_1						(1 << WDTCLKSEL_SEL_1_bit)

+

+#define WDTCLKSEL_SEL_IRC_value				0

+#define WDTCLKSEL_SEL_MAINCLK_value			1

+#define WDTCLKSEL_SEL_WDTOSC_value			2

+#define WDTCLKSEL_SEL_mask					255

+

+#define WDTCLKSEL_SEL_IRC					(WDTCLKSEL_SEL_IRC_value << WDTCLKSEL_SEL_bit)

+#define WDTCLKSEL_SEL_MAINCLK				(WDTCLKSEL_SEL_MAINCLK_value << WDTCLKSEL_SEL_bit)

+#define WDTCLKSEL_SEL_WDTOSC				(WDTCLKSEL_SEL_WDTOSC_value << WDTCLKSEL_SEL_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| WDTCLKUEN - WDT clock source update enable register

++-----------------------------------------------------------------------------+

+*/

+

+#define WDTCLKUEN_ENA_bit					0

+

+#define WDTCLKUEN_ENA						(1 << WDTCLKUEN_ENA_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| WDTCLKDIV - WDT clock divider register

++-----------------------------------------------------------------------------+

+*/

+

+#define WDTCLKDIV_DIV_bit					0

+#define WDTCLKDIV_DIV_0_bit					0

+#define WDTCLKDIV_DIV_1_bit					1

+#define WDTCLKDIV_DIV_2_bit					2

+#define WDTCLKDIV_DIV_3_bit					3

+#define WDTCLKDIV_DIV_4_bit					4

+#define WDTCLKDIV_DIV_5_bit					5

+#define WDTCLKDIV_DIV_6_bit					6

+#define WDTCLKDIV_DIV_7_bit					7

+

+#define WDTCLKDIV_DIV_0						(1 << WDTCLKDIV_DIV_0_bit)

+#define WDTCLKDIV_DIV_1						(1 << WDTCLKDIV_DIV_1_bit)

+#define WDTCLKDIV_DIV_2						(1 << WDTCLKDIV_DIV_2_bit)

+#define WDTCLKDIV_DIV_3						(1 << WDTCLKDIV_DIV_3_bit)

+#define WDTCLKDIV_DIV_4						(1 << WDTCLKDIV_DIV_4_bit)

+#define WDTCLKDIV_DIV_5						(1 << WDTCLKDIV_DIV_5_bit)

+#define WDTCLKDIV_DIV_6						(1 << WDTCLKDIV_DIV_6_bit)

+#define WDTCLKDIV_DIV_7						(1 << WDTCLKDIV_DIV_7_bit)

+

+#define WDTCLKDIV_DIV_CLKDISABLED_value		0

+#define WDTCLKDIV_DIV_mask					255

+

+#define WDTCLKDIV_DIV_CLKDISABLED			(WDTCLKDIV_DIV_CLKDISABLED_value << WDTCLKDIV_DIV_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| CLKOUTCLKSEL - CLKOUT clock source select register

++-----------------------------------------------------------------------------+

+*/

+

+#define CLKOUTCLKSEL_SEL_bit				0

+#define CLKOUTCLKSEL_SEL_0_bit				0

+#define CLKOUTCLKSEL_SEL_1_bit				1

+

+#define CLKOUTCLKSEL_SEL_0					(1 << CLKOUTCLKSEL_SEL_0_bit)

+#define CLKOUTCLKSEL_SEL_1					(1 << CLKOUTCLKSEL_SEL_1_bit)

+

+#define CLKOUTCLKSEL_SEL_IRC_value			0

+#define CLKOUTCLKSEL_SEL_SYSOSC_value		1

+#define CLKOUTCLKSEL_SEL_WDTOSC_value		2

+#define CLKOUTCLKSEL_SEL_MAINCLK_value		3

+#define CLKOUTCLKSEL_SEL_mask				3

+

+#define CLKOUTCLKSEL_SEL_IRC				(CLKOUTCLKSEL_SEL_IRC_value << CLKOUTCLKSEL_SEL_bit)

+#define CLKOUTCLKSEL_SEL_SYSOSC				(CLKOUTCLKSEL_SEL_SYSOSC_value << CLKOUTCLKSEL_SEL_bit)

+#define CLKOUTCLKSEL_SEL_WDTOSC				(CLKOUTCLKSEL_SEL_WDTOSC_value << CLKOUTCLKSEL_SEL_bit)

+#define CLKOUTCLKSEL_SEL_MAINCLK			(CLKOUTCLKSEL_SEL_MAINCLK_value << CLKOUTCLKSEL_SEL_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| CLKOUTUEN - CLKOUT clock source update enable register

++-----------------------------------------------------------------------------+

+*/

+

+#define CLKOUTUEN_ENA_bit					0

+

+#define CLKOUTUEN_ENA						(1 << CLKOUTUEN_ENA_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| CLKOUTCLKDIV - CLKOUT clock divider registers

++-----------------------------------------------------------------------------+

+*/

+

+#define CLKOUTCLKDIV_DIV_bit				0

+#define CLKOUTCLKDIV_DIV_0_bit				0

+#define CLKOUTCLKDIV_DIV_1_bit				1

+#define CLKOUTCLKDIV_DIV_2_bit				2

+#define CLKOUTCLKDIV_DIV_3_bit				3

+#define CLKOUTCLKDIV_DIV_4_bit				4

+#define CLKOUTCLKDIV_DIV_5_bit				5

+#define CLKOUTCLKDIV_DIV_6_bit				6

+#define CLKOUTCLKDIV_DIV_7_bit				7

+

+#define CLKOUTCLKDIV_DIV_0					(1 << CLKOUTCLKDIV_DIV_0_bit)

+#define CLKOUTCLKDIV_DIV_1					(1 << CLKOUTCLKDIV_DIV_1_bit)

+#define CLKOUTCLKDIV_DIV_2					(1 << CLKOUTCLKDIV_DIV_2_bit)

+#define CLKOUTCLKDIV_DIV_3					(1 << CLKOUTCLKDIV_DIV_3_bit)

+#define CLKOUTCLKDIV_DIV_4					(1 << CLKOUTCLKDIV_DIV_4_bit)

+#define CLKOUTCLKDIV_DIV_5					(1 << CLKOUTCLKDIV_DIV_5_bit)

+#define CLKOUTCLKDIV_DIV_6					(1 << CLKOUTCLKDIV_DIV_6_bit)

+#define CLKOUTCLKDIV_DIV_7					(1 << CLKOUTCLKDIV_DIV_7_bit)

+

+#define CLKOUTCLKDIV_DIV_CLKDISABLED_value	0

+#define CLKOUTCLKDIV_DIV_mask				255

+

+#define CLKOUTCLKDIV_DIV_CLKDISABLED		(CLKOUTCLKDIV_DIV_CLKDISABLED_value << CLKOUTCLKDIV_DIV_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| PIOPORCAP0 - POR captured PIO status registers 0

++-----------------------------------------------------------------------------+

+*/

+

+#define PIOPORCAP0_CAPPIO0_0_bit			0

+#define PIOPORCAP0_CAPPIO0_1_bit			1

+#define PIOPORCAP0_CAPPIO0_2_bit			2

+#define PIOPORCAP0_CAPPIO0_3_bit			3

+#define PIOPORCAP0_CAPPIO0_4_bit			4

+#define PIOPORCAP0_CAPPIO0_5_bit			5

+#define PIOPORCAP0_CAPPIO0_6_bit			6

+#define PIOPORCAP0_CAPPIO0_7_bit			7

+#define PIOPORCAP0_CAPPIO0_8_bit			8

+#define PIOPORCAP0_CAPPIO0_9_bit			9

+#define PIOPORCAP0_CAPPIO0_10_bit			10

+#define PIOPORCAP0_CAPPIO0_11_bit			11

+#define PIOPORCAP0_CAPPIO1_0_bit			12

+#define PIOPORCAP0_CAPPIO1_1_bit			13

+#define PIOPORCAP0_CAPPIO1_2_bit			14

+#define PIOPORCAP0_CAPPIO1_3_bit			15

+#define PIOPORCAP0_CAPPIO1_4_bit			16

+#define PIOPORCAP0_CAPPIO1_5_bit			17

+#define PIOPORCAP0_CAPPIO1_6_bit			18

+#define PIOPORCAP0_CAPPIO1_7_bit			19

+#define PIOPORCAP0_CAPPIO1_8_bit			20

+#define PIOPORCAP0_CAPPIO1_9_bit			21

+#define PIOPORCAP0_CAPPIO1_10_bit			22

+#define PIOPORCAP0_CAPPIO1_11_bit			23

+#define PIOPORCAP0_CAPPIO2_0_bit			24

+#define PIOPORCAP0_CAPPIO2_1_bit			25

+#define PIOPORCAP0_CAPPIO2_2_bit			26

+#define PIOPORCAP0_CAPPIO2_3_bit			27

+#define PIOPORCAP0_CAPPIO2_4_bit			28

+#define PIOPORCAP0_CAPPIO2_5_bit			29

+#define PIOPORCAP0_CAPPIO2_6_bit			30

+#define PIOPORCAP0_CAPPIO2_7_bit			31

+

+#define PIOPORCAP0_CAPPIO0_0				(1 << PIOPORCAP0_CAPPIO0_0_bit)

+#define PIOPORCAP0_CAPPIO0_1				(1 << PIOPORCAP0_CAPPIO0_1_bit)

+#define PIOPORCAP0_CAPPIO0_2				(1 << PIOPORCAP0_CAPPIO0_2_bit)

+#define PIOPORCAP0_CAPPIO0_3				(1 << PIOPORCAP0_CAPPIO0_3_bit)

+#define PIOPORCAP0_CAPPIO0_4				(1 << PIOPORCAP0_CAPPIO0_4_bit)

+#define PIOPORCAP0_CAPPIO0_5				(1 << PIOPORCAP0_CAPPIO0_5_bit)

+#define PIOPORCAP0_CAPPIO0_6				(1 << PIOPORCAP0_CAPPIO0_6_bit)

+#define PIOPORCAP0_CAPPIO0_7				(1 << PIOPORCAP0_CAPPIO0_7_bit)

+#define PIOPORCAP0_CAPPIO0_8				(1 << PIOPORCAP0_CAPPIO0_8_bit)

+#define PIOPORCAP0_CAPPIO0_9				(1 << PIOPORCAP0_CAPPIO0_9_bit)

+#define PIOPORCAP0_CAPPIO0_10				(1 << PIOPORCAP0_CAPPIO0_10_bit)

+#define PIOPORCAP0_CAPPIO0_11				(1 << PIOPORCAP0_CAPPIO0_11_bit)

+#define PIOPORCAP0_CAPPIO1_0				(1 << PIOPORCAP0_CAPPIO1_0_bit)

+#define PIOPORCAP0_CAPPIO1_1				(1 << PIOPORCAP0_CAPPIO1_1_bit)

+#define PIOPORCAP0_CAPPIO1_2				(1 << PIOPORCAP0_CAPPIO1_2_bit)

+#define PIOPORCAP0_CAPPIO1_3				(1 << PIOPORCAP0_CAPPIO1_3_bit)

+#define PIOPORCAP0_CAPPIO1_4				(1 << PIOPORCAP0_CAPPIO1_4_bit)

+#define PIOPORCAP0_CAPPIO1_5				(1 << PIOPORCAP0_CAPPIO1_5_bit)

+#define PIOPORCAP0_CAPPIO1_6				(1 << PIOPORCAP0_CAPPIO1_6_bit)

+#define PIOPORCAP0_CAPPIO1_7				(1 << PIOPORCAP0_CAPPIO1_7_bit)

+#define PIOPORCAP0_CAPPIO1_8				(1 << PIOPORCAP0_CAPPIO1_8_bit)

+#define PIOPORCAP0_CAPPIO1_9				(1 << PIOPORCAP0_CAPPIO1_9_bit)

+#define PIOPORCAP0_CAPPIO1_10				(1 << PIOPORCAP0_CAPPIO1_10_bit)

+#define PIOPORCAP0_CAPPIO1_11				(1 << PIOPORCAP0_CAPPIO1_11_bit)

+#define PIOPORCAP0_CAPPIO2_0				(1 << PIOPORCAP0_CAPPIO2_0_bit)

+#define PIOPORCAP0_CAPPIO2_1				(1 << PIOPORCAP0_CAPPIO2_1_bit)

+#define PIOPORCAP0_CAPPIO2_2				(1 << PIOPORCAP0_CAPPIO2_2_bit)

+#define PIOPORCAP0_CAPPIO2_3				(1 << PIOPORCAP0_CAPPIO2_3_bit)

+#define PIOPORCAP0_CAPPIO2_4				(1 << PIOPORCAP0_CAPPIO2_4_bit)

+#define PIOPORCAP0_CAPPIO2_5				(1 << PIOPORCAP0_CAPPIO2_5_bit)

+#define PIOPORCAP0_CAPPIO2_6				(1 << PIOPORCAP0_CAPPIO2_6_bit)

+#define PIOPORCAP0_CAPPIO2_7				(1 << PIOPORCAP0_CAPPIO2_7_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| PIOPORCAP1 - POR captured PIO status registers 1

++-----------------------------------------------------------------------------+

+*/

+

+#define PIOPORCAP1_CAPPIO2_8_bit			0

+#define PIOPORCAP1_CAPPIO2_9_bit			1

+#define PIOPORCAP1_CAPPIO2_10_bit			2

+#define PIOPORCAP1_CAPPIO2_11_bit			3

+#define PIOPORCAP1_CAPPIO3_0_bit			4

+#define PIOPORCAP1_CAPPIO3_1_bit			5

+#define PIOPORCAP1_CAPPIO3_2_bit			6

+#define PIOPORCAP1_CAPPIO3_3_bit			7

+#define PIOPORCAP1_CAPPIO3_4_bit			8

+#define PIOPORCAP1_CAPPIO3_5_bit			9

+

+#define PIOPORCAP1_CAPPIO2_8				(1 << PIOPORCAP1_CAPPIO2_8_bit)

+#define PIOPORCAP1_CAPPIO2_9				(1 << PIOPORCAP1_CAPPIO2_9_bit)

+#define PIOPORCAP1_CAPPIO2_10				(1 << PIOPORCAP1_CAPPIO2_10_bit)

+#define PIOPORCAP1_CAPPIO2_11				(1 << PIOPORCAP1_CAPPIO2_11_bit)

+#define PIOPORCAP1_CAPPIO3_0				(1 << PIOPORCAP1_CAPPIO3_0_bit)

+#define PIOPORCAP1_CAPPIO3_1				(1 << PIOPORCAP1_CAPPIO3_1_bit)

+#define PIOPORCAP1_CAPPIO3_2				(1 << PIOPORCAP1_CAPPIO3_2_bit)

+#define PIOPORCAP1_CAPPIO3_3				(1 << PIOPORCAP1_CAPPIO3_3_bit)

+#define PIOPORCAP1_CAPPIO3_4				(1 << PIOPORCAP1_CAPPIO3_4_bit)

+#define PIOPORCAP1_CAPPIO3_5				(1 << PIOPORCAP1_CAPPIO3_5_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| BODCTRL - BOD control register

++-----------------------------------------------------------------------------+

+*/

+

+#define BODCTRL_BODRSTLEV_bit				0

+#define BODCTRL_BODRSTLEV_0_bit				0

+#define BODCTRL_BODRSTLEV_1_bit				1

+#define BODCTRL_BODINTVAL_bit				2

+#define BODCTRL_BODINTVAL_0_bit				2

+#define BODCTRL_BODINTVAL_1_bit				3

+#define BODCTRL_BODRSTENA_bit				4

+

+#define BODCTRL_BODRSTLEV_0					(1 << BODCTRL_BODRSTLEV_0_bit)

+#define BODCTRL_BODRSTLEV_1					(1 << BODCTRL_BODRSTLEV_1_bit)

+#define BODCTRL_BODINTVAL_0					(1 << BODCTRL_BODINTVAL_0_bit)

+#define BODCTRL_BODINTVAL_1					(1 << BODCTRL_BODINTVAL_1_bit)

+#define BODCTRL_BODRSTENA					(1 << BODCTRL_BODRSTENA_bit)

+

+#define BODCTRL_BODRSTLEV_LEVEL0_value		0

+#define BODCTRL_BODRSTLEV_LEVEL1_value		1

+#define BODCTRL_BODRSTLEV_LEVEL2_value		2

+#define BODCTRL_BODRSTLEV_LEVEL3_value		3

+#define BODCTRL_BODRSTLEV_mask				3

+

+#define BODCTRL_BODINTVAL_LEVEL0_value		0

+#define BODCTRL_BODINTVAL_LEVEL1_value		1

+#define BODCTRL_BODINTVAL_LEVEL2_value		2

+#define BODCTRL_BODINTVAL_LEVEL3_value		3

+#define BODCTRL_BODINTVAL_mask				3

+

+#define BODCTRL_BODRSTLEV_LEVEL0			(BODCTRL_BODRSTLEV_LEVEL0_value << BODCTRL_BODRSTLEV_bit)

+#define BODCTRL_BODRSTLEV_LEVEL1			(BODCTRL_BODRSTLEV_LEVEL1_value << BODCTRL_BODRSTLEV_bit)

+#define BODCTRL_BODRSTLEV_LEVEL2			(BODCTRL_BODRSTLEV_LEVEL2_value << BODCTRL_BODRSTLEV_bit)

+#define BODCTRL_BODRSTLEV_LEVEL3			(BODCTRL_BODRSTLEV_LEVEL3_value << BODCTRL_BODRSTLEV_bit)

+

+#define BODCTRL_BODINTVAL_LEVEL0			(BODCTRL_BODINTVAL_LEVEL0_value << BODCTRL_BODINTVAL_bit)

+#define BODCTRL_BODINTVAL_LEVEL1			(BODCTRL_BODINTVAL_LEVEL1_value << BODCTRL_BODINTVAL_bit)

+#define BODCTRL_BODINTVAL_LEVEL2			(BODCTRL_BODINTVAL_LEVEL2_value << BODCTRL_BODINTVAL_bit)

+#define BODCTRL_BODINTVAL_LEVEL3			(BODCTRL_BODINTVAL_LEVEL3_value << BODCTRL_BODINTVAL_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| SYSTCKCAL - System tick timer calibration register

++-----------------------------------------------------------------------------+

+*/

+

+#define SYSTCKCAL_CAL_bit					0

+#define SYSTCKCAL_CAL_0_bit					0

+#define SYSTCKCAL_CAL_1_bit					1

+#define SYSTCKCAL_CAL_2_bit					2

+#define SYSTCKCAL_CAL_3_bit					3

+#define SYSTCKCAL_CAL_4_bit					4

+#define SYSTCKCAL_CAL_5_bit					5

+#define SYSTCKCAL_CAL_6_bit					6

+#define SYSTCKCAL_CAL_7_bit					7

+#define SYSTCKCAL_CAL_8_bit					8

+#define SYSTCKCAL_CAL_9_bit					9

+#define SYSTCKCAL_CAL_10_bit				10

+#define SYSTCKCAL_CAL_11_bit				11

+#define SYSTCKCAL_CAL_12_bit				12

+#define SYSTCKCAL_CAL_13_bit				13

+#define SYSTCKCAL_CAL_14_bit				14

+#define SYSTCKCAL_CAL_15_bit				15

+#define SYSTCKCAL_CAL_16_bit				16

+#define SYSTCKCAL_CAL_17_bit				17

+#define SYSTCKCAL_CAL_18_bit				18

+#define SYSTCKCAL_CAL_19_bit				19

+#define SYSTCKCAL_CAL_20_bit				20

+#define SYSTCKCAL_CAL_21_bit				21

+#define SYSTCKCAL_CAL_22_bit				22

+#define SYSTCKCAL_CAL_23_bit				23

+#define SYSTCKCAL_CAL_24_bit				24

+#define SYSTCKCAL_CAL_25_bit				25

+

+#define SYSTCKCAL_CAL_0						(1 << SYSTCKCAL_CAL_0_bit)

+#define SYSTCKCAL_CAL_1						(1 << SYSTCKCAL_CAL_1_bit)

+#define SYSTCKCAL_CAL_2						(1 << SYSTCKCAL_CAL_2_bit)

+#define SYSTCKCAL_CAL_3						(1 << SYSTCKCAL_CAL_3_bit)

+#define SYSTCKCAL_CAL_4						(1 << SYSTCKCAL_CAL_4_bit)

+#define SYSTCKCAL_CAL_5						(1 << SYSTCKCAL_CAL_5_bit)

+#define SYSTCKCAL_CAL_6						(1 << SYSTCKCAL_CAL_6_bit)

+#define SYSTCKCAL_CAL_7						(1 << SYSTCKCAL_CAL_7_bit)

+#define SYSTCKCAL_CAL_8						(1 << SYSTCKCAL_CAL_8_bit)

+#define SYSTCKCAL_CAL_9						(1 << SYSTCKCAL_CAL_9_bit)

+#define SYSTCKCAL_CAL_10					(1 << SYSTCKCAL_CAL_10_bit)

+#define SYSTCKCAL_CAL_11					(1 << SYSTCKCAL_CAL_11_bit)

+#define SYSTCKCAL_CAL_12					(1 << SYSTCKCAL_CAL_12_bit)

+#define SYSTCKCAL_CAL_13					(1 << SYSTCKCAL_CAL_13_bit)

+#define SYSTCKCAL_CAL_14					(1 << SYSTCKCAL_CAL_14_bit)

+#define SYSTCKCAL_CAL_15					(1 << SYSTCKCAL_CAL_15_bit)

+#define SYSTCKCAL_CAL_16					(1 << SYSTCKCAL_CAL_16_bit)

+#define SYSTCKCAL_CAL_17					(1 << SYSTCKCAL_CAL_17_bit)

+#define SYSTCKCAL_CAL_18					(1 << SYSTCKCAL_CAL_18_bit)

+#define SYSTCKCAL_CAL_19					(1 << SYSTCKCAL_CAL_19_bit)

+#define SYSTCKCAL_CAL_20					(1 << SYSTCKCAL_CAL_20_bit)

+#define SYSTCKCAL_CAL_21					(1 << SYSTCKCAL_CAL_21_bit)

+#define SYSTCKCAL_CAL_22					(1 << SYSTCKCAL_CAL_22_bit)

+#define SYSTCKCAL_CAL_23					(1 << SYSTCKCAL_CAL_23_bit)

+#define SYSTCKCAL_CAL_24					(1 << SYSTCKCAL_CAL_24_bit)

+#define SYSTCKCAL_CAL_25					(1 << SYSTCKCAL_CAL_25_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| STARTAPRP0 - Start logic edge control register 0

++-----------------------------------------------------------------------------+

+*/

+

+#define STARTAPRP0_APRPIO0_0_bit			0

+#define STARTAPRP0_APRPIO0_1_bit			1

+#define STARTAPRP0_APRPIO0_2_bit			2

+#define STARTAPRP0_APRPIO0_3_bit			3

+#define STARTAPRP0_APRPIO0_4_bit			4

+#define STARTAPRP0_APRPIO0_5_bit			5

+#define STARTAPRP0_APRPIO0_6_bit			6

+#define STARTAPRP0_APRPIO0_7_bit			7

+#define STARTAPRP0_APRPIO0_8_bit			8

+#define STARTAPRP0_APRPIO0_9_bit			9

+#define STARTAPRP0_APRPIO0_10_bit			10

+#define STARTAPRP0_APRPIO0_11_bit			11

+#define STARTAPRP0_APRPIO1_0_bit			12

+

+#define STARTAPRP0_APRPIO0_0				(1 << STARTAPRP0_APRPIO0_0_bit)

+#define STARTAPRP0_APRPIO0_1				(1 << STARTAPRP0_APRPIO0_1_bit)

+#define STARTAPRP0_APRPIO0_2				(1 << STARTAPRP0_APRPIO0_2_bit)

+#define STARTAPRP0_APRPIO0_3				(1 << STARTAPRP0_APRPIO0_3_bit)

+#define STARTAPRP0_APRPIO0_4				(1 << STARTAPRP0_APRPIO0_4_bit)

+#define STARTAPRP0_APRPIO0_5				(1 << STARTAPRP0_APRPIO0_5_bit)

+#define STARTAPRP0_APRPIO0_6				(1 << STARTAPRP0_APRPIO0_6_bit)

+#define STARTAPRP0_APRPIO0_7				(1 << STARTAPRP0_APRPIO0_7_bit)

+#define STARTAPRP0_APRPIO0_8				(1 << STARTAPRP0_APRPIO0_8_bit)

+#define STARTAPRP0_APRPIO0_9				(1 << STARTAPRP0_APRPIO0_9_bit)

+#define STARTAPRP0_APRPIO0_10				(1 << STARTAPRP0_APRPIO0_10_bit)

+#define STARTAPRP0_APRPIO0_11				(1 << STARTAPRP0_APRPIO0_11_bit)

+#define STARTAPRP0_APRPIO1_0				(1 << STARTAPRP0_APRPIO1_0_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| STARTERP0 - Start logic signal enable register 0

++-----------------------------------------------------------------------------+

+*/

+

+#define STARTERP0_ERPIO0_0_bit				0

+#define STARTERP0_ERPIO0_1_bit				1

+#define STARTERP0_ERPIO0_2_bit				2

+#define STARTERP0_ERPIO0_3_bit				3

+#define STARTERP0_ERPIO0_4_bit				4

+#define STARTERP0_ERPIO0_5_bit				5

+#define STARTERP0_ERPIO0_6_bit				6

+#define STARTERP0_ERPIO0_7_bit				7

+#define STARTERP0_ERPIO0_8_bit				8

+#define STARTERP0_ERPIO0_9_bit				9

+#define STARTERP0_ERPIO0_10_bit				10

+#define STARTERP0_ERPIO0_11_bit				11

+#define STARTERP0_ERPIO1_0_bit				12

+

+#define STARTERP0_ERPIO0_0					(1 << STARTERP0_ERPIO0_0_bit)

+#define STARTERP0_ERPIO0_1					(1 << STARTERP0_ERPIO0_1_bit)

+#define STARTERP0_ERPIO0_2					(1 << STARTERP0_ERPIO0_2_bit)

+#define STARTERP0_ERPIO0_3					(1 << STARTERP0_ERPIO0_3_bit)

+#define STARTERP0_ERPIO0_4					(1 << STARTERP0_ERPIO0_4_bit)

+#define STARTERP0_ERPIO0_5					(1 << STARTERP0_ERPIO0_5_bit)

+#define STARTERP0_ERPIO0_6					(1 << STARTERP0_ERPIO0_6_bit)

+#define STARTERP0_ERPIO0_7					(1 << STARTERP0_ERPIO0_7_bit)

+#define STARTERP0_ERPIO0_8					(1 << STARTERP0_ERPIO0_8_bit)

+#define STARTERP0_ERPIO0_9					(1 << STARTERP0_ERPIO0_9_bit)

+#define STARTERP0_ERPIO0_10					(1 << STARTERP0_ERPIO0_10_bit)

+#define STARTERP0_ERPIO0_11					(1 << STARTERP0_ERPIO0_11_bit)

+#define STARTERP0_ERPIO1_0					(1 << STARTERP0_ERPIO1_0_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| STARTRSRP0CLR - Start logic reset register 0

++-----------------------------------------------------------------------------+

+*/

+

+#define STARTRSRP0CLR_RSRPIO0_0_bit			0

+#define STARTRSRP0CLR_RSRPIO0_1_bit			1

+#define STARTRSRP0CLR_RSRPIO0_2_bit			2

+#define STARTRSRP0CLR_RSRPIO0_3_bit			3

+#define STARTRSRP0CLR_RSRPIO0_4_bit			4

+#define STARTRSRP0CLR_RSRPIO0_5_bit			5

+#define STARTRSRP0CLR_RSRPIO0_6_bit			6

+#define STARTRSRP0CLR_RSRPIO0_7_bit			7

+#define STARTRSRP0CLR_RSRPIO0_8_bit			8

+#define STARTRSRP0CLR_RSRPIO0_9_bit			9

+#define STARTRSRP0CLR_RSRPIO0_10_bit		10

+#define STARTRSRP0CLR_RSRPIO0_11_bit		11

+#define STARTRSRP0CLR_RSRPIO1_0_bit			12

+

+#define STARTRSRP0CLR_RSRPIO0_0				(1 << STARTRSRP0CLR_RSRPIO0_0_bit)

+#define STARTRSRP0CLR_RSRPIO0_1				(1 << STARTRSRP0CLR_RSRPIO0_1_bit)

+#define STARTRSRP0CLR_RSRPIO0_2				(1 << STARTRSRP0CLR_RSRPIO0_2_bit)

+#define STARTRSRP0CLR_RSRPIO0_3				(1 << STARTRSRP0CLR_RSRPIO0_3_bit)

+#define STARTRSRP0CLR_RSRPIO0_4				(1 << STARTRSRP0CLR_RSRPIO0_4_bit)

+#define STARTRSRP0CLR_RSRPIO0_5				(1 << STARTRSRP0CLR_RSRPIO0_5_bit)

+#define STARTRSRP0CLR_RSRPIO0_6				(1 << STARTRSRP0CLR_RSRPIO0_6_bit)

+#define STARTRSRP0CLR_RSRPIO0_7				(1 << STARTRSRP0CLR_RSRPIO0_7_bit)

+#define STARTRSRP0CLR_RSRPIO0_8				(1 << STARTRSRP0CLR_RSRPIO0_8_bit)

+#define STARTRSRP0CLR_RSRPIO0_9				(1 << STARTRSRP0CLR_RSRPIO0_9_bit)

+#define STARTRSRP0CLR_RSRPIO0_10			(1 << STARTRSRP0CLR_RSRPIO0_10_bit)

+#define STARTRSRP0CLR_RSRPIO0_11			(1 << STARTRSRP0CLR_RSRPIO0_11_bit)

+#define STARTRSRP0CLR_RSRPIO1_0				(1 << STARTRSRP0CLR_RSRPIO1_0_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| STARTSRP0 - Start logic status register 0

++-----------------------------------------------------------------------------+

+*/

+

+#define STARTSRP0_SRPIO0_0_bit				0

+#define STARTSRP0_SRPIO0_1_bit				1

+#define STARTSRP0_SRPIO0_2_bit				2

+#define STARTSRP0_SRPIO0_3_bit				3

+#define STARTSRP0_SRPIO0_4_bit				4

+#define STARTSRP0_SRPIO0_5_bit				5

+#define STARTSRP0_SRPIO0_6_bit				6

+#define STARTSRP0_SRPIO0_7_bit				7

+#define STARTSRP0_SRPIO0_8_bit				8

+#define STARTSRP0_SRPIO0_9_bit				9

+#define STARTSRP0_SRPIO0_10_bit				10

+#define STARTSRP0_SRPIO0_11_bit				11

+#define STARTSRP0_SRPIO1_0_bit				12

+

+#define STARTSRP0_SRPIO0_0					(1 << STARTSRP0_SRPIO0_0_bit)

+#define STARTSRP0_SRPIO0_1					(1 << STARTSRP0_SRPIO0_1_bit)

+#define STARTSRP0_SRPIO0_2					(1 << STARTSRP0_SRPIO0_2_bit)

+#define STARTSRP0_SRPIO0_3					(1 << STARTSRP0_SRPIO0_3_bit)

+#define STARTSRP0_SRPIO0_4					(1 << STARTSRP0_SRPIO0_4_bit)

+#define STARTSRP0_SRPIO0_5					(1 << STARTSRP0_SRPIO0_5_bit)

+#define STARTSRP0_SRPIO0_6					(1 << STARTSRP0_SRPIO0_6_bit)

+#define STARTSRP0_SRPIO0_7					(1 << STARTSRP0_SRPIO0_7_bit)

+#define STARTSRP0_SRPIO0_8					(1 << STARTSRP0_SRPIO0_8_bit)

+#define STARTSRP0_SRPIO0_9					(1 << STARTSRP0_SRPIO0_9_bit)

+#define STARTSRP0_SRPIO0_10					(1 << STARTSRP0_SRPIO0_10_bit)

+#define STARTSRP0_SRPIO0_11					(1 << STARTSRP0_SRPIO0_11_bit)

+#define STARTSRP0_SRPIO1_0					(1 << STARTSRP0_SRPIO1_0_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| PDSLEEPCFG - Deep-sleep mode configuration register

++-----------------------------------------------------------------------------+

+*/

+

+#define PDSLEEPCFG_BOD_PD_bit				3

+#define PDSLEEPCFG_WDTOSC_PD_bit			6

+

+#define PDSLEEPCFG_BOD_PD					(1 << PDSLEEPCFG_BOD_PD_bit)

+#define PDSLEEPCFG_WDTOSC_PD				(1 << PDSLEEPCFG_WDTOSC_PD_bit)

+

+

+/*

++-----------------------------------------------------------------------------+

+| PDAWAKECFG - Wake-up configuration register

++-----------------------------------------------------------------------------+

+*/

+

+#define PDAWAKECFG_IRCOUT_PD_bit			0

+#define PDAWAKECFG_IRC_PD_bit				1

+#define PDAWAKECFG_FLASH_PD_bit				2

+#define PDAWAKECFG_BOD_PD_bit				3

+#define PDAWAKECFG_ADC_PD_bit				4

+#define PDAWAKECFG_SYSOSC_PD_bit			5

+#define PDAWAKECFG_WDTOSC_PD_bit			6

+#define PDAWAKECFG_SYSPLL_PD_bit			7

+

+#define PDAWAKECFG_IRCOUT_PD				(1 << PDAWAKECFG_IRCOUT_PD_bit)

+#define PDAWAKECFG_IRC_PD					(1 << PDAWAKECFG_IRC_PD_bit)

+#define PDAWAKECFG_FLASH_PD					(1 << PDAWAKECFG_FLASH_PD_bit)

+#define PDAWAKECFG_BOD_PD					(1 << PDAWAKECFG_BOD_PD_bit)

+#define PDAWAKECFG_ADC_PD					(1 << PDAWAKECFG_ADC_PD_bit)

+#define PDAWAKECFG_SYSOSC_PD				(1 << PDAWAKECFG_SYSOSC_PD_bit)

+#define PDAWAKECFG_WDTOSC_PD				(1 << PDAWAKECFG_WDTOSC_PD_bit)

+#define PDAWAKECFG_SYSPLL_PD				(1 << PDAWAKECFG_SYSPLL_PD_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| PDRUNCFG - Power-down configuration register

++-----------------------------------------------------------------------------+

+*/

+

+#define PDRUNCFG_IRCOUT_PD_bit				0

+#define PDRUNCFG_IRC_PD_bit					1

+#define PDRUNCFG_FLASH_PD_bit				2

+#define PDRUNCFG_BOD_PD_bit					3

+#define PDRUNCFG_ADC_PD_bit					4

+#define PDRUNCFG_SYSOSC_PD_bit				5

+#define PDRUNCFG_WDTOSC_PD_bit				6

+#define PDRUNCFG_SYSPLL_PD_bit				7

+

+#define PDRUNCFG_IRCOUT_PD					(1 << PDRUNCFG_IRCOUT_PD_bit)

+#define PDRUNCFG_IRC_PD						(1 << PDRUNCFG_IRC_PD_bit)

+#define PDRUNCFG_FLASH_PD					(1 << PDRUNCFG_FLASH_PD_bit)

+#define PDRUNCFG_BOD_PD						(1 << PDRUNCFG_BOD_PD_bit)

+#define PDRUNCFG_ADC_PD						(1 << PDRUNCFG_ADC_PD_bit)

+#define PDRUNCFG_SYSOSC_PD					(1 << PDRUNCFG_SYSOSC_PD_bit)

+#define PDRUNCFG_WDTOSC_PD					(1 << PDRUNCFG_WDTOSC_PD_bit)

+#define PDRUNCFG_SYSPLL_PD					(1 << PDRUNCFG_SYSPLL_PD_bit)

+

+/*

++-----------------------------------------------------------------------------+

+| DEVICE_ID - Device ID register

++-----------------------------------------------------------------------------+

+*/

+

+#define DEVICE_ID_DEVICEID_LPC1111FHN33_101_value	0x041E502B

+#define DEVICE_ID_DEVICEID_LPC1111FHN33_201_value	0x0416502B

+#define DEVICE_ID_DEVICEID_LPC1112FHN33_101_value	0x042D502B

+#define DEVICE_ID_DEVICEID_LPC1112FHN33_201_value	0x0425502B

+#define DEVICE_ID_DEVICEID_LPC1113FHN33_201_value	0x0434502B

+#define DEVICE_ID_DEVICEID_LPC1113FHN33_301_value	0x0434102B

+#define DEVICE_ID_DEVICEID_LPC1113FBD48_301_value	0x0434102B

+#define DEVICE_ID_DEVICEID_LPC1114FHN33_201_value	0x0444502B

+#define DEVICE_ID_DEVICEID_LPC1114FHN33_301_value	0x0444102B

+#define DEVICE_ID_DEVICEID_LPC1114FBD48_301_value	0x0444102B

+#define DEVICE_ID_DEVICEID_LPC1114FA44_301_value	0x0444102B

+#define DEVICE_ID_DEVICEID_LPC11C12_FBD48_301_value	0x1421102B

+#define DEVICE_ID_DEVICEID_LPC11C14_FBD48_301_value	0x1440102B

+

+/*

++-----------------------------------------------------------------------------+

+| FLASHCFG - Flash configuration register

++-----------------------------------------------------------------------------+

+*/

+

+// Why is this register missing from LPC11xx.h file?

+// Temporary define it here for now...

+#include <stdint.h>

+#define FLASHCFG							(*(volatile uint32_t*)0x4003C010)

+// end of temporary fix

+

+#define FLASHCFG_FLASHTIM_bit				0

+#define FLASHCFG_FLASHTIM_0_bit				0

+#define FLASHCFG_FLASHTIM_1_bit				1

+

+#define FLASHCFG_FLASHTIM_0					(1 << FLASHCFG_FLASHTIM_0_bit)

+#define FLASHCFG_FLASHTIM_1					(1 << FLASHCFG_FLASHTIM_1_bit)

+

+#define FLASHCFG_FLASHTIM_1CLK_value		0

+#define FLASHCFG_FLASHTIM_2CLK_value		1

+#define FLASHCFG_FLASHTIM_3CLK_value		2

+#define FLASHCFG_FLASHTIM_mask				3

+

+#define FLASHCFG_FLASHTIM_1CLK				(FLASHCFG_FLASHTIM_1CLK_value << FLASHCFG_FLASHTIM_bit)

+#define FLASHCFG_FLASHTIM_2CLK				(FLASHCFG_FLASHTIM_2CLK_value << FLASHCFG_FLASHTIM_bit)

+#define FLASHCFG_FLASHTIM_3CLK				(FLASHCFG_FLASHTIM_3CLK_value << FLASHCFG_FLASHTIM_bit)

+

+/******************************************************************************

+* END OF FILE

+******************************************************************************/

+#endif /* HDR_SYSCON_H_ */

diff --git a/inc/LPC11xx.h b/inc/LPC11xx.h
new file mode 100644
index 0000000..854f719
--- /dev/null
+++ b/inc/LPC11xx.h
@@ -0,0 +1,559 @@
+/****************************************************************************

+ *   $Id:: LPC11xx.h 3635 2010-06-02 00:31:46Z usb00423                     $

+ *   Project: NXP LPC11xx software example  

+ *

+ *   Description:

+ *     CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 

+ *           NXP LPC11xx Device Series

+ *

+ ****************************************************************************

+ * Software that is described herein is for illustrative purposes only

+ * which provides customers with programming information regarding the

+ * products. This software is supplied "AS IS" without any warranties.

+ * NXP Semiconductors assumes no responsibility or liability for the

+ * use of the software, conveys no license or title under any patent,

+ * copyright, or mask work right to the product. NXP Semiconductors

+ * reserves the right to make changes in the software without

+ * notification. NXP Semiconductors also make no representation or

+ * warranty that such application will be suitable for the specified

+ * use without further testing or modification.

+****************************************************************************/

+#ifndef __LPC11xx_H__

+#define __LPC11xx_H__

+

+#ifdef __cplusplus

+ extern "C" {

+#endif 

+

+/** @addtogroup LPC11xx_Definitions LPC11xx Definitions

+  This file defines all structures and symbols for LPC11xx:

+    - Registers and bitfields

+    - peripheral base address

+    - peripheral ID

+    - PIO definitions

+  @{

+*/

+

+

+/******************************************************************************/

+/*                Processor and Core Peripherals                              */

+/******************************************************************************/

+/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions

+  Configuration of the Cortex-M0 Processor and Core Peripherals

+  @{

+*/

+

+/*

+ * ==========================================================================

+ * ---------- Interrupt Number Definition -----------------------------------

+ * ==========================================================================

+ */

+

+typedef enum IRQn

+{

+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/

+  NonMaskableInt_IRQn           = -14,    /*!< 2 Non Maskable Interrupt                           */

+  HardFault_IRQn                = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                   */

+  SVCall_IRQn                   = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                     */

+  PendSV_IRQn                   = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                     */

+  SysTick_IRQn                  = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                 */

+

+/******  LPC11xx Specific Interrupt Numbers *******************************************************/

+  WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.       */

+  WAKEUP1_IRQn                  = 1,        /*!< There are 13 pins in total for LPC11xx           */

+  WAKEUP2_IRQn                  = 2,

+  WAKEUP3_IRQn                  = 3,

+  WAKEUP4_IRQn                  = 4,   

+  WAKEUP5_IRQn                  = 5,        

+  WAKEUP6_IRQn                  = 6,        

+  WAKEUP7_IRQn                  = 7,        

+  WAKEUP8_IRQn                  = 8,        

+  WAKEUP9_IRQn                  = 9,        

+  WAKEUP10_IRQn                 = 10,       

+  WAKEUP11_IRQn                 = 11,       

+  WAKEUP12_IRQn                 = 12,       

+  CAN_IRQn                      = 13,       /*!< CAN Interrupt                                    */

+  SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                   */

+  I2C_IRQn                      = 15,       /*!< I2C Interrupt                                    */

+  TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                          */

+  TIMER_16_1_IRQn               = 17,       /*!< 16-bit Timer1 Interrupt                          */

+  TIMER_32_0_IRQn               = 18,       /*!< 32-bit Timer0 Interrupt                          */

+  TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                          */

+  SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                   */

+  UART_IRQn                     = 21,       /*!< UART Interrupt                                   */

+  ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                          */

+  WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                         */  

+  BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                  */

+  EINT3_IRQn                    = 28,       /*!< External Interrupt 3 Interrupt                   */

+  EINT2_IRQn                    = 29,       /*!< External Interrupt 2 Interrupt                   */

+  EINT1_IRQn                    = 30,       /*!< External Interrupt 1 Interrupt                   */

+  EINT0_IRQn                    = 31,       /*!< External Interrupt 0 Interrupt                   */

+} IRQn_Type;

+

+

+/*

+ * ==========================================================================

+ * ----------- Processor and Core Peripheral Section ------------------------

+ * ==========================================================================

+ */

+

+/* Configuration of the Cortex-M3 Processor and Core Peripherals */

+#define __MPU_PRESENT             0         /*!< MPU present or not                               */

+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */

+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */

+

+/*@}*/ /* end of group LPC11xx_CMSIS */

+

+

+#include "core_cm0.h"                       /* Cortex-M0 processor and core peripherals           */

+#include "system_LPC11xx.h"                 /* System Header                                      */

+

+

+/******************************************************************************/

+/*                Device Specific Peripheral Registers structures             */

+/******************************************************************************/

+

+#if defined ( __CC_ARM   )

+#pragma anon_unions

+#endif

+

+/*------------- System Control (SYSCON) --------------------------------------*/

+/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W) */

+  __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W) */

+  __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W) */

+  __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/ ) */

+       uint32_t RESERVED0[4];

+

+  __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W) */

+  __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 Watchdog oscillator control (R/W) */

+  __IO uint32_t IRCCTRL;                /*!< Offset: 0x028 IRC control (R/W) */

+       uint32_t RESERVED1[1];

+  __IO uint32_t SYSRESSTAT;             /*!< Offset: 0x030 System reset status Register (R/ ) */

+       uint32_t RESERVED2[3];

+  __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 System PLL clock source select (R/W) */	

+  __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 System PLL clock source update enable (R/W) */

+       uint32_t RESERVED3[10];

+

+  __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 Main clock source select (R/W) */

+  __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 Main clock source update enable (R/W) */

+  __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 System AHB clock divider (R/W) */

+       uint32_t RESERVED4[1];

+

+  __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 System AHB clock control (R/W) */

+       uint32_t RESERVED5[4];

+  __IO uint32_t SSP0CLKDIV;             /*!< Offset: 0x094 SSP0 clock divider (R/W) */          

+  __IO uint32_t UARTCLKDIV;             /*!< Offset: 0x098 UART clock divider (R/W) */

+  __IO uint32_t SSP1CLKDIV;             /*!< Offset: 0x09C SSP1 clock divider (R/W) */          

+       uint32_t RESERVED6[4];

+

+  __IO uint32_t SYSTICKCLKDIV;          /*!< Offset: 0x0B0 SYSTICK clock divider (R/W) */          

+       uint32_t RESERVED7[7];

+

+  __IO uint32_t WDTCLKSEL;              /*!< Offset: 0x0D0 WDT clock source select (R/W) */

+  __IO uint32_t WDTCLKUEN;              /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */

+  __IO uint32_t WDTCLKDIV;              /*!< Offset: 0x0D8 WDT clock divider (R/W) */

+       uint32_t RESERVED8[1];              

+  __IO uint32_t CLKOUTCLKSEL;           /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */

+  __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */

+  __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */       

+       uint32_t RESERVED9[5];

+  

+  __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */           

+  __IO uint32_t PIOPORCAP1;             /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */   

+       uint32_t RESERVED10[18];

+

+  __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W) */

+       uint32_t RESERVED11[1];

+  __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x158 System tick counter calibration (R/W) */

+       uint32_t RESERVED12;

+  __IO uint32_t MAINREGVOUT0CFG;        /*!< Offset: 0x160 Main Regulator Voltage 0 Configuration */ 

+  __IO uint32_t MAINREGVOUT1CFG;        /*!< Offset: 0x164 Main Regulator Voltage 1 Configuration */

+       uint32_t RESERVED13[38];

+

+  __IO uint32_t STARTAPRP0;             /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */     

+  __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */      

+  __IO uint32_t STARTRSRP0CLR;          /*!< Offset: 0x208 Start logic reset Register 0  ( /W) */

+  __IO uint32_t STARTSRP0;              /*!< Offset: 0x20C Start logic status Register 0 (R/W) */

+       uint32_t RESERVED14[8];

+

+  __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */

+  __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W) */        

+  __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W) */

+       uint32_t RESERVED15[101];

+  __O  uint32_t VOUTCFGPROT;            /*!< Offset: 0x3D0 Voltage Output Configuration Protection Register (W) */

+       uint32_t RESERVED16[8];

+  __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ ) */

+} LPC_SYSCON_TypeDef;

+/*@}*/ /* end of group LPC11xx_SYSCON */

+

+

+/*------------- Pin Connect Block (IOCON) --------------------------------*/

+/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t PIO2_6;                 /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */

+       uint32_t RESERVED0[1];

+  __IO uint32_t PIO2_0;                 /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */

+  __IO uint32_t RESET_PIO0_0;           /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0  (R/W) */

+  __IO uint32_t PIO0_1;                 /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */

+  __IO uint32_t PIO1_8;                 /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */

+       uint32_t RESERVED1[1];

+  __IO uint32_t PIO0_2;                 /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */

+

+  __IO uint32_t PIO2_7;                 /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */

+  __IO uint32_t PIO2_8;                 /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */

+  __IO uint32_t PIO2_1;                 /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */

+  __IO uint32_t PIO0_3;                 /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */

+  __IO uint32_t PIO0_4;                 /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */

+  __IO uint32_t PIO0_5;                 /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */

+  __IO uint32_t PIO1_9;                 /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */

+  __IO uint32_t PIO3_4;                 /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */

+

+  __IO uint32_t PIO2_4;                 /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */

+  __IO uint32_t PIO2_5;                 /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */

+  __IO uint32_t PIO3_5;                 /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */

+  __IO uint32_t PIO0_6;                 /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */

+  __IO uint32_t PIO0_7;                 /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */

+  __IO uint32_t PIO2_9;                 /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */

+  __IO uint32_t PIO2_10;                /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */

+  __IO uint32_t PIO2_2;                 /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */

+

+  __IO uint32_t PIO0_8;                 /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */

+  __IO uint32_t PIO0_9;                 /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */

+  __IO uint32_t SWCLK_PIO0_10;          /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */

+  __IO uint32_t PIO1_10;                /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */

+  __IO uint32_t PIO2_11;                /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */

+  __IO uint32_t R_PIO0_11;              /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */

+  __IO uint32_t R_PIO1_0;               /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */

+  __IO uint32_t R_PIO1_1;               /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */

+

+  __IO uint32_t R_PIO1_2;               /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */

+  __IO uint32_t PIO3_0;                 /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */

+  __IO uint32_t PIO3_1;                 /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */

+  __IO uint32_t PIO2_3;                 /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */

+  __IO uint32_t SWDIO_PIO1_3;           /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */

+  __IO uint32_t PIO1_4;                 /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */

+  __IO uint32_t PIO1_11;                /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */

+  __IO uint32_t PIO3_2;                 /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */

+

+  __IO uint32_t PIO1_5;                 /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */

+  __IO uint32_t PIO1_6;                 /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */

+  __IO uint32_t PIO1_7;                 /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */

+  __IO uint32_t PIO3_3;                 /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */

+  __IO uint32_t SCK_LOC;                /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */

+  __IO uint32_t DSR_LOC;                /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */

+  __IO uint32_t DCD_LOC;                /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */

+  __IO uint32_t RI_LOC;                 /*!< Offset: 0x0BC RI pin location Register (R/W) */

+} LPC_IOCON_TypeDef;

+/*@}*/ /* end of group LPC11xx_IOCON */

+

+

+/*------------- Power Management Unit (PMU) --------------------------*/

+/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t PCON;                   /*!< Offset: 0x000 Power control Register (R/W) */

+  __IO uint32_t GPREG0;                 /*!< Offset: 0x004 General purpose Register 0 (R/W) */

+  __IO uint32_t GPREG1;                 /*!< Offset: 0x008 General purpose Register 1 (R/W) */

+  __IO uint32_t GPREG2;                 /*!< Offset: 0x00C General purpose Register 2 (R/W) */

+  __IO uint32_t GPREG3;                 /*!< Offset: 0x010 General purpose Register 3 (R/W) */

+  __IO uint32_t GPREG4;                 /*!< Offset: 0x014 General purpose Register 4 (R/W) */

+} LPC_PMU_TypeDef;

+/*@}*/ /* end of group LPC11xx_PMU */

+

+

+/*------------- General Purpose Input/Output (GPIO) --------------------------*/

+/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output 

+  @{

+*/

+typedef struct

+{

+  union {

+    __IO uint32_t MASKED_ACCESS[4096];  /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */

+    struct {

+         uint32_t RESERVED0[4095];

+    __IO uint32_t DATA;                 /*!< Offset: 0x3FFC Port data Register (R/W) */

+    };

+  };

+       uint32_t RESERVED1[4096];

+  __IO uint32_t DIR;                    /*!< Offset: 0x8000 Data direction Register (R/W) */

+  __IO uint32_t IS;                     /*!< Offset: 0x8004 Interrupt sense Register (R/W) */

+  __IO uint32_t IBE;                    /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */

+  __IO uint32_t IEV;                    /*!< Offset: 0x800C Interrupt event Register  (R/W) */

+  __IO uint32_t IE;                     /*!< Offset: 0x8010 Interrupt mask Register (R/W) */

+  __IO uint32_t RIS;                    /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */

+  __IO uint32_t MIS;                    /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */

+  __IO uint32_t IC;                     /*!< Offset: 0x801C Interrupt clear Register (R/W) */

+} LPC_GPIO_TypeDef;

+/*@}*/ /* end of group LPC11xx_GPIO */

+

+

+/*------------- Timer (TMR) --------------------------------------------------*/

+/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */

+  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */

+  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */

+  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */

+  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */

+  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */

+  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */

+  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */

+  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */

+  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */

+  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */

+  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */

+       uint32_t RESERVED1[3];

+  __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */

+       uint32_t RESERVED2[12];

+  __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */

+  __IO uint32_t PWMC;                   /*!< Offset: 0x074 PWM Control Register (R/W) */

+} LPC_TMR_TypeDef;

+/*@}*/ /* end of group LPC11xx_TMR */

+

+

+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/

+/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter 

+  @{

+*/

+typedef struct

+{

+  union {

+  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */

+  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */

+  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */

+  };

+  union {

+  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */

+  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */

+  };

+  union {

+  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */

+  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */

+  };

+  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */

+  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */

+  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */

+  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */

+  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */

+  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */

+       uint32_t  RESERVED0;

+  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */

+       uint32_t  RESERVED1;

+  __IO uint32_t  TER;                   /*!< Offset: 0x030 Transmit Enable Register (R/W) */

+       uint32_t  RESERVED2[6];

+  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */

+  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */

+  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */

+  __I  uint32_t  FIFOLVL;               /*!< Offset: 0x058 FIFO Level Register (R/ ) */

+} LPC_UART_TypeDef;

+/*@}*/ /* end of group LPC11xx_UART */

+

+

+/*------------- Synchronous Serial Communication (SSP) -----------------------*/

+/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */

+  __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */

+  __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */

+  __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */

+  __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */

+  __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */

+  __IO uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */

+  __IO uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */

+  __IO uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */

+} LPC_SSP_TypeDef;

+/*@}*/ /* end of group LPC11xx_SSP */

+

+

+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/

+/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */

+  __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */

+  __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */

+  __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */

+  __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */

+  __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */

+  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */

+  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */

+  __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */

+  __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */

+  __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */

+  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */

+  __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */

+  __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */

+  __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */

+  __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */

+} LPC_I2C_TypeDef;

+/*@}*/ /* end of group LPC11xx_I2C */

+

+

+/*------------- Watchdog Timer (WDT) -----------------------------------------*/

+/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W) */

+  __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W) */

+  __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register ( /W) */

+  __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R/ ) */

+       uint32_t RESERVED0;

+  __IO uint32_t WARNINT;

+  __IO uint32_t WINDOW;

+} LPC_WDT_TypeDef;

+/*@}*/ /* end of group LPC11xx_WDT */

+

+

+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/

+/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */

+  __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */

+       uint32_t RESERVED0;

+  __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */

+  __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */

+  __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */

+} LPC_ADC_TypeDef;

+/*@}*/ /* end of group LPC11xx_ADC */

+

+

+/*------------- CAN Controller (CAN) ----------------------------*/

+/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN) 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t CNTL;				/* 0x000 */

+  __IO uint32_t STAT;

+  __IO uint32_t EC;

+  __IO uint32_t BT;

+  __IO uint32_t INT;

+  __IO uint32_t TEST;

+  __IO uint32_t BRPE;

+       uint32_t RESERVED0;

+  __IO uint32_t IF1_CMDREQ;			/* 0x020 */

+  __IO uint32_t IF1_CMDMSK;

+  __IO uint32_t IF1_MSK1;

+  __IO uint32_t IF1_MSK2;

+  __IO uint32_t IF1_ARB1;

+  __IO uint32_t IF1_ARB2;

+  __IO uint32_t IF1_MCTRL;

+  __IO uint32_t IF1_DA1;

+  __IO uint32_t IF1_DA2;

+  __IO uint32_t IF1_DB1;

+  __IO uint32_t IF1_DB2;

+       uint32_t RESERVED1[13];   

+  __IO uint32_t IF2_CMDREQ;			/* 0x080 */

+  __IO uint32_t IF2_CMDMSK;

+  __IO uint32_t IF2_MSK1;

+  __IO uint32_t IF2_MSK2;

+  __IO uint32_t IF2_ARB1;

+  __IO uint32_t IF2_ARB2;

+  __IO uint32_t IF2_MCTRL;

+  __IO uint32_t IF2_DA1;

+  __IO uint32_t IF2_DA2;

+  __IO uint32_t IF2_DB1;

+  __IO uint32_t IF2_DB2;

+	   uint32_t RESERVED2[21];

+  __I  uint32_t TXREQ1;				/* 0x100 */

+  __I  uint32_t TXREQ2;

+	   uint32_t RESERVED3[6];

+  __I  uint32_t ND1;				/* 0x120 */

+  __I  uint32_t ND2;

+	   uint32_t RESERVED4[6];

+  __I  uint32_t IR1;				/* 0x140 */

+  __I  uint32_t IR2;

+	   uint32_t RESERVED5[6];

+  __I  uint32_t MSGV1;				/* 0x160 */

+  __I  uint32_t MSGV2;

+	   uint32_t RESERVED6[6];

+  __IO uint32_t CLKDIV;				/* 0x180 */

+} LPC_CAN_TypeDef;

+/*@}*/ /* end of group LPC11xx_CAN */

+

+#if defined ( __CC_ARM   )

+#pragma no_anon_unions

+#endif

+

+/******************************************************************************/

+/*                         Peripheral memory map                              */

+/******************************************************************************/

+/* Base addresses                                                             */

+#define LPC_FLASH_BASE        (0x00000000UL)

+#define LPC_RAM_BASE          (0x10000000UL)

+#define LPC_APB0_BASE         (0x40000000UL)

+#define LPC_AHB_BASE          (0x50000000UL)

+

+/* APB0 peripherals                                                           */

+#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x00000)

+#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x04000)

+#define LPC_UART_BASE         (LPC_APB0_BASE + 0x08000)

+#define LPC_CT16B0_BASE       (LPC_APB0_BASE + 0x0C000)

+#define LPC_CT16B1_BASE       (LPC_APB0_BASE + 0x10000)

+#define LPC_CT32B0_BASE       (LPC_APB0_BASE + 0x14000)

+#define LPC_CT32B1_BASE       (LPC_APB0_BASE + 0x18000)

+#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x1C000)

+#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x38000)

+#define LPC_SSP0_BASE         (LPC_APB0_BASE + 0x40000)

+#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)

+#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)

+#define LPC_CAN_BASE          (LPC_APB0_BASE + 0x50000)

+#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x58000)

+

+/* AHB peripherals                                                            */	

+#define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)

+#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)

+#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)

+#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x20000)

+#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x30000)

+

+/******************************************************************************/

+/*                         Peripheral declaration                             */

+/******************************************************************************/

+#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )

+#define LPC_WDT               ((LPC_WDT_TypeDef    *) LPC_WDT_BASE   )

+#define LPC_UART              ((LPC_UART_TypeDef   *) LPC_UART_BASE  )

+#define LPC_TMR16B0           ((LPC_TMR_TypeDef    *) LPC_CT16B0_BASE)

+#define LPC_TMR16B1           ((LPC_TMR_TypeDef    *) LPC_CT16B1_BASE)

+#define LPC_TMR32B0           ((LPC_TMR_TypeDef    *) LPC_CT32B0_BASE)

+#define LPC_TMR32B1           ((LPC_TMR_TypeDef    *) LPC_CT32B1_BASE)

+#define LPC_ADC               ((LPC_ADC_TypeDef    *) LPC_ADC_BASE   )

+#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )

+#define LPC_SSP0              ((LPC_SSP_TypeDef    *) LPC_SSP0_BASE  )

+#define LPC_SSP1              ((LPC_SSP_TypeDef    *) LPC_SSP1_BASE  )

+#define LPC_CAN               ((LPC_CAN_TypeDef    *) LPC_CAN_BASE   )

+#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )

+#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)

+#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )

+#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )

+#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )

+#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif  /* __LPC11xx_H__ */

diff --git a/inc/core_cm0.h b/inc/core_cm0.h
new file mode 100644
index 0000000..4f7fb25
--- /dev/null
+++ b/inc/core_cm0.h
@@ -0,0 +1,618 @@
+/**************************************************************************//**

+ * @file     core_cm0.h

+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File

+ * @version  V2.03

+ * @date     23. May 2011

+ *

+ * @note

+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.

+ *

+ * @par

+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 

+ * processor based microcontrollers.  This file can be freely distributed 

+ * within development tools that are supporting such ARM based processors. 

+ *

+ * @par

+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

+ *

+ ******************************************************************************/

+#if defined ( __ICCARM__ )                   

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifdef __cplusplus

+ extern "C" {

+#endif 

+

+#ifndef __CORE_CM0_H_GENERIC

+#define __CORE_CM0_H_GENERIC

+

+

+/** \mainpage CMSIS Cortex-M0

+   

+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.

+  It consists of:

+ 

+     - Cortex-M Core Register Definitions

+     - Cortex-M functions

+     - Cortex-M instructions

+ 

+  The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease 

+  access to the Cortex-M Core

+ */ 

+

+/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration

+  List of Lint messages which will be suppressed and not shown:

+    - not yet checked

+  .

+  Note:  To re-enable a Message, insert a space before 'lint' *

+ 

+ */

+

+

+/*******************************************************************************

+ *                 CMSIS definitions

+ ******************************************************************************/

+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions

+  This file defines all structures and symbols for CMSIS core:

+   - CMSIS version number

+   - Cortex-M core 

+   - Cortex-M core Revision Number

+  @{

+ */

+

+/*  CMSIS CM0 definitions */

+#define __CM0_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */

+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */

+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */

+

+#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */

+

+

+#if defined ( __CC_ARM   )

+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

+

+#elif defined ( __ICCARM__ )

+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */

+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

+

+#elif defined   (  __GNUC__  )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+

+#elif defined   (  __TASKING__  )

+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

+

+#endif

+

+#include <stdint.h>                      /*!< standard types definitions                      */

+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */

+#include "core_cmFunc.h"                 /*!< Core Function Access                            */

+

+#endif /* __CORE_CM0_H_GENERIC */

+

+

+#ifndef __CMSIS_GENERIC

+

+#ifndef __CORE_CM0_H_DEPENDANT

+#define __CORE_CM0_H_DEPENDANT

+

+/* IO definitions (access restrictions to peripheral registers) */

+#ifdef __cplusplus

+  #define     __I     volatile           /*!< defines 'read only' permissions                 */

+#else

+  #define     __I     volatile const     /*!< defines 'read only' permissions                 */

+#endif

+#define     __O     volatile             /*!< defines 'write only' permissions                */

+#define     __IO    volatile             /*!< defines 'read / write' permissions              */

+

+/*@} end of group CMSIS_core_definitions */

+

+

+

+/*******************************************************************************

+ *                 Register Abstraction

+ ******************************************************************************/

+/** \defgroup CMSIS_core_register CMSIS Core Register

+  Core Register contain:

+  - Core Register

+  - Core NVIC Register

+  - Core SCB Register

+  - Core SysTick Register

+*/

+

+/** \ingroup  CMSIS_core_register   

+    \defgroup CMSIS_CORE CMSIS Core

+  Type definitions for the Cortex-M Core Registers

+  @{

+ */

+

+/** \brief  Union type to access the Application Program Status Register (APSR).

+ */

+typedef union

+{

+  struct

+  {

+#if (__CORTEX_M != 0x04)

+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

+#else

+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

+#endif

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */ 

+} APSR_Type;

+

+

+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} IPSR_Type;

+

+

+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+#if (__CORTEX_M != 0x04)

+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

+#else

+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

+#endif

+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} xPSR_Type;

+

+

+/** \brief  Union type to access the Control Registers (CONTROL).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} CONTROL_Type;

+

+/*@} end of group CMSIS_CORE */

+

+

+/** \ingroup  CMSIS_core_register   

+    \defgroup CMSIS_NVIC CMSIS NVIC

+  Type definitions for the Cortex-M NVIC Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

+ */

+typedef struct

+{

+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

+       uint32_t RESERVED0[31];

+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */

+       uint32_t RSERVED1[31];

+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */

+       uint32_t RESERVED2[31];

+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */

+       uint32_t RESERVED3[31];

+       uint32_t RESERVED4[64];

+  __IO uint32_t IPR[8];                  /*!< Offset: 0x3EC (R/W)  Interrupt Priority Register              */

+}  NVIC_Type;

+

+/*@} end of group CMSIS_NVIC */

+

+

+/** \ingroup  CMSIS_core_register   

+    \defgroup CMSIS_SCB CMSIS SCB

+  Type definitions for the Cortex-M System Control Block Registers

+  @{

+ */

+

+/** \brief  Structure type to access the System Control Block (SCB).

+ */

+typedef struct

+{

+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */

+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */

+       uint32_t RESERVED0;                                      

+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */

+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

+       uint32_t RESERVED1;                                      

+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */

+} SCB_Type;                                                

+

+/* SCB CPUID Register Definitions */

+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

+

+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

+

+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

+

+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

+

+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

+

+/* SCB Interrupt Control State Register Definitions */

+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

+

+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

+

+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

+

+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

+

+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

+

+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

+

+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

+

+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

+

+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

+

+/* SCB Application Interrupt and Reset Control Register Definitions */

+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

+

+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

+

+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

+

+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

+

+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

+

+/* SCB System Control Register Definitions */

+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

+

+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

+

+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

+

+/* SCB Configuration Control Register Definitions */

+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

+

+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

+

+/*@} end of group CMSIS_SCB */

+

+

+/** \ingroup  CMSIS_core_register   

+    \defgroup CMSIS_SysTick CMSIS SysTick

+  Type definitions for the Cortex-M System Timer Registers

+  @{

+ */

+

+/** \brief  Structure type to access the System Timer (SysTick).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

+} SysTick_Type;

+

+/* SysTick Control / Status Register Definitions */

+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

+

+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

+

+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

+

+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

+

+/* SysTick Reload Register Definitions */

+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

+

+/* SysTick Current Register Definitions */

+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

+

+/* SysTick Calibration Register Definitions */

+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

+

+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

+

+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */

+

+/*@} end of group CMSIS_SysTick */

+

+

+/** \ingroup  CMSIS_core_register   

+    \defgroup CMSIS_CoreDebug CMSIS Core Debug

+  Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP 

+  and not via processor. Therefore they are not covered by the Cortex-M0 header file.

+  @{

+ */

+

+/*@} end of group CMSIS_CoreDebug */

+

+

+/** \ingroup  CMSIS_core_register   

+  @{

+ */

+ 

+/* Memory mapping of Cortex-M0 Hardware */

+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */

+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */

+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */

+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

+

+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */

+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */

+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */

+

+/*@} */

+

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+ ******************************************************************************/

+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface

+  Core Function Interface contains:

+  - Core NVIC Functions

+  - Core SysTick Functions

+  - Core Register Access Functions

+*/

+

+

+

+/* ##########################   NVIC functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface   

+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions

+  @{

+ */

+

+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

+/* The following MACROS handle generation of the register offset and byte masks */

+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )

+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )

+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )

+

+

+/** \brief  Enable External Interrupt

+

+    This function enables a device specific interrupt in the NVIC interrupt controller.

+    The interrupt number cannot be a negative value. 

+

+    \param [in]      IRQn  Number of the external interrupt to enable

+ */

+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+}

+

+

+/** \brief  Disable External Interrupt

+

+    This function disables a device specific interupt in the NVIC interrupt controller.

+    The interrupt number cannot be a negative value. 

+

+    \param [in]      IRQn  Number of the external interrupt to disable

+ */

+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+}

+

+

+/** \brief  Get Pending Interrupt

+

+    This function reads the pending register in the NVIC and returns the pending bit

+    for the specified interrupt. 

+

+    \param [in]      IRQn  Number of the interrupt for get pending

+    \return             0  Interrupt status is not pending

+    \return             1  Interrupt status is pending

+ */

+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

+{

+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));

+}

+

+

+/** \brief  Set Pending Interrupt

+

+    This function sets the pending bit for the specified interrupt. 

+    The interrupt number cannot be a negative value.

+

+    \param [in]      IRQn  Number of the interrupt for set pending

+ */

+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+}

+

+

+/** \brief  Clear Pending Interrupt

+

+    This function clears the pending bit for the specified interrupt. 

+    The interrupt number cannot be a negative value.

+

+    \param [in]      IRQn  Number of the interrupt for clear pending

+ */

+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

+}

+

+

+/** \brief  Set Interrupt Priority

+

+    This function sets the priority for the specified interrupt. The interrupt 

+    number can be positive to specify an external (device specific) 

+    interrupt, or negative to specify an internal (core) interrupt.

+

+    Note: The priority cannot be set for every core interrupt.

+

+    \param [in]      IRQn  Number of the interrupt for set priority

+    \param [in]  priority  Priority to set

+ */

+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

+{

+  if(IRQn < 0) {

+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 

+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

+  else {

+    NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

+}

+

+

+/** \brief  Get Interrupt Priority

+

+    This function reads the priority for the specified interrupt. The interrupt 

+    number can be positive to specify an external (device specific) 

+    interrupt, or negative to specify an internal (core) interrupt.

+

+    The returned priority value is automatically aligned to the implemented

+    priority bits of the microcontroller.

+

+    \param [in]   IRQn  Number of the interrupt for get priority

+    \return             Interrupt Priority

+ */

+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

+{

+

+  if(IRQn < 0) {

+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */

+  else {

+    return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

+}

+

+

+/** \brief  System Reset

+

+    This function initiate a system reset request to reset the MCU.

+ */

+static __INLINE void NVIC_SystemReset(void)

+{

+  __DSB();                                                     /* Ensure all outstanding memory accesses included

+                                                                  buffered write are completed before reset */              

+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 

+                 SCB_AIRCR_SYSRESETREQ_Msk);

+  __DSB();                                                     /* Ensure completion of memory access */              

+  while(1);                                                    /* wait until reset */

+}

+

+/*@} end of CMSIS_Core_NVICFunctions */

+

+

+

+/* ##################################    SysTick function  ############################################ */

+/** \ingroup  CMSIS_Core_FunctionInterface   

+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions

+  @{

+ */

+

+#if (__Vendor_SysTickConfig == 0)

+

+/** \brief  System Tick Configuration

+

+    This function initialises the system tick timer and its interrupt and start the system tick timer.

+    Counter is in free running mode to generate periodical interrupts.

+

+    \param [in]  ticks  Number of ticks between two interrupts

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+static __INLINE uint32_t SysTick_Config(uint32_t ticks)

+{ 

+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */

+                                                               

+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */

+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 

+                   SysTick_CTRL_TICKINT_Msk   | 

+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

+  return (0);                                                  /* Function successful */

+}

+

+#endif

+

+/*@} end of CMSIS_Core_SysTickFunctions */

+

+

+

+

+#endif /* __CORE_CM0_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

+

+#ifdef __cplusplus

+}

+#endif

+

+/*lint -restore */

diff --git a/inc/core_cmFunc.h b/inc/core_cmFunc.h
new file mode 100644
index 0000000..1ff04d9
--- /dev/null
+++ b/inc/core_cmFunc.h
@@ -0,0 +1,844 @@
+/**************************************************************************//**

+ * @file     core_cmFunc.h

+ * @brief    CMSIS Cortex-M Core Function Access Header File

+ * @version  V2.01

+ * @date     06. December 2010

+ *

+ * @note

+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.

+ *

+ * @par

+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 

+ * processor based microcontrollers.  This file can be freely distributed 

+ * within development tools that are supporting such ARM based processors. 

+ *

+ * @par

+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

+ *

+ ******************************************************************************/

+

+#ifndef __CORE_CMFUNC_H__

+#define __CORE_CMFUNC_H__

+

+/* ###########################  Core Function Access  ########################### */

+/** \ingroup  CMSIS_Core_FunctionInterface   

+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

+  @{

+ */

+

+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/

+/* ARM armcc specific functions */

+

+/* intrinsic void __enable_irq();     */

+/* intrinsic void __disable_irq();    */

+

+/** \brief  Get Control Register

+

+    This function returns the content of the Control Register.

+

+    \return               Control Register value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_CONTROL(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t __get_CONTROL(void)

+{

+  register uint32_t __regControl         __ASM("control");

+  return(__regControl);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Set Control Register

+

+    This function writes the given value to the Control Register.

+

+    \param [in]    control  Control Register value to set

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          void __set_CONTROL(uint32_t control);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE void __set_CONTROL(uint32_t control)

+{

+  register uint32_t __regControl         __ASM("control");

+  __regControl = control;

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Get ISPR Register

+

+    This function returns the content of the ISPR Register.

+

+    \return               ISPR Register value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_IPSR(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t __get_IPSR(void)

+{

+  register uint32_t __regIPSR          __ASM("ipsr");

+  return(__regIPSR);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_APSR(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t __get_APSR(void)

+{

+  register uint32_t __regAPSR          __ASM("apsr");

+  return(__regAPSR);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Get xPSR Register

+

+    This function returns the content of the xPSR Register.

+

+    \return               xPSR Register value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_xPSR(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t __get_xPSR(void)

+{

+  register uint32_t __regXPSR          __ASM("xpsr");

+  return(__regXPSR);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Get Process Stack Pointer

+

+    This function returns the current value of the Process Stack Pointer (PSP).

+

+    \return               PSP Register value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_PSP(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t __get_PSP(void)

+{

+  register uint32_t __regProcessStackPointer  __ASM("psp");

+  return(__regProcessStackPointer);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the Process Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          void __set_PSP(uint32_t topOfProcStack);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE void __set_PSP(uint32_t topOfProcStack)

+{

+  register uint32_t __regProcessStackPointer  __ASM("psp");

+  __regProcessStackPointer = topOfProcStack;

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Get Main Stack Pointer

+

+    This function returns the current value of the Main Stack Pointer (MSP).

+

+    \return               MSP Register value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_MSP(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t __get_MSP(void)

+{

+  register uint32_t __regMainStackPointer     __ASM("msp");

+  return(__regMainStackPointer);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Set Main Stack Pointer

+

+    This function assigns the given value to the Main Stack Pointer (MSP).

+

+    \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          void __set_MSP(uint32_t topOfMainStack);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE void __set_MSP(uint32_t topOfMainStack)

+{

+  register uint32_t __regMainStackPointer     __ASM("msp");

+  __regMainStackPointer = topOfMainStack;

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Get Priority Mask

+

+    This function returns the current state of the priority mask bit from the Priority Mask Register.

+

+    \return               Priority Mask value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_PRIMASK(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t __get_PRIMASK(void)

+{

+  register uint32_t __regPriMask         __ASM("primask");

+  return(__regPriMask);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Set Priority Mask

+

+    This function assigns the given value to the Priority Mask Register.

+

+    \param [in]    priMask  Priority Mask

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          void __set_PRIMASK(uint32_t priMask);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE void __set_PRIMASK(uint32_t priMask)

+{

+  register uint32_t __regPriMask         __ASM("primask");

+  __regPriMask = (priMask);

+}

+#endif /*  __ARMCC_VERSION  */ 

+ 

+

+#if       (__CORTEX_M >= 0x03)

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __enable_fault_irq                __enable_fiq

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __disable_fault_irq               __disable_fiq

+

+

+/** \brief  Get Base Priority

+

+    This function returns the current value of the Base Priority register.

+

+    \return               Base Priority register value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_BASEPRI(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t  __get_BASEPRI(void)

+{

+  register uint32_t __regBasePri         __ASM("basepri");

+  return(__regBasePri);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Set Base Priority

+

+    This function assigns the given value to the Base Priority register.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          void __set_BASEPRI(uint32_t basePri);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE void __set_BASEPRI(uint32_t basePri)

+{

+  register uint32_t __regBasePri         __ASM("basepri");

+  __regBasePri = (basePri & 0xff);

+}

+#endif /*  __ARMCC_VERSION  */ 

+ 

+

+/** \brief  Get Fault Mask

+

+    This function returns the current value of the Fault Mask register.

+

+    \return               Fault Mask register value

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          uint32_t __get_FAULTMASK(void);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE uint32_t __get_FAULTMASK(void)

+{

+  register uint32_t __regFaultMask       __ASM("faultmask");

+  return(__regFaultMask);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+

+/** \brief  Set Fault Mask

+

+    This function assigns the given value to the Fault Mask register.

+

+    \param [in]    faultMask  Fault Mask value to set

+ */

+#if       (__ARMCC_VERSION <  400000)

+extern          void __set_FAULTMASK(uint32_t faultMask);

+#else  /* (__ARMCC_VERSION >= 400000) */

+static __INLINE void __set_FAULTMASK(uint32_t faultMask)

+{

+  register uint32_t __regFaultMask       __ASM("faultmask");

+  __regFaultMask = (faultMask & 1);

+}

+#endif /*  __ARMCC_VERSION  */ 

+

+#endif /* (__CORTEX_M >= 0x03) */

+

+

+#if       (__CORTEX_M == 0x04)

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+static __INLINE uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1)

+  register uint32_t __regfpscr         __ASM("fpscr");

+  return(__regfpscr);

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+static __INLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1)

+  register uint32_t __regfpscr         __ASM("fpscr");

+  __regfpscr = (fpscr);

+#endif

+}

+

+#endif /* (__CORTEX_M == 0x04) */

+

+

+ #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/

+/* IAR iccarm specific functions */

+

+#if defined (__ICCARM__)

+  #include <intrinsics.h>                     /* IAR Intrinsics   */

+#endif

+

+#pragma diag_suppress=Pe940

+

+/** \brief  Enable IRQ Interrupts

+

+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+#define __enable_irq                              __enable_interrupt

+

+

+/** \brief  Disable IRQ Interrupts

+

+  This function disables IRQ interrupts by setting the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+#define __disable_irq                             __disable_interrupt

+

+

+/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */

+/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */

+

+

+/** \brief  Get ISPR Register

+

+    This function returns the content of the ISPR Register.

+

+    \return               ISPR Register value

+ */

+static uint32_t __get_IPSR(void)

+{

+  __ASM("mrs r0, ipsr");

+}

+

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+static uint32_t __get_APSR(void)

+{

+  __ASM("mrs r0, apsr");

+}

+

+

+/** \brief  Get xPSR Register

+

+    This function returns the content of the xPSR Register.

+

+    \return               xPSR Register value

+ */

+static uint32_t __get_xPSR(void)

+{

+  __ASM("mrs r0, psr");           // assembler does not know "xpsr"

+}

+

+

+/** \brief  Get Process Stack Pointer

+

+    This function returns the current value of the Process Stack Pointer (PSP).

+

+    \return               PSP Register value

+ */

+static uint32_t __get_PSP(void)

+{

+  __ASM("mrs r0, psp");

+}

+ 

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the Process Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+static void __set_PSP(uint32_t topOfProcStack)

+{

+  __ASM("msr psp, r0");

+}

+

+

+/** \brief  Get Main Stack Pointer

+

+    This function returns the current value of the Main Stack Pointer (MSP).

+

+    \return               MSP Register value

+ */

+static uint32_t __get_MSP(void)

+{

+  __ASM("mrs r0, msp");

+}

+ 

+

+/** \brief  Set Main Stack Pointer

+

+    This function assigns the given value to the Main Stack Pointer (MSP).

+

+    \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+static void __set_MSP(uint32_t topOfMainStack)

+{

+  __ASM("msr msp, r0");

+}

+ 

+

+/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */

+/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */

+ 

+

+#if       (__CORTEX_M >= 0x03)

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+static __INLINE void __enable_fault_irq(void)

+{

+  __ASM ("cpsie f");

+}

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+static __INLINE void __disable_fault_irq(void)

+{

+  __ASM ("cpsid f");

+}

+

+

+/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */

+/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */

+/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */

+/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */

+

+#endif /* (__CORTEX_M >= 0x03) */

+

+

+#if       (__CORTEX_M == 0x04)

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+static uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1)

+  __ASM("vmrs r0, fpscr"); 

+#else

+  return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+static void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1)

+  __ASM("vmsr fpscr, r0");

+#endif

+}

+

+#endif /* (__CORTEX_M == 0x04) */

+

+#pragma diag_default=Pe940

+

+

+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+/** \brief  Enable IRQ Interrupts

+

+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)

+{

+  __ASM volatile ("cpsie i");

+}

+

+

+/** \brief  Disable IRQ Interrupts

+

+  This function disables IRQ interrupts by setting the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)

+{

+  __ASM volatile ("cpsid i");

+}

+

+

+/** \brief  Get Control Register

+

+    This function returns the content of the Control Register.

+

+    \return               Control Register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, control" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Control Register

+

+    This function writes the given value to the Control Register.

+

+    \param [in]    control  Control Register value to set

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)

+{

+  __ASM volatile ("MSR control, %0" : : "r" (control) );

+}

+

+

+/** \brief  Get ISPR Register

+

+    This function returns the content of the ISPR Register.

+

+    \return               ISPR Register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get xPSR Register

+

+    This function returns the content of the xPSR Register.

+

+    \return               xPSR Register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get Process Stack Pointer

+

+    This function returns the current value of the Process Stack Pointer (PSP).

+

+    \return               PSP Register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );

+  return(result);

+}

+ 

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the Process Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)

+{

+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );

+}

+

+

+/** \brief  Get Main Stack Pointer

+

+    This function returns the current value of the Main Stack Pointer (MSP).

+

+    \return               MSP Register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );

+  return(result);

+}

+ 

+

+/** \brief  Set Main Stack Pointer

+

+    This function assigns the given value to the Main Stack Pointer (MSP).

+

+    \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)

+{

+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );

+}

+

+

+/** \brief  Get Priority Mask

+

+    This function returns the current state of the priority mask bit from the Priority Mask Register.

+

+    \return               Priority Mask value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, primask" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Priority Mask

+

+    This function assigns the given value to the Priority Mask Register.

+

+    \param [in]    priMask  Priority Mask

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)

+{

+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );

+}

+ 

+

+#if       (__CORTEX_M >= 0x03)

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)

+{

+  __ASM volatile ("cpsie f");

+}

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)

+{

+  __ASM volatile ("cpsid f");

+}

+

+

+/** \brief  Get Base Priority

+

+    This function returns the current value of the Base Priority register.

+

+    \return               Base Priority register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)

+{

+  uint32_t result;

+  

+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Base Priority

+

+    This function assigns the given value to the Base Priority register.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)

+{

+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );

+}

+

+

+/** \brief  Get Fault Mask

+

+    This function returns the current value of the Fault Mask register.

+

+    \return               Fault Mask register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)

+{

+  uint32_t result;

+  

+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Fault Mask

+

+    This function assigns the given value to the Fault Mask register.

+

+    \param [in]    faultMask  Fault Mask value to set

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)

+{

+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );

+}

+

+#endif /* (__CORTEX_M >= 0x03) */

+

+

+#if       (__CORTEX_M == 0x04)

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1)

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );

+  return(result);

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1)

+  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );

+#endif

+}

+

+#endif /* (__CORTEX_M == 0x04) */

+

+

+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/

+/* TASKING carm specific functions */

+

+/*

+ * The CMSIS functions have been implemented as intrinsics in the compiler.

+ * Please use "carm -?i" to get an up to date list of all instrinsics,

+ * Including the CMSIS ones.

+ */

+

+#endif

+

+/*@} end of CMSIS_Core_RegAccFunctions */

+

+

+#endif /* __CORE_CMFUNC_H__ */

diff --git a/inc/core_cmInstr.h b/inc/core_cmInstr.h
new file mode 100644
index 0000000..95ce06c
--- /dev/null
+++ b/inc/core_cmInstr.h
@@ -0,0 +1,775 @@
+/**************************************************************************//**

+ * @file     core_cmInstr.h

+ * @brief    CMSIS Cortex-M Core Instruction Access Header File

+ * @version  V2.01

+ * @date     06. December 2010

+ *

+ * @note

+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.

+ *

+ * @par

+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 

+ * processor based microcontrollers.  This file can be freely distributed 

+ * within development tools that are supporting such ARM based processors. 

+ *

+ * @par

+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

+ *

+ ******************************************************************************/

+

+#ifndef __CORE_CMINSTR_H__

+#define __CORE_CMINSTR_H__

+

+

+/* ##########################  Core Instruction Access  ######################### */

+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

+  Access to dedicated instructions

+  @{

+*/

+

+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/

+/* ARM armcc specific functions */

+

+/** \brief  No Operation

+

+    No Operation does nothing. This instruction can be used for code alignment purposes.

+ */

+#define __NOP                             __nop

+

+

+/** \brief  Wait For Interrupt

+

+    Wait For Interrupt is a hint instruction that suspends execution

+    until one of a number of events occurs.

+ */

+#define __WFI                             __wfi

+

+

+/** \brief  Wait For Event

+

+    Wait For Event is a hint instruction that permits the processor to enter

+    a low-power state until one of a number of events occurs.

+ */

+#define __WFE                             __wfe

+

+

+/** \brief  Send Event

+

+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ */

+#define __SEV                             __sev

+

+

+/** \brief  Instruction Synchronization Barrier

+

+    Instruction Synchronization Barrier flushes the pipeline in the processor, 

+    so that all instructions following the ISB are fetched from cache or 

+    memory, after the instruction has been completed.

+ */

+#define __ISB()                           __isb(0xF)

+

+

+/** \brief  Data Synchronization Barrier

+

+    This function acts as a special kind of Data Memory Barrier. 

+    It completes when all explicit memory accesses before this instruction complete.

+ */

+#define __DSB()                           __dsb(0xF)

+

+

+/** \brief  Data Memory Barrier

+

+    This function ensures the apparent order of the explicit memory operations before 

+    and after the instruction, without ensuring their completion.

+ */

+#define __DMB()                           __dmb(0xF)

+

+

+/** \brief  Reverse byte order (32 bit)

+

+    This function reverses the byte order in integer value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#define __REV                             __rev

+

+

+/** \brief  Reverse byte order (16 bit)

+

+    This function reverses the byte order in two unsigned short values.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#if (__ARMCC_VERSION < 400677)

+extern uint32_t __REV16(uint32_t value);

+#else  /* (__ARMCC_VERSION >= 400677)  */

+static __INLINE __ASM uint32_t __REV16(uint32_t value)

+{

+  rev16 r0, r0

+  bx lr

+}

+#endif /* __ARMCC_VERSION  */ 

+

+

+/** \brief  Reverse byte order in signed short value

+

+    This function reverses the byte order in a signed short value with sign extension to integer.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#if (__ARMCC_VERSION < 400677)

+extern int32_t __REVSH(int32_t value);

+#else  /* (__ARMCC_VERSION >= 400677)  */

+static __INLINE __ASM int32_t __REVSH(int32_t value)

+{

+  revsh r0, r0

+  bx lr

+}

+#endif /* __ARMCC_VERSION  */ 

+

+

+#if       (__CORTEX_M >= 0x03)

+

+/** \brief  Reverse bit order of value

+

+    This function reverses the bit order of the given value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#define __RBIT                            __rbit

+

+

+/** \brief  LDR Exclusive (8 bit)

+

+    This function performs a exclusive LDR command for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))

+

+

+/** \brief  LDR Exclusive (16 bit)

+

+    This function performs a exclusive LDR command for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))

+

+

+/** \brief  LDR Exclusive (32 bit)

+

+    This function performs a exclusive LDR command for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))

+

+

+/** \brief  STR Exclusive (8 bit)

+

+    This function performs a exclusive STR command for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXB(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  STR Exclusive (16 bit)

+

+    This function performs a exclusive STR command for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXH(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  STR Exclusive (32 bit)

+

+    This function performs a exclusive STR command for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXW(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  Remove the exclusive lock

+

+    This function removes the exclusive lock which is created by LDREX.

+

+ */

+#if (__ARMCC_VERSION < 400000)

+extern void __CLREX(void);

+#else  /* (__ARMCC_VERSION >= 400000)  */

+#define __CLREX                           __clrex

+#endif /* __ARMCC_VERSION  */ 

+

+

+/** \brief  Signed Saturate

+

+    This function saturates a signed value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (1..32)

+    \return             Saturated value

+ */

+#define __SSAT                            __ssat

+

+

+/** \brief  Unsigned Saturate

+

+    This function saturates an unsigned value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (0..31)

+    \return             Saturated value

+ */

+#define __USAT                            __usat

+

+

+/** \brief  Count leading zeros

+

+    This function counts the number of leading zeros of a data value.

+

+    \param [in]  value  Value to count the leading zeros

+    \return             number of leading zeros in value

+ */

+#define __CLZ                             __clz 

+

+#endif /* (__CORTEX_M >= 0x03) */

+

+

+

+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/

+/* IAR iccarm specific functions */

+

+#include <intrinsics.h>                     /* IAR Intrinsics   */

+

+#pragma diag_suppress=Pe940

+

+/** \brief  No Operation

+

+    No Operation does nothing. This instruction can be used for code alignment purposes.

+ */

+#define __NOP                           __no_operation

+

+

+/** \brief  Wait For Interrupt

+

+    Wait For Interrupt is a hint instruction that suspends execution

+    until one of a number of events occurs.

+ */

+static __INLINE  void __WFI(void)

+{

+  __ASM ("wfi");

+}

+

+

+/** \brief  Wait For Event

+

+    Wait For Event is a hint instruction that permits the processor to enter

+    a low-power state until one of a number of events occurs.

+ */

+static __INLINE  void __WFE(void)

+{

+  __ASM ("wfe");

+}

+

+

+/** \brief  Send Event

+

+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ */

+static __INLINE  void __SEV(void)

+{

+  __ASM ("sev");

+}

+

+

+/* intrinsic     void __ISB(void)            (see intrinsics.h) */

+/* intrinsic     void __DSB(void)            (see intrinsics.h) */

+/* intrinsic     void __DMB(void)            (see intrinsics.h) */

+/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */

+/* intrinsic          __SSAT                 (see intrinsics.h) */

+/* intrinsic          __USAT                 (see intrinsics.h) */

+

+

+/** \brief  Reverse byte order (16 bit)

+

+    This function reverses the byte order in two unsigned short values.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+static uint32_t __REV16(uint32_t value)

+{

+  __ASM("rev16 r0, r0");

+}

+

+

+/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */

+

+

+#if       (__CORTEX_M >= 0x03)

+

+/** \brief  Reverse bit order of value

+

+    This function reverses the bit order of the given value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+static uint32_t __RBIT(uint32_t value)

+{

+  __ASM("rbit r0, r0");

+}

+

+

+/** \brief  LDR Exclusive (8 bit)

+

+    This function performs a exclusive LDR command for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+static uint8_t __LDREXB(volatile uint8_t *addr)

+{

+  __ASM("ldrexb r0, [r0]");

+}

+

+

+/** \brief  LDR Exclusive (16 bit)

+

+    This function performs a exclusive LDR command for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+static uint16_t __LDREXH(volatile uint16_t *addr)

+{

+  __ASM("ldrexh r0, [r0]");

+}

+

+

+/** \brief  LDR Exclusive (32 bit)

+

+    This function performs a exclusive LDR command for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */

+static uint32_t __LDREXW(volatile uint32_t *addr)

+{

+  __ASM("ldrex r0, [r0]");

+}

+

+

+/** \brief  STR Exclusive (8 bit)

+

+    This function performs a exclusive STR command for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

+{

+  __ASM("strexb r0, r0, [r1]");

+}

+

+

+/** \brief  STR Exclusive (16 bit)

+

+    This function performs a exclusive STR command for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

+{

+  __ASM("strexh r0, r0, [r1]");

+}

+

+

+/** \brief  STR Exclusive (32 bit)

+

+    This function performs a exclusive STR command for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/

+static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

+{

+  __ASM("strex r0, r0, [r1]");

+}

+

+

+/** \brief  Remove the exclusive lock

+

+    This function removes the exclusive lock which is created by LDREX.

+

+ */

+static __INLINE void __CLREX(void)

+{

+  __ASM ("clrex");

+}

+

+/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */

+

+#endif /* (__CORTEX_M >= 0x03) */

+

+#pragma diag_default=Pe940

+

+

+

+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+/** \brief  No Operation

+

+    No Operation does nothing. This instruction can be used for code alignment purposes.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)

+{

+  __ASM volatile ("nop");

+}

+

+

+/** \brief  Wait For Interrupt

+

+    Wait For Interrupt is a hint instruction that suspends execution

+    until one of a number of events occurs.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)

+{

+  __ASM volatile ("wfi");

+}

+

+

+/** \brief  Wait For Event

+

+    Wait For Event is a hint instruction that permits the processor to enter

+    a low-power state until one of a number of events occurs.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)

+{

+  __ASM volatile ("wfe");

+}

+

+

+/** \brief  Send Event

+

+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)

+{

+  __ASM volatile ("sev");

+}

+

+

+/** \brief  Instruction Synchronization Barrier

+

+    Instruction Synchronization Barrier flushes the pipeline in the processor, 

+    so that all instructions following the ISB are fetched from cache or 

+    memory, after the instruction has been completed.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)

+{

+  __ASM volatile ("isb");

+}

+

+

+/** \brief  Data Synchronization Barrier

+

+    This function acts as a special kind of Data Memory Barrier. 

+    It completes when all explicit memory accesses before this instruction complete.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)

+{

+  __ASM volatile ("dsb");

+}

+

+

+/** \brief  Data Memory Barrier

+

+    This function ensures the apparent order of the explicit memory operations before 

+    and after the instruction, without ensuring their completion.

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)

+{

+  __ASM volatile ("dmb");

+}

+

+

+/** \brief  Reverse byte order (32 bit)

+

+    This function reverses the byte order in integer value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)

+{

+  uint32_t result;

+  

+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );

+  return(result);

+}

+

+

+/** \brief  Reverse byte order (16 bit)

+

+    This function reverses the byte order in two unsigned short values.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)

+{

+  uint32_t result;

+  

+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );

+  return(result);

+}

+

+

+/** \brief  Reverse byte order in signed short value

+

+    This function reverses the byte order in a signed short value with sign extension to integer.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)

+{

+  uint32_t result;

+  

+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );

+  return(result);

+}

+

+

+#if       (__CORTEX_M >= 0x03)

+

+/** \brief  Reverse bit order of value

+

+    This function reverses the bit order of the given value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)

+{

+  uint32_t result;

+  

+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

+   return(result);

+}

+

+

+/** \brief  LDR Exclusive (8 bit)

+

+    This function performs a exclusive LDR command for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)

+{

+    uint8_t result;

+  

+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );

+   return(result);

+}

+

+

+/** \brief  LDR Exclusive (16 bit)

+

+    This function performs a exclusive LDR command for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)

+{

+    uint16_t result;

+  

+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );

+   return(result);

+}

+

+

+/** \brief  LDR Exclusive (32 bit)

+

+    This function performs a exclusive LDR command for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)

+{

+    uint32_t result;

+  

+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (8 bit)

+

+    This function performs a exclusive STR command for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

+{

+   uint32_t result;

+  

+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (16 bit)

+

+    This function performs a exclusive STR command for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

+{

+   uint32_t result;

+  

+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (32 bit)

+

+    This function performs a exclusive STR command for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

+{

+   uint32_t result;

+  

+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );

+   return(result);

+}

+

+

+/** \brief  Remove the exclusive lock

+

+    This function removes the exclusive lock which is created by LDREX.

+

+ */

+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)

+{

+  __ASM volatile ("clrex");

+}

+

+

+/** \brief  Signed Saturate

+

+    This function saturates a signed value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (1..32)

+    \return             Saturated value

+ */

+#define __SSAT(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+

+/** \brief  Unsigned Saturate

+

+    This function saturates an unsigned value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (0..31)

+    \return             Saturated value

+ */

+#define __USAT(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+

+/** \brief  Count leading zeros

+

+    This function counts the number of leading zeros of a data value.

+

+    \param [in]  value  Value to count the leading zeros

+    \return             number of leading zeros in value

+ */

+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)

+{

+  uint8_t result;

+  

+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );

+  return(result);

+}

+

+#endif /* (__CORTEX_M >= 0x03) */

+

+

+

+

+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/

+/* TASKING carm specific functions */

+

+/*

+ * The CMSIS functions have been implemented as intrinsics in the compiler.

+ * Please use "carm -?i" to get an up to date list of all instrinsics,

+ * Including the CMSIS ones.

+ */

+

+#endif

+

+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

+

+#endif /* __CORE_CMINSTR_H__ */

diff --git a/inc/system_LPC11xx.h b/inc/system_LPC11xx.h
new file mode 100644
index 0000000..385fe38
--- /dev/null
+++ b/inc/system_LPC11xx.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**

+ * @file     system_LPC11xx.h

+ * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File

+ *           for the NXP LPC11xx Device Series

+ * @version  V1.00

+ * @date     17. November 2009

+ *

+ * @note

+ * Copyright (C) 2009 ARM Limited. All rights reserved.

+ *

+ * @par

+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 

+ * processor based microcontrollers.  This file can be freely distributed 

+ * within development tools that are supporting such ARM based processors. 

+ *

+ * @par

+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

+ *

+ ******************************************************************************/

+

+

+#ifndef __SYSTEM_LPC11xx_H

+#define __SYSTEM_LPC11xx_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include <stdint.h>

+

+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */

+

+

+/**

+ * Initialize the system

+ *

+ * @param  none

+ * @return none

+ *

+ * @brief  Setup the microcontroller system.

+ *         Initialize the System and update the SystemCoreClock variable.

+ */

+extern void SystemInit (void);

+

+/**

+ * Update SystemCoreClock variable

+ *

+ * @param  none

+ * @return none

+ *

+ * @brief  Updates the SystemCoreClock with current core Clock 

+ *         retrieved from cpu registers.

+ */

+extern void SystemCoreClockUpdate (void);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __SYSTEM_LPC11x_H */

diff --git a/main.c b/main.c
new file mode 100644
index 0000000..297c18f
--- /dev/null
+++ b/main.c
@@ -0,0 +1,202 @@
+/** \file main.c

+ * \brief Sample LPC1114 project

+ * \details This file holds a very basic code for LPC1114. This code configures

+ * flash access time, enables the PLL and all required clocks and peripherals

+ * to achieve the highest allowed frequency for LPC1114 (50MHz). Main code

+ * block just blinks the LED. The LED port and pin are defined in config.h

+ * file. Target core frequency and quartz crystal resonator frequency are

+ * defined there as well.

+ *

+ * \author Freddie Chopin, http://www.freddiechopin.info/

+ * \date 2012-01-08

+ */

+

+/******************************************************************************

+* project: lpc1114_blink_led

+* chip: LPC1114

+* compiler: arm-none-eabi-gcc (Sourcery CodeBench Lite 2011.09-69) 4.6.1

+*

+* prefix: (none)

+*

+* available global functions:

+* 	int main(void)

+*

+* available local functions:

+* 	static void flash_access_time(uint32_t frequency)

+* 	static uint32_t pll_start(uint32_t crystal, uint32_t frequency)

+* 	static void system_init(void)

+*

+* available interrupt handlers:

+******************************************************************************/

+

+/*

++=============================================================================+

+| includes

++=============================================================================+

+*/

+

+#include <stdint.h>

+

+#include "inc/LPC11xx.h"

+

+#include "config.h"

+

+#include "hdr/hdr_syscon.h"

+

+/*

++=============================================================================+

+| module variables

++=============================================================================+

+*/

+

+/*

++=============================================================================+

+| local functions' declarations

++=============================================================================+

+*/

+

+static void flash_access_time(uint32_t frequency);

+static uint32_t pll_start(uint32_t crystal, uint32_t frequency);

+static void system_init(void);

+

+/*

++=============================================================================+

+| global functions

++=============================================================================+

+*/

+

+/*------------------------------------------------------------------------*//**

+* \brief main code block

+* \details Call some static initialization functions and blink the led with

+* frequency defined via count_max variable.

+*//*-------------------------------------------------------------------------*/

+

+int main(void)

+{

+	volatile uint32_t count, count_max = 1000000;	// with core frequency ~50MHz this gives ~1.5Hz blinking frequency

+

+	pll_start(CRYSTAL, FREQUENCY);			// start the PLL

+	system_init();							// initialize other necessary elements

+

+	LED_GPIO->DIR |= LED;					// set the direction of the LED pin to output

+

+	while (1)

+	{

+		for (count = 0; count < count_max; count++);	// delay

+		LED_gma = LED;						// instead of LED_GPIO->DATA |= LED;

+		for (count = 0; count < count_max; count++);	// delay

+		LED_gma = 0;						// instead of LED_GPIO->DATA &= ~LED;

+	}

+}

+

+/*

++=============================================================================+

+| local functions

++=============================================================================+

+*/

+

+/*------------------------------------------------------------------------*//**

+* \brief Configures flash access time.

+* \details Configures flash access time which allows the chip to run at higher

+* speeds.

+*

+* \param [in] frequency defines the target frequency of the core

+*//*-------------------------------------------------------------------------*/

+

+static void flash_access_time(uint32_t frequency)

+{

+	uint32_t access_time, flashcfg_register;

+

+	if (frequency < 20000000ul)				// 1 system clock for core speed below 20MHz

+		access_time = FLASHCFG_FLASHTIM_1CLK;

+	else if (frequency < 40000000ul)		// 2 system clocks for core speed between 20MHz and 40MHz

+		access_time = FLASHCFG_FLASHTIM_2CLK;

+	else									// 3 system clocks for core speed over 40MHz

+		access_time = FLASHCFG_FLASHTIM_3CLK;

+

+	// do not modify reserved bits in FLASHCFG register

+	flashcfg_register = FLASHCFG;			// read register

+	flashcfg_register &= ~(FLASHCFG_FLASHTIM_mask << FLASHCFG_FLASHTIM_bit);	// mask the FLASHTIM field

+	flashcfg_register |= access_time << FLASHCFG_FLASHTIM_bit;	// use new FLASHTIM value

+	FLASHCFG = flashcfg_register;			// save the new value back to the register

+}

+

+/*------------------------------------------------------------------------*//**

+* \brief Starts the PLL.

+* \details Configure and enable PLL to achieve some frequency with some

+* crystal. Before the speed change flash access time is configured via

+* flash_access_time(). Main oscillator is configured and started. PLL

+* parameters m and p are based on function parameters. The PLL is configured,

+* started and selected as the main clock. AHB clock divider is set to 1.

+*

+* \param [in] crystal is the frequency of the crystal resonator connected to

+* the LPC1114 chip.

+* \param [in] frequency is the desired target frequency after enabling the PLL

+*

+* \return real frequency that was set

+*//*-------------------------------------------------------------------------*/

+

+static uint32_t pll_start(uint32_t crystal, uint32_t frequency)

+{

+	uint32_t m, p = 0, fcco;

+

+	flash_access_time(frequency);			// configure flash access time first

+

+	// SYSOSCCTRL_FREQRANGE should be 0 for crystals in range 1 - 20MHz

+	// SYSOSCCTRL_FREQRANGE should be 1 for crystals in range 15 - 25MHz

+	if (crystal < 17500000)					// divide the ranges on 17.5MHz then

+		LPC_SYSCON->SYSOSCCTRL = 0;			// "lower speed" crystals

+	else

+		LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_FREQRANGE;	// "higher speed" crystals

+

+	LPC_SYSCON->PDRUNCFG &= ~PDRUNCFG_SYSOSC_PD;	// power-up main oscillator

+

+	LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_SEL_IRC;	// select main oscillator as the input clock for PLL

+	LPC_SYSCON->SYSPLLCLKUEN = 0;			// confirm the change of PLL input clock by toggling the...

+	LPC_SYSCON->SYSPLLCLKUEN = SYSPLLUEN_ENA;	// ...ENA bit in LPC_SYSCON->SYSPLLCLKUEN register

+

+	// calculate PLL parameters

+	m = frequency / crystal;				// M is the PLL multiplier

+	fcco = m * crystal * 2;					// FCCO is the internal PLL frequency

+

+	frequency = crystal * m;

+

+	while (fcco < 156000000)

+	{

+		fcco *= 2;

+		p++;								// find P which gives FCCO in the allowed range (over 156MHz)

+	}

+

+	LPC_SYSCON->SYSPLLCTRL = ((m - 1) << SYSPLLCTRL_MSEL_bit) | (p << SYSPLLCTRL_PSEL_bit);	// configure PLL

+	LPC_SYSCON->PDRUNCFG &= ~PDRUNCFG_SYSPLL_PD; // power-up PLL

+

+	while (!(LPC_SYSCON->SYSPLLSTAT & SYSPLLSTAT_LOCK));	// wait for PLL lock

+

+	LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_SEL_PLLOUT;	// select PLL output as the main clock

+	LPC_SYSCON->MAINCLKUEN = 0;				// confirm the change of main clock by toggling the...

+	LPC_SYSCON->MAINCLKUEN = MAINCLKUEN_ENA;	// ...ENA bit in LPC_SYSCON->MAINCLKUEN register

+

+	LPC_SYSCON->SYSAHBCLKDIV = 1;			// set AHB clock divider to 1

+

+	return frequency;

+}

+

+/*------------------------------------------------------------------------*//**

+* \brief Initializes system.

+* \details Enables clock for IO configuration block.

+*//*-------------------------------------------------------------------------*/

+

+static void system_init(void)

+{

+	LPC_SYSCON->SYSAHBCLKCTRL |= SYSAHBCLKCTRL_IOCON;	// enable clock for IO configuration block

+}

+

+/*

++=============================================================================+

+| ISRs

++=============================================================================+

+*/

+

+/******************************************************************************

+* END OF FILE

+******************************************************************************/

diff --git a/myapp.strace b/myapp.strace
new file mode 100644
index 0000000..4983565
--- /dev/null
+++ b/myapp.strace
@@ -0,0 +1,38 @@
+read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\3\0\1\0\0\0`\20\0\0004\0\0\0hq\0\0\0\0\0\0004\0 \0\7\0(\0\32\0\31\0\1\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\20a\0\0\20a\0\0\5\0\0\0\0\20\0\0\1\0\0\0\364n\0\0\364~\0\0\364~\0\0\200\1\0\0\320\25\0\0\6\0\0\0\0\20\0\0\2\0\0\0\10o\0\0\10\177\0\0\10\177\0\0\310\0\0\0\310\0\0\0\6\0\0\0\4\0\0\0\4\0\0\0\24\1\0\0\24\1\0\0\24\1\0\0$\0\0\0$\0\0\0\4\0\0\0\4\0\0\0P\345td\304W\0\0\304W\0\0\304W\0\0l\1\0\0l\1\0\0\4\0\0\0\4\0\0\0Q\345td\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\6\0\0\0\4\0\0\0R\345td\364n\0\0\364~\0\0\364~\0\0\f\1\0\0\f\1\0\0\4\0\0\0\1\0\0\0\4\0\0\0\24\0\0\0\3\0\0\0GNU\0\217,\37\32\213\33\222IW\226\2229-+\30\371\5\347\357\357%\0\0\0\37\0\0\0\20\0\0\0\t\0\0\0\20\0\2\200r\f\"\200!\200\6\0\0 B\n8\221B\0\0\201\20\200e\0\0`\310@@BQ\0\0\0\0\0\27\220\254@\202\201X\2 \0\10\0\0 D\20\2\t!\0(\1\210\6\0(\37\0\0\0\0\0\0\0 \0\0\0#\0\0\0\0\0\0\0$\0\0\0'\0\0\0\0\0\0\0(\0\0\0)\0\0\0,\0\0\0.\0\0\0\0\0\0\0/\0\0\0001\0\0\0005\0\0\0008\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0:\0\0\0\0\0\0\0;\0\0\0\0\0\0\0>\0\0\0A\0\0\0C\0\0\0D\0\0\0E\0\0\0G\0\0\0", 512) = 512
+read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\3\0\1\0\0\0\20\271\1\0004\0\0\0\350\275\24\0\0\0\0\0004\0 \0\7\0(\0\34\0\33\0\1\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\20k\24\0\20k\24\0\5\0\0\0\0\20\0\0\1\0\0\0\260s\24\0\260s\24\0\260s\24\0(I\0\0DX\0\0\6\0\0\0\0\20\0\0\2\0\0\0\310\255\24\0\310\255\24\0\310\255\24\0\360\0\0\0\360\0\0\0\6\0\0\0\4\0\0\0\4\0\0\0\24\1\0\0\24\1\0\0\24\1\0\0$\0\0\0$\0\0\0\4\0\0\0\4\0\0\0P\345td<U\22\0<U\22\0<U\22\0TN\0\0TN\0\0\4\0\0\0\4\0\0\0Q\345td\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\6\0\0\0\4\0\0\0R\345td\260s\24\0\260s\24\0\260s\24\0P<\0\0P<\0\0\4\0\0\0\1\0\0\0\4\0\0\0\24\0\0\0\3\0\0\0GNU\0\252\202n[\375\17$Z\316\2166\340fD\262\"\2559\32\333\7\4\0\0p\0\0\0\0\2\0\0\16\0\0\0\20\30\305 \2\10\0\204\0\f\0\0\204B\30\4\"0\0$\31\6\4\304\1 \t\264@ \342\2\0\21\200\25\0\30\6\4\24DA0\200\0\20\30\0\1\220\0\10\20\0\"\21P!`K\10 \203\0\200\0\200D\0\6\5 \206\340`\0\4\10\0\0002\220\4\0\24@\0\260\2\t\301\0@\10\23\3\0011\20\4\0\2\0\4\24\32I\2\34\200\2\10\0\1\201HA\245DR\210\10\202\0\0\0\0\\\231\0ZTH\10\0\200\26@\0\4\0@\300\0\0\fH\214@\5\0\200\0\0\4\1\10\25\20\200@\200\20 \22\302\20H p\0\0\0\0\0\2d@@\4\305@\0", 512) = 512
+read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\3\0\1\0\0\0p\222\1\0004\0\0\0P\253\27\0\0\0\0\0004\0 \0\n\0(\0#\0\"\0\6\0\0\0004\0\0\0004\0\0\0004\0\0\0@\1\0\0@\1\0\0\5\0\0\0\4\0\0\0\3\0\0\0h8\24\0h8\24\0h8\24\0\23\0\0\0\23\0\0\0\4\0\0\0\1\0\0\0\1\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\30s\27\0\30s\27\0\5\0\0\0\0\20\0\0\1\0\0\0\354\201\27\0\354\201\27\0\354\201\27\0\320'\0\0,X\0\0\6\0\0\0\0\20\0\0\2\0\0\0|\235\27\0|\235\27\0|\235\27\0\360\0\0\0\360\0\0\0\6\0\0\0\4\0\0\0\4\0\0\0t\1\0\0t\1\0\0t\1\0\0D\0\0\0D\0\0\0\4\0\0\0\4\0\0\0\7\0\0\0\354\201\27\0\354\201\27\0\354\201\27\0\10\0\0\0@\0\0\0\4\0\0\0\4\0\0\0P\345td|8\24\0|8\24\0|8\24\0\264s\0\0\264s\0\0\4\0\0\0\4\0\0\0Q\345td\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\6\0\0\0\4\0\0\0R\345td\354\201\27\0\354\201\27\0\354\201\27\0\24\36\0\0\24\36\0\0\4\0\0\0\1\0\0\0\4\0\0\0\24\0\0\0\3\0\0\0GNU\0\17\307\237\222\347\233\31\324\22138%\216\240\30\324Z\25qY\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\17\0\0\0\363\3\0\0\t\0\0\0\0\2\0\0\16\0\0\0\2400\20D\200 \2\1\214\3\346\220AE\210\0\204\0\10\0E\200\0`\300\200\0\f\212\f\0\0010\0\10@2\10\256\4\210H6l\240\0260\0&\204\200\216\4\10B$", 512) = 512
+read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\3\0\1\0\0\0`\n\0\0004\0\0\0t1\0\0\0\0\0\0004\0 \0\t\0(\0 \0\37\0\6\0\0\0004\0\0\0004\0\0\0004\0\0\0 \1\0\0 \1\0\0\5\0\0\0\4\0\0\0\3\0\0\0\307\32\0\0\307\32\0\0\307\32\0\0\23\0\0\0\23\0\0\0\4\0\0\0\1\0\0\0\1\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\!\0\0\\!\0\0\5\0\0\0\0\20\0\0\1\0\0\0\244.\0\0\244>\0\0\244>\0\0\240\1\0\0\324\1\0\0\6\0\0\0\0\20\0\0\2\0\0\0\300.\0\0\300>\0\0\300>\0\0\10\1\0\0\10\1\0\0\6\0\0\0\4\0\0\0\4\0\0\0T\1\0\0T\1\0\0T\1\0\0D\0\0\0D\0\0\0\4\0\0\0\4\0\0\0P\345td\334\32\0\0\334\32\0\0\334\32\0\0\324\0\0\0\324\0\0\0\4\0\0\0\4\0\0\0Q\345td\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\6\0\0\0\4\0\0\0R\345td\244.\0\0\244>\0\0\244>\0\0\\\1\0\0\\\1\0\0\4\0\0\0\1\0\0\0\4\0\0\0\24\0\0\0\3\0\0\0GNU\0\332_\367dc\335\347\0\210\317\236\2159\311\2304\25@\352#\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\17\0\0\0\26\0\0\0\30\0\0\0\4\0\0\0\7\0\0\0\230\0\21\0\0B\0\0\202\0`\10\223(\10\336\30\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\31\0\0\0\0\0\0\0\32\0\0\0\33\0\0\0\0\0\0\0\35\0\0\0\0\0\0\0\0\0\0\0\36\0\0\0 \0\0\0!\0\0\0\0\0\0\0\0\0\0\0\"\0\0\0", 512) = 512
+read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\3\0\1\0\0\0`\27\0\0004\0\0\0\0242\1\0\0\0\0\0004\0 \0\7\0(\0\34\0\33\0\1\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\10.\1\0\10.\1\0\5\0\0\0\0\20\0\0\1\0\0\0\34.\1\0\34>\1\0\34>\1\0\354\2\0\0\364\2\0\0\6\0\0\0\0\20\0\0\2\0\0\0\350.\1\0\350>\1\0\350>\1\0\330\0\0\0\330\0\0\0\6\0\0\0\4\0\0\0\4\0\0\0\24\1\0\0\24\1\0\0\24\1\0\0$\0\0\0$\0\0\0\4\0\0\0\4\0\0\0P\345td\240-\1\0\240-\1\0\240-\1\0\24\0\0\0\24\0\0\0\4\0\0\0\4\0\0\0Q\345td\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\6\0\0\0\4\0\0\0R\345td\34.\1\0\34>\1\0\34>\1\0\344\1\0\0\344\1\0\0\4\0\0\0\1\0\0\0\4\0\0\0\24\0\0\0\3\0\0\0GNU\0\375\31\232H\361~\204\264\341\371\341\264\312\264T \256+x\313C\0\0\0\37\0\0\0\20\0\0\0\t\0\0\0\10\3l\24\f\0\0\24!\0\3I\232\0\226\20\234\0\4\f\21\4\0\200<\0B\242\220\27\213\3\2Kp\363\4\202\20B\0l\0\0\250\241\200\237@\224\21E G\302!P\0\16\20\6\200 \20\37\0\0\0 \0\0\0!\0\0\0\"\0\0\0$\0\0\0\0\0\0\0\0\0\0\0%\0\0\0\0\0\0\0&\0\0\0'\0\0\0*\0\0\0-\0\0\0.\0\0\0\0\0\0\0000\0\0\0\0\0\0\0001\0\0\0003\0\0\0004\0\0\0006\0\0\0008\0\0\0\0\0\0\0009\0\0\0:\0\0\0;\0\0\0\0\0\0\0<\0\0\0\0\0\0\0>\0\0\0", 512) = 512
+read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\3\0\1\0\0\0\2604\0\0004\0\0\0T\221\2\0\0\0\0\0004\0 \0\t\0(\0\36\0\35\0\6\0\0\0004\0\0\0004\0\0\0004\0\0\0 \1\0\0 \1\0\0\5\0\0\0\4\0\0\0\3\0\0\0\30'\2\0\30'\2\0\30'\2\0\23\0\0\0\23\0\0\0\4\0\0\0\1\0\0\0\1\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0P\177\2\0P\177\2\0\5\0\0\0\0\20\0\0\1\0\0\0\334\216\2\0\334\216\2\0\334\216\2\0`\1\0\0\244\1\0\0\6\0\0\0\0\20\0\0\2\0\0\0\360\216\2\0\360\216\2\0\360\216\2\0\350\0\0\0\350\0\0\0\6\0\0\0\4\0\0\0\4\0\0\0T\1\0\0T\1\0\0T\1\0\0D\0\0\0D\0\0\0\4\0\0\0\4\0\0\0P\345td,'\2\0,'\2\0,'\2\0\4\r\0\0\4\r\0\0\4\0\0\0\4\0\0\0Q\345td\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\6\0\0\0\4\0\0\0R\345td\334\216\2\0\334\216\2\0\334\216\2\0$\1\0\0$\1\0\0\4\0\0\0\1\0\0\0\4\0\0\0\24\0\0\0\3\0\0\0GNU\0\207\3678p\351\227\267\317e\354\261\6\340\2\210B\6\365%\303\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\17\0\0\0\214\2\0\0\20\0\0\0@\0\0\0\v\0\0\0%\220 \305\t\204g\v\0\302\20 \4iER\202\20\200\240\0}\210\272\10\10I\0\0\0\0\0\33\4\201\0\0\0\232U\20A P \200\224\202\220\21@\3722\0\304a\24\0\10\6\306\220\232\f\207\300 \250\0  \202\0\230\201\4E\7\0054a\2\0\0\251C\30\310", 512) = 512
+write(1, "VSProg 1.0 svn:\n", 16)       = 16
+write(1, "CopyRight(c) 2008-2010 by SimonQian <SimonQian@SimonQian.com>\n", 62) = 62
+write(1, "\n", 1)                       = 1
+write(1, "URL: http://www.SimonQian.com/en/Versaloon\n", 43) = 43
+write(1, "mail: SimonQian@SimonQian.com\n", 30) = 30
+write(1, "\n", 1)                       = 1
+read(3, "<?xml version=\"1.0\"?>\n<series name=\"lpc1000\">\n  <chip name=\"lpc1000\">\n    <chip_id>0x0000</chip_id>\n    <program_mode>j:JTAG(F)|s:SWD|i:ISP(C)</program_mode>\n    <sram_size>2048</sram_size>\n    <app_page_size>1024</app_page_size>\n    <app_page_num>512</app_page_num>\n    <app_default>0xFF</app_default>\n    <app_addr>0x00000000</app_addr>\n    <app_seg>0</app_seg>\n    <param0>4000</param0>\n  </chip>\n  <chip name=\"lpc1111fhn33/101\">\n    <chip_id>0x041E502B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>2048</sram_size>\n    <app_page_num>8</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1111fhn33/201\">\n    <chip_id>0x0416502B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>4096</sram_size>\n    <app_page_num>8</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1112fhn33/101\">\n    <chip_id>0x042D502B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>2048</sram_size>\n    <app_page_num>32</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1112fhn33/201\">\n    <chip_id>0x0425502B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>4096</sram_size>\n    <app_page_num>16</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1113fhn33/201\">\n    <chip_id>0x0434502B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>4096</sram_size>\n    <app_page_num>24</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1113fhn33/301\">\n    <chip_id>0x0434102B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>8192</sram_size>\n    <app_page_num>24</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1114fhn33/201\">\n    <chip_id>0x0444502B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>4096</sram_size>\n    <app_page_num>24</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1114fhn33/301\">\n    <chip_id>0x0444102B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>8192</sram_size>\n    <app_page_num>32</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1114fn28\">\n    <chip_id>0x1A40902B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>4096</sram_size>\n    <app_page_num>24</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc11c12fbd48/301\">\n    <chip_id>0x1421102B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>8192</sram_size>\n    <app_page_num>16</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc11c14fbd48/301\">\n    <chip_id>0x1440102B</chip_id>\n    <program_mode>si</program_mode>\n    <sram_size>8192</sram_size>\n    <app_page_num>32</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1311fhn33\">\n    <chip_id>0x2C42502B</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>2048</sram_size>\n    <app_page_num>8</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1313fhn33\">\n    <chip_id>0x2C40102B</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>8192</sram_size>\n    <app_page_num>32</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1342fhn33\">\n    <chip_id>0x3D01402B</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>4096</sram_size>\n    <app_page_num>16</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1343fhn33\">\n    <chip_id>0x3D00002B</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>8192</sram_size>\n    <app_page_num>32</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>12000</param0>\n    <param1>0x40048000</param1>\n    <param2>2</param2>\n  </chip>\n  <chip name=\"lpc1769\">\n    <chip_id>0x26113F37</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>65536</sram_size>\n    <app_page_num>512</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1768\">\n    <chip_id>0x26013F37</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>65536</sram_size>\n    <app_page_num>512</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1767\">\n    <chip_id>0x26012837</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>65536</sram_size>\n    <app_page_num>512</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1766\">\n    <chip_id>0x26013F33</chip_id>\n    <program_mode>jsi</program_mode>\n\t<sram_size>65536</sram_size>\n    <app_page_num>256</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1765\">\n    <chip_id>0x26013733</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>65536</sram_size>\n    <app_page_num>256</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1764\">\n    <chip_id>0x26011922</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>32768</sram_size>\n    <app_page_num>128</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1759\">\n    <chip_id>0x25113737</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>65536</sram_size>\n    <app_page_num>512</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1758\">\n    <chip_id>0x25013F37</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>65536</sram_size>\n    <app_page_num>512</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1756\">\n    <chip_id>0x25011723</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>32768</sram_size>\n    <app_page_num>256</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1754\">\n    <chip_id>0x25011722</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>32768</sram_size>\n    <app_page_num>128</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF\" format=\"%4x%4x%4x%4x\"></uid>\n    <param0>4000</param0>\n    <param1>0x400FC040</param1>\n    <param2>1</param2>\n  </chip>\n  <chip name=\"lpc1752\">\n    <chip_id>0x25001121</chip_id>\n    <program_mode>jsi</program_mode>\n    <sram_size>16384</sram_size>\n    <app_page_num>64</app_page_num>\n    <uid init=\"0xFF\" bytesize=\"16\" mask=\"0xFFFFFFFF:0xFFFFFFFF:0xFFFFFFFF:0x"..., 16384) = 10508
+read(3, "", 4096)                       = 0
+write(1, "Info:   Chip name undefined, try auto-detecting.\n", 49) = 49
+ioctl(3, SNDCTL_TMR_TIMEBASE or TCGETS, {B115200 -opost -isig -icanon -echo ...}) = 0
+ioctl(3, TCFLSH, 0)                     = 0
+ioctl(3, SNDCTL_TMR_TIMEBASE or TCGETS, {B115200 -opost -isig -icanon -echo ...}) = 0
+ioctl(3, SNDCTL_TMR_START or TCSETS, {B115200 -opost -isig -icanon -echo ...}) = 0
+ioctl(3, SNDCTL_TMR_TIMEBASE or TCGETS, {B115200 -opost -isig -icanon -echo ...}) = 0
+ioctl(3, TCFLSH, 0)                     = 0
+write(3, "?", 1)                        = 1
+read(3, "", 14)                         = 0
+write(3, "\33", 1)                      = 1
+ioctl(3, TCFLSH, 0)                     = 0
+write(3, "A 0\r", 4)                    = 4
+read(3, "", 7)                          = 0
+ioctl(3, TCFLSH, 0)                     = 0
+write(3, "?", 1)                        = 1
+read(3, "", 14)                         = 0
+write(3, "\33", 1)                      = 1
+ioctl(3, TCFLSH, 0)                     = 0
+write(3, "A 0\r", 4)                    = 4
+read(3, "", 7)                          = 0
+write(2, "Error:  Fail to enter program mode.\n", 36) = 36
+write(2, "Error:  lpc1000 auto-detect failed.\n", 36) = 36
+write(2, "Error:  Fail to initialize target.\n", 35) = 35
+write(2, "Error:  Fail to run command: prepare.\n", 38) = 38
diff --git a/startup.S b/startup.S
new file mode 100644
index 0000000..010b99a
--- /dev/null
+++ b/startup.S
@@ -0,0 +1,176 @@
+/******************************************************************************

+* author: Freddie Chopin, http://www.freddiechopin.info/

+* file: startup.S

+* last change: 2012-01-08

+*

+* chip: ARMv6-M (Cortex-M0)

+* compiler: arm-none-eabi-gcc (Sourcery CodeBench Lite 2011.09-69) 4.6.1

+*

+* description:

+* ARMv6-M (Cortex-M0) assembly startup code

+******************************************************************************/

+

+/*

++=============================================================================+

+| includes

++=============================================================================+

+*/

+

+#include "hdr/hdr_special_registers.h"

+

+/*

++=============================================================================+

+| ARMv6-M (Cortex-M0) startup code

++=============================================================================+

+*/

+

+.text

+.balign 2

+.syntax unified

+.thumb

+.thumb_func

+.global Reset_Handler

+

+Reset_Handler:

+

+/*

++-----------------------------------------------------------------------------+

+| Initialize the process stack pointer

++-----------------------------------------------------------------------------+

+*/

+

+	ldr		r0, =__process_stack_end

+	msr		PSP, r0

+

+/*

++-----------------------------------------------------------------------------+

+| Thread mode uses process stack (PSP). Thread mode on ARMv6-M is privileged.

++-----------------------------------------------------------------------------+

+*/

+

+	movs	r0, #CONTROL_ALTERNATE_STACK

+	msr		CONTROL, r0

+	isb

+

+/*

++-----------------------------------------------------------------------------+

+| Branch to low_level_init_0() function (.data and .bss are not initialized!)

++-----------------------------------------------------------------------------+

+*/

+

+	ldr		r0, =low_level_init_0

+	blx		r0

+

+/*

++-----------------------------------------------------------------------------+

+| Initialize .data section

++-----------------------------------------------------------------------------+

+*/

+

+	ldr		r1, =__data_init_start

+    ldr		r2, =__data_start

+    ldr		r3, =__data_end

+

+	b		2f

+1:	ldmia	r1!, {r0}

+	stmia	r2!, {r0}

+2:	cmp		r2, r3

+	bne		1b

+

+/*

++-----------------------------------------------------------------------------+

+| Zero-init .bss section

++-----------------------------------------------------------------------------+

+*/

+

+	movs	r0, #0

+	ldr		r1, =__bss_start

+	ldr		r2, =__bss_end

+

+	b		2f

+1:	stmia	r1!, {r0}

+2:	cmp		r1, r2

+	bne		1b

+

+

+/*

++-----------------------------------------------------------------------------+

+| Call C++ constructors for global and static objects

++-----------------------------------------------------------------------------+

+*/

+#ifdef __USES_CXX

+	ldr		r0, =__libc_init_array

+	blx		r0

+#endif

+

+/*

++-----------------------------------------------------------------------------+

+| Branch to low_level_init_1() function

++-----------------------------------------------------------------------------+

+*/

+

+	ldr		r0, =low_level_init_1

+	blx		r0

+

+/*

++-----------------------------------------------------------------------------+

+| Branch to main() with link

++-----------------------------------------------------------------------------+

+*/

+

+	ldr		r0, =main

+	blx		r0

+

+/*

++-----------------------------------------------------------------------------+

+| Call C++ destructors for global and static objects

++-----------------------------------------------------------------------------+

+*/

+#ifdef __USES_CXX

+	ldr		r0, =__libc_fini_array

+	blx		r0

+#endif

+

+/*

++-----------------------------------------------------------------------------+

+| On return - loop till the end of the world

++-----------------------------------------------------------------------------+

+*/

+

+	b		.

+

+/*

++=============================================================================+

+| __default_low_level_init() - replacement for undefined low_level_init_0()

+| and/or low_level_init_1(). This function just returns.

++=============================================================================+

+*/

+

+.text

+.balign 2

+.syntax unified

+.thumb

+.thumb_func

+.global __default_low_level_init

+

+__default_low_level_init:

+	bx		lr

+

+/*

++=============================================================================+

+| assign undefined low_level_init_0() and/or low_level_init_1() to

+| __default_low_level_init()

++=============================================================================+

+*/

+

+.weak	low_level_init_0

+.global	low_level_init_0

+.set	low_level_init_0, __default_low_level_init

+

+.weak	low_level_init_1

+.global	low_level_init_1

+.set	low_level_init_1, __default_low_level_init

+

+/******************************************************************************

+* END OF FILE

+******************************************************************************/

diff --git a/vectors.c b/vectors.c
new file mode 100644
index 0000000..a98fa1e
--- /dev/null
+++ b/vectors.c
@@ -0,0 +1,232 @@
+/** \file vectors.c

+ * \brief LPC11xx vector table and __Default_Handler()

+ * \details LPC11xx vector table and __Default_Handler()

+ * \author Freddie Chopin, http://www.freddiechopin.info/

+ * \date 2012-01-08

+ */

+

+/******************************************************************************

+* chip: LPC11xx

+* compiler: arm-none-eabi-gcc (Sourcery CodeBench Lite 2011.09-69) 4.6.1

+******************************************************************************/

+

+/*------------------------------------------------------------------------*//**

+* \brief Default interrupt handler.

+* \details Default interrupt handler, used for interrupts that don't have their

+* own handler defined.

+*//*-------------------------------------------------------------------------*/

+

+static void __Default_Handler(void) __attribute__ ((interrupt));

+static void __Default_Handler(void)

+{

+	while (1);

+}

+

+/*

++=============================================================================+

+| assign all unhandled interrupts to the default handler

++=============================================================================+

+*/

+

+// Reserved 0x08

+void __Reserved_0x08_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// All class of fault

+void HardFault_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x10

+void __Reserved_0x10_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x14

+void __Reserved_0x14_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x18

+void __Reserved_0x18_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x1C

+void __Reserved_0x1C_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x20

+void __Reserved_0x20_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x24

+void __Reserved_0x24_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x28

+void __Reserved_0x28_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// System service call via SWI instruction

+void SVC_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x30

+void __Reserved_0x30_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x34

+void __Reserved_0x34_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Pendable request for system service

+void PendSV_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// System tick timer

+void SysTick_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_0 interrupt

+void WAKEUP_PIO0_0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_1 interrupt

+void WAKEUP_PIO0_1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_2 interrupt

+void WAKEUP_PIO0_2_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_3 interrupt

+void WAKEUP_PIO0_3_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_4 interrupt

+void WAKEUP_PIO0_4_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_5 interrupt

+void WAKEUP_PIO0_5_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_6 interrupt

+void WAKEUP_PIO0_6_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_7 interrupt

+void WAKEUP_PIO0_7_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_8 interrupt

+void WAKEUP_PIO0_8_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_9 interrupt

+void WAKEUP_PIO0_9_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_10 interrupt

+void WAKEUP_PIO0_10_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO0_11 interrupt

+void WAKEUP_PIO0_11_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Start logic wake-up from PIO1_0 interrupt

+void WAKEUP_PIO1_0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// C_CAN interrupt (LPC11C12/C14 only)

+void CAN_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// SPI/SSP1 interrupt

+void SSP1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// I2C interrupt

+void I2C_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// CT16B0 (16-bit Timer0) interrupt

+void TIMER16_0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// CT16B1 (16-bit Timer1) interrupt

+void TIMER16_1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// CT32B0 (32-bit Timer0) interrupt

+void TIMER32_0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// CT32B1 (32-bit Timer1) interrupt

+void TIMER32_1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// SPI/SSP0 interrupt

+void SSP0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// UART interrupt

+void UART_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x98

+void __Reserved_0x98_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0x9C

+void __Reserved_0x9C_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// A/D Converter interrupt

+void ADC_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Watchdog timer interrupt

+void WDT_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Brown Out Detect interrupt

+void BOD_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// Reserved 0xAC

+void __Reserved_0xAC_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// PIO INT3 interrupt

+void PIOINT3_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// PIO INT2 interrupt

+void PIOINT2_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// PIO INT1 interrupt

+void PIOINT1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+// PIO INT0 interrupt

+void PIOINT0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));

+

+/*

++=============================================================================+

+| Vector table

++=============================================================================+

+*/

+

+extern const char __main_stack_end;			// imported main stack end (from linker script)

+

+void Reset_Handler(void);					// import the address of Reset_Handler()

+

+void (* const vectors[])(void) __attribute__ ((section(".vectors"))) = {

+		(void (*)(void))&__main_stack_end,	// Main stack end address

+		Reset_Handler,						// Reset

+		__Reserved_0x08_Handler,			// Reserved 0x08

+		HardFault_Handler,					// All class of fault

+		__Reserved_0x10_Handler,			// Reserved 0x10

+		__Reserved_0x14_Handler,			// Reserved 0x14

+		__Reserved_0x18_Handler,			// Reserved 0x18

+		__Reserved_0x1C_Handler,			// Reserved 0x1C

+		__Reserved_0x20_Handler,			// Reserved 0x20

+		__Reserved_0x24_Handler,			// Reserved 0x24

+		__Reserved_0x28_Handler,			// Reserved 0x28

+		SVC_Handler,						// System service call via SWI instruction

+		__Reserved_0x30_Handler,			// Reserved 0x30

+		__Reserved_0x34_Handler,			// Reserved 0x34

+		PendSV_Handler,						// Pendable request for system service

+		SysTick_Handler,					// System tick timer

+		WAKEUP_PIO0_0_IRQHandler,			// Start logic wake-up from PIO0_0 interrupt

+		WAKEUP_PIO0_1_IRQHandler,			// Start logic wake-up from PIO0_1 interrupt

+		WAKEUP_PIO0_2_IRQHandler,			// Start logic wake-up from PIO0_2 interrupt

+		WAKEUP_PIO0_3_IRQHandler,			// Start logic wake-up from PIO0_3 interrupt

+		WAKEUP_PIO0_4_IRQHandler,			// Start logic wake-up from PIO0_4 interrupt

+		WAKEUP_PIO0_5_IRQHandler,			// Start logic wake-up from PIO0_5 interrupt

+		WAKEUP_PIO0_6_IRQHandler,			// Start logic wake-up from PIO0_6 interrupt

+		WAKEUP_PIO0_7_IRQHandler,			// Start logic wake-up from PIO0_7 interrupt

+		WAKEUP_PIO0_8_IRQHandler,			// Start logic wake-up from PIO0_8 interrupt

+		WAKEUP_PIO0_9_IRQHandler,			// Start logic wake-up from PIO0_9 interrupt

+		WAKEUP_PIO0_10_IRQHandler,			// Start logic wake-up from PIO0_10 interrupt

+		WAKEUP_PIO0_11_IRQHandler,			// Start logic wake-up from PIO0_11 interrupt

+		WAKEUP_PIO1_0_IRQHandler,			// Start logic wake-up from PIO1_0 interrupt

+		CAN_IRQHandler,						// C_CAN interrupt (LPC11C12/C14 only)

+		SSP1_IRQHandler,					// SPI/SSP1 interrupt

+		I2C_IRQHandler,						// I2C interrupt

+		TIMER16_0_IRQHandler,				// CT16B0 (16-bit Timer0) interrupt

+		TIMER16_1_IRQHandler,				// CT16B1 (16-bit Timer1) interrupt

+		TIMER32_0_IRQHandler,				// CT32B0 (32-bit Timer0) interrupt

+		TIMER32_1_IRQHandler,				// CT32B1 (32-bit Timer1) interrupt

+		SSP0_IRQHandler,					// SPI/SSP0 interrupt

+		UART_IRQHandler,					// UART interrupt

+		__Reserved_0x98_Handler,			// Reserved 0x98

+		__Reserved_0x9C_Handler,			// Reserved 0x9C

+		ADC_IRQHandler,						// A/D Converter interrupt

+		WDT_IRQHandler,						// Watchdog timer interrupt

+		BOD_IRQHandler,						// Brown Out Detect interrupt

+		__Reserved_0xAC_Handler,			// Reserved 0xAC

+		PIOINT3_IRQHandler,					// PIO INT3 interrupt

+		PIOINT2_IRQHandler,					// PIO INT2 interrupt

+		PIOINT1_IRQHandler,					// PIO INT1 interrupt

+		PIOINT0_IRQHandler,					// PIO INT0 interrupt

+};

+

+/******************************************************************************

+* END OF FILE

+******************************************************************************/