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authorDean <Dean@d5102386-fcda-11dd-9fdb-3debd5008f28>2010-10-13 14:23:23 +0000
committerDean <Dean@d5102386-fcda-11dd-9fdb-3debd5008f28>2010-10-13 14:23:23 +0000
commit97965b37df3f9a63647a13ac4c31dc0a4e247d77 (patch)
tree496346e6ee123a9098ae4479de091c6807964fad /LUFA/Drivers/Peripheral
parent6910200d724af51b2460e848b7c7ea03912845e7 (diff)
Fix SoftUART.c not compiling due to accidental check in of changes not yet complete in the rest of the XPLAINBridge project code.
git-svn-id: http://lufa-lib.googlecode.com/svn/trunk@1526 d5102386-fcda-11dd-9fdb-3debd5008f28
Diffstat (limited to 'LUFA/Drivers/Peripheral')
-rw-r--r--LUFA/Drivers/Peripheral/AVRU4U6U7/ADC.h12
1 files changed, 8 insertions, 4 deletions
diff --git a/LUFA/Drivers/Peripheral/AVRU4U6U7/ADC.h b/LUFA/Drivers/Peripheral/AVRU4U6U7/ADC.h
index 0aaaa930..9b6f87a9 100644
--- a/LUFA/Drivers/Peripheral/AVRU4U6U7/ADC.h
+++ b/LUFA/Drivers/Peripheral/AVRU4U6U7/ADC.h
@@ -81,19 +81,23 @@
#define ADC_REFERENCE_INT2560MV ((1 << REFS1) | (1 << REFS0))
/** Left-adjusts the 10-bit ADC result, so that the upper 8 bits of the value returned by the
- * ADC_GetResult() macro contain the 8 most significant bits of the result. */
+ * ADC_GetResult() macro contain the 8 most significant bits of the result.
+ */
#define ADC_LEFT_ADJUSTED (1 << ADLAR)
/** Right-adjusts the 10-bit ADC result, so that the lower 8 bits of the value returned by the
- * ADC_GetResult() macro contain the 8 least significant bits of the result. */
+ * ADC_GetResult() macro contain the 8 least significant bits of the result.
+ */
#define ADC_RIGHT_ADJUSTED (0 << ADLAR)
/** Sets the ADC mode to free running, so that conversions take place continuously as fast as the ADC
- * is capable of at the given input clock speed. */
+ * is capable of at the given input clock speed.
+ */
#define ADC_FREE_RUNNING (1 << ADATE)
/** Sets the ADC mode to single conversion, so that only a single conversion will take place before
- * the ADC returns to idle. */
+ * the ADC returns to idle.
+ */
#define ADC_SINGLE_CONVERSION (0 << ADATE)
/** Sets the ADC input clock to prescale by a factor of 2 the AVR's system clock. */