diff options
| author | Scott Shawcroft <scott@tannewt.org> | 2017-09-22 18:05:51 -0700 |
|---|---|---|
| committer | Dan Halbert <halbert@halwitz.org> | 2017-09-22 21:05:51 -0400 |
| commit | 6839fff31303463d5c7942387fa498895edf1abf (patch) | |
| tree | f4c5b94c6534c8d5c65ea6b7209cd2d681508f5f /atmel-samd/asf4/samd21/include/instance | |
| parent | 3ad01ddb04b160b74b4baee9fce043da17dbcef5 (diff) | |
Move to ASF4 and introduce SAMD51 support. (#258)3.0.0-alpha.0
* atmel-samd: Remove ASF3. This will break builds.
* atmel-samd: Add ASF4 for the SAMD21 and SAMD51.
* Introduce the supervisor concept to facilitate porting.
The supervisor is the code which runs individual MicroPython VMs. By
splitting it out we make it more consistent and easier to find.
This also adds very basic SAMD21 and SAMD51 support using the
supervisor. Only the REPL currently works.
This begins the work for #178.
Diffstat (limited to 'atmel-samd/asf4/samd21/include/instance')
35 files changed, 3578 insertions, 0 deletions
diff --git a/atmel-samd/asf4/samd21/include/instance/ac.h b/atmel-samd/asf4/samd21/include/instance/ac.h new file mode 100644 index 000000000..af6120f6c --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/ac.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief Instance description for AC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_AC_INSTANCE_ +#define _SAMD21_AC_INSTANCE_ + +/* ========== Register definition for AC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AC_CTRLA (0x42004400) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (0x42004401) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (0x42004402) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (0x42004404) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (0x42004405) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (0x42004406) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (0x42004408) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (0x42004409) /**< \brief (AC) Status B */ +#define REG_AC_STATUSC (0x4200440A) /**< \brief (AC) Status C */ +#define REG_AC_WINCTRL (0x4200440C) /**< \brief (AC) Window Control */ +#define REG_AC_COMPCTRL0 (0x42004410) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (0x42004414) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SCALER0 (0x42004420) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (0x42004421) /**< \brief (AC) Scaler 1 */ +#else +#define REG_AC_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (*(WoReg8 *)0x42004401UL) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (*(RwReg16*)0x42004402UL) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (*(RoReg8 *)0x42004408UL) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (*(RoReg8 *)0x42004409UL) /**< \brief (AC) Status B */ +#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AUL) /**< \brief (AC) Status C */ +#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (AC) Window Control */ +#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410UL) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414UL) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420UL) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421UL) /**< \brief (AC) Scaler 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AC peripheral ========== */ +#define AC_CMP_NUM 2 // Number of comparators +#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog +#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital +#define AC_NUM_CMP 2 +#define AC_PAIRS 1 // Number of pairs of comparators + +#endif /* _SAMD21_AC_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/adc.h b/atmel-samd/asf4/samd21/include/instance/adc.h new file mode 100644 index 000000000..9b2b22820 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/adc.h @@ -0,0 +1,84 @@ +/** + * \file + * + * \brief Instance description for ADC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_ADC_INSTANCE_ +#define _SAMD21_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CTRLA (0x42004000) /**< \brief (ADC) Control A */ +#define REG_ADC_REFCTRL (0x42004001) /**< \brief (ADC) Reference Control */ +#define REG_ADC_AVGCTRL (0x42004002) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (0x42004003) /**< \brief (ADC) Sampling Time Control */ +#define REG_ADC_CTRLB (0x42004004) /**< \brief (ADC) Control B */ +#define REG_ADC_WINCTRL (0x42004008) /**< \brief (ADC) Window Monitor Control */ +#define REG_ADC_SWTRIG (0x4200400C) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_INPUTCTRL (0x42004010) /**< \brief (ADC) Input Control */ +#define REG_ADC_EVCTRL (0x42004014) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (0x42004016) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (0x42004017) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (0x42004018) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_STATUS (0x42004019) /**< \brief (ADC) Status */ +#define REG_ADC_RESULT (0x4200401A) /**< \brief (ADC) Result */ +#define REG_ADC_WINLT (0x4200401C) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (0x42004020) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (0x42004024) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (0x42004026) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_CALIB (0x42004028) /**< \brief (ADC) Calibration */ +#define REG_ADC_DBGCTRL (0x4200402A) /**< \brief (ADC) Debug Control */ +#else +#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000UL) /**< \brief (ADC) Control A */ +#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001UL) /**< \brief (ADC) Reference Control */ +#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002UL) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003UL) /**< \brief (ADC) Sampling Time Control */ +#define REG_ADC_CTRLB (*(RwReg16*)0x42004004UL) /**< \brief (ADC) Control B */ +#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008UL) /**< \brief (ADC) Window Monitor Control */ +#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CUL) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010UL) /**< \brief (ADC) Input Control */ +#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014UL) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016UL) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017UL) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018UL) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_STATUS (*(RoReg8 *)0x42004019UL) /**< \brief (ADC) Status */ +#define REG_ADC_RESULT (*(RoReg16*)0x4200401AUL) /**< \brief (ADC) Result */ +#define REG_ADC_WINLT (*(RwReg16*)0x4200401CUL) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (*(RwReg16*)0x42004020UL) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024UL) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026UL) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_CALIB (*(RwReg16*)0x42004028UL) /**< \brief (ADC) Calibration */ +#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AUL) /**< \brief (ADC) Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for ADC peripheral ========== */ +#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger +#define ADC_EXTCHANNEL_MSB 19 // Number of external channels +#define ADC_GCLK_ID 30 // Index of Generic Clock +#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield +#define ADC_RESULT_MSB 15 // Size of Result + +#endif /* _SAMD21_ADC_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/dac.h b/atmel-samd/asf4/samd21/include/instance/dac.h new file mode 100644 index 000000000..c034a56a5 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/dac.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Instance description for DAC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_DAC_INSTANCE_ +#define _SAMD21_DAC_INSTANCE_ + +/* ========== Register definition for DAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DAC_CTRLA (0x42004800) /**< \brief (DAC) Control A */ +#define REG_DAC_CTRLB (0x42004801) /**< \brief (DAC) Control B */ +#define REG_DAC_EVCTRL (0x42004802) /**< \brief (DAC) Event Control */ +#define REG_DAC_INTENCLR (0x42004804) /**< \brief (DAC) Interrupt Enable Clear */ +#define REG_DAC_INTENSET (0x42004805) /**< \brief (DAC) Interrupt Enable Set */ +#define REG_DAC_INTFLAG (0x42004806) /**< \brief (DAC) Interrupt Flag Status and Clear */ +#define REG_DAC_STATUS (0x42004807) /**< \brief (DAC) Status */ +#define REG_DAC_DATA (0x42004808) /**< \brief (DAC) Data */ +#define REG_DAC_DATABUF (0x4200480C) /**< \brief (DAC) Data Buffer */ +#else +#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800UL) /**< \brief (DAC) Control A */ +#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801UL) /**< \brief (DAC) Control B */ +#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802UL) /**< \brief (DAC) Event Control */ +#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804UL) /**< \brief (DAC) Interrupt Enable Clear */ +#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805UL) /**< \brief (DAC) Interrupt Enable Set */ +#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806UL) /**< \brief (DAC) Interrupt Flag Status and Clear */ +#define REG_DAC_STATUS (*(RoReg8 *)0x42004807UL) /**< \brief (DAC) Status */ +#define REG_DAC_DATA (*(RwReg16*)0x42004808UL) /**< \brief (DAC) Data */ +#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CUL) /**< \brief (DAC) Data Buffer */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DAC peripheral ========== */ +#define DAC_DMAC_ID_EMPTY 40 // Index of DMAC EMPTY trigger +#define DAC_GCLK_ID 33 // Index of Generic Clock + +#endif /* _SAMD21_DAC_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/dmac.h b/atmel-samd/asf4/samd21/include/instance/dmac.h new file mode 100644 index 000000000..bd71ed85a --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/dmac.h @@ -0,0 +1,94 @@ +/** + * \file + * + * \brief Instance description for DMAC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_DMAC_INSTANCE_ +#define _SAMD21_DMAC_INSTANCE_ + +/* ========== Register definition for DMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC_CTRL (0x41004800) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (0x41004802) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (0x41004804) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (0x41004808) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (0x4100480C) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (0x4100480D) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_QOSCTRL (0x4100480E) /**< \brief (DMAC) QOS Control */ +#define REG_DMAC_SWTRIGCTRL (0x41004810) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (0x41004814) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (0x41004820) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (0x41004824) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (0x41004828) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (0x4100482C) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (0x41004830) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (0x41004834) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (0x41004838) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (0x4100483F) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (0x41004840) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (0x41004844) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (0x4100484C) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (0x4100484D) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (0x4100484E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (0x4100484F) /**< \brief (DMAC) Channel Status */ +#else +#define REG_DMAC_CTRL (*(RwReg16*)0x41004800UL) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802UL) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804UL) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808UL) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CUL) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DUL) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EUL) /**< \brief (DMAC) QOS Control */ +#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810UL) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814UL) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820UL) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824UL) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828UL) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CUL) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830UL) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FUL) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840UL) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844UL) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FUL) /**< \brief (DMAC) Channel Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DMAC peripheral ========== */ +#define DMAC_CH_BITS 4 // Number of bits to select channel +#define DMAC_CH_NUM 12 // Number of channels +#define DMAC_CLK_AHB_ID 5 // AHB clock index +#define DMAC_EVIN_NUM 4 // Number of input events +#define DMAC_EVOUT_NUM 4 // Number of output events +#define DMAC_LVL_BITS 2 // Number of bit to select level priority +#define DMAC_LVL_NUM 4 // Enable priority level number +#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source +#define DMAC_TRIG_NUM 45 // Number of peripheral triggers + +#endif /* _SAMD21_DMAC_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/dsu.h b/atmel-samd/asf4/samd21/include/instance/dsu.h new file mode 100644 index 000000000..3db525a28 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/dsu.h @@ -0,0 +1,84 @@ +/** + * \file + * + * \brief Instance description for DSU + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_DSU_INSTANCE_ +#define _SAMD21_DSU_INSTANCE_ + +/* ========== Register definition for DSU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */ +#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) Coresight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) Coresight ROM Table Entry 1 */ +#define REG_DSU_END (0x41003008) /**< \brief (DSU) Coresight ROM Table End */ +#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) Coresight ROM Table Memory Type */ +#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */ +#else +#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */ +#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) Coresight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) Coresight ROM Table Entry 1 */ +#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) Coresight ROM Table End */ +#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) Coresight ROM Table Memory Type */ +#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DSU peripheral ========== */ +#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register + +#endif /* _SAMD21_DSU_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/eic.h b/atmel-samd/asf4/samd21/include/instance/eic.h new file mode 100644 index 000000000..55e761ce1 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/eic.h @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief Instance description for EIC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_EIC_INSTANCE_ +#define _SAMD21_EIC_INSTANCE_ + +/* ========== Register definition for EIC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EIC_CTRL (0x40001800) /**< \brief (EIC) Control */ +#define REG_EIC_STATUS (0x40001801) /**< \brief (EIC) Status */ +#define REG_EIC_NMICTRL (0x40001802) /**< \brief (EIC) Non-Maskable Interrupt Control */ +#define REG_EIC_NMIFLAG (0x40001803) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ +#define REG_EIC_EVCTRL (0x40001804) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (0x40001808) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (0x4000180C) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (0x40001810) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_WAKEUP (0x40001814) /**< \brief (EIC) Wake-Up Enable */ +#define REG_EIC_CONFIG0 (0x40001818) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (0x4000181C) /**< \brief (EIC) Configuration 1 */ +#else +#define REG_EIC_CTRL (*(RwReg8 *)0x40001800UL) /**< \brief (EIC) Control */ +#define REG_EIC_STATUS (*(RoReg8 *)0x40001801UL) /**< \brief (EIC) Status */ +#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802UL) /**< \brief (EIC) Non-Maskable Interrupt Control */ +#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ +#define REG_EIC_EVCTRL (*(RwReg *)0x40001804UL) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (*(RwReg *)0x40001808UL) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (*(RwReg *)0x4000180CUL) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (*(RwReg *)0x40001810UL) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_WAKEUP (*(RwReg *)0x40001814UL) /**< \brief (EIC) Wake-Up Enable */ +#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818UL) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CUL) /**< \brief (EIC) Configuration 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EIC peripheral ========== */ +#define EIC_CONFIG_NUM 2 // Number of CONFIG registers +#define EIC_GCLK_ID 5 // Index of Generic Clock + +#endif /* _SAMD21_EIC_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/evsys.h b/atmel-samd/asf4/samd21/include/instance/evsys.h new file mode 100644 index 000000000..e6256acf6 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/evsys.h @@ -0,0 +1,179 @@ +/** + * \file + * + * \brief Instance description for EVSYS + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_EVSYS_INSTANCE_ +#define _SAMD21_EVSYS_INSTANCE_ + +/* ========== Register definition for EVSYS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EVSYS_CTRL (0x42000400) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHANNEL (0x42000404) /**< \brief (EVSYS) Channel */ +#define REG_EVSYS_USER (0x42000408) /**< \brief (EVSYS) User Multiplexer */ +#define REG_EVSYS_CHSTATUS (0x4200040C) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (0x42000410) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (0x42000414) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (0x42000418) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#else +#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400UL) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404UL) /**< \brief (EVSYS) Channel */ +#define REG_EVSYS_USER (*(RwReg16*)0x42000408UL) /**< \brief (EVSYS) User Multiplexer */ +#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CUL) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410UL) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414UL) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EVSYS peripheral ========== */ +#define EVSYS_CHANNELS 12 // Number of Channels +#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel +#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1 +#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators +#define EVSYS_GCLK_ID_0 7 +#define EVSYS_GCLK_ID_1 8 +#define EVSYS_GCLK_ID_2 9 +#define EVSYS_GCLK_ID_3 10 +#define EVSYS_GCLK_ID_4 11 +#define EVSYS_GCLK_ID_5 12 +#define EVSYS_GCLK_ID_6 13 +#define EVSYS_GCLK_ID_7 14 +#define EVSYS_GCLK_ID_8 15 +#define EVSYS_GCLK_ID_9 16 +#define EVSYS_GCLK_ID_10 17 +#define EVSYS_GCLK_ID_11 18 +#define EVSYS_GCLK_ID_LSB 7 +#define EVSYS_GCLK_ID_MSB 18 +#define EVSYS_GCLK_ID_SIZE 12 +#define EVSYS_GENERATORS 73 // Total Number of Event Generators +#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator +#define EVSYS_USERS 29 // Total Number of Event Users +#define EVSYS_USERS_BITS 5 // Number of bits to select Event User + +// GENERATORS +#define EVSYS_ID_GEN_RTC_CMP_0 1 +#define EVSYS_ID_GEN_RTC_CMP_1 2 +#define EVSYS_ID_GEN_RTC_OVF 3 +#define EVSYS_ID_GEN_RTC_PER_0 4 +#define EVSYS_ID_GEN_RTC_PER_1 5 +#define EVSYS_ID_GEN_RTC_PER_2 6 +#define EVSYS_ID_GEN_RTC_PER_3 7 +#define EVSYS_ID_GEN_RTC_PER_4 8 +#define EVSYS_ID_GEN_RTC_PER_5 9 +#define EVSYS_ID_GEN_RTC_PER_6 10 +#define EVSYS_ID_GEN_RTC_PER_7 11 +#define EVSYS_ID_GEN_EIC_EXTINT_0 12 +#define EVSYS_ID_GEN_EIC_EXTINT_1 13 +#define EVSYS_ID_GEN_EIC_EXTINT_2 14 +#define EVSYS_ID_GEN_EIC_EXTINT_3 15 +#define EVSYS_ID_GEN_EIC_EXTINT_4 16 +#define EVSYS_ID_GEN_EIC_EXTINT_5 17 +#define EVSYS_ID_GEN_EIC_EXTINT_6 18 +#define EVSYS_ID_GEN_EIC_EXTINT_7 19 +#define EVSYS_ID_GEN_EIC_EXTINT_8 20 +#define EVSYS_ID_GEN_EIC_EXTINT_9 21 +#define EVSYS_ID_GEN_EIC_EXTINT_10 22 +#define EVSYS_ID_GEN_EIC_EXTINT_11 23 +#define EVSYS_ID_GEN_EIC_EXTINT_12 24 +#define EVSYS_ID_GEN_EIC_EXTINT_13 25 +#define EVSYS_ID_GEN_EIC_EXTINT_14 26 +#define EVSYS_ID_GEN_EIC_EXTINT_15 27 +#define EVSYS_ID_GEN_EIC_EXTINT_16 28 +#define EVSYS_ID_GEN_EIC_EXTINT_17 29 +#define EVSYS_ID_GEN_DMAC_CH_0 30 +#define EVSYS_ID_GEN_DMAC_CH_1 31 +#define EVSYS_ID_GEN_DMAC_CH_2 32 +#define EVSYS_ID_GEN_DMAC_CH_3 33 +#define EVSYS_ID_GEN_TCC0_OVF 34 +#define EVSYS_ID_GEN_TCC0_TRG 35 +#define EVSYS_ID_GEN_TCC0_CNT 36 +#define EVSYS_ID_GEN_TCC0_MCX_0 37 +#define EVSYS_ID_GEN_TCC0_MCX_1 38 +#define EVSYS_ID_GEN_TCC0_MCX_2 39 +#define EVSYS_ID_GEN_TCC0_MCX_3 40 +#define EVSYS_ID_GEN_TCC1_OVF 41 +#define EVSYS_ID_GEN_TCC1_TRG 42 +#define EVSYS_ID_GEN_TCC1_CNT 43 +#define EVSYS_ID_GEN_TCC1_MCX_0 44 +#define EVSYS_ID_GEN_TCC1_MCX_1 45 +#define EVSYS_ID_GEN_TCC2_OVF 46 +#define EVSYS_ID_GEN_TCC2_TRG 47 +#define EVSYS_ID_GEN_TCC2_CNT 48 +#define EVSYS_ID_GEN_TCC2_MCX_0 49 +#define EVSYS_ID_GEN_TCC2_MCX_1 50 +#define EVSYS_ID_GEN_TC3_OVF 51 +#define EVSYS_ID_GEN_TC3_MCX_0 52 +#define EVSYS_ID_GEN_TC3_MCX_1 53 +#define EVSYS_ID_GEN_TC4_OVF 54 +#define EVSYS_ID_GEN_TC4_MCX_0 55 +#define EVSYS_ID_GEN_TC4_MCX_1 56 +#define EVSYS_ID_GEN_TC5_OVF 57 +#define EVSYS_ID_GEN_TC5_MCX_0 58 +#define EVSYS_ID_GEN_TC5_MCX_1 59 +#define EVSYS_ID_GEN_TC6_OVF 60 +#define EVSYS_ID_GEN_TC6_MCX_0 61 +#define EVSYS_ID_GEN_TC6_MCX_1 62 +#define EVSYS_ID_GEN_TC7_OVF 63 +#define EVSYS_ID_GEN_TC7_MCX_0 64 +#define EVSYS_ID_GEN_TC7_MCX_1 65 +#define EVSYS_ID_GEN_ADC_RESRDY 66 +#define EVSYS_ID_GEN_ADC_WINMON 67 +#define EVSYS_ID_GEN_AC_COMP_0 68 +#define EVSYS_ID_GEN_AC_COMP_1 69 +#define EVSYS_ID_GEN_AC_WIN_0 70 +#define EVSYS_ID_GEN_DAC_EMPTY 71 + +// USERS +#define EVSYS_ID_USER_DMAC_CH_0 0 +#define EVSYS_ID_USER_DMAC_CH_1 1 +#define EVSYS_ID_USER_DMAC_CH_2 2 +#define EVSYS_ID_USER_DMAC_CH_3 3 +#define EVSYS_ID_USER_TCC0_EV_0 4 +#define EVSYS_ID_USER_TCC0_EV_1 5 +#define EVSYS_ID_USER_TCC0_MC_0 6 +#define EVSYS_ID_USER_TCC0_MC_1 7 +#define EVSYS_ID_USER_TCC0_MC_2 8 +#define EVSYS_ID_USER_TCC0_MC_3 9 +#define EVSYS_ID_USER_TCC1_EV_0 10 +#define EVSYS_ID_USER_TCC1_EV_1 11 +#define EVSYS_ID_USER_TCC1_MC_0 12 +#define EVSYS_ID_USER_TCC1_MC_1 13 +#define EVSYS_ID_USER_TCC2_EV_0 14 +#define EVSYS_ID_USER_TCC2_EV_1 15 +#define EVSYS_ID_USER_TCC2_MC_0 16 +#define EVSYS_ID_USER_TCC2_MC_1 17 +#define EVSYS_ID_USER_TC3_EVU 18 +#define EVSYS_ID_USER_TC4_EVU 19 +#define EVSYS_ID_USER_TC5_EVU 20 +#define EVSYS_ID_USER_TC6_EVU 21 +#define EVSYS_ID_USER_TC7_EVU 22 +#define EVSYS_ID_USER_ADC_START 23 +#define EVSYS_ID_USER_ADC_SYNC 24 +#define EVSYS_ID_USER_AC_SOC_0 25 +#define EVSYS_ID_USER_AC_SOC_1 26 +#define EVSYS_ID_USER_DAC_START 27 + +#endif /* _SAMD21_EVSYS_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/gclk.h b/atmel-samd/asf4/samd21/include/instance/gclk.h new file mode 100644 index 000000000..e75ad3b55 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/gclk.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Instance description for GCLK + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_GCLK_INSTANCE_ +#define _SAMD21_GCLK_INSTANCE_ + +/* ========== Register definition for GCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GCLK_CTRL (0x40000C00) /**< \brief (GCLK) Control */ +#define REG_GCLK_STATUS (0x40000C01) /**< \brief (GCLK) Status */ +#define REG_GCLK_CLKCTRL (0x40000C02) /**< \brief (GCLK) Generic Clock Control */ +#define REG_GCLK_GENCTRL (0x40000C04) /**< \brief (GCLK) Generic Clock Generator Control */ +#define REG_GCLK_GENDIV (0x40000C08) /**< \brief (GCLK) Generic Clock Generator Division */ +#else +#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00UL) /**< \brief (GCLK) Control */ +#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01UL) /**< \brief (GCLK) Status */ +#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02UL) /**< \brief (GCLK) Generic Clock Control */ +#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04UL) /**< \brief (GCLK) Generic Clock Generator Control */ +#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08UL) /**< \brief (GCLK) Generic Clock Generator Division */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for GCLK peripheral ========== */ +#define GCLK_GENDIV_BITS 16 +#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators +#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 +#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 +#define GCLK_NUM 37 // Number of Generic Clock Users +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_FDPLL 8 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC8M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 + +#endif /* _SAMD21_GCLK_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/i2s.h b/atmel-samd/asf4/samd21/include/instance/i2s.h new file mode 100644 index 000000000..4df326ee7 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/i2s.h @@ -0,0 +1,79 @@ +/** + * \file + * + * \brief Instance description for I2S + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_I2S_INSTANCE_ +#define _SAMD21_I2S_INSTANCE_ + +/* ========== Register definition for I2S peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_I2S_CTRLA (0x42005000) /**< \brief (I2S) Control A */ +#define REG_I2S_CLKCTRL0 (0x42005004) /**< \brief (I2S) Clock Unit 0 Control */ +#define REG_I2S_CLKCTRL1 (0x42005008) /**< \brief (I2S) Clock Unit 1 Control */ +#define REG_I2S_INTENCLR (0x4200500C) /**< \brief (I2S) Interrupt Enable Clear */ +#define REG_I2S_INTENSET (0x42005010) /**< \brief (I2S) Interrupt Enable Set */ +#define REG_I2S_INTFLAG (0x42005014) /**< \brief (I2S) Interrupt Flag Status and Clear */ +#define REG_I2S_SYNCBUSY (0x42005018) /**< \brief (I2S) Synchronization Status */ +#define REG_I2S_SERCTRL0 (0x42005020) /**< \brief (I2S) Serializer 0 Control */ +#define REG_I2S_SERCTRL1 (0x42005024) /**< \brief (I2S) Serializer 1 Control */ +#define REG_I2S_DATA0 (0x42005030) /**< \brief (I2S) Data 0 */ +#define REG_I2S_DATA1 (0x42005034) /**< \brief (I2S) Data 1 */ +#else +#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000UL) /**< \brief (I2S) Control A */ +#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004UL) /**< \brief (I2S) Clock Unit 0 Control */ +#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008UL) /**< \brief (I2S) Clock Unit 1 Control */ +#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CUL) /**< \brief (I2S) Interrupt Enable Clear */ +#define REG_I2S_INTENSET (*(RwReg16*)0x42005010UL) /**< \brief (I2S) Interrupt Enable Set */ +#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014UL) /**< \brief (I2S) Interrupt Flag Status and Clear */ +#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018UL) /**< \brief (I2S) Synchronization Status */ +#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020UL) /**< \brief (I2S) Serializer 0 Control */ +#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024UL) /**< \brief (I2S) Serializer 1 Control */ +#define REG_I2S_DATA0 (*(RwReg *)0x42005030UL) /**< \brief (I2S) Data 0 */ +#define REG_I2S_DATA1 (*(RwReg *)0x42005034UL) /**< \brief (I2S) Data 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for I2S peripheral ========== */ +#define I2S_CLK_NUM 2 // Number of clock units +#define I2S_DMAC_ID_RX_0 41 +#define I2S_DMAC_ID_RX_1 42 +#define I2S_DMAC_ID_RX_LSB 41 +#define I2S_DMAC_ID_RX_MSB 42 +#define I2S_DMAC_ID_RX_SIZE 2 +#define I2S_DMAC_ID_TX_0 43 +#define I2S_DMAC_ID_TX_1 44 +#define I2S_DMAC_ID_TX_LSB 43 +#define I2S_DMAC_ID_TX_MSB 44 +#define I2S_DMAC_ID_TX_SIZE 2 +#define I2S_GCLK_ID_0 35 +#define I2S_GCLK_ID_1 36 +#define I2S_GCLK_ID_LSB 35 +#define I2S_GCLK_ID_MSB 36 +#define I2S_GCLK_ID_SIZE 2 +#define I2S_MAX_SLOTS 8 // Max number of data slots in frame +#define I2S_SER_NUM 2 // Number of serializers + +#endif /* _SAMD21_I2S_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/mtb.h b/atmel-samd/asf4/samd21/include/instance/mtb.h new file mode 100644 index 000000000..76b047f2f --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/mtb.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Instance description for MTB + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_MTB_INSTANCE_ +#define _SAMD21_MTB_INSTANCE_ + +/* ========== Register definition for MTB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MTB_POSITION (0x41006000) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (0x41006004) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (0x41006008) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (0x4100600C) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (0x41006F00) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (0x41006FA0) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (0x41006FA4) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (0x41006FB0) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (0x41006FB4) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (0x41006FB8) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (0x41006FBC) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (0x41006FC8) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (0x41006FCC) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (0x41006FD0) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID5 (0x41006FD4) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID6 (0x41006FD8) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID7 (0x41006FDC) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID0 (0x41006FE0) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID1 (0x41006FE4) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID2 (0x41006FE8) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID3 (0x41006FEC) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID0 (0x41006FF0) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID1 (0x41006FF4) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID2 (0x41006FF8) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID3 (0x41006FFC) /**< \brief (MTB) CoreSight */ +#else +#define REG_MTB_POSITION (*(RwReg *)0x41006000UL) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (*(RwReg *)0x41006004UL) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (*(RwReg *)0x41006008UL) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (*(RoReg *)0x4100600CUL) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00UL) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0UL) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4UL) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0UL) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4UL) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8UL) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCUL) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (*(RoReg *)0x41006FC8UL) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCUL) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (*(RoReg *)0x41006FD0UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID5 (*(RoReg *)0x41006FD4UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID6 (*(RoReg *)0x41006FD8UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID7 (*(RoReg *)0x41006FDCUL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID0 (*(RoReg *)0x41006FE0UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID1 (*(RoReg *)0x41006FE4UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID2 (*(RoReg *)0x41006FE8UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID3 (*(RoReg *)0x41006FECUL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID0 (*(RoReg *)0x41006FF0UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID1 (*(RoReg *)0x41006FF4UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID2 (*(RoReg *)0x41006FF8UL) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID3 (*(RoReg *)0x41006FFCUL) /**< \brief (MTB) CoreSight */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAMD21_MTB_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/nvmctrl.h b/atmel-samd/asf4/samd21/include/instance/nvmctrl.h new file mode 100644 index 000000000..7636f034e --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/nvmctrl.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Instance description for NVMCTRL + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_NVMCTRL_INSTANCE_ +#define _SAMD21_NVMCTRL_INSTANCE_ + +/* ========== Register definition for NVMCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */ +#else +#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for NVMCTRL peripheral ========== */ +#define NVMCTRL_AUX0_ADDRESS 0x00804000 +#define NVMCTRL_AUX1_ADDRESS 0x00806000 +#define NVMCTRL_AUX2_ADDRESS 0x00808000 +#define NVMCTRL_AUX3_ADDRESS 0x0080A000 +#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register +#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF +#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 +#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 +#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 +#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF + +#endif /* _SAMD21_NVMCTRL_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/pac0.h b/atmel-samd/asf4/samd21/include/instance/pac0.h new file mode 100644 index 000000000..fe59d372f --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/pac0.h @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Instance description for PAC0 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_PAC0_INSTANCE_ +#define _SAMD21_PAC0_INSTANCE_ + +/* ========== Register definition for PAC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC0_WPCLR (0x40000000) /**< \brief (PAC0) Write Protection Clear */ +#define REG_PAC0_WPSET (0x40000004) /**< \brief (PAC0) Write Protection Set */ +#else +#define REG_PAC0_WPCLR (*(RwReg *)0x40000000UL) /**< \brief (PAC0) Write Protection Clear */ +#define REG_PAC0_WPSET (*(RwReg *)0x40000004UL) /**< \brief (PAC0) Write Protection Set */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC0 peripheral ========== */ +#define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset + +#endif /* _SAMD21_PAC0_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/pac1.h b/atmel-samd/asf4/samd21/include/instance/pac1.h new file mode 100644 index 000000000..ad4e78159 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/pac1.h @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Instance description for PAC1 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_PAC1_INSTANCE_ +#define _SAMD21_PAC1_INSTANCE_ + +/* ========== Register definition for PAC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC1_WPCLR (0x41000000) /**< \brief (PAC1) Write Protection Clear */ +#define REG_PAC1_WPSET (0x41000004) /**< \brief (PAC1) Write Protection Set */ +#else +#define REG_PAC1_WPCLR (*(RwReg *)0x41000000UL) /**< \brief (PAC1) Write Protection Clear */ +#define REG_PAC1_WPSET (*(RwReg *)0x41000004UL) /**< \brief (PAC1) Write Protection Set */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC1 peripheral ========== */ +#define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset + +#endif /* _SAMD21_PAC1_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/pac2.h b/atmel-samd/asf4/samd21/include/instance/pac2.h new file mode 100644 index 000000000..8f2bd50fa --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/pac2.h @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Instance description for PAC2 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_PAC2_INSTANCE_ +#define _SAMD21_PAC2_INSTANCE_ + +/* ========== Register definition for PAC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC2_WPCLR (0x42000000) /**< \brief (PAC2) Write Protection Clear */ +#define REG_PAC2_WPSET (0x42000004) /**< \brief (PAC2) Write Protection Set */ +#else +#define REG_PAC2_WPCLR (*(RwReg *)0x42000000UL) /**< \brief (PAC2) Write Protection Clear */ +#define REG_PAC2_WPSET (*(RwReg *)0x42000004UL) /**< \brief (PAC2) Write Protection Set */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC2 peripheral ========== */ +#define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset + +#endif /* _SAMD21_PAC2_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/pm.h b/atmel-samd/asf4/samd21/include/instance/pm.h new file mode 100644 index 000000000..feca8a6f6 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/pm.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief Instance description for PM + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_PM_INSTANCE_ +#define _SAMD21_PM_INSTANCE_ + +/* ========== Register definition for PM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PM_CTRL (0x40000400) /**< \brief (PM) Control */ +#define REG_PM_SLEEP (0x40000401) /**< \brief (PM) Sleep Mode */ +#define REG_PM_CPUSEL (0x40000408) /**< \brief (PM) CPU Clock Select */ +#define REG_PM_APBASEL (0x40000409) /**< \brief (PM) APBA Clock Select */ +#define REG_PM_APBBSEL (0x4000040A) /**< \brief (PM) APBB Clock Select */ +#define REG_PM_APBCSEL (0x4000040B) /**< \brief (PM) APBC Clock Select */ +#define REG_PM_AHBMASK (0x40000414) /**< \brief (PM) AHB Mask */ +#define REG_PM_APBAMASK (0x40000418) /**< \brief (PM) APBA Mask */ +#define REG_PM_APBBMASK (0x4000041C) /**< \brief (PM) APBB Mask */ +#define REG_PM_APBCMASK (0x40000420) /**< \brief (PM) APBC Mask */ +#define REG_PM_INTENCLR (0x40000434) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (0x40000435) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (0x40000436) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_RCAUSE (0x40000438) /**< \brief (PM) Reset Cause */ +#else +#define REG_PM_CTRL (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control */ +#define REG_PM_SLEEP (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Mode */ +#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408UL) /**< \brief (PM) CPU Clock Select */ +#define REG_PM_APBASEL (*(RwReg8 *)0x40000409UL) /**< \brief (PM) APBA Clock Select */ +#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) APBB Clock Select */ +#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BUL) /**< \brief (PM) APBC Clock Select */ +#define REG_PM_AHBMASK (*(RwReg *)0x40000414UL) /**< \brief (PM) AHB Mask */ +#define REG_PM_APBAMASK (*(RwReg *)0x40000418UL) /**< \brief (PM) APBA Mask */ +#define REG_PM_APBBMASK (*(RwReg *)0x4000041CUL) /**< \brief (PM) APBB Mask */ +#define REG_PM_APBCMASK (*(RwReg *)0x40000420UL) /**< \brief (PM) APBC Mask */ +#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434UL) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (*(RwReg8 *)0x40000435UL) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436UL) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438UL) /**< \brief (PM) Reset Cause */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PM peripheral ========== */ +#define PM_CTRL_MCSEL_DFLL48M 3 +#define PM_CTRL_MCSEL_GCLK 0 +#define PM_CTRL_MCSEL_OSC8M 1 +#define PM_CTRL_MCSEL_XOSC 2 +#define PM_PM_CLK_APB_NUM 2 + +#endif /* _SAMD21_PM_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/port.h b/atmel-samd/asf4/samd21/include/instance/port.h new file mode 100644 index 000000000..ab9c40bfd --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/port.h @@ -0,0 +1,121 @@ +/** + * \file + * + * \brief Instance description for PORT + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_PORT_INSTANCE_ +#define _SAMD21_PORT_INSTANCE_ + +/* ========== Register definition for PORT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PORT_DIR0 (0x41004400) /**< \brief (PORT) Data Direction 0 */ +#define REG_PORT_DIRCLR0 (0x41004404) /**< \brief (PORT) Data Direction Clear 0 */ +#define REG_PORT_DIRSET0 (0x41004408) /**< \brief (PORT) Data Direction Set 0 */ +#define REG_PORT_DIRTGL0 (0x4100440C) /**< \brief (PORT) Data Direction Toggle 0 */ +#define REG_PORT_OUT0 (0x41004410) /**< \brief (PORT) Data Output Value 0 */ +#define REG_PORT_OUTCLR0 (0x41004414) /**< \brief (PORT) Data Output Value Clear 0 */ +#define REG_PORT_OUTSET0 (0x41004418) /**< \brief (PORT) Data Output Value Set 0 */ +#define REG_PORT_OUTTGL0 (0x4100441C) /**< \brief (PORT) Data Output Value Toggle 0 */ +#define REG_PORT_IN0 (0x41004420) /**< \brief (PORT) Data Input Value 0 */ +#define REG_PORT_CTRL0 (0x41004424) /**< \brief (PORT) Control 0 */ +#define REG_PORT_WRCONFIG0 (0x41004428) /**< \brief (PORT) Write Configuration 0 */ +#define REG_PORT_PMUX0 (0x41004430) /**< \brief (PORT) Peripheral Multiplexing 0 */ +#define REG_PORT_PINCFG0 (0x41004440) /**< \brief (PORT) Pin Configuration 0 */ +#define REG_PORT_DIR1 (0x41004480) /**< \brief (PORT) Data Direction 1 */ +#define REG_PORT_DIRCLR1 (0x41004484) /**< \brief (PORT) Data Direction Clear 1 */ +#define REG_PORT_DIRSET1 (0x41004488) /**< \brief (PORT) Data Direction Set 1 */ +#define REG_PORT_DIRTGL1 (0x4100448C) /**< \brief (PORT) Data Direction Toggle 1 */ +#define REG_PORT_OUT1 (0x41004490) /**< \brief (PORT) Data Output Value 1 */ +#define REG_PORT_OUTCLR1 (0x41004494) /**< \brief (PORT) Data Output Value Clear 1 */ +#define REG_PORT_OUTSET1 (0x41004498) /**< \brief (PORT) Data Output Value Set 1 */ +#define REG_PORT_OUTTGL1 (0x4100449C) /**< \brief (PORT) Data Output Value Toggle 1 */ +#define REG_PORT_IN1 (0x410044A0) /**< \brief (PORT) Data Input Value 1 */ +#define REG_PORT_CTRL1 (0x410044A4) /**< \brief (PORT) Control 1 */ +#define REG_PORT_WRCONFIG1 (0x410044A8) /**< \brief (PORT) Write Configuration 1 */ +#define REG_PORT_PMUX1 (0x410044B0) /**< \brief (PORT) Peripheral Multiplexing 1 */ +#define REG_PORT_PINCFG1 (0x410044C0) /**< \brief (PORT) Pin Configuration 1 */ +#else +#define REG_PORT_DIR0 (*(RwReg *)0x41004400UL) /**< \brief (PORT) Data Direction 0 */ +#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404UL) /**< \brief (PORT) Data Direction Clear 0 */ +#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408UL) /**< \brief (PORT) Data Direction Set 0 */ +#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CUL) /**< \brief (PORT) Data Direction Toggle 0 */ +#define REG_PORT_OUT0 (*(RwReg *)0x41004410UL) /**< \brief (PORT) Data Output Value 0 */ +#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414UL) /**< \brief (PORT) Data Output Value Clear 0 */ +#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418UL) /**< \brief (PORT) Data Output Value Set 0 */ +#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CUL) /**< \brief (PORT) Data Output Value Toggle 0 */ +#define REG_PORT_IN0 (*(RoReg *)0x41004420UL) /**< \brief (PORT) Data Input Value 0 */ +#define REG_PORT_CTRL0 (*(RwReg *)0x41004424UL) /**< \brief (PORT) Control 0 */ +#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428UL) /**< \brief (PORT) Write Configuration 0 */ +#define REG_PORT_PMUX0 (*(RwReg *)0x41004430UL) /**< \brief (PORT) Peripheral Multiplexing 0 */ +#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440UL) /**< \brief (PORT) Pin Configuration 0 */ +#define REG_PORT_DIR1 (*(RwReg *)0x41004480UL) /**< \brief (PORT) Data Direction 1 */ +#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484UL) /**< \brief (PORT) Data Direction Clear 1 */ +#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488UL) /**< \brief (PORT) Data Direction Set 1 */ +#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CUL) /**< \brief (PORT) Data Direction Toggle 1 */ +#define REG_PORT_OUT1 (*(RwReg *)0x41004490UL) /**< \brief (PORT) Data Output Value 1 */ +#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494UL) /**< \brief (PORT) Data Output Value Clear 1 */ +#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498UL) /**< \brief (PORT) Data Output Value Set 1 */ +#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CUL) /**< \brief (PORT) Data Output Value Toggle 1 */ +#define REG_PORT_IN1 (*(RoReg *)0x410044A0UL) /**< \brief (PORT) Data Input Value 1 */ +#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4UL) /**< \brief (PORT) Control 1 */ +#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8UL) /**< \brief (PORT) Write Configuration 1 */ +#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */ +#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0UL) /**< \brief (PORT) Pin Configuration 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PORT peripheral ========== */ +#define PORT_BITS 84 // Number of PORT pins +#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins +#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins +#define PORT_DRVSTR 1 // DRVSTR supported +#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins +#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins +#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins +#define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins +#define PORT_ODRAIN 0 // ODRAIN supported +#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins +#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins +#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins +#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins +#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins +#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins +#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins +#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins +#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins +#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins +#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins +#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins +#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins +#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins +#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins +#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins +#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins +#define PORT_SLEWLIM 0 // SLEWLIM supported +#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins +#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins + +#endif /* _SAMD21_PORT_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/rtc.h b/atmel-samd/asf4/samd21/include/instance/rtc.h new file mode 100644 index 000000000..7a974e5e3 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/rtc.h @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief Instance description for RTC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_RTC_INSTANCE_ +#define _SAMD21_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_READREQ (0x40001402) /**< \brief (RTC) Read Request */ +#define REG_RTC_STATUS (0x4000140A) /**< \brief (RTC) Status */ +#define REG_RTC_DBGCTRL (0x4000140B) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (0x4000140C) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_MODE0_CTRL (0x40001400) /**< \brief (RTC) MODE0 Control */ +#define REG_RTC_MODE0_EVCTRL (0x40001404) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (0x40001406) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (0x40001407) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (0x40001408) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_COUNT (0x40001410) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (0x40001418) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE1_CTRL (0x40001400) /**< \brief (RTC) MODE1 Control */ +#define REG_RTC_MODE1_EVCTRL (0x40001404) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (0x40001406) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (0x40001407) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (0x40001408) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_COUNT (0x40001410) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (0x40001414) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (0x40001418) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (0x4000141A) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE2_CTRL (0x40001400) /**< \brief (RTC) MODE2 Control */ +#define REG_RTC_MODE2_EVCTRL (0x40001404) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (0x40001406) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (0x40001407) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (0x40001408) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_CLOCK (0x40001410) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141C) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#else +#define REG_RTC_READREQ (*(RwReg16*)0x40001402UL) /**< \brief (RTC) Read Request */ +#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AUL) /**< \brief (RTC) Status */ +#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BUL) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CUL) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE0 Control */ +#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE1 Control */ +#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410UL) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414UL) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418UL) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AUL) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE2 Control */ +#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CUL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RTC peripheral ========== */ +#define RTC_ALARM_NUM 1 // Number of Alarms +#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators +#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators +#define RTC_GCLK_ID 4 // Index of Generic Clock +#define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete) +#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete) +#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete) + +#endif /* _SAMD21_RTC_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/sbmatrix.h b/atmel-samd/asf4/samd21/include/instance/sbmatrix.h new file mode 100644 index 000000000..bdc4651a1 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/sbmatrix.h @@ -0,0 +1,150 @@ +/** + * \file + * + * \brief Instance description for SBMATRIX + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_SBMATRIX_INSTANCE_ +#define _SAMD21_SBMATRIX_INSTANCE_ + +/* ========== Register definition for SBMATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SBMATRIX_PRAS0 (0x41007080) /**< \brief (SBMATRIX) Priority A for Slave 0 */ +#define REG_SBMATRIX_PRBS0 (0x41007084) /**< \brief (SBMATRIX) Priority B for Slave 0 */ +#define REG_SBMATRIX_PRAS1 (0x41007088) /**< \brief (SBMATRIX) Priority A for Slave 1 */ +#define REG_SBMATRIX_PRBS1 (0x4100708C) /**< \brief (SBMATRIX) Priority B for Slave 1 */ +#define REG_SBMATRIX_PRAS2 (0x41007090) /**< \brief (SBMATRIX) Priority A for Slave 2 */ +#define REG_SBMATRIX_PRBS2 (0x41007094) /**< \brief (SBMATRIX) Priority B for Slave 2 */ +#define REG_SBMATRIX_PRAS3 (0x41007098) /**< \brief (SBMATRIX) Priority A for Slave 3 */ +#define REG_SBMATRIX_PRBS3 (0x4100709C) /**< \brief (SBMATRIX) Priority B for Slave 3 */ +#define REG_SBMATRIX_PRAS4 (0x410070A0) /**< \brief (SBMATRIX) Priority A for Slave 4 */ +#define REG_SBMATRIX_PRBS4 (0x410070A4) /**< \brief (SBMATRIX) Priority B for Slave 4 */ +#define REG_SBMATRIX_PRAS5 (0x410070A8) /**< \brief (SBMATRIX) Priority A for Slave 5 */ +#define REG_SBMATRIX_PRBS5 (0x410070AC) /**< \brief (SBMATRIX) Priority B for Slave 5 */ +#define REG_SBMATRIX_PRAS6 (0x410070B0) /**< \brief (SBMATRIX) Priority A for Slave 6 */ +#define REG_SBMATRIX_PRBS6 (0x410070B4) /**< \brief (SBMATRIX) Priority B for Slave 6 */ +#define REG_SBMATRIX_PRAS7 (0x410070B8) /**< \brief (SBMATRIX) Priority A for Slave 7 */ +#define REG_SBMATRIX_PRBS7 (0x410070BC) /**< \brief (SBMATRIX) Priority B for Slave 7 */ +#define REG_SBMATRIX_PRAS8 (0x410070C0) /**< \brief (SBMATRIX) Priority A for Slave 8 */ +#define REG_SBMATRIX_PRBS8 (0x410070C4) /**< \brief (SBMATRIX) Priority B for Slave 8 */ +#define REG_SBMATRIX_PRAS9 (0x410070C8) /**< \brief (SBMATRIX) Priority A for Slave 9 */ +#define REG_SBMATRIX_PRBS9 (0x410070CC) /**< \brief (SBMATRIX) Priority B for Slave 9 */ +#define REG_SBMATRIX_PRAS10 (0x410070D0) /**< \brief (SBMATRIX) Priority A for Slave 10 */ +#define REG_SBMATRIX_PRBS10 (0x410070D4) /**< \brief (SBMATRIX) Priority B for Slave 10 */ +#define REG_SBMATRIX_PRAS11 (0x410070D8) /**< \brief (SBMATRIX) Priority A for Slave 11 */ +#define REG_SBMATRIX_PRBS11 (0x410070DC) /**< \brief (SBMATRIX) Priority B for Slave 11 */ +#define REG_SBMATRIX_PRAS12 (0x410070E0) /**< \brief (SBMATRIX) Priority A for Slave 12 */ +#define REG_SBMATRIX_PRBS12 (0x410070E4) /**< \brief (SBMATRIX) Priority B for Slave 12 */ +#define REG_SBMATRIX_PRAS13 (0x410070E8) /**< \brief (SBMATRIX) Priority A for Slave 13 */ +#define REG_SBMATRIX_PRBS13 (0x410070EC) /**< \brief (SBMATRIX) Priority B for Slave 13 */ +#define REG_SBMATRIX_PRAS14 (0x410070F0) /**< \brief (SBMATRIX) Priority A for Slave 14 */ +#define REG_SBMATRIX_PRBS14 (0x410070F4) /**< \brief (SBMATRIX) Priority B for Slave 14 */ +#define REG_SBMATRIX_PRAS15 (0x410070F8) /**< \brief (SBMATRIX) Priority A for Slave 15 */ +#define REG_SBMATRIX_PRBS15 (0x410070FC) /**< \brief (SBMATRIX) Priority B for Slave 15 */ +#define REG_SBMATRIX_SFR0 (0x41007110) /**< \brief (SBMATRIX) Special Function 0 */ +#define REG_SBMATRIX_SFR1 (0x41007114) /**< \brief (SBMATRIX) Special Function 1 */ +#define REG_SBMATRIX_SFR2 (0x41007118) /**< \brief (SBMATRIX) Special Function 2 */ +#define REG_SBMATRIX_SFR3 (0x4100711C) /**< \brief (SBMATRIX) Special Function 3 */ +#define REG_SBMATRIX_SFR4 (0x41007120) /**< \brief (SBMATRIX) Special Function 4 */ +#define REG_SBMATRIX_SFR5 (0x41007124) /**< \brief (SBMATRIX) Special Function 5 */ +#define REG_SBMATRIX_SFR6 (0x41007128) /**< \brief (SBMATRIX) Special Function 6 */ +#define REG_SBMATRIX_SFR7 (0x4100712C) /**< \brief (SBMATRIX) Special Function 7 */ +#define REG_SBMATRIX_SFR8 (0x41007130) /**< \brief (SBMATRIX) Special Function 8 */ +#define REG_SBMATRIX_SFR9 (0x41007134) /**< \brief (SBMATRIX) Special Function 9 */ +#define REG_SBMATRIX_SFR10 (0x41007138) /**< \brief (SBMATRIX) Special Function 10 */ +#define REG_SBMATRIX_SFR11 (0x4100713C) /**< \brief (SBMATRIX) Special Function 11 */ +#define REG_SBMATRIX_SFR12 (0x41007140) /**< \brief (SBMATRIX) Special Function 12 */ +#define REG_SBMATRIX_SFR13 (0x41007144) /**< \brief (SBMATRIX) Special Function 13 */ +#define REG_SBMATRIX_SFR14 (0x41007148) /**< \brief (SBMATRIX) Special Function 14 */ +#define REG_SBMATRIX_SFR15 (0x4100714C) /**< \brief (SBMATRIX) Special Function 15 */ +#else +#define REG_SBMATRIX_PRAS0 (*(RwReg *)0x41007080UL) /**< \brief (SBMATRIX) Priority A for Slave 0 */ +#define REG_SBMATRIX_PRBS0 (*(RwReg *)0x41007084UL) /**< \brief (SBMATRIX) Priority B for Slave 0 */ +#define REG_SBMATRIX_PRAS1 (*(RwReg *)0x41007088UL) /**< \brief (SBMATRIX) Priority A for Slave 1 */ +#define REG_SBMATRIX_PRBS1 (*(RwReg *)0x4100708CUL) /**< \brief (SBMATRIX) Priority B for Slave 1 */ +#define REG_SBMATRIX_PRAS2 (*(RwReg *)0x41007090UL) /**< \brief (SBMATRIX) Priority A for Slave 2 */ +#define REG_SBMATRIX_PRBS2 (*(RwReg *)0x41007094UL) /**< \brief (SBMATRIX) Priority B for Slave 2 */ +#define REG_SBMATRIX_PRAS3 (*(RwReg *)0x41007098UL) /**< \brief (SBMATRIX) Priority A for Slave 3 */ +#define REG_SBMATRIX_PRBS3 (*(RwReg *)0x4100709CUL) /**< \brief (SBMATRIX) Priority B for Slave 3 */ +#define REG_SBMATRIX_PRAS4 (*(RwReg *)0x410070A0UL) /**< \brief (SBMATRIX) Priority A for Slave 4 */ +#define REG_SBMATRIX_PRBS4 (*(RwReg *)0x410070A4UL) /**< \brief (SBMATRIX) Priority B for Slave 4 */ +#define REG_SBMATRIX_PRAS5 (*(RwReg *)0x410070A8UL) /**< \brief (SBMATRIX) Priority A for Slave 5 */ +#define REG_SBMATRIX_PRBS5 (*(RwReg *)0x410070ACUL) /**< \brief (SBMATRIX) Priority B for Slave 5 */ +#define REG_SBMATRIX_PRAS6 (*(RwReg *)0x410070B0UL) /**< \brief (SBMATRIX) Priority A for Slave 6 */ +#define REG_SBMATRIX_PRBS6 (*(RwReg *)0x410070B4UL) /**< \brief (SBMATRIX) Priority B for Slave 6 */ +#define REG_SBMATRIX_PRAS7 (*(RwReg *)0x410070B8UL) /**< \brief (SBMATRIX) Priority A for Slave 7 */ +#define REG_SBMATRIX_PRBS7 (*(RwReg *)0x410070BCUL) /**< \brief (SBMATRIX) Priority B for Slave 7 */ +#define REG_SBMATRIX_PRAS8 (*(RwReg *)0x410070C0UL) /**< \brief (SBMATRIX) Priority A for Slave 8 */ +#define REG_SBMATRIX_PRBS8 (*(RwReg *)0x410070C4UL) /**< \brief (SBMATRIX) Priority B for Slave 8 */ +#define REG_SBMATRIX_PRAS9 (*(RwReg *)0x410070C8UL) /**< \brief (SBMATRIX) Priority A for Slave 9 */ +#define REG_SBMATRIX_PRBS9 (*(RwReg *)0x410070CCUL) /**< \brief (SBMATRIX) Priority B for Slave 9 */ +#define REG_SBMATRIX_PRAS10 (*(RwReg *)0x410070D0UL) /**< \brief (SBMATRIX) Priority A for Slave 10 */ +#define REG_SBMATRIX_PRBS10 (*(RwReg *)0x410070D4UL) /**< \brief (SBMATRIX) Priority B for Slave 10 */ +#define REG_SBMATRIX_PRAS11 (*(RwReg *)0x410070D8UL) /**< \brief (SBMATRIX) Priority A for Slave 11 */ +#define REG_SBMATRIX_PRBS11 (*(RwReg *)0x410070DCUL) /**< \brief (SBMATRIX) Priority B for Slave 11 */ +#define REG_SBMATRIX_PRAS12 (*(RwReg *)0x410070E0UL) /**< \brief (SBMATRIX) Priority A for Slave 12 */ +#define REG_SBMATRIX_PRBS12 (*(RwReg *)0x410070E4UL) /**< \brief (SBMATRIX) Priority B for Slave 12 */ +#define REG_SBMATRIX_PRAS13 (*(RwReg *)0x410070E8UL) /**< \brief (SBMATRIX) Priority A for Slave 13 */ +#define REG_SBMATRIX_PRBS13 (*(RwReg *)0x410070ECUL) /**< \brief (SBMATRIX) Priority B for Slave 13 */ +#define REG_SBMATRIX_PRAS14 (*(RwReg *)0x410070F0UL) /**< \brief (SBMATRIX) Priority A for Slave 14 */ +#define REG_SBMATRIX_PRBS14 (*(RwReg *)0x410070F4UL) /**< \brief (SBMATRIX) Priority B for Slave 14 */ +#define REG_SBMATRIX_PRAS15 (*(RwReg *)0x410070F8UL) /**< \brief (SBMATRIX) Priority A for Slave 15 */ +#define REG_SBMATRIX_PRBS15 (*(RwReg *)0x410070FCUL) /**< \brief (SBMATRIX) Priority B for Slave 15 */ +#define REG_SBMATRIX_SFR0 (*(RwReg *)0x41007110UL) /**< \brief (SBMATRIX) Special Function 0 */ +#define REG_SBMATRIX_SFR1 (*(RwReg *)0x41007114UL) /**< \brief (SBMATRIX) Special Function 1 */ +#define REG_SBMATRIX_SFR2 (*(RwReg *)0x41007118UL) /**< \brief (SBMATRIX) Special Function 2 */ +#define REG_SBMATRIX_SFR3 (*(RwReg *)0x4100711CUL) /**< \brief (SBMATRIX) Special Function 3 */ +#define REG_SBMATRIX_SFR4 (*(RwReg *)0x41007120UL) /**< \brief (SBMATRIX) Special Function 4 */ +#define REG_SBMATRIX_SFR5 (*(RwReg *)0x41007124UL) /**< \brief (SBMATRIX) Special Function 5 */ +#define REG_SBMATRIX_SFR6 (*(RwReg *)0x41007128UL) /**< \brief (SBMATRIX) Special Function 6 */ +#define REG_SBMATRIX_SFR7 (*(RwReg *)0x4100712CUL) /**< \brief (SBMATRIX) Special Function 7 */ +#define REG_SBMATRIX_SFR8 (*(RwReg *)0x41007130UL) /**< \brief (SBMATRIX) Special Function 8 */ +#define REG_SBMATRIX_SFR9 (*(RwReg *)0x41007134UL) /**< \brief (SBMATRIX) Special Function 9 */ +#define REG_SBMATRIX_SFR10 (*(RwReg *)0x41007138UL) /**< \brief (SBMATRIX) Special Function 10 */ +#define REG_SBMATRIX_SFR11 (*(RwReg *)0x4100713CUL) /**< \brief (SBMATRIX) Special Function 11 */ +#define REG_SBMATRIX_SFR12 (*(RwReg *)0x41007140UL) /**< \brief (SBMATRIX) Special Function 12 */ +#define REG_SBMATRIX_SFR13 (*(RwReg *)0x41007144UL) /**< \brief (SBMATRIX) Special Function 13 */ +#define REG_SBMATRIX_SFR14 (*(RwReg *)0x41007148UL) /**< \brief (SBMATRIX) Special Function 14 */ +#define REG_SBMATRIX_SFR15 (*(RwReg *)0x4100714CUL) /**< \brief (SBMATRIX) Special Function 15 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SBMATRIX peripheral ========== */ +#define SBMATRIX_DEFINED +/* ========== Instance parameters for SBMATRIX ========== */ +#define SBMATRIX_SLAVE_FLASH 0 +#define SBMATRIX_SLAVE_HPB0 1 +#define SBMATRIX_SLAVE_HPB1 2 +#define SBMATRIX_SLAVE_HPB2 3 +#define SBMATRIX_SLAVE_HMCRAMC0 4 +#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5 +#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6 +#define SBMATRIX_SLAVE_NUM 7 + +#define SBMATRIX_MASTER_CM0PLUS 0 +#define SBMATRIX_MASTER_DSU 1 +#define SBMATRIX_MASTER_DMAC 2 +#define SBMATRIX_MASTER_NUM 3 + +#endif /* _SAMD21_SBMATRIX_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/sercom0.h b/atmel-samd/asf4/samd21/include/instance/sercom0.h new file mode 100644 index 000000000..b7065f8d3 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/sercom0.h @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Instance description for SERCOM0 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_SERCOM0_INSTANCE_ +#define _SAMD21_SERCOM0_INSTANCE_ + +/* ========== Register definition for SERCOM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM0_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (0x4200080C) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (0x42000814) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (0x42000816) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (0x42000818) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (0x4200081A) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) I2CM Syncbusy */ +#define REG_SERCOM0_I2CM_ADDR (0x42000824) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (0x42000828) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (0x42000814) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (0x42000816) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (0x42000818) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (0x4200081A) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) I2CS Syncbusy */ +#define REG_SERCOM0_I2CS_ADDR (0x42000824) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (0x42000828) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (0x42000800) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (0x42000804) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (0x4200080C) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (0x42000814) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (0x42000816) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (0x42000818) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (0x4200081A) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) SPI Syncbusy */ +#define REG_SERCOM0_SPI_ADDR (0x42000824) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (0x42000828) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (0x42000830) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (0x42000800) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (0x42000804) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_BAUD (0x4200080C) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (0x4200080E) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (0x42000814) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (0x42000816) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (0x42000818) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (0x4200081A) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) USART Syncbusy */ +#define REG_SERCOM0_USART_DATA (0x42000828) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (0x42000830) /**< \brief (SERCOM0) USART Debug Control */ +#else +#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) I2CM Syncbusy */ +#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) I2CS Syncbusy */ +#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) SPI Syncbusy */ +#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828UL) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) USART Syncbusy */ +#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM0 peripheral ========== */ +#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger +#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger +#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core +#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM0_INT_MSB 6 + +#endif /* _SAMD21_SERCOM0_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/sercom1.h b/atmel-samd/asf4/samd21/include/instance/sercom1.h new file mode 100644 index 000000000..12500b9e3 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/sercom1.h @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Instance description for SERCOM1 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_SERCOM1_INSTANCE_ +#define _SAMD21_SERCOM1_INSTANCE_ + +/* ========== Register definition for SERCOM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM1_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) I2CM Syncbusy */ +#define REG_SERCOM1_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (0x42000C28) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) I2CS Syncbusy */ +#define REG_SERCOM1_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (0x42000C28) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) SPI Syncbusy */ +#define REG_SERCOM1_SPI_ADDR (0x42000C24) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (0x42000C28) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (0x42000C00) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (0x42000C04) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_BAUD (0x42000C0C) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (0x42000C0E) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (0x42000C16) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (0x42000C1A) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) USART Syncbusy */ +#define REG_SERCOM1_USART_DATA (0x42000C28) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) USART Debug Control */ +#else +#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) I2CM Syncbusy */ +#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) I2CS Syncbusy */ +#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) SPI Syncbusy */ +#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) USART Syncbusy */ +#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM1 peripheral ========== */ +#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger +#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger +#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core +#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM1_INT_MSB 6 + +#endif /* _SAMD21_SERCOM1_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/sercom2.h b/atmel-samd/asf4/samd21/include/instance/sercom2.h new file mode 100644 index 000000000..e1816e24f --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/sercom2.h @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Instance description for SERCOM2 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_SERCOM2_INSTANCE_ +#define _SAMD21_SERCOM2_INSTANCE_ + +/* ========== Register definition for SERCOM2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM2_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) I2CM Syncbusy */ +#define REG_SERCOM2_I2CM_ADDR (0x42001024) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (0x42001028) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) I2CS Syncbusy */ +#define REG_SERCOM2_I2CS_ADDR (0x42001024) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (0x42001028) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (0x42001000) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (0x42001004) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (0x4200100C) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (0x42001016) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (0x4200101A) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) SPI Syncbusy */ +#define REG_SERCOM2_SPI_ADDR (0x42001024) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (0x42001028) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (0x42001000) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (0x42001004) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_BAUD (0x4200100C) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (0x4200100E) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (0x42001014) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (0x42001016) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (0x42001018) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (0x4200101A) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) USART Syncbusy */ +#define REG_SERCOM2_USART_DATA (0x42001028) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM2) USART Debug Control */ +#else +#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) I2CM Syncbusy */ +#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) I2CS Syncbusy */ +#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) SPI Syncbusy */ +#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) USART Syncbusy */ +#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM2 peripheral ========== */ +#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger +#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger +#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core +#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM2_INT_MSB 6 + +#endif /* _SAMD21_SERCOM2_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/sercom3.h b/atmel-samd/asf4/samd21/include/instance/sercom3.h new file mode 100644 index 000000000..ad4d85d33 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/sercom3.h @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Instance description for SERCOM3 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_SERCOM3_INSTANCE_ +#define _SAMD21_SERCOM3_INSTANCE_ + +/* ========== Register definition for SERCOM3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM3_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) I2CM Syncbusy */ +#define REG_SERCOM3_I2CM_ADDR (0x42001424) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (0x42001428) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) I2CS Syncbusy */ +#define REG_SERCOM3_I2CS_ADDR (0x42001424) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (0x42001428) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (0x42001400) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (0x42001404) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (0x4200140C) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (0x42001416) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (0x4200141A) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) SPI Syncbusy */ +#define REG_SERCOM3_SPI_ADDR (0x42001424) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (0x42001428) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (0x42001400) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (0x42001404) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_BAUD (0x4200140C) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (0x4200140E) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (0x42001414) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (0x42001416) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (0x42001418) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (0x4200141A) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) USART Syncbusy */ +#define REG_SERCOM3_USART_DATA (0x42001428) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM3) USART Debug Control */ +#else +#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) I2CM Syncbusy */ +#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) I2CS Syncbusy */ +#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) SPI Syncbusy */ +#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) USART Syncbusy */ +#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM3 peripheral ========== */ +#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger +#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger +#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core +#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM3_INT_MSB 6 + +#endif /* _SAMD21_SERCOM3_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/sercom4.h b/atmel-samd/asf4/samd21/include/instance/sercom4.h new file mode 100644 index 000000000..b51c4626b --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/sercom4.h @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Instance description for SERCOM4 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_SERCOM4_INSTANCE_ +#define _SAMD21_SERCOM4_INSTANCE_ + +/* ========== Register definition for SERCOM4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM4_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) I2CM Syncbusy */ +#define REG_SERCOM4_I2CM_ADDR (0x42001824) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (0x42001828) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) I2CS Syncbusy */ +#define REG_SERCOM4_I2CS_ADDR (0x42001824) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (0x42001828) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (0x42001800) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (0x42001804) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (0x4200180C) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (0x42001816) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (0x4200181A) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) SPI Syncbusy */ +#define REG_SERCOM4_SPI_ADDR (0x42001824) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (0x42001828) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (0x42001800) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (0x42001804) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_BAUD (0x4200180C) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (0x4200180E) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (0x42001814) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (0x42001816) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (0x42001818) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (0x4200181A) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) USART Syncbusy */ +#define REG_SERCOM4_USART_DATA (0x42001828) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM4) USART Debug Control */ +#else +#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) I2CM Syncbusy */ +#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) I2CS Syncbusy */ +#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) SPI Syncbusy */ +#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) USART Syncbusy */ +#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM4 peripheral ========== */ +#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger +#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger +#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core +#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM4_INT_MSB 6 + +#endif /* _SAMD21_SERCOM4_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/sercom5.h b/atmel-samd/asf4/samd21/include/instance/sercom5.h new file mode 100644 index 000000000..70ffc3be9 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/sercom5.h @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Instance description for SERCOM5 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_SERCOM5_INSTANCE_ +#define _SAMD21_SERCOM5_INSTANCE_ + +/* ========== Register definition for SERCOM5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM5_I2CM_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (0x42001C0C) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (0x42001C16) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (0x42001C1A) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) I2CM Syncbusy */ +#define REG_SERCOM5_I2CM_ADDR (0x42001C24) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (0x42001C28) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (0x42001C16) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (0x42001C1A) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) I2CS Syncbusy */ +#define REG_SERCOM5_I2CS_ADDR (0x42001C24) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (0x42001C28) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (0x42001C00) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (0x42001C04) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (0x42001C0C) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (0x42001C14) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (0x42001C16) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (0x42001C18) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (0x42001C1A) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) SPI Syncbusy */ +#define REG_SERCOM5_SPI_ADDR (0x42001C24) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (0x42001C28) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (0x42001C00) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (0x42001C04) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_BAUD (0x42001C0C) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (0x42001C0E) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (0x42001C14) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (0x42001C16) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (0x42001C18) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (0x42001C1A) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) USART Syncbusy */ +#define REG_SERCOM5_USART_DATA (0x42001C28) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) USART Debug Control */ +#else +#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CUL) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) I2CM Syncbusy */ +#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) I2CS Syncbusy */ +#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) SPI Syncbusy */ +#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28UL) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CUL) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) USART Syncbusy */ +#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28UL) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM5 peripheral ========== */ +#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger +#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger +#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core +#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM5_INT_MSB 6 + +#endif /* _SAMD21_SERCOM5_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/sysctrl.h b/atmel-samd/asf4/samd21/include/instance/sysctrl.h new file mode 100644 index 000000000..fe31e772a --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/sysctrl.h @@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for SYSCTRL + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_SYSCTRL_INSTANCE_ +#define _SAMD21_SYSCTRL_INSTANCE_ + +/* ========== Register definition for SYSCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SYSCTRL_INTENCLR (0x40000800) /**< \brief (SYSCTRL) Interrupt Enable Clear */ +#define REG_SYSCTRL_INTENSET (0x40000804) /**< \brief (SYSCTRL) Interrupt Enable Set */ +#define REG_SYSCTRL_INTFLAG (0x40000808) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ +#define REG_SYSCTRL_PCLKSR (0x4000080C) /**< \brief (SYSCTRL) Power and Clocks Status */ +#define REG_SYSCTRL_XOSC (0x40000810) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_SYSCTRL_XOSC32K (0x40000814) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_SYSCTRL_OSC32K (0x40000818) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ +#define REG_SYSCTRL_OSCULP32K (0x4000081C) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#define REG_SYSCTRL_OSC8M (0x40000820) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ +#define REG_SYSCTRL_DFLLCTRL (0x40000824) /**< \brief (SYSCTRL) DFLL48M Control */ +#define REG_SYSCTRL_DFLLVAL (0x40000828) /**< \brief (SYSCTRL) DFLL48M Value */ +#define REG_SYSCTRL_DFLLMUL (0x4000082C) /**< \brief (SYSCTRL) DFLL48M Multiplier */ +#define REG_SYSCTRL_DFLLSYNC (0x40000830) /**< \brief (SYSCTRL) DFLL48M Synchronization */ +#define REG_SYSCTRL_BOD33 (0x40000834) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ +#define REG_SYSCTRL_VREG (0x4000083C) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ +#define REG_SYSCTRL_VREF (0x40000840) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ +#define REG_SYSCTRL_DPLLCTRLA (0x40000844) /**< \brief (SYSCTRL) DPLL Control A */ +#define REG_SYSCTRL_DPLLRATIO (0x40000848) /**< \brief (SYSCTRL) DPLL Ratio Control */ +#define REG_SYSCTRL_DPLLCTRLB (0x4000084C) /**< \brief (SYSCTRL) DPLL Control B */ +#define REG_SYSCTRL_DPLLSTATUS (0x40000850) /**< \brief (SYSCTRL) DPLL Status */ +#else +#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800UL) /**< \brief (SYSCTRL) Interrupt Enable Clear */ +#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804UL) /**< \brief (SYSCTRL) Interrupt Enable Set */ +#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808UL) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ +#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CUL) /**< \brief (SYSCTRL) Power and Clocks Status */ +#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810UL) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814UL) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818UL) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ +#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CUL) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820UL) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ +#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824UL) /**< \brief (SYSCTRL) DFLL48M Control */ +#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828UL) /**< \brief (SYSCTRL) DFLL48M Value */ +#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CUL) /**< \brief (SYSCTRL) DFLL48M Multiplier */ +#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830UL) /**< \brief (SYSCTRL) DFLL48M Synchronization */ +#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834UL) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ +#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CUL) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ +#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840UL) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ +#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844UL) /**< \brief (SYSCTRL) DPLL Control A */ +#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848UL) /**< \brief (SYSCTRL) DPLL Ratio Control */ +#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CUL) /**< \brief (SYSCTRL) DPLL Control B */ +#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850UL) /**< \brief (SYSCTRL) DPLL Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SYSCTRL peripheral ========== */ +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 5 +#define SYSCTRL_DFLL48M_FINE_MSB 9 +#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 +#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL +#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_SYSTEM_CLOCK 1000000 // Initial system clock frequency +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x111 +#define SYSCTRL_BOD33_VERSION 0x111 +#define SYSCTRL_DFLL48M_VERSION 0x301 +#define SYSCTRL_FDPLL_VERSION 0x111 +#define SYSCTRL_OSCULP32K_VERSION 0x111 +#define SYSCTRL_OSC8M_VERSION 0x120 +#define SYSCTRL_OSC32K_VERSION 0x1101 +#define SYSCTRL_VREF_VERSION 0x200 +#define SYSCTRL_VREG_VERSION 0x201 +#define SYSCTRL_XOSC_VERSION 0x1111 +#define SYSCTRL_XOSC32K_VERSION 0x1111 + +#endif /* _SAMD21_SYSCTRL_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/tc3.h b/atmel-samd/asf4/samd21/include/instance/tc3.h new file mode 100644 index 000000000..b7acb6893 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/tc3.h @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief Instance description for TC3 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_TC3_INSTANCE_ +#define _SAMD21_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */ +#define REG_TC3_READREQ (0x42002C02) /**< \brief (TC3) Read Request */ +#define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */ +#define REG_TC3_CTRLC (0x42002C06) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (0x42002C08) /**< \brief (TC3) Debug Control */ +#define REG_TC3_EVCTRL (0x42002C0A) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (0x42002C0C) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (0x42002C0D) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (0x42002C0E) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (0x42002C0F) /**< \brief (TC3) Status */ +#define REG_TC3_COUNT16_COUNT (0x42002C10) /**< \brief (TC3) COUNT16 Counter Value */ +#define REG_TC3_COUNT16_CC0 (0x42002C18) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ +#define REG_TC3_COUNT16_CC1 (0x42002C1A) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ +#define REG_TC3_COUNT32_COUNT (0x42002C10) /**< \brief (TC3) COUNT32 Counter Value */ +#define REG_TC3_COUNT32_CC0 (0x42002C18) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ +#define REG_TC3_COUNT32_CC1 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ +#define REG_TC3_COUNT8_COUNT (0x42002C10) /**< \brief (TC3) COUNT8 Counter Value */ +#define REG_TC3_COUNT8_PER (0x42002C14) /**< \brief (TC3) COUNT8 Period Value */ +#define REG_TC3_COUNT8_CC0 (0x42002C18) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ +#define REG_TC3_COUNT8_CC1 (0x42002C19) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00UL) /**< \brief (TC3) Control A */ +#define REG_TC3_READREQ (*(RwReg16*)0x42002C02UL) /**< \brief (TC3) Read Request */ +#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */ +#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06UL) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Debug Control */ +#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AUL) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EUL) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FUL) /**< \brief (TC3) Status */ +#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10UL) /**< \brief (TC3) COUNT16 Counter Value */ +#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18UL) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ +#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AUL) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ +#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10UL) /**< \brief (TC3) COUNT32 Counter Value */ +#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18UL) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ +#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ +#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10UL) /**< \brief (TC3) COUNT8 Counter Value */ +#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Period Value */ +#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18UL) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ +#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19UL) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC3 peripheral ========== */ +#define TC3_CC8_NUM 2 // Number of 8-bit Counters +#define TC3_CC16_NUM 2 // Number of 16-bit Counters +#define TC3_CC32_NUM 2 // Number of 32-bit Counters +#define TC3_DITHERING_EXT 0 // Dithering feature implemented +#define TC3_DMAC_ID_MC_0 25 +#define TC3_DMAC_ID_MC_1 26 +#define TC3_DMAC_ID_MC_LSB 25 +#define TC3_DMAC_ID_MC_MSB 26 +#define TC3_DMAC_ID_MC_SIZE 2 +#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger +#define TC3_GCLK_ID 27 // Index of Generic Clock +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 // Number of Output Waveforms +#define TC3_PERIOD_EXT 0 // Period feature implemented +#define TC3_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC3_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/tc4.h b/atmel-samd/asf4/samd21/include/instance/tc4.h new file mode 100644 index 000000000..83aeea408 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/tc4.h @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief Instance description for TC4 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_TC4_INSTANCE_ +#define _SAMD21_TC4_INSTANCE_ + +/* ========== Register definition for TC4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC4_CTRLA (0x42003000) /**< \brief (TC4) Control A */ +#define REG_TC4_READREQ (0x42003002) /**< \brief (TC4) Read Request */ +#define REG_TC4_CTRLBCLR (0x42003004) /**< \brief (TC4) Control B Clear */ +#define REG_TC4_CTRLBSET (0x42003005) /**< \brief (TC4) Control B Set */ +#define REG_TC4_CTRLC (0x42003006) /**< \brief (TC4) Control C */ +#define REG_TC4_DBGCTRL (0x42003008) /**< \brief (TC4) Debug Control */ +#define REG_TC4_EVCTRL (0x4200300A) /**< \brief (TC4) Event Control */ +#define REG_TC4_INTENCLR (0x4200300C) /**< \brief (TC4) Interrupt Enable Clear */ +#define REG_TC4_INTENSET (0x4200300D) /**< \brief (TC4) Interrupt Enable Set */ +#define REG_TC4_INTFLAG (0x4200300E) /**< \brief (TC4) Interrupt Flag Status and Clear */ +#define REG_TC4_STATUS (0x4200300F) /**< \brief (TC4) Status */ +#define REG_TC4_COUNT16_COUNT (0x42003010) /**< \brief (TC4) COUNT16 Counter Value */ +#define REG_TC4_COUNT16_CC0 (0x42003018) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ +#define REG_TC4_COUNT16_CC1 (0x4200301A) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ +#define REG_TC4_COUNT32_COUNT (0x42003010) /**< \brief (TC4) COUNT32 Counter Value */ +#define REG_TC4_COUNT32_CC0 (0x42003018) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ +#define REG_TC4_COUNT32_CC1 (0x4200301C) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ +#define REG_TC4_COUNT8_COUNT (0x42003010) /**< \brief (TC4) COUNT8 Counter Value */ +#define REG_TC4_COUNT8_PER (0x42003014) /**< \brief (TC4) COUNT8 Period Value */ +#define REG_TC4_COUNT8_CC0 (0x42003018) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ +#define REG_TC4_COUNT8_CC1 (0x42003019) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC4_CTRLA (*(RwReg16*)0x42003000UL) /**< \brief (TC4) Control A */ +#define REG_TC4_READREQ (*(RwReg16*)0x42003002UL) /**< \brief (TC4) Read Request */ +#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004UL) /**< \brief (TC4) Control B Clear */ +#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005UL) /**< \brief (TC4) Control B Set */ +#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006UL) /**< \brief (TC4) Control C */ +#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008UL) /**< \brief (TC4) Debug Control */ +#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AUL) /**< \brief (TC4) Event Control */ +#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CUL) /**< \brief (TC4) Interrupt Enable Clear */ +#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DUL) /**< \brief (TC4) Interrupt Enable Set */ +#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EUL) /**< \brief (TC4) Interrupt Flag Status and Clear */ +#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FUL) /**< \brief (TC4) Status */ +#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010UL) /**< \brief (TC4) COUNT16 Counter Value */ +#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018UL) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ +#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AUL) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ +#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010UL) /**< \brief (TC4) COUNT32 Counter Value */ +#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018UL) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ +#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CUL) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ +#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010UL) /**< \brief (TC4) COUNT8 Counter Value */ +#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014UL) /**< \brief (TC4) COUNT8 Period Value */ +#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018UL) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ +#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019UL) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC4 peripheral ========== */ +#define TC4_CC8_NUM 2 // Number of 8-bit Counters +#define TC4_CC16_NUM 2 // Number of 16-bit Counters +#define TC4_CC32_NUM 2 // Number of 32-bit Counters +#define TC4_DITHERING_EXT 0 // Dithering feature implemented +#define TC4_DMAC_ID_MC_0 28 +#define TC4_DMAC_ID_MC_1 29 +#define TC4_DMAC_ID_MC_LSB 28 +#define TC4_DMAC_ID_MC_MSB 29 +#define TC4_DMAC_ID_MC_SIZE 2 +#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger +#define TC4_GCLK_ID 28 // Index of Generic Clock +#define TC4_MASTER 1 +#define TC4_OW_NUM 2 // Number of Output Waveforms +#define TC4_PERIOD_EXT 0 // Period feature implemented +#define TC4_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC4_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/tc5.h b/atmel-samd/asf4/samd21/include/instance/tc5.h new file mode 100644 index 000000000..0a364f375 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/tc5.h @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief Instance description for TC5 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_TC5_INSTANCE_ +#define _SAMD21_TC5_INSTANCE_ + +/* ========== Register definition for TC5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC5_CTRLA (0x42003400) /**< \brief (TC5) Control A */ +#define REG_TC5_READREQ (0x42003402) /**< \brief (TC5) Read Request */ +#define REG_TC5_CTRLBCLR (0x42003404) /**< \brief (TC5) Control B Clear */ +#define REG_TC5_CTRLBSET (0x42003405) /**< \brief (TC5) Control B Set */ +#define REG_TC5_CTRLC (0x42003406) /**< \brief (TC5) Control C */ +#define REG_TC5_DBGCTRL (0x42003408) /**< \brief (TC5) Debug Control */ +#define REG_TC5_EVCTRL (0x4200340A) /**< \brief (TC5) Event Control */ +#define REG_TC5_INTENCLR (0x4200340C) /**< \brief (TC5) Interrupt Enable Clear */ +#define REG_TC5_INTENSET (0x4200340D) /**< \brief (TC5) Interrupt Enable Set */ +#define REG_TC5_INTFLAG (0x4200340E) /**< \brief (TC5) Interrupt Flag Status and Clear */ +#define REG_TC5_STATUS (0x4200340F) /**< \brief (TC5) Status */ +#define REG_TC5_COUNT16_COUNT (0x42003410) /**< \brief (TC5) COUNT16 Counter Value */ +#define REG_TC5_COUNT16_CC0 (0x42003418) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ +#define REG_TC5_COUNT16_CC1 (0x4200341A) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ +#define REG_TC5_COUNT32_COUNT (0x42003410) /**< \brief (TC5) COUNT32 Counter Value */ +#define REG_TC5_COUNT32_CC0 (0x42003418) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ +#define REG_TC5_COUNT32_CC1 (0x4200341C) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ +#define REG_TC5_COUNT8_COUNT (0x42003410) /**< \brief (TC5) COUNT8 Counter Value */ +#define REG_TC5_COUNT8_PER (0x42003414) /**< \brief (TC5) COUNT8 Period Value */ +#define REG_TC5_COUNT8_CC0 (0x42003418) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ +#define REG_TC5_COUNT8_CC1 (0x42003419) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC5_CTRLA (*(RwReg16*)0x42003400UL) /**< \brief (TC5) Control A */ +#define REG_TC5_READREQ (*(RwReg16*)0x42003402UL) /**< \brief (TC5) Read Request */ +#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404UL) /**< \brief (TC5) Control B Clear */ +#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405UL) /**< \brief (TC5) Control B Set */ +#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406UL) /**< \brief (TC5) Control C */ +#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408UL) /**< \brief (TC5) Debug Control */ +#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AUL) /**< \brief (TC5) Event Control */ +#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CUL) /**< \brief (TC5) Interrupt Enable Clear */ +#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DUL) /**< \brief (TC5) Interrupt Enable Set */ +#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EUL) /**< \brief (TC5) Interrupt Flag Status and Clear */ +#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FUL) /**< \brief (TC5) Status */ +#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410UL) /**< \brief (TC5) COUNT16 Counter Value */ +#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418UL) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ +#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AUL) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ +#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410UL) /**< \brief (TC5) COUNT32 Counter Value */ +#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418UL) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ +#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CUL) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ +#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410UL) /**< \brief (TC5) COUNT8 Counter Value */ +#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414UL) /**< \brief (TC5) COUNT8 Period Value */ +#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418UL) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ +#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419UL) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC5 peripheral ========== */ +#define TC5_CC8_NUM 2 // Number of 8-bit Counters +#define TC5_CC16_NUM 2 // Number of 16-bit Counters +#define TC5_CC32_NUM 2 // Number of 32-bit Counters +#define TC5_DITHERING_EXT 0 // Dithering feature implemented +#define TC5_DMAC_ID_MC_0 31 +#define TC5_DMAC_ID_MC_1 32 +#define TC5_DMAC_ID_MC_LSB 31 +#define TC5_DMAC_ID_MC_MSB 32 +#define TC5_DMAC_ID_MC_SIZE 2 +#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger +#define TC5_GCLK_ID 28 // Index of Generic Clock +#define TC5_MASTER 0 +#define TC5_OW_NUM 2 // Number of Output Waveforms +#define TC5_PERIOD_EXT 0 // Period feature implemented +#define TC5_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC5_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/tc6.h b/atmel-samd/asf4/samd21/include/instance/tc6.h new file mode 100644 index 000000000..debdf847b --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/tc6.h @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief Instance description for TC6 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_TC6_INSTANCE_ +#define _SAMD21_TC6_INSTANCE_ + +/* ========== Register definition for TC6 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC6_CTRLA (0x42003800) /**< \brief (TC6) Control A */ +#define REG_TC6_READREQ (0x42003802) /**< \brief (TC6) Read Request */ +#define REG_TC6_CTRLBCLR (0x42003804) /**< \brief (TC6) Control B Clear */ +#define REG_TC6_CTRLBSET (0x42003805) /**< \brief (TC6) Control B Set */ +#define REG_TC6_CTRLC (0x42003806) /**< \brief (TC6) Control C */ +#define REG_TC6_DBGCTRL (0x42003808) /**< \brief (TC6) Debug Control */ +#define REG_TC6_EVCTRL (0x4200380A) /**< \brief (TC6) Event Control */ +#define REG_TC6_INTENCLR (0x4200380C) /**< \brief (TC6) Interrupt Enable Clear */ +#define REG_TC6_INTENSET (0x4200380D) /**< \brief (TC6) Interrupt Enable Set */ +#define REG_TC6_INTFLAG (0x4200380E) /**< \brief (TC6) Interrupt Flag Status and Clear */ +#define REG_TC6_STATUS (0x4200380F) /**< \brief (TC6) Status */ +#define REG_TC6_COUNT16_COUNT (0x42003810) /**< \brief (TC6) COUNT16 Counter Value */ +#define REG_TC6_COUNT16_CC0 (0x42003818) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ +#define REG_TC6_COUNT16_CC1 (0x4200381A) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ +#define REG_TC6_COUNT32_COUNT (0x42003810) /**< \brief (TC6) COUNT32 Counter Value */ +#define REG_TC6_COUNT32_CC0 (0x42003818) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ +#define REG_TC6_COUNT32_CC1 (0x4200381C) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ +#define REG_TC6_COUNT8_COUNT (0x42003810) /**< \brief (TC6) COUNT8 Counter Value */ +#define REG_TC6_COUNT8_PER (0x42003814) /**< \brief (TC6) COUNT8 Period Value */ +#define REG_TC6_COUNT8_CC0 (0x42003818) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ +#define REG_TC6_COUNT8_CC1 (0x42003819) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC6_CTRLA (*(RwReg16*)0x42003800UL) /**< \brief (TC6) Control A */ +#define REG_TC6_READREQ (*(RwReg16*)0x42003802UL) /**< \brief (TC6) Read Request */ +#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804UL) /**< \brief (TC6) Control B Clear */ +#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805UL) /**< \brief (TC6) Control B Set */ +#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806UL) /**< \brief (TC6) Control C */ +#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808UL) /**< \brief (TC6) Debug Control */ +#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AUL) /**< \brief (TC6) Event Control */ +#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CUL) /**< \brief (TC6) Interrupt Enable Clear */ +#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DUL) /**< \brief (TC6) Interrupt Enable Set */ +#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EUL) /**< \brief (TC6) Interrupt Flag Status and Clear */ +#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FUL) /**< \brief (TC6) Status */ +#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810UL) /**< \brief (TC6) COUNT16 Counter Value */ +#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818UL) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ +#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AUL) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ +#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810UL) /**< \brief (TC6) COUNT32 Counter Value */ +#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818UL) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ +#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CUL) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ +#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810UL) /**< \brief (TC6) COUNT8 Counter Value */ +#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814UL) /**< \brief (TC6) COUNT8 Period Value */ +#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818UL) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ +#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819UL) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC6 peripheral ========== */ +#define TC6_CC8_NUM 2 // Number of 8-bit Counters +#define TC6_CC16_NUM 2 // Number of 16-bit Counters +#define TC6_CC32_NUM 2 // Number of 32-bit Counters +#define TC6_DITHERING_EXT 0 // Dithering feature implemented +#define TC6_DMAC_ID_MC_0 34 +#define TC6_DMAC_ID_MC_1 35 +#define TC6_DMAC_ID_MC_LSB 34 +#define TC6_DMAC_ID_MC_MSB 35 +#define TC6_DMAC_ID_MC_SIZE 2 +#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger +#define TC6_GCLK_ID 29 // Index of Generic Clock +#define TC6_MASTER 1 +#define TC6_OW_NUM 2 // Number of Output Waveforms +#define TC6_PERIOD_EXT 0 // Period feature implemented +#define TC6_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC6_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/tc7.h b/atmel-samd/asf4/samd21/include/instance/tc7.h new file mode 100644 index 000000000..299f6ab79 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/tc7.h @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief Instance description for TC7 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_TC7_INSTANCE_ +#define _SAMD21_TC7_INSTANCE_ + +/* ========== Register definition for TC7 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC7_CTRLA (0x42003C00) /**< \brief (TC7) Control A */ +#define REG_TC7_READREQ (0x42003C02) /**< \brief (TC7) Read Request */ +#define REG_TC7_CTRLBCLR (0x42003C04) /**< \brief (TC7) Control B Clear */ +#define REG_TC7_CTRLBSET (0x42003C05) /**< \brief (TC7) Control B Set */ +#define REG_TC7_CTRLC (0x42003C06) /**< \brief (TC7) Control C */ +#define REG_TC7_DBGCTRL (0x42003C08) /**< \brief (TC7) Debug Control */ +#define REG_TC7_EVCTRL (0x42003C0A) /**< \brief (TC7) Event Control */ +#define REG_TC7_INTENCLR (0x42003C0C) /**< \brief (TC7) Interrupt Enable Clear */ +#define REG_TC7_INTENSET (0x42003C0D) /**< \brief (TC7) Interrupt Enable Set */ +#define REG_TC7_INTFLAG (0x42003C0E) /**< \brief (TC7) Interrupt Flag Status and Clear */ +#define REG_TC7_STATUS (0x42003C0F) /**< \brief (TC7) Status */ +#define REG_TC7_COUNT16_COUNT (0x42003C10) /**< \brief (TC7) COUNT16 Counter Value */ +#define REG_TC7_COUNT16_CC0 (0x42003C18) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ +#define REG_TC7_COUNT16_CC1 (0x42003C1A) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ +#define REG_TC7_COUNT32_COUNT (0x42003C10) /**< \brief (TC7) COUNT32 Counter Value */ +#define REG_TC7_COUNT32_CC0 (0x42003C18) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ +#define REG_TC7_COUNT32_CC1 (0x42003C1C) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ +#define REG_TC7_COUNT8_COUNT (0x42003C10) /**< \brief (TC7) COUNT8 Counter Value */ +#define REG_TC7_COUNT8_PER (0x42003C14) /**< \brief (TC7) COUNT8 Period Value */ +#define REG_TC7_COUNT8_CC0 (0x42003C18) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ +#define REG_TC7_COUNT8_CC1 (0x42003C19) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00UL) /**< \brief (TC7) Control A */ +#define REG_TC7_READREQ (*(RwReg16*)0x42003C02UL) /**< \brief (TC7) Read Request */ +#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04UL) /**< \brief (TC7) Control B Clear */ +#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05UL) /**< \brief (TC7) Control B Set */ +#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06UL) /**< \brief (TC7) Control C */ +#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08UL) /**< \brief (TC7) Debug Control */ +#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AUL) /**< \brief (TC7) Event Control */ +#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CUL) /**< \brief (TC7) Interrupt Enable Clear */ +#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DUL) /**< \brief (TC7) Interrupt Enable Set */ +#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EUL) /**< \brief (TC7) Interrupt Flag Status and Clear */ +#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FUL) /**< \brief (TC7) Status */ +#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10UL) /**< \brief (TC7) COUNT16 Counter Value */ +#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18UL) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ +#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AUL) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ +#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10UL) /**< \brief (TC7) COUNT32 Counter Value */ +#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18UL) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ +#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CUL) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ +#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10UL) /**< \brief (TC7) COUNT8 Counter Value */ +#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14UL) /**< \brief (TC7) COUNT8 Period Value */ +#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18UL) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ +#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19UL) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC7 peripheral ========== */ +#define TC7_CC8_NUM 2 // Number of 8-bit Counters +#define TC7_CC16_NUM 2 // Number of 16-bit Counters +#define TC7_CC32_NUM 2 // Number of 32-bit Counters +#define TC7_DITHERING_EXT 0 // Dithering feature implemented +#define TC7_DMAC_ID_MC_0 37 +#define TC7_DMAC_ID_MC_1 38 +#define TC7_DMAC_ID_MC_LSB 37 +#define TC7_DMAC_ID_MC_MSB 38 +#define TC7_DMAC_ID_MC_SIZE 2 +#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger +#define TC7_GCLK_ID 29 // Index of Generic Clock +#define TC7_MASTER 0 +#define TC7_OW_NUM 2 // Number of Output Waveforms +#define TC7_PERIOD_EXT 0 // Period feature implemented +#define TC7_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC7_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/tcc0.h b/atmel-samd/asf4/samd21/include/instance/tcc0.h new file mode 100644 index 000000000..451eaecf7 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/tcc0.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief Instance description for TCC0 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_TCC0_INSTANCE_ +#define _SAMD21_TCC0_INSTANCE_ + +/* ========== Register definition for TCC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC0_CTRLA (0x42002000) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (0x42002004) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (0x42002005) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (0x42002008) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (0x4200200C) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (0x42002010) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (0x42002014) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (0x42002018) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (0x4200201E) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (0x42002020) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (0x42002024) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (0x42002028) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (0x4200202C) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (0x42002030) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (0x42002034) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (0x42002038) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (0x4200203C) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (0x42002040) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (0x42002044) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (0x42002048) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (0x4200204C) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (0x42002050) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTB (0x42002064) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_WAVEB (0x42002068) /**< \brief (TCC0) Waveform Control Buffer */ +#define REG_TCC0_PERB (0x4200206C) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCB0 (0x42002070) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCB1 (0x42002074) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCB2 (0x42002078) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCB3 (0x4200207C) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#else +#define REG_TCC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008UL) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014UL) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018UL) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EUL) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020UL) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024UL) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (*(RwReg *)0x42002028UL) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (*(RwReg *)0x42002030UL) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (*(RwReg *)0x42002034UL) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (*(RwReg16*)0x42002038UL) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (*(RwReg *)0x4200203CUL) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (*(RwReg *)0x42002040UL) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (*(RwReg *)0x42002044UL) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (*(RwReg *)0x42002048UL) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (*(RwReg *)0x4200204CUL) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (*(RwReg *)0x42002050UL) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTB (*(RwReg16*)0x42002064UL) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_WAVEB (*(RwReg *)0x42002068UL) /**< \brief (TCC0) Waveform Control Buffer */ +#define REG_TCC0_PERB (*(RwReg *)0x4200206CUL) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCB0 (*(RwReg *)0x42002070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCB1 (*(RwReg *)0x42002074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCB2 (*(RwReg *)0x42002078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC0 peripheral ========== */ +#define TCC0_CC_NUM 4 // Number of Compare/Capture units +#define TCC0_DITHERING 1 // Dithering feature implemented +#define TCC0_DMAC_ID_MC_0 14 +#define TCC0_DMAC_ID_MC_1 15 +#define TCC0_DMAC_ID_MC_2 16 +#define TCC0_DMAC_ID_MC_3 17 +#define TCC0_DMAC_ID_MC_LSB 14 +#define TCC0_DMAC_ID_MC_MSB 17 +#define TCC0_DMAC_ID_MC_SIZE 4 +#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger +#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented +#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1) +#define TCC0_GCLK_ID 26 // Index of Generic Clock +#define TCC0_OTMX 1 // Output Matrix feature implemented +#define TCC0_OW_NUM 8 // Number of Output Waveforms +#define TCC0_PG 1 // Pattern Generation feature implemented +#define TCC0_SIZE 24 +#define TCC0_SWAP 1 // DTI outputs swap feature implemented +#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAMD21_TCC0_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/tcc1.h b/atmel-samd/asf4/samd21/include/instance/tcc1.h new file mode 100644 index 000000000..64dc3dbdc --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/tcc1.h @@ -0,0 +1,104 @@ +/** + * \file + * + * \brief Instance description for TCC1 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_TCC1_INSTANCE_ +#define _SAMD21_TCC1_INSTANCE_ + +/* ========== Register definition for TCC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC1_CTRLA (0x42002400) /**< \brief (TCC1) Control A */ +#define REG_TCC1_CTRLBCLR (0x42002404) /**< \brief (TCC1) Control B Clear */ +#define REG_TCC1_CTRLBSET (0x42002405) /**< \brief (TCC1) Control B Set */ +#define REG_TCC1_SYNCBUSY (0x42002408) /**< \brief (TCC1) Synchronization Busy */ +#define REG_TCC1_FCTRLA (0x4200240C) /**< \brief (TCC1) Recoverable Fault A Configuration */ +#define REG_TCC1_FCTRLB (0x42002410) /**< \brief (TCC1) Recoverable Fault B Configuration */ +#define REG_TCC1_DRVCTRL (0x42002418) /**< \brief (TCC1) Driver Control */ +#define REG_TCC1_DBGCTRL (0x4200241E) /**< \brief (TCC1) Debug Control */ +#define REG_TCC1_EVCTRL (0x42002420) /**< \brief (TCC1) Event Control */ +#define REG_TCC1_INTENCLR (0x42002424) /**< \brief (TCC1) Interrupt Enable Clear */ +#define REG_TCC1_INTENSET (0x42002428) /**< \brief (TCC1) Interrupt Enable Set */ +#define REG_TCC1_INTFLAG (0x4200242C) /**< \brief (TCC1) Interrupt Flag Status and Clear */ +#define REG_TCC1_STATUS (0x42002430) /**< \brief (TCC1) Status */ +#define REG_TCC1_COUNT (0x42002434) /**< \brief (TCC1) Count */ +#define REG_TCC1_PATT (0x42002438) /**< \brief (TCC1) Pattern */ +#define REG_TCC1_WAVE (0x4200243C) /**< \brief (TCC1) Waveform Control */ +#define REG_TCC1_PER (0x42002440) /**< \brief (TCC1) Period */ +#define REG_TCC1_CC0 (0x42002444) /**< \brief (TCC1) Compare and Capture 0 */ +#define REG_TCC1_CC1 (0x42002448) /**< \brief (TCC1) Compare and Capture 1 */ +#define REG_TCC1_PATTB (0x42002464) /**< \brief (TCC1) Pattern Buffer */ +#define REG_TCC1_WAVEB (0x42002468) /**< \brief (TCC1) Waveform Control Buffer */ +#define REG_TCC1_PERB (0x4200246C) /**< \brief (TCC1) Period Buffer */ +#define REG_TCC1_CCB0 (0x42002470) /**< \brief (TCC1) Compare and Capture Buffer 0 */ +#define REG_TCC1_CCB1 (0x42002474) /**< \brief (TCC1) Compare and Capture Buffer 1 */ +#else +#define REG_TCC1_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TCC1) Control A */ +#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TCC1) Control B Clear */ +#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TCC1) Control B Set */ +#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408UL) /**< \brief (TCC1) Synchronization Busy */ +#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */ +#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410UL) /**< \brief (TCC1) Recoverable Fault B Configuration */ +#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418UL) /**< \brief (TCC1) Driver Control */ +#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EUL) /**< \brief (TCC1) Debug Control */ +#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420UL) /**< \brief (TCC1) Event Control */ +#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424UL) /**< \brief (TCC1) Interrupt Enable Clear */ +#define REG_TCC1_INTENSET (*(RwReg *)0x42002428UL) /**< \brief (TCC1) Interrupt Enable Set */ +#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */ +#define REG_TCC1_STATUS (*(RwReg *)0x42002430UL) /**< \brief (TCC1) Status */ +#define REG_TCC1_COUNT (*(RwReg *)0x42002434UL) /**< \brief (TCC1) Count */ +#define REG_TCC1_PATT (*(RwReg16*)0x42002438UL) /**< \brief (TCC1) Pattern */ +#define REG_TCC1_WAVE (*(RwReg *)0x4200243CUL) /**< \brief (TCC1) Waveform Control */ +#define REG_TCC1_PER (*(RwReg *)0x42002440UL) /**< \brief (TCC1) Period */ +#define REG_TCC1_CC0 (*(RwReg *)0x42002444UL) /**< \brief (TCC1) Compare and Capture 0 */ +#define REG_TCC1_CC1 (*(RwReg *)0x42002448UL) /**< \brief (TCC1) Compare and Capture 1 */ +#define REG_TCC1_PATTB (*(RwReg16*)0x42002464UL) /**< \brief (TCC1) Pattern Buffer */ +#define REG_TCC1_WAVEB (*(RwReg *)0x42002468UL) /**< \brief (TCC1) Waveform Control Buffer */ +#define REG_TCC1_PERB (*(RwReg *)0x4200246CUL) /**< \brief (TCC1) Period Buffer */ +#define REG_TCC1_CCB0 (*(RwReg *)0x42002470UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */ +#define REG_TCC1_CCB1 (*(RwReg *)0x42002474UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC1 peripheral ========== */ +#define TCC1_CC_NUM 2 // Number of Compare/Capture units +#define TCC1_DITHERING 1 // Dithering feature implemented +#define TCC1_DMAC_ID_MC_0 19 +#define TCC1_DMAC_ID_MC_1 20 +#define TCC1_DMAC_ID_MC_LSB 19 +#define TCC1_DMAC_ID_MC_MSB 20 +#define TCC1_DMAC_ID_MC_SIZE 2 +#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger +#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented +#define TCC1_EXT 24 // Coding of implemented extended features +#define TCC1_GCLK_ID 26 // Index of Generic Clock +#define TCC1_OTMX 0 // Output Matrix feature implemented +#define TCC1_OW_NUM 4 // Number of Output Waveforms +#define TCC1_PG 1 // Pattern Generation feature implemented +#define TCC1_SIZE 24 +#define TCC1_SWAP 0 // DTI outputs swap feature implemented +#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAMD21_TCC1_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/tcc2.h b/atmel-samd/asf4/samd21/include/instance/tcc2.h new file mode 100644 index 000000000..2b394b352 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/tcc2.h @@ -0,0 +1,100 @@ +/** + * \file + * + * \brief Instance description for TCC2 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_TCC2_INSTANCE_ +#define _SAMD21_TCC2_INSTANCE_ + +/* ========== Register definition for TCC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC2_CTRLA (0x42002800) /**< \brief (TCC2) Control A */ +#define REG_TCC2_CTRLBCLR (0x42002804) /**< \brief (TCC2) Control B Clear */ +#define REG_TCC2_CTRLBSET (0x42002805) /**< \brief (TCC2) Control B Set */ +#define REG_TCC2_SYNCBUSY (0x42002808) /**< \brief (TCC2) Synchronization Busy */ +#define REG_TCC2_FCTRLA (0x4200280C) /**< \brief (TCC2) Recoverable Fault A Configuration */ +#define REG_TCC2_FCTRLB (0x42002810) /**< \brief (TCC2) Recoverable Fault B Configuration */ +#define REG_TCC2_DRVCTRL (0x42002818) /**< \brief (TCC2) Driver Control */ +#define REG_TCC2_DBGCTRL (0x4200281E) /**< \brief (TCC2) Debug Control */ +#define REG_TCC2_EVCTRL (0x42002820) /**< \brief (TCC2) Event Control */ +#define REG_TCC2_INTENCLR (0x42002824) /**< \brief (TCC2) Interrupt Enable Clear */ +#define REG_TCC2_INTENSET (0x42002828) /**< \brief (TCC2) Interrupt Enable Set */ +#define REG_TCC2_INTFLAG (0x4200282C) /**< \brief (TCC2) Interrupt Flag Status and Clear */ +#define REG_TCC2_STATUS (0x42002830) /**< \brief (TCC2) Status */ +#define REG_TCC2_COUNT (0x42002834) /**< \brief (TCC2) Count */ +#define REG_TCC2_WAVE (0x4200283C) /**< \brief (TCC2) Waveform Control */ +#define REG_TCC2_PER (0x42002840) /**< \brief (TCC2) Period */ +#define REG_TCC2_CC0 (0x42002844) /**< \brief (TCC2) Compare and Capture 0 */ +#define REG_TCC2_CC1 (0x42002848) /**< \brief (TCC2) Compare and Capture 1 */ +#define REG_TCC2_WAVEB (0x42002868) /**< \brief (TCC2) Waveform Control Buffer */ +#define REG_TCC2_PERB (0x4200286C) /**< \brief (TCC2) Period Buffer */ +#define REG_TCC2_CCB0 (0x42002870) /**< \brief (TCC2) Compare and Capture Buffer 0 */ +#define REG_TCC2_CCB1 (0x42002874) /**< \brief (TCC2) Compare and Capture Buffer 1 */ +#else +#define REG_TCC2_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TCC2) Control A */ +#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TCC2) Control B Clear */ +#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TCC2) Control B Set */ +#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808UL) /**< \brief (TCC2) Synchronization Busy */ +#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */ +#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810UL) /**< \brief (TCC2) Recoverable Fault B Configuration */ +#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818UL) /**< \brief (TCC2) Driver Control */ +#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EUL) /**< \brief (TCC2) Debug Control */ +#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820UL) /**< \brief (TCC2) Event Control */ +#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824UL) /**< \brief (TCC2) Interrupt Enable Clear */ +#define REG_TCC2_INTENSET (*(RwReg *)0x42002828UL) /**< \brief (TCC2) Interrupt Enable Set */ +#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */ +#define REG_TCC2_STATUS (*(RwReg *)0x42002830UL) /**< \brief (TCC2) Status */ +#define REG_TCC2_COUNT (*(RwReg *)0x42002834UL) /**< \brief (TCC2) Count */ +#define REG_TCC2_WAVE (*(RwReg *)0x4200283CUL) /**< \brief (TCC2) Waveform Control */ +#define REG_TCC2_PER (*(RwReg *)0x42002840UL) /**< \brief (TCC2) Period */ +#define REG_TCC2_CC0 (*(RwReg *)0x42002844UL) /**< \brief (TCC2) Compare and Capture 0 */ +#define REG_TCC2_CC1 (*(RwReg *)0x42002848UL) /**< \brief (TCC2) Compare and Capture 1 */ +#define REG_TCC2_WAVEB (*(RwReg *)0x42002868UL) /**< \brief (TCC2) Waveform Control Buffer */ +#define REG_TCC2_PERB (*(RwReg *)0x4200286CUL) /**< \brief (TCC2) Period Buffer */ +#define REG_TCC2_CCB0 (*(RwReg *)0x42002870UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */ +#define REG_TCC2_CCB1 (*(RwReg *)0x42002874UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC2 peripheral ========== */ +#define TCC2_CC_NUM 2 // Number of Compare/Capture units +#define TCC2_DITHERING 0 // Dithering feature implemented +#define TCC2_DMAC_ID_MC_0 22 +#define TCC2_DMAC_ID_MC_1 23 +#define TCC2_DMAC_ID_MC_LSB 22 +#define TCC2_DMAC_ID_MC_MSB 23 +#define TCC2_DMAC_ID_MC_SIZE 2 +#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger +#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented +#define TCC2_EXT 0 // Coding of implemented extended features +#define TCC2_GCLK_ID 27 // Index of Generic Clock +#define TCC2_OTMX 0 // Output Matrix feature implemented +#define TCC2_OW_NUM 2 // Number of Output Waveforms +#define TCC2_PG 0 // Pattern Generation feature implemented +#define TCC2_SIZE 16 +#define TCC2_SWAP 0 // DTI outputs swap feature implemented +#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAMD21_TCC2_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/usb.h b/atmel-samd/asf4/samd21/include/instance/usb.h new file mode 100644 index 000000000..357e8c9a4 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/usb.h @@ -0,0 +1,329 @@ +/** + * \file + * + * \brief Instance description for USB + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_USB_INSTANCE_ +#define _SAMD21_USB_INSTANCE_ + +/* ========== Register definition for USB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USB_CTRLA (0x41005000) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (0x41005002) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (0x41005003) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (0x4100500D) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (0x41005024) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (0x41005028) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (0x41005008) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (0x4100500A) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (0x4100500C) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (0x41005010) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (0x41005014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (0x41005018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (0x4100501C) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (0x41005020) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (0x41005008) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (0x4100500A) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (0x4100500C) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (0x41005010) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (0x41005012) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (0x41005014) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (0x41005018) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (0x4100501C) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (0x41005020) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (0x41005100) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (0x41005120) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (0x41005140) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (0x41005160) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (0x41005180) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#else +#define REG_USB_CTRLA (*(RwReg8 *)0x41005000UL) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002UL) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003UL) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DUL) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (*(RwReg *)0x41005024UL) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (*(RwReg16*)0x41005028UL) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008UL) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CUL) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010UL) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008UL) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CUL) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010UL) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012UL) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014UL) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018UL) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CUL) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020UL) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100UL) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120UL) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140UL) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160UL) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180UL) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for USB peripheral ========== */ +#define USB_EPT_NBR 8 // Number of USB end points (obsolete) +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 6 // Index of Generic Clock +#define USB_PIPE_NUM 8 // Number of USB pipes + +#endif /* _SAMD21_USB_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd21/include/instance/wdt.h b/atmel-samd/asf4/samd21/include/instance/wdt.h new file mode 100644 index 000000000..33110ef6f --- /dev/null +++ b/atmel-samd/asf4/samd21/include/instance/wdt.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_WDT_INSTANCE_ +#define _SAMD21_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRL (0x40001000) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40001001) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40001002) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40001004) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40001006) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_STATUS (0x40001007) /**< \brief (WDT) Status */ +#define REG_WDT_CLEAR (0x40001008) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRL (*(RwReg8 *)0x40001000UL) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001UL) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002UL) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004UL) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_STATUS (*(RoReg8 *)0x40001007UL) /**< \brief (WDT) Status */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008UL) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for WDT peripheral ========== */ +#define WDT_GCLK_ID 3 // Index of Generic Clock + +#endif /* _SAMD21_WDT_INSTANCE_ */ |