Merge pull request #1 from adafruit/main

merge from adafruit

115 files changed, 15850 insertions, 289 deletions

diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile
index 489f3a7af..dc7b4e4c8 100644
--- a/ports/atmel-samd/Makefile
+++ b/ports/atmel-samd/Makefile
@@ -99,6 +99,13 @@ OPTIMIZATION_FLAGS ?= -O2
 CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD51 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024
 endif
 
+ifeq ($(CHIP_FAMILY), same51)
+PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x
+OPTIMIZATION_FLAGS ?= -O2
+# TinyUSB defines
+CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAME5X -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=256 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=256 -DCFG_TUD_MSC_BUFSIZE=1024
+endif
+
 ifeq ($(CHIP_FAMILY), same54)
 PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x
 OPTIMIZATION_FLAGS ?= -O2
@@ -177,10 +184,20 @@ CFLAGS += \
 	-mfpu=fpv4-sp-d16 \
 	-DSAM_D5X_E5X -DSAME54
 endif
+ifeq ($(CHIP_FAMILY), same51)
+CFLAGS += \
+	-mthumb \
+	-mabi=aapcs-linux \
+	-mcpu=cortex-m4 \
+	-mfloat-abi=hard \
+	-mfpu=fpv4-sp-d16 \
+	-DSAM_D5X_E5X -DSAME51
+endif
 
 
 
 LDFLAGS = $(CFLAGS) -nostartfiles -Wl,-nostdlib -Wl,-T,$(GENERATED_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs
+LDFLAGS += -flto=$(shell $(NPROC))
 LIBS := -lgcc -lc
 
 # Use toolchain libm if we're not using our own.
@@ -197,6 +214,9 @@ BOOTLOADER_SIZE := 0x4000
 else ifeq ($(CHIP_FAMILY), same54)
 LDFLAGS += -mthumb -mcpu=cortex-m4
 BOOTLOADER_SIZE := 0x4000
+else ifeq ($(CHIP_FAMILY), same51)
+LDFLAGS += -mthumb -mcpu=cortex-m4
+BOOTLOADER_SIZE := 0x4000
 endif
 
 SRC_ASF := \
@@ -241,7 +261,16 @@ SRC_ASF += \
 
 else ifeq ($(CHIP_FAMILY), same54)
 SRC_ASF += \
-    hal/src/hal_rand_sync.c \
+	hal/src/hal_rand_sync.c \
+	hpl/core/hpl_core_m4.c \
+	hpl/mclk/hpl_mclk.c \
+	hpl/osc32kctrl/hpl_osc32kctrl.c \
+	hpl/oscctrl/hpl_oscctrl.c \
+	hpl/trng/hpl_trng.c \
+
+else ifeq ($(CHIP_FAMILY), same51)
+SRC_ASF += \
+	hal/src/hal_rand_sync.c \
 	hpl/core/hpl_core_m4.c \
 	hpl/mclk/hpl_mclk.c \
 	hpl/osc32kctrl/hpl_osc32kctrl.c \
@@ -255,11 +284,9 @@ SRC_ASF += \
 	hal/src/hal_mci_sync.c \
 	hpl/sdhc/hpl_sdhc.c \
 
-$(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sdhc/hpl_sdhc.o: CFLAGS += -Wno-cast-align
+$(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sdhc/hpl_sdhc.o: CFLAGS += -Wno-cast-align -Wno-implicit-fallthrough
 endif
 
-$(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sercom/hpl_sercom.o: CFLAGS += -Wno-maybe-uninitialized
-
 SRC_ASF := $(addprefix asf4/$(CHIP_FAMILY)/, $(SRC_ASF))
 
 SRC_C += \
@@ -367,6 +394,10 @@ SRC_QSTR += $(HEADER_BUILD)/sdiodata.h
 $(HEADER_BUILD)/sdiodata.h: tools/mksdiodata.py | $(HEADER_BUILD)
 	$(Q)$(PYTHON3) $< > $@
 
+SRC_QSTR += $(HEADER_BUILD)/candata.h
+$(HEADER_BUILD)/candata.h: tools/mkcandata.py | $(HEADER_BUILD)
+	$(Q)$(PYTHON3) $< > $@
+
 SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
 # Sources that only hold QSTRs after pre-processing.
 SRC_QSTR_PREPROCESSOR += peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c
diff --git a/ports/atmel-samd/asf4 b/ports/atmel-samd/asf4
-Subproject 35a1525796c7ef8a3893d90befdad2f267fca20
+Subproject 84f56af13292d8f32c40acbd949bde698ddd450
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_adc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_adc_config.h
new file mode 100644
index 000000000..13d815102
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_adc_config.h
@@ -0,0 +1,303 @@
+/* Auto-generated config file hpl_adc_config.h */
+#ifndef HPL_ADC_CONFIG_H
+#define HPL_ADC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
+// <id> adc_resolution
+#ifndef CONF_ADC_0_RESSEL
+#define CONF_ADC_0_RESSEL 0x0
+#endif
+
+// <o> Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>VDDANA
+// <0x4=>External reference A
+// <0x5=>External reference B
+// <0x6=>External reference C
+// <i> Select the reference for the ADC (REFSEL)
+// <id> adc_reference
+#ifndef CONF_ADC_0_REFSEL
+#define CONF_ADC_0_REFSEL 0x0
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// <id> adc_prescaler
+#ifndef CONF_ADC_0_PRESCALER
+#define CONF_ADC_0_PRESCALER 0x3
+#endif
+
+// <q> Free Running Mode
+// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// <id> adc_freerunning_mode
+#ifndef CONF_ADC_0_FREERUN
+#define CONF_ADC_0_FREERUN 0
+#endif
+
+// <q> Differential Mode
+// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// <id> adc_differential_mode
+#ifndef CONF_ADC_0_DIFFMODE
+#define CONF_ADC_0_DIFFMODE 0
+#endif
+
+// <o> Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x18=>1/4 scaled core supply
+// <0x19=>1/4 Scaled VBAT Supply
+// <0x1A=>1/4 scaled I/O supply
+// <0x1B=>Bandgap voltage
+// <0x1C=>Temperature reference (PTAT)
+// <0x1D=>Temperature reference (CTAT)
+// <0x1E=>DAC Output
+// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// <id> adc_pinmux_positive
+#ifndef CONF_ADC_0_MUXPOS
+#define CONF_ADC_0_MUXPOS 0x0
+#endif
+
+// <o> Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// <0x19=>I/O ground
+// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// <id> adc_pinmux_negative
+#ifndef CONF_ADC_0_MUXNEG
+#define CONF_ADC_0_MUXNEG 0x0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> adc_advanced_settings
+#ifndef CONF_ADC_0_ADVANCED
+#define CONF_ADC_0_ADVANCED 0
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// <id> adc_arch_runstdby
+#ifndef CONF_ADC_0_RUNSTDBY
+#define CONF_ADC_0_RUNSTDBY 0
+#endif
+
+// <q>Debug Run
+// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// <id> adc_arch_dbgrun
+#ifndef CONF_ADC_0_DBGRUN
+#define CONF_ADC_0_DBGRUN 0
+#endif
+
+// <q> On Demand Control
+// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// <id> adc_arch_ondemand
+#ifndef CONF_ADC_0_ONDEMAND
+#define CONF_ADC_0_ONDEMAND 0
+#endif
+
+// <q> Left-Adjusted Result
+// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// <id> adc_arch_leftadj
+#ifndef CONF_ADC_0_LEFTADJ
+#define CONF_ADC_0_LEFTADJ 0
+#endif
+
+// <q> Reference Buffer Offset Compensation Enable
+// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// <id> adc_arch_refcomp
+#ifndef CONF_ADC_0_REFCOMP
+#define CONF_ADC_0_REFCOMP 0
+#endif
+
+// <q>Comparator Offset Compensation Enable
+// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// <id> adc_arch_offcomp
+#ifndef CONF_ADC_0_OFFCOMP
+#define CONF_ADC_0_OFFCOMP 0
+#endif
+
+// <q> Digital Correction Logic Enabled
+// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// <id> adc_arch_corren
+#ifndef CONF_ADC_0_CORREN
+#define CONF_ADC_0_CORREN 0
+#endif
+
+// <o> Offset Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// <id> adc_arch_offsetcorr
+#ifndef CONF_ADC_0_OFFSETCORR
+#define CONF_ADC_0_OFFSETCORR 0
+#endif
+
+// <o> Gain Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// <id> adc_arch_gaincorr
+#ifndef CONF_ADC_0_GAINCORR
+#define CONF_ADC_0_GAINCORR 0
+#endif
+
+// <o> Adjusting Result / Division Coefficient <0-7>
+// <i> These bits define the division coefficient in 2n steps. (ADJRES)
+// <id> adc_arch_adjres
+#ifndef CONF_ADC_0_ADJRES
+#define CONF_ADC_0_ADJRES 0x0
+#endif
+
+// <o.0..10> Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// <id> adc_arch_samplenum
+#ifndef CONF_ADC_0_SAMPLENUM
+#define CONF_ADC_0_SAMPLENUM 0x0
+#endif
+
+// <o> Sampling Time Length <0-63>
+// <i> These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// <id> adc_arch_samplen
+#ifndef CONF_ADC_0_SAMPLEN
+#define CONF_ADC_0_SAMPLEN 0
+#endif
+
+// <o> Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// <i> These bits enable and define the window monitor mode. (WINMODE)
+// <id> adc_arch_winmode
+#ifndef CONF_ADC_0_WINMODE
+#define CONF_ADC_0_WINMODE 0x0
+#endif
+
+// <o> Window Monitor Lower Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// <id> adc_arch_winlt
+#ifndef CONF_ADC_0_WINLT
+#define CONF_ADC_0_WINLT 0
+#endif
+
+// <o> Window Monitor Upper Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// <id> adc_arch_winut
+#ifndef CONF_ADC_0_WINUT
+#define CONF_ADC_0_WINUT 0
+#endif
+
+// <o> Bitmask for positive input sequence <0-4294967295>
+// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// <id> adc_arch_seqen
+#ifndef CONF_ADC_0_SEQEN
+#define CONF_ADC_0_SEQEN 0x0
+#endif
+
+// </e>
+
+// <e> Event Control
+// <id> adc_arch_event_settings
+#ifndef CONF_ADC_0_EVENT_CONTROL
+#define CONF_ADC_0_EVENT_CONTROL 0
+#endif
+
+// <q> Window Monitor Event Out
+// <i> Enables event output on window event (WINMONEO)
+// <id> adc_arch_winmoneo
+#ifndef CONF_ADC_0_WINMONEO
+#define CONF_ADC_0_WINMONEO 0
+#endif
+
+// <q> Result Ready Event Out
+// <i> Enables event output on result ready event (RESRDEO)
+// <id> adc_arch_resrdyeo
+#ifndef CONF_ADC_0_RESRDYEO
+#define CONF_ADC_0_RESRDYEO 0
+#endif
+
+// <q> Invert flush Event Signal
+// <i> Invert the flush event input signal (FLUSHINV)
+// <id> adc_arch_flushinv
+#ifndef CONF_ADC_0_FLUSHINV
+#define CONF_ADC_0_FLUSHINV 0
+#endif
+
+// <q> Trigger Flush On Event
+// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
+// <id> adc_arch_flushei
+#ifndef CONF_ADC_0_FLUSHEI
+#define CONF_ADC_0_FLUSHEI 0
+#endif
+
+// <q> Invert Start Conversion Event Signal
+// <i> Invert the start conversion event input signal (STARTINV)
+// <id> adc_arch_startinv
+#ifndef CONF_ADC_0_STARTINV
+#define CONF_ADC_0_STARTINV 0
+#endif
+
+// <q> Trigger Conversion On Event
+// <i> Trigger a conversion on event. (STARTEI)
+// <id> adc_arch_startei
+#ifndef CONF_ADC_0_STARTEI
+#define CONF_ADC_0_STARTEI 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_ADC_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_dac_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_dac_config.h
new file mode 100644
index 000000000..c46f99b7d
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_dac_config.h
@@ -0,0 +1,169 @@
+/* Auto-generated config file hpl_dac_config.h */
+#ifndef HPL_DAC_CONFIG_H
+#define HPL_DAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic configuration
+// <o> Reference Selection
+// <0x00=> Unbuffered external voltage reference
+// <0x01=> Voltage supply
+// <0x02=> Buffered external voltage reference
+// <0x03=> Internal bandgap reference
+// <id> dac_arch_refsel
+#ifndef CONF_DAC_REFSEL
+#define CONF_DAC_REFSEL 0
+#endif
+
+// <q> Differential mode
+// <i> Indicates whether the differential mode is enabled or not
+// <id> dac_arch_diff
+#ifndef CONF_DAC_DIFF
+#define CONF_DAC_DIFF 0
+#endif
+// </h>
+
+// <e> Advanced Configuration
+// <id> dac_advanced_settings
+#ifndef CONF_DAC_ADVANCED_CONFIG
+#define CONF_DAC_ADVANCED_CONFIG 0
+#endif
+
+// <q> Debug Run
+// <i> Indicate whether running when CPU is halted
+// <id> adc_arch_dbgrun
+#ifndef CONF_DAC_DBGRUN
+#define CONF_DAC_DBGRUN 1
+#endif
+
+// <h> Channel 0 configuration
+// <q> Left Adjusted Data
+// <i> Indicate how the data is adjusted in the Data and Data Buffer register
+// <id> dac0_arch_leftadj
+#ifndef CONF_DAC0_LEFTADJ
+#define CONF_DAC0_LEFTADJ 1
+#endif
+
+// <o> Current control
+// <0=> GCLK_DAC <= 1.2MHz (100kSPS)
+// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS)
+// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS)
+// <i> This defines the current in output buffer according to conversion rate
+// <id> dac0_arch_cctrl
+#ifndef CONF_DAC0_CCTRL
+#define CONF_DAC0_CCTRL 0
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the DAC channel will continue running in standby sleep mode or not
+// <id> dac0_arch_runstdby
+#ifndef CONF_DAC0_RUNSTDBY
+#define CONF_DAC0_RUNSTDBY 0
+#endif
+
+// <q> Dithering Mode
+// <i> Indicate whether dithering mode is enabled
+// <id> dac0_arch_ditrher
+#ifndef CONF_DAC0_DITHER
+#define CONF_DAC0_DITHER 0
+#endif
+
+// <o> Refresh period <0x00-0xFF>
+// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us
+// <id> dac0_arch_refresh
+#ifndef CONF_DAC0_REFRESH
+#define CONF_DAC0_REFRESH 2
+#endif
+// </h>
+// <h> Channel 1 configuration
+// <q> Left Adjusted Data
+// <i> Indicate how the data is adjusted in the Data and Data Buffer register
+// <id> dac1_arch_leftadj
+#ifndef CONF_DAC1_LEFTADJ
+#define CONF_DAC1_LEFTADJ 1
+#endif
+
+// <o> Current control
+// <0=> GCLK_DAC <= 1.2MHz (100kSPS)
+// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS)
+// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS)
+// <i> This defines the current in output buffer according to conversion rate
+// <id> dac1_arch_cctrl
+#ifndef CONF_DAC1_CCTRL
+#define CONF_DAC1_CCTRL 0
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the DAC channel will continue running in standby sleep mode or not
+// <id> dac1_arch_runstdby
+#ifndef CONF_DAC1_RUNSTDBY
+#define CONF_DAC1_RUNSTDBY 0
+#endif
+
+// <q> Dithering Mode
+// <i> Indicate whether dithering mode is enabled
+// <id> dac1_arch_ditrher
+#ifndef CONF_DAC1_DITHER
+#define CONF_DAC1_DITHER 0
+#endif
+
+// <o> Refresh period <0x00-0xFF>
+// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us
+// <id> dac1_arch_refresh
+#ifndef CONF_DAC1_REFRESH
+#define CONF_DAC1_REFRESH 2
+#endif
+// </h>
+
+// <h> Event configuration
+// <o> Inversion of DAC 0 event
+// <0=> Detection on rising edge pf the input event
+// <1=> Detection on falling edge pf the input event
+// <i> This defines the edge detection of the input event
+// <id> dac_arch_invei0
+#ifndef CONF_DAC_INVEI0
+#define CONF_DAC_INVEI0 0
+#endif
+
+// <q> Data Buffer of DAC 0 Empty Event Output
+// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not
+// <id> dac_arch_emptyeo_0
+#ifndef CONF_DAC_EMPTYEO0
+#define CONF_DAC_EMPTYEO0 0
+#endif
+
+// <q> Start Conversion Event Input DAC 0
+// <i> Indicate whether Start input event is enabled
+// <id> dac_arch_startei_0
+#ifndef CONF_DAC_STARTEI0
+#define CONF_DAC_STARTEI0 0
+#endif
+// <o> Inversion of DAC 1 event
+// <0=> Detection on rising edge pf the input event
+// <1=> Detection on falling edge pf the input event
+// <i> This defines the edge detection of the input event
+// <id> dac_arch_invei1
+#ifndef CONF_DAC_INVEI1
+#define CONF_DAC_INVEI1 0
+#endif
+
+// <q> Data Buffer of DAC 1 Empty Event Output
+// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not
+// <id> dac_arch_emptyeo_1
+#ifndef CONF_DAC_EMPTYEO1
+#define CONF_DAC_EMPTYEO1 0
+#endif
+
+// <q> Start Conversion Event Input DAC 1
+// <i> Indicate whether Start input event is enabled
+// <id> dac_arch_startei_1
+#ifndef CONF_DAC_STARTEI1
+#define CONF_DAC_STARTEI1 0
+#endif
+
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_DAC_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_dmac_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_dmac_config.h
new file mode 100644
index 000000000..90499fc27
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_dmac_config.h
@@ -0,0 +1,7277 @@
+/* Auto-generated config file hpl_dmac_config.h */
+#ifndef HPL_DMAC_CONFIG_H
+#define HPL_DMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> DMAC enable
+// <i> Indicates whether dmac is enabled or not
+// <id> dmac_enable
+#ifndef CONF_DMAC_ENABLE
+#define CONF_DMAC_ENABLE 0
+#endif
+
+// <q> Priority Level 0
+// <i> Indicates whether Priority Level 0 is enabled or not
+// <id> dmac_lvlen0
+#ifndef CONF_DMAC_LVLEN0
+#define CONF_DMAC_LVLEN0 1
+#endif
+
+// <o> Level 0 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 0
+// <1=> Round-robin arbitration scheme for channel with priority 0
+// <i> Defines Level 0 Arbitration for DMA channels
+// <id> dmac_rrlvlen0
+#ifndef CONF_DMAC_RRLVLEN0
+#define CONF_DMAC_RRLVLEN0 0
+#endif
+
+// <o> Level 0 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri0
+#ifndef CONF_DMAC_LVLPRI0
+#define CONF_DMAC_LVLPRI0 0
+#endif
+// <q> Priority Level 1
+// <i> Indicates whether Priority Level 1 is enabled or not
+// <id> dmac_lvlen1
+#ifndef CONF_DMAC_LVLEN1
+#define CONF_DMAC_LVLEN1 1
+#endif
+
+// <o> Level 1 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 1
+// <1=> Round-robin arbitration scheme for channel with priority 1
+// <i> Defines Level 1 Arbitration for DMA channels
+// <id> dmac_rrlvlen1
+#ifndef CONF_DMAC_RRLVLEN1
+#define CONF_DMAC_RRLVLEN1 0
+#endif
+
+// <o> Level 1 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri1
+#ifndef CONF_DMAC_LVLPRI1
+#define CONF_DMAC_LVLPRI1 0
+#endif
+// <q> Priority Level 2
+// <i> Indicates whether Priority Level 2 is enabled or not
+// <id> dmac_lvlen2
+#ifndef CONF_DMAC_LVLEN2
+#define CONF_DMAC_LVLEN2 1
+#endif
+
+// <o> Level 2 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 2
+// <1=> Round-robin arbitration scheme for channel with priority 2
+// <i> Defines Level 2 Arbitration for DMA channels
+// <id> dmac_rrlvlen2
+#ifndef CONF_DMAC_RRLVLEN2
+#define CONF_DMAC_RRLVLEN2 0
+#endif
+
+// <o> Level 2 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri2
+#ifndef CONF_DMAC_LVLPRI2
+#define CONF_DMAC_LVLPRI2 0
+#endif
+// <q> Priority Level 3
+// <i> Indicates whether Priority Level 3 is enabled or not
+// <id> dmac_lvlen3
+#ifndef CONF_DMAC_LVLEN3
+#define CONF_DMAC_LVLEN3 1
+#endif
+
+// <o> Level 3 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 3
+// <1=> Round-robin arbitration scheme for channel with priority 3
+// <i> Defines Level 3 Arbitration for DMA channels
+// <id> dmac_rrlvlen3
+#ifndef CONF_DMAC_RRLVLEN3
+#define CONF_DMAC_RRLVLEN3 0
+#endif
+
+// <o> Level 3 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri3
+#ifndef CONF_DMAC_LVLPRI3
+#define CONF_DMAC_LVLPRI3 0
+#endif
+// <q> Debug Run
+// <i> Indicates whether Debug Run is enabled or not
+// <id> dmac_dbgrun
+#ifndef CONF_DMAC_DBGRUN
+#define CONF_DMAC_DBGRUN 0
+#endif
+
+// <e> Channel 0 settings
+// <id> dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 0 is running in standby mode or not
+// <id> dmac_runstdby_0
+#ifndef CONF_DMAC_RUNSTDBY_0
+#define CONF_DMAC_RUNSTDBY_0 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_0
+#ifndef CONF_DMAC_TRIGACT_0
+#define CONF_DMAC_TRIGACT_0 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_0
+#ifndef CONF_DMAC_LVL_0
+#define CONF_DMAC_LVL_0 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_0
+#ifndef CONF_DMAC_EVOE_0
+#define CONF_DMAC_EVOE_0 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_0
+#ifndef CONF_DMAC_EVIE_0
+#define CONF_DMAC_EVIE_0 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_0
+#ifndef CONF_DMAC_EVACT_0
+#define CONF_DMAC_EVACT_0 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_0
+#ifndef CONF_DMAC_STEPSIZE_0
+#define CONF_DMAC_STEPSIZE_0 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_0
+#ifndef CONF_DMAC_STEPSEL_0
+#define CONF_DMAC_STEPSEL_0 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_0
+#ifndef CONF_DMAC_SRCINC_0
+#define CONF_DMAC_SRCINC_0 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_0
+#ifndef CONF_DMAC_DSTINC_0
+#define CONF_DMAC_DSTINC_0 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_0
+#ifndef CONF_DMAC_BEATSIZE_0
+#define CONF_DMAC_BEATSIZE_0 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_0
+#ifndef CONF_DMAC_BLOCKACT_0
+#define CONF_DMAC_BLOCKACT_0 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_0
+#ifndef CONF_DMAC_EVOSEL_0
+#define CONF_DMAC_EVOSEL_0 0
+#endif
+// </e>
+
+// <e> Channel 1 settings
+// <id> dmac_channel_1_settings
+#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
+#define CONF_DMAC_CHANNEL_1_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 1 is running in standby mode or not
+// <id> dmac_runstdby_1
+#ifndef CONF_DMAC_RUNSTDBY_1
+#define CONF_DMAC_RUNSTDBY_1 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_1
+#ifndef CONF_DMAC_TRIGACT_1
+#define CONF_DMAC_TRIGACT_1 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_1
+#ifndef CONF_DMAC_TRIGSRC_1
+#define CONF_DMAC_TRIGSRC_1 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_1
+#ifndef CONF_DMAC_LVL_1
+#define CONF_DMAC_LVL_1 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_1
+#ifndef CONF_DMAC_EVOE_1
+#define CONF_DMAC_EVOE_1 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_1
+#ifndef CONF_DMAC_EVIE_1
+#define CONF_DMAC_EVIE_1 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_1
+#ifndef CONF_DMAC_EVACT_1
+#define CONF_DMAC_EVACT_1 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_1
+#ifndef CONF_DMAC_STEPSIZE_1
+#define CONF_DMAC_STEPSIZE_1 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_1
+#ifndef CONF_DMAC_STEPSEL_1
+#define CONF_DMAC_STEPSEL_1 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_1
+#ifndef CONF_DMAC_SRCINC_1
+#define CONF_DMAC_SRCINC_1 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_1
+#ifndef CONF_DMAC_DSTINC_1
+#define CONF_DMAC_DSTINC_1 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_1
+#ifndef CONF_DMAC_BEATSIZE_1
+#define CONF_DMAC_BEATSIZE_1 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_1
+#ifndef CONF_DMAC_BLOCKACT_1
+#define CONF_DMAC_BLOCKACT_1 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_1
+#ifndef CONF_DMAC_EVOSEL_1
+#define CONF_DMAC_EVOSEL_1 0
+#endif
+// </e>
+
+// <e> Channel 2 settings
+// <id> dmac_channel_2_settings
+#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
+#define CONF_DMAC_CHANNEL_2_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 2 is running in standby mode or not
+// <id> dmac_runstdby_2
+#ifndef CONF_DMAC_RUNSTDBY_2
+#define CONF_DMAC_RUNSTDBY_2 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_2
+#ifndef CONF_DMAC_TRIGACT_2
+#define CONF_DMAC_TRIGACT_2 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_2
+#ifndef CONF_DMAC_TRIGSRC_2
+#define CONF_DMAC_TRIGSRC_2 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_2
+#ifndef CONF_DMAC_LVL_2
+#define CONF_DMAC_LVL_2 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_2
+#ifndef CONF_DMAC_EVOE_2
+#define CONF_DMAC_EVOE_2 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_2
+#ifndef CONF_DMAC_EVIE_2
+#define CONF_DMAC_EVIE_2 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_2
+#ifndef CONF_DMAC_EVACT_2
+#define CONF_DMAC_EVACT_2 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_2
+#ifndef CONF_DMAC_STEPSIZE_2
+#define CONF_DMAC_STEPSIZE_2 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_2
+#ifndef CONF_DMAC_STEPSEL_2
+#define CONF_DMAC_STEPSEL_2 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_2
+#ifndef CONF_DMAC_SRCINC_2
+#define CONF_DMAC_SRCINC_2 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_2
+#ifndef CONF_DMAC_DSTINC_2
+#define CONF_DMAC_DSTINC_2 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_2
+#ifndef CONF_DMAC_BEATSIZE_2
+#define CONF_DMAC_BEATSIZE_2 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_2
+#ifndef CONF_DMAC_BLOCKACT_2
+#define CONF_DMAC_BLOCKACT_2 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_2
+#ifndef CONF_DMAC_EVOSEL_2
+#define CONF_DMAC_EVOSEL_2 0
+#endif
+// </e>
+
+// <e> Channel 3 settings
+// <id> dmac_channel_3_settings
+#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
+#define CONF_DMAC_CHANNEL_3_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 3 is running in standby mode or not
+// <id> dmac_runstdby_3
+#ifndef CONF_DMAC_RUNSTDBY_3
+#define CONF_DMAC_RUNSTDBY_3 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_3
+#ifndef CONF_DMAC_TRIGACT_3
+#define CONF_DMAC_TRIGACT_3 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_3
+#ifndef CONF_DMAC_TRIGSRC_3
+#define CONF_DMAC_TRIGSRC_3 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_3
+#ifndef CONF_DMAC_LVL_3
+#define CONF_DMAC_LVL_3 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_3
+#ifndef CONF_DMAC_EVOE_3
+#define CONF_DMAC_EVOE_3 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_3
+#ifndef CONF_DMAC_EVIE_3
+#define CONF_DMAC_EVIE_3 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_3
+#ifndef CONF_DMAC_EVACT_3
+#define CONF_DMAC_EVACT_3 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_3
+#ifndef CONF_DMAC_STEPSIZE_3
+#define CONF_DMAC_STEPSIZE_3 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_3
+#ifndef CONF_DMAC_STEPSEL_3
+#define CONF_DMAC_STEPSEL_3 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_3
+#ifndef CONF_DMAC_SRCINC_3
+#define CONF_DMAC_SRCINC_3 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_3
+#ifndef CONF_DMAC_DSTINC_3
+#define CONF_DMAC_DSTINC_3 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_3
+#ifndef CONF_DMAC_BEATSIZE_3
+#define CONF_DMAC_BEATSIZE_3 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_3
+#ifndef CONF_DMAC_BLOCKACT_3
+#define CONF_DMAC_BLOCKACT_3 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_3
+#ifndef CONF_DMAC_EVOSEL_3
+#define CONF_DMAC_EVOSEL_3 0
+#endif
+// </e>
+
+// <e> Channel 4 settings
+// <id> dmac_channel_4_settings
+#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
+#define CONF_DMAC_CHANNEL_4_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 4 is running in standby mode or not
+// <id> dmac_runstdby_4
+#ifndef CONF_DMAC_RUNSTDBY_4
+#define CONF_DMAC_RUNSTDBY_4 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_4
+#ifndef CONF_DMAC_TRIGACT_4
+#define CONF_DMAC_TRIGACT_4 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_4
+#ifndef CONF_DMAC_TRIGSRC_4
+#define CONF_DMAC_TRIGSRC_4 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_4
+#ifndef CONF_DMAC_LVL_4
+#define CONF_DMAC_LVL_4 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_4
+#ifndef CONF_DMAC_EVOE_4
+#define CONF_DMAC_EVOE_4 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_4
+#ifndef CONF_DMAC_EVIE_4
+#define CONF_DMAC_EVIE_4 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_4
+#ifndef CONF_DMAC_EVACT_4
+#define CONF_DMAC_EVACT_4 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_4
+#ifndef CONF_DMAC_STEPSIZE_4
+#define CONF_DMAC_STEPSIZE_4 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_4
+#ifndef CONF_DMAC_STEPSEL_4
+#define CONF_DMAC_STEPSEL_4 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_4
+#ifndef CONF_DMAC_SRCINC_4
+#define CONF_DMAC_SRCINC_4 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_4
+#ifndef CONF_DMAC_DSTINC_4
+#define CONF_DMAC_DSTINC_4 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_4
+#ifndef CONF_DMAC_BEATSIZE_4
+#define CONF_DMAC_BEATSIZE_4 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_4
+#ifndef CONF_DMAC_BLOCKACT_4
+#define CONF_DMAC_BLOCKACT_4 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_4
+#ifndef CONF_DMAC_EVOSEL_4
+#define CONF_DMAC_EVOSEL_4 0
+#endif
+// </e>
+
+// <e> Channel 5 settings
+// <id> dmac_channel_5_settings
+#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
+#define CONF_DMAC_CHANNEL_5_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 5 is running in standby mode or not
+// <id> dmac_runstdby_5
+#ifndef CONF_DMAC_RUNSTDBY_5
+#define CONF_DMAC_RUNSTDBY_5 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_5
+#ifndef CONF_DMAC_TRIGACT_5
+#define CONF_DMAC_TRIGACT_5 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_5
+#ifndef CONF_DMAC_TRIGSRC_5
+#define CONF_DMAC_TRIGSRC_5 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_5
+#ifndef CONF_DMAC_LVL_5
+#define CONF_DMAC_LVL_5 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_5
+#ifndef CONF_DMAC_EVOE_5
+#define CONF_DMAC_EVOE_5 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_5
+#ifndef CONF_DMAC_EVIE_5
+#define CONF_DMAC_EVIE_5 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_5
+#ifndef CONF_DMAC_EVACT_5
+#define CONF_DMAC_EVACT_5 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_5
+#ifndef CONF_DMAC_STEPSIZE_5
+#define CONF_DMAC_STEPSIZE_5 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_5
+#ifndef CONF_DMAC_STEPSEL_5
+#define CONF_DMAC_STEPSEL_5 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_5
+#ifndef CONF_DMAC_SRCINC_5
+#define CONF_DMAC_SRCINC_5 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_5
+#ifndef CONF_DMAC_DSTINC_5
+#define CONF_DMAC_DSTINC_5 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_5
+#ifndef CONF_DMAC_BEATSIZE_5
+#define CONF_DMAC_BEATSIZE_5 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_5
+#ifndef CONF_DMAC_BLOCKACT_5
+#define CONF_DMAC_BLOCKACT_5 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_5
+#ifndef CONF_DMAC_EVOSEL_5
+#define CONF_DMAC_EVOSEL_5 0
+#endif
+// </e>
+
+// <e> Channel 6 settings
+// <id> dmac_channel_6_settings
+#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
+#define CONF_DMAC_CHANNEL_6_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 6 is running in standby mode or not
+// <id> dmac_runstdby_6
+#ifndef CONF_DMAC_RUNSTDBY_6
+#define CONF_DMAC_RUNSTDBY_6 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_6
+#ifndef CONF_DMAC_TRIGACT_6
+#define CONF_DMAC_TRIGACT_6 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_6
+#ifndef CONF_DMAC_TRIGSRC_6
+#define CONF_DMAC_TRIGSRC_6 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_6
+#ifndef CONF_DMAC_LVL_6
+#define CONF_DMAC_LVL_6 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_6
+#ifndef CONF_DMAC_EVOE_6
+#define CONF_DMAC_EVOE_6 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_6
+#ifndef CONF_DMAC_EVIE_6
+#define CONF_DMAC_EVIE_6 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_6
+#ifndef CONF_DMAC_EVACT_6
+#define CONF_DMAC_EVACT_6 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_6
+#ifndef CONF_DMAC_STEPSIZE_6
+#define CONF_DMAC_STEPSIZE_6 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_6
+#ifndef CONF_DMAC_STEPSEL_6
+#define CONF_DMAC_STEPSEL_6 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_6
+#ifndef CONF_DMAC_SRCINC_6
+#define CONF_DMAC_SRCINC_6 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_6
+#ifndef CONF_DMAC_DSTINC_6
+#define CONF_DMAC_DSTINC_6 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_6
+#ifndef CONF_DMAC_BEATSIZE_6
+#define CONF_DMAC_BEATSIZE_6 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_6
+#ifndef CONF_DMAC_BLOCKACT_6
+#define CONF_DMAC_BLOCKACT_6 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_6
+#ifndef CONF_DMAC_EVOSEL_6
+#define CONF_DMAC_EVOSEL_6 0
+#endif
+// </e>
+
+// <e> Channel 7 settings
+// <id> dmac_channel_7_settings
+#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
+#define CONF_DMAC_CHANNEL_7_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 7 is running in standby mode or not
+// <id> dmac_runstdby_7
+#ifndef CONF_DMAC_RUNSTDBY_7
+#define CONF_DMAC_RUNSTDBY_7 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_7
+#ifndef CONF_DMAC_TRIGACT_7
+#define CONF_DMAC_TRIGACT_7 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_7
+#ifndef CONF_DMAC_TRIGSRC_7
+#define CONF_DMAC_TRIGSRC_7 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_7
+#ifndef CONF_DMAC_LVL_7
+#define CONF_DMAC_LVL_7 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_7
+#ifndef CONF_DMAC_EVOE_7
+#define CONF_DMAC_EVOE_7 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_7
+#ifndef CONF_DMAC_EVIE_7
+#define CONF_DMAC_EVIE_7 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_7
+#ifndef CONF_DMAC_EVACT_7
+#define CONF_DMAC_EVACT_7 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_7
+#ifndef CONF_DMAC_STEPSIZE_7
+#define CONF_DMAC_STEPSIZE_7 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_7
+#ifndef CONF_DMAC_STEPSEL_7
+#define CONF_DMAC_STEPSEL_7 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_7
+#ifndef CONF_DMAC_SRCINC_7
+#define CONF_DMAC_SRCINC_7 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_7
+#ifndef CONF_DMAC_DSTINC_7
+#define CONF_DMAC_DSTINC_7 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_7
+#ifndef CONF_DMAC_BEATSIZE_7
+#define CONF_DMAC_BEATSIZE_7 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_7
+#ifndef CONF_DMAC_BLOCKACT_7
+#define CONF_DMAC_BLOCKACT_7 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_7
+#ifndef CONF_DMAC_EVOSEL_7
+#define CONF_DMAC_EVOSEL_7 0
+#endif
+// </e>
+
+// <e> Channel 8 settings
+// <id> dmac_channel_8_settings
+#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 8 is running in standby mode or not
+// <id> dmac_runstdby_8
+#ifndef CONF_DMAC_RUNSTDBY_8
+#define CONF_DMAC_RUNSTDBY_8 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_8
+#ifndef CONF_DMAC_TRIGACT_8
+#define CONF_DMAC_TRIGACT_8 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_8
+#ifndef CONF_DMAC_TRIGSRC_8
+#define CONF_DMAC_TRIGSRC_8 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_8
+#ifndef CONF_DMAC_LVL_8
+#define CONF_DMAC_LVL_8 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_8
+#ifndef CONF_DMAC_EVOE_8
+#define CONF_DMAC_EVOE_8 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_8
+#ifndef CONF_DMAC_EVIE_8
+#define CONF_DMAC_EVIE_8 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_8
+#ifndef CONF_DMAC_EVACT_8
+#define CONF_DMAC_EVACT_8 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_8
+#ifndef CONF_DMAC_STEPSIZE_8
+#define CONF_DMAC_STEPSIZE_8 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_8
+#ifndef CONF_DMAC_STEPSEL_8
+#define CONF_DMAC_STEPSEL_8 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_8
+#ifndef CONF_DMAC_SRCINC_8
+#define CONF_DMAC_SRCINC_8 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_8
+#ifndef CONF_DMAC_DSTINC_8
+#define CONF_DMAC_DSTINC_8 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_8
+#ifndef CONF_DMAC_BEATSIZE_8
+#define CONF_DMAC_BEATSIZE_8 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_8
+#ifndef CONF_DMAC_BLOCKACT_8
+#define CONF_DMAC_BLOCKACT_8 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_8
+#ifndef CONF_DMAC_EVOSEL_8
+#define CONF_DMAC_EVOSEL_8 0
+#endif
+// </e>
+
+// <e> Channel 9 settings
+// <id> dmac_channel_9_settings
+#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 9 is running in standby mode or not
+// <id> dmac_runstdby_9
+#ifndef CONF_DMAC_RUNSTDBY_9
+#define CONF_DMAC_RUNSTDBY_9 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_9
+#ifndef CONF_DMAC_TRIGACT_9
+#define CONF_DMAC_TRIGACT_9 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_9
+#ifndef CONF_DMAC_TRIGSRC_9
+#define CONF_DMAC_TRIGSRC_9 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_9
+#ifndef CONF_DMAC_LVL_9
+#define CONF_DMAC_LVL_9 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_9
+#ifndef CONF_DMAC_EVOE_9
+#define CONF_DMAC_EVOE_9 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_9
+#ifndef CONF_DMAC_EVIE_9
+#define CONF_DMAC_EVIE_9 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_9
+#ifndef CONF_DMAC_EVACT_9
+#define CONF_DMAC_EVACT_9 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_9
+#ifndef CONF_DMAC_STEPSIZE_9
+#define CONF_DMAC_STEPSIZE_9 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_9
+#ifndef CONF_DMAC_STEPSEL_9
+#define CONF_DMAC_STEPSEL_9 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_9
+#ifndef CONF_DMAC_SRCINC_9
+#define CONF_DMAC_SRCINC_9 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_9
+#ifndef CONF_DMAC_DSTINC_9
+#define CONF_DMAC_DSTINC_9 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_9
+#ifndef CONF_DMAC_BEATSIZE_9
+#define CONF_DMAC_BEATSIZE_9 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_9
+#ifndef CONF_DMAC_BLOCKACT_9
+#define CONF_DMAC_BLOCKACT_9 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_9
+#ifndef CONF_DMAC_EVOSEL_9
+#define CONF_DMAC_EVOSEL_9 0
+#endif
+// </e>
+
+// <e> Channel 10 settings
+// <id> dmac_channel_10_settings
+#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 10 is running in standby mode or not
+// <id> dmac_runstdby_10
+#ifndef CONF_DMAC_RUNSTDBY_10
+#define CONF_DMAC_RUNSTDBY_10 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_10
+#ifndef CONF_DMAC_TRIGACT_10
+#define CONF_DMAC_TRIGACT_10 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_10
+#ifndef CONF_DMAC_TRIGSRC_10
+#define CONF_DMAC_TRIGSRC_10 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_10
+#ifndef CONF_DMAC_LVL_10
+#define CONF_DMAC_LVL_10 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_10
+#ifndef CONF_DMAC_EVOE_10
+#define CONF_DMAC_EVOE_10 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_10
+#ifndef CONF_DMAC_EVIE_10
+#define CONF_DMAC_EVIE_10 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_10
+#ifndef CONF_DMAC_EVACT_10
+#define CONF_DMAC_EVACT_10 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_10
+#ifndef CONF_DMAC_STEPSIZE_10
+#define CONF_DMAC_STEPSIZE_10 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_10
+#ifndef CONF_DMAC_STEPSEL_10
+#define CONF_DMAC_STEPSEL_10 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_10
+#ifndef CONF_DMAC_SRCINC_10
+#define CONF_DMAC_SRCINC_10 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_10
+#ifndef CONF_DMAC_DSTINC_10
+#define CONF_DMAC_DSTINC_10 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_10
+#ifndef CONF_DMAC_BEATSIZE_10
+#define CONF_DMAC_BEATSIZE_10 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_10
+#ifndef CONF_DMAC_BLOCKACT_10
+#define CONF_DMAC_BLOCKACT_10 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_10
+#ifndef CONF_DMAC_EVOSEL_10
+#define CONF_DMAC_EVOSEL_10 0
+#endif
+// </e>
+
+// <e> Channel 11 settings
+// <id> dmac_channel_11_settings
+#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
+#define CONF_DMAC_CHANNEL_11_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 11 is running in standby mode or not
+// <id> dmac_runstdby_11
+#ifndef CONF_DMAC_RUNSTDBY_11
+#define CONF_DMAC_RUNSTDBY_11 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_11
+#ifndef CONF_DMAC_TRIGACT_11
+#define CONF_DMAC_TRIGACT_11 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_11
+#ifndef CONF_DMAC_TRIGSRC_11
+#define CONF_DMAC_TRIGSRC_11 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_11
+#ifndef CONF_DMAC_LVL_11
+#define CONF_DMAC_LVL_11 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_11
+#ifndef CONF_DMAC_EVOE_11
+#define CONF_DMAC_EVOE_11 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_11
+#ifndef CONF_DMAC_EVIE_11
+#define CONF_DMAC_EVIE_11 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_11
+#ifndef CONF_DMAC_EVACT_11
+#define CONF_DMAC_EVACT_11 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_11
+#ifndef CONF_DMAC_STEPSIZE_11
+#define CONF_DMAC_STEPSIZE_11 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_11
+#ifndef CONF_DMAC_STEPSEL_11
+#define CONF_DMAC_STEPSEL_11 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_11
+#ifndef CONF_DMAC_SRCINC_11
+#define CONF_DMAC_SRCINC_11 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_11
+#ifndef CONF_DMAC_DSTINC_11
+#define CONF_DMAC_DSTINC_11 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_11
+#ifndef CONF_DMAC_BEATSIZE_11
+#define CONF_DMAC_BEATSIZE_11 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_11
+#ifndef CONF_DMAC_BLOCKACT_11
+#define CONF_DMAC_BLOCKACT_11 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_11
+#ifndef CONF_DMAC_EVOSEL_11
+#define CONF_DMAC_EVOSEL_11 0
+#endif
+// </e>
+
+// <e> Channel 12 settings
+// <id> dmac_channel_12_settings
+#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
+#define CONF_DMAC_CHANNEL_12_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 12 is running in standby mode or not
+// <id> dmac_runstdby_12
+#ifndef CONF_DMAC_RUNSTDBY_12
+#define CONF_DMAC_RUNSTDBY_12 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_12
+#ifndef CONF_DMAC_TRIGACT_12
+#define CONF_DMAC_TRIGACT_12 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_12
+#ifndef CONF_DMAC_TRIGSRC_12
+#define CONF_DMAC_TRIGSRC_12 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_12
+#ifndef CONF_DMAC_LVL_12
+#define CONF_DMAC_LVL_12 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_12
+#ifndef CONF_DMAC_EVOE_12
+#define CONF_DMAC_EVOE_12 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_12
+#ifndef CONF_DMAC_EVIE_12
+#define CONF_DMAC_EVIE_12 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_12
+#ifndef CONF_DMAC_EVACT_12
+#define CONF_DMAC_EVACT_12 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_12
+#ifndef CONF_DMAC_STEPSIZE_12
+#define CONF_DMAC_STEPSIZE_12 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_12
+#ifndef CONF_DMAC_STEPSEL_12
+#define CONF_DMAC_STEPSEL_12 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_12
+#ifndef CONF_DMAC_SRCINC_12
+#define CONF_DMAC_SRCINC_12 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_12
+#ifndef CONF_DMAC_DSTINC_12
+#define CONF_DMAC_DSTINC_12 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_12
+#ifndef CONF_DMAC_BEATSIZE_12
+#define CONF_DMAC_BEATSIZE_12 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_12
+#ifndef CONF_DMAC_BLOCKACT_12
+#define CONF_DMAC_BLOCKACT_12 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_12
+#ifndef CONF_DMAC_EVOSEL_12
+#define CONF_DMAC_EVOSEL_12 0
+#endif
+// </e>
+
+// <e> Channel 13 settings
+// <id> dmac_channel_13_settings
+#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
+#define CONF_DMAC_CHANNEL_13_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 13 is running in standby mode or not
+// <id> dmac_runstdby_13
+#ifndef CONF_DMAC_RUNSTDBY_13
+#define CONF_DMAC_RUNSTDBY_13 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_13
+#ifndef CONF_DMAC_TRIGACT_13
+#define CONF_DMAC_TRIGACT_13 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_13
+#ifndef CONF_DMAC_TRIGSRC_13
+#define CONF_DMAC_TRIGSRC_13 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_13
+#ifndef CONF_DMAC_LVL_13
+#define CONF_DMAC_LVL_13 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_13
+#ifndef CONF_DMAC_EVOE_13
+#define CONF_DMAC_EVOE_13 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_13
+#ifndef CONF_DMAC_EVIE_13
+#define CONF_DMAC_EVIE_13 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_13
+#ifndef CONF_DMAC_EVACT_13
+#define CONF_DMAC_EVACT_13 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_13
+#ifndef CONF_DMAC_STEPSIZE_13
+#define CONF_DMAC_STEPSIZE_13 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_13
+#ifndef CONF_DMAC_STEPSEL_13
+#define CONF_DMAC_STEPSEL_13 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_13
+#ifndef CONF_DMAC_SRCINC_13
+#define CONF_DMAC_SRCINC_13 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_13
+#ifndef CONF_DMAC_DSTINC_13
+#define CONF_DMAC_DSTINC_13 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_13
+#ifndef CONF_DMAC_BEATSIZE_13
+#define CONF_DMAC_BEATSIZE_13 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_13
+#ifndef CONF_DMAC_BLOCKACT_13
+#define CONF_DMAC_BLOCKACT_13 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_13
+#ifndef CONF_DMAC_EVOSEL_13
+#define CONF_DMAC_EVOSEL_13 0
+#endif
+// </e>
+
+// <e> Channel 14 settings
+// <id> dmac_channel_14_settings
+#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
+#define CONF_DMAC_CHANNEL_14_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 14 is running in standby mode or not
+// <id> dmac_runstdby_14
+#ifndef CONF_DMAC_RUNSTDBY_14
+#define CONF_DMAC_RUNSTDBY_14 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_14
+#ifndef CONF_DMAC_TRIGACT_14
+#define CONF_DMAC_TRIGACT_14 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_14
+#ifndef CONF_DMAC_TRIGSRC_14
+#define CONF_DMAC_TRIGSRC_14 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_14
+#ifndef CONF_DMAC_LVL_14
+#define CONF_DMAC_LVL_14 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_14
+#ifndef CONF_DMAC_EVOE_14
+#define CONF_DMAC_EVOE_14 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_14
+#ifndef CONF_DMAC_EVIE_14
+#define CONF_DMAC_EVIE_14 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_14
+#ifndef CONF_DMAC_EVACT_14
+#define CONF_DMAC_EVACT_14 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_14
+#ifndef CONF_DMAC_STEPSIZE_14
+#define CONF_DMAC_STEPSIZE_14 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_14
+#ifndef CONF_DMAC_STEPSEL_14
+#define CONF_DMAC_STEPSEL_14 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_14
+#ifndef CONF_DMAC_SRCINC_14
+#define CONF_DMAC_SRCINC_14 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_14
+#ifndef CONF_DMAC_DSTINC_14
+#define CONF_DMAC_DSTINC_14 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_14
+#ifndef CONF_DMAC_BEATSIZE_14
+#define CONF_DMAC_BEATSIZE_14 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_14
+#ifndef CONF_DMAC_BLOCKACT_14
+#define CONF_DMAC_BLOCKACT_14 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_14
+#ifndef CONF_DMAC_EVOSEL_14
+#define CONF_DMAC_EVOSEL_14 0
+#endif
+// </e>
+
+// <e> Channel 15 settings
+// <id> dmac_channel_15_settings
+#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
+#define CONF_DMAC_CHANNEL_15_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 15 is running in standby mode or not
+// <id> dmac_runstdby_15
+#ifndef CONF_DMAC_RUNSTDBY_15
+#define CONF_DMAC_RUNSTDBY_15 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_15
+#ifndef CONF_DMAC_TRIGACT_15
+#define CONF_DMAC_TRIGACT_15 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_15
+#ifndef CONF_DMAC_TRIGSRC_15
+#define CONF_DMAC_TRIGSRC_15 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_15
+#ifndef CONF_DMAC_LVL_15
+#define CONF_DMAC_LVL_15 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_15
+#ifndef CONF_DMAC_EVOE_15
+#define CONF_DMAC_EVOE_15 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_15
+#ifndef CONF_DMAC_EVIE_15
+#define CONF_DMAC_EVIE_15 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_15
+#ifndef CONF_DMAC_EVACT_15
+#define CONF_DMAC_EVACT_15 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_15
+#ifndef CONF_DMAC_STEPSIZE_15
+#define CONF_DMAC_STEPSIZE_15 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_15
+#ifndef CONF_DMAC_STEPSEL_15
+#define CONF_DMAC_STEPSEL_15 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_15
+#ifndef CONF_DMAC_SRCINC_15
+#define CONF_DMAC_SRCINC_15 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_15
+#ifndef CONF_DMAC_DSTINC_15
+#define CONF_DMAC_DSTINC_15 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_15
+#ifndef CONF_DMAC_BEATSIZE_15
+#define CONF_DMAC_BEATSIZE_15 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_15
+#ifndef CONF_DMAC_BLOCKACT_15
+#define CONF_DMAC_BLOCKACT_15 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_15
+#ifndef CONF_DMAC_EVOSEL_15
+#define CONF_DMAC_EVOSEL_15 0
+#endif
+// </e>
+
+// <e> Channel 16 settings
+// <id> dmac_channel_16_settings
+#ifndef CONF_DMAC_CHANNEL_16_SETTINGS
+#define CONF_DMAC_CHANNEL_16_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 16 is running in standby mode or not
+// <id> dmac_runstdby_16
+#ifndef CONF_DMAC_RUNSTDBY_16
+#define CONF_DMAC_RUNSTDBY_16 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_16
+#ifndef CONF_DMAC_TRIGACT_16
+#define CONF_DMAC_TRIGACT_16 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_16
+#ifndef CONF_DMAC_TRIGSRC_16
+#define CONF_DMAC_TRIGSRC_16 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_16
+#ifndef CONF_DMAC_LVL_16
+#define CONF_DMAC_LVL_16 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_16
+#ifndef CONF_DMAC_EVOE_16
+#define CONF_DMAC_EVOE_16 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_16
+#ifndef CONF_DMAC_EVIE_16
+#define CONF_DMAC_EVIE_16 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_16
+#ifndef CONF_DMAC_EVACT_16
+#define CONF_DMAC_EVACT_16 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_16
+#ifndef CONF_DMAC_STEPSIZE_16
+#define CONF_DMAC_STEPSIZE_16 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_16
+#ifndef CONF_DMAC_STEPSEL_16
+#define CONF_DMAC_STEPSEL_16 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_16
+#ifndef CONF_DMAC_SRCINC_16
+#define CONF_DMAC_SRCINC_16 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_16
+#ifndef CONF_DMAC_DSTINC_16
+#define CONF_DMAC_DSTINC_16 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_16
+#ifndef CONF_DMAC_BEATSIZE_16
+#define CONF_DMAC_BEATSIZE_16 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_16
+#ifndef CONF_DMAC_BLOCKACT_16
+#define CONF_DMAC_BLOCKACT_16 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_16
+#ifndef CONF_DMAC_EVOSEL_16
+#define CONF_DMAC_EVOSEL_16 0
+#endif
+// </e>
+
+// <e> Channel 17 settings
+// <id> dmac_channel_17_settings
+#ifndef CONF_DMAC_CHANNEL_17_SETTINGS
+#define CONF_DMAC_CHANNEL_17_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 17 is running in standby mode or not
+// <id> dmac_runstdby_17
+#ifndef CONF_DMAC_RUNSTDBY_17
+#define CONF_DMAC_RUNSTDBY_17 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_17
+#ifndef CONF_DMAC_TRIGACT_17
+#define CONF_DMAC_TRIGACT_17 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_17
+#ifndef CONF_DMAC_TRIGSRC_17
+#define CONF_DMAC_TRIGSRC_17 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_17
+#ifndef CONF_DMAC_LVL_17
+#define CONF_DMAC_LVL_17 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_17
+#ifndef CONF_DMAC_EVOE_17
+#define CONF_DMAC_EVOE_17 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_17
+#ifndef CONF_DMAC_EVIE_17
+#define CONF_DMAC_EVIE_17 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_17
+#ifndef CONF_DMAC_EVACT_17
+#define CONF_DMAC_EVACT_17 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_17
+#ifndef CONF_DMAC_STEPSIZE_17
+#define CONF_DMAC_STEPSIZE_17 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_17
+#ifndef CONF_DMAC_STEPSEL_17
+#define CONF_DMAC_STEPSEL_17 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_17
+#ifndef CONF_DMAC_SRCINC_17
+#define CONF_DMAC_SRCINC_17 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_17
+#ifndef CONF_DMAC_DSTINC_17
+#define CONF_DMAC_DSTINC_17 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_17
+#ifndef CONF_DMAC_BEATSIZE_17
+#define CONF_DMAC_BEATSIZE_17 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_17
+#ifndef CONF_DMAC_BLOCKACT_17
+#define CONF_DMAC_BLOCKACT_17 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_17
+#ifndef CONF_DMAC_EVOSEL_17
+#define CONF_DMAC_EVOSEL_17 0
+#endif
+// </e>
+
+// <e> Channel 18 settings
+// <id> dmac_channel_18_settings
+#ifndef CONF_DMAC_CHANNEL_18_SETTINGS
+#define CONF_DMAC_CHANNEL_18_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 18 is running in standby mode or not
+// <id> dmac_runstdby_18
+#ifndef CONF_DMAC_RUNSTDBY_18
+#define CONF_DMAC_RUNSTDBY_18 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_18
+#ifndef CONF_DMAC_TRIGACT_18
+#define CONF_DMAC_TRIGACT_18 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_18
+#ifndef CONF_DMAC_TRIGSRC_18
+#define CONF_DMAC_TRIGSRC_18 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_18
+#ifndef CONF_DMAC_LVL_18
+#define CONF_DMAC_LVL_18 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_18
+#ifndef CONF_DMAC_EVOE_18
+#define CONF_DMAC_EVOE_18 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_18
+#ifndef CONF_DMAC_EVIE_18
+#define CONF_DMAC_EVIE_18 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_18
+#ifndef CONF_DMAC_EVACT_18
+#define CONF_DMAC_EVACT_18 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_18
+#ifndef CONF_DMAC_STEPSIZE_18
+#define CONF_DMAC_STEPSIZE_18 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_18
+#ifndef CONF_DMAC_STEPSEL_18
+#define CONF_DMAC_STEPSEL_18 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_18
+#ifndef CONF_DMAC_SRCINC_18
+#define CONF_DMAC_SRCINC_18 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_18
+#ifndef CONF_DMAC_DSTINC_18
+#define CONF_DMAC_DSTINC_18 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_18
+#ifndef CONF_DMAC_BEATSIZE_18
+#define CONF_DMAC_BEATSIZE_18 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_18
+#ifndef CONF_DMAC_BLOCKACT_18
+#define CONF_DMAC_BLOCKACT_18 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_18
+#ifndef CONF_DMAC_EVOSEL_18
+#define CONF_DMAC_EVOSEL_18 0
+#endif
+// </e>
+
+// <e> Channel 19 settings
+// <id> dmac_channel_19_settings
+#ifndef CONF_DMAC_CHANNEL_19_SETTINGS
+#define CONF_DMAC_CHANNEL_19_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 19 is running in standby mode or not
+// <id> dmac_runstdby_19
+#ifndef CONF_DMAC_RUNSTDBY_19
+#define CONF_DMAC_RUNSTDBY_19 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_19
+#ifndef CONF_DMAC_TRIGACT_19
+#define CONF_DMAC_TRIGACT_19 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_19
+#ifndef CONF_DMAC_TRIGSRC_19
+#define CONF_DMAC_TRIGSRC_19 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_19
+#ifndef CONF_DMAC_LVL_19
+#define CONF_DMAC_LVL_19 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_19
+#ifndef CONF_DMAC_EVOE_19
+#define CONF_DMAC_EVOE_19 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_19
+#ifndef CONF_DMAC_EVIE_19
+#define CONF_DMAC_EVIE_19 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_19
+#ifndef CONF_DMAC_EVACT_19
+#define CONF_DMAC_EVACT_19 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_19
+#ifndef CONF_DMAC_STEPSIZE_19
+#define CONF_DMAC_STEPSIZE_19 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_19
+#ifndef CONF_DMAC_STEPSEL_19
+#define CONF_DMAC_STEPSEL_19 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_19
+#ifndef CONF_DMAC_SRCINC_19
+#define CONF_DMAC_SRCINC_19 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_19
+#ifndef CONF_DMAC_DSTINC_19
+#define CONF_DMAC_DSTINC_19 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_19
+#ifndef CONF_DMAC_BEATSIZE_19
+#define CONF_DMAC_BEATSIZE_19 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_19
+#ifndef CONF_DMAC_BLOCKACT_19
+#define CONF_DMAC_BLOCKACT_19 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_19
+#ifndef CONF_DMAC_EVOSEL_19
+#define CONF_DMAC_EVOSEL_19 0
+#endif
+// </e>
+
+// <e> Channel 20 settings
+// <id> dmac_channel_20_settings
+#ifndef CONF_DMAC_CHANNEL_20_SETTINGS
+#define CONF_DMAC_CHANNEL_20_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 20 is running in standby mode or not
+// <id> dmac_runstdby_20
+#ifndef CONF_DMAC_RUNSTDBY_20
+#define CONF_DMAC_RUNSTDBY_20 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_20
+#ifndef CONF_DMAC_TRIGACT_20
+#define CONF_DMAC_TRIGACT_20 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_20
+#ifndef CONF_DMAC_TRIGSRC_20
+#define CONF_DMAC_TRIGSRC_20 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_20
+#ifndef CONF_DMAC_LVL_20
+#define CONF_DMAC_LVL_20 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_20
+#ifndef CONF_DMAC_EVOE_20
+#define CONF_DMAC_EVOE_20 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_20
+#ifndef CONF_DMAC_EVIE_20
+#define CONF_DMAC_EVIE_20 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_20
+#ifndef CONF_DMAC_EVACT_20
+#define CONF_DMAC_EVACT_20 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_20
+#ifndef CONF_DMAC_STEPSIZE_20
+#define CONF_DMAC_STEPSIZE_20 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_20
+#ifndef CONF_DMAC_STEPSEL_20
+#define CONF_DMAC_STEPSEL_20 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_20
+#ifndef CONF_DMAC_SRCINC_20
+#define CONF_DMAC_SRCINC_20 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_20
+#ifndef CONF_DMAC_DSTINC_20
+#define CONF_DMAC_DSTINC_20 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_20
+#ifndef CONF_DMAC_BEATSIZE_20
+#define CONF_DMAC_BEATSIZE_20 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_20
+#ifndef CONF_DMAC_BLOCKACT_20
+#define CONF_DMAC_BLOCKACT_20 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_20
+#ifndef CONF_DMAC_EVOSEL_20
+#define CONF_DMAC_EVOSEL_20 0
+#endif
+// </e>
+
+// <e> Channel 21 settings
+// <id> dmac_channel_21_settings
+#ifndef CONF_DMAC_CHANNEL_21_SETTINGS
+#define CONF_DMAC_CHANNEL_21_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 21 is running in standby mode or not
+// <id> dmac_runstdby_21
+#ifndef CONF_DMAC_RUNSTDBY_21
+#define CONF_DMAC_RUNSTDBY_21 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_21
+#ifndef CONF_DMAC_TRIGACT_21
+#define CONF_DMAC_TRIGACT_21 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_21
+#ifndef CONF_DMAC_TRIGSRC_21
+#define CONF_DMAC_TRIGSRC_21 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_21
+#ifndef CONF_DMAC_LVL_21
+#define CONF_DMAC_LVL_21 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_21
+#ifndef CONF_DMAC_EVOE_21
+#define CONF_DMAC_EVOE_21 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_21
+#ifndef CONF_DMAC_EVIE_21
+#define CONF_DMAC_EVIE_21 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_21
+#ifndef CONF_DMAC_EVACT_21
+#define CONF_DMAC_EVACT_21 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_21
+#ifndef CONF_DMAC_STEPSIZE_21
+#define CONF_DMAC_STEPSIZE_21 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_21
+#ifndef CONF_DMAC_STEPSEL_21
+#define CONF_DMAC_STEPSEL_21 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_21
+#ifndef CONF_DMAC_SRCINC_21
+#define CONF_DMAC_SRCINC_21 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_21
+#ifndef CONF_DMAC_DSTINC_21
+#define CONF_DMAC_DSTINC_21 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_21
+#ifndef CONF_DMAC_BEATSIZE_21
+#define CONF_DMAC_BEATSIZE_21 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_21
+#ifndef CONF_DMAC_BLOCKACT_21
+#define CONF_DMAC_BLOCKACT_21 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_21
+#ifndef CONF_DMAC_EVOSEL_21
+#define CONF_DMAC_EVOSEL_21 0
+#endif
+// </e>
+
+// <e> Channel 22 settings
+// <id> dmac_channel_22_settings
+#ifndef CONF_DMAC_CHANNEL_22_SETTINGS
+#define CONF_DMAC_CHANNEL_22_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 22 is running in standby mode or not
+// <id> dmac_runstdby_22
+#ifndef CONF_DMAC_RUNSTDBY_22
+#define CONF_DMAC_RUNSTDBY_22 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_22
+#ifndef CONF_DMAC_TRIGACT_22
+#define CONF_DMAC_TRIGACT_22 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_22
+#ifndef CONF_DMAC_TRIGSRC_22
+#define CONF_DMAC_TRIGSRC_22 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_22
+#ifndef CONF_DMAC_LVL_22
+#define CONF_DMAC_LVL_22 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_22
+#ifndef CONF_DMAC_EVOE_22
+#define CONF_DMAC_EVOE_22 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_22
+#ifndef CONF_DMAC_EVIE_22
+#define CONF_DMAC_EVIE_22 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_22
+#ifndef CONF_DMAC_EVACT_22
+#define CONF_DMAC_EVACT_22 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_22
+#ifndef CONF_DMAC_STEPSIZE_22
+#define CONF_DMAC_STEPSIZE_22 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_22
+#ifndef CONF_DMAC_STEPSEL_22
+#define CONF_DMAC_STEPSEL_22 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_22
+#ifndef CONF_DMAC_SRCINC_22
+#define CONF_DMAC_SRCINC_22 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_22
+#ifndef CONF_DMAC_DSTINC_22
+#define CONF_DMAC_DSTINC_22 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_22
+#ifndef CONF_DMAC_BEATSIZE_22
+#define CONF_DMAC_BEATSIZE_22 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_22
+#ifndef CONF_DMAC_BLOCKACT_22
+#define CONF_DMAC_BLOCKACT_22 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_22
+#ifndef CONF_DMAC_EVOSEL_22
+#define CONF_DMAC_EVOSEL_22 0
+#endif
+// </e>
+
+// <e> Channel 23 settings
+// <id> dmac_channel_23_settings
+#ifndef CONF_DMAC_CHANNEL_23_SETTINGS
+#define CONF_DMAC_CHANNEL_23_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 23 is running in standby mode or not
+// <id> dmac_runstdby_23
+#ifndef CONF_DMAC_RUNSTDBY_23
+#define CONF_DMAC_RUNSTDBY_23 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_23
+#ifndef CONF_DMAC_TRIGACT_23
+#define CONF_DMAC_TRIGACT_23 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_23
+#ifndef CONF_DMAC_TRIGSRC_23
+#define CONF_DMAC_TRIGSRC_23 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_23
+#ifndef CONF_DMAC_LVL_23
+#define CONF_DMAC_LVL_23 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_23
+#ifndef CONF_DMAC_EVOE_23
+#define CONF_DMAC_EVOE_23 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_23
+#ifndef CONF_DMAC_EVIE_23
+#define CONF_DMAC_EVIE_23 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_23
+#ifndef CONF_DMAC_EVACT_23
+#define CONF_DMAC_EVACT_23 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_23
+#ifndef CONF_DMAC_STEPSIZE_23
+#define CONF_DMAC_STEPSIZE_23 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_23
+#ifndef CONF_DMAC_STEPSEL_23
+#define CONF_DMAC_STEPSEL_23 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_23
+#ifndef CONF_DMAC_SRCINC_23
+#define CONF_DMAC_SRCINC_23 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_23
+#ifndef CONF_DMAC_DSTINC_23
+#define CONF_DMAC_DSTINC_23 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_23
+#ifndef CONF_DMAC_BEATSIZE_23
+#define CONF_DMAC_BEATSIZE_23 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_23
+#ifndef CONF_DMAC_BLOCKACT_23
+#define CONF_DMAC_BLOCKACT_23 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_23
+#ifndef CONF_DMAC_EVOSEL_23
+#define CONF_DMAC_EVOSEL_23 0
+#endif
+// </e>
+
+// <e> Channel 24 settings
+// <id> dmac_channel_24_settings
+#ifndef CONF_DMAC_CHANNEL_24_SETTINGS
+#define CONF_DMAC_CHANNEL_24_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 24 is running in standby mode or not
+// <id> dmac_runstdby_24
+#ifndef CONF_DMAC_RUNSTDBY_24
+#define CONF_DMAC_RUNSTDBY_24 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_24
+#ifndef CONF_DMAC_TRIGACT_24
+#define CONF_DMAC_TRIGACT_24 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_24
+#ifndef CONF_DMAC_TRIGSRC_24
+#define CONF_DMAC_TRIGSRC_24 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_24
+#ifndef CONF_DMAC_LVL_24
+#define CONF_DMAC_LVL_24 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_24
+#ifndef CONF_DMAC_EVOE_24
+#define CONF_DMAC_EVOE_24 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_24
+#ifndef CONF_DMAC_EVIE_24
+#define CONF_DMAC_EVIE_24 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_24
+#ifndef CONF_DMAC_EVACT_24
+#define CONF_DMAC_EVACT_24 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_24
+#ifndef CONF_DMAC_STEPSIZE_24
+#define CONF_DMAC_STEPSIZE_24 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_24
+#ifndef CONF_DMAC_STEPSEL_24
+#define CONF_DMAC_STEPSEL_24 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_24
+#ifndef CONF_DMAC_SRCINC_24
+#define CONF_DMAC_SRCINC_24 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_24
+#ifndef CONF_DMAC_DSTINC_24
+#define CONF_DMAC_DSTINC_24 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_24
+#ifndef CONF_DMAC_BEATSIZE_24
+#define CONF_DMAC_BEATSIZE_24 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_24
+#ifndef CONF_DMAC_BLOCKACT_24
+#define CONF_DMAC_BLOCKACT_24 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_24
+#ifndef CONF_DMAC_EVOSEL_24
+#define CONF_DMAC_EVOSEL_24 0
+#endif
+// </e>
+
+// <e> Channel 25 settings
+// <id> dmac_channel_25_settings
+#ifndef CONF_DMAC_CHANNEL_25_SETTINGS
+#define CONF_DMAC_CHANNEL_25_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 25 is running in standby mode or not
+// <id> dmac_runstdby_25
+#ifndef CONF_DMAC_RUNSTDBY_25
+#define CONF_DMAC_RUNSTDBY_25 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_25
+#ifndef CONF_DMAC_TRIGACT_25
+#define CONF_DMAC_TRIGACT_25 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_25
+#ifndef CONF_DMAC_TRIGSRC_25
+#define CONF_DMAC_TRIGSRC_25 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_25
+#ifndef CONF_DMAC_LVL_25
+#define CONF_DMAC_LVL_25 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_25
+#ifndef CONF_DMAC_EVOE_25
+#define CONF_DMAC_EVOE_25 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_25
+#ifndef CONF_DMAC_EVIE_25
+#define CONF_DMAC_EVIE_25 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_25
+#ifndef CONF_DMAC_EVACT_25
+#define CONF_DMAC_EVACT_25 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_25
+#ifndef CONF_DMAC_STEPSIZE_25
+#define CONF_DMAC_STEPSIZE_25 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_25
+#ifndef CONF_DMAC_STEPSEL_25
+#define CONF_DMAC_STEPSEL_25 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_25
+#ifndef CONF_DMAC_SRCINC_25
+#define CONF_DMAC_SRCINC_25 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_25
+#ifndef CONF_DMAC_DSTINC_25
+#define CONF_DMAC_DSTINC_25 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_25
+#ifndef CONF_DMAC_BEATSIZE_25
+#define CONF_DMAC_BEATSIZE_25 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_25
+#ifndef CONF_DMAC_BLOCKACT_25
+#define CONF_DMAC_BLOCKACT_25 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_25
+#ifndef CONF_DMAC_EVOSEL_25
+#define CONF_DMAC_EVOSEL_25 0
+#endif
+// </e>
+
+// <e> Channel 26 settings
+// <id> dmac_channel_26_settings
+#ifndef CONF_DMAC_CHANNEL_26_SETTINGS
+#define CONF_DMAC_CHANNEL_26_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 26 is running in standby mode or not
+// <id> dmac_runstdby_26
+#ifndef CONF_DMAC_RUNSTDBY_26
+#define CONF_DMAC_RUNSTDBY_26 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_26
+#ifndef CONF_DMAC_TRIGACT_26
+#define CONF_DMAC_TRIGACT_26 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_26
+#ifndef CONF_DMAC_TRIGSRC_26
+#define CONF_DMAC_TRIGSRC_26 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_26
+#ifndef CONF_DMAC_LVL_26
+#define CONF_DMAC_LVL_26 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_26
+#ifndef CONF_DMAC_EVOE_26
+#define CONF_DMAC_EVOE_26 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_26
+#ifndef CONF_DMAC_EVIE_26
+#define CONF_DMAC_EVIE_26 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_26
+#ifndef CONF_DMAC_EVACT_26
+#define CONF_DMAC_EVACT_26 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_26
+#ifndef CONF_DMAC_STEPSIZE_26
+#define CONF_DMAC_STEPSIZE_26 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_26
+#ifndef CONF_DMAC_STEPSEL_26
+#define CONF_DMAC_STEPSEL_26 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_26
+#ifndef CONF_DMAC_SRCINC_26
+#define CONF_DMAC_SRCINC_26 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_26
+#ifndef CONF_DMAC_DSTINC_26
+#define CONF_DMAC_DSTINC_26 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_26
+#ifndef CONF_DMAC_BEATSIZE_26
+#define CONF_DMAC_BEATSIZE_26 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_26
+#ifndef CONF_DMAC_BLOCKACT_26
+#define CONF_DMAC_BLOCKACT_26 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_26
+#ifndef CONF_DMAC_EVOSEL_26
+#define CONF_DMAC_EVOSEL_26 0
+#endif
+// </e>
+
+// <e> Channel 27 settings
+// <id> dmac_channel_27_settings
+#ifndef CONF_DMAC_CHANNEL_27_SETTINGS
+#define CONF_DMAC_CHANNEL_27_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 27 is running in standby mode or not
+// <id> dmac_runstdby_27
+#ifndef CONF_DMAC_RUNSTDBY_27
+#define CONF_DMAC_RUNSTDBY_27 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_27
+#ifndef CONF_DMAC_TRIGACT_27
+#define CONF_DMAC_TRIGACT_27 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_27
+#ifndef CONF_DMAC_TRIGSRC_27
+#define CONF_DMAC_TRIGSRC_27 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_27
+#ifndef CONF_DMAC_LVL_27
+#define CONF_DMAC_LVL_27 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_27
+#ifndef CONF_DMAC_EVOE_27
+#define CONF_DMAC_EVOE_27 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_27
+#ifndef CONF_DMAC_EVIE_27
+#define CONF_DMAC_EVIE_27 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_27
+#ifndef CONF_DMAC_EVACT_27
+#define CONF_DMAC_EVACT_27 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_27
+#ifndef CONF_DMAC_STEPSIZE_27
+#define CONF_DMAC_STEPSIZE_27 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_27
+#ifndef CONF_DMAC_STEPSEL_27
+#define CONF_DMAC_STEPSEL_27 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_27
+#ifndef CONF_DMAC_SRCINC_27
+#define CONF_DMAC_SRCINC_27 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_27
+#ifndef CONF_DMAC_DSTINC_27
+#define CONF_DMAC_DSTINC_27 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_27
+#ifndef CONF_DMAC_BEATSIZE_27
+#define CONF_DMAC_BEATSIZE_27 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_27
+#ifndef CONF_DMAC_BLOCKACT_27
+#define CONF_DMAC_BLOCKACT_27 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_27
+#ifndef CONF_DMAC_EVOSEL_27
+#define CONF_DMAC_EVOSEL_27 0
+#endif
+// </e>
+
+// <e> Channel 28 settings
+// <id> dmac_channel_28_settings
+#ifndef CONF_DMAC_CHANNEL_28_SETTINGS
+#define CONF_DMAC_CHANNEL_28_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 28 is running in standby mode or not
+// <id> dmac_runstdby_28
+#ifndef CONF_DMAC_RUNSTDBY_28
+#define CONF_DMAC_RUNSTDBY_28 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_28
+#ifndef CONF_DMAC_TRIGACT_28
+#define CONF_DMAC_TRIGACT_28 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_28
+#ifndef CONF_DMAC_TRIGSRC_28
+#define CONF_DMAC_TRIGSRC_28 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_28
+#ifndef CONF_DMAC_LVL_28
+#define CONF_DMAC_LVL_28 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_28
+#ifndef CONF_DMAC_EVOE_28
+#define CONF_DMAC_EVOE_28 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_28
+#ifndef CONF_DMAC_EVIE_28
+#define CONF_DMAC_EVIE_28 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_28
+#ifndef CONF_DMAC_EVACT_28
+#define CONF_DMAC_EVACT_28 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_28
+#ifndef CONF_DMAC_STEPSIZE_28
+#define CONF_DMAC_STEPSIZE_28 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_28
+#ifndef CONF_DMAC_STEPSEL_28
+#define CONF_DMAC_STEPSEL_28 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_28
+#ifndef CONF_DMAC_SRCINC_28
+#define CONF_DMAC_SRCINC_28 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_28
+#ifndef CONF_DMAC_DSTINC_28
+#define CONF_DMAC_DSTINC_28 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_28
+#ifndef CONF_DMAC_BEATSIZE_28
+#define CONF_DMAC_BEATSIZE_28 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_28
+#ifndef CONF_DMAC_BLOCKACT_28
+#define CONF_DMAC_BLOCKACT_28 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_28
+#ifndef CONF_DMAC_EVOSEL_28
+#define CONF_DMAC_EVOSEL_28 0
+#endif
+// </e>
+
+// <e> Channel 29 settings
+// <id> dmac_channel_29_settings
+#ifndef CONF_DMAC_CHANNEL_29_SETTINGS
+#define CONF_DMAC_CHANNEL_29_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 29 is running in standby mode or not
+// <id> dmac_runstdby_29
+#ifndef CONF_DMAC_RUNSTDBY_29
+#define CONF_DMAC_RUNSTDBY_29 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_29
+#ifndef CONF_DMAC_TRIGACT_29
+#define CONF_DMAC_TRIGACT_29 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_29
+#ifndef CONF_DMAC_TRIGSRC_29
+#define CONF_DMAC_TRIGSRC_29 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_29
+#ifndef CONF_DMAC_LVL_29
+#define CONF_DMAC_LVL_29 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_29
+#ifndef CONF_DMAC_EVOE_29
+#define CONF_DMAC_EVOE_29 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_29
+#ifndef CONF_DMAC_EVIE_29
+#define CONF_DMAC_EVIE_29 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_29
+#ifndef CONF_DMAC_EVACT_29
+#define CONF_DMAC_EVACT_29 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_29
+#ifndef CONF_DMAC_STEPSIZE_29
+#define CONF_DMAC_STEPSIZE_29 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_29
+#ifndef CONF_DMAC_STEPSEL_29
+#define CONF_DMAC_STEPSEL_29 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_29
+#ifndef CONF_DMAC_SRCINC_29
+#define CONF_DMAC_SRCINC_29 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_29
+#ifndef CONF_DMAC_DSTINC_29
+#define CONF_DMAC_DSTINC_29 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_29
+#ifndef CONF_DMAC_BEATSIZE_29
+#define CONF_DMAC_BEATSIZE_29 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_29
+#ifndef CONF_DMAC_BLOCKACT_29
+#define CONF_DMAC_BLOCKACT_29 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_29
+#ifndef CONF_DMAC_EVOSEL_29
+#define CONF_DMAC_EVOSEL_29 0
+#endif
+// </e>
+
+// <e> Channel 30 settings
+// <id> dmac_channel_30_settings
+#ifndef CONF_DMAC_CHANNEL_30_SETTINGS
+#define CONF_DMAC_CHANNEL_30_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 30 is running in standby mode or not
+// <id> dmac_runstdby_30
+#ifndef CONF_DMAC_RUNSTDBY_30
+#define CONF_DMAC_RUNSTDBY_30 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_30
+#ifndef CONF_DMAC_TRIGACT_30
+#define CONF_DMAC_TRIGACT_30 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_30
+#ifndef CONF_DMAC_TRIGSRC_30
+#define CONF_DMAC_TRIGSRC_30 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_30
+#ifndef CONF_DMAC_LVL_30
+#define CONF_DMAC_LVL_30 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_30
+#ifndef CONF_DMAC_EVOE_30
+#define CONF_DMAC_EVOE_30 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_30
+#ifndef CONF_DMAC_EVIE_30
+#define CONF_DMAC_EVIE_30 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_30
+#ifndef CONF_DMAC_EVACT_30
+#define CONF_DMAC_EVACT_30 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_30
+#ifndef CONF_DMAC_STEPSIZE_30
+#define CONF_DMAC_STEPSIZE_30 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_30
+#ifndef CONF_DMAC_STEPSEL_30
+#define CONF_DMAC_STEPSEL_30 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_30
+#ifndef CONF_DMAC_SRCINC_30
+#define CONF_DMAC_SRCINC_30 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_30
+#ifndef CONF_DMAC_DSTINC_30
+#define CONF_DMAC_DSTINC_30 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_30
+#ifndef CONF_DMAC_BEATSIZE_30
+#define CONF_DMAC_BEATSIZE_30 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_30
+#ifndef CONF_DMAC_BLOCKACT_30
+#define CONF_DMAC_BLOCKACT_30 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_30
+#ifndef CONF_DMAC_EVOSEL_30
+#define CONF_DMAC_EVOSEL_30 0
+#endif
+// </e>
+
+// <e> Channel 31 settings
+// <id> dmac_channel_31_settings
+#ifndef CONF_DMAC_CHANNEL_31_SETTINGS
+#define CONF_DMAC_CHANNEL_31_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 31 is running in standby mode or not
+// <id> dmac_runstdby_31
+#ifndef CONF_DMAC_RUNSTDBY_31
+#define CONF_DMAC_RUNSTDBY_31 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_31
+#ifndef CONF_DMAC_TRIGACT_31
+#define CONF_DMAC_TRIGACT_31 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_31
+#ifndef CONF_DMAC_TRIGSRC_31
+#define CONF_DMAC_TRIGSRC_31 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_31
+#ifndef CONF_DMAC_LVL_31
+#define CONF_DMAC_LVL_31 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_31
+#ifndef CONF_DMAC_EVOE_31
+#define CONF_DMAC_EVOE_31 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_31
+#ifndef CONF_DMAC_EVIE_31
+#define CONF_DMAC_EVIE_31 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_31
+#ifndef CONF_DMAC_EVACT_31
+#define CONF_DMAC_EVACT_31 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_31
+#ifndef CONF_DMAC_STEPSIZE_31
+#define CONF_DMAC_STEPSIZE_31 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_31
+#ifndef CONF_DMAC_STEPSEL_31
+#define CONF_DMAC_STEPSEL_31 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_31
+#ifndef CONF_DMAC_SRCINC_31
+#define CONF_DMAC_SRCINC_31 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_31
+#ifndef CONF_DMAC_DSTINC_31
+#define CONF_DMAC_DSTINC_31 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_31
+#ifndef CONF_DMAC_BEATSIZE_31
+#define CONF_DMAC_BEATSIZE_31 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_31
+#ifndef CONF_DMAC_BLOCKACT_31
+#define CONF_DMAC_BLOCKACT_31 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_31
+#ifndef CONF_DMAC_EVOSEL_31
+#define CONF_DMAC_EVOSEL_31 0
+#endif
+// </e>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_DMAC_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h
new file mode 100644
index 000000000..6f4f01a7e
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h
@@ -0,0 +1,924 @@
+// Circuit Python SAMD51 clock tree:
+// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5, GCLK6
+//   GCLK1 (48MHz) -> 48 MHz peripherals
+//   GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0
+//     DPLL0 (multiplied up to 120 MHz) -> GCLK0, GCLK4 (output for monitoring)
+//   GCLK6 (48 MHz divided down to 12 MHz) -> DAC
+
+// We'd like to use XOSC32K as a ref for DFLL48M on boards with a 32kHz crystal,
+// but haven't figured that out yet.
+
+// Used in hpl/core/hpl_init.c to define which clocks should be initialized first.
+// Not clear why all these need to be specified, but it doesn't work properly otherwise.
+
+//#define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1 | 1 << 3 | 1 <<5)
+#define CIRCUITPY_GCLK_INIT_1ST 0xffff
+
+/* Auto-generated config file hpl_gclk_config.h */
+#ifndef HPL_GCLK_CONFIG_H
+#define HPL_GCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> Generic clock generator 0 configuration
+// <i> Indicates whether generic clock 0 configuration is enabled or not
+// <id> enable_gclk_gen_0
+#ifndef CONF_GCLK_GENERATOR_0_CONFIG
+#define CONF_GCLK_GENERATOR_0_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 0 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 0
+// <id> gclk_gen_0_oscillator
+#ifndef CONF_GCLK_GEN_0_SOURCE
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_0_runstdby
+#ifndef CONF_GCLK_GEN_0_RUNSTDBY
+#define CONF_GCLK_GEN_0_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_0_div_sel
+#ifndef CONF_GCLK_GEN_0_DIVSEL
+#define CONF_GCLK_GEN_0_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_0_oe
+#ifndef CONF_GCLK_GEN_0_OE
+#define CONF_GCLK_GEN_0_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_0_oov
+#ifndef CONF_GCLK_GEN_0_OOV
+#define CONF_GCLK_GEN_0_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_0_idc
+#ifndef CONF_GCLK_GEN_0_IDC
+#define CONF_GCLK_GEN_0_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_0_enable
+#ifndef CONF_GCLK_GEN_0_GENEN
+#define CONF_GCLK_GEN_0_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 0 division <0x0000-0xFFFF>
+// <id> gclk_gen_0_div
+#ifndef CONF_GCLK_GEN_0_DIV
+#define CONF_GCLK_GEN_0_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 1 configuration
+// <i> Indicates whether generic clock 1 configuration is enabled or not
+// <id> enable_gclk_gen_1
+#ifndef CONF_GCLK_GENERATOR_1_CONFIG
+#define CONF_GCLK_GENERATOR_1_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 1 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 1
+// <id> gclk_gen_1_oscillator
+#ifndef CONF_GCLK_GEN_1_SOURCE
+#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_1_runstdby
+#ifndef CONF_GCLK_GEN_1_RUNSTDBY
+#define CONF_GCLK_GEN_1_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_1_div_sel
+#ifndef CONF_GCLK_GEN_1_DIVSEL
+#define CONF_GCLK_GEN_1_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_1_oe
+#ifndef CONF_GCLK_GEN_1_OE
+#define CONF_GCLK_GEN_1_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_1_oov
+#ifndef CONF_GCLK_GEN_1_OOV
+#define CONF_GCLK_GEN_1_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_1_idc
+#ifndef CONF_GCLK_GEN_1_IDC
+#define CONF_GCLK_GEN_1_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_1_enable
+#ifndef CONF_GCLK_GEN_1_GENEN
+#define CONF_GCLK_GEN_1_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 1 division <0x0000-0xFFFF>
+// <id> gclk_gen_1_div
+#ifndef CONF_GCLK_GEN_1_DIV
+#define CONF_GCLK_GEN_1_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 2 configuration
+// <i> Indicates whether generic clock 2 configuration is enabled or not
+// <id> enable_gclk_gen_2
+#ifndef CONF_GCLK_GENERATOR_2_CONFIG
+#define CONF_GCLK_GENERATOR_2_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 2 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 2
+// <id> gclk_gen_2_oscillator
+#ifndef CONF_GCLK_GEN_2_SOURCE
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_2_runstdby
+#ifndef CONF_GCLK_GEN_2_RUNSTDBY
+#define CONF_GCLK_GEN_2_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_2_div_sel
+#ifndef CONF_GCLK_GEN_2_DIVSEL
+#define CONF_GCLK_GEN_2_DIVSEL 1
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_2_oe
+#ifndef CONF_GCLK_GEN_2_OE
+#define CONF_GCLK_GEN_2_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_2_oov
+#ifndef CONF_GCLK_GEN_2_OOV
+#define CONF_GCLK_GEN_2_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_2_idc
+#ifndef CONF_GCLK_GEN_2_IDC
+#define CONF_GCLK_GEN_2_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_2_enable
+#ifndef CONF_GCLK_GEN_2_GENEN
+#define CONF_GCLK_GEN_2_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 2 division <0x0000-0xFFFF>
+// <id> gclk_gen_2_div
+#ifndef CONF_GCLK_GEN_2_DIV
+#define CONF_GCLK_GEN_2_DIV 4
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 3 configuration
+// <i> Indicates whether generic clock 3 configuration is enabled or not
+// <id> enable_gclk_gen_3
+#ifndef CONF_GCLK_GENERATOR_3_CONFIG
+#define CONF_GCLK_GENERATOR_3_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 3 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 3
+// <id> gclk_gen_3_oscillator
+#ifndef CONF_GCLK_GEN_3_SOURCE
+#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_3_runstdby
+#ifndef CONF_GCLK_GEN_3_RUNSTDBY
+#define CONF_GCLK_GEN_3_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_3_div_sel
+#ifndef CONF_GCLK_GEN_3_DIVSEL
+#define CONF_GCLK_GEN_3_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_3_oe
+#ifndef CONF_GCLK_GEN_3_OE
+#define CONF_GCLK_GEN_3_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_3_oov
+#ifndef CONF_GCLK_GEN_3_OOV
+#define CONF_GCLK_GEN_3_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_3_idc
+#ifndef CONF_GCLK_GEN_3_IDC
+#define CONF_GCLK_GEN_3_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_3_enable
+#ifndef CONF_GCLK_GEN_3_GENEN
+#define CONF_GCLK_GEN_3_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 3 division <0x0000-0xFFFF>
+// <id> gclk_gen_3_div
+#ifndef CONF_GCLK_GEN_3_DIV
+#define CONF_GCLK_GEN_3_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 4 configuration
+// <i> Indicates whether generic clock 4 configuration is enabled or not
+// <id> enable_gclk_gen_4
+#ifndef CONF_GCLK_GENERATOR_4_CONFIG
+#define CONF_GCLK_GENERATOR_4_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 4 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 4
+// <id> gclk_gen_4_oscillator
+#ifndef CONF_GCLK_GEN_4_SOURCE
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DPLL0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_4_runstdby
+#ifndef CONF_GCLK_GEN_4_RUNSTDBY
+#define CONF_GCLK_GEN_4_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_4_div_sel
+#ifndef CONF_GCLK_GEN_4_DIVSEL
+#define CONF_GCLK_GEN_4_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_4_oe
+#ifndef CONF_GCLK_GEN_4_OE
+#define CONF_GCLK_GEN_4_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_4_oov
+#ifndef CONF_GCLK_GEN_4_OOV
+#define CONF_GCLK_GEN_4_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_4_idc
+#ifndef CONF_GCLK_GEN_4_IDC
+#define CONF_GCLK_GEN_4_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_4_enable
+#ifndef CONF_GCLK_GEN_4_GENEN
+#define CONF_GCLK_GEN_4_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 4 division <0x0000-0xFFFF>
+// <id> gclk_gen_4_div
+#ifndef CONF_GCLK_GEN_4_DIV
+#define CONF_GCLK_GEN_4_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 5 configuration
+// <i> Indicates whether generic clock 5 configuration is enabled or not
+// <id> enable_gclk_gen_5
+#ifndef CONF_GCLK_GENERATOR_5_CONFIG
+#define CONF_GCLK_GENERATOR_5_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 5 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 5
+// <id> gclk_gen_5_oscillator
+#ifndef CONF_GCLK_GEN_5_SOURCE
+#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DFLL
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_5_runstdby
+#ifndef CONF_GCLK_GEN_5_RUNSTDBY
+#define CONF_GCLK_GEN_5_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_5_div_sel
+#ifndef CONF_GCLK_GEN_5_DIVSEL
+#define CONF_GCLK_GEN_5_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_5_oe
+#ifndef CONF_GCLK_GEN_5_OE
+#define CONF_GCLK_GEN_5_OE 1
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_5_oov
+#ifndef CONF_GCLK_GEN_5_OOV
+#define CONF_GCLK_GEN_5_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_5_idc
+#ifndef CONF_GCLK_GEN_5_IDC
+#define CONF_GCLK_GEN_5_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_5_enable
+#ifndef CONF_GCLK_GEN_5_GENEN
+#define CONF_GCLK_GEN_5_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 5 division <0x0000-0xFFFF>
+// <id> gclk_gen_5_div
+#ifndef CONF_GCLK_GEN_5_DIV
+#define CONF_GCLK_GEN_5_DIV 24
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 6 configuration
+// <i> Indicates whether generic clock 6 configuration is enabled or not
+// <id> enable_gclk_gen_6
+#ifndef CONF_GCLK_GENERATOR_6_CONFIG
+#define CONF_GCLK_GENERATOR_6_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 6 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 6
+// <id> gclk_gen_6_oscillator
+#ifndef CONF_GCLK_GEN_6_SOURCE
+#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_DFLL
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_6_runstdby
+#ifndef CONF_GCLK_GEN_6_RUNSTDBY
+#define CONF_GCLK_GEN_6_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_6_div_sel
+#ifndef CONF_GCLK_GEN_6_DIVSEL
+#define CONF_GCLK_GEN_6_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_6_oe
+#ifndef CONF_GCLK_GEN_6_OE
+#define CONF_GCLK_GEN_6_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_6_oov
+#ifndef CONF_GCLK_GEN_6_OOV
+#define CONF_GCLK_GEN_6_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_6_idc
+#ifndef CONF_GCLK_GEN_6_IDC
+#define CONF_GCLK_GEN_6_IDC 1
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_6_enable
+#ifndef CONF_GCLK_GEN_6_GENEN
+#define CONF_GCLK_GEN_6_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 6 division <0x0000-0xFFFF>
+// <id> gclk_gen_6_div
+#ifndef CONF_GCLK_GEN_6_DIV
+#define CONF_GCLK_GEN_6_DIV 4
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 7 configuration
+// <i> Indicates whether generic clock 7 configuration is enabled or not
+// <id> enable_gclk_gen_7
+#ifndef CONF_GCLK_GENERATOR_7_CONFIG
+#define CONF_GCLK_GENERATOR_7_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 7 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 7
+// <id> gclk_gen_7_oscillator
+#ifndef CONF_GCLK_GEN_7_SOURCE
+#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_7_runstdby
+#ifndef CONF_GCLK_GEN_7_RUNSTDBY
+#define CONF_GCLK_GEN_7_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_7_div_sel
+#ifndef CONF_GCLK_GEN_7_DIVSEL
+#define CONF_GCLK_GEN_7_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_7_oe
+#ifndef CONF_GCLK_GEN_7_OE
+#define CONF_GCLK_GEN_7_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_7_oov
+#ifndef CONF_GCLK_GEN_7_OOV
+#define CONF_GCLK_GEN_7_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_7_idc
+#ifndef CONF_GCLK_GEN_7_IDC
+#define CONF_GCLK_GEN_7_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_7_enable
+#ifndef CONF_GCLK_GEN_7_GENEN
+#define CONF_GCLK_GEN_7_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 7 division <0x0000-0xFFFF>
+// <id> gclk_gen_7_div
+#ifndef CONF_GCLK_GEN_7_DIV
+#define CONF_GCLK_GEN_7_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 8 configuration
+// <i> Indicates whether generic clock 8 configuration is enabled or not
+// <id> enable_gclk_gen_8
+#ifndef CONF_GCLK_GENERATOR_8_CONFIG
+#define CONF_GCLK_GENERATOR_8_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 8 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 8
+// <id> gclk_gen_8_oscillator
+#ifndef CONF_GCLK_GEN_8_SOURCE
+#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_8_runstdby
+#ifndef CONF_GCLK_GEN_8_RUNSTDBY
+#define CONF_GCLK_GEN_8_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_8_div_sel
+#ifndef CONF_GCLK_GEN_8_DIVSEL
+#define CONF_GCLK_GEN_8_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_8_oe
+#ifndef CONF_GCLK_GEN_8_OE
+#define CONF_GCLK_GEN_8_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_8_oov
+#ifndef CONF_GCLK_GEN_8_OOV
+#define CONF_GCLK_GEN_8_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_8_idc
+#ifndef CONF_GCLK_GEN_8_IDC
+#define CONF_GCLK_GEN_8_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_8_enable
+#ifndef CONF_GCLK_GEN_8_GENEN
+#define CONF_GCLK_GEN_8_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 8 division <0x0000-0xFFFF>
+// <id> gclk_gen_8_div
+#ifndef CONF_GCLK_GEN_8_DIV
+#define CONF_GCLK_GEN_8_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 9 configuration
+// <i> Indicates whether generic clock 9 configuration is enabled or not
+// <id> enable_gclk_gen_9
+#ifndef CONF_GCLK_GENERATOR_9_CONFIG
+#define CONF_GCLK_GENERATOR_9_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 9 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 9
+// <id> gclk_gen_9_oscillator
+#ifndef CONF_GCLK_GEN_9_SOURCE
+#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_9_runstdby
+#ifndef CONF_GCLK_GEN_9_RUNSTDBY
+#define CONF_GCLK_GEN_9_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_9_div_sel
+#ifndef CONF_GCLK_GEN_9_DIVSEL
+#define CONF_GCLK_GEN_9_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_9_oe
+#ifndef CONF_GCLK_GEN_9_OE
+#define CONF_GCLK_GEN_9_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_9_oov
+#ifndef CONF_GCLK_GEN_9_OOV
+#define CONF_GCLK_GEN_9_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_9_idc
+#ifndef CONF_GCLK_GEN_9_IDC
+#define CONF_GCLK_GEN_9_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_9_enable
+#ifndef CONF_GCLK_GEN_9_GENEN
+#define CONF_GCLK_GEN_9_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 9 division <0x0000-0xFFFF>
+// <id> gclk_gen_9_div
+#ifndef CONF_GCLK_GEN_9_DIV
+#define CONF_GCLK_GEN_9_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 10 configuration
+// <i> Indicates whether generic clock 10 configuration is enabled or not
+// <id> enable_gclk_gen_10
+#ifndef CONF_GCLK_GENERATOR_10_CONFIG
+#define CONF_GCLK_GENERATOR_10_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 10 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 10
+// <id> gclk_gen_10_oscillator
+#ifndef CONF_GCLK_GEN_10_SOURCE
+#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_10_runstdby
+#ifndef CONF_GCLK_GEN_10_RUNSTDBY
+#define CONF_GCLK_GEN_10_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_10_div_sel
+#ifndef CONF_GCLK_GEN_10_DIVSEL
+#define CONF_GCLK_GEN_10_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_10_oe
+#ifndef CONF_GCLK_GEN_10_OE
+#define CONF_GCLK_GEN_10_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_10_oov
+#ifndef CONF_GCLK_GEN_10_OOV
+#define CONF_GCLK_GEN_10_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_10_idc
+#ifndef CONF_GCLK_GEN_10_IDC
+#define CONF_GCLK_GEN_10_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_10_enable
+#ifndef CONF_GCLK_GEN_10_GENEN
+#define CONF_GCLK_GEN_10_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 10 division <0x0000-0xFFFF>
+// <id> gclk_gen_10_div
+#ifndef CONF_GCLK_GEN_10_DIV
+#define CONF_GCLK_GEN_10_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 11 configuration
+// <i> Indicates whether generic clock 11 configuration is enabled or not
+// <id> enable_gclk_gen_11
+#ifndef CONF_GCLK_GENERATOR_11_CONFIG
+#define CONF_GCLK_GENERATOR_11_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 11 source// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 11
+// <id> gclk_gen_11_oscillator
+#ifndef CONF_GCLK_GEN_11_SOURCE
+#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_11_runstdby
+#ifndef CONF_GCLK_GEN_11_RUNSTDBY
+#define CONF_GCLK_GEN_11_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_11_div_sel
+#ifndef CONF_GCLK_GEN_11_DIVSEL
+#define CONF_GCLK_GEN_11_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_11_oe
+#ifndef CONF_GCLK_GEN_11_OE
+#define CONF_GCLK_GEN_11_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_11_oov
+#ifndef CONF_GCLK_GEN_11_OOV
+#define CONF_GCLK_GEN_11_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_11_idc
+#ifndef CONF_GCLK_GEN_11_IDC
+#define CONF_GCLK_GEN_11_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_11_enable
+#ifndef CONF_GCLK_GEN_11_GENEN
+#define CONF_GCLK_GEN_11_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 11 division <0x0000-0xFFFF>
+// <id> gclk_gen_11_div
+#ifndef CONF_GCLK_GEN_11_DIV
+#define CONF_GCLK_GEN_11_DIV 1
+#endif
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_GCLK_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_mclk_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_mclk_config.h
new file mode 100644
index 000000000..a5a7de53c
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_mclk_config.h
@@ -0,0 +1,104 @@
+/* Auto-generated config file hpl_mclk_config.h */
+#ifndef HPL_MCLK_CONFIG_H
+#define HPL_MCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <e> System Configuration
+// <i> Indicates whether configuration for system is enabled or not
+// <id> enable_cpu_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// <h> Basic settings
+// <y> CPU Clock source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <i> This defines the clock source for the CPU
+// <id> cpu_clock_source
+#ifndef CONF_CPU_SRC
+#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> CPU Clock Division Factor
+// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
+// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
+// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
+// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
+// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
+// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
+// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
+// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
+// <i> Prescalar for CPU clock
+// <id> cpu_div
+#ifndef CONF_MCLK_CPUDIV
+#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
+#endif
+// <y> Low Power Clock Division
+// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
+// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
+// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
+// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
+// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
+// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
+// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
+// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_lpdiv
+#ifndef CONF_MCLK_LPDIV
+#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
+#endif
+
+// <y> Backup Clock Division
+// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
+// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
+// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
+// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
+// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
+// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
+// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
+// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_bupdiv
+#ifndef CONF_MCLK_BUPDIV
+#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
+#endif
+// <y> High-Speed Clock Division
+// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
+// <id> mclk_arch_hsdiv
+#ifndef CONF_MCLK_HSDIV
+#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
+#endif
+// </h>
+
+// <h> NVM Settings
+// <o> NVM Wait States
+// <i> These bits select the number of wait states for a read operation.
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <id> nvm_wait_states
+#ifndef CONF_NVM_WAIT_STATE
+#define CONF_NVM_WAIT_STATE 0
+#endif
+
+// </h>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCLK_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_nvmctrl_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_nvmctrl_config.h
new file mode 100644
index 000000000..53fcb593a
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_nvmctrl_config.h
@@ -0,0 +1,36 @@
+/* Auto-generated config file hpl_nvmctrl_config.h */
+#ifndef HPL_NVMCTRL_CONFIG_H
+#define HPL_NVMCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Settings
+
+// <o> Power Reduction Mode During Sleep
+// <0x00=> Wake On Access
+// <0x01=> Wake Up Instant
+// <0x03=> Disabled
+// <id> nvm_arch_sleepprm
+#ifndef CONF_NVM_SLEEPPRM
+#define CONF_NVM_SLEEPPRM 0
+#endif
+
+// <q> AHB0 Cache Disable
+// <i> Indicate whether AHB0 cache is disable or not
+// <id> nvm_arch_cache0
+#ifndef CONF_NVM_CACHE0
+#define CONF_NVM_CACHE0 1
+#endif
+
+// <q> AHB1 Cache Disable
+// <i> Indicate whether AHB1 cache is disable or not
+// <id> nvm_arch_cache1
+#ifndef CONF_NVM_CACHE1
+#define CONF_NVM_CACHE1 1
+#endif
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_NVMCTRL_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_osc32kctrl_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_osc32kctrl_config.h
new file mode 100644
index 000000000..d93cbf922
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_osc32kctrl_config.h
@@ -0,0 +1,163 @@
+/* Auto-generated config file hpl_osc32kctrl_config.h */
+#ifndef HPL_OSC32KCTRL_CONFIG_H
+#define HPL_OSC32KCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> RTC Source configuration
+// <id> enable_rtc_source
+#ifndef CONF_RTCCTRL_CONFIG
+#define CONF_RTCCTRL_CONFIG 0
+#endif
+
+// <h> RTC source control
+// <y> RTC Clock Source Selection
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <i> This defines the clock source for RTC
+// <id> rtc_source_oscillator
+#ifndef CONF_RTCCTRL_SRC
+#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// <q> Use 1 kHz output
+// <id> rtc_1khz_selection
+#ifndef CONF_RTCCTRL_1KHZ
+#define CONF_RTCCTRL_1KHZ 1
+#endif
+
+#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
+#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
+#else
+#error unexpected CONF_RTCCTRL_SRC
+#endif
+
+// </h>
+// </e>
+
+// <e> 32kHz External Crystal Oscillator Configuration
+// <i> Indicates whether configuration for External 32K Osc is enabled or not
+// <id> enable_xosc32k
+#ifndef CONF_XOSC32K_CONFIG
+#define CONF_XOSC32K_CONFIG 1
+#endif
+
+// <h> 32kHz External Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
+// <id> xosc32k_arch_enable
+#ifndef CONF_XOSC32K_ENABLE
+#define CONF_XOSC32K_ENABLE 1
+#endif
+
+// <o> Start-Up Time
+// <0x0=>62592us
+// <0x1=>125092us
+// <0x2=>500092us
+// <0x3=>1000092us
+// <0x4=>2000092us
+// <0x5=>4000092us
+// <0x6=>8000092us
+// <id> xosc32k_arch_startup
+#ifndef CONF_XOSC32K_STARTUP
+#define CONF_XOSC32K_STARTUP 0x0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc32k_arch_ondemand
+#ifndef CONF_XOSC32K_ONDEMAND
+#define CONF_XOSC32K_ONDEMAND 1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc32k_arch_runstdby
+#ifndef CONF_XOSC32K_RUNSTDBY
+#define CONF_XOSC32K_RUNSTDBY 0
+#endif
+
+// <q> 1kHz Output Enable
+// <i> Indicates whether 1kHz Output is enabled or not
+// <id> xosc32k_arch_en1k
+#ifndef CONF_XOSC32K_EN1K
+#define CONF_XOSC32K_EN1K 0
+#endif
+
+// <q> 32kHz Output Enable
+// <i> Indicates whether 32kHz Output is enabled or not
+// <id> xosc32k_arch_en32k
+#ifndef CONF_XOSC32K_EN32K
+#define CONF_XOSC32K_EN32K 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc32k_arch_swben
+#ifndef CONF_XOSC32K_SWBEN
+#define CONF_XOSC32K_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc32k_arch_cfden
+#ifndef CONF_XOSC32K_CFDEN
+#define CONF_XOSC32K_CFDEN 0
+#endif
+
+// <q> Clock Failure Detector Event Out
+// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
+// <id> xosc32k_arch_cfdeo
+#ifndef CONF_XOSC32K_CFDEO
+#define CONF_XOSC32K_CFDEO 0
+#endif
+
+// <q> Crystal connected to XIN32/XOUT32 Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc32k_arch_xtalen
+#ifndef CONF_XOSC32K_XTALEN
+#define CONF_XOSC32K_XTALEN 0
+#endif
+
+// <o> Control Gain Mode
+// <0x0=>Low Power mode
+// <0x1=>Standard mode
+// <0x2=>High Speed mode
+// <id> xosc32k_arch_cgm
+#ifndef CONF_XOSC32K_CGM
+#define CONF_XOSC32K_CGM 0x1
+#endif
+
+// </h>
+// </e>
+
+// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
+// <i> Indicates whether configuration for OSCULP32K is enabled or not
+// <id> enable_osculp32k
+#ifndef CONF_OSCULP32K_CONFIG
+#define CONF_OSCULP32K_CONFIG 1
+#endif
+
+// <h> 32kHz Ultra Low Power Internal Oscillator Control
+
+// <q> Oscillator Calibration Control
+// <i> Indicates whether Oscillator Calibration is enabled or not
+// <id> osculp32k_calib_enable
+#ifndef CONF_OSCULP32K_CALIB_ENABLE
+#define CONF_OSCULP32K_CALIB_ENABLE 0
+#endif
+
+// <o> Oscillator Calibration <0x0-0x3F>
+// <id> osculp32k_calib
+#ifndef CONF_OSCULP32K_CALIB
+#define CONF_OSCULP32K_CALIB 0x0
+#endif
+
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSC32KCTRL_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h
new file mode 100644
index 000000000..cd1186605
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_oscctrl_config.h
@@ -0,0 +1,634 @@
+/* Auto-generated config file hpl_oscctrl_config.h */
+#ifndef HPL_OSCCTRL_CONFIG_H
+#define HPL_OSCCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> External Multipurpose Crystal Oscillator Configuration
+// <i> Indicates whether configuration for XOSC0 is enabled or not
+// <id> enable_xosc0
+#ifndef CONF_XOSC0_CONFIG
+#define CONF_XOSC0_CONFIG 0
+#endif
+
+// <o> Frequency <8000000-48000000>
+// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// <id> xosc0_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC0_FREQUENCY 12000000
+#endif
+
+// <h> External Multipurpose Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// <id> xosc0_arch_enable
+#ifndef CONF_XOSC0_ENABLE
+#define CONF_XOSC0_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// <id> xosc0_arch_startup
+#ifndef CONF_XOSC0_STARTUP
+#define CONF_XOSC0_STARTUP 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc0_arch_swben
+#ifndef CONF_XOSC0_SWBEN
+#define CONF_XOSC0_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc0_arch_cfden
+#ifndef CONF_XOSC0_CFDEN
+#define CONF_XOSC0_CFDEN 0
+#endif
+
+// <q> Automatic Loop Control Enable
+// <i> Indicates whether Automatic Loop Control is enabled or not
+// <id> xosc0_arch_enalc
+#ifndef CONF_XOSC0_ENALC
+#define CONF_XOSC0_ENALC 0
+#endif
+
+// <q> Low Buffer Gain Enable
+// <i> Indicates whether Low Buffer Gain is enabled or not
+// <id> xosc0_arch_lowbufgain
+#ifndef CONF_XOSC0_LOWBUFGAIN
+#define CONF_XOSC0_LOWBUFGAIN 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc0_arch_ondemand
+#ifndef CONF_XOSC0_ONDEMAND
+#define CONF_XOSC0_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc0_arch_runstdby
+#ifndef CONF_XOSC0_RUNSTDBY
+#define CONF_XOSC0_RUNSTDBY 0
+#endif
+
+// <q> Crystal connected to XIN/XOUT Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc0_arch_xtalen
+#ifndef CONF_XOSC0_XTALEN
+#define CONF_XOSC0_XTALEN 0
+#endif
+//</h>
+//</e>
+
+#if CONF_XOSC0_FREQUENCY >= 32000000
+#define CONF_XOSC0_CFDPRESC 0x0
+#define CONF_XOSC0_IMULT 0x7
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 24000000
+#define CONF_XOSC0_CFDPRESC 0x1
+#define CONF_XOSC0_IMULT 0x6
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 16000000
+#define CONF_XOSC0_CFDPRESC 0x2
+#define CONF_XOSC0_IMULT 0x5
+#define CONF_XOSC0_IPTAT 0x3
+#elif CONF_XOSC0_FREQUENCY >= 8000000
+#define CONF_XOSC0_CFDPRESC 0x3
+#define CONF_XOSC0_IMULT 0x4
+#define CONF_XOSC0_IPTAT 0x3
+#endif
+
+// <e> External Multipurpose Crystal Oscillator Configuration
+// <i> Indicates whether configuration for XOSC1 is enabled or not
+// <id> enable_xosc1
+#ifndef CONF_XOSC1_CONFIG
+#define CONF_XOSC1_CONFIG 0
+#endif
+
+// <o> Frequency <8000000-48000000>
+// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// <id> xosc1_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC1_FREQUENCY 12000000
+#endif
+
+// <h> External Multipurpose Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// <id> xosc1_arch_enable
+#ifndef CONF_XOSC1_ENABLE
+#define CONF_XOSC1_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// <id> xosc1_arch_startup
+#ifndef CONF_XOSC1_STARTUP
+#define CONF_XOSC1_STARTUP 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc1_arch_swben
+#ifndef CONF_XOSC1_SWBEN
+#define CONF_XOSC1_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc1_arch_cfden
+#ifndef CONF_XOSC1_CFDEN
+#define CONF_XOSC1_CFDEN 0
+#endif
+
+// <q> Automatic Loop Control Enable
+// <i> Indicates whether Automatic Loop Control is enabled or not
+// <id> xosc1_arch_enalc
+#ifndef CONF_XOSC1_ENALC
+#define CONF_XOSC1_ENALC 0
+#endif
+
+// <q> Low Buffer Gain Enable
+// <i> Indicates whether Low Buffer Gain is enabled or not
+// <id> xosc1_arch_lowbufgain
+#ifndef CONF_XOSC1_LOWBUFGAIN
+#define CONF_XOSC1_LOWBUFGAIN 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc1_arch_ondemand
+#ifndef CONF_XOSC1_ONDEMAND
+#define CONF_XOSC1_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc1_arch_runstdby
+#ifndef CONF_XOSC1_RUNSTDBY
+#define CONF_XOSC1_RUNSTDBY 0
+#endif
+
+// <q> Crystal connected to XIN/XOUT Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc1_arch_xtalen
+#ifndef CONF_XOSC1_XTALEN
+#define CONF_XOSC1_XTALEN 0
+#endif
+//</h>
+//</e>
+
+#if CONF_XOSC1_FREQUENCY >= 32000000
+#define CONF_XOSC1_CFDPRESC 0x0
+#define CONF_XOSC1_IMULT 0x7
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 24000000
+#define CONF_XOSC1_CFDPRESC 0x1
+#define CONF_XOSC1_IMULT 0x6
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 16000000
+#define CONF_XOSC1_CFDPRESC 0x2
+#define CONF_XOSC1_IMULT 0x5
+#define CONF_XOSC1_IPTAT 0x3
+#elif CONF_XOSC1_FREQUENCY >= 8000000
+#define CONF_XOSC1_CFDPRESC 0x3
+#define CONF_XOSC1_IMULT 0x4
+#define CONF_XOSC1_IPTAT 0x3
+#endif
+
+// <e> DFLL Configuration
+// <i> Indicates whether configuration for DFLL is enabled or not
+// <id> enable_dfll
+#ifndef CONF_DFLL_CONFIG
+#define CONF_DFLL_CONFIG 0
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source
+// <id> dfll_ref_clock
+#ifndef CONF_DFLL_GCLK
+#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+// <h> Digital Frequency Locked Loop Control
+// <q> DFLL Enable
+// <i> Indicates whether DFLL is enabled or not
+// <id> dfll_arch_enable
+#ifndef CONF_DFLL_ENABLE
+#define CONF_DFLL_ENABLE 1
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> dfll_arch_ondemand
+#ifndef CONF_DFLL_ONDEMAND
+#define CONF_DFLL_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> dfll_arch_runstdby
+#ifndef CONF_DFLL_RUNSTDBY
+#define CONF_DFLL_RUNSTDBY 0
+#endif
+
+// <q> USB Clock Recovery Mode
+// <i> Indicates whether USB Clock Recovery Mode is enabled or not
+// <id> dfll_arch_usbcrm
+#ifndef CONF_DFLL_USBCRM
+#define CONF_DFLL_USBCRM 1
+#endif
+
+// <q> Wait Lock
+// <i> Indicates whether Wait Lock is enabled or not
+// <id> dfll_arch_waitlock
+#ifndef CONF_DFLL_WAITLOCK
+#define CONF_DFLL_WAITLOCK 1
+#endif
+
+// <q> Bypass Coarse Lock
+// <i> Indicates whether Bypass Coarse Lock is enabled or not
+// <id> dfll_arch_bplckc
+#ifndef CONF_DFLL_BPLCKC
+#define CONF_DFLL_BPLCKC 0
+#endif
+
+// <q> Quick Lock Disable
+// <i> Indicates whether Quick Lock Disable is enabled or not
+// <id> dfll_arch_qldis
+#ifndef CONF_DFLL_QLDIS
+#define CONF_DFLL_QLDIS 0
+#endif
+
+// <q> Chill Cycle Disable
+// <i> Indicates whether Chill Cycle Disable is enabled or not
+// <id> dfll_arch_ccdis
+#ifndef CONF_DFLL_CCDIS
+#define CONF_DFLL_CCDIS 1
+#endif
+
+// <q> Lose Lock After Wake
+// <i> Indicates whether Lose Lock After Wake is enabled or not
+// <id> dfll_arch_llaw
+#ifndef CONF_DFLL_LLAW
+#define CONF_DFLL_LLAW 0
+#endif
+
+// <q> Stable DFLL Frequency
+// <i> Indicates whether Stable DFLL Frequency is enabled or not
+// <id> dfll_arch_stable
+#ifndef CONF_DFLL_STABLE
+#define CONF_DFLL_STABLE 0
+#endif
+
+// <o> Operating Mode Selection
+// <0=>Open Loop Mode
+// <1=>Closed Loop Mode
+// <id> dfll_mode
+#ifndef CONF_DFLL_MODE
+#define CONF_DFLL_MODE 0x0
+#endif
+
+// <o> Coarse Maximum Step <0x0-0x1F>
+// <id> dfll_arch_cstep
+#ifndef CONF_DFLL_CSTEP
+#define CONF_DFLL_CSTEP 0x1
+#endif
+
+// <o> Fine Maximum Step <0x0-0xFF>
+// <id> dfll_arch_fstep
+#ifndef CONF_DFLL_FSTEP
+#define CONF_DFLL_FSTEP 0x1
+#endif
+
+// <o> DFLL Multiply Factor <0x0-0xFFFF>
+//  <id> dfll_mul
+#ifndef CONF_DFLL_MUL
+#define CONF_DFLL_MUL 0x0
+#endif
+
+// <e> DFLL Calibration Overwrite
+// <i> Indicates whether Overwrite Calibration value of DFLL
+// <id> dfll_arch_calibration
+#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
+#define CONF_DFLL_OVERWRITE_CALIBRATION 0
+#endif
+
+// <o> Coarse Value <0x0-0x3F>
+// <id> dfll_arch_coarse
+#ifndef CONF_DFLL_COARSE
+#define CONF_DFLL_COARSE (0x1f / 4)
+#endif
+
+// <o> Fine Value <0x0-0xFF>
+// <id> dfll_arch_fine
+#ifndef CONF_DFLL_FINE
+#define CONF_DFLL_FINE (0x80)
+#endif
+
+//</e>
+
+//</h>
+
+//</e>
+
+// <e> FDPLL0 Configuration
+// <i> Indicates whether configuration for FDPLL0 is enabled or not
+// <id> enable_fdpll0
+#ifndef CONF_FDPLL0_CONFIG
+#define CONF_FDPLL0_CONFIG 1
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source.
+// <id> fdpll0_ref_clock
+#ifndef CONF_FDPLL0_GCLK
+#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK5_Val
+#endif
+
+// <h> Digital Phase Locked Loop Control
+// <q> Enable
+// <i> Indicates whether Digital Phase Locked Loop is enabled or not
+// <id> fdpll0_arch_enable
+#ifndef CONF_FDPLL0_ENABLE
+#define CONF_FDPLL0_ENABLE 1
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> fdpll0_arch_ondemand
+#ifndef CONF_FDPLL0_ONDEMAND
+#define CONF_FDPLL0_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> fdpll0_arch_runstdby
+#ifndef CONF_FDPLL0_RUNSTDBY
+#define CONF_FDPLL0_RUNSTDBY 0
+#endif
+
+// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <id> fdpll0_ldrfrac
+#ifndef CONF_FDPLL0_LDRFRAC
+#define CONF_FDPLL0_LDRFRAC 0x0
+#endif
+
+// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <id> fdpll0_ldr
+#ifndef CONF_FDPLL0_LDR
+#define CONF_FDPLL0_LDR 59
+#endif
+
+// <o> Clock Divider <0x0-0x7FF>
+// <id> fdpll0_clock_div
+#ifndef CONF_FDPLL0_DIV
+#define CONF_FDPLL0_DIV 0x0
+#endif
+
+// <q> DCO Filter Enable
+// <i> Indicates whether DCO Filter Enable is enabled or not
+// <id> fdpll0_arch_dcoen
+#ifndef CONF_FDPLL0_DCOEN
+#define CONF_FDPLL0_DCOEN 0
+#endif
+
+// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
+// <id> fdpll0_clock_dcofilter
+#ifndef CONF_FDPLL0_DCOFILTER
+#define CONF_FDPLL0_DCOFILTER 0x0
+#endif
+
+// <q> Lock Bypass
+// <i> Indicates whether Lock Bypass is enabled or not
+// <id> fdpll0_arch_lbypass
+#ifndef CONF_FDPLL0_LBYPASS
+#define CONF_FDPLL0_LBYPASS 0
+#endif
+
+// <o> Lock Time
+// <0x0=>No time-out, automatic lock
+// <0x4=>The Time-out if no lock within 800 us
+// <0x5=>The Time-out if no lock within 900 us
+// <0x6=>The Time-out if no lock within 1 ms
+// <0x7=>The Time-out if no lock within 11 ms
+// <id> fdpll0_arch_ltime
+#ifndef CONF_FDPLL0_LTIME
+#define CONF_FDPLL0_LTIME 0x0
+#endif
+
+// <o> Reference Clock Selection
+// <0x0=>GCLK clock reference
+// <0x1=>XOSC32K clock reference
+// <0x2=>XOSC0 clock reference
+// <0x3=>XOSC1 clock reference
+// <id> fdpll0_arch_refclk
+#ifndef CONF_FDPLL0_REFCLK
+#define CONF_FDPLL0_REFCLK 0x0
+#endif
+
+// <q> Wake Up Fast
+// <i> Indicates whether Wake Up Fast is enabled or not
+// <id> fdpll0_arch_wuf
+#ifndef CONF_FDPLL0_WUF
+#define CONF_FDPLL0_WUF 0
+#endif
+
+// <o> Proportional Integral Filter Selection <0x0-0xF>
+// <id> fdpll0_arch_filter
+#ifndef CONF_FDPLL0_FILTER
+#define CONF_FDPLL0_FILTER 0x0
+#endif
+
+//</h>
+//</e>
+// <e> FDPLL1 Configuration
+// <i> Indicates whether configuration for FDPLL1 is enabled or not
+// <id> enable_fdpll1
+#ifndef CONF_FDPLL1_CONFIG
+#define CONF_FDPLL1_CONFIG 0
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+// <i> Select the clock source.
+// <id> fdpll1_ref_clock
+#ifndef CONF_FDPLL1_GCLK
+#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// <h> Digital Phase Locked Loop Control
+// <q> Enable
+// <i> Indicates whether Digital Phase Locked Loop is enabled or not
+// <id> fdpll1_arch_enable
+#ifndef CONF_FDPLL1_ENABLE
+#define CONF_FDPLL1_ENABLE 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> fdpll1_arch_ondemand
+#ifndef CONF_FDPLL1_ONDEMAND
+#define CONF_FDPLL1_ONDEMAND 0
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> fdpll1_arch_runstdby
+#ifndef CONF_FDPLL1_RUNSTDBY
+#define CONF_FDPLL1_RUNSTDBY 0
+#endif
+
+// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <id> fdpll1_ldrfrac
+#ifndef CONF_FDPLL1_LDRFRAC
+#define CONF_FDPLL1_LDRFRAC 0xd
+#endif
+
+// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <id> fdpll1_ldr
+#ifndef CONF_FDPLL1_LDR
+#define CONF_FDPLL1_LDR 0x5b7
+#endif
+
+// <o> Clock Divider <0x0-0x7FF>
+// <id> fdpll1_clock_div
+#ifndef CONF_FDPLL1_DIV
+#define CONF_FDPLL1_DIV 0x0
+#endif
+
+// <q> DCO Filter Enable
+// <i> Indicates whether DCO Filter Enable is enabled or not
+// <id> fdpll1_arch_dcoen
+#ifndef CONF_FDPLL1_DCOEN
+#define CONF_FDPLL1_DCOEN 0
+#endif
+
+// <o> Sigma-Delta DCO Filter Selection <0x0-0x7>
+// <id> fdpll1_clock_dcofilter
+#ifndef CONF_FDPLL1_DCOFILTER
+#define CONF_FDPLL1_DCOFILTER 0x0
+#endif
+
+// <q> Lock Bypass
+// <i> Indicates whether Lock Bypass is enabled or not
+// <id> fdpll1_arch_lbypass
+#ifndef CONF_FDPLL1_LBYPASS
+#define CONF_FDPLL1_LBYPASS 0
+#endif
+
+// <o> Lock Time
+// <0x0=>No time-out, automatic lock
+// <0x4=>The Time-out if no lock within 800 us
+// <0x5=>The Time-out if no lock within 900 us
+// <0x6=>The Time-out if no lock within 1 ms
+// <0x7=>The Time-out if no lock within 11 ms
+// <id> fdpll1_arch_ltime
+#ifndef CONF_FDPLL1_LTIME
+#define CONF_FDPLL1_LTIME 0x0
+#endif
+
+// <o> Reference Clock Selection
+// <0x0=>GCLK clock reference
+// <0x1=>XOSC32K clock reference
+// <0x2=>XOSC0 clock reference
+// <0x3=>XOSC1 clock reference
+// <id> fdpll1_arch_refclk
+#ifndef CONF_FDPLL1_REFCLK
+#define CONF_FDPLL1_REFCLK 0x1
+#endif
+
+// <q> Wake Up Fast
+// <i> Indicates whether Wake Up Fast is enabled or not
+// <id> fdpll1_arch_wuf
+#ifndef CONF_FDPLL1_WUF
+#define CONF_FDPLL1_WUF 0
+#endif
+
+// <o> Proportional Integral Filter Selection <0x0-0xF>
+// <id> fdpll1_arch_filter
+#ifndef CONF_FDPLL1_FILTER
+#define CONF_FDPLL1_FILTER 0x0
+#endif
+
+//</h>
+//</e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSCCTRL_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_rtc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_rtc_config.h
new file mode 100644
index 000000000..2b0b6712e
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_rtc_config.h
@@ -0,0 +1,145 @@
+/* Auto-generated config file hpl_rtc_config.h */
+#ifndef HPL_RTC_CONFIG_H
+#define HPL_RTC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic settings
+
+#ifndef CONF_RTC_ENABLE
+#define CONF_RTC_ENABLE 1
+#endif
+
+// <q> Force reset RTC on initialization
+// <i> Force RTC to reset on initialization.
+// <i> Note that the previous power down data in RTC is lost if it's enabled.
+// <id> rtc_arch_init_reset
+#ifndef CONF_RTC_INIT_RESET
+#define CONF_RTC_INIT_RESET 0
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>OFF(Peripheral clock divided by 1)
+// <0x1=>Peripheral clock divided by 1
+// <0x2=>Peripheral clock divided by 2
+// <0x3=>Peripheral clock divided by 4
+// <0x4=>Peripheral clock divided by 8
+// <0x5=>Peripheral clock divided by 16
+// <0x6=>Peripheral clock divided by 32
+// <0x7=>Peripheral clock divided by 64
+// <0x8=>Peripheral clock divided by 128
+// <0x9=>Peripheral clock divided by 256
+// <0xA=>Peripheral clock divided by 512
+// <0xB=>Peripheral clock divided by 1024
+// <i> These bits define the RTC clock relative to the peripheral clock
+// <id> rtc_arch_prescaler
+#ifndef CONF_RTC_PRESCALER
+#define CONF_RTC_PRESCALER 0xb
+
+#endif
+
+// <o> Compare Value <1-4294967295>
+// <i> These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value),
+// <i> by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms.
+// <id> rtc_arch_comp_val
+
+#ifndef CONF_RTC_COMP_VAL
+#define CONF_RTC_COMP_VAL 1
+
+#endif
+
+// <e> Event control
+// <id> rtc_event_control
+#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
+#define CONF_RTC_EVENT_CONTROL_ENABLE 0
+#endif
+
+// <q> Periodic Interval 0 Event Output
+// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
+// <id> rtc_pereo0
+#ifndef CONF_RTC_PEREO0
+#define CONF_RTC_PEREO0 0
+#endif
+// <q> Periodic Interval 1 Event Output
+// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
+// <id> rtc_pereo1
+#ifndef CONF_RTC_PEREO1
+#define CONF_RTC_PEREO1 0
+#endif
+// <q> Periodic Interval 2 Event Output
+// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
+// <id> rtc_pereo2
+#ifndef CONF_RTC_PEREO2
+#define CONF_RTC_PEREO2 0
+#endif
+// <q> Periodic Interval 3 Event Output
+// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
+// <id> rtc_pereo3
+#ifndef CONF_RTC_PEREO3
+#define CONF_RTC_PEREO3 0
+#endif
+// <q> Periodic Interval 4 Event Output
+// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
+// <id> rtc_pereo4
+#ifndef CONF_RTC_PEREO4
+#define CONF_RTC_PEREO4 0
+#endif
+// <q> Periodic Interval 5 Event Output
+// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
+// <id> rtc_pereo5
+#ifndef CONF_RTC_PEREO5
+#define CONF_RTC_PEREO5 0
+#endif
+// <q> Periodic Interval 6 Event Output
+// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
+// <id> rtc_pereo6
+#ifndef CONF_RTC_PEREO6
+#define CONF_RTC_PEREO6 0
+#endif
+// <q> Periodic Interval 7 Event Output
+// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
+// <id> rtc_pereo7
+#ifndef CONF_RTC_PEREO7
+#define CONF_RTC_PEREO7 0
+#endif
+
+// <q> Compare 0 Event Output
+// <i> This bit indicates whether Compare O event is enabled and will be generated
+// <id> rtc_cmpeo0
+#ifndef CONF_RTC_COMPE0
+#define CONF_RTC_COMPE0 0
+#endif
+
+// <q> Compare 1 Event Output
+// <i> This bit indicates whether Compare 1 event is enabled and will be generated
+// <id> rtc_cmpeo1
+#ifndef CONF_RTC_COMPE1
+#define CONF_RTC_COMPE1 0
+#endif
+// <q> Overflow Event Output
+// <i> This bit indicates whether Overflow event is enabled and will be generated
+// <id> rtc_ovfeo
+#ifndef CONF_RTC_OVFEO
+#define CONF_RTC_OVFEO 0
+#endif
+
+// <q> Tamper Event Output
+// <i> This bit indicates whether Tamper event output is enabled and will be generated
+// <id> rtc_tampereo
+#ifndef CONF_RTC_TAMPEREO
+#define CONF_RTC_TAMPEREO 0
+#endif
+
+// <q> Tamper Event Input
+// <i> This bit indicates whether Tamper event input is enabled and will be generated
+// <id> rtc_tampevei
+#ifndef CONF_RTC_TAMPEVEI
+#define CONF_RTC_TAMPEVEI 0
+#endif
+// </e>
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_RTC_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_sdhc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_sdhc_config.h
new file mode 100644
index 000000000..daa662051
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_sdhc_config.h
@@ -0,0 +1,24 @@
+/* Auto-generated config file hpl_sdhc_config.h */
+#ifndef HPL_SDHC_CONFIG_H
+#define HPL_SDHC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include "peripheral_clk_config.h"
+
+#ifndef CONF_BASE_FREQUENCY
+#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
+#endif
+
+// <o> Clock Generator Select
+// <0=> Divided Clock mode
+// <1=> Programmable Clock mode
+// <i> This defines the clock generator mode in the SDCLK Frequency Select field
+// <id> sdhc_clk_gsel
+#ifndef CONF_SDHC0_CLK_GEN_SEL
+#define CONF_SDHC0_CLK_GEN_SEL 0
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SDHC_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h
new file mode 100644
index 000000000..cd411154c
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_sercom_config.h
@@ -0,0 +1,751 @@
+// For CircuitPython, use SERCOM settings as prototypes to set
+// the default settings. This file defines these SERCOMs
+//
+// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous
+// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous
+// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous
+// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA
+
+#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0
+#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY
+
+#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1
+
+#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2
+#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY
+
+/* Auto-generated config file hpl_sercom_config.h */
+#ifndef HPL_SERCOM_CONFIG_H
+#define HPL_SERCOM_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_0_SPI_ENABLE
+#define CONF_SERCOM_0_SPI_ENABLE 1
+#endif
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_0_SPI_MODE
+#define CONF_SERCOM_0_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_0_SPI_RXEN
+#define CONF_SERCOM_0_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_0_SPI_CHSIZE
+#define CONF_SERCOM_0_SPI_CHSIZE 0x0
+#endif
+
+// <o> Baud rate <1-12000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_0_SPI_BAUD
+#define CONF_SERCOM_0_SPI_BAUD 50000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_0_SPI_ADVANCED
+#define CONF_SERCOM_0_SPI_ADVANCED 1
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE
+#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_0_SPI_DORD
+#define CONF_SERCOM_0_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_0_SPI_CPOL
+#define CONF_SERCOM_0_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_0_SPI_CPHA
+#define CONF_SERCOM_0_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_0_SPI_IBON
+#define CONF_SERCOM_0_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_0_SPI_RUNSTDBY
+#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_0_SPI_DBGSTOP
+#define CONF_SERCOM_0_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_0_SPI_AMODE_EN
+#define CONF_SERCOM_0_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_AMODE
+#define CONF_SERCOM_0_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_ADDR
+#define CONF_SERCOM_0_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_ADDRMASK
+#define CONF_SERCOM_0_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_SSDE
+#define CONF_SERCOM_0_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_MSSEN
+#define CONF_SERCOM_0_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_0_SPI_PLOADEN
+#define CONF_SERCOM_0_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_0_SPI_RXPO
+#define CONF_SERCOM_0_SPI_RXPO 2
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_0_SPI_TXPO
+#define CONF_SERCOM_0_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_0_SPI_BAUD_RATE
+#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1
+#endif
+
+#include <peripheral_clk_config.h>
+
+#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#endif
+
+#ifndef CONF_SERCOM_1_I2CM_ENABLE
+#define CONF_SERCOM_1_I2CM_ENABLE 1
+#endif
+
+// <h> Basic
+
+// <o> I2C Bus clock speed (Hz) <1-400000>
+// <i> I2C Bus clock (SCL) speed measured in Hz
+// <id> i2c_master_baud_rate
+#ifndef CONF_SERCOM_1_I2CM_BAUD
+#define CONF_SERCOM_1_I2CM_BAUD 100000
+#endif
+
+// </h>
+
+// <e> Advanced
+// <id> i2c_master_advanced
+#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
+#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 1
+#endif
+
+// <o> TRise (ns) <0-300>
+// <i> Determined by the bus impedance, check electric characteristics in the datasheet
+// <i> Standard Fast Mode: typical 215ns, max 300ns
+// <i> Fast Mode +: typical 60ns, max 100ns
+// <i> High Speed Mode: typical 20ns, max 40ns
+// <id> i2c_master_arch_trise
+
+#ifndef CONF_SERCOM_1_I2CM_TRISE
+#define CONF_SERCOM_1_I2CM_TRISE 215
+#endif
+
+// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
+// <i> This enables the master SCL low extend time-out
+// <id> i2c_master_arch_mexttoen
+#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
+#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
+#endif
+
+// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
+// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
+// <id> i2c_master_arch_sexttoen
+#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
+#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
+#endif
+
+// <q> SCL Low Time-Out (LOWTOUT)
+// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
+// <id> i2c_master_arch_lowtout
+#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
+#define CONF_SERCOM_1_I2CM_LOWTOUT 0
+#endif
+
+// <o> Inactive Time-Out (INACTOUT)
+// <0x0=>Disabled
+// <0x1=>5-6 SCL cycle time-out(50-60us)
+// <0x2=>10-11 SCL cycle time-out(100-110us)
+// <0x3=>20-21 SCL cycle time-out(200-210us)
+// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
+// <id> i2c_master_arch_inactout
+#ifndef CONF_SERCOM_1_I2CM_INACTOUT
+#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
+#endif
+
+// <o> SDA Hold Time (SDAHOLD)
+// <0=>Disabled
+// <1=>50-100ns hold time
+// <2=>300-600ns hold time
+// <3=>400-800ns hold time
+// <i> Defines the SDA hold time with respect to the negative edge of SCL
+// <id> i2c_master_arch_sdahold
+#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
+#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
+#endif
+
+// <q> Run in stand-by
+// <i> Determine if the module shall run in standby sleep mode
+// <id> i2c_master_arch_runstdby
+#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
+#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> i2c_master_arch_dbgstop
+#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
+#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
+#endif
+
+// </e>
+
+#ifndef CONF_SERCOM_1_I2CM_SPEED
+#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#endif
+#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#undef CONF_SERCOM_1_I2CM_TRISE
+#define CONF_SERCOM_1_I2CM_TRISE 215
+#endif
+
+//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
+// BAUD + BAUDLOW = --------------------------------------------------------------------
+//                  i2c_scl_freq
+// BAUD:    register value low  [7:0]
+// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
+#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW                                                                                \
+	(((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10)                                               \
+	   - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000)      \
+	      / 1000))                                                                                                     \
+	      * 10                                                                                                         \
+	  + 5)                                                                                                             \
+	 / (CONF_SERCOM_1_I2CM_BAUD * 10))
+#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
+#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
+#warning Requested I2C baudrate too low, please check
+#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
+#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
+#warning Requested I2C baudrate too high, please check
+#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
+#else
+#define CONF_SERCOM_1_I2CM_BAUD_RATE                                                                                   \
+	((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
+	     ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
+	     : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
+#endif
+#endif
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_SERCOM_2_USART_ENABLE
+#define CONF_SERCOM_2_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_2_USART_RXEN
+#define CONF_SERCOM_2_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_2_USART_TXEN
+#define CONF_SERCOM_2_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x0=>No parity
+// <0x1=>Even parity
+// <0x2=>Odd parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_2_USART_PARITY
+#define CONF_SERCOM_2_USART_PARITY 0x0
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_2_USART_CHSIZE
+#define CONF_SERCOM_2_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_2_USART_SBMODE
+#define CONF_SERCOM_2_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_2_USART_BAUD
+#define CONF_SERCOM_2_USART_BAUD 9600
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 1
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_2_USART_RUNSTDBY
+#define CONF_SERCOM_2_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_2_USART_IBON
+#define CONF_SERCOM_2_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_2_USART_SFDE
+#define CONF_SERCOM_2_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_2_USART_CLODEN
+#define CONF_SERCOM_2_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x0=>USART with external clock
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_2_USART_MODE
+#define CONF_SERCOM_2_USART_MODE 0x1
+#endif
+
+// <o> Sample Rate
+// <0x0=>16x arithmetic
+// <0x1=>16x fractional
+// <0x2=>8x arithmetic
+// <0x3=>8x fractional
+// <0x3=>3x
+// <i> How many over-sampling bits used when samling data state
+// <id> usart_arch_sampr
+#ifndef CONF_SERCOM_2_USART_SAMPR
+#define CONF_SERCOM_2_USART_SAMPR 0x0
+#endif
+
+// <o> Sample Adjustment
+// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
+// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
+// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
+// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
+// <i> Adjust which samples to use for data sampling in asynchronous mode
+// <id> usart_arch_sampa
+#ifndef CONF_SERCOM_2_USART_SAMPA
+#define CONF_SERCOM_2_USART_SAMPA 0x0
+#endif
+
+// <o> Fractional Part <0-7>
+// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
+// <id> usart_arch_fractional
+#ifndef CONF_SERCOM_2_USART_FRACTIONAL
+#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_2_USART_DORD
+#define CONF_SERCOM_2_USART_DORD 1
+#endif
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_2_USART_CPOL 0
+
+// <o> Encoding Format
+// <0=>No encoding
+// <1=>IrDA encoded
+// <id> usart_arch_enc
+#ifndef CONF_SERCOM_2_USART_ENC
+#define CONF_SERCOM_2_USART_ENC 0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
+#endif
+
+// </e>
+
+#ifndef CONF_SERCOM_2_USART_INACK
+#define CONF_SERCOM_2_USART_INACK 0x0
+#endif
+
+#ifndef CONF_SERCOM_2_USART_DSNACK
+#define CONF_SERCOM_2_USART_DSNACK 0x0
+#endif
+
+#ifndef CONF_SERCOM_2_USART_MAXITER
+#define CONF_SERCOM_2_USART_MAXITER 0x7
+#endif
+
+#ifndef CONF_SERCOM_2_USART_GTIME
+#define CONF_SERCOM_2_USART_GTIME 0x2
+#endif
+
+#define CONF_SERCOM_2_USART_RXINV 0x0
+#define CONF_SERCOM_2_USART_TXINV 0x0
+
+#ifndef CONF_SERCOM_2_USART_CMODE
+#define CONF_SERCOM_2_USART_CMODE 0
+#endif
+
+#ifndef CONF_SERCOM_2_USART_RXPO
+#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA08 */
+#endif
+
+#ifndef CONF_SERCOM_2_USART_TXPO
+#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA09 */
+#endif
+
+/* Set correct parity settings in register interface based on PARITY setting */
+#if CONF_SERCOM_2_USART_PARITY == 0
+#define CONF_SERCOM_2_USART_PMODE 0
+#define CONF_SERCOM_2_USART_FORM 0
+#else
+#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
+#define CONF_SERCOM_2_USART_FORM 1
+#endif
+
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_2_USART_SAMPR == 0
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 1
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 2
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 3
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 4
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_3_SPI_ENABLE
+#define CONF_SERCOM_3_SPI_ENABLE 1
+#endif
+
+//<o> SPI DMA TX Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_tx_channel
+#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL
+#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0
+#endif
+
+// <e> SPI RX Channel Enable
+// <id> spi_master_rx_channel
+#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL
+#define CONF_SERCOM_3_SPI_RX_CHANNEL 1
+#endif
+
+//<o> DMA Channel <0-32>
+//<i> This defines DMA channel to be used
+//<id> spi_master_dma_rx_channel
+#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL
+#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1
+#endif
+
+// </e>
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_3_SPI_MODE
+#define CONF_SERCOM_3_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_3_SPI_RXEN
+#define CONF_SERCOM_3_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_3_SPI_CHSIZE
+#define CONF_SERCOM_3_SPI_CHSIZE 0x0
+#endif
+
+// <o> Baud rate <1-12000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_3_SPI_BAUD
+#define CONF_SERCOM_3_SPI_BAUD 50000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_3_SPI_ADVANCED
+#define CONF_SERCOM_3_SPI_ADVANCED 0
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE
+#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_3_SPI_DORD
+#define CONF_SERCOM_3_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_3_SPI_CPOL
+#define CONF_SERCOM_3_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_3_SPI_CPHA
+#define CONF_SERCOM_3_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_3_SPI_IBON
+#define CONF_SERCOM_3_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_3_SPI_RUNSTDBY
+#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_3_SPI_DBGSTOP
+#define CONF_SERCOM_3_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_3_SPI_AMODE_EN
+#define CONF_SERCOM_3_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_AMODE
+#define CONF_SERCOM_3_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_ADDR
+#define CONF_SERCOM_3_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_ADDRMASK
+#define CONF_SERCOM_3_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_SSDE
+#define CONF_SERCOM_3_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_MSSEN
+#define CONF_SERCOM_3_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_PLOADEN
+#define CONF_SERCOM_3_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_3_SPI_RXPO
+#define CONF_SERCOM_3_SPI_RXPO 2
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_3_SPI_TXPO
+#define CONF_SERCOM_3_SPI_TXPO 0
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_3_SPI_BAUD_RATE
+#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SERCOM_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_systick_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_systick_config.h
new file mode 100644
index 000000000..a7f2f3620
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_systick_config.h
@@ -0,0 +1,18 @@
+/* Auto-generated config file hpl_systick_config.h */
+#ifndef HPL_SYSTICK_CONFIG_H
+#define HPL_SYSTICK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Advanced settings
+// <q> SysTick exception request
+// <i> Indicates whether the generation of SysTick exception is enabled or not
+// <id> systick_arch_tickint
+#ifndef CONF_SYSTICK_TICKINT
+#define CONF_SYSTICK_TICKINT 0
+#endif
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SYSTICK_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h
new file mode 100644
index 000000000..38d48e9b6
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_tc_config.h
@@ -0,0 +1,209 @@
+/* Auto-generated config file hpl_tc_config.h */
+#ifndef HPL_TC_CONFIG_H
+#define HPL_TC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_TC0_ENABLE
+#define CONF_TC0_ENABLE 1
+#endif
+
+// <h> Basic settings
+// <o> Prescaler
+// <0=> No division
+// <1=> Divide by 2
+// <2=> Divide by 4
+// <3=> Divide by 8
+// <4=> Divide by 16
+// <5=> Divide by 64
+// <6=> Divide by 256
+// <7=> Divide by 1024
+// <i> This defines the prescaler value
+// <id> tc_prescaler
+#ifndef CONF_TC0_PRESCALER
+#define CONF_TC0_PRESCALER 0
+#endif
+// </h>
+
+// <h> PWM Waveform Output settings
+// <o> Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// <i> The unit of this value is us.
+// <id> tc_arch_wave_per_val
+#ifndef CONF_TC0_WAVE_PER_VAL
+#define CONF_TC0_WAVE_PER_VAL 0x3e8
+#endif
+
+// <o> Waveform Duty Value (0.1%) <0x00-0x03E8>
+// <i> The unit of this value is 1/1000.
+// <id> tc_arch_wave_duty_val
+#ifndef CONF_TC0_WAVE_DUTY_VAL
+#define CONF_TC0_WAVE_DUTY_VAL 0x1f4
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TC0_CC0                                                                                                   \
+	((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1))
+#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 64000000 - 1))
+#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 256000000 - 1))
+#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1024000000 - 1))
+#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000)
+#endif
+
+// </h>
+
+// <h> Advanced settings
+// <y> Mode
+// <TC_CTRLA_MODE_COUNT16_Val"> Counter in 16-bit mode
+// <TC_CTRLA_MODE_COUNT32_Val"> Counter in 32-bit mode
+// <i> These bits mode
+// <id> tc_mode
+#ifndef CONF_TC0_MODE
+#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT16_Val
+#endif
+
+// <o> Period Value <0x00000000-0xFFFFFFFF>
+// <id> tc_per
+#ifndef CONF_TC0_PER
+#define CONF_TC0_PER 0x32
+#endif
+// </h>
+
+// <h> Advanced settings
+// <y> Prescaler and Counter Synchronization Selection
+// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
+// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
+// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
+// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
+// <id> tc_arch_presync
+#ifndef CONF_TC0_PRESCSYNC
+#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the will continue running in standby sleep mode or not
+// <id> tc_arch_runstdby
+#ifndef CONF_TC0_RUNSTDBY
+#define CONF_TC0_RUNSTDBY 0
+#endif
+
+// <q> On-Demand
+// <i> Indicates whether the TC0's on-demand mode is on or not
+// <id> tc_arch_ondemand
+#ifndef CONF_TC0_ONDEMAND
+#define CONF_TC0_ONDEMAND 0
+#endif
+
+// <o> Auto Lock
+// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event
+// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event
+// <id> tc_arch_alock
+#ifndef CONF_TC0_ALOCK
+#define CONF_TC0_ALOCK 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC0_CAPTEN0 0
+//#define CONF_TC0_CAPTEN1 0
+//#define CONF_TC0_COPEN0  0
+//#define CONF_TC0_COPEN1  0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC0_DIR     0
+//#define CONF_TC0_ONESHOT 0
+//#define CONF_TC0_LUPD    0
+
+// <q> Debug Running Mode
+// <i> Indicates whether the Debug Running Mode is enabled or not
+// <id> tc_arch_dbgrun
+#ifndef CONF_TC0_DBGRUN
+#define CONF_TC0_DBGRUN 0
+#endif
+
+// <e> Event control
+// <id> timer_event_control
+#ifndef CONF_TC0_EVENT_CONTROL_ENABLE
+#define CONF_TC0_EVENT_CONTROL_ENABLE 0
+#endif
+
+// <q> Output Event On Match or Capture on Channel 0
+// <i> Enable output of event on timer tick
+// <id> tc_arch_mceo0
+#ifndef CONF_TC0_MCEO0
+#define CONF_TC0_MCEO0 0
+#endif
+
+// <q> Output Event On Match or Capture on Channel 1
+// <i> Enable output of event on timer tick
+// <id> tc_arch_mceo1
+#ifndef CONF_TC0_MCEO1
+#define CONF_TC0_MCEO1 0
+#endif
+
+// <q> Output Event On Timer Tick
+// <i> Enable output of event on timer tick
+// <id> tc_arch_ovfeo
+#ifndef CONF_TC0_OVFEO
+#define CONF_TC0_OVFEO 0
+#endif
+
+// <q> Event Input
+// <i> Enable asynchronous input events
+// <id> tc_arch_tcei
+#ifndef CONF_TC0_TCEI
+#define CONF_TC0_TCEI 0
+#endif
+
+// <q> Inverted Event Input
+// <i> Invert the asynchronous input events
+// <id> tc_arch_tcinv
+#ifndef CONF_TC0_TCINV
+#define CONF_TC0_TCINV 0
+#endif
+
+// <o> Event action
+// <0=> Event action disabled
+// <1=> Start, restart or re-trigger TC on event
+// <2=> Count on event
+// <3=> Start on event
+// <4=> Time stamp capture
+// <5=> Period captured in CC0, pulse width in CC1
+// <6=> Period captured in CC1, pulse width in CC0
+// <7=> Pulse width capture
+// <i> Event which will be performed on an event
+//<id> tc_arch_evact
+#ifndef CONF_TC0_EVACT
+#define CONF_TC0_EVACT 0
+#endif
+// </e>
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC0_WAVEGEN   TC_CTRLA_WAVEGEN_MFRQ_Val
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC0_INVEN0 0
+//#define CONF_TC0_INVEN1 0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC0_PERBUF 0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC0_CCBUF0 0
+//#define CONF_TC0_CCBUF1 0
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TC_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_trng_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_trng_config.h
new file mode 100644
index 000000000..ba9014989
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_trng_config.h
@@ -0,0 +1,27 @@
+/* Auto-generated config file hpl_trng_config.h */
+#ifndef HPL_TRNG_CONFIG_H
+#define HPL_TRNG_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Advanced configurations
+
+// <q> Run In Standby
+// <i> Indicates whether the TRNG works in standby mode
+// <id> trng_runstdby
+#ifndef CONF_TRNG_RUNSTDBY
+#define CONF_TRNG_RUNSTDBY 0
+#endif
+
+// <q> Data Ready Event Output Enable
+// <i> Indicates whether the TRNG generates event on Data Ready
+// <id> trng_datardyeo
+#ifndef CONF_TRNG_DATARDYEO
+#define CONF_TRNG_DATARDYEO 0
+#endif
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TRNG_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_usb_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_usb_config.h
new file mode 100644
index 000000000..d1bb42fe4
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/hpl_usb_config.h
@@ -0,0 +1,413 @@
+/* Auto-generated config file hpl_usb_config.h */
+#ifndef HPL_USB_CONFIG_H
+#define HPL_USB_CONFIG_H
+
+// CIRCUITPY:
+
+// Use 64-byte USB buffers for endpoint directions that are in use. They're set to 0 below otherwise.
+
+#include "genhdr/autogen_usb_descriptor.h"
+
+#if defined(USB_ENDPOINT_1_OUT_USED) && USB_ENDPOINT_1_OUT_USED
+#define CONF_USB_EP1_CACHE 64
+#endif
+#if defined(USB_ENDPOINT_1_IN_USED) && USB_ENDPOINT_1_IN_USED
+#define CONF_USB_EP1_I_CACHE 64
+#endif
+
+#if defined(USB_ENDPOINT_2_OUT_USED) && USB_ENDPOINT_2_OUT_USED
+#define CONF_USB_EP2_CACHE 64
+#endif
+#if defined(USB_ENDPOINT_2_IN_USED) && USB_ENDPOINT_2_IN_USED
+#define CONF_USB_EP2_I_CACHE 64
+#endif
+
+#if defined(USB_ENDPOINT_3_OUT_USED) && USB_ENDPOINT_3_OUT_USED
+#define CONF_USB_EP3_CACHE 64
+#endif
+#if defined(USB_ENDPOINT_3_IN_USED) && USB_ENDPOINT_3_IN_USED
+#define CONF_USB_EP3_I_CACHE 64
+#endif
+
+#if defined(USB_ENDPOINT_4_OUT_USED) && USB_ENDPOINT_4_OUT_USED
+#define CONF_USB_EP4_CACHE 64
+#endif
+#if defined(USB_ENDPOINT_4_IN_USED) && USB_ENDPOINT_4_IN_USED
+#define CONF_USB_EP4_I_CACHE 64
+#endif
+
+#if defined(USB_ENDPOINT_5_OUT_USED) && USB_ENDPOINT_5_OUT_USED
+#define CONF_USB_EP5_CACHE 64
+#endif
+#if defined(USB_ENDPOINT_5_IN_USED) && USB_ENDPOINT_5_IN_USED
+#define CONF_USB_EP5_I_CACHE 64
+#endif
+
+#if defined(USB_ENDPOINT_6_OUT_USED) && USB_ENDPOINT_6_OUT_USED
+#define CONF_USB_EP6_CACHE 64
+#endif
+#if defined(USB_ENDPOINT_6_IN_USED) && USB_ENDPOINT_6_IN_USED
+#define CONF_USB_EP6_I_CACHE 64
+#endif
+
+#if defined(USB_ENDPOINT_7_OUT_USED) && USB_ENDPOINT_7_OUT_USED
+#define CONF_USB_EP7_CACHE 64
+#endif
+#if defined(USB_ENDPOINT_7_IN_USED) && USB_ENDPOINT_7_IN_USED
+#define CONF_USB_EP7_I_CACHE 64
+#endif
+
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#define CONF_USB_N_0 0
+#define CONF_USB_N_1 1
+#define CONF_USB_N_2 2
+#define CONF_USB_N_3 3
+#define CONF_USB_N_4 4
+#define CONF_USB_N_5 5
+#define CONF_USB_N_6 6
+#define CONF_USB_N_7 7
+#define CONF_USB_N_8 8
+#define CONF_USB_N_9 9
+#define CONF_USB_N_10 10
+#define CONF_USB_N_11 11
+#define CONF_USB_N_12 12
+#define CONF_USB_N_13 13
+#define CONF_USB_N_14 14
+#define CONF_USB_N_15 15
+
+#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1)
+#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1)
+
+// <h> USB Device HAL Configuration
+
+// <y> Max number of endpoints supported
+// <i> Limits the number of endpoints (described by EP address) can be used in app.
+// NOTE(tannewt): This not only limits the number of endpoints but also the
+// addresses. In other words, even if you use endpoint 6 you need to set this to 11.
+// <CONF_USB_N_1"> 1 (EP0 only)
+// <CONF_USB_N_2"> 2 (EP0 + 1 endpoint)
+// <CONF_USB_N_3"> 3 (EP0 + 2 endpoints)
+// <CONF_USB_N_4"> 4 (EP0 + 3 endpoints)
+// <CONF_USB_N_5"> 5 (EP0 + 4 endpoints)
+// <CONF_USB_N_6"> 6 (EP0 + 5 endpoints)
+// <CONF_USB_N_7"> 7 (EP0 + 6 endpoints)
+// <CONF_USB_N_8"> 8 (EP0 + 7 endpoints)
+// <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config)
+// <id> usbd_num_ep_sp
+#ifndef CONF_USB_D_NUM_EP_SP
+#define CONF_USB_D_NUM_EP_SP CONF_USB_D_N_EP_MAX
+#endif
+
+// </h>
+
+// <y> Max Endpoint Number supported
+// <i> Limits the max endpoint number.
+// <i> USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1.
+// <i> Reduce the value according to specific device design, to cut-off memory usage.
+// <CONF_USB_N_0"> 0 (only EP0)
+// <CONF_USB_N_1"> 1 (EP 0x81 or 0x01)
+// <CONF_USB_N_2"> 2 (EP 0x82 or 0x02)
+// <CONF_USB_N_3"> 3 (EP 0x83 or 0x03)
+// <CONF_USB_N_4"> 4 (EP 0x84 or 0x04)
+// <CONF_USB_N_5"> 5 (EP 0x85 or 0x05)
+// <CONF_USB_N_6"> 6 (EP 0x86 or 0x06)
+// <CONF_USB_N_7"> 7 (EP 0x87 or 0x07)
+// <CONF_USB_EP_N_MAX"> Max possible (by HW)
+// <i> The number of physical endpoints - 1
+// <id> usbd_arch_max_ep_n
+#ifndef CONF_USB_D_MAX_EP_N
+#define CONF_USB_D_MAX_EP_N CONF_USB_D_EP_N_MAX
+#endif
+
+// <y> USB Speed Limit
+// <i> Limits the working speed of the device.
+// <USB_SPEED_FS"> Full speed
+// <USB_SPEED_LS"> Low Speed
+// <id> usbd_arch_speed
+#ifndef CONF_USB_D_SPEED
+#define CONF_USB_D_SPEED USB_SPEED_FS
+#endif
+
+// <o> Cache buffer size for EP0
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time.
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <id> usb_arch_ep0_cache
+#ifndef CONF_USB_EP0_CACHE
+#define CONF_USB_EP0_CACHE 64
+#endif
+
+// <h> Cache configuration EP1
+// <o> Cache buffer size for EP1 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep1_cache
+#ifndef CONF_USB_EP1_CACHE
+#define CONF_USB_EP1_CACHE 0
+#endif
+
+// <o> Cache buffer size for EP1 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep1_I_CACHE
+#ifndef CONF_USB_EP1_I_CACHE
+#define CONF_USB_EP1_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP2
+// <o> Cache buffer size for EP2 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep2_cache
+#ifndef CONF_USB_EP2_CACHE
+#define CONF_USB_EP2_CACHE 0
+#endif
+
+// <o> Cache buffer size for EP2 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep2_I_CACHE
+#ifndef CONF_USB_EP2_I_CACHE
+#define CONF_USB_EP2_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP3
+// <o> Cache buffer size for EP3 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep3_cache
+#ifndef CONF_USB_EP3_CACHE
+#define CONF_USB_EP3_CACHE 0
+#endif
+
+// <o> Cache buffer size for EP3 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep3_I_CACHE
+#ifndef CONF_USB_EP3_I_CACHE
+#define CONF_USB_EP3_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP4
+// <o> Cache buffer size for EP4 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep4_cache
+#ifndef CONF_USB_EP4_CACHE
+#define CONF_USB_EP4_CACHE 0
+#endif
+
+// <o> Cache buffer size for EP4 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep4_I_CACHE
+#ifndef CONF_USB_EP4_I_CACHE
+#define CONF_USB_EP4_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP5
+// <o> Cache buffer size for EP5 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep5_cache
+#ifndef CONF_USB_EP5_CACHE
+#define CONF_USB_EP5_CACHE 0
+#endif
+
+// <o> Cache buffer size for EP5 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep5_I_CACHE
+#ifndef CONF_USB_EP5_I_CACHE
+#define CONF_USB_EP5_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP6
+// <o> Cache buffer size for EP6 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep6_cache
+#ifndef CONF_USB_EP6_CACHE
+#define CONF_USB_EP6_CACHE 0
+#endif
+
+// <o> Cache buffer size for EP6 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep6_I_CACHE
+#ifndef CONF_USB_EP6_I_CACHE
+#define CONF_USB_EP6_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP7
+// <o> Cache buffer size for EP7 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep7_cache
+#ifndef CONF_USB_EP7_CACHE
+#define CONF_USB_EP7_CACHE 0
+#endif
+
+// <o> Cache buffer size for EP7 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep7_I_CACHE
+#ifndef CONF_USB_EP7_I_CACHE
+#define CONF_USB_EP7_I_CACHE 0
+#endif
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_USB_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h
new file mode 100644
index 000000000..51173f6d3
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h
@@ -0,0 +1,1252 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <y> ADC Clock Source
+// <id> adc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC0_SRC
+#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC0_FREQUENCY
+ * \brief ADC0's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC0_FREQUENCY
+#define CONF_GCLK_ADC0_FREQUENCY 48000000
+#endif
+
+// <y> DAC Clock Source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <id> dac_gclk_selection
+// <i> Select the clock source for DAC.
+#ifndef CONF_GCLK_DAC_SRC
+#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK6_Val
+#endif
+
+/**
+ * \def CONF_GCLK_DAC_FREQUENCY
+ * \brief DAC's Clock frequency
+ */
+#ifndef CONF_GCLK_DAC_FREQUENCY
+#define CONF_GCLK_DAC_FREQUENCY 2000000
+#endif
+
+// <y> EVSYS Channel 0 Clock Source
+// <id> evsys_clk_selection_0
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 0.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 1 Clock Source
+// <id> evsys_clk_selection_1
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 1.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 2 Clock Source
+// <id> evsys_clk_selection_2
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 2.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 3 Clock Source
+// <id> evsys_clk_selection_3
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 3.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 4 Clock Source
+// <id> evsys_clk_selection_4
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 4.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 5 Clock Source
+// <id> evsys_clk_selection_5
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 5.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 6 Clock Source
+// <id> evsys_clk_selection_6
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 6.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 7 Clock Source
+// <id> evsys_clk_selection_7
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 7.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 8 Clock Source
+// <id> evsys_clk_selection_8
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 8.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 9 Clock Source
+// <id> evsys_clk_selection_9
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 9.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 10 Clock Source
+// <id> evsys_clk_selection_10
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 10.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 48000000.0
+#endif
+
+// <y> EVSYS Channel 11 Clock Source
+// <id> evsys_clk_selection_11
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for channel 11.
+#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC
+#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
+ * \brief EVSYS's Clock frequency
+ */
+
+#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
+#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 48000000.0
+#endif
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 120000000
+#endif
+
+// <y> RTC Clock Source
+// <id> rtc_clk_selection
+// <RTC_CLOCK_SOURCE"> RTC source
+// <i> Select the clock source for RTC.
+#ifndef CONF_GCLK_RTC_SRC
+#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_RTC_FREQUENCY
+ * \brief RTC's Clock frequency
+ */
+#ifndef CONF_GCLK_RTC_FREQUENCY
+#define CONF_GCLK_RTC_FREQUENCY 1024
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM0_CORE_SRC
+#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
+#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
+ * \brief SERCOM0's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+ * \brief SERCOM0's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM1_CORE_SRC
+#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
+#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
+ * \brief SERCOM1's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+ * \brief SERCOM1's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM2_CORE_SRC
+#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
+#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
+ * \brief SERCOM2's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+ * \brief SERCOM2's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM3_CORE_SRC
+#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
+#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
+ * \brief SERCOM3's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
+ * \brief SERCOM3's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC0_SRC
+#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC0_FREQUENCY
+ * \brief TC0's Clock frequency
+ */
+#ifndef CONF_GCLK_TC0_FREQUENCY
+#define CONF_GCLK_TC0_FREQUENCY 48000000
+#endif
+
+// <y> USB Clock Source
+// <id> usb_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for USB.
+#ifndef CONF_GCLK_USB_SRC
+#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+
+#endif
+
+/**
+ * \def CONF_GCLK_USB_FREQUENCY
+ * \brief USB's Clock frequency
+ */
+#ifndef CONF_GCLK_USB_FREQUENCY
+#define CONF_GCLK_USB_FREQUENCY 48000000
+#endif
+
+// <h> SDHC Clock Settings
+// <y> SDHC Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for SDHC.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_SDHC0_SRC
+#define CONF_GCLK_SDHC0_SRC GCLK_GENCTRL_SRC_DFLL_Val
+#endif
+
+// <y> SDHC clock slow source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for SDHC.
+// <id> sdhc_slow_gclk_selection
+#ifndef CONF_GCLK_SDHC0_SLOW_SRC
+#define CONF_GCLK_SDHC0_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
+#endif
+// </h>
+
+/**
+ * \def SDHC FREQUENCY
+ * \brief SDHC's Clock frequency
+ */
+#ifndef CONF_SDHC0_FREQUENCY
+#define CONF_SDHC0_FREQUENCY 12000000
+#endif
+
+/**
+ * \def SDHC FREQUENCY
+ * \brief SDHC's Clock slow frequency
+ */
+#ifndef CONF_SDHC0_SLOW_FREQUENCY
+#define CONF_SDHC0_SLOW_FREQUENCY 12000000
+#endif
+
+// <h> SDHC Clock Settings
+// <y> SDHC Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for SDHC.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_SDHC1_SRC
+#define CONF_GCLK_SDHC1_SRC GCLK_GENCTRL_SRC_DFLL_Val
+#endif
+
+// <y> SDHC clock slow source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for SDHC.
+// <id> sdhc_slow_gclk_selection
+#ifndef CONF_GCLK_SDHC1_SLOW_SRC
+#define CONF_GCLK_SDHC1_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
+#endif
+// </h>
+
+/**
+ * \def SDHC FREQUENCY
+ * \brief SDHC's Clock frequency
+ */
+#ifndef CONF_SDHC1_FREQUENCY
+#define CONF_SDHC1_FREQUENCY 12000000
+#endif
+
+/**
+ * \def SDHC FREQUENCY
+ * \brief SDHC's Clock slow frequency
+ */
+#ifndef CONF_SDHC1_SLOW_FREQUENCY
+#define CONF_SDHC1_SLOW_FREQUENCY 12000000
+#endif
+
+// <h> CAN Clock Settings
+// <y> CAN Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CAN.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_CAN0_SRC
+#define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CAN FREQUENCY
+ * \brief CAN's Clock frequency
+ */
+#ifndef CONF_CAN0_FREQUENCY
+#define CONF_CAN0_FREQUENCY 120000000
+#endif
+
+// <h> CAN Clock Settings
+// <y> CAN Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CAN.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_CAN1_SRC
+#define CONF_GCLK_CAN1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CAN FREQUENCY
+ * \brief CAN's Clock frequency
+ */
+#ifndef CONF_CAN1_FREQUENCY
+#define CONF_CAN1_FREQUENCY 120000000
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same51/usbd_config.h b/ports/atmel-samd/asf4_conf/same51/usbd_config.h
new file mode 100644
index 000000000..be1fa3c9e
--- /dev/null
+++ b/ports/atmel-samd/asf4_conf/same51/usbd_config.h
@@ -0,0 +1,850 @@
+/* Auto-generated config file usbd_config.h */
+#ifndef USBD_CONFIG_H
+#define USBD_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// ---- USB Device Stack Core Options ----
+
+// <q> High Speed Support
+// <i> Enable high speed specific descriptors support, e.g., DeviceQualifierDescriptor and OtherSpeedConfiguration Descriptor.
+// <i> High speed support require descriptors description array on start, for LS/FS and HS support in first and second place.
+// <id> usbd_hs_sp
+#ifndef CONF_USBD_HS_SP
+#define CONF_USBD_HS_SP 0
+#endif
+
+// ---- USB Device Stack Composite Options ----
+
+// <e> Enable String Descriptors
+// <id> usb_composite_str_en
+#ifndef CONF_USB_COMPOSITE_STR_EN
+#define CONF_USB_COMPOSITE_STR_EN 0
+#endif
+// <s> Language IDs
+// <i> Language IDs in c format, split by comma (E.g., 0x0409 ...)
+// <id> usb_composite_langid
+#ifndef CONF_USB_COMPOSITE_LANGID
+#define CONF_USB_COMPOSITE_LANGID "0x0409"
+#endif
+
+#ifndef CONF_USB_COMPOSITE_LANGID_DESC
+#define CONF_USB_COMPOSITE_LANGID_DESC
+#endif
+// </e>
+
+// <h> Composite Device Descriptor
+
+// <o> bcdUSB
+// <0x0200=> USB 2.0 version
+// <0x0210=> USB 2.1 version
+// <id> usb_composite_bcdusb
+#ifndef CONF_USB_COMPOSITE_BCDUSB
+#define CONF_USB_COMPOSITE_BCDUSB 0x200
+#endif
+
+// <o> bMaxPackeSize0
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <id> usb_composite_bmaxpksz0
+#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0
+#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40
+#endif
+
+// <o> idVender <0x0000-0xFFFF>
+// <id> usb_composite_idvender
+#ifndef CONF_USB_COMPOSITE_IDVENDER
+#define CONF_USB_COMPOSITE_IDVENDER 0x3eb
+#endif
+
+// <o> idProduct <0x0000-0xFFFF>
+// <id> usb_composite_idproduct
+#ifndef CONF_USB_COMPOSITE_IDPRODUCT
+#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421
+#endif
+
+// <o> bcdDevice <0x0000-0xFFFF>
+// <id> usb_composite_bcddevice
+#ifndef CONF_USB_COMPOSITE_BCDDEVICE
+#define CONF_USB_COMPOSITE_BCDDEVICE 0x100
+#endif
+
+// <e> Enable string descriptor of iManufact
+// <id> usb_composite_imanufact_en
+#ifndef CONF_USB_COMPOSITE_IMANUFACT_EN
+#define CONF_USB_COMPOSITE_IMANUFACT_EN 0
+#endif
+
+#ifndef CONF_USB_COMPOSITE_IMANUFACT
+#define CONF_USB_COMPOSITE_IMANUFACT (CONF_USB_COMPOSITE_IMANUFACT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN))
+#endif
+
+// <s> Unicode string of iManufact
+// <id> usb_composite_imanufact_str
+#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR
+#define CONF_USB_COMPOSITE_IMANUFACT_STR "Atmel"
+#endif
+
+#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR_DESC
+#define CONF_USB_COMPOSITE_IMANUFACT_STR_DESC
+#endif
+
+// </e>
+
+// <e> Enable string descriptor of iProduct
+// <id> usb_composite_iproduct_en
+#ifndef CONF_USB_COMPOSITE_IPRODUCT_EN
+#define CONF_USB_COMPOSITE_IPRODUCT_EN 0
+#endif
+
+#ifndef CONF_USB_COMPOSITE_IPRODUCT
+#define CONF_USB_COMPOSITE_IPRODUCT                                                                                    \
+	(CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN))
+#endif
+
+// <s> Unicode string of iProduct
+// <id> usb_composite_iproduct_str
+#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR
+#define CONF_USB_COMPOSITE_IPRODUCT_STR "Composite Demo"
+#endif
+
+#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR_DESC
+#define CONF_USB_COMPOSITE_IPRODUCT_STR_DESC
+#endif
+
+// </e>
+
+// <e> Enable string descriptor of iSerialNum
+// <id> usb_composite_iserialnum_en
+#ifndef CONF_USB_COMPOSITE_ISERIALNUM_EN
+#define CONF_USB_COMPOSITE_ISERIALNUM_EN 0
+#endif
+
+#ifndef CONF_USB_COMPOSITE_ISERIALNUM
+#define CONF_USB_COMPOSITE_ISERIALNUM                                                                                  \
+	(CONF_USB_COMPOSITE_ISERIALNUM_EN                                                                                  \
+	 * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN))
+#endif
+
+// <s> Unicode string of iSerialNum
+// <id> usb_composite_iserialnum_str
+#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR
+#define CONF_USB_COMPOSITE_ISERIALNUM_STR "123456789ABCDEF"
+#endif
+
+#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC
+#define CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC
+#endif
+
+// </e>
+
+// <o> bNumConfigurations <0x01-0xFF>
+// <id> usb_composite_bnumconfig
+#ifndef CONF_USB_COMPOSITE_BNUMCONFIG
+#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1
+#endif
+
+// </h>
+
+// <h> Composite Configuration Descriptor
+// <o> bConfigurationValue <0x01-0xFF>
+// <id> usb_composite_bconfigval
+#ifndef CONF_USB_COMPOSITE_BCONFIGVAL
+#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1
+#endif
+// <e> Enable string descriptor of iConfig
+// <id> usb_composite_iconfig_en
+#ifndef CONF_USB_COMPOSITE_ICONFIG_EN
+#define CONF_USB_COMPOSITE_ICONFIG_EN 0
+#endif
+
+#ifndef CONF_USB_COMPOSITE_ICONFIG
+#define CONF_USB_COMPOSITE_ICONFIG                                                                                     \
+	(CONF_USB_COMPOSITE_ICONFIG_EN                                                                                     \
+	 * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN            \
+	    + CONF_USB_COMPOSITE_ICONFIG_EN))
+#endif
+
+// <s> Unicode string of iConfig
+// <id> usb_composite_iconfig_str
+#ifndef CONF_USB_COMPOSITE_ICONFIG_STR
+#define CONF_USB_COMPOSITE_ICONFIG_STR ""
+#endif
+
+#ifndef CONF_USB_COMPOSITE_ICONFIG_STR_DESC
+#define CONF_USB_COMPOSITE_ICONFIG_STR_DESC
+#endif
+
+// </e>
+
+// <o> bmAttributes
+// <0x80=> Bus power supply, not support for remote wakeup
+// <0xA0=> Bus power supply, support for remote wakeup
+// <0xC0=> Self powered, not support for remote wakeup
+// <0xE0=> Self powered, support for remote wakeup
+// <id> usb_composite_bmattri
+#ifndef CONF_USB_COMPOSITE_BMATTRI
+#define CONF_USB_COMPOSITE_BMATTRI 0x80
+#endif
+
+// <o> bMaxPower <0x00-0xFF>
+// <id> usb_composite_bmaxpower
+#ifndef CONF_USB_COMPOSITE_BMAXPOWER
+#define CONF_USB_COMPOSITE_BMAXPOWER 0x32
+#endif
+// </h>
+
+// <e> CDC ACM Support
+// <id> usb_composite_cdc_acm_support
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN
+#define CONF_USB_COMPOSITE_CDC_ACM_EN 0
+#endif
+
+// <o> CDC ACM Comm Interrupt IN Endpoint Address
+// <0x81=> EndpointAddress = 0x81
+// <0x82=> EndpointAddress = 0x82
+// <0x83=> EndpointAddress = 0x83
+// <0x84=> EndpointAddress = 0x84
+// <0x85=> EndpointAddress = 0x85
+// <0x86=> EndpointAddress = 0x86
+// <0x87=> EndpointAddress = 0x87
+// <0x88=> EndpointAddress = 0x88
+// <0x89=> EndpointAddress = 0x89
+
+// <id> usb_composite_cdc_acm_epaddr
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR
+#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82
+#endif
+
+// <o> CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+
+// <id> usb_composite_cdc_acm_comm_int_maxpksz
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ
+#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40
+#endif
+
+// <o> CDC ACM Data BULK IN Endpoint Address
+// <0x81=> EndpointAddress = 0x81
+// <0x82=> EndpointAddress = 0x82
+// <0x83=> EndpointAddress = 0x83
+// <0x84=> EndpointAddress = 0x84
+// <0x85=> EndpointAddress = 0x85
+// <0x86=> EndpointAddress = 0x86
+// <0x87=> EndpointAddress = 0x87
+// <0x88=> EndpointAddress = 0x88
+// <0x89=> EndpointAddress = 0x89
+
+// <id> usb_composite_cdc_acm_data_bulkin_epaddr
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR
+#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81
+#endif
+
+// <o> CDC ACM Data BULK IN Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+
+// <id> usb_composite_cdc_acm_data_builin_maxpksz
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ
+#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40
+#endif
+
+// <o> CDC ACM Data BULK IN Endpoint wMaxPacketSize for High Speed
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <0x0080=> 128 bytes
+// <0x0100=> 256 bytes
+// <0x0200=> 512 bytes
+
+// <id> usb_composite_cdc_acm_data_builin_maxpksz_hs
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS
+#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS 0x200
+#endif
+
+// <o> CDC ACM Data BULK OUT Endpoint Address
+// <0x01=> EndpointAddress = 0x01
+// <0x02=> EndpointAddress = 0x02
+// <0x03=> EndpointAddress = 0x03
+// <0x04=> EndpointAddress = 0x04
+// <0x05=> EndpointAddress = 0x05
+// <0x06=> EndpointAddress = 0x06
+// <0x07=> EndpointAddress = 0x07
+// <0x08=> EndpointAddress = 0x08
+// <0x09=> EndpointAddress = 0x09
+
+// <id> usb_composite_cdc_acm_data_bulkout_epaddr
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR
+#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1
+#endif
+
+// <o> CDC ACM Data BULK OUT Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+
+// <id> usb_composite_cdc_acm_data_buckout_maxpksz
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ
+#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40
+#endif
+
+// <o> CDC ACM Data BULK OUT Endpoint wMaxPacketSize for High Speed
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <0x0080=> 128 bytes
+// <0x0100=> 256 bytes
+// <0x0200=> 512 bytes
+
+// <id> usb_composite_cdc_acm_data_buckout_maxpksz_hs
+#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS
+#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS 0x200
+#endif
+
+// <q> CDC ACM Echo Demo generation
+// <id> conf_usb_composite_cdc_echo_demo
+// <i> Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo.
+// <i> Buf is packet buffer for data receive and echo back.
+// <i> The buffer is 4 byte aligned to support DMA.
+#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO
+#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0
+#endif
+
+// </e>
+
+// <e> HID Mouse Support
+// <id> usb_composite_hid_mouse_support
+#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN
+#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0
+#endif
+
+// <o> HID Mouse INTERRUPT IN Endpoint Address
+// <0x81=> EndpointAddress = 0x81
+// <0x82=> EndpointAddress = 0x82
+// <0x83=> EndpointAddress = 0x83
+// <0x84=> EndpointAddress = 0x84
+// <0x85=> EndpointAddress = 0x85
+// <0x86=> EndpointAddress = 0x86
+// <0x87=> EndpointAddress = 0x87
+// <0x88=> EndpointAddress = 0x88
+// <0x89=> EndpointAddress = 0x89
+
+// <id> usb_composite_hid_mouse_intin_epaddr
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR
+#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83
+#endif
+
+// <o> HID Mouse INTERRUPT IN Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+
+// <id> usb_composite_hid_mouse_intin_maxpksz
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ
+#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8
+#endif
+
+// <q> HID Mouse Move Demo generation
+// <id> conf_usb_composite_hid_mouse_demo
+// <i> Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo.
+// <i> Button1 and button3 are the pins used for mouse moving left and right.
+#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO
+#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0
+#endif
+
+// </e>
+
+// <e> HID Keyboard Support
+// <id> usb_composite_hid_keyboard_support
+#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN
+#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0
+#endif
+
+// <o> HID Keyboard INTERRUPT IN Endpoint Address
+// <0x81=> EndpointAddress = 0x81
+// <0x82=> EndpointAddress = 0x82
+// <0x83=> EndpointAddress = 0x83
+// <0x84=> EndpointAddress = 0x84
+// <0x85=> EndpointAddress = 0x85
+// <0x86=> EndpointAddress = 0x86
+// <0x87=> EndpointAddress = 0x87
+// <0x88=> EndpointAddress = 0x88
+// <0x89=> EndpointAddress = 0x89
+
+// <id> usb_composite_hid_keyboard_intin_epaddr
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR
+#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84
+#endif
+
+// <o> HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+
+// <id> usb_composite_hid_keyboard_intin_maxpksz
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ
+#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8
+#endif
+
+// <o> HID Keyboard INTERRUPT OUT Endpoint Address
+// <0x01=> EndpointAddress = 0x01
+// <0x02=> EndpointAddress = 0x02
+// <0x03=> EndpointAddress = 0x03
+// <0x04=> EndpointAddress = 0x04
+// <0x05=> EndpointAddress = 0x05
+// <0x06=> EndpointAddress = 0x06
+// <0x07=> EndpointAddress = 0x07
+// <0x08=> EndpointAddress = 0x08
+// <0x09=> EndpointAddress = 0x09
+
+// <id> usb_composite_hid_keyboard_intout_epaddr
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR
+#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2
+#endif
+
+// <o> HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+
+// <id> usb_composite_hid_keyboard_intout_maxpksz
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ
+#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8
+#endif
+
+// <q> HID Keyboard Caps Lock Demo generation
+// <id> conf_usb_composite_hid_keyboard_demo
+// <i> Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo.
+// <i> Buffon2 is the pin used for keyboard CAPS LOCK simulation.
+#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO
+#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0
+#endif
+
+// </e>
+
+// <e> HID Generic Support
+// <id> usb_composite_hid_generic_support
+#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN
+#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0
+#endif
+
+#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN
+#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53
+#endif
+
+#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT
+#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT                                                                          \
+	0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95,  \
+	    0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02,    \
+	    0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0
+#endif
+
+// <o> HID Generic INTERRUPT IN Endpoint Address
+// <0x81=> EndpointAddress = 0x81
+// <0x82=> EndpointAddress = 0x82
+// <0x83=> EndpointAddress = 0x83
+// <0x84=> EndpointAddress = 0x84
+// <0x85=> EndpointAddress = 0x85
+// <0x86=> EndpointAddress = 0x86
+// <0x87=> EndpointAddress = 0x87
+// <0x88=> EndpointAddress = 0x88
+// <0x89=> EndpointAddress = 0x89
+
+// <id> usb_composite_hid_generic_intin_epaddr
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR
+#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85
+#endif
+
+// <o> HID Generic INTERRUPT IN Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+
+// <id> usb_composite_hid_generic_intin_maxpksz
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ
+#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40
+#endif
+
+// <o> HID Generic INTERRUPT OUT Endpoint Address
+// <0x01=> EndpointAddress = 0x01
+// <0x02=> EndpointAddress = 0x02
+// <0x03=> EndpointAddress = 0x03
+// <0x04=> EndpointAddress = 0x04
+// <0x05=> EndpointAddress = 0x05
+// <0x06=> EndpointAddress = 0x06
+// <0x07=> EndpointAddress = 0x07
+// <0x08=> EndpointAddress = 0x08
+// <0x09=> EndpointAddress = 0x09
+
+// <id> usb_composite_hid_generic_intout_epaddr
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR
+#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3
+#endif
+
+// <o> HID Generic INTERRUPT OUT Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <id> usb_composite_hid_generic_intout_maxpksz
+// <i> Please make sure that the setting here is coincide with the endpoint setting in USB device driver.
+#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ
+#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40
+#endif
+
+// </e>
+
+// <e> MSC Support
+// <id> usb_composite_msc_support
+#ifndef CONF_USB_COMPOSITE_MSC_EN
+#define CONF_USB_COMPOSITE_MSC_EN 0
+#endif
+
+// <o> MSC BULK Endpoints wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+
+// <id> usb_composite_msc_bulk_maxpksz
+#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ
+#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x40
+#endif
+
+// <o> MSC BULK Endpoints wMaxPacketSize for High Speed
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <0x0080=> 128 bytes
+// <0x0100=> 256 bytes
+// <0x0200=> 512 bytes
+
+// <id> usb_composite_msc_bulk_maxpksz_hs
+#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS
+#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS 0x200
+#endif
+
+// <o> MSC BULK IN Endpoint Address
+// <0x81=> EndpointAddress = 0x81
+// <0x82=> EndpointAddress = 0x82
+// <0x83=> EndpointAddress = 0x83
+// <0x84=> EndpointAddress = 0x84
+// <0x85=> EndpointAddress = 0x85
+// <0x86=> EndpointAddress = 0x86
+// <0x87=> EndpointAddress = 0x87
+// <0x88=> EndpointAddress = 0x88
+// <0x89=> EndpointAddress = 0x89
+
+// <id> usb_composite_msc_bulkin_epaddr
+#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR
+#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86
+#endif
+
+// <o> MSC BULK OUT Endpoint Address
+// <0x01=> EndpointAddress = 0x01
+// <0x02=> EndpointAddress = 0x02
+// <0x03=> EndpointAddress = 0x03
+// <0x04=> EndpointAddress = 0x04
+// <0x05=> EndpointAddress = 0x05
+// <0x06=> EndpointAddress = 0x06
+// <0x07=> EndpointAddress = 0x07
+// <0x08=> EndpointAddress = 0x08
+// <0x09=> EndpointAddress = 0x09
+
+// <id> usb_composite_msc_bulkout_epaddr
+#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR
+#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x4
+#endif
+
+// <e> Enable Demo code for Disk LUN handling
+// <id> usb_composite_msc_demo_en
+#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO
+#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1
+#endif
+
+// <o> Disk access cache/buffer of sectors if non-RAM disk (e.g., SD/MMC) enabled <1-64>
+// <id> conf_usb_msc_lun_buf_sectors
+#ifndef CONF_USB_MSC_LUN_BUF_SECTORS
+#define CONF_USB_MSC_LUN_BUF_SECTORS 4
+#endif
+
+// <e> Enable Demo for RAM Disk
+// <id> conf_usb_msc_lun0_enable
+#ifndef CONF_USB_MSC_LUN0_ENABLE
+#define CONF_USB_MSC_LUN0_ENABLE 1
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_TYPE
+#define CONF_USB_MSC_LUN0_TYPE 0x00
+#endif
+
+// <q> The disk is removable
+// <id> conf_usb_msc_lun0_rmb
+#ifndef CONF_USB_MSC_LUN0_RMB
+#define CONF_USB_MSC_LUN0_RMB 0x1
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_ISO
+#define CONF_USB_MSC_LUN0_ISO 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_ECMA
+#define CONF_USB_MSC_LUN0_ECMA 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_ANSI
+#define CONF_USB_MSC_LUN0_ANSI 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_REPO
+#define CONF_USB_MSC_LUN0_REPO 0x01
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_FACTORY
+#define CONF_USB_MSC_LUN0_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_PRODUCT
+#define CONF_USB_MSC_LUN0_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_PRODUCT_VERSION
+#define CONF_USB_MSC_LUN0_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00
+#endif
+
+// <o> Disk Size (in KB) <0x1-0xFFFFFFFF>
+// <i> Windows will not show disk less than 20K, so 22K is used to reserve more RAM for APP
+// <id> conf_usb_msc_lun0_capacity
+
+#ifndef CONF_USB_MSC_LUN0_CAPACITY
+#define CONF_USB_MSC_LUN0_CAPACITY 22
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_BLOCK_SIZE
+#define CONF_USB_MSC_LUN0_BLOCK_SIZE 512
+#endif
+
+#ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR
+#define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR                                                                              \
+	((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1)
+#endif
+
+// </e>
+
+// <e> Enable Demo for SD/MMC Disk
+// <i> SD/MMC stack must be added before enable SD/MMC demo
+// <i> SD/MMC insert/eject not supported by this simple demo
+// <id> conf_usb_msc_lun1_enable
+#ifndef CONF_USB_MSC_LUN1_ENABLE
+#define CONF_USB_MSC_LUN1_ENABLE 0
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_TYPE
+#define CONF_USB_MSC_LUN1_TYPE 0x00
+#endif
+
+// <q> The disk is removable
+// <i> SD/MMC stack must be added before enable SD/MMC demo
+// <i> SD/MMC insert/eject not supported by this simple demo
+// <id> conf_usb_msc_lun1_rmb
+#ifndef CONF_USB_MSC_LUN1_RMB
+#define CONF_USB_MSC_LUN1_RMB 0x1
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_ISO
+#define CONF_USB_MSC_LUN1_ISO 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_ECMA
+#define CONF_USB_MSC_LUN1_ECMA 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_ANSI
+#define CONF_USB_MSC_LUN1_ANSI 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_REPO
+#define CONF_USB_MSC_LUN1_REPO 0x01
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_FACTORY
+#define CONF_USB_MSC_LUN1_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_PRODUCT
+#define CONF_USB_MSC_LUN1_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_PRODUCT_VERSION
+#define CONF_USB_MSC_LUN1_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_CAPACITY
+#define CONF_USB_MSC_LUN1_CAPACITY 22
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_BLOCK_SIZE
+#define CONF_USB_MSC_LUN1_BLOCK_SIZE 512
+#endif
+
+#ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR
+#define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR                                                                              \
+	((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1)
+#endif
+
+// </e>
+
+// <e> Enable Demo for LUN 2
+// <id> conf_usb_msc_lun2_enable
+#ifndef CONF_USB_MSC_LUN2_ENABLE
+#define CONF_USB_MSC_LUN2_ENABLE 0
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_TYPE
+#define CONF_USB_MSC_LUN2_TYPE 0x00
+#endif
+
+// <q> The disk is removable
+// <id> conf_usb_msc_lun2_rmb
+#ifndef CONF_USB_MSC_LUN2_RMB
+#define CONF_USB_MSC_LUN2_RMB 0x1
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_ISO
+#define CONF_USB_MSC_LUN2_ISO 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_ECMA
+#define CONF_USB_MSC_LUN2_ECMA 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_ANSI
+#define CONF_USB_MSC_LUN2_ANSI 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_REPO
+#define CONF_USB_MSC_LUN2_REPO 0x01
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_FACTORY
+#define CONF_USB_MSC_LUN2_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_PRODUCT
+#define CONF_USB_MSC_LUN2_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_PRODUCT_VERSION
+#define CONF_USB_MSC_LUN2_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00
+#endif
+
+// <o> Disk Size (in KB) <0x1-0xFFFFFFFF>
+// <id> conf_usb_msc_lun2_capacity
+
+#ifndef CONF_USB_MSC_LUN2_CAPACITY
+#define CONF_USB_MSC_LUN2_CAPACITY 22
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_BLOCK_SIZE
+#define CONF_USB_MSC_LUN2_BLOCK_SIZE 512
+#endif
+
+#ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR
+#define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR                                                                              \
+	((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1)
+#endif
+
+// </e>
+
+// <e> Enable Demo for LUN 3
+// <id> conf_usb_msc_lun3_enable
+#ifndef CONF_USB_MSC_LUN3_ENABLE
+#define CONF_USB_MSC_LUN3_ENABLE 0
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_TYPE
+#define CONF_USB_MSC_LUN3_TYPE 0x00
+#endif
+
+// <q> The disk is removable
+// <id> conf_usb_msc_lun3_rmb
+#ifndef CONF_USB_MSC_LUN3_RMB
+#define CONF_USB_MSC_LUN3_RMB 0x1
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_ISO
+#define CONF_USB_MSC_LUN3_ISO 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_ECMA
+#define CONF_USB_MSC_LUN3_ECMA 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_ANSI
+#define CONF_USB_MSC_LUN3_ANSI 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_REPO
+#define CONF_USB_MSC_LUN3_REPO 0x01
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_FACTORY
+#define CONF_USB_MSC_LUN3_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_PRODUCT
+#define CONF_USB_MSC_LUN3_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_PRODUCT_VERSION
+#define CONF_USB_MSC_LUN3_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00
+#endif
+
+// <o> Disk Size (in KB) <0x1-0xFFFFFFFF>
+// <id> conf_usb_msc_lun3_capacity
+
+#ifndef CONF_USB_MSC_LUN3_CAPACITY
+#define CONF_USB_MSC_LUN3_CAPACITY 22
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_BLOCK_SIZE
+#define CONF_USB_MSC_LUN3_BLOCK_SIZE 512
+#endif
+
+#ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR
+#define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR                                                                              \
+	((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1)
+#endif
+
+// </e>
+
+// </e>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // USBD_CONFIG_H
diff --git a/ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h
index 59fe8730e..51173f6d3 100644
--- a/ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h
+++ b/ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h
@@ -1165,6 +1165,88 @@
 #define CONF_SDHC1_SLOW_FREQUENCY 12000000
 #endif
 
+// <h> CAN Clock Settings
+// <y> CAN Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CAN.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_CAN0_SRC
+#define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CAN FREQUENCY
+ * \brief CAN's Clock frequency
+ */
+#ifndef CONF_CAN0_FREQUENCY
+#define CONF_CAN0_FREQUENCY 120000000
+#endif
+
+// <h> CAN Clock Settings
+// <y> CAN Clock source
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CAN.
+// <id> sdhc_gclk_selection
+#ifndef CONF_GCLK_CAN1_SRC
+#define CONF_GCLK_CAN1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CAN FREQUENCY
+ * \brief CAN's Clock frequency
+ */
+#ifndef CONF_CAN1_FREQUENCY
+#define CONF_CAN1_FREQUENCY 120000000
+#endif
+
 // <<< end of configuration section >>>
 
 #endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/board.c b/ports/atmel-samd/boards/bdmicro_vina_d21/board.c
index bd63baa6f..bd63baa6f 100644
--- a/ports/atmel-samd/boards/bdmicro_vina_m0/board.c
+++ b/ports/atmel-samd/boards/bdmicro_vina_d21/board.c
diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h b/ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.h
index 458b1e12a..f2332bbe5 100644
--- a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h
+++ b/ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.h
@@ -1,34 +1,31 @@
-#define MICROPY_HW_BOARD_NAME "BDMICRO Vina M0"
+#define MICROPY_HW_BOARD_NAME "BDMICRO VINA-D21"
 #define MICROPY_HW_MCU_NAME "samd21g18"
 
-#define MICROPY_HW_LED_STATUS (&pin_PA28)
-#define MICROPY_HW_LED_TX &pin_PA27
-#define MICROPY_HW_LED_RX &pin_PA31
-
-// Clock rates are off: Salae reads 12MHz which is the limit even though we set it to the safer 8MHz.
-#define SPI_FLASH_BAUDRATE (8000000)
-
-#define SPI_FLASH_MOSI_PIN &pin_PB22
-#define SPI_FLASH_MISO_PIN &pin_PB03
-#define SPI_FLASH_SCK_PIN &pin_PB23
-#define SPI_FLASH_CS_PIN &pin_PA13
-
 // These are pins not to reset.
 #define MICROPY_PORT_A (0)
 #define MICROPY_PORT_B (0)
 #define MICROPY_PORT_C (0)
 
-#define BOARD_HAS_CRYSTAL 0
+#define SPI_FLASH_CS_PIN &pin_PA13
+#define SPI_FLASH_MISO_PIN &pin_PB03
+#define SPI_FLASH_MOSI_PIN &pin_PB22
+#define SPI_FLASH_SCK_PIN &pin_PB23
 
-#define DEFAULT_I2C_BUS_SCL (&pin_PA23)
-#define DEFAULT_I2C_BUS_SDA (&pin_PA22)
+// Clock rates are off: Salae reads 12MHz which is the limit even though we set it to the safer 8MHz.
+#define SPI_FLASH_BAUDRATE (8000000)
 
-#define DEFAULT_SPI_BUS_SCK (&pin_PB11)
-#define DEFAULT_SPI_BUS_MOSI (&pin_PB10)
-#define DEFAULT_SPI_BUS_MISO (&pin_PA12)
+#define BOARD_HAS_CRYSTAL 1
 
-#define DEFAULT_UART_BUS_RX (&pin_PA11)
 #define DEFAULT_UART_BUS_TX (&pin_PA10)
+#define DEFAULT_UART_BUS_RX (&pin_PA11)
+#define DEFAULT_SPI_BUS_MISO (&pin_PA12)
+#define DEFAULT_I2C_BUS_SDA (&pin_PA22)
+#define DEFAULT_I2C_BUS_SCL (&pin_PA23)
+#define MICROPY_HW_LED_TX (&pin_PA27)
+#define MICROPY_HW_LED_STATUS (&pin_PA28)
+#define MICROPY_HW_LED_RX (&pin_PA31)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PB10)
+#define DEFAULT_SPI_BUS_SCK (&pin_PB11)
 
 // USB is always used internally so skip the pin objects for it.
 #define IGNORE_PIN_PA24 1
diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk b/ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.mk
index b7ad47ff2..a9885d064 100644
--- a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/bdmicro_vina_d21/mpconfigboard.mk
@@ -1,19 +1,22 @@
 USB_VID = 0x31e2
-USB_PID = 0x2002
-USB_PRODUCT = "Vina M0"
+USB_PID = 0x2001
+USB_PRODUCT = "VINA-D21"
 USB_MANUFACTURER = "BDMICRO LLC"
 
 CHIP_VARIANT = SAMD21G18A
 CHIP_FAMILY = samd21
 
 SPI_FLASH_FILESYSTEM = 1
-EXTERNAL_FLASH_DEVICE_COUNT = 1
-EXTERNAL_FLASH_DEVICES = "MX25L51245G"
+EXTERNAL_FLASH_DEVICE_COUNT = 2
+EXTERNAL_FLASH_DEVICES = "MX25L51245G","GD25S512MD"
 LONGINT_IMPL = MPZ
 
 CIRCUITPY_BITBANGIO = 0
+CIRCUITPY_COUNTIO = 0
 CIRCUITPY_I2CPERIPHERAL = 0
 CIRCUITPY_VECTORIO = 0
 
-CFLAGS_INLINE_LIMIT = 50
+CFLAGS_INLINE_LIMIT = 60
 SUPEROPT_GC = 0
+
+CFLAGS_BOARD = --param max-inline-insns-auto=15
diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/pins.c b/ports/atmel-samd/boards/bdmicro_vina_d21/pins.c
index 0ebceb28d..323f71dec 100644
--- a/ports/atmel-samd/boards/bdmicro_vina_m0/pins.c
+++ b/ports/atmel-samd/boards/bdmicro_vina_d21/pins.c
@@ -1,8 +1,6 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
-    { MP_ROM_QSTR(MP_QSTR_RTC_INT), MP_ROM_PTR(&pin_PA00) },
-    { MP_ROM_QSTR(MP_QSTR_RTC_CLK), MP_ROM_PTR(&pin_PA01) },
     { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) },
     { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PB08) },
     { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PB09) },
@@ -13,8 +11,11 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
     { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA11) },
     { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA10) },
     { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) },
     { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA14) },
-    { MP_ROM_QSTR(MP_QSTR_RTC_TS), MP_ROM_PTR(&pin_PA14) },
     { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA09) },
     { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA08) },
     { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA15) },
@@ -22,16 +23,14 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
     { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) },
     { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) },
     { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) },
-    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) },
-    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) },
-    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) },
-    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) },
-    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) },
-    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) },
-    { MP_ROM_QSTR(MP_QSTR_PGM_LED), MP_ROM_PTR(&pin_PA28) },
-    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB11) },
-    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_LED_STATUS), MP_ROM_PTR(&pin_PA28) },
+    { MP_ROM_QSTR(MP_QSTR_LED_TX), MP_ROM_PTR(&pin_PA27) },
     { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB11) },
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) },
+    { MP_ROM_QSTR(MP_QSTR_LED_RX), MP_ROM_PTR(&pin_PA31) },
     { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
     { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
     { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/board.c b/ports/atmel-samd/boards/bdmicro_vina_d51/board.c
new file mode 100644
index 000000000..bd63baa6f
--- /dev/null
+++ b/ports/atmel-samd/boards/bdmicro_vina_d51/board.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+#include "mpconfigboard.h"
+
+void board_init(void)
+{
+    // struct port_config pin_conf;
+    // port_get_config_defaults(&pin_conf);
+    //
+    // pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+    // port_pin_set_config(MICROPY_HW_LED_TX, &pin_conf);
+    // port_pin_set_output_level(MICROPY_HW_LED_TX, true);
+    //
+    // port_pin_set_config(MICROPY_HW_LED_RX, &pin_conf);
+    // port_pin_set_output_level(MICROPY_HW_LED_RX, true);
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+}
diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.h b/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.h
new file mode 100644
index 000000000..8b015df05
--- /dev/null
+++ b/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.h
@@ -0,0 +1,28 @@
+#define MICROPY_HW_BOARD_NAME "BDMICRO VINA-D51"
+#define MICROPY_HW_MCU_NAME "samd51n20"
+
+#define CIRCUITPY_MCU_FAMILY samd51
+
+// These are pins not to reset.
+// Don't reset QSPI data pins
+#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11)
+#define MICROPY_PORT_B (PORT_PB10 | PORT_PB11)
+#define MICROPY_PORT_C (0)
+#define MICROPY_PORT_D (0)
+
+#define BOARD_HAS_CRYSTAL 1
+
+#define DEFAULT_I2C_BUS_SCL (&pin_PA16)
+#define DEFAULT_I2C_BUS_SDA (&pin_PA17)
+#define DEFAULT_UART_BUS_RX (&pin_PB20)
+#define DEFAULT_UART_BUS_TX (&pin_PB21)
+#define DEFAULT_SPI_BUS_MISO (&pin_PB23)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PC27)
+#define DEFAULT_SPI_BUS_SCK (&pin_PC28)
+#define MICROPY_HW_LED_STATUS (&pin_PA23)
+#define MICROPY_HW_LED_RX (&pin_PC05)
+#define MICROPY_HW_LED_TX (&pin_PC06)
+
+// USB is always used internally so skip the pin objects for it.
+#define IGNORE_PIN_PA24 1
+#define IGNORE_PIN_PA25 1
diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.mk b/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.mk
new file mode 100644
index 000000000..f1b2f4c1d
--- /dev/null
+++ b/ports/atmel-samd/boards/bdmicro_vina_d51/mpconfigboard.mk
@@ -0,0 +1,12 @@
+USB_VID = 0x31e2
+USB_PID = 0x2011
+USB_PRODUCT = "VINA-D51"
+USB_MANUFACTURER = "BDMICRO LLC"
+
+CHIP_VARIANT = SAMD51N20A
+CHIP_FAMILY = samd51
+
+QSPI_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICE_COUNT = 2
+EXTERNAL_FLASH_DEVICES = "MX25L51245G","GD25S512MD"
+LONGINT_IMPL = MPZ
diff --git a/ports/atmel-samd/boards/bdmicro_vina_d51/pins.c b/ports/atmel-samd/boards/bdmicro_vina_d51/pins.c
new file mode 100644
index 000000000..8eeab8a9a
--- /dev/null
+++ b/ports/atmel-samd/boards/bdmicro_vina_d51/pins.c
@@ -0,0 +1,90 @@
+#include "shared-bindings/board/__init__.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PB31) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PC16) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PC13) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PC17) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PC18) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PC19) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PC20) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PC21) },
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PB18) },
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PB19) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_DAC0), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_ESP01_EN), MP_ROM_PTR(&pin_PC15) },
+    { MP_ROM_QSTR(MP_QSTR_E5), MP_ROM_PTR(&pin_PC15) },
+    { MP_ROM_QSTR(MP_QSTR_ESP01_GPIO0), MP_ROM_PTR(&pin_PA18) },
+    { MP_ROM_QSTR(MP_QSTR_E3), MP_ROM_PTR(&pin_PA18) },
+    { MP_ROM_QSTR(MP_QSTR_ESP01_GPIO2), MP_ROM_PTR(&pin_PA19) },
+    { MP_ROM_QSTR(MP_QSTR_E4), MP_ROM_PTR(&pin_PA19) },
+    { MP_ROM_QSTR(MP_QSTR_ESP01_RESET), MP_ROM_PTR(&pin_PC14) },
+    { MP_ROM_QSTR(MP_QSTR_E6), MP_ROM_PTR(&pin_PC14) },
+    { MP_ROM_QSTR(MP_QSTR_ESP01_RX), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_I2C3_SCL), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_E2), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_ESP01_TX), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_I2C3_SDA), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_E1), MP_ROM_PTR(&pin_PA13) },
+    { MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PA16) },
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA16) },
+    { MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PA17) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA17) },
+    { MP_ROM_QSTR(MP_QSTR_I2S_FS_0), MP_ROM_PTR(&pin_PA20) },
+    { MP_ROM_QSTR(MP_QSTR_I2S_MCK_0), MP_ROM_PTR(&pin_PB17) },
+    { MP_ROM_QSTR(MP_QSTR_I2S_SCK_0), MP_ROM_PTR(&pin_PB16) },
+    { MP_ROM_QSTR(MP_QSTR_I2S_SDI), MP_ROM_PTR(&pin_PA22) },
+    { MP_ROM_QSTR(MP_QSTR_I2S_SDO), MP_ROM_PTR(&pin_PA21) },
+    { MP_ROM_QSTR(MP_QSTR_LED_B), MP_ROM_PTR(&pin_PA23) },
+    { MP_ROM_QSTR(MP_QSTR_LED_STATUS), MP_ROM_PTR(&pin_PA23) },
+    { MP_ROM_QSTR(MP_QSTR_LED_G), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_LED_R), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_LED_RX), MP_ROM_PTR(&pin_PC05) },
+    { MP_ROM_QSTR(MP_QSTR_LED_TX), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_RS485_RE), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_RS485_RX), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_RS485_TE), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_RS485_TX), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_SPI_MISO), MP_ROM_PTR(&pin_PB23) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB23) },
+    { MP_ROM_QSTR(MP_QSTR_SPI_MOSI), MP_ROM_PTR(&pin_PC27) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PC27) },
+    { MP_ROM_QSTR(MP_QSTR_SPI_SCK), MP_ROM_PTR(&pin_PC28) },
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PC28) },
+    { MP_ROM_QSTR(MP_QSTR_SPI_SS), MP_ROM_PTR(&pin_PB22) },
+    { MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PB22) },
+    { MP_ROM_QSTR(MP_QSTR_UART1_CTS), MP_ROM_PTR(&pin_PC25) },
+    { MP_ROM_QSTR(MP_QSTR_UART1_RTS), MP_ROM_PTR(&pin_PC24) },
+    { MP_ROM_QSTR(MP_QSTR_UART1_RX), MP_ROM_PTR(&pin_PB24) },
+    { MP_ROM_QSTR(MP_QSTR_UART1_TX), MP_ROM_PTR(&pin_PB25) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PB20) },
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB20) },
+    { MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PB20) },
+    { MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PB21) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB21) },
+    { MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PB21) },
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk b/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk
index 5656d4cb8..178258b6c 100755
--- a/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/circuitbrains_basic_m0/mpconfigboard.mk
@@ -16,6 +16,7 @@ CIRCUITPY_COUNTIO = 0
 CIRCUITPY_FREQUENCYIO = 0
 CIRCUITPY_I2CPERIPHERAL = 0
 CIRCUITPY_VECTORIO = 0
+MICROPY_PY_ASYNC_AWAIT = 0
 
 SUPEROPT_GC = 0
 
diff --git a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h
index 12c48b1e3..4321335e5 100644
--- a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h
+++ b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h
@@ -25,7 +25,7 @@
 #define CALIBRATE_CRYSTALLESS 1
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 // Increase stack size slightly due to CPX library import nesting
 #define CIRCUITPY_DEFAULT_STACK_SIZE  (4248) //divisible by 8
diff --git a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
index 81391b953..13ec9e861 100644
--- a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
@@ -15,6 +15,7 @@ LONGINT_IMPL = MPZ
 CIRCUITPY_DISPLAYIO = 0
 CIRCUITPY_FREQUENCYIO = 0
 CIRCUITPY_I2CPERIPHERAL = 0
+MICROPY_PY_ASYNC_AWAIT = 0
 
 SUPEROPT_GC = 0
 CFLAGS_INLINE_LIMIT = 55
diff --git a/ports/atmel-samd/boards/circuitplayground_express_crickit/mpconfigboard.h b/ports/atmel-samd/boards/circuitplayground_express_crickit/mpconfigboard.h
index 95b4ec110..5673be290 100644
--- a/ports/atmel-samd/boards/circuitplayground_express_crickit/mpconfigboard.h
+++ b/ports/atmel-samd/boards/circuitplayground_express_crickit/mpconfigboard.h
@@ -27,7 +27,7 @@
 #define USER_NEOPIXELS_PIN      (&pin_PB23)
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 // Increase stack size slightly due to CPX library import nesting
 #define CIRCUITPY_DEFAULT_STACK_SIZE  (4248) // divisible by 8
diff --git a/ports/atmel-samd/boards/circuitplayground_express_displayio/mpconfigboard.h b/ports/atmel-samd/boards/circuitplayground_express_displayio/mpconfigboard.h
index d478ea38b..fab235149 100644
--- a/ports/atmel-samd/boards/circuitplayground_express_displayio/mpconfigboard.h
+++ b/ports/atmel-samd/boards/circuitplayground_express_displayio/mpconfigboard.h
@@ -25,7 +25,7 @@
 #define CALIBRATE_CRYSTALLESS 1
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 // Increase stack size slightly due to CPX library import nesting.
 #define CIRCUITPY_DEFAULT_STACK_SIZE  (4248)  // divisible by 8
diff --git a/ports/atmel-samd/boards/common.template.ld b/ports/atmel-samd/boards/common.template.ld
index 1054605c8..53c4cf5ee 100644
--- a/ports/atmel-samd/boards/common.template.ld
+++ b/ports/atmel-samd/boards/common.template.ld
@@ -43,6 +43,15 @@ SECTIONS
         _sidata = .;       /* start of .data section */
     } >FLASH_FIRMWARE
 
+    /* Data accessed by the CAN peripheral must be in the first 64kB RAM */
+    /* place it at the very start of RAM, before the .data section */
+    /* it is zeroed by reset_port */
+    .canram (NOLOAD) :
+    {
+        . = ALIGN(4);
+        *(.canram)
+    } > RAM
+
     /* This is the initialized data section
     The program executes knowing that the data is in the RAM
     but the loader puts the initial values in the FLASH_FIRMWARE (inidata).
@@ -61,7 +70,7 @@ SECTIONS
     } >RAM
 
     /* Uninitialized data section */
-    .bss :
+    .bss (NOLOAD) :
     {
         . = ALIGN(4);
         _sbss = .;
diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/board.c b/ports/atmel-samd/boards/dynossat_edu_eps/board.c
new file mode 100644
index 000000000..c8e20206a
--- /dev/null
+++ b/ports/atmel-samd/boards/dynossat_edu_eps/board.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+
+void board_init(void)
+{
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+}
diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h
new file mode 100644
index 000000000..ef4fa8f99
--- /dev/null
+++ b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.h
@@ -0,0 +1,40 @@
+#define MICROPY_HW_BOARD_NAME "DynOSSAT-EDU-EPS"
+#define MICROPY_HW_MCU_NAME "samd21g18"
+
+#define MICROPY_HW_NEOPIXEL (&pin_PA06)
+
+#define SPI_FLASH_MOSI_PIN          &pin_PA22
+#define SPI_FLASH_MISO_PIN          &pin_PA21
+#define SPI_FLASH_SCK_PIN           &pin_PA23
+#define SPI_FLASH_CS_PIN            &pin_PA20
+
+// These are pins not to reset.
+#define MICROPY_PORT_A        ( 0 )
+#define MICROPY_PORT_B        ( 0 )
+#define MICROPY_PORT_C        ( 0 )
+
+#define BOARD_HAS_CRYSTAL 1
+
+#define DEFAULT_I2C_BUS_SCL (&pin_PA09)
+#define DEFAULT_I2C_BUS_SDA (&pin_PA08)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_PB11)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PA12)
+#define DEFAULT_SPI_BUS_MISO (&pin_PB10)
+
+#define DEFAULT_UART_BUS_RX (&pin_PA17)
+#define DEFAULT_UART_BUS_TX (&pin_PA16)
+
+// USB is always used internally so skip the pin objects for it.
+#define IGNORE_PIN_PA24     1
+#define IGNORE_PIN_PA25     1
+#define IGNORE_PIN_PA03	    1
+#define IGNORE_PIN_PA13     1
+#define IGNORE_PIN_PA14     1
+#define IGNORE_PIN_PA15     1
+#define IGNORE_PIN_PA18     1
+#define IGNORE_PIN_PA27     1
+#define IGNORE_PIN_PA28     1
+#define IGNORE_PIN_PB08     1
+#define IGNORE_PIN_PB22     1
+#define IGNORE_PIN_PB23     1
diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.mk b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.mk
new file mode 100644
index 000000000..3c0cc07be
--- /dev/null
+++ b/ports/atmel-samd/boards/dynossat_edu_eps/mpconfigboard.mk
@@ -0,0 +1,23 @@
+USB_VID = 0x04D8
+USB_PID = 0xEAD1
+
+USB_PRODUCT = "DynOSSAT-EDU-EPS-v1.0"
+USB_MANUFACTURER = "BH Dynamics"
+
+CHIP_VARIANT = SAMD21G18A
+CHIP_FAMILY = samd21
+
+SPI_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICE_COUNT = 1
+EXTERNAL_FLASH_DEVICES = "GD25Q32C"
+LONGINT_IMPL = MPZ
+
+CIRCUITPY_BITBANGIO = 0
+CIRCUITPY_FREQUENCYIO = 0
+CIRCUITPY_COUNTIO = 0
+CIRCUITPY_I2CPERIPHERAL = 0
+CIRCUITPY_VECTORIO = 0
+
+CFLAGS_INLINE_LIMIT = 60
+
+SUPEROPT_GC = 0
diff --git a/ports/atmel-samd/boards/dynossat_edu_eps/pins.c b/ports/atmel-samd/boards/dynossat_edu_eps/pins.c
new file mode 100644
index 000000000..a910311d4
--- /dev/null
+++ b/ports/atmel-samd/boards/dynossat_edu_eps/pins.c
@@ -0,0 +1,32 @@
+#include "shared-bindings/board/__init__.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB11) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PA30) },
+    { MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PA31) },
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA17) },
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_OVTEMP), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA16) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_SAT_RESET), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_SAT_PWR_ENABLE), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA19) },
+    { MP_ROM_QSTR(MP_QSTR_INT_IMU_OBC), MP_ROM_PTR(&pin_PA19) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_PWRMON_SDA), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_PWRMON_SCL), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_PWRMON_ALERT), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_I2C_MONITOR), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/board.c b/ports/atmel-samd/boards/dynossat_edu_obc/board.c
new file mode 100644
index 000000000..c8e20206a
--- /dev/null
+++ b/ports/atmel-samd/boards/dynossat_edu_obc/board.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+
+void board_init(void)
+{
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+}
diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h
new file mode 100644
index 000000000..d7df8db74
--- /dev/null
+++ b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.h
@@ -0,0 +1,44 @@
+#define MICROPY_HW_BOARD_NAME "DynOSSAT-EDU-OBC"
+#define MICROPY_HW_MCU_NAME "samd51j20"
+
+#define MICROPY_HW_NEOPIXEL (&pin_PA08)
+
+#define SPI_FLASH_MOSI_PIN          &pin_PA16
+#define SPI_FLASH_MISO_PIN          &pin_PA18
+#define SPI_FLASH_SCK_PIN           &pin_PA17
+#define SPI_FLASH_CS_PIN            &pin_PA19
+
+// These are pins not to reset.
+#define MICROPY_PORT_A        ( PORT_PA16 | PORT_PA17 | PORT_PA18 | PORT_PA19 )
+#define MICROPY_PORT_B        ( 0 )
+#define MICROPY_PORT_C        ( 0 )
+#define MICROPY_PORT_D        ( 0 )
+
+#define BOARD_HAS_CRYSTAL 1
+
+#define DEFAULT_I2C_BUS_SCL (&pin_PB13)
+#define DEFAULT_I2C_BUS_SDA (&pin_PB12)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_PB03)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PB02)
+#define DEFAULT_SPI_BUS_MISO (&pin_PB01)
+
+#define DEFAULT_UART_BUS_RX (&pin_PA23)
+#define DEFAULT_UART_BUS_TX (&pin_PA22)
+
+// USB is always used internally so skip the pin objects for it.
+#define IGNORE_PIN_PA24     1
+#define IGNORE_PIN_PA25     1
+#define IGNORE_PIN_PA02     1
+#define IGNORE_PIN_PA13     1
+#define IGNORE_PIN_PA14     1
+#define IGNORE_PIN_PA20     1
+#define IGNORE_PIN_PA21     1
+#define IGNORE_PIN_PA27     1
+#define IGNORE_PIN_PB00     1
+#define IGNORE_PIN_PB04     1
+#define IGNORE_PIN_PB05     1
+#define IGNORE_PIN_PB16     1
+#define IGNORE_PIN_PB17     1
+#define IGNORE_PIN_PB23     1
+#define IGNORE_PIN_PB31     1
diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.mk b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.mk
new file mode 100644
index 000000000..360940cf1
--- /dev/null
+++ b/ports/atmel-samd/boards/dynossat_edu_obc/mpconfigboard.mk
@@ -0,0 +1,16 @@
+USB_VID = 0x04D8
+USB_PID = 0xEAD2
+
+USB_PRODUCT = "DynOSSAT-EDU-OBC-v1.0"
+USB_MANUFACTURER = "BH Dynamics"
+
+CHIP_VARIANT = SAMD51J20A
+CHIP_FAMILY = samd51
+
+SPI_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICE_COUNT = 1
+EXTERNAL_FLASH_DEVICES = "GD25Q32C"
+LONGINT_IMPL = MPZ
+
+CFLAGS_INLINE_LIMIT = 60
+SUPEROPT_GC = 0
diff --git a/ports/atmel-samd/boards/dynossat_edu_obc/pins.c b/ports/atmel-samd/boards/dynossat_edu_obc/pins.c
new file mode 100644
index 000000000..a560360f7
--- /dev/null
+++ b/ports/atmel-samd/boards/dynossat_edu_obc/pins.c
@@ -0,0 +1,40 @@
+#include "shared-bindings/board/__init__.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PA22) },
+    { MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PA23) },
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA23) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA22) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PB11) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB30) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA30) },
+    { MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PA31) },
+    { MP_ROM_QSTR(MP_QSTR_SD_CS), MP_ROM_PTR(&pin_PB22) },
+    { MP_ROM_QSTR(MP_QSTR_INT_IMU), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_SAT_POWER), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.h b/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.h
index 3a984188f..c4c8c4f3c 100644
--- a/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.h
+++ b/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.h
@@ -11,7 +11,7 @@
 #define CALIBRATE_CRYSTALLESS 1
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PA08)
 #define DEFAULT_I2C_BUS_SDA (&pin_PA09)
diff --git a/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk
index 54c5bff6a..143910318 100644
--- a/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk
@@ -1,5 +1,5 @@
 USB_VID = 0x239A
-USB_PID = 0x8015
+USB_PID = 0x80D3
 USB_PRODUCT = "Feather M0 Adalogger"
 USB_MANUFACTURER = "Adafruit Industries LLC"
 
diff --git a/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.mk
index 9e27ec7b4..5624144e8 100644
--- a/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/feather_m0_express_crickit/mpconfigboard.mk
@@ -1,5 +1,5 @@
 USB_VID = 0x239A
-USB_PID = 0x8023
+USB_PID = 0x80D1
 USB_PRODUCT = "Feather M0 Express"
 USB_MANUFACTURER = "Adafruit Industries LLC"
 
diff --git a/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk
index b589ae766..d746cdf81 100644
--- a/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/feather_m0_rfm69/mpconfigboard.mk
@@ -1,5 +1,5 @@
 USB_VID = 0x239A
-USB_PID = 0x8015
+USB_PID = 0x80D2
 USB_PRODUCT = "Feather M0 RFM69"
 USB_MANUFACTURER = "Adafruit Industries LLC"
 
@@ -12,7 +12,7 @@ CIRCUITPY_FULL_BUILD = 0
 
 # A number of modules are removed for RFM69 to make room for frozen libraries.
 # Many I/O functions are not available.
-CIRCUITPY_ANALOGIO = 0
+CIRCUITPY_ANALOGIO = 1
 CIRCUITPY_PULSEIO = 0
 CIRCUITPY_NEOPIXEL_WRITE = 1
 CIRCUITPY_ROTARYIO = 0
@@ -22,6 +22,7 @@ CIRCUITPY_USB_MIDI = 0
 CIRCUITPY_USB_HID = 0
 CIRCUITPY_TOUCHIO = 0
 CFLAGS_INLINE_LIMIT = 35
+
 # Make more room.
 SUPEROPT_GC = 0
 
diff --git a/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk
index 512bc533c..d37334688 100644
--- a/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/feather_m0_rfm9x/mpconfigboard.mk
@@ -1,5 +1,5 @@
 USB_VID = 0x239A
-USB_PID = 0x8015
+USB_PID = 0x80D4
 USB_PRODUCT = "Feather M0 RFM9x"
 USB_MANUFACTURER = "Adafruit Industries LLC"
 
@@ -13,7 +13,7 @@ CIRCUITPY_FULL_BUILD = 0
 
 # A number of modules are removed for RFM9x to make room for frozen libraries.
 # Many I/O functions are not available.
-CIRCUITPY_ANALOGIO = 0
+CIRCUITPY_ANALOGIO = 1
 CIRCUITPY_PULSEIO = 0
 CIRCUITPY_NEOPIXEL_WRITE = 1
 CIRCUITPY_ROTARYIO = 0
@@ -22,6 +22,7 @@ CIRCUITPY_SAMD = 0
 CIRCUITPY_USB_MIDI = 0
 CIRCUITPY_USB_HID = 0
 CIRCUITPY_TOUCHIO = 0
+
 CFLAGS_INLINE_LIMIT = 35
 # Make more room.
 SUPEROPT_GC = 0
diff --git a/ports/atmel-samd/boards/feather_m4_can/board.c b/ports/atmel-samd/boards/feather_m4_can/board.c
new file mode 100644
index 000000000..8096b9b8e
--- /dev/null
+++ b/ports/atmel-samd/boards/feather_m4_can/board.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+#include "mpconfigboard.h"
+
+void board_init(void) {
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+}
diff --git a/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.h b/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.h
new file mode 100644
index 000000000..20c4670e2
--- /dev/null
+++ b/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.h
@@ -0,0 +1,35 @@
+#define MICROPY_HW_BOARD_NAME "Adafruit Feather M4 CAN"
+#define MICROPY_HW_MCU_NAME "same51j19a"
+
+#define CIRCUITPY_MCU_FAMILY samd51
+
+// Rev E
+
+#define MICROPY_HW_LED_STATUS   (&pin_PA23)
+#define MICROPY_HW_NEOPIXEL (&pin_PB03)
+
+// These are pins not to reset.
+// QSPI Data pins
+#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11)
+// QSPI CS, QSPI SCK and NeoPixel pin
+#define MICROPY_PORT_B (PORT_PB03 | PORT_PB10 | PORT_PB11)
+#define MICROPY_PORT_C (0)
+#define MICROPY_PORT_D (0)
+
+#define EXTERNAL_FLASH_QSPI_DUAL
+
+#define BOARD_HAS_CRYSTAL 1
+
+#define DEFAULT_I2C_BUS_SCL (&pin_PA13)
+#define DEFAULT_I2C_BUS_SDA (&pin_PA12)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_PA17)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PB23)
+#define DEFAULT_SPI_BUS_MISO (&pin_PB22)
+
+#define DEFAULT_UART_BUS_RX (&pin_PB17)
+#define DEFAULT_UART_BUS_TX (&pin_PB16)
+
+// USB is always used internally so skip the pin objects for it.
+#define IGNORE_PIN_PA24     1
+#define IGNORE_PIN_PA25     1
diff --git a/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.mk b/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.mk
new file mode 100644
index 000000000..345ac33c5
--- /dev/null
+++ b/ports/atmel-samd/boards/feather_m4_can/mpconfigboard.mk
@@ -0,0 +1,15 @@
+USB_VID = 0x239A
+USB_PID = 0x80CE
+USB_PRODUCT = "Feather M4 CAN"
+USB_MANUFACTURER = "Adafruit Industries LLC"
+
+CHIP_VARIANT = SAME51J19A
+CHIP_FAMILY = same51
+
+QSPI_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICE_COUNT = 1
+EXTERNAL_FLASH_DEVICES = GD25Q16C
+LONGINT_IMPL = MPZ
+
+CIRCUITPY_VECTORIO = 1
+CIRCUITPY_CANIO = 1
diff --git a/ports/atmel-samd/boards/feather_m4_can/pins.c b/ports/atmel-samd/boards/feather_m4_can/pins.c
new file mode 100644
index 000000000..015047330
--- /dev/null
+++ b/ports/atmel-samd/boards/feather_m4_can/pins.c
@@ -0,0 +1,65 @@
+#include "shared-bindings/board/__init__.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PA02) },
+
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PA05) },
+
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PB08) },
+
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB09) },
+
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PA04) },
+
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PA06) },
+
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA17) },
+    { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PA17) },
+
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB23) },
+    { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PB23) },
+
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB22) },
+    { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB22) },
+
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PB17) },
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB17) },
+
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PB16) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB16) },
+
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA12) },
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA13) },
+
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA16) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA18) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA19) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA20) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA21) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA22) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA23) },
+
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL_POWER), MP_ROM_PTR(&pin_PB03) },
+
+    { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_BATTERY), MP_ROM_PTR(&pin_PB00) },
+
+    { MP_ROM_QSTR(MP_QSTR_BOOST_ENABLE), MP_ROM_PTR(&pin_PB13) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_RX),  MP_ROM_PTR(&pin_PB15) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_TX),  MP_ROM_PTR(&pin_PB14) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_STANDBY),  MP_ROM_PTR(&pin_PB12) },
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/atmel-samd/boards/feather_m4_express/mpconfigboard.h b/ports/atmel-samd/boards/feather_m4_express/mpconfigboard.h
index ba16d17ee..a57b18e24 100644
--- a/ports/atmel-samd/boards/feather_m4_express/mpconfigboard.h
+++ b/ports/atmel-samd/boards/feather_m4_express/mpconfigboard.h
@@ -16,8 +16,6 @@
 #define MICROPY_PORT_C (0)
 #define MICROPY_PORT_D (0)
 
-#define EXTERNAL_FLASH_QSPI_DUAL
-
 #define BOARD_HAS_CRYSTAL 1
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PA13)
diff --git a/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk b/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk
index 754594f34..9f9bb0501 100755
--- a/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/feather_radiofruit_zigbee/mpconfigboard.mk
@@ -1,5 +1,5 @@
 USB_VID = 0x239A
-USB_PID = 0x8023
+USB_PID = 0x80D0
 USB_PRODUCT = "Feather RadioFruit Zigbee"
 USB_MANUFACTURER = "Adafruit Industries LLC"
 
diff --git a/ports/atmel-samd/boards/hallowing_m0_express/board.c b/ports/atmel-samd/boards/hallowing_m0_express/board.c
index 4717e6ceb..14a2bdb81 100644
--- a/ports/atmel-samd/boards/hallowing_m0_express/board.c
+++ b/ports/atmel-samd/boards/hallowing_m0_express/board.c
@@ -110,7 +110,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // not SH1107
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/hallowing_m4_express/board.c b/ports/atmel-samd/boards/hallowing_m4_express/board.c
index 7da1d8128..61e797d65 100644
--- a/ports/atmel-samd/boards/hallowing_m4_express/board.c
+++ b/ports/atmel-samd/boards/hallowing_m4_express/board.c
@@ -91,7 +91,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // not SH1107
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk b/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk
index 18cef738e..249265151 100644
--- a/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/kicksat-sprite/mpconfigboard.mk
@@ -11,12 +11,12 @@ LONGINT_IMPL = MPZ
 
 # Not needed.
 CIRCUITPY_AUDIOBUSIO = 0
-CIRCUITPY_FRAMEBUFFERIO = 0
+CIRCUITPY_AUDIOMP3 = 0
+CIRCUITPY_BLEIO_HCI = 0
 CIRCUITPY_DISPLAYIO = 0
-CIRCUITPY_RGBMATRIX = 0
+CIRCUITPY_FRAMEBUFFERIO = 0
 CIRCUITPY_PS2IO = 0
-CIRCUITPY_AUDIOMP3 = 0
-
+CIRCUITPY_RGBMATRIX = 0
 CIRCUITPY_ULAB = 0
 
 # Override optimization to keep binary small
diff --git a/ports/atmel-samd/boards/matrixportal_m4/mpconfigboard.h b/ports/atmel-samd/boards/matrixportal_m4/mpconfigboard.h
index 0368d577b..475752afb 100644
--- a/ports/atmel-samd/boards/matrixportal_m4/mpconfigboard.h
+++ b/ports/atmel-samd/boards/matrixportal_m4/mpconfigboard.h
@@ -9,14 +9,14 @@
 
 // These are pins not to reset.
 // QSPI Data pins, PA23 is NeoPixel
-#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 | PA23)
+#define MICROPY_PORT_A (PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 | PORT_PA23)
 // QSPI CS, QSPI SCK
 #define MICROPY_PORT_B (PORT_PB10 | PORT_PB11)
 #define MICROPY_PORT_C (0)
 #define MICROPY_PORT_D (0)
 
-#define DEFAULT_I2C_BUS_SCL (&pin_PB03)
-#define DEFAULT_I2C_BUS_SDA (&pin_PB02)
+#define DEFAULT_I2C_BUS_SCL (&pin_PB30)
+#define DEFAULT_I2C_BUS_SDA (&pin_PB31)
 
 #define DEFAULT_SPI_BUS_SCK (&pin_PA16)
 #define DEFAULT_SPI_BUS_MOSI (&pin_PA19)
diff --git a/ports/atmel-samd/boards/matrixportal_m4/pins.c b/ports/atmel-samd/boards/matrixportal_m4/pins.c
index 34865597b..1f9956d9e 100644
--- a/ports/atmel-samd/boards/matrixportal_m4/pins.c
+++ b/ports/atmel-samd/boards/matrixportal_m4/pins.c
@@ -16,8 +16,8 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
     { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_BUSY), MP_ROM_PTR(&pin_PA22) },
     { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RESET), MP_ROM_PTR(&pin_PA21) },
     { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RTS), MP_ROM_PTR(&pin_PA18) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_PA12) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_PA13) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_PA13) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_PA12) },
 
     { MP_OBJ_NEW_QSTR(MP_QSTR_SCL),MP_ROM_PTR(&pin_PB30) },
     { MP_OBJ_NEW_QSTR(MP_QSTR_SDA),MP_ROM_PTR(&pin_PB31) },
diff --git a/ports/atmel-samd/boards/meowmeow/mpconfigboard.h b/ports/atmel-samd/boards/meowmeow/mpconfigboard.h
index 80d367863..7bbbf3322 100644
--- a/ports/atmel-samd/boards/meowmeow/mpconfigboard.h
+++ b/ports/atmel-samd/boards/meowmeow/mpconfigboard.h
@@ -11,7 +11,7 @@
 #define CALIBRATE_CRYSTALLESS 1
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PA01)
 #define DEFAULT_I2C_BUS_SDA (&pin_PA00)
diff --git a/ports/atmel-samd/boards/metro_m4_airlift_lite/mpconfigboard.mk b/ports/atmel-samd/boards/metro_m4_airlift_lite/mpconfigboard.mk
index e999629c3..4895cda77 100644
--- a/ports/atmel-samd/boards/metro_m4_airlift_lite/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/metro_m4_airlift_lite/mpconfigboard.mk
@@ -6,10 +6,6 @@ USB_MANUFACTURER = "Adafruit Industries LLC"
 CHIP_VARIANT = SAMD51J19A
 CHIP_FAMILY = samd51
 
-# Support _bleio via the on-board ESP32 module.
-CIRCUITPY_BLEIO = 1
-CIRCUITPY_BLEIO_HCI = 1
-
 QSPI_FLASH_FILESYSTEM = 1
 EXTERNAL_FLASH_DEVICE_COUNT = 3
 EXTERNAL_FLASH_DEVICES = "S25FL116K, S25FL216K, GD25Q16C"
diff --git a/ports/atmel-samd/boards/monster_m4sk/board.c b/ports/atmel-samd/boards/monster_m4sk/board.c
index 4dd65f8c9..45fea9d52 100644
--- a/ports/atmel-samd/boards/monster_m4sk/board.c
+++ b/ports/atmel-samd/boards/monster_m4sk/board.c
@@ -92,7 +92,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/openbook_m4/board.c b/ports/atmel-samd/boards/openbook_m4/board.c
index f0010f6d7..07dd1741a 100644
--- a/ports/atmel-samd/boards/openbook_m4/board.c
+++ b/ports/atmel-samd/boards/openbook_m4/board.c
@@ -97,7 +97,8 @@ void board_init(void) {
         &pin_PA01, // busy_pin
         false, // busy_state
         5, // seconds_per_frame
-        false); // chip_select (don't always toggle chip select)
+        false, // chip_select (don't always toggle chip select)
+        false); // grayscale
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pewpew10/mpconfigboard.mk b/ports/atmel-samd/boards/pewpew10/mpconfigboard.mk
index 7305abf73..1cc91a8df 100644
--- a/ports/atmel-samd/boards/pewpew10/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/pewpew10/mpconfigboard.mk
@@ -1,5 +1,5 @@
 USB_VID = 0x239A
-USB_PID = 0x801D
+USB_PID = 0x80D5
 USB_PRODUCT = "PewPew 10.2"
 USB_MANUFACTURER = "Radomir Dopieralski"
 
diff --git a/ports/atmel-samd/boards/pewpew_m4/board.c b/ports/atmel-samd/boards/pewpew_m4/board.c
index 52a52b4b7..d02e0dc01 100644
--- a/ports/atmel-samd/boards/pewpew_m4/board.c
+++ b/ports/atmel-samd/boards/pewpew_m4/board.c
@@ -143,7 +143,8 @@ void board_init(void) {
         false, // data_as_commands
         false, // auto_refresh
         20, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pybadge/board.c b/ports/atmel-samd/boards/pybadge/board.c
index 45298acc2..35f228c75 100644
--- a/ports/atmel-samd/boards/pybadge/board.c
+++ b/ports/atmel-samd/boards/pybadge/board.c
@@ -114,7 +114,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pybadge_airlift/board.c b/ports/atmel-samd/boards/pybadge_airlift/board.c
index 7495c7d48..fe3e4a017 100644
--- a/ports/atmel-samd/boards/pybadge_airlift/board.c
+++ b/ports/atmel-samd/boards/pybadge_airlift/board.c
@@ -92,7 +92,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pygamer/board.c b/ports/atmel-samd/boards/pygamer/board.c
index 2e83440ea..b478b5947 100644
--- a/ports/atmel-samd/boards/pygamer/board.c
+++ b/ports/atmel-samd/boards/pygamer/board.c
@@ -114,7 +114,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pygamer_advance/board.c b/ports/atmel-samd/boards/pygamer_advance/board.c
index 330446b6f..7dfe07c00 100644
--- a/ports/atmel-samd/boards/pygamer_advance/board.c
+++ b/ports/atmel-samd/boards/pygamer_advance/board.c
@@ -92,7 +92,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pyportal/board.c b/ports/atmel-samd/boards/pyportal/board.c
index d14b6b6a5..cd94f6887 100644
--- a/ports/atmel-samd/boards/pyportal/board.c
+++ b/ports/atmel-samd/boards/pyportal/board.c
@@ -100,7 +100,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pyportal_titano/board.c b/ports/atmel-samd/boards/pyportal_titano/board.c
index 0ee2e68aa..dc417f5d1 100644
--- a/ports/atmel-samd/boards/pyportal_titano/board.c
+++ b/ports/atmel-samd/boards/pyportal_titano/board.c
@@ -117,7 +117,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/qtpy_m0/board.c b/ports/atmel-samd/boards/qtpy_m0/board.c
new file mode 100644
index 000000000..1a65a561f
--- /dev/null
+++ b/ports/atmel-samd/boards/qtpy_m0/board.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+#include "common-hal/microcontroller/Pin.h"
+#include "supervisor/shared/board.h"
+#include "hal/include/hal_gpio.h"
+
+void board_init(void) {
+    gpio_set_pin_function(PIN_PA15, GPIO_PIN_FUNCTION_OFF);
+    gpio_set_pin_direction(PIN_PA15, GPIO_DIRECTION_OUT);
+    gpio_set_pin_level(PIN_PA15, true); // Turn on neopixel by default
+    never_reset_pin_number(PIN_PA15);
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+}
diff --git a/ports/atmel-samd/boards/qtpy_m0/mpconfigboard.h b/ports/atmel-samd/boards/qtpy_m0/mpconfigboard.h
new file mode 100644
index 000000000..713d2c03e
--- /dev/null
+++ b/ports/atmel-samd/boards/qtpy_m0/mpconfigboard.h
@@ -0,0 +1,55 @@
+#define MICROPY_HW_BOARD_NAME "Adafruit QT Py M0"
+#define MICROPY_HW_MCU_NAME "samd21e18"
+
+#define MICROPY_HW_NEOPIXEL (&pin_PA18)
+
+#define MICROPY_PORT_A        (0)
+#define MICROPY_PORT_B        (0)
+#define MICROPY_PORT_C        (0)
+
+#define IGNORE_PIN_PA00     1
+#define IGNORE_PIN_PA01     1
+#define IGNORE_PIN_PA12     1
+#define IGNORE_PIN_PA13     1
+#define IGNORE_PIN_PA14     1
+#define IGNORE_PIN_PA20     1
+#define IGNORE_PIN_PA21     1
+// USB is always used internally so skip the pin objects for it.
+#define IGNORE_PIN_PA24     1
+#define IGNORE_PIN_PA25     1
+#define IGNORE_PIN_PA27     1
+#define IGNORE_PIN_PA28     1
+#define IGNORE_PIN_PA30     1
+#define IGNORE_PIN_PA31     1
+#define IGNORE_PIN_PB01     1
+#define IGNORE_PIN_PB02     1
+#define IGNORE_PIN_PB03     1
+#define IGNORE_PIN_PB04     1
+#define IGNORE_PIN_PB05     1
+#define IGNORE_PIN_PB06     1
+#define IGNORE_PIN_PB07     1
+#define IGNORE_PIN_PB08     1
+#define IGNORE_PIN_PB09     1
+#define IGNORE_PIN_PB10     1
+#define IGNORE_PIN_PB11     1
+#define IGNORE_PIN_PB12     1
+#define IGNORE_PIN_PB13     1
+#define IGNORE_PIN_PB14     1
+#define IGNORE_PIN_PB15     1
+#define IGNORE_PIN_PB16     1
+#define IGNORE_PIN_PB17     1
+#define IGNORE_PIN_PB22     1
+#define IGNORE_PIN_PB23     1
+#define IGNORE_PIN_PB30     1
+#define IGNORE_PIN_PB31     1
+#define IGNORE_PIN_PB00     1
+
+#define DEFAULT_I2C_BUS_SCL (&pin_PA17)
+#define DEFAULT_I2C_BUS_SDA (&pin_PA16)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_PA11)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PA10)
+#define DEFAULT_SPI_BUS_MISO (&pin_PA09)
+
+#define DEFAULT_UART_BUS_RX (&pin_PA07)
+#define DEFAULT_UART_BUS_TX (&pin_PA06)
diff --git a/ports/atmel-samd/boards/qtpy_m0/mpconfigboard.mk b/ports/atmel-samd/boards/qtpy_m0/mpconfigboard.mk
new file mode 100644
index 000000000..964cbe643
--- /dev/null
+++ b/ports/atmel-samd/boards/qtpy_m0/mpconfigboard.mk
@@ -0,0 +1,24 @@
+USB_VID = 0x239A
+USB_PID = 0x80CC
+USB_PRODUCT = "QT Py M0"
+USB_MANUFACTURER = "Adafruit Industries LLC"
+
+CHIP_VARIANT = SAMD21E18A
+CHIP_FAMILY = samd21
+
+INTERNAL_FLASH_FILESYSTEM = 1
+LONGINT_IMPL = NONE
+CIRCUITPY_FULL_BUILD = 0
+
+SUPEROPT_GC = 0
+
+CFLAGS_BOARD = --param max-inline-insns-auto=15
+ifeq ($(TRANSLATION), zh_Latn_pinyin)
+RELEASE_NEEDS_CLEAN_BUILD = 1
+CFLAGS_INLINE_LIMIT = 35
+endif
+ifeq ($(TRANSLATION), de_DE)
+RELEASE_NEEDS_CLEAN_BUILD = 1
+CFLAGS_INLINE_LIMIT = 35
+SUPEROPT_VM = 0
+endif
diff --git a/ports/atmel-samd/boards/qtpy_m0/pins.c b/ports/atmel-samd/boards/qtpy_m0/pins.c
new file mode 100644
index 000000000..636c48bff
--- /dev/null
+++ b/ports/atmel-samd/boards/qtpy_m0/pins.c
@@ -0,0 +1,49 @@
+#include "shared-bindings/board/__init__.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) },
+
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA03) },
+
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA04) },
+
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA05) },
+
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA16) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA16) },
+
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA17) },
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA17) },
+
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA06) },
+
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA07) },
+
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA11) },
+
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA09) },
+
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA10) },
+
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA18) },
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL_POWER), MP_ROM_PTR(&pin_PA15) },
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/atmel-samd/boards/qtpy_m0_haxpress/board.c b/ports/atmel-samd/boards/qtpy_m0_haxpress/board.c
new file mode 100644
index 000000000..1a65a561f
--- /dev/null
+++ b/ports/atmel-samd/boards/qtpy_m0_haxpress/board.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+#include "common-hal/microcontroller/Pin.h"
+#include "supervisor/shared/board.h"
+#include "hal/include/hal_gpio.h"
+
+void board_init(void) {
+    gpio_set_pin_function(PIN_PA15, GPIO_PIN_FUNCTION_OFF);
+    gpio_set_pin_direction(PIN_PA15, GPIO_DIRECTION_OUT);
+    gpio_set_pin_level(PIN_PA15, true); // Turn on neopixel by default
+    never_reset_pin_number(PIN_PA15);
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+}
diff --git a/ports/atmel-samd/boards/qtpy_m0_haxpress/mpconfigboard.h b/ports/atmel-samd/boards/qtpy_m0_haxpress/mpconfigboard.h
new file mode 100644
index 000000000..4e557751f
--- /dev/null
+++ b/ports/atmel-samd/boards/qtpy_m0_haxpress/mpconfigboard.h
@@ -0,0 +1,60 @@
+#define MICROPY_HW_BOARD_NAME "Adafruit QT Py M0 Haxpress"
+#define MICROPY_HW_MCU_NAME "samd21e18"
+
+#define MICROPY_HW_NEOPIXEL (&pin_PA18)
+
+#define MICROPY_PORT_A        (0)
+#define MICROPY_PORT_B        (0)
+#define MICROPY_PORT_C        (0)
+
+#define SPI_FLASH_MOSI_PIN          &pin_PA22
+#define SPI_FLASH_MISO_PIN          &pin_PA19
+#define SPI_FLASH_SCK_PIN           &pin_PA23
+#define SPI_FLASH_CS_PIN            &pin_PA08
+
+#define IGNORE_PIN_PA00     1
+#define IGNORE_PIN_PA01     1
+#define IGNORE_PIN_PA12     1
+#define IGNORE_PIN_PA13     1
+#define IGNORE_PIN_PA14     1
+#define IGNORE_PIN_PA20     1
+#define IGNORE_PIN_PA21     1
+// USB is always used internally so skip the pin objects for it.
+#define IGNORE_PIN_PA24     1
+#define IGNORE_PIN_PA25     1
+#define IGNORE_PIN_PA27     1
+#define IGNORE_PIN_PA28     1
+#define IGNORE_PIN_PA30     1
+#define IGNORE_PIN_PA31     1
+#define IGNORE_PIN_PB01     1
+#define IGNORE_PIN_PB02     1
+#define IGNORE_PIN_PB03     1
+#define IGNORE_PIN_PB04     1
+#define IGNORE_PIN_PB05     1
+#define IGNORE_PIN_PB06     1
+#define IGNORE_PIN_PB07     1
+#define IGNORE_PIN_PB08     1
+#define IGNORE_PIN_PB09     1
+#define IGNORE_PIN_PB10     1
+#define IGNORE_PIN_PB11     1
+#define IGNORE_PIN_PB12     1
+#define IGNORE_PIN_PB13     1
+#define IGNORE_PIN_PB14     1
+#define IGNORE_PIN_PB15     1
+#define IGNORE_PIN_PB16     1
+#define IGNORE_PIN_PB17     1
+#define IGNORE_PIN_PB22     1
+#define IGNORE_PIN_PB23     1
+#define IGNORE_PIN_PB30     1
+#define IGNORE_PIN_PB31     1
+#define IGNORE_PIN_PB00     1
+
+#define DEFAULT_I2C_BUS_SCL (&pin_PA17)
+#define DEFAULT_I2C_BUS_SDA (&pin_PA16)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_PA11)
+#define DEFAULT_SPI_BUS_MOSI (&pin_PA10)
+#define DEFAULT_SPI_BUS_MISO (&pin_PA09)
+
+#define DEFAULT_UART_BUS_RX (&pin_PA07)
+#define DEFAULT_UART_BUS_TX (&pin_PA06)
diff --git a/ports/atmel-samd/boards/qtpy_m0_haxpress/mpconfigboard.mk b/ports/atmel-samd/boards/qtpy_m0_haxpress/mpconfigboard.mk
new file mode 100644
index 000000000..a63f14274
--- /dev/null
+++ b/ports/atmel-samd/boards/qtpy_m0_haxpress/mpconfigboard.mk
@@ -0,0 +1,32 @@
+USB_VID = 0x239A
+USB_PID = 0x00CC
+USB_PRODUCT = "QT Py M0 Haxpress"
+USB_MANUFACTURER = "Adafruit Industries LLC"
+
+CHIP_VARIANT = SAMD21E18A
+CHIP_FAMILY = samd21
+
+INTERNAL_FLASH_FILESYSTEM = 0
+LONGINT_IMPL = MPZ
+SPI_FLASH_FILESYSTEM = 1
+EXTERNAL_FLASH_DEVICE_COUNT = 1
+EXTERNAL_FLASH_DEVICES = GD25Q16C
+
+CIRCUITPY_AUDIOBUSIO = 0
+CIRCUITPY_BITBANGIO = 0
+CIRCUITPY_COUNTIO = 0
+CIRCUITPY_FREQUENCYIO = 0
+CIRCUITPY_I2CPERIPHERAL = 0
+
+SUPEROPT_GC = 0
+
+CFLAGS_BOARD = --param max-inline-insns-auto=15
+ifeq ($(TRANSLATION), zh_Latn_pinyin)
+RELEASE_NEEDS_CLEAN_BUILD = 1
+CFLAGS_INLINE_LIMIT = 35
+endif
+ifeq ($(TRANSLATION), de_DE)
+RELEASE_NEEDS_CLEAN_BUILD = 1
+CFLAGS_INLINE_LIMIT = 35
+SUPEROPT_VM = 0
+endif
diff --git a/ports/atmel-samd/boards/qtpy_m0_haxpress/pins.c b/ports/atmel-samd/boards/qtpy_m0_haxpress/pins.c
new file mode 100644
index 000000000..636c48bff
--- /dev/null
+++ b/ports/atmel-samd/boards/qtpy_m0_haxpress/pins.c
@@ -0,0 +1,49 @@
+#include "shared-bindings/board/__init__.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) },
+
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA03) },
+
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA04) },
+
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA05) },
+
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA16) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA16) },
+
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA17) },
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA17) },
+
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA06) },
+
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA07) },
+
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA11) },
+
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA09) },
+
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA10) },
+
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA18) },
+    { MP_ROM_QSTR(MP_QSTR_NEOPIXEL_POWER), MP_ROM_PTR(&pin_PA15) },
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/atmel-samd/boards/same54_xplained/mpconfigboard.mk b/ports/atmel-samd/boards/same54_xplained/mpconfigboard.mk
index 7ac126514..e4472e05d 100644
--- a/ports/atmel-samd/boards/same54_xplained/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/same54_xplained/mpconfigboard.mk
@@ -12,3 +12,4 @@ EXTERNAL_FLASH_DEVICES = "N25Q256A"
 LONGINT_IMPL = MPZ
 
 CIRCUITPY_SDIOIO = 1
+CIRCUITPY_CANIO = 1
diff --git a/ports/atmel-samd/boards/same54_xplained/pins.c b/ports/atmel-samd/boards/same54_xplained/pins.c
index 8a864ab97..1ed431fba 100644
--- a/ports/atmel-samd/boards/same54_xplained/pins.c
+++ b/ports/atmel-samd/boards/same54_xplained/pins.c
@@ -48,8 +48,9 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
 
     { MP_OBJ_NEW_QSTR(MP_QSTR_QT),  MP_ROM_PTR(&pin_PA16) },
 
-    { MP_OBJ_NEW_QSTR(MP_QSTR_CANRX),  MP_ROM_PTR(&pin_PB12) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_CANTX),  MP_ROM_PTR(&pin_PB13) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_RX),  MP_ROM_PTR(&pin_PB13) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_TX),  MP_ROM_PTR(&pin_PB12) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_CAN_STANDBY),  MP_ROM_PTR(&pin_PC13) },
 
     // EXT1 header
     { MP_OBJ_NEW_QSTR(MP_QSTR_PB04),  MP_ROM_PTR(&pin_PB04) },
diff --git a/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c b/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c
index b7fc736eb..49db49860 100644
--- a/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c
+++ b/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c
@@ -31,8 +31,12 @@
 #include "shared-bindings/displayio/FourWire.h"
 #include "shared-module/displayio/__init__.h"
 #include "shared-module/displayio/mipi_constants.h"
+#include "shared-bindings/digitalio/DigitalInOut.h"
 
 displayio_fourwire_obj_t board_display_obj;
+digitalio_digitalinout_obj_t CTR_5V;
+digitalio_digitalinout_obj_t CTR_3V3;
+digitalio_digitalinout_obj_t USB_HOST_ENABLE;
 
 uint8_t display_init_sequence[] = {
     0x01, 0x80, 0x80, // Software reset then delay 0x80 (128ms)
@@ -105,7 +109,27 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
+
+        // Enabling the Power of the 40-pin at the back
+        CTR_5V.base.type = &digitalio_digitalinout_type;
+        CTR_3V3.base.type = &digitalio_digitalinout_type;
+        USB_HOST_ENABLE.base.type = &digitalio_digitalinout_type;
+
+        common_hal_digitalio_digitalinout_construct(&CTR_5V, PIN_CTR_5V);
+        common_hal_digitalio_digitalinout_construct(&CTR_3V3, PIN_CTR_3V3);
+        common_hal_digitalio_digitalinout_construct(&USB_HOST_ENABLE, PIN_USB_HOST_ENABLE);
+
+        common_hal_digitalio_digitalinout_set_value(&CTR_5V, true);
+        common_hal_digitalio_digitalinout_set_value(&CTR_3V3, false);
+        common_hal_digitalio_digitalinout_set_value(&USB_HOST_ENABLE, false);
+
+        // Never reset
+        common_hal_digitalio_digitalinout_never_reset(&CTR_5V);
+        common_hal_digitalio_digitalinout_never_reset(&CTR_3V3);
+        common_hal_digitalio_digitalinout_never_reset(&USB_HOST_ENABLE);
+
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/seeeduino_wio_terminal/mpconfigboard.h b/ports/atmel-samd/boards/seeeduino_wio_terminal/mpconfigboard.h
index f7d0448df..c87ca46d8 100644
--- a/ports/atmel-samd/boards/seeeduino_wio_terminal/mpconfigboard.h
+++ b/ports/atmel-samd/boards/seeeduino_wio_terminal/mpconfigboard.h
@@ -27,6 +27,10 @@
 #define DEFAULT_UART_BUS_RX (&pin_PB27)
 #define DEFAULT_UART_BUS_TX (&pin_PB26)
 
+#define PIN_CTR_5V (&pin_PC14)
+#define PIN_CTR_3V3 (&pin_PC15)
+#define PIN_USB_HOST_ENABLE (&pin_PA27)
+
 // USB is always used internally so skip the pin objects for it.
 #define IGNORE_PIN_PA24     1
 #define IGNORE_PIN_PA25     1
diff --git a/ports/atmel-samd/boards/sparkfun_lumidrive/mpconfigboard.h b/ports/atmel-samd/boards/sparkfun_lumidrive/mpconfigboard.h
index d184945f3..80f37429f 100755
--- a/ports/atmel-samd/boards/sparkfun_lumidrive/mpconfigboard.h
+++ b/ports/atmel-samd/boards/sparkfun_lumidrive/mpconfigboard.h
@@ -35,9 +35,6 @@
 #define IGNORE_PIN_PA12     1
 #define IGNORE_PIN_PA15     1
 #define IGNORE_PIN_PA16     1
-#define IGNORE_PIN_PA21     1
-#define IGNORE_PIN_PA22     1
-#define IGNORE_PIN_PA23     1
 #define IGNORE_PIN_PA27     1
 #define IGNORE_PIN_PA28     1
 
diff --git a/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk b/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk
index 402db7ebc..7eda151f3 100644
--- a/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/trinket_m0_haxpress/mpconfigboard.mk
@@ -17,6 +17,7 @@ CIRCUITPY_COUNTIO = 0
 CIRCUITPY_RTC = 0
 CIRCUITPY_FREQUENCYIO = 0
 CIRCUITPY_I2CPERIPHERAL = 0
+MICROPY_PY_ASYNC_AWAIT = 0
 
 SUPEROPT_GC = 0
 
diff --git a/ports/atmel-samd/boards/uchip/mpconfigboard.h b/ports/atmel-samd/boards/uchip/mpconfigboard.h
index 1877a41ef..5d6af4b78 100644
--- a/ports/atmel-samd/boards/uchip/mpconfigboard.h
+++ b/ports/atmel-samd/boards/uchip/mpconfigboard.h
@@ -16,8 +16,6 @@
 
 #define IGNORE_PIN_PA27     1
 #define IGNORE_PIN_PA28     1
-#define IGNORE_PIN_PA30     1
-#define IGNORE_PIN_PA31     1
 
 #define IGNORE_PIN_PB01     1
 #define IGNORE_PIN_PB02     1
diff --git a/ports/atmel-samd/boards/uchip/pins.c b/ports/atmel-samd/boards/uchip/pins.c
index 856a22074..de5508110 100644
--- a/ports/atmel-samd/boards/uchip/pins.c
+++ b/ports/atmel-samd/boards/uchip/pins.c
@@ -1,14 +1,18 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
-    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA08) },
-    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA10) },
-    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA09) },
-    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA11) },
-    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA02) },
-    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA04) },
-    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA03) },
-    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA07) },
+    { MP_ROM_QSTR(MP_QSTR_BOOST_EN), MP_ROM_PTR(&pin_PA14) },
+    { MP_ROM_QSTR(MP_QSTR_VEXT_SELECT), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA08) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA10) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA09) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA11) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PA04) },
     { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA16) },
     { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA08) },
     { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA10) },
@@ -19,8 +23,10 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
     { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA19) },
     { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA22) },
     { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA23) },
-    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PA03) },
-    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA31) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA30) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PA02) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PA03) },
     { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA09) },
     { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA08) },
     { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) },
diff --git a/ports/atmel-samd/boards/ugame10/board.c b/ports/atmel-samd/boards/ugame10/board.c
index 3bb9eab7d..9f2b8d039 100644
--- a/ports/atmel-samd/boards/ugame10/board.c
+++ b/ports/atmel-samd/boards/ugame10/board.c
@@ -111,7 +111,8 @@ void board_init(void) {
         false, // data as commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/ugame10/mpconfigboard.mk b/ports/atmel-samd/boards/ugame10/mpconfigboard.mk
index bd320d9e4..b1242d206 100644
--- a/ports/atmel-samd/boards/ugame10/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/ugame10/mpconfigboard.mk
@@ -1,5 +1,5 @@
 USB_VID = 0x239A
-USB_PID = 0x801F
+USB_PID = 0x80AF
 USB_PRODUCT = "uGame10"
 USB_MANUFACTURER = "Radomir Dopieralski"
 
diff --git a/ports/atmel-samd/boards/winterbloom_sol/mpconfigboard.mk b/ports/atmel-samd/boards/winterbloom_sol/mpconfigboard.mk
index 9217cdf23..fcefaee9b 100644
--- a/ports/atmel-samd/boards/winterbloom_sol/mpconfigboard.mk
+++ b/ports/atmel-samd/boards/winterbloom_sol/mpconfigboard.mk
@@ -18,7 +18,7 @@ LONGINT_IMPL = MPZ
 # Disable modules that are unusable on this special-purpose board.
 CIRCUITPY_AUDIOBUSIO = 0
 CIRCUITPY_AUDIOIO = 0
-CIRCUITPY_BLEIO = 0
+CIRCUITPY_BLEIO_HCI = 0
 CIRCUITPY_DISPLAYIO = 0
 CIRCUITPY_FRAMEBUFFERIO = 0
 CIRCUITPY_GAMEPAD = 0
diff --git a/ports/atmel-samd/common-hal/analogio/AnalogOut.c b/ports/atmel-samd/common-hal/analogio/AnalogOut.c
index fac4c6bfc..1565b0a8f 100644
--- a/ports/atmel-samd/common-hal/analogio/AnalogOut.c
+++ b/ports/atmel-samd/common-hal/analogio/AnalogOut.c
@@ -44,26 +44,36 @@
 #include "hpl/pm/hpl_pm_base.h"
 #endif
 
+#define HAVE_ANALOGOUT ( \
+    (defined(PIN_PA02) && !defined(IGNORE_PA02)) || \
+    (defined(SAM_D5X_E5X) && defined(PIN_PA05) && !defined(IGNORE_PA05)) \
+)
+
 void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self,
         const mcu_pin_obj_t *pin) {
-    #if defined(SAMD21) && !defined(PIN_PA02)
+    #if !HAVE_ANALOGOUT
     mp_raise_NotImplementedError(translate("No DAC on chip"));
     #else
-    if (pin->number != PIN_PA02
-    #ifdef SAM_D5X_E5X
-        && pin->number != PIN_PA05
+
+    int channel = -1;
+
+    #if defined(PIN_PA02) && !defined(IGNORE_PIN_PA02)
+    if (pin->number != PIN_PA02) {
+        channel = 0;
+    }
+    #endif
+    #if defined(PIN_PA05) && defined(PIN_PA05) && !defined(IGNORE_PIN_PA05)
+    if (pin->number != PIN_PA05) {
+        channel = 1;
+    }
     #endif
-    ) {
+
+    if(channel == -1) {
         mp_raise_ValueError(translate("AnalogOut not supported on given pin"));
         return;
     }
 
-    self->channel = 0;
-    #ifdef SAM_D5X_E5X
-    if (pin->number == PIN_PA05) {
-        self->channel = 1;
-    }
-    #endif
+    self->channel = channel;
 
     #ifdef SAM_D5X_E5X
     hri_mclk_set_APBDMASK_DAC_bit(MCLK);
@@ -105,11 +115,15 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self,
 }
 
 bool common_hal_analogio_analogout_deinited(analogio_analogout_obj_t *self) {
+    #if !HAVE_ANALOGOUT
+    return false;
+    #else
     return self->deinited;
+    #endif
 }
 
 void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) {
-    #if (defined(SAMD21) && defined(PIN_PA02)) || defined(SAM_D5X_E5X)
+    #if HAVE_ANALOGOUT
     if (common_hal_analogio_analogout_deinited(self)) {
         return;
     }
@@ -130,12 +144,11 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) {
 
 void common_hal_analogio_analogout_set_value(analogio_analogout_obj_t *self,
         uint16_t value) {
-    #if defined(SAMD21) && !defined(PIN_PA02)
-    return;
-    #endif
+    #if HAVE_ANALOGOUT
     // Input is 16 bit so make sure and set LEFTADJ to 1 so it takes the top
     // bits. This is currently done in asf4_conf/*/hpl_dac_config.h.
     dac_sync_write(&self->descriptor, self->channel, &value, 1);
+    #endif
 }
 
 void analogout_reset(void) {
@@ -143,7 +156,7 @@ void analogout_reset(void) {
     // if it was enabled, so do that instead if AudioOut is enabled.
 #if CIRCUITPY_AUDIOIO
     audioout_reset();
-#else
+#elif HAVE_ANALOGOUT
     #ifdef SAMD21
     while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {}
     #endif
diff --git a/ports/atmel-samd/common-hal/busio/SPI.c b/ports/atmel-samd/common-hal/busio/SPI.c
index 921713d69..189fd93b5 100644
--- a/ports/atmel-samd/common-hal/busio/SPI.c
+++ b/ports/atmel-samd/common-hal/busio/SPI.c
@@ -98,8 +98,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
     uint8_t miso_pad = 0;
     uint8_t dopo = 255;
 
-    // Special case for SAMR boards.
-    #ifdef PIN_PC19
+    // Special case for SAMR21 boards. (feather_radiofruit_zigbee)
+    #if defined(PIN_PC19F_SERCOM4_PAD0)
     if (miso == &pin_PC19) {
         if (mosi == &pin_PB30 && clock == &pin_PC18) {
             sercom = SERCOM4;
@@ -113,67 +113,67 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
             dopo = samd_peripherals_get_spi_dopo(clock_pad, mosi_pad);
         }
         // Error, leave SERCOM unset to throw an exception later.
-    } else {
+    } else
     #endif
-    for (int i = 0; i < NUM_SERCOMS_PER_PIN; i++) {
-        sercom_index = clock->sercom[i].index; // 2 for SERCOM2, etc.
-        if (sercom_index >= SERCOM_INST_NUM) {
-            continue;
-        }
-        Sercom* potential_sercom = sercom_insts[sercom_index];
-        if (
-        #if defined(MICROPY_HW_APA102_SCK) && defined(MICROPY_HW_APA102_MOSI) && !CIRCUITPY_BITBANG_APA102
-            (potential_sercom->SPI.CTRLA.bit.ENABLE != 0 &&
-             potential_sercom != status_apa102.spi_desc.dev.prvt &&
-             !apa102_sck_in_use)) {
-        #else
-            potential_sercom->SPI.CTRLA.bit.ENABLE != 0) {
-        #endif
-            continue;
-        }
-        clock_pinmux = PINMUX(clock->number, (i == 0) ? MUX_C : MUX_D);
-        clock_pad = clock->sercom[i].pad;
-        if (!samd_peripherals_valid_spi_clock_pad(clock_pad)) {
-            continue;
-        }
-        for (int j = 0; j < NUM_SERCOMS_PER_PIN; j++) {
-            if (!mosi_none) {
-                if (sercom_index == mosi->sercom[j].index) {
-                    mosi_pinmux = PINMUX(mosi->number, (j == 0) ? MUX_C : MUX_D);
-                    mosi_pad = mosi->sercom[j].pad;
-                    dopo = samd_peripherals_get_spi_dopo(clock_pad, mosi_pad);
-                    if (dopo > 0x3) {
-                        continue;  // pad combination not possible
-                    }
-                    if (miso_none) {
-                        sercom = potential_sercom;
-                        break;
+    {
+        for (int i = 0; i < NUM_SERCOMS_PER_PIN; i++) {
+            sercom_index = clock->sercom[i].index; // 2 for SERCOM2, etc.
+            if (sercom_index >= SERCOM_INST_NUM) {
+                continue;
+            }
+            Sercom* potential_sercom = sercom_insts[sercom_index];
+            if (
+            #if defined(MICROPY_HW_APA102_SCK) && defined(MICROPY_HW_APA102_MOSI) && !CIRCUITPY_BITBANG_APA102
+                (potential_sercom->SPI.CTRLA.bit.ENABLE != 0 &&
+                 potential_sercom != status_apa102.spi_desc.dev.prvt &&
+                 !apa102_sck_in_use)
+            #else
+                potential_sercom->SPI.CTRLA.bit.ENABLE != 0
+            #endif
+            ) {
+                continue;
+            }
+            clock_pinmux = PINMUX(clock->number, (i == 0) ? MUX_C : MUX_D);
+            clock_pad = clock->sercom[i].pad;
+            if (!samd_peripherals_valid_spi_clock_pad(clock_pad)) {
+                continue;
+            }
+            for (int j = 0; j < NUM_SERCOMS_PER_PIN; j++) {
+                if (!mosi_none) {
+                    if (sercom_index == mosi->sercom[j].index) {
+                        mosi_pinmux = PINMUX(mosi->number, (j == 0) ? MUX_C : MUX_D);
+                        mosi_pad = mosi->sercom[j].pad;
+                        dopo = samd_peripherals_get_spi_dopo(clock_pad, mosi_pad);
+                        if (dopo > 0x3) {
+                            continue;  // pad combination not possible
+                        }
+                        if (miso_none) {
+                            sercom = potential_sercom;
+                            break;
+                        }
+                    } else {
+                        continue;
                     }
-                } else {
-                    continue;
                 }
-            }
-            if (!miso_none) {
-                for (int k = 0; k < NUM_SERCOMS_PER_PIN; k++) {
-                    if (sercom_index == miso->sercom[k].index) {
-                        miso_pinmux = PINMUX(miso->number, (k == 0) ? MUX_C : MUX_D);
-                        miso_pad = miso->sercom[k].pad;
-                        sercom = potential_sercom;
-                        break;
+                if (!miso_none) {
+                    for (int k = 0; k < NUM_SERCOMS_PER_PIN; k++) {
+                        if (sercom_index == miso->sercom[k].index) {
+                            miso_pinmux = PINMUX(miso->number, (k == 0) ? MUX_C : MUX_D);
+                            miso_pad = miso->sercom[k].pad;
+                            sercom = potential_sercom;
+                            break;
+                        }
                     }
                 }
+                if (sercom != NULL) {
+                    break;
+                }
             }
             if (sercom != NULL) {
                 break;
             }
-        }
-        if (sercom != NULL) {
-            break;
-        }
     }
-    #ifdef PIN_PC19
     }
-    #endif
     if (sercom == NULL) {
         mp_raise_ValueError(translate("Invalid pins"));
     }
diff --git a/ports/atmel-samd/common-hal/canio/CAN.c b/ports/atmel-samd/common-hal/canio/CAN.c
new file mode 100644
index 000000000..76599a9a7
--- /dev/null
+++ b/ports/atmel-samd/common-hal/canio/CAN.c
@@ -0,0 +1,421 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jeff Epler for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <string.h>
+
+#include "py/runtime.h"
+#include "py/mperrno.h"
+
+#include "peripheral_clk_config.h"
+
+#include "common-hal/canio/CAN.h"
+#include "shared-bindings/microcontroller/Pin.h"
+#include "shared-bindings/util.h"
+#include "supervisor/port.h"
+
+#include "component/can.h"
+
+#include "genhdr/candata.h"
+
+STATIC Can * const can_insts[] = CAN_INSTS;
+
+STATIC canio_can_obj_t *can_objs[MP_ARRAY_SIZE(can_insts)];
+
+// This must be placed in the first 64kB of RAM
+STATIC COMPILER_SECTION(".canram") canio_can_state_t can_state[MP_ARRAY_SIZE(can_insts)];
+
+void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent)
+{
+    mcu_pin_function_t *tx_function = mcu_find_pin_function(can_tx, tx, -1, MP_QSTR_tx);
+    int instance = tx_function->instance;
+
+    mcu_pin_function_t *rx_function = mcu_find_pin_function(can_rx, rx, instance, MP_QSTR_rx);
+
+    const uint32_t can_frequency = CONF_CAN0_FREQUENCY;
+
+#define DIV_ROUND(a, b) (((a) + (b)/2) / (b))
+#define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
+
+    uint32_t clocks_per_bit = DIV_ROUND(can_frequency, baudrate);
+    uint32_t clocks_to_sample = DIV_ROUND(clocks_per_bit * 7, 8);
+    uint32_t clocks_after_sample = clocks_per_bit - clocks_to_sample;
+    uint32_t divisor = MAX(DIV_ROUND_UP(clocks_to_sample, 256), DIV_ROUND_UP(clocks_after_sample, 128));
+    if (divisor > 32) {
+        mp_raise_OSError(MP_EINVAL); // baudrate cannot be attained (16kHz or something is lower bound, should never happen)
+    }
+
+    gpio_set_pin_direction(tx_function->pin, GPIO_DIRECTION_OUT);
+    gpio_set_pin_function(tx_function->pin, tx_function->function);
+    common_hal_never_reset_pin(tx_function->obj);
+
+    gpio_set_pin_direction(rx_function->pin, GPIO_DIRECTION_IN);
+    gpio_set_pin_function(rx_function->pin, rx_function->function);
+    common_hal_never_reset_pin(rx_function->obj);
+
+    self->tx_pin_number = tx ? common_hal_mcu_pin_number(tx) : COMMON_HAL_MCU_NO_PIN;
+    self->rx_pin_number = rx ? common_hal_mcu_pin_number(rx) : COMMON_HAL_MCU_NO_PIN;
+    self->hw = can_insts[instance];
+    self->state = &can_state[instance];
+
+    self->loopback = loopback;
+    self->silent = silent;
+
+    // Allow configuration change
+    hri_can_set_CCCR_INIT_bit(self->hw);
+    while (hri_can_get_CCCR_INIT_bit(self->hw) == 0) {
+    }
+    hri_can_set_CCCR_CCE_bit(self->hw);
+
+    if (instance == 0) {
+        hri_mclk_set_AHBMASK_CAN0_bit(MCLK);
+        hri_gclk_write_PCHCTRL_reg(GCLK, CAN0_GCLK_ID, CONF_GCLK_CAN0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+        NVIC_DisableIRQ(CAN0_IRQn);
+        NVIC_ClearPendingIRQ(CAN0_IRQn);
+        NVIC_EnableIRQ(CAN0_IRQn);
+        hri_can_write_ILE_reg(self->hw, CAN_ILE_EINT0);
+#ifdef CAN1_GCLK_ID
+    } else if (instance == 1) {
+        hri_mclk_set_AHBMASK_CAN1_bit(MCLK);
+        hri_gclk_write_PCHCTRL_reg(GCLK, CAN1_GCLK_ID, CONF_GCLK_CAN1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+        NVIC_DisableIRQ(CAN1_IRQn);
+        NVIC_ClearPendingIRQ(CAN1_IRQn);
+        NVIC_EnableIRQ(CAN1_IRQn);
+        hri_can_write_ILE_reg(self->hw, CAN_ILE_EINT0);
+#endif
+    }
+
+    self->hw->CCCR.bit.FDOE = 0; // neither FD nor Bit Rate Switch enabled
+    self->hw->CCCR.bit.BRSE = 0;
+
+    hri_can_write_MRCFG_reg(self->hw, CAN_MRCFG_QOS(CAN_MRCFG_QOS_DISABLE_Val)); // QoS disabled (no sensitive operation)
+
+    // A "nominal bit" is a header bit.  With dual rate CAN FD, this is a slower rate
+    {
+        CAN_NBTP_Type btp = {
+            // 0 means "1 tq", but 2 is subtracted from NTSEG1 for the
+            // fixed 1 "SYNC" tq
+            .bit.NTSEG1 = DIV_ROUND(clocks_to_sample, divisor) - 2,
+            .bit.NTSEG2 = DIV_ROUND(clocks_after_sample, divisor) - 1,
+            .bit.NBRP = divisor - 1,
+            .bit.NSJW = DIV_ROUND(clocks_after_sample, divisor * 4),
+        };
+        hri_can_write_NBTP_reg(self->hw, btp.reg);
+    }
+
+    // A "data bit" is a data bit :) with dula rate CAN FD, this is a higher
+    // rate.  However, CAN FD is not implemented in CircuitPython, and this is
+    // the same rate as the "nominal rate".
+    {
+        CAN_DBTP_Type btp = {
+            .bit.DTSEG1 = DIV_ROUND(clocks_to_sample, divisor) - 1,
+            .bit.DTSEG2 = DIV_ROUND(clocks_after_sample, divisor) - 1,
+            .bit.DBRP = divisor - 1,
+            .bit.DSJW = DIV_ROUND(clocks_after_sample, divisor * 4),
+        };
+        hri_can_write_DBTP_reg(self->hw, btp.reg);
+    }
+
+    {
+        CAN_RXF0C_Type rxf = {
+            .bit.F0SA = (uint32_t)self->state->rx0_fifo,
+            .bit.F0S = COMMON_HAL_CANIO_RX_FIFO_SIZE,
+        };
+        hri_can_write_RXF0C_reg(self->hw, rxf.reg);
+    }
+
+    {
+        CAN_RXF1C_Type rxf = {
+            .bit.F1SA = (uint32_t)self->state->rx1_fifo,
+            .bit.F1S = COMMON_HAL_CANIO_RX_FIFO_SIZE,
+        };
+        hri_can_write_RXF1C_reg(self->hw, rxf.reg);
+    }
+
+    // All RX data has an 8 byte payload (max)
+    {
+        CAN_RXESC_Type esc = {
+            .bit.F0DS = CAN_RXESC_F0DS_DATA8_Val,
+            .bit.F1DS = CAN_RXESC_F1DS_DATA8_Val,
+            .bit.RBDS = CAN_RXESC_RBDS_DATA8_Val,
+        };
+        hri_can_write_RXESC_reg(self->hw, esc.reg);
+    }
+
+    // All TX data has an 8 byte payload (max)
+    {
+        CAN_TXESC_Type esc = {
+            .bit.TBDS = CAN_TXESC_TBDS_DATA8_Val,
+        };
+        hri_can_write_TXESC_reg(self->hw, esc.reg);
+    }
+
+    {
+        CAN_TXBC_Type bc = {
+            .bit.TBSA = (uint32_t)self->state->tx_buffer,
+            .bit.NDTB = COMMON_HAL_CANIO_TX_FIFO_SIZE,
+            .bit.TFQM = 0, // Messages are transmitted in the order submitted
+        };
+        hri_can_write_TXBC_reg(self->hw, bc.reg);
+    }
+
+    {
+        CAN_TXEFC_Type efc = {
+            .bit.EFS = 0,
+        };
+        hri_can_write_TXEFC_reg(self->hw, efc.reg);
+    }
+
+    {
+        CAN_GFC_Type gfc = {
+            .bit.RRFE = 0,
+            .bit.ANFS = CAN_GFC_ANFS_REJECT_Val,
+            .bit.ANFE = CAN_GFC_ANFE_REJECT_Val,
+        };
+        hri_can_write_GFC_reg(self->hw, gfc.reg);
+    }
+
+    {
+        CAN_SIDFC_Type dfc = {
+            .bit.LSS = COMMON_HAL_CANIO_RX_FILTER_SIZE,
+            .bit.FLSSA = (uint32_t)self->state->standard_rx_filter
+        };
+        hri_can_write_SIDFC_reg(self->hw, dfc.reg);
+    }
+
+    {
+        CAN_XIDFC_Type dfc = {
+            .bit.LSE = COMMON_HAL_CANIO_RX_FILTER_SIZE,
+            .bit.FLESA = (uint32_t)self->state->extended_rx_filter
+        };
+        hri_can_write_XIDFC_reg(self->hw, dfc.reg);
+    }
+
+    {
+        CAN_IE_Type ie = {
+            .bit.EWE = 1,
+            .bit.EPE = 1,
+            .bit.BOE = 1,
+        };
+        hri_can_write_IE_reg(self->hw, ie.reg);
+    }
+
+    hri_can_write_XIDAM_reg(self->hw, CAN_XIDAM_RESETVALUE);
+
+// silent: The CAN is set in Bus Monitoring Mode by programming CCCR.MON to '1'. (tx pin unused)
+// external loopback: The CAN can be set in External Loop Back Mode by programming TEST.LBCK and CCCR.MON to '1'. (rx pin unused)
+// internal loopback (silent loopback): Internal Loop Back Mode is entered by programming bits TEST.LBCK and CCCR.MON to '1'. (tx, rx unused)
+    self->hw->CCCR.bit.MON = silent;
+    self->hw->CCCR.bit.TEST = loopback;
+    self->hw->TEST.bit.LBCK = loopback;
+
+    if (instance == 0) {
+        NVIC_DisableIRQ(CAN0_IRQn);
+        NVIC_ClearPendingIRQ(CAN0_IRQn);
+        NVIC_EnableIRQ(CAN0_IRQn);
+#ifdef CAN1_GCLK_ID
+    } else if (instance == 1) {
+        NVIC_DisableIRQ(CAN1_IRQn);
+        NVIC_ClearPendingIRQ(CAN1_IRQn);
+        NVIC_EnableIRQ(CAN1_IRQn);
+#endif
+    }
+
+    hri_can_write_ILE_reg(self->hw, CAN_ILE_EINT0);
+    // Prevent configuration change
+    hri_can_clear_CCCR_CCE_bit(self->hw);
+    hri_can_clear_CCCR_INIT_bit(self->hw);
+    while (hri_can_get_CCCR_INIT_bit(self->hw)) {
+    }
+
+    can_objs[instance] = self;
+}
+
+bool common_hal_canio_can_loopback_get(canio_can_obj_t *self)
+{
+    return self->loopback;
+}
+
+int common_hal_canio_can_baudrate_get(canio_can_obj_t *self)
+{
+    return self->baudrate;
+}
+
+int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self)
+{
+    return self->hw->ECR.bit.TEC;
+}
+
+int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self)
+{
+    return self->hw->ECR.bit.REC;
+}
+
+canio_bus_state_t common_hal_canio_can_state_get(canio_can_obj_t *self) {
+    CAN_PSR_Type psr = self->hw->PSR;
+    if (psr.bit.BO) {
+        return BUS_STATE_OFF;
+    }
+    if (psr.bit.EP) {
+        return BUS_STATE_ERROR_PASSIVE;
+    }
+    if (psr.bit.EW) {
+        return BUS_STATE_ERROR_WARNING;
+    }
+    return BUS_STATE_ERROR_ACTIVE;
+}
+
+void common_hal_canio_can_restart(canio_can_obj_t *self) {
+    if (!self->hw->PSR.bit.BO) {
+        return;
+    }
+
+    hri_can_clear_CCCR_INIT_bit(self->hw);
+    while (hri_can_get_CCCR_INIT_bit(self->hw)) {
+    }
+}
+
+bool common_hal_canio_can_auto_restart_get(canio_can_obj_t *self) {
+    return self->auto_restart;
+}
+
+void common_hal_canio_can_auto_restart_set(canio_can_obj_t *self, bool value) {
+    self->auto_restart = value;
+}
+
+static void maybe_auto_restart(canio_can_obj_t *self) {
+    if (self->auto_restart) {
+        common_hal_canio_can_restart(self);
+    }
+}
+
+void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in)
+{
+    maybe_auto_restart(self);
+
+    canio_message_obj_t *message = message_in;;
+    // We have just one dedicated TX buffer, use it!
+    canio_can_tx_buffer_t *ent = &self->state->tx_buffer[0];
+
+    bool rtr = message->base.type == &canio_remote_transmission_request_type;
+    ent->txb0.bit.ESI = false;
+    ent->txb0.bit.XTD = message->extended;
+    ent->txb0.bit.RTR = rtr;
+    if (message->extended) {
+        ent->txb0.bit.ID = message->id;
+    } else {
+        ent->txb0.bit.ID = message->id << 18; // short addresses are left-justified
+    }
+
+    ent->txb1.bit.MM = 0; // "message marker"
+    ent->txb1.bit.EFC = 0; // don't store fifo events to event queue
+    ent->txb1.bit.FDF = 0; // Classic CAN format
+    ent->txb1.bit.BRS = 0; // No bit rate switching
+    ent->txb1.bit.DLC = message->size;
+
+    if (!rtr) {
+        memcpy(ent->data, message->data, message->size);
+    }
+
+    // TX buffer add request
+    self->hw->TXBAR.reg = 1;
+
+    // wait 8ms (hard coded for now) for TX to occur
+    uint64_t deadline = port_get_raw_ticks(NULL) + 8;
+    while (port_get_raw_ticks(NULL) < deadline && !(self->hw->TXBTO.reg & 1)) {
+        RUN_BACKGROUND_TASKS;
+    }
+}
+
+bool common_hal_canio_can_silent_get(canio_can_obj_t *self) {
+    return self->silent;
+}
+
+bool common_hal_canio_can_deinited(canio_can_obj_t *self) {
+    return !self->hw;
+}
+
+void common_hal_canio_can_check_for_deinit(canio_can_obj_t *self) {
+    if (common_hal_canio_can_deinited(self)) {
+        raise_deinited_error();
+    }
+}
+
+void common_hal_canio_can_deinit(canio_can_obj_t *self)
+{
+    if (self->hw) {
+        hri_can_set_CCCR_INIT_bit(self->hw);
+        self->hw = 0;
+    }
+    if (self->rx_pin_number != COMMON_HAL_MCU_NO_PIN) {
+        reset_pin_number(self->rx_pin_number);
+        self->rx_pin_number = COMMON_HAL_MCU_NO_PIN;
+    }
+    if (self->tx_pin_number != COMMON_HAL_MCU_NO_PIN) {
+        reset_pin_number(self->tx_pin_number);
+        self->tx_pin_number = COMMON_HAL_MCU_NO_PIN;
+    }
+}
+
+void common_hal_canio_reset(void) {
+    memset(can_state, 0, sizeof(can_state));
+
+    for (size_t i=0; i<MP_ARRAY_SIZE(can_insts); i++) {
+        hri_can_set_CCCR_INIT_bit(can_insts[i]);
+    }
+
+    for (size_t i=0; i<MP_ARRAY_SIZE(can_objs); i++) {
+        if (can_objs[i]) {
+            common_hal_canio_can_deinit(can_objs[i]);
+            can_objs[i] = NULL;
+        }
+    }
+}
+
+
+STATIC void can_handler(int i) {
+    canio_can_obj_t *self = can_objs[i];
+    (void) self;
+
+    Can *hw = can_insts[i];
+    uint32_t ir = hri_can_read_IR_reg(hw);
+
+    /* Acknowledge interrupt */
+    hri_can_write_IR_reg(hw, ir);
+}
+
+__attribute__((used))
+void CAN0_Handler(void) {
+    can_handler(0);
+}
+
+#ifdef CAN1_GCLK_ID
+__attribute__((used))
+void CAN1_Handler(void) {
+    can_handler(1);
+}
+#endif
diff --git a/ports/atmel-samd/common-hal/canio/CAN.h b/ports/atmel-samd/common-hal/canio/CAN.h
new file mode 100644
index 000000000..15ac0f4b7
--- /dev/null
+++ b/ports/atmel-samd/common-hal/canio/CAN.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jeff Epler for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+
+#include "py/obj.h"
+#include "shared-bindings/canio/__init__.h"
+#include "shared-bindings/canio/CAN.h"
+#include "component/can.h"
+#include "common-hal/microcontroller/Pin.h"
+#include "common-hal/canio/__init__.h"
+#include "shared-module/canio/Message.h"
+
+#define COMMON_HAL_CAN_RX_FIFO_LEN (2)
+#define COMMON_HAL_CAN_TX_FIFO_LEN (2)
+
+typedef struct canio_can_obj {
+    mp_obj_base_t base;
+    Can *hw;
+    canio_can_state_t *state;
+    int baudrate;
+    uint8_t rx_pin_number:8;
+    uint8_t tx_pin_number:8;
+    bool loopback:1;
+    bool silent:1;
+    bool auto_restart:1;
+    bool fifo0_in_use:1;
+    bool fifo1_in_use:1;
+} canio_can_obj_t;
diff --git a/ports/atmel-samd/common-hal/canio/Listener.c b/ports/atmel-samd/common-hal/canio/Listener.c
new file mode 100644
index 000000000..b27c8cd1b
--- /dev/null
+++ b/ports/atmel-samd/common-hal/canio/Listener.c
@@ -0,0 +1,394 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jeff Epler for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <math.h>
+#include <string.h>
+
+#include "py/obj.h"
+#include "py/runtime.h"
+
+#include "common-hal/canio/__init__.h"
+#include "common-hal/canio/Listener.h"
+#include "shared-bindings/canio/Listener.h"
+#include "shared-bindings/util.h"
+#include "supervisor/shared/tick.h"
+#include "component/can.h"
+
+STATIC void allow_config_change(canio_can_obj_t *can) {
+    can->hw->CCCR.bit.INIT = 1;
+    while (!can->hw->CCCR.bit.INIT) {
+    }
+    can->hw->CCCR.bit.CCE = 1;
+}
+
+STATIC void prevent_config_change(canio_can_obj_t *can) {
+    can->hw->CCCR.bit.CCE = 0;
+    can->hw->CCCR.bit.INIT = 0;
+    while (can->hw->CCCR.bit.INIT) {
+    }
+}
+
+__attribute__((unused))
+STATIC void static_assertions(void) {
+    MP_STATIC_ASSERT(CAN_GFC_ANFE_RXF0_Val + 1 == CAN_GFC_ANFE_RXF1_Val);
+    MP_STATIC_ASSERT(CAN_GFC_ANFS_RXF0_Val + 1 == CAN_GFC_ANFS_RXF1_Val);
+    MP_STATIC_ASSERT(CAN_SIDFE_0_SFEC_STF0M_Val + 1 == CAN_SIDFE_0_SFEC_STF1M_Val);
+    MP_STATIC_ASSERT(CAN_XIDFE_0_EFEC_STF0M_Val + 1 == CAN_XIDFE_0_EFEC_STF1M_Val);
+}
+
+STATIC bool single_id_filter(canio_match_obj_t *match) {
+    return match->mask == 0 || match->mask == match->id;
+}
+
+STATIC bool standard_filter_in_use(CanMramSidfe *filter) {
+    return filter->SIDFE_0.bit.SFEC != CAN_SIDFE_0_SFEC_DISABLE_Val;
+}
+
+STATIC bool extended_filter_in_use(CanMramXidfe *filter) {
+    return filter->XIDFE_0.bit.EFEC != CAN_XIDFE_0_EFEC_DISABLE_Val;
+}
+
+STATIC size_t num_filters_needed(size_t nmatch, canio_match_obj_t **matches, bool extended) {
+    size_t num_half_filters_needed = 1;
+    for(size_t i=0; i<nmatch; i++) {
+        if (extended != matches[i]->extended) {
+            continue;
+        }
+        if (single_id_filter(matches[i])) {
+            num_half_filters_needed += 1;
+        } else {
+            num_half_filters_needed += 2;
+        }
+    }
+    return num_half_filters_needed / 2;
+}
+
+STATIC size_t num_filters_available(canio_can_obj_t *can, bool extended) {
+    size_t available = 0;
+    if (extended) {
+        for(size_t i = 0; i < MP_ARRAY_SIZE(can->state->extended_rx_filter); i++) {
+            if (!extended_filter_in_use(&can->state->extended_rx_filter[i])) {
+                available++;
+            }
+        }
+    } else {
+        for(size_t i = 0; i < MP_ARRAY_SIZE(can->state->standard_rx_filter); i++) {
+            if (!standard_filter_in_use(&can->state->standard_rx_filter[i])) {
+                available++;
+            }
+        }
+    }
+    return available;
+}
+
+STATIC void clear_filters(canio_listener_obj_t *self) {
+    canio_can_obj_t *can = self->can;
+    int fifo = self->fifo_idx;
+
+    // If it was a global accept, clear it
+    allow_config_change(can);
+    if (can->hw->GFC.bit.ANFS == CAN_GFC_ANFS_RXF0 + fifo) {
+        can->hw->GFC.bit.ANFS = CAN_GFC_ANFS_REJECT_Val;
+    }
+    if (can->hw->GFC.bit.ANFE == CAN_GFC_ANFE_RXF0 + fifo) {
+        can->hw->GFC.bit.ANFE = CAN_GFC_ANFE_REJECT_Val;
+    }
+    prevent_config_change(can);
+
+    // For each filter entry, if it pointed at this FIFO set it to DISABLE
+    for(size_t i = 0; i < MP_ARRAY_SIZE(can->state->extended_rx_filter); i++) {
+        int val = CAN_XIDFE_0_EFEC_STF0M_Val + fifo;
+        if (can->state->extended_rx_filter[i].XIDFE_0.bit.EFEC == val) {
+            can->state->extended_rx_filter[i].XIDFE_0.bit.EFEC = CAN_XIDFE_0_EFEC_DISABLE_Val;
+        }
+    }
+    for(size_t i = 0; i < MP_ARRAY_SIZE(can->state->standard_rx_filter); i++) {
+        int val = CAN_SIDFE_0_SFEC_STF1M_Val + fifo;
+        if (can->state->standard_rx_filter[i].SIDFE_0.bit.SFEC == val) {
+            can->state->standard_rx_filter[i].SIDFE_0.bit.SFEC = CAN_SIDFE_0_SFEC_DISABLE_Val;
+        }
+    }
+}
+
+STATIC CanMramXidfe *next_extended_filter(canio_listener_obj_t *self, CanMramXidfe *start) {
+    CanMramXidfe *end = &self->can->state->extended_rx_filter[MP_ARRAY_SIZE(self->can->state->extended_rx_filter)];
+    if (start == NULL) {
+        start = self->can->state->extended_rx_filter;
+    } else {
+        start = start + 1;
+    }
+    while (extended_filter_in_use(start)) {
+        if (start == end) {
+            return NULL;
+        }
+        start = start + 1;
+    }
+    return start;
+}
+
+STATIC CanMramSidfe *next_standard_filter(canio_listener_obj_t *self, CanMramSidfe *start) {
+    CanMramSidfe *end = &self->can->state->standard_rx_filter[MP_ARRAY_SIZE(self->can->state->standard_rx_filter)];
+    if (start == NULL) {
+        start = self->can->state->standard_rx_filter;
+    } else {
+        start = start + 1;
+    }
+    while (standard_filter_in_use(start)) {
+        if (start == end) {
+            return NULL;
+        }
+        start = start + 1;
+    }
+    return start;
+}
+
+STATIC void install_standard_filter(CanMramSidfe *standard, int id1, int id2, int sfec, int sft) {
+    assert(standard);
+    CAN_SIDFE_0_Type val = {
+        .bit.SFID1 = id1,
+        .bit.SFID2 = id2,
+        .bit.SFEC = sfec,
+        .bit.SFT = sft,
+    };
+    standard->SIDFE_0 = val;
+}
+
+STATIC void install_extended_filter(CanMramXidfe *extended, int id1, int id2, int efec, int eft) {
+    assert(extended);
+    CAN_XIDFE_0_Type val0 = {
+        .bit.EFID1 = id1,
+        .bit.EFEC = efec,
+    };
+    CAN_XIDFE_1_Type val1 = {
+        .bit.EFID2 = id2,
+        .bit.EFT = eft,
+    };
+    // Set entry 0 second, because it has the enable bits (XIDFE_0_EFEC)
+    extended->XIDFE_1 = val1;
+    extended->XIDFE_0 = val0;
+}
+
+
+#define NO_ID (-1)
+void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **matches) {
+    int fifo = self->fifo_idx;
+
+    if (!nmatch) {
+        allow_config_change(self->can);
+        self->can->hw->GFC.bit.ANFS = CAN_GFC_ANFS_RXF0_Val + fifo;
+        self->can->hw->GFC.bit.ANFE = CAN_GFC_ANFE_RXF0_Val + fifo;
+        self->can->hw->CCCR.bit.CCE = 0;
+        prevent_config_change(self->can);
+        return;
+    }
+
+    CanMramSidfe *standard = next_standard_filter(self, NULL);
+    CanMramXidfe *extended = next_extended_filter(self, NULL);
+
+    int first_id = NO_ID;
+
+    // step 1: single id standard matches
+    // we have to gather up pairs and stuff them in a single filter entry
+    for(size_t i = 0; i<nmatch; i++) {
+        canio_match_obj_t *match = matches[i];
+        if (match->extended) {
+            continue;
+        }
+        if (!single_id_filter(match)) {
+            continue;
+        }
+        if (first_id != NO_ID) {
+            install_standard_filter(standard, first_id, match->id, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_DUAL_Val);
+            first_id = NO_ID;
+            standard = next_standard_filter(self, standard);
+        } else {
+            first_id = match->id;
+        }
+    }
+    // step 1.5. odd single id standard match
+    if (first_id != NO_ID) {
+            install_standard_filter(standard, first_id, first_id, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_DUAL_Val);
+            standard = next_standard_filter(self, standard);
+            first_id = NO_ID;
+    }
+
+    // step 2: standard mask filter
+    for(size_t i = 0; i<nmatch; i++) {
+        canio_match_obj_t *match = matches[i];
+        if (match->extended) {
+            continue;
+        }
+        if (single_id_filter(match)) {
+            continue;
+        }
+        install_standard_filter(standard, match->id, match->mask, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_CLASSIC_Val);
+        standard = next_standard_filter(self, standard);
+    }
+
+    // step 3: single id extended matches
+    // we have to gather up pairs and stuff them in a single filter entry
+    for(size_t i = 0; i<nmatch; i++) {
+        canio_match_obj_t *match = matches[i];
+        if (!match->extended) {
+            continue;
+        }
+        if (!single_id_filter(match)) {
+            continue;
+        }
+        if (first_id != NO_ID) {
+            install_extended_filter(extended, first_id, match->id, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_DUAL_Val);
+            first_id = NO_ID;
+            extended = next_extended_filter(self, extended);
+        } else {
+            first_id = match->id;
+        }
+    }
+    // step 3.5. odd single id standard match
+    if (first_id != NO_ID) {
+            install_extended_filter(extended, first_id, first_id, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_DUAL_Val);
+            extended = next_extended_filter(self, extended);
+            first_id = NO_ID;
+    }
+
+    // step 4: extended mask filters
+    for(size_t i = 0; i<nmatch; i++) {
+        canio_match_obj_t *match = matches[i];
+        if (!match->extended) {
+            continue;
+        }
+        if (single_id_filter(match)) {
+            continue;
+        }
+        install_extended_filter(extended, match->id, match->mask, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_CLASSIC_Val);
+        extended = next_extended_filter(self, extended);
+    }
+
+    // phew, easy(!)
+}
+
+
+void common_hal_canio_listener_construct(canio_listener_obj_t *self, canio_can_obj_t *can, size_t nmatch, canio_match_obj_t **matches, float timeout) {
+    if (!can->fifo0_in_use) {
+        self->fifo_idx = 0;
+        self->fifo = can->state->rx0_fifo;
+        self->hw = (canio_rxfifo_reg_t*)&can->hw->RXF0C;
+        can->hw->IR.reg = CAN_IR_RF0N | CAN_IR_RF0W | CAN_IR_RF0F | CAN_IR_RF0L;
+        can->fifo0_in_use = true;
+    } else if (!can->fifo1_in_use) {
+        self->fifo_idx = 1;
+        self->fifo = can->state->rx1_fifo;
+        self->hw = (canio_rxfifo_reg_t*)&can->hw->RXF1C;
+        can->fifo1_in_use = true;
+        can->hw->IR.reg = CAN_IR_RF1N | CAN_IR_RF1W | CAN_IR_RF1F | CAN_IR_RF1L;
+    } else {
+        mp_raise_ValueError(translate("All RX FIFOs in use"));
+    }
+
+    if (!nmatch) {
+        if (can->hw->GFC.bit.ANFS == CAN_GFC_ANFS_RXF1_Val - self->fifo_idx) {
+            mp_raise_ValueError(translate("Already have all-matches listener"));
+        }
+        if (can->hw->GFC.bit.ANFE == CAN_GFC_ANFE_RXF1_Val - self->fifo_idx) {
+            mp_raise_ValueError(translate("Already have all-matches listener"));
+        }
+    }
+
+    if (num_filters_needed(nmatch, matches, false) > num_filters_available(can, false)) {
+        mp_raise_ValueError(translate("Filters too complex"));
+    }
+
+    if (num_filters_needed(nmatch, matches, true) > num_filters_available(can, true)) {
+        mp_raise_ValueError(translate("Filters too complex"));
+    }
+
+    // Nothing can fail now so it's safe to assign self->can
+    self->can = can;
+    set_filters(self, nmatch, matches);
+    common_hal_canio_listener_set_timeout(self, timeout);
+}
+
+void common_hal_canio_listener_set_timeout(canio_listener_obj_t *self, float timeout) {
+    self->timeout_ms = (int)MICROPY_FLOAT_C_FUN(ceil)(timeout * 1000);
+}
+
+float common_hal_canio_listener_get_timeout(canio_listener_obj_t *self) {
+    return self->timeout_ms / 1000.0f;
+}
+
+void common_hal_canio_listener_check_for_deinit(canio_listener_obj_t *self) {
+    if (!self->can) {
+        raise_deinited_error();
+    }
+    common_hal_canio_can_check_for_deinit(self->can);
+}
+
+int common_hal_canio_listener_in_waiting(canio_listener_obj_t *self) {
+    return self->hw->RXFS.bit.F0FL;
+}
+
+mp_obj_t common_hal_canio_listener_receive(canio_listener_obj_t *self) {
+    if (!common_hal_canio_listener_in_waiting(self)) {
+        uint64_t deadline = supervisor_ticks_ms64() + self->timeout_ms;
+        do {
+            if (supervisor_ticks_ms64() > deadline) {
+                return NULL;
+            }
+        } while (!common_hal_canio_listener_in_waiting(self));
+    }
+    int index = self->hw->RXFS.bit.F0GI;
+    canio_can_rx_fifo_t *hw_message = &self->fifo[index];
+    bool rtr = hw_message->rxf0.bit.RTR;
+    canio_message_obj_t *message = m_new_obj(canio_message_obj_t);
+    message->base.type = rtr ? &canio_remote_transmission_request_type : &canio_message_type;
+    message->extended = hw_message->rxf0.bit.XTD;
+    if (message->extended) {
+        message->id = hw_message->rxf0.bit.ID;
+    } else {
+        message->id = hw_message->rxf0.bit.ID >> 18; // short ids are left-justified
+    }
+    message->size = hw_message->rxf1.bit.DLC;
+    if (!rtr) {
+        memcpy(message->data, hw_message->data, message->size);
+    }
+    self->hw->RXFA.bit.F0AI = index;
+    return message;
+}
+
+void common_hal_canio_listener_deinit(canio_listener_obj_t *self) {
+    if (self->can) {
+        clear_filters(self);
+        if (self->fifo_idx == 0) {
+            self->can->fifo0_in_use = false;
+        }
+        if (self->fifo_idx == 1) {
+            self->can->fifo1_in_use = false;
+        }
+    }
+    self->fifo_idx = -1;
+    self->fifo = NULL;
+    self->can = NULL;
+    self->hw = NULL;
+}
diff --git a/ports/atmel-samd/common-hal/canio/Listener.h b/ports/atmel-samd/common-hal/canio/Listener.h
new file mode 100644
index 000000000..237dca870
--- /dev/null
+++ b/ports/atmel-samd/common-hal/canio/Listener.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jeff Epler for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+
+#include "common-hal/canio/CAN.h"
+#include "shared-module/canio/Match.h"
+
+typedef struct {
+  __IO CAN_RXF0C_Type            RXFC;       /**< \brief (R/W 32) Rx FIFO n Configuration */
+  __I  CAN_RXF0S_Type            RXFS;       /**< \brief (R/  32) Rx FIFO n Status */
+  __IO CAN_RXF0A_Type            RXFA;       /**< \brief (R/W 32) Rx FIFO n Acknowledge */
+} canio_rxfifo_reg_t;
+
+typedef struct canio_listener_obj {
+    mp_obj_base_t base;
+    canio_can_obj_t *can;
+    canio_can_rx_fifo_t *fifo;
+    canio_rxfifo_reg_t *hw;
+    uint32_t timeout_ms;
+    uint8_t fifo_idx;
+} canio_listener_obj_t;
diff --git a/ports/atmel-samd/common-hal/canio/__init__.c b/ports/atmel-samd/common-hal/canio/__init__.c
new file mode 100644
index 000000000..7932bfc2d
--- /dev/null
+++ b/ports/atmel-samd/common-hal/canio/__init__.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jeff Epler for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
diff --git a/ports/atmel-samd/common-hal/canio/__init__.h b/ports/atmel-samd/common-hal/canio/__init__.h
new file mode 100644
index 000000000..32adc5bf9
--- /dev/null
+++ b/ports/atmel-samd/common-hal/canio/__init__.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jeff Epler for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#pragma once
+
+#include "hal/utils/include/utils.h"
+#include "component/can.h"
+
+#define COMMON_HAL_CANIO_MAX_MESSAGE_LENGTH (8)
+#define COMMON_HAL_CANIO_RX_FIFO_SIZE (3)
+#define COMMON_HAL_CANIO_RX_FILTER_SIZE (4)
+#define COMMON_HAL_CANIO_TX_FIFO_SIZE (1)
+
+// This appears to be a typo (transposition error) in the ASF4 headers
+// It's called the "Extended ID Filter Entry"
+typedef CanMramXifde CanMramXidfe;
+
+typedef struct canio_listener canio_listener_t;
+typedef struct canio_can canio_can_t;
+
+typedef struct {
+    CAN_TXBE_0_Type txb0;
+    CAN_TXBE_1_Type txb1;
+    COMPILER_ALIGNED(4)
+    uint8_t data[COMMON_HAL_CANIO_MAX_MESSAGE_LENGTH];
+} canio_can_tx_buffer_t;
+
+typedef struct {
+    CAN_RXF0E_0_Type rxf0;
+    CAN_RXF0E_1_Type rxf1;
+    COMPILER_ALIGNED(4)
+    uint8_t data[COMMON_HAL_CANIO_MAX_MESSAGE_LENGTH];
+} canio_can_rx_fifo_t;
+
+typedef uint32_t canio_can_filter_t;
+
+typedef struct {
+    canio_can_tx_buffer_t tx_buffer[COMMON_HAL_CANIO_TX_FIFO_SIZE];
+    canio_can_rx_fifo_t rx0_fifo[COMMON_HAL_CANIO_RX_FIFO_SIZE];
+    canio_can_rx_fifo_t rx1_fifo[COMMON_HAL_CANIO_RX_FIFO_SIZE];
+    CanMramSidfe standard_rx_filter[COMMON_HAL_CANIO_RX_FILTER_SIZE];
+    CanMramXifde extended_rx_filter[COMMON_HAL_CANIO_RX_FILTER_SIZE];
+} canio_can_state_t;
diff --git a/ports/atmel-samd/common-hal/microcontroller/Pin.c b/ports/atmel-samd/common-hal/microcontroller/Pin.c
index ef1d8fffa..7dd87a3b2 100644
--- a/ports/atmel-samd/common-hal/microcontroller/Pin.c
+++ b/ports/atmel-samd/common-hal/microcontroller/Pin.c
@@ -24,6 +24,8 @@
  * THE SOFTWARE.
  */
 
+#include "py/runtime.h"
+
 #include "shared-bindings/microcontroller/Pin.h"
 
 #include "atmel_start_pins.h"
@@ -221,9 +223,11 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t* pin) {
     #ifdef MICROPY_HW_NEOPIXEL
     if (pin == MICROPY_HW_NEOPIXEL) {
         // Special case for Metro M0 where the NeoPixel is also SWCLK
+#ifndef IGNORE_PIN_PA30
         if (MICROPY_HW_NEOPIXEL == &pin_PA30 && DSU->STATUSB.bit.DBGPRES == 1) {
             return false;
         }
+#endif
         return !neopixel_in_use;
     }
     #endif
@@ -256,3 +260,19 @@ void common_hal_mcu_pin_claim(const mcu_pin_obj_t* pin) {
 void common_hal_mcu_pin_reset_number(uint8_t pin_no) {
     reset_pin_number(pin_no);
 }
+
+mcu_pin_function_t *mcu_find_pin_function(mcu_pin_function_t *table, const mcu_pin_obj_t *pin, int instance, uint16_t name) {
+    if (!pin) {
+        return NULL;
+    }
+
+    for(; table->obj; table++) {
+        if (instance != -1 && instance != table->instance) {
+            continue;
+        }
+        if (pin == table->obj) {
+            return table;
+        }
+    }
+    mp_raise_ValueError_varg(translate("%q pin invalid"), name);
+}
diff --git a/ports/atmel-samd/common-hal/microcontroller/Pin.h b/ports/atmel-samd/common-hal/microcontroller/Pin.h
index 14887207a..59302713a 100644
--- a/ports/atmel-samd/common-hal/microcontroller/Pin.h
+++ b/ports/atmel-samd/common-hal/microcontroller/Pin.h
@@ -47,4 +47,13 @@ void never_reset_pin_number(uint8_t pin_number);
 void claim_pin(const mcu_pin_obj_t* pin);
 bool pin_number_is_free(uint8_t pin_number);
 
+typedef struct {
+    const mcu_pin_obj_t *obj;
+    uint8_t instance;
+    uint8_t pin;
+    uint16_t function;
+} mcu_pin_function_t;
+
+mcu_pin_function_t *mcu_find_pin_function(mcu_pin_function_t *table, const mcu_pin_obj_t *pin, int instance, uint16_t name);
+
 #endif // MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_MICROCONTROLLER_PIN_H
diff --git a/ports/atmel-samd/common-hal/microcontroller/Processor.c b/ports/atmel-samd/common-hal/microcontroller/Processor.c
index 199f19354..ba8daf3fb 100644
--- a/ports/atmel-samd/common-hal/microcontroller/Processor.c
+++ b/ports/atmel-samd/common-hal/microcontroller/Processor.c
@@ -61,6 +61,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <math.h>
+
 #include "py/mphal.h"
 #include "common-hal/microcontroller/Processor.h"
 
@@ -276,6 +278,9 @@ float common_hal_mcu_processor_get_temperature(void) {
 }
 
 float common_hal_mcu_processor_get_voltage(void) {
+#if MICROCONTROLLER_VOLTAGE_DISABLE
+    return NAN;
+#else
     struct adc_sync_descriptor adc;
 
     static Adc* adc_insts[] = ADC_INSTS;
@@ -320,6 +325,7 @@ float common_hal_mcu_processor_get_voltage(void) {
     adc_sync_deinit(&adc);
     // Multiply by 4 to compensate for SCALEDIOVCC division by 4.
     return (reading / 4095.0f) * 4.0f;
+#endif
 }
 
 uint32_t common_hal_mcu_processor_get_frequency(void) {
diff --git a/ports/atmel-samd/common-hal/microcontroller/__init__.c b/ports/atmel-samd/common-hal/microcontroller/__init__.c
index 09212a0d1..50a1ec038 100644
--- a/ports/atmel-samd/common-hal/microcontroller/__init__.c
+++ b/ports/atmel-samd/common-hal/microcontroller/__init__.c
@@ -275,120 +275,119 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = {
     { MP_ROM_QSTR(MP_QSTR_PB31), MP_ROM_PTR(&pin_PB31) },
 #endif
 
-// These are SAMD51 specific so we assume we want them in RAM
-#if defined(PIN_PC00)
+#if defined(PIN_PC00) && !defined(IGNORE_PIN_PC00)
     { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
 #endif
-#if defined(PIN_PC01)
+#if defined(PIN_PC01) && !defined(IGNORE_PIN_PC01)
     { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
 #endif
-#if defined(PIN_PC02)
+#if defined(PIN_PC02) && !defined(IGNORE_PIN_PC02)
     { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) },
 #endif
-#if defined(PIN_PC03)
+#if defined(PIN_PC03) && !defined(IGNORE_PIN_PC03)
     { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) },
 #endif
-#if defined(PIN_PC04)
+#if defined(PIN_PC04) && !defined(IGNORE_PIN_PC04)
     { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
 #endif
-#if defined(PIN_PC05)
+#if defined(PIN_PC05) && !defined(IGNORE_PIN_PC05)
     { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
 #endif
-#if defined(PIN_PC06)
+#if defined(PIN_PC06) && !defined(IGNORE_PIN_PC06)
     { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
 #endif
-#if defined(PIN_PC07)
+#if defined(PIN_PC07) && !defined(IGNORE_PIN_PC07)
     { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
 #endif
-#if defined(PIN_PC10)
+#if defined(PIN_PC10) && !defined(IGNORE_PIN_PC10)
     { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
 #endif
-#if defined(PIN_PC11)
+#if defined(PIN_PC11) && !defined(IGNORE_PIN_PC11)
     { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
 #endif
-#if defined(PIN_PC12)
+#if defined(PIN_PC12) && !defined(IGNORE_PIN_PC12)
     { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
 #endif
-#if defined(PIN_PC13)
+#if defined(PIN_PC13) && !defined(IGNORE_PIN_PC13)
     { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
 #endif
-#if defined(PIN_PC14)
+#if defined(PIN_PC14) && !defined(IGNORE_PIN_PC14)
     { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) },
 #endif
-#if defined(PIN_PC15)
+#if defined(PIN_PC15) && !defined(IGNORE_PIN_PC15)
     { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) },
 #endif
-#if defined(PIN_PC16)
+#if defined(PIN_PC16) && !defined(IGNORE_PIN_PC16)
     { MP_ROM_QSTR(MP_QSTR_PC16), MP_ROM_PTR(&pin_PC16) },
 #endif
-#if defined(PIN_PC17)
+#if defined(PIN_PC17) && !defined(IGNORE_PIN_PC17)
     { MP_ROM_QSTR(MP_QSTR_PC17), MP_ROM_PTR(&pin_PC17) },
 #endif
-#if defined(PIN_PC18)
+#if defined(PIN_PC18) && !defined(IGNORE_PIN_PC18)
     { MP_ROM_QSTR(MP_QSTR_PC18), MP_ROM_PTR(&pin_PC18) },
 #endif
-#if defined(PIN_PC19)
+#if defined(PIN_PC19) && !defined(IGNORE_PIN_PC19)
     { MP_ROM_QSTR(MP_QSTR_PC19), MP_ROM_PTR(&pin_PC19) },
 #endif
-#if defined(PIN_PC20)
+#if defined(PIN_PC20) && !defined(IGNORE_PIN_PC20)
     { MP_ROM_QSTR(MP_QSTR_PC20), MP_ROM_PTR(&pin_PC20) },
 #endif
-#if defined(PIN_PC21)
+#if defined(PIN_PC21) && !defined(IGNORE_PIN_PC21)
     { MP_ROM_QSTR(MP_QSTR_PC21), MP_ROM_PTR(&pin_PC21) },
 #endif
-#if defined(PIN_PC22)
+#if defined(PIN_PC22) && !defined(IGNORE_PIN_PC22)
     { MP_ROM_QSTR(MP_QSTR_PC22), MP_ROM_PTR(&pin_PC22) },
 #endif
-#if defined(PIN_PC23)
+#if defined(PIN_PC23) && !defined(IGNORE_PIN_PC23)
     { MP_ROM_QSTR(MP_QSTR_PC23), MP_ROM_PTR(&pin_PC23) },
 #endif
-#if defined(PIN_PC24)
+#if defined(PIN_PC24) && !defined(IGNORE_PIN_PC24)
     { MP_ROM_QSTR(MP_QSTR_PC24), MP_ROM_PTR(&pin_PC24) },
 #endif
-#if defined(PIN_PC25)
+#if defined(PIN_PC25) && !defined(IGNORE_PIN_PC25)
     { MP_ROM_QSTR(MP_QSTR_PC25), MP_ROM_PTR(&pin_PC25) },
 #endif
-#if defined(PIN_PC26)
+#if defined(PIN_PC26) && !defined(IGNORE_PIN_PC26)
     { MP_ROM_QSTR(MP_QSTR_PC26), MP_ROM_PTR(&pin_PC26) },
 #endif
-#if defined(PIN_PC27)
+#if defined(PIN_PC27) && !defined(IGNORE_PIN_PC27)
     { MP_ROM_QSTR(MP_QSTR_PC27), MP_ROM_PTR(&pin_PC27) },
 #endif
-#if defined(PIN_PC28)
+#if defined(PIN_PC28) && !defined(IGNORE_PIN_PC28)
     { MP_ROM_QSTR(MP_QSTR_PC28), MP_ROM_PTR(&pin_PC28) },
 #endif
-#if defined(PIN_PC30)
+#if defined(PIN_PC30) && !defined(IGNORE_PIN_PC30)
     { MP_ROM_QSTR(MP_QSTR_PC30), MP_ROM_PTR(&pin_PC30) },
 #endif
-#if defined(PIN_PC31)
+#if defined(PIN_PC31) && !defined(IGNORE_PIN_PC31)
     { MP_ROM_QSTR(MP_QSTR_PC31), MP_ROM_PTR(&pin_PC31) },
 #endif
 
-#if defined(PIN_PD00)
+#if defined(PIN_PD00) && !defined(IGNORE_PIN_PD00)
     { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
 #endif
-#if defined(PIN_PD01)
+#if defined(PIN_PD01) && !defined(IGNORE_PIN_PD01)
     { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
 #endif
-#if defined(PIN_PD08)
+#if defined(PIN_PD08) && !defined(IGNORE_PIN_PD08)
     { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
 #endif
-#if defined(PIN_PD09)
+#if defined(PIN_PD09) && !defined(IGNORE_PIN_PD09)
     { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
 #endif
-#if defined(PIN_PD10)
+#if defined(PIN_PD10) && !defined(IGNORE_PIN_PD10)
     { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
 #endif
-#if defined(PIN_PD11)
+#if defined(PIN_PD11) && !defined(IGNORE_PIN_PD11)
     { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
 #endif
-#if defined(PIN_PD12)
+#if defined(PIN_PD12) && !defined(IGNORE_PIN_PD12)
     { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
 #endif
-#if defined(PIN_PD20)
+#if defined(PIN_PD20) && !defined(IGNORE_PIN_PD20)
     { MP_ROM_QSTR(MP_QSTR_PD20), MP_ROM_PTR(&pin_PD20) },
 #endif
-#if defined(PIN_PD21)
+#if defined(PIN_PD21) && !defined(IGNORE_PIN_PD21)
     { MP_ROM_QSTR(MP_QSTR_PD21), MP_ROM_PTR(&pin_PD21) },
 #endif
 };
diff --git a/ports/atmel-samd/common-hal/neopixel_write/__init__.c b/ports/atmel-samd/common-hal/neopixel_write/__init__.c
index 43c8575cb..6f2090b98 100644
--- a/ports/atmel-samd/common-hal/neopixel_write/__init__.c
+++ b/ports/atmel-samd/common-hal/neopixel_write/__init__.c
@@ -34,6 +34,9 @@
 #if defined(SAME54)
 #include "hri/hri_cmcc_e54.h"
 #include "hri/hri_nvmctrl_e54.h"
+#elif defined(SAME51)
+#include "hri/hri_cmcc_e51.h"
+#include "hri/hri_nvmctrl_e51.h"
 #elif defined(SAMD51)
 #include "hri/hri_cmcc_d51.h"
 #include "hri/hri_nvmctrl_d51.h"
diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.c b/ports/atmel-samd/common-hal/pulseio/PulseIn.c
index d3d993672..f65d58364 100644
--- a/ports/atmel-samd/common-hal/pulseio/PulseIn.c
+++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.c
@@ -44,12 +44,14 @@
 #include "shared-bindings/pulseio/PulseIn.h"
 #include "supervisor/shared/tick.h"
 #include "supervisor/shared/translate.h"
+#include "supervisor/port.h"
 
 // This timer is shared amongst all PulseIn objects as a higher resolution clock.
 static uint8_t refcount = 0;
 static uint8_t pulsein_tc_index = 0xff;
 
 volatile static uint32_t overflow_count = 0;
+volatile static uint32_t start_overflow = 0;
 
 void pulsein_timer_interrupt_handler(uint8_t index) {
     if (index != pulsein_tc_index) return;
@@ -77,6 +79,8 @@ static void pulsein_set_config(pulseio_pulsein_obj_t* self, bool first_edge) {
 }
 
 void pulsein_interrupt_handler(uint8_t channel) {
+    // Turn off interrupts while in handler
+    common_hal_mcu_disable_interrupts();
     // Grab the current time first.
     uint32_t current_overflow = overflow_count;
     Tc* tc = tc_insts[pulsein_tc_index];
@@ -88,10 +92,8 @@ void pulsein_interrupt_handler(uint8_t channel) {
     uint32_t current_count = tc->COUNT16.COUNT.reg;
 
     pulseio_pulsein_obj_t* self = get_eic_channel_data(channel);
-    if (!supervisor_background_tasks_ok() || self->errored_too_fast) {
-        self->errored_too_fast = true;
-        common_hal_pulseio_pulsein_pause(self);
-        return;
+    if (self->len == 0 ) {
+        start_overflow = overflow_count;
     }
     if (self->first_edge) {
         self->first_edge = false;
@@ -112,6 +114,13 @@ void pulsein_interrupt_handler(uint8_t channel) {
         if (total_diff < duration) {
             duration = total_diff;
         }
+        //check if the input is taking too long, 15 timer overflows is approx 1 second
+        if (current_overflow - start_overflow > 15) {
+            self->errored_too_fast = true;
+            common_hal_pulseio_pulsein_pause(self);
+            common_hal_mcu_enable_interrupts();
+            return;
+        }
 
         uint16_t i = (self->start + self->len) % self->maxlen;
         self->buffer[i] = duration;
@@ -123,6 +132,7 @@ void pulsein_interrupt_handler(uint8_t channel) {
     }
     self->last_overflow = current_overflow;
     self->last_count = current_count;
+    common_hal_mcu_enable_interrupts();
 }
 
 void pulsein_reset() {
@@ -264,9 +274,6 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self,
     // Make sure we're paused.
     common_hal_pulseio_pulsein_pause(self);
 
-    // Reset erroring
-    self->errored_too_fast = false;
-
     // Send the trigger pulse.
     if (trigger_duration > 0) {
         gpio_set_pin_pull_mode(self->pin, GPIO_PULL_OFF);
@@ -280,6 +287,7 @@ void common_hal_pulseio_pulsein_resume(pulseio_pulsein_obj_t* self,
     self->first_edge = true;
     self->last_overflow = 0;
     self->last_count = 0;
+    self->errored_too_fast = false;
     gpio_set_pin_function(self->pin, GPIO_PIN_FUNCTION_A);
     uint32_t mask = 1 << self->channel;
     // Clear previous interrupt state and re-enable it.
@@ -300,12 +308,15 @@ uint16_t common_hal_pulseio_pulsein_popleft(pulseio_pulsein_obj_t* self) {
     if (self->len == 0) {
         mp_raise_IndexError_varg(translate("pop from empty %q"), MP_QSTR_PulseIn);
     }
+    if (self->errored_too_fast) {
+      self->errored_too_fast = 0;
+      mp_raise_RuntimeError(translate("Input taking too long"));
+    }
     common_hal_mcu_disable_interrupts();
     uint16_t value = self->buffer[self->start];
     self->start = (self->start + 1) % self->maxlen;
     self->len--;
     common_hal_mcu_enable_interrupts();
-
     return value;
 }
 
diff --git a/ports/atmel-samd/common-hal/pulseio/PulseIn.h b/ports/atmel-samd/common-hal/pulseio/PulseIn.h
index 99358178f..b91bbd703 100644
--- a/ports/atmel-samd/common-hal/pulseio/PulseIn.h
+++ b/ports/atmel-samd/common-hal/pulseio/PulseIn.h
@@ -51,7 +51,6 @@ void pulsein_reset(void);
 void pulsein_interrupt_handler(uint8_t channel);
 void pulsein_timer_interrupt_handler(uint8_t index);
 #ifdef SAMD21
-void rtc_set_continuous(void);
 void rtc_start_pulsein(void);
 void rtc_end_pulsein(void);
 #endif
diff --git a/ports/atmel-samd/common-hal/sdioio/SDCard.c b/ports/atmel-samd/common-hal/sdioio/SDCard.c
index 8cd077ecd..4d2539aa5 100644
--- a/ports/atmel-samd/common-hal/sdioio/SDCard.c
+++ b/ports/atmel-samd/common-hal/sdioio/SDCard.c
@@ -58,24 +58,6 @@
 
 static Sdhc *sdhc_insts[] = SDHC_INSTS;
 
-STATIC pin_function_t *find_pin_function(pin_function_t *table, const mcu_pin_obj_t *pin, int instance, uint16_t name) {
-    DEBUG_PRINT("\n\n[inst=% 2d] %q: ", instance, name);
-    DEBUG_PRINT_OBJ_NL(pin);
-
-    for(; table->obj; table++) {
-        DEBUG_PRINT("[inst=% 2d] considering table @%p: ");
-        DEBUG_PRINT_OBJ(table->obj);
-        DEBUG_PRINT(" %d %d\n", table->instance, table->pin);
-        if (instance != -1 && instance != table->instance) {
-            continue;
-        }
-        if (pin == table->obj) {
-            return table;
-        }
-    }
-    mp_raise_ValueError_varg(translate("%q pin invalid"), name);
-}
-
 void common_hal_sdioio_sdcard_construct(sdioio_sdcard_obj_t *self,
         const mcu_pin_obj_t * clock, const mcu_pin_obj_t * command,
         uint8_t num_data, mcu_pin_obj_t ** data, uint32_t frequency) {
@@ -98,15 +80,15 @@ CLK PA21 PCC_D? (D32)  BROWN
 
 */
 
-    pin_function_t *functions[6] = {};
-    functions[0] = find_pin_function(sdio_cmd, command, -1, MP_QSTR_command);
+    mcu_pin_function_t *functions[6] = {};
+    functions[0] = mcu_find_pin_function(sdio_cmd, command, -1, MP_QSTR_command);
     int instance = functions[0]->instance;
-    functions[1] = find_pin_function(sdio_ck, clock, instance, MP_QSTR_clock);
-    functions[2] = find_pin_function(sdio_dat0, data[0], instance, MP_QSTR_data0);
+    functions[1] = mcu_find_pin_function(sdio_ck, clock, instance, MP_QSTR_clock);
+    functions[2] = mcu_find_pin_function(sdio_dat0, data[0], instance, MP_QSTR_data0);
     if(num_data == 4) {
-        functions[3] = find_pin_function(sdio_dat1, data[1], instance, MP_QSTR_data1);
-        functions[4] = find_pin_function(sdio_dat2, data[2], instance, MP_QSTR_data2);
-        functions[5] = find_pin_function(sdio_dat3, data[3], instance, MP_QSTR_data3);
+        functions[3] = mcu_find_pin_function(sdio_dat1, data[1], instance, MP_QSTR_data1);
+        functions[4] = mcu_find_pin_function(sdio_dat2, data[2], instance, MP_QSTR_data2);
+        functions[5] = mcu_find_pin_function(sdio_dat3, data[3], instance, MP_QSTR_data3);
     }
 
     // We've verified all pins, now set their special functions
@@ -114,7 +96,7 @@ CLK PA21 PCC_D? (D32)  BROWN
     self->clock_pin = common_hal_mcu_pin_number(functions[1]->obj);
 
     for(int i=0; i<num_data; i++) {
-        pin_function_t *function = functions[2+i];
+        mcu_pin_function_t *function = functions[2+i];
         if (function) {
             self->data_pins[i] = common_hal_mcu_pin_number(function->obj);
         } else {
@@ -144,8 +126,8 @@ CLK PA21 PCC_D? (D32)  BROWN
         hri_mclk_set_AHBMASK_SDHC0_bit(MCLK);
         hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, CONF_GCLK_SDHC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
         hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, CONF_GCLK_SDHC0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
-    } else {
 #ifdef SDHC1_GCLK_ID
+    } else {
         hri_mclk_set_AHBMASK_SDHC1_bit(MCLK);
         hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID, CONF_GCLK_SDHC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
         hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID_SLOW, CONF_GCLK_SDHC1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
diff --git a/ports/atmel-samd/mpconfigport.h b/ports/atmel-samd/mpconfigport.h
index 2a2428d67..ed10da9b9 100644
--- a/ports/atmel-samd/mpconfigport.h
+++ b/ports/atmel-samd/mpconfigport.h
@@ -43,12 +43,13 @@
 #define MICROPY_PY_SYS_PLATFORM                     "Atmel SAMD21"
 #define SPI_FLASH_MAX_BAUDRATE 8000000
 #define MICROPY_PY_BUILTINS_NOTIMPLEMENTED          (0)
-#define MICROPY_PY_COLLECTIONS_ORDEREDDICT          (0)
 #define MICROPY_PY_FUNCTION_ATTRS                   (0)
 // MICROPY_PY_UJSON depends on MICROPY_PY_IO
 #define MICROPY_PY_IO                               (0)
 #define MICROPY_PY_REVERSE_SPECIAL_METHODS          (0)
+#define MICROPY_PY_UBINASCII                        (0)
 #define MICROPY_PY_UJSON                            (0)
+#define MICROPY_PY_COLLECTIONS_ORDEREDDICT          (0)
 #define MICROPY_PY_UERRNO_LIST \
     X(EPERM) \
     X(ENOENT) \
@@ -75,10 +76,12 @@
 #define MICROPY_PY_SYS_PLATFORM                     "MicroChip SAMD51"
 #elif defined(SAME54)
 #define MICROPY_PY_SYS_PLATFORM                     "MicroChip SAME54"
+#ifndef MICROCONTROLLER_VOLTAGE_DISABLE
+#define MICROCONTROLLER_VOLTAGE_DISABLE (1)
+#endif
 #endif
 #define SPI_FLASH_MAX_BAUDRATE 24000000
 #define MICROPY_PY_BUILTINS_NOTIMPLEMENTED          (1)
-#define MICROPY_PY_COLLECTIONS_ORDEREDDICT          (1)
 #define MICROPY_PY_FUNCTION_ATTRS                   (1)
 // MICROPY_PY_UJSON depends on MICROPY_PY_IO
 #define MICROPY_PY_IO                               (1)
@@ -246,4 +249,8 @@
     CIRCUITPY_COMMON_ROOT_POINTERS \
     mp_obj_t playing_audio[AUDIO_DMA_CHANNEL_COUNT];
 
+#ifndef MICROCONTROLLER_VOLTAGE_DISABLE
+#define MICROCONTROLLER_VOLTAGE_DISABLE (0)
+#endif
+
 #endif  // __INCLUDED_MPCONFIGPORT_H
diff --git a/ports/atmel-samd/mpconfigport.mk b/ports/atmel-samd/mpconfigport.mk
index a16daf4b0..1929e146d 100644
--- a/ports/atmel-samd/mpconfigport.mk
+++ b/ports/atmel-samd/mpconfigport.mk
@@ -37,6 +37,9 @@ ifndef CIRCUITPY_TOUCHIO_USE_NATIVE
 CIRCUITPY_TOUCHIO_USE_NATIVE = 1
 endif
 
+# No room for HCI _bleio on SAMD21.
+CIRCUITPY_BLEIO_HCI = 0
+
 CIRCUITPY_SDCARDIO ?= 0
 
 # Not enough RAM for framebuffers
diff --git a/ports/atmel-samd/peripherals b/ports/atmel-samd/peripherals
-Subproject 0f5f1522d09c8fa7d858edec484a994c21c5966
+Subproject a7e39c4d01aa5916015beecb021777617e77b0a
diff --git a/ports/atmel-samd/reset.c b/ports/atmel-samd/reset.c
index 735639cc4..066c9897a 100644
--- a/ports/atmel-samd/reset.c
+++ b/ports/atmel-samd/reset.c
@@ -29,6 +29,8 @@
 #include "reset.h"
 #include "supervisor/filesystem.h"
 
+void NVIC_SystemReset(void) NORETURN;
+
 void reset(void) {
     filesystem_flush();
     NVIC_SystemReset();
diff --git a/ports/atmel-samd/reset.h b/ports/atmel-samd/reset.h
index b589d2611..482eb6ee8 100644
--- a/ports/atmel-samd/reset.h
+++ b/ports/atmel-samd/reset.h
@@ -29,14 +29,16 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#include "py/mpconfig.h"
+
 // Copied from inc/uf2.h in https://github.com/Microsoft/uf2-samd21
 #define DBL_TAP_MAGIC 0xf01669ef // Randomly selected, adjusted to have first and last bit set
 #define DBL_TAP_MAGIC_QUICK_BOOT 0xf02669ef
 
 extern uint32_t _bootloader_dbl_tap;
 
-void reset_to_bootloader(void);
-void reset(void);
+void reset_to_bootloader(void) NORETURN;
+void reset(void) NORETURN;
 bool bootloader_available(void);
 
 #endif  // MICROPY_INCLUDED_ATMEL_SAMD_RESET_H
diff --git a/ports/atmel-samd/supervisor/internal_flash.c b/ports/atmel-samd/supervisor/internal_flash.c
index ecb59f836..4c7ca0dc7 100644
--- a/ports/atmel-samd/supervisor/internal_flash.c
+++ b/ports/atmel-samd/supervisor/internal_flash.c
@@ -39,6 +39,9 @@
 #ifdef SAMD21
 #include "hpl/pm/hpl_pm_base.h"
 #endif
+#ifdef SAME51
+#include "hri/hri_mclk_e51.h"
+#endif
 #ifdef SAME54
 #include "hri/hri_mclk_e54.h"
 #endif
diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c
index 6352afb1d..d65d09825 100644
--- a/ports/atmel-samd/supervisor/port.c
+++ b/ports/atmel-samd/supervisor/port.c
@@ -44,6 +44,9 @@
 #include "hri/hri_pm_d21.h"
 #elif defined(SAME54)
 #include "hri/hri_rstc_e54.h"
+#elif defined(SAME51)
+#include "sam.h"
+#include "hri/hri_rstc_e51.h"
 #elif defined(SAMD51)
 #include "hri/hri_rstc_d51.h"
 #else
@@ -93,19 +96,20 @@
 #endif
 volatile bool hold_interrupt = false;
 #ifdef SAMD21
+static void rtc_set_continuous(bool continuous) {
+    while (RTC->MODE0.STATUS.bit.SYNCBUSY);
+    RTC->MODE0.READREQ.reg = (continuous ? RTC_READREQ_RCONT : 0) | 0x0010;
+    while (RTC->MODE0.STATUS.bit.SYNCBUSY);
+}
+
 void rtc_start_pulsein(void) {
-    rtc_set_continuous();
+    rtc_set_continuous(true);
     hold_interrupt = true;
 }
 
 void rtc_end_pulsein(void) {
     hold_interrupt = false;
-}
-
-void rtc_set_continuous(void) {
-    while (RTC->MODE0.STATUS.bit.SYNCBUSY);
-    RTC->MODE0.READREQ.reg = RTC_READREQ_RREQ | RTC_READREQ_RCONT | 0x0010;
-    while (RTC->MODE0.STATUS.bit.SYNCBUSY);
+    rtc_set_continuous(false);
 }
 #endif
 
@@ -427,6 +431,42 @@ uint32_t port_get_saved_word(void) {
 static volatile uint64_t overflowed_ticks = 0;
 static volatile bool _ticks_enabled = false;
 
+static uint32_t _get_count(uint32_t* overflow_count) {
+    #ifdef SAM_D5X_E5X
+    while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) {}
+    #endif
+    #ifdef SAMD21
+    // Request a read so we don't stall the bus later. See section 14.3.1.5 Read Request
+    RTC->MODE0.READREQ.reg = RTC_READREQ_RREQ | 0x0010;
+    while (RTC->MODE0.STATUS.bit.SYNCBUSY != 0) {}
+    #endif
+    // Disable interrupts so we can grab the count and the overflow.
+    common_hal_mcu_disable_interrupts();
+    uint32_t count = RTC->MODE0.COUNT.reg;
+    if (overflow_count != NULL) {
+        *overflow_count = overflowed_ticks;
+    }
+    common_hal_mcu_enable_interrupts();
+
+    return count;
+}
+
+static void _port_interrupt_after_ticks(uint32_t ticks) {
+    uint32_t current_ticks = _get_count(NULL);
+    if (ticks > 1 << 28) {
+        // We'll interrupt sooner with an overflow.
+        return;
+    }
+#ifdef SAMD21
+    if (hold_interrupt) {
+        return;
+    }
+#endif
+    RTC->MODE0.COMP[0].reg = current_ticks + (ticks << 4);
+    RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+    RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
 void RTC_Handler(void) {
     uint32_t intflag = RTC->MODE0.INTFLAG.reg;
     if (intflag & RTC_MODE0_INTFLAG_OVF) {
@@ -449,7 +489,7 @@ void RTC_Handler(void) {
             supervisor_tick();
             // Check _ticks_enabled again because a tick handler may have turned it off.
             if (_ticks_enabled) {
-                port_interrupt_after_ticks(1);
+                _port_interrupt_after_ticks(1);
             }
         }
         #endif
@@ -459,24 +499,14 @@ void RTC_Handler(void) {
     }
 }
 
-static uint32_t _get_count(void) {
-    #ifdef SAM_D5X_E5X
-    while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) {}
-    #endif
-    #ifdef SAMD21
-    while (RTC->MODE0.STATUS.bit.SYNCBUSY != 0) {}
-    #endif
-
-    return RTC->MODE0.COUNT.reg;
-}
-
 uint64_t port_get_raw_ticks(uint8_t* subticks) {
-    uint32_t current_ticks = _get_count();
+    uint32_t overflow_count;
+    uint32_t current_ticks = _get_count(&overflow_count);
     if (subticks != NULL) {
         *subticks = (current_ticks % 16) * 2;
     }
 
-    return overflowed_ticks + current_ticks / 16;
+    return overflow_count + current_ticks / 16;
 }
 
 // Enable 1/1024 second tick.
@@ -486,8 +516,9 @@ void port_enable_tick(void) {
     RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
     #endif
     #ifdef SAMD21
+    // TODO: Switch to using the PER *event* from the RTC to generate an interrupt via EVSYS.
     _ticks_enabled = true;
-    port_interrupt_after_ticks(1);
+    _port_interrupt_after_ticks(1);
     #endif
 }
 
@@ -502,20 +533,14 @@ void port_disable_tick(void) {
     #endif
 }
 
+// This is called by sleep, we ignore it when our ticks are enabled because
+// they'll wake us up earlier. If we don't, we'll mess up ticks by overwriting
+// the next RTC wake up time.
 void port_interrupt_after_ticks(uint32_t ticks) {
-    uint32_t current_ticks = _get_count();
-    if (ticks > 1 << 28) {
-        // We'll interrupt sooner with an overflow.
+    if (_ticks_enabled) {
         return;
     }
-#ifdef SAMD21
-    if (hold_interrupt) {
-        return;
-    }
-#endif
-    RTC->MODE0.COMP[0].reg = current_ticks + (ticks << 4);
-    RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
-    RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+    _port_interrupt_after_ticks(ticks);
 }
 
 void port_sleep_until_interrupt(void) {
diff --git a/ports/atmel-samd/supervisor/same51_cpu.s b/ports/atmel-samd/supervisor/same51_cpu.s
new file mode 100755
index 000000000..9e6807a5e
--- /dev/null
+++ b/ports/atmel-samd/supervisor/same51_cpu.s
@@ -0,0 +1,27 @@
+.syntax unified
+.cpu cortex-m4
+.thumb
+.text
+.align  2
+
+@ uint cpu_get_regs_and_sp(r0=uint regs[10])
+.global cpu_get_regs_and_sp
+.thumb
+.thumb_func
+.type   cpu_get_regs_and_sp, %function
+cpu_get_regs_and_sp:
+@ store registers into given array
+str     r4, [r0], #4
+str     r5, [r0], #4
+str     r6, [r0], #4
+str     r7, [r0], #4
+str     r8, [r0], #4
+str     r9, [r0], #4
+str     r10, [r0], #4
+str     r11, [r0], #4
+str     r12, [r0], #4
+str     r13, [r0], #4
+
+@ return the sp
+mov     r0, sp
+bx      lr
diff --git a/ports/atmel-samd/tools/mkcandata.py b/ports/atmel-samd/tools/mkcandata.py
new file mode 100755
index 000000000..9668d2208
--- /dev/null
+++ b/ports/atmel-samd/tools/mkcandata.py
@@ -0,0 +1,31 @@
+#!/usr/bin/python3
+
+def defines(name, suffix):
+    print(f'mcu_pin_function_t {name} [] = {{')
+    for instance in (0, 1):
+        for function in 'HI':
+            for port in 'ABCD':
+                for idx in range(32):
+                    pin = f'P{port}{idx:02d}'
+                    pinmux = f'PINMUX_{pin}{function}_CAN{instance}_{suffix}'
+                    print(f'''\
+#if defined({pinmux}) && ! defined(IGNORE_PIN_{pin})
+    {{&pin_{pin}, {instance}, PIN_{pin}, {pinmux} & 0xffff}},
+#endif''')
+    print(f'{{NULL, 0, 0}}')
+    print(f'}};')
+    print()
+
+print('''\
+#include <stdint.h>
+#include "py/obj.h"
+#include "sam.h"
+#include "samd/pins.h"
+#include "mpconfigport.h"
+#include "atmel_start_pins.h"
+#include "hal/include/hal_gpio.h"
+#include "common-hal/microcontroller/Pin.h"
+''')
+
+defines('can_rx', 'RX')
+defines('can_tx', 'TX')
diff --git a/ports/atmel-samd/tools/mksdiodata.py b/ports/atmel-samd/tools/mksdiodata.py
index 0cce3819f..48c4a085f 100755
--- a/ports/atmel-samd/tools/mksdiodata.py
+++ b/ports/atmel-samd/tools/mksdiodata.py
@@ -1,7 +1,7 @@
 #!/usr/bin/python3
 
 def defines(name, function):
-    print(f'pin_function_t {name} [] = {{')
+    print(f'mcu_pin_function_t {name} [] = {{')
     for instance in (0, 1):
         for port in 'ABCD':
             for idx in range(32):
@@ -23,13 +23,8 @@ print('''\
 #include "mpconfigport.h"
 #include "atmel_start_pins.h"
 #include "hal/include/hal_gpio.h"
+#include "common-hal/microcontroller/Pin.h"
 
-typedef struct {
-    const mcu_pin_obj_t *obj;
-    uint8_t instance;
-    uint8_t pin;
-    uint16_t function;
-} pin_function_t;
 ''')
 
 defines('sdio_ck', 'SDCK')