Merge branch 'main' into esp32-analogin

68 files changed, 714 insertions, 140 deletions

diff --git a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h
index 54789f04f..4321335e5 100644
--- a/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h
+++ b/ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.h
@@ -25,7 +25,7 @@
 #define CALIBRATE_CRYSTALLESS 1
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 // Increase stack size slightly due to CPX library import nesting
 #define CIRCUITPY_DEFAULT_STACK_SIZE  (4248) //divisible by 8
diff --git a/ports/atmel-samd/boards/circuitplayground_express_crickit/mpconfigboard.h b/ports/atmel-samd/boards/circuitplayground_express_crickit/mpconfigboard.h
index e377275b7..5673be290 100644
--- a/ports/atmel-samd/boards/circuitplayground_express_crickit/mpconfigboard.h
+++ b/ports/atmel-samd/boards/circuitplayground_express_crickit/mpconfigboard.h
@@ -27,7 +27,7 @@
 #define USER_NEOPIXELS_PIN      (&pin_PB23)
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 // Increase stack size slightly due to CPX library import nesting
 #define CIRCUITPY_DEFAULT_STACK_SIZE  (4248) // divisible by 8
diff --git a/ports/atmel-samd/boards/circuitplayground_express_displayio/mpconfigboard.h b/ports/atmel-samd/boards/circuitplayground_express_displayio/mpconfigboard.h
index cacbed0de..fab235149 100644
--- a/ports/atmel-samd/boards/circuitplayground_express_displayio/mpconfigboard.h
+++ b/ports/atmel-samd/boards/circuitplayground_express_displayio/mpconfigboard.h
@@ -25,7 +25,7 @@
 #define CALIBRATE_CRYSTALLESS 1
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 // Increase stack size slightly due to CPX library import nesting.
 #define CIRCUITPY_DEFAULT_STACK_SIZE  (4248)  // divisible by 8
diff --git a/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.h b/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.h
index ac1add545..c4c8c4f3c 100644
--- a/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.h
+++ b/ports/atmel-samd/boards/escornabot_makech/mpconfigboard.h
@@ -11,7 +11,7 @@
 #define CALIBRATE_CRYSTALLESS 1
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PA08)
 #define DEFAULT_I2C_BUS_SDA (&pin_PA09)
diff --git a/ports/atmel-samd/boards/hallowing_m0_express/board.c b/ports/atmel-samd/boards/hallowing_m0_express/board.c
index 4717e6ceb..14a2bdb81 100644
--- a/ports/atmel-samd/boards/hallowing_m0_express/board.c
+++ b/ports/atmel-samd/boards/hallowing_m0_express/board.c
@@ -110,7 +110,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // not SH1107
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/hallowing_m4_express/board.c b/ports/atmel-samd/boards/hallowing_m4_express/board.c
index 7da1d8128..61e797d65 100644
--- a/ports/atmel-samd/boards/hallowing_m4_express/board.c
+++ b/ports/atmel-samd/boards/hallowing_m4_express/board.c
@@ -91,7 +91,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // not SH1107
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/meowmeow/mpconfigboard.h b/ports/atmel-samd/boards/meowmeow/mpconfigboard.h
index 79d477cac..7bbbf3322 100644
--- a/ports/atmel-samd/boards/meowmeow/mpconfigboard.h
+++ b/ports/atmel-samd/boards/meowmeow/mpconfigboard.h
@@ -11,7 +11,7 @@
 #define CALIBRATE_CRYSTALLESS 1
 
 // Explanation of how a user got into safe mode.
-#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing both buttons at start up.\n")
 
 #define DEFAULT_I2C_BUS_SCL (&pin_PA01)
 #define DEFAULT_I2C_BUS_SDA (&pin_PA00)
diff --git a/ports/atmel-samd/boards/monster_m4sk/board.c b/ports/atmel-samd/boards/monster_m4sk/board.c
index 4dd65f8c9..45fea9d52 100644
--- a/ports/atmel-samd/boards/monster_m4sk/board.c
+++ b/ports/atmel-samd/boards/monster_m4sk/board.c
@@ -92,7 +92,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pewpew_m4/board.c b/ports/atmel-samd/boards/pewpew_m4/board.c
index 52a52b4b7..d02e0dc01 100644
--- a/ports/atmel-samd/boards/pewpew_m4/board.c
+++ b/ports/atmel-samd/boards/pewpew_m4/board.c
@@ -143,7 +143,8 @@ void board_init(void) {
         false, // data_as_commands
         false, // auto_refresh
         20, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pybadge/board.c b/ports/atmel-samd/boards/pybadge/board.c
index 45298acc2..35f228c75 100644
--- a/ports/atmel-samd/boards/pybadge/board.c
+++ b/ports/atmel-samd/boards/pybadge/board.c
@@ -114,7 +114,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pybadge_airlift/board.c b/ports/atmel-samd/boards/pybadge_airlift/board.c
index 7495c7d48..fe3e4a017 100644
--- a/ports/atmel-samd/boards/pybadge_airlift/board.c
+++ b/ports/atmel-samd/boards/pybadge_airlift/board.c
@@ -92,7 +92,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pygamer/board.c b/ports/atmel-samd/boards/pygamer/board.c
index 2e83440ea..b478b5947 100644
--- a/ports/atmel-samd/boards/pygamer/board.c
+++ b/ports/atmel-samd/boards/pygamer/board.c
@@ -114,7 +114,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pygamer_advance/board.c b/ports/atmel-samd/boards/pygamer_advance/board.c
index 330446b6f..7dfe07c00 100644
--- a/ports/atmel-samd/boards/pygamer_advance/board.c
+++ b/ports/atmel-samd/boards/pygamer_advance/board.c
@@ -92,7 +92,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pyportal/board.c b/ports/atmel-samd/boards/pyportal/board.c
index d14b6b6a5..cd94f6887 100644
--- a/ports/atmel-samd/boards/pyportal/board.c
+++ b/ports/atmel-samd/boards/pyportal/board.c
@@ -100,7 +100,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/pyportal_titano/board.c b/ports/atmel-samd/boards/pyportal_titano/board.c
index 0ee2e68aa..dc417f5d1 100644
--- a/ports/atmel-samd/boards/pyportal_titano/board.c
+++ b/ports/atmel-samd/boards/pyportal_titano/board.c
@@ -117,7 +117,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c b/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c
index b7fc736eb..49db49860 100644
--- a/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c
+++ b/ports/atmel-samd/boards/seeeduino_wio_terminal/board.c
@@ -31,8 +31,12 @@
 #include "shared-bindings/displayio/FourWire.h"
 #include "shared-module/displayio/__init__.h"
 #include "shared-module/displayio/mipi_constants.h"
+#include "shared-bindings/digitalio/DigitalInOut.h"
 
 displayio_fourwire_obj_t board_display_obj;
+digitalio_digitalinout_obj_t CTR_5V;
+digitalio_digitalinout_obj_t CTR_3V3;
+digitalio_digitalinout_obj_t USB_HOST_ENABLE;
 
 uint8_t display_init_sequence[] = {
     0x01, 0x80, 0x80, // Software reset then delay 0x80 (128ms)
@@ -105,7 +109,27 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
+
+        // Enabling the Power of the 40-pin at the back
+        CTR_5V.base.type = &digitalio_digitalinout_type;
+        CTR_3V3.base.type = &digitalio_digitalinout_type;
+        USB_HOST_ENABLE.base.type = &digitalio_digitalinout_type;
+
+        common_hal_digitalio_digitalinout_construct(&CTR_5V, PIN_CTR_5V);
+        common_hal_digitalio_digitalinout_construct(&CTR_3V3, PIN_CTR_3V3);
+        common_hal_digitalio_digitalinout_construct(&USB_HOST_ENABLE, PIN_USB_HOST_ENABLE);
+
+        common_hal_digitalio_digitalinout_set_value(&CTR_5V, true);
+        common_hal_digitalio_digitalinout_set_value(&CTR_3V3, false);
+        common_hal_digitalio_digitalinout_set_value(&USB_HOST_ENABLE, false);
+
+        // Never reset
+        common_hal_digitalio_digitalinout_never_reset(&CTR_5V);
+        common_hal_digitalio_digitalinout_never_reset(&CTR_3V3);
+        common_hal_digitalio_digitalinout_never_reset(&USB_HOST_ENABLE);
+
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/boards/seeeduino_wio_terminal/mpconfigboard.h b/ports/atmel-samd/boards/seeeduino_wio_terminal/mpconfigboard.h
index f7d0448df..c87ca46d8 100644
--- a/ports/atmel-samd/boards/seeeduino_wio_terminal/mpconfigboard.h
+++ b/ports/atmel-samd/boards/seeeduino_wio_terminal/mpconfigboard.h
@@ -27,6 +27,10 @@
 #define DEFAULT_UART_BUS_RX (&pin_PB27)
 #define DEFAULT_UART_BUS_TX (&pin_PB26)
 
+#define PIN_CTR_5V (&pin_PC14)
+#define PIN_CTR_3V3 (&pin_PC15)
+#define PIN_USB_HOST_ENABLE (&pin_PA27)
+
 // USB is always used internally so skip the pin objects for it.
 #define IGNORE_PIN_PA24     1
 #define IGNORE_PIN_PA25     1
diff --git a/ports/atmel-samd/boards/ugame10/board.c b/ports/atmel-samd/boards/ugame10/board.c
index 3bb9eab7d..9f2b8d039 100644
--- a/ports/atmel-samd/boards/ugame10/board.c
+++ b/ports/atmel-samd/boards/ugame10/board.c
@@ -111,7 +111,8 @@ void board_init(void) {
         false, // data as commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/atmel-samd/common-hal/canio/CAN.c b/ports/atmel-samd/common-hal/canio/CAN.c
index 4f28698fb..76599a9a7 100644
--- a/ports/atmel-samd/common-hal/canio/CAN.c
+++ b/ports/atmel-samd/common-hal/canio/CAN.c
@@ -275,21 +275,6 @@ int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self)
     return self->hw->ECR.bit.REC;
 }
 
-int common_hal_canio_can_error_warning_state_count_get(canio_can_obj_t *self)
-{
-    return self->error_warning_state_count;
-}
-
-int common_hal_canio_can_error_passive_state_count_get(canio_can_obj_t *self)
-{
-    return self->error_passive_state_count;
-}
-
-int common_hal_canio_can_bus_off_state_count_get(canio_can_obj_t *self)
-{
-    return self->bus_off_state_count;
-}
-
 canio_bus_state_t common_hal_canio_can_state_get(canio_can_obj_t *self) {
     CAN_PSR_Type psr = self->hw->PSR;
     if (psr.bit.BO) {
@@ -328,16 +313,18 @@ static void maybe_auto_restart(canio_can_obj_t *self) {
     }
 }
 
-void common_hal_canio_can_send(canio_can_obj_t *self, canio_message_obj_t *message)
+void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in)
 {
     maybe_auto_restart(self);
 
+    canio_message_obj_t *message = message_in;;
     // We have just one dedicated TX buffer, use it!
     canio_can_tx_buffer_t *ent = &self->state->tx_buffer[0];
 
+    bool rtr = message->base.type == &canio_remote_transmission_request_type;
     ent->txb0.bit.ESI = false;
     ent->txb0.bit.XTD = message->extended;
-    ent->txb0.bit.RTR = message->rtr;
+    ent->txb0.bit.RTR = rtr;
     if (message->extended) {
         ent->txb0.bit.ID = message->id;
     } else {
@@ -350,7 +337,7 @@ void common_hal_canio_can_send(canio_can_obj_t *self, canio_message_obj_t *messa
     ent->txb1.bit.BRS = 0; // No bit rate switching
     ent->txb1.bit.DLC = message->size;
 
-    if (!message->rtr) {
+    if (!rtr) {
         memcpy(ent->data, message->data, message->size);
     }
 
@@ -417,17 +404,6 @@ STATIC void can_handler(int i) {
     Can *hw = can_insts[i];
     uint32_t ir = hri_can_read_IR_reg(hw);
 
-    /* Count up errors*/
-    if (ir & CAN_IE_EWE) {
-        self->error_warning_state_count += 1;
-    }
-    if (ir & CAN_IE_EPE) {
-        self->error_passive_state_count += 1;
-    }
-    if (ir & CAN_IE_BOE) {
-        self->bus_off_state_count += 1;
-    }
-
     /* Acknowledge interrupt */
     hri_can_write_IR_reg(hw, ir);
 }
diff --git a/ports/atmel-samd/common-hal/canio/Listener.c b/ports/atmel-samd/common-hal/canio/Listener.c
index 02cfde9cc..b27c8cd1b 100644
--- a/ports/atmel-samd/common-hal/canio/Listener.c
+++ b/ports/atmel-samd/common-hal/canio/Listener.c
@@ -32,6 +32,7 @@
 
 #include "common-hal/canio/__init__.h"
 #include "common-hal/canio/Listener.h"
+#include "shared-bindings/canio/Listener.h"
 #include "shared-bindings/util.h"
 #include "supervisor/shared/tick.h"
 #include "component/can.h"
@@ -58,8 +59,8 @@ STATIC void static_assertions(void) {
     MP_STATIC_ASSERT(CAN_XIDFE_0_EFEC_STF0M_Val + 1 == CAN_XIDFE_0_EFEC_STF1M_Val);
 }
 
-STATIC bool single_address_filter(canio_match_obj_t *match) {
-    return match->mask == 0 || match->mask == match->address;
+STATIC bool single_id_filter(canio_match_obj_t *match) {
+    return match->mask == 0 || match->mask == match->id;
 }
 
 STATIC bool standard_filter_in_use(CanMramSidfe *filter) {
@@ -76,7 +77,7 @@ STATIC size_t num_filters_needed(size_t nmatch, canio_match_obj_t **matches, boo
         if (extended != matches[i]->extended) {
             continue;
         }
-        if (single_address_filter(matches[i])) {
+        if (single_id_filter(matches[i])) {
             num_half_filters_needed += 1;
         } else {
             num_half_filters_needed += 2;
@@ -191,7 +192,7 @@ STATIC void install_extended_filter(CanMramXidfe *extended, int id1, int id2, in
 }
 
 
-#define NO_ADDRESS (-1)
+#define NO_ID (-1)
 void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **matches) {
     int fifo = self->fifo_idx;
 
@@ -207,31 +208,31 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **
     CanMramSidfe *standard = next_standard_filter(self, NULL);
     CanMramXidfe *extended = next_extended_filter(self, NULL);
 
-    int first_address = NO_ADDRESS;
+    int first_id = NO_ID;
 
-    // step 1: single address standard matches
+    // step 1: single id standard matches
     // we have to gather up pairs and stuff them in a single filter entry
     for(size_t i = 0; i<nmatch; i++) {
         canio_match_obj_t *match = matches[i];
         if (match->extended) {
             continue;
         }
-        if (!single_address_filter(match)) {
+        if (!single_id_filter(match)) {
             continue;
         }
-        if (first_address != NO_ADDRESS) {
-            install_standard_filter(standard, first_address, match->address, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_DUAL_Val);
-            first_address = NO_ADDRESS;
+        if (first_id != NO_ID) {
+            install_standard_filter(standard, first_id, match->id, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_DUAL_Val);
+            first_id = NO_ID;
             standard = next_standard_filter(self, standard);
         } else {
-            first_address = match->address;
+            first_id = match->id;
         }
     }
-    // step 1.5. odd single address standard match
-    if (first_address != NO_ADDRESS) {
-            install_standard_filter(standard, first_address, first_address, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_DUAL_Val);
+    // step 1.5. odd single id standard match
+    if (first_id != NO_ID) {
+            install_standard_filter(standard, first_id, first_id, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_DUAL_Val);
             standard = next_standard_filter(self, standard);
-            first_address = NO_ADDRESS;
+            first_id = NO_ID;
     }
 
     // step 2: standard mask filter
@@ -240,36 +241,36 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **
         if (match->extended) {
             continue;
         }
-        if (single_address_filter(match)) {
+        if (single_id_filter(match)) {
             continue;
         }
-        install_standard_filter(standard, match->address, match->mask, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_CLASSIC_Val);
+        install_standard_filter(standard, match->id, match->mask, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_CLASSIC_Val);
         standard = next_standard_filter(self, standard);
     }
 
-    // step 3: single address extended matches
+    // step 3: single id extended matches
     // we have to gather up pairs and stuff them in a single filter entry
     for(size_t i = 0; i<nmatch; i++) {
         canio_match_obj_t *match = matches[i];
         if (!match->extended) {
             continue;
         }
-        if (!single_address_filter(match)) {
+        if (!single_id_filter(match)) {
             continue;
         }
-        if (first_address != NO_ADDRESS) {
-            install_extended_filter(extended, first_address, match->address, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_DUAL_Val);
-            first_address = NO_ADDRESS;
+        if (first_id != NO_ID) {
+            install_extended_filter(extended, first_id, match->id, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_DUAL_Val);
+            first_id = NO_ID;
             extended = next_extended_filter(self, extended);
         } else {
-            first_address = match->address;
+            first_id = match->id;
         }
     }
-    // step 3.5. odd single address standard match
-    if (first_address != NO_ADDRESS) {
-            install_extended_filter(extended, first_address, first_address, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_DUAL_Val);
+    // step 3.5. odd single id standard match
+    if (first_id != NO_ID) {
+            install_extended_filter(extended, first_id, first_id, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_DUAL_Val);
             extended = next_extended_filter(self, extended);
-            first_address = NO_ADDRESS;
+            first_id = NO_ID;
     }
 
     // step 4: extended mask filters
@@ -278,10 +279,10 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **
         if (!match->extended) {
             continue;
         }
-        if (single_address_filter(match)) {
+        if (single_id_filter(match)) {
             continue;
         }
-        install_extended_filter(extended, match->address, match->mask, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_CLASSIC_Val);
+        install_extended_filter(extended, match->id, match->mask, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_CLASSIC_Val);
         extended = next_extended_filter(self, extended);
     }
 
@@ -348,30 +349,32 @@ int common_hal_canio_listener_in_waiting(canio_listener_obj_t *self) {
     return self->hw->RXFS.bit.F0FL;
 }
 
-bool common_hal_canio_listener_readinto(canio_listener_obj_t *self, canio_message_obj_t *message) {
+mp_obj_t common_hal_canio_listener_receive(canio_listener_obj_t *self) {
     if (!common_hal_canio_listener_in_waiting(self)) {
         uint64_t deadline = supervisor_ticks_ms64() + self->timeout_ms;
         do {
             if (supervisor_ticks_ms64() > deadline) {
-                return false;
+                return NULL;
             }
         } while (!common_hal_canio_listener_in_waiting(self));
     }
     int index = self->hw->RXFS.bit.F0GI;
     canio_can_rx_fifo_t *hw_message = &self->fifo[index];
+    bool rtr = hw_message->rxf0.bit.RTR;
+    canio_message_obj_t *message = m_new_obj(canio_message_obj_t);
+    message->base.type = rtr ? &canio_remote_transmission_request_type : &canio_message_type;
     message->extended = hw_message->rxf0.bit.XTD;
     if (message->extended) {
         message->id = hw_message->rxf0.bit.ID;
     } else {
-        message->id = hw_message->rxf0.bit.ID >> 18; // short addresses are left-justified
+        message->id = hw_message->rxf0.bit.ID >> 18; // short ids are left-justified
     }
-    message->rtr = hw_message->rxf0.bit.RTR;
     message->size = hw_message->rxf1.bit.DLC;
-    if (!message->rtr) {
+    if (!rtr) {
         memcpy(message->data, hw_message->data, message->size);
     }
     self->hw->RXFA.bit.F0AI = index;
-    return true;
+    return message;
 }
 
 void common_hal_canio_listener_deinit(canio_listener_obj_t *self) {
diff --git a/ports/atmel-samd/common-hal/canio/Listener.h b/ports/atmel-samd/common-hal/canio/Listener.h
index 1b81d82aa..237dca870 100644
--- a/ports/atmel-samd/common-hal/canio/Listener.h
+++ b/ports/atmel-samd/common-hal/canio/Listener.h
@@ -35,7 +35,7 @@ typedef struct {
   __IO CAN_RXF0A_Type            RXFA;       /**< \brief (R/W 32) Rx FIFO n Acknowledge */
 } canio_rxfifo_reg_t;
 
-typedef struct {
+typedef struct canio_listener_obj {
     mp_obj_base_t base;
     canio_can_obj_t *can;
     canio_can_rx_fifo_t *fifo;
@@ -43,11 +43,3 @@ typedef struct {
     uint32_t timeout_ms;
     uint8_t fifo_idx;
 } canio_listener_obj_t;
-
-void common_hal_canio_listener_construct(canio_listener_obj_t *self, canio_can_obj_t *can, size_t nmatch, canio_match_obj_t **matches, float timeout);
-void common_hal_canio_listener_check_for_deinit(canio_listener_obj_t *self);
-void common_hal_canio_listener_deinit(canio_listener_obj_t *self);
-bool common_hal_canio_listener_readinto(canio_listener_obj_t *self, canio_message_obj_t *message);
-int common_hal_canio_listener_in_waiting(canio_listener_obj_t *self);
-float common_hal_canio_listener_get_timeout(canio_listener_obj_t *self);
-void common_hal_canio_listener_set_timeout(canio_listener_obj_t *self, float timeout);
diff --git a/ports/atmel-samd/reset.c b/ports/atmel-samd/reset.c
index 735639cc4..066c9897a 100644
--- a/ports/atmel-samd/reset.c
+++ b/ports/atmel-samd/reset.c
@@ -29,6 +29,8 @@
 #include "reset.h"
 #include "supervisor/filesystem.h"
 
+void NVIC_SystemReset(void) NORETURN;
+
 void reset(void) {
     filesystem_flush();
     NVIC_SystemReset();
diff --git a/ports/atmel-samd/reset.h b/ports/atmel-samd/reset.h
index b589d2611..482eb6ee8 100644
--- a/ports/atmel-samd/reset.h
+++ b/ports/atmel-samd/reset.h
@@ -29,14 +29,16 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#include "py/mpconfig.h"
+
 // Copied from inc/uf2.h in https://github.com/Microsoft/uf2-samd21
 #define DBL_TAP_MAGIC 0xf01669ef // Randomly selected, adjusted to have first and last bit set
 #define DBL_TAP_MAGIC_QUICK_BOOT 0xf02669ef
 
 extern uint32_t _bootloader_dbl_tap;
 
-void reset_to_bootloader(void);
-void reset(void);
+void reset_to_bootloader(void) NORETURN;
+void reset(void) NORETURN;
 bool bootloader_available(void);
 
 #endif  // MICROPY_INCLUDED_ATMEL_SAMD_RESET_H
diff --git a/ports/cxd56/supervisor/port.c b/ports/cxd56/supervisor/port.c
index 6164f7411..92d335cd5 100644
--- a/ports/cxd56/supervisor/port.c
+++ b/ports/cxd56/supervisor/port.c
@@ -71,6 +71,8 @@ safe_mode_t port_init(void) {
 
 void reset_cpu(void) {
     boardctl(BOARDIOC_RESET, 0);
+    for (;;) {
+    }
 }
 
 void reset_port(void) {
@@ -91,6 +93,9 @@ void reset_port(void) {
 }
 
 void reset_to_bootloader(void) {
+    boardctl(BOARDIOC_RESET, 0);
+    for (;;) {
+    }
 }
 
 supervisor_allocation* port_fixed_stack(void) {
diff --git a/ports/esp32s2/Makefile b/ports/esp32s2/Makefile
index 3488780f6..ee7d638f3 100644
--- a/ports/esp32s2/Makefile
+++ b/ports/esp32s2/Makefile
@@ -235,9 +235,17 @@ IDF_PATH = $(realpath ./esp-idf)
 $(BUILD)/esp-idf:
 	$(Q)$(MKDIR) -p $@
 
+FLASH_SDKCONFIG = esp-idf-config/sdkconfig-$(CIRCUITPY_ESP_FLASH_SIZE).defaults
+ifeq ($(DEBUG), 1)
+	DEBUG_SDKCONFIG = esp-idf-config/sdkconfig-debug.defaults
+else
+	DEBUG_SDKCONFIG = esp-idf-config/sdkconfig-opt.defaults
+endif
+SDKCONFIGS = esp-idf-config/sdkconfig.defaults;$(DEBUG_SDKCONFIG);$(FLASH_SDKCONFIG);boards/$(BOARD)/sdkconfig
+
 # create the config headers
 $(BUILD)/esp-idf/config/sdkconfig.h: boards/$(BOARD)/sdkconfig | $(BUILD)/esp-idf
-	IDF_PATH=$(IDF_PATH) cmake -S . -B $(BUILD)/esp-idf -DSDKCONFIG=$(BUILD)/esp-idf/sdkconfig -DSDKCONFIG_DEFAULTS="sdkconfig.defaults;sdkconfig-$(CIRCUITPY_ESP_FLASH_SIZE).defaults;boards/$(BOARD)/sdkconfig" -DCMAKE_TOOLCHAIN_FILE=$(IDF_PATH)/tools/cmake/toolchain-esp32s2.cmake -DIDF_TARGET=esp32s2 -GNinja
+	IDF_PATH=$(IDF_PATH) cmake -S . -B $(BUILD)/esp-idf -DSDKCONFIG=$(BUILD)/esp-idf/sdkconfig -DSDKCONFIG_DEFAULTS="$(SDKCONFIGS)" -DCMAKE_TOOLCHAIN_FILE=$(IDF_PATH)/tools/cmake/toolchain-esp32s2.cmake -DIDF_TARGET=esp32s2 -GNinja
 
 # build a lib
 # Adding -d explain -j 1 -v to the ninja line will output debug info
@@ -254,10 +262,11 @@ $(BUILD)/esp-idf/esp-idf/esp32s2/ld/esp32s2.project.ld: $(BUILD)/esp-idf/config/
 $(BUILD)/esp-idf/partition_table/partition-table.bin: $(BUILD)/esp-idf/config/sdkconfig.h
 	IDF_PATH=$(IDF_PATH) ninja -C $(BUILD)/esp-idf partition_table/partition-table.bin
 
-# run menuconfig
+# run menuconfig and then remove standard settings
 menuconfig: $(BUILD)/esp-idf/config
 	$(Q)ninja -C $(BUILD)/esp-idf menuconfig
-	$(Q)diff --old-line-format= --unchanged-line-format= sdkconfig.defaults $(BUILD)/esp-idf/sdkconfig > boards/$(BOARD)/sdkconfig || true
+	$(Q)diff --old-line-format= --unchanged-line-format= esp-idf-config/sdkconfig.defaults $(BUILD)/esp-idf/sdkconfig > $(BUILD)/sdkconfig.diff || true
+	$(Q)grep -Fvxf $(DEBUG_SDKCONFIG) -f $(FLASH_SDKCONFIG) $(BUILD)/sdkconfig.diff > boards/$(BOARD)/sdkconfig
 
 # qstr builds include headers so we need to make sure they are up to date
 $(HEADER_BUILD)/qstr.i.last: | $(BUILD)/esp-idf/config/sdkconfig.h
@@ -314,8 +323,6 @@ $(BUILD)/firmware.elf: $(OBJ) | esp-idf-stamp
 $(BUILD)/circuitpython-firmware.bin: $(BUILD)/firmware.elf
 	$(STEPECHO) "Create $@"
 	$(Q)esptool.py --chip esp32s2 elf2image $(FLASH_FLAGS) --elf-sha256-offset 0xb0 -o $@ $^
-#	$(Q)$(OBJCOPY) -O binary $^ $@
-#   $(Q)$(OBJCOPY) -O binary -j .vectors -j .text -j .data $^ $@
 
 $(BUILD)/firmware.bin: $(BUILD)/circuitpython-firmware.bin | esp-idf-stamp
 	$(Q)$(PYTHON) ../../tools/join_bins.py $@ 0x1000 $(BUILD)/esp-idf/bootloader/bootloader.bin 0x8000 $(BUILD)/esp-idf/partition_table/partition-table.bin 0x10000 $(BUILD)/circuitpython-firmware.bin
diff --git a/ports/esp32s2/boards/adafruit_metro_esp32s2/board.c b/ports/esp32s2/boards/adafruit_metro_esp32s2/board.c
new file mode 100644
index 000000000..7380be6da
--- /dev/null
+++ b/ports/esp32s2/boards/adafruit_metro_esp32s2/board.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+#include "mpconfigboard.h"
+#include "shared-bindings/microcontroller/Pin.h"
+
+void board_init(void) {
+    // USB
+    common_hal_never_reset_pin(&pin_GPIO19);
+    common_hal_never_reset_pin(&pin_GPIO20);
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+
+}
diff --git a/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.h b/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.h
new file mode 100644
index 000000000..7280aab9c
--- /dev/null
+++ b/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+//Micropython setup
+
+#define MICROPY_HW_BOARD_NAME       "Metro ESP32S2"
+#define MICROPY_HW_MCU_NAME         "ESP32S2"
+
+#define MICROPY_HW_NEOPIXEL (&pin_GPIO45)
+
+#define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
+
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
+
+#define AUTORESET_DELAY_MS 500
+
+#define DEFAULT_I2C_BUS_SCL (&pin_GPIO34)
+#define DEFAULT_I2C_BUS_SDA (&pin_GPIO33)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_GPIO36)
+#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO35)
+#define DEFAULT_SPI_BUS_MISO (&pin_GPIO37)
+
+#define DEFAULT_UART_BUS_RX (&pin_GPIO5)
+#define DEFAULT_UART_BUS_TX (&pin_GPIO6)
diff --git a/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.mk b/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.mk
new file mode 100644
index 000000000..e78098d64
--- /dev/null
+++ b/ports/esp32s2/boards/adafruit_metro_esp32s2/mpconfigboard.mk
@@ -0,0 +1,17 @@
+USB_VID = 0x239A
+USB_PID = 0x80E0
+USB_PRODUCT = "Metro ESP32S2"
+USB_MANUFACTURER = "Adafruit"
+
+INTERNAL_FLASH_FILESYSTEM = 1
+LONGINT_IMPL = MPZ
+
+# The default queue depth of 16 overflows on release builds,
+# so increase it to 32.
+CFLAGS += -DCFG_TUD_TASK_QUEUE_SZ=32
+
+CIRCUITPY_ESP_FLASH_MODE=dio
+CIRCUITPY_ESP_FLASH_FREQ=40m
+CIRCUITPY_ESP_FLASH_SIZE=4MB
+
+CIRCUITPY_MODULE=wrover
diff --git a/ports/esp32s2/boards/adafruit_metro_esp32s2/pins.c b/ports/esp32s2/boards/adafruit_metro_esp32s2/pins.c
new file mode 100644
index 000000000..08d2b2a1a
--- /dev/null
+++ b/ports/esp32s2/boards/adafruit_metro_esp32s2/pins.c
@@ -0,0 +1,44 @@
+#include "shared-bindings/board/__init__.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO17) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO18) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO1) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO2) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO3) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO4) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO5) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO5) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO6) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO6) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO7) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO8) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO9) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO10) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO11) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO12) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO13) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO14) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO15) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO16) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO21) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO42) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SDA),MP_ROM_PTR(&pin_GPIO33) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SCL),MP_ROM_PTR(&pin_GPIO34) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO45) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_DEBUG_RX), MP_ROM_PTR(&pin_GPIO38) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_DEBUG_TX), MP_ROM_PTR(&pin_GPIO37) },
+
+    { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO36) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI),MP_ROM_PTR(&pin_GPIO35) },
+    { MP_OBJ_NEW_QSTR(MP_QSTR_MISO),MP_ROM_PTR(&pin_GPIO37) },
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/esp32s2/boards/adafruit_metro_esp32s2/sdkconfig b/ports/esp32s2/boards/adafruit_metro_esp32s2/sdkconfig
new file mode 100644
index 000000000..9d8bbde96
--- /dev/null
+++ b/ports/esp32s2/boards/adafruit_metro_esp32s2/sdkconfig
@@ -0,0 +1,33 @@
+CONFIG_ESP32S2_SPIRAM_SUPPORT=y
+
+#
+# SPI RAM config
+#
+# CONFIG_SPIRAM_TYPE_AUTO is not set
+CONFIG_SPIRAM_TYPE_ESPPSRAM16=y
+# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
+CONFIG_SPIRAM_SIZE=2097152
+
+#
+# PSRAM clock and cs IO for ESP32S2
+#
+CONFIG_DEFAULT_PSRAM_CLK_IO=30
+CONFIG_DEFAULT_PSRAM_CS_IO=26
+# end of PSRAM clock and cs IO for ESP32S2
+
+# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
+# CONFIG_SPIRAM_RODATA is not set
+# CONFIG_SPIRAM_SPEED_80M is not set
+CONFIG_SPIRAM_SPEED_40M=y
+# CONFIG_SPIRAM_SPEED_26M is not set
+# CONFIG_SPIRAM_SPEED_20M is not set
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_BOOT_INIT=y
+# CONFIG_SPIRAM_IGNORE_NOTFOUND is not set
+CONFIG_SPIRAM_USE_MEMMAP=y
+# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
+# CONFIG_SPIRAM_USE_MALLOC is not set
+CONFIG_SPIRAM_MEMTEST=y
+# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
+# end of SPI RAM config
diff --git a/ports/esp32s2/boards/electroniccats_bastwifi/mpconfigboard.h b/ports/esp32s2/boards/electroniccats_bastwifi/mpconfigboard.h
index 2af3515f4..1ec61e946 100644
--- a/ports/esp32s2/boards/electroniccats_bastwifi/mpconfigboard.h
+++ b/ports/esp32s2/boards/electroniccats_bastwifi/mpconfigboard.h
@@ -31,6 +31,6 @@
 
 #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
 
-#define BOARD_USER_SAFE_MODE_ACTION "pressing boot button at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
 
 #define AUTORESET_DELAY_MS 500
diff --git a/ports/esp32s2/boards/espressif_kaluga_1/mpconfigboard.h b/ports/esp32s2/boards/espressif_kaluga_1/mpconfigboard.h
index a4c8e6576..2c0f175ab 100644
--- a/ports/esp32s2/boards/espressif_kaluga_1/mpconfigboard.h
+++ b/ports/esp32s2/boards/espressif_kaluga_1/mpconfigboard.h
@@ -33,6 +33,6 @@
 
 #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
 
-#define BOARD_USER_SAFE_MODE_ACTION "pressing boot button at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
 
 #define AUTORESET_DELAY_MS 500
diff --git a/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.h b/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.h
index 335aaeb5e..3f628c0f1 100644
--- a/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.h
+++ b/ports/esp32s2/boards/espressif_saola_1_wroom/mpconfigboard.h
@@ -33,6 +33,6 @@
 
 #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
 
-#define BOARD_USER_SAFE_MODE_ACTION "pressing boot button at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
 
 #define AUTORESET_DELAY_MS 500
diff --git a/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.h b/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.h
index d3ef8bb26..961522891 100644
--- a/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.h
+++ b/ports/esp32s2/boards/espressif_saola_1_wrover/mpconfigboard.h
@@ -33,6 +33,6 @@
 
 #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
 
-#define BOARD_USER_SAFE_MODE_ACTION "pressing boot button at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
 
 #define AUTORESET_DELAY_MS 500
diff --git a/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h b/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h
index c138c8ed1..b87b5dfa0 100644
--- a/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h
+++ b/ports/esp32s2/boards/microdev_micro_s2/mpconfigboard.h
@@ -35,6 +35,6 @@
 
 #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
 
-#define BOARD_USER_SAFE_MODE_ACTION "pressing boot button at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
 
 #define AUTORESET_DELAY_MS 500
diff --git a/ports/esp32s2/boards/microdev_micro_s2/sdkconfig b/ports/esp32s2/boards/microdev_micro_s2/sdkconfig
index b73c4a8c2..67ac6d2f3 100644
--- a/ports/esp32s2/boards/microdev_micro_s2/sdkconfig
+++ b/ports/esp32s2/boards/microdev_micro_s2/sdkconfig
@@ -16,10 +16,8 @@ CONFIG_DEFAULT_PSRAM_CLK_IO=30
 CONFIG_DEFAULT_PSRAM_CS_IO=26
 # end of PSRAM clock and cs IO for ESP32S2
 
-CONFIG_SPIRAM_SPIWP_SD3_PIN=28
 # CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
 # CONFIG_SPIRAM_RODATA is not set
-# CONFIG_SPIRAM_USE_AHB_DBUS3 is not set
 # CONFIG_SPIRAM_SPEED_80M is not set
 CONFIG_SPIRAM_SPEED_40M=y
 # CONFIG_SPIRAM_SPEED_26M is not set
@@ -33,3 +31,4 @@ CONFIG_SPIRAM_USE_MEMMAP=y
 CONFIG_SPIRAM_MEMTEST=y
 # CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
 # end of SPI RAM config
+
diff --git a/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h b/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h
index 5a165decc..6b05ac06f 100644
--- a/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h
+++ b/ports/esp32s2/boards/muselab_nanoesp32_s2/mpconfigboard.h
@@ -31,4 +31,8 @@
 
 #define MICROPY_HW_NEOPIXEL (&pin_GPIO18)
 
+#define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
+
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
+
 #define AUTORESET_DELAY_MS 500
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.h b/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.h
index a65d00206..a77de1511 100644
--- a/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.h
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.h
@@ -31,10 +31,9 @@
 
 #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
 
-#define BOARD_USER_SAFE_MODE_ACTION "pressing boot button at start up.\n"
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
 
 #define AUTORESET_DELAY_MS 500
 
-// Doesn't work with this on.
-// #define MICROPY_HW_APA102_MOSI   (&pin_GPIO44)
-// #define MICROPY_HW_APA102_SCK    (&pin_GPIO45)
+#define MICROPY_HW_APA102_MOSI   (&pin_GPIO40)
+#define MICROPY_HW_APA102_SCK    (&pin_GPIO45)
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.mk b/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.mk
index 294736d17..9857c0761 100644
--- a/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.mk
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2/mpconfigboard.mk
@@ -16,3 +16,6 @@ CIRCUITPY_ESP_FLASH_FREQ=40m
 CIRCUITPY_ESP_FLASH_SIZE=16MB
 
 CIRCUITPY_BITBANG_APA102 = 1
+
+# Include these Python libraries in firmware.
+# FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_DotStar
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2/pins.c b/ports/esp32s2/boards/unexpectedmaker_feathers2/pins.c
index e8dd2edf6..c294fb9d3 100644
--- a/ports/esp32s2/boards/unexpectedmaker_feathers2/pins.c
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2/pins.c
@@ -1,55 +1,100 @@
 #include "shared-bindings/board/__init__.h"
 
 STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_IO17), MP_ROM_PTR(&pin_GPIO17) },
     { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO17) },
     { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO17) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO18), MP_ROM_PTR(&pin_GPIO18) },
     { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO18) },
     { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO18) },
 
-    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO14) },
-    { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_GPIO14) },
+    { MP_ROM_QSTR(MP_QSTR_IO13), MP_ROM_PTR(&pin_GPIO13) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO13) },
+    { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_GPIO13) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO12), MP_ROM_PTR(&pin_GPIO12) },
     { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO12) },
     { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_GPIO12) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO6), MP_ROM_PTR(&pin_GPIO6) },
     { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO6) },
     { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_GPIO6) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO5), MP_ROM_PTR(&pin_GPIO5) },
     { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO5) },
     { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_GPIO5) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO36), MP_ROM_PTR(&pin_GPIO36) },
     { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO36) },
     { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_GPIO36) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO35), MP_ROM_PTR(&pin_GPIO35) },
     { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO35) },
     { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_GPIO35) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO37), MP_ROM_PTR(&pin_GPIO37) },
     { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO37) },
     { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_GPIO37) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO44), MP_ROM_PTR(&pin_GPIO44) },
     { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO44) },
     { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO44) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO43), MP_ROM_PTR(&pin_GPIO43) },
     { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO43) },
     { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO43) },
 
-    // Moving to 9 and 8
-    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO38) },
-    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO33) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO8) },
+    { MP_ROM_QSTR(MP_QSTR_IO8), MP_ROM_PTR(&pin_GPIO8) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO8) },
+
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO9) },
+    { MP_ROM_QSTR(MP_QSTR_IO9), MP_ROM_PTR(&pin_GPIO9) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO9) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_GPIO0) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO0) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_GPIO1) },
     { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO1) },
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_GPIO1) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_GPIO3) },
     { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO3) },
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_GPIO3) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO7), MP_ROM_PTR(&pin_GPIO7) },
     { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO7) },
-    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO8) },
-    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO9) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_GPIO7) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO33), MP_ROM_PTR(&pin_GPIO33) },
+    { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_GPIO33) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO38), MP_ROM_PTR(&pin_GPIO38) },
+    { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_GPIO38) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO10), MP_ROM_PTR(&pin_GPIO10) },
     { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO10) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_GPIO10) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO11), MP_ROM_PTR(&pin_GPIO11) },
     { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO11) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_GPIO11) },
 
-    { MP_ROM_QSTR(MP_QSTR_APA102_MOSI), MP_ROM_PTR(&pin_GPIO44) }, // MTDO
+    { MP_ROM_QSTR(MP_QSTR_APA102_MOSI), MP_ROM_PTR(&pin_GPIO40) }, // MTDO
     { MP_ROM_QSTR(MP_QSTR_APA102_SCK), MP_ROM_PTR(&pin_GPIO45) },
 
+
+    { MP_ROM_QSTR(MP_QSTR_LDO2), MP_ROM_PTR(&pin_GPIO21) },
+    { MP_ROM_QSTR(MP_QSTR_IO21), MP_ROM_PTR(&pin_GPIO21) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO13), MP_ROM_PTR(&pin_GPIO13) },
     { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO13) },
 
+    { MP_ROM_QSTR(MP_QSTR_IO4), MP_ROM_PTR(&pin_GPIO4) },
+    { MP_ROM_QSTR(MP_QSTR_AMB), MP_ROM_PTR(&pin_GPIO4) },
+
     { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
     { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
     { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2/sdkconfig b/ports/esp32s2/boards/unexpectedmaker_feathers2/sdkconfig
index b73c4a8c2..67ac6d2f3 100644
--- a/ports/esp32s2/boards/unexpectedmaker_feathers2/sdkconfig
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2/sdkconfig
@@ -16,10 +16,8 @@ CONFIG_DEFAULT_PSRAM_CLK_IO=30
 CONFIG_DEFAULT_PSRAM_CS_IO=26
 # end of PSRAM clock and cs IO for ESP32S2
 
-CONFIG_SPIRAM_SPIWP_SD3_PIN=28
 # CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
 # CONFIG_SPIRAM_RODATA is not set
-# CONFIG_SPIRAM_USE_AHB_DBUS3 is not set
 # CONFIG_SPIRAM_SPEED_80M is not set
 CONFIG_SPIRAM_SPEED_40M=y
 # CONFIG_SPIRAM_SPEED_26M is not set
@@ -33,3 +31,4 @@ CONFIG_SPIRAM_USE_MEMMAP=y
 CONFIG_SPIRAM_MEMTEST=y
 # CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
 # end of SPI RAM config
+
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/board.c b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/board.c
new file mode 100644
index 000000000..1dc30b5af
--- /dev/null
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/board.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+#include "mpconfigboard.h"
+#include "shared-bindings/microcontroller/Pin.h"
+
+void board_init(void) {
+    // USB
+    common_hal_never_reset_pin(&pin_GPIO19);
+    common_hal_never_reset_pin(&pin_GPIO20);
+
+    // Debug UART
+    common_hal_never_reset_pin(&pin_GPIO43);
+    common_hal_never_reset_pin(&pin_GPIO44);
+
+    // SPI Flash and RAM
+    common_hal_never_reset_pin(&pin_GPIO26);
+    common_hal_never_reset_pin(&pin_GPIO27);
+    common_hal_never_reset_pin(&pin_GPIO28);
+    common_hal_never_reset_pin(&pin_GPIO29);
+    common_hal_never_reset_pin(&pin_GPIO30);
+    common_hal_never_reset_pin(&pin_GPIO31);
+    common_hal_never_reset_pin(&pin_GPIO32);
+}
+
+bool board_requests_safe_mode(void) {
+    return false;
+}
+
+void reset_board(void) {
+
+}
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h
new file mode 100644
index 000000000..ee97d62c6
--- /dev/null
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+//Micropython setup
+
+#define MICROPY_HW_BOARD_NAME       "FeatherS2"
+#define MICROPY_HW_MCU_NAME         "ESP32S2"
+
+#define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0)
+#define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n")
+
+#define AUTORESET_DELAY_MS 500
+
+#define MICROPY_HW_APA102_MOSI   (&pin_GPIO40)
+#define MICROPY_HW_APA102_SCK    (&pin_GPIO45)
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.mk b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.mk
new file mode 100644
index 000000000..9857c0761
--- /dev/null
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/mpconfigboard.mk
@@ -0,0 +1,21 @@
+USB_VID = 0x239A
+USB_PID = 0x80AC
+USB_PRODUCT = "FeatherS2"
+USB_MANUFACTURER = "UnexpectedMaker"
+USB_DEVICES = "CDC,MSC,HID"
+
+INTERNAL_FLASH_FILESYSTEM = 1
+LONGINT_IMPL = MPZ
+
+# The default queue depth of 16 overflows on release builds,
+# so increase it to 32.
+CFLAGS += -DCFG_TUD_TASK_QUEUE_SZ=32
+
+CIRCUITPY_ESP_FLASH_MODE=qio
+CIRCUITPY_ESP_FLASH_FREQ=40m
+CIRCUITPY_ESP_FLASH_SIZE=16MB
+
+CIRCUITPY_BITBANG_APA102 = 1
+
+# Include these Python libraries in firmware.
+# FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_DotStar
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/pins.c b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/pins.c
new file mode 100644
index 000000000..967f5e8d9
--- /dev/null
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/pins.c
@@ -0,0 +1,102 @@
+#include "shared-bindings/board/__init__.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_IO17), MP_ROM_PTR(&pin_GPIO17) },
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO17) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO17) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO18), MP_ROM_PTR(&pin_GPIO18) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO18) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO18) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO13), MP_ROM_PTR(&pin_GPIO13) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO13) },
+    { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_GPIO13) },
+    { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO13) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO12), MP_ROM_PTR(&pin_GPIO12) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO12) },
+    { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_GPIO12) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO6), MP_ROM_PTR(&pin_GPIO6) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO6) },
+    { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_GPIO6) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO5), MP_ROM_PTR(&pin_GPIO5) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO5) },
+    { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_GPIO5) },
+
+     { MP_ROM_QSTR(MP_QSTR_IO36), MP_ROM_PTR(&pin_GPIO36) },
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO36) },
+    { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_GPIO36) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO35), MP_ROM_PTR(&pin_GPIO35) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO35) },
+    { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_GPIO35) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO37), MP_ROM_PTR(&pin_GPIO37) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO37) },
+    { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_GPIO37) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO44), MP_ROM_PTR(&pin_GPIO44) },
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO44) },
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO44) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO43), MP_ROM_PTR(&pin_GPIO43) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO43) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO43) },
+
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO38) },
+    { MP_ROM_QSTR(MP_QSTR_IO38), MP_ROM_PTR(&pin_GPIO38) },
+    { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_GPIO38) },
+
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO33) },
+    { MP_ROM_QSTR(MP_QSTR_IO33), MP_ROM_PTR(&pin_GPIO33) },
+    { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_GPIO33) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_GPIO0) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO0) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_GPIO1) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO1) },
+    { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_GPIO1) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_GPIO3) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO3) },
+    { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_GPIO3) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO7), MP_ROM_PTR(&pin_GPIO7) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO7) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_GPIO7) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO8), MP_ROM_PTR(&pin_GPIO8) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO8) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO9), MP_ROM_PTR(&pin_GPIO9) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO9) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO10), MP_ROM_PTR(&pin_GPIO10) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO10) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_GPIO10) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO11), MP_ROM_PTR(&pin_GPIO11) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO11) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_GPIO11) },
+
+    { MP_ROM_QSTR(MP_QSTR_APA102_MOSI), MP_ROM_PTR(&pin_GPIO40) }, // MTDO
+    { MP_ROM_QSTR(MP_QSTR_APA102_SCK), MP_ROM_PTR(&pin_GPIO45) },
+
+    { MP_ROM_QSTR(MP_QSTR_LDO2), MP_ROM_PTR(&pin_GPIO21) },
+    { MP_ROM_QSTR(MP_QSTR_IO21), MP_ROM_PTR(&pin_GPIO21) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO13), MP_ROM_PTR(&pin_GPIO13) },
+    { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO13) },
+
+    { MP_ROM_QSTR(MP_QSTR_IO4), MP_ROM_PTR(&pin_GPIO4) },
+    { MP_ROM_QSTR(MP_QSTR_AMB), MP_ROM_PTR(&pin_GPIO4) },
+
+    { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+    { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+    { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/sdkconfig b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/sdkconfig
new file mode 100644
index 000000000..b73c4a8c2
--- /dev/null
+++ b/ports/esp32s2/boards/unexpectedmaker_feathers2_prerelease/sdkconfig
@@ -0,0 +1,35 @@
+CONFIG_ESP32S2_SPIRAM_SUPPORT=y
+
+#
+# SPI RAM config
+#
+# CONFIG_SPIRAM_TYPE_AUTO is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
+CONFIG_SPIRAM_TYPE_ESPPSRAM64=y
+CONFIG_SPIRAM_SIZE=8388608
+
+#
+# PSRAM clock and cs IO for ESP32S2
+#
+CONFIG_DEFAULT_PSRAM_CLK_IO=30
+CONFIG_DEFAULT_PSRAM_CS_IO=26
+# end of PSRAM clock and cs IO for ESP32S2
+
+CONFIG_SPIRAM_SPIWP_SD3_PIN=28
+# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
+# CONFIG_SPIRAM_RODATA is not set
+# CONFIG_SPIRAM_USE_AHB_DBUS3 is not set
+# CONFIG_SPIRAM_SPEED_80M is not set
+CONFIG_SPIRAM_SPEED_40M=y
+# CONFIG_SPIRAM_SPEED_26M is not set
+# CONFIG_SPIRAM_SPEED_20M is not set
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_BOOT_INIT=y
+# CONFIG_SPIRAM_IGNORE_NOTFOUND is not set
+CONFIG_SPIRAM_USE_MEMMAP=y
+# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
+# CONFIG_SPIRAM_USE_MALLOC is not set
+CONFIG_SPIRAM_MEMTEST=y
+# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
+# end of SPI RAM config
diff --git a/ports/esp32s2/common-hal/digitalio/DigitalInOut.c b/ports/esp32s2/common-hal/digitalio/DigitalInOut.c
index 46c47a285..a2a0209f9 100644
--- a/ports/esp32s2/common-hal/digitalio/DigitalInOut.c
+++ b/ports/esp32s2/common-hal/digitalio/DigitalInOut.c
@@ -42,6 +42,16 @@ digitalinout_result_t common_hal_digitalio_digitalinout_construct(
     claim_pin(pin);
     self->pin = pin;
 
+    gpio_config_t config;
+    config.pin_bit_mask = 1ull << pin->number;
+    config.mode = GPIO_MODE_INPUT;
+    config.pull_up_en = GPIO_PULLUP_DISABLE;
+    config.pull_down_en = GPIO_PULLDOWN_DISABLE;
+    config.intr_type = GPIO_INTR_DISABLE;
+    if (gpio_config(&config) != ESP_OK) {
+        return DIGITALINOUT_PIN_BUSY;
+    }
+
     return DIGITALINOUT_OK;
 }
 
@@ -67,7 +77,7 @@ void common_hal_digitalio_digitalinout_switch_to_input(
 digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output(
         digitalio_digitalinout_obj_t *self, bool value,
         digitalio_drive_mode_t drive_mode) {
-    gpio_set_level(self->pin->number, value);
+    common_hal_digitalio_digitalinout_set_value(self, value);
     return common_hal_digitalio_digitalinout_set_drive_mode(self, drive_mode);
 }
 
@@ -82,12 +92,16 @@ digitalio_direction_t common_hal_digitalio_digitalinout_get_direction(
 
 void common_hal_digitalio_digitalinout_set_value(
         digitalio_digitalinout_obj_t *self, bool value) {
+    self->output_value = value;
     gpio_set_level(self->pin->number, value);
 }
 
 bool common_hal_digitalio_digitalinout_get_value(
         digitalio_digitalinout_obj_t *self) {
-    return gpio_get_level(self->pin->number) == 1;
+    if (common_hal_digitalio_digitalinout_get_direction(self) == DIRECTION_INPUT) {
+        return gpio_get_level(self->pin->number) == 1;
+    }
+    return self->output_value;
 }
 
 digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode(
diff --git a/ports/esp32s2/common-hal/digitalio/DigitalInOut.h b/ports/esp32s2/common-hal/digitalio/DigitalInOut.h
index 6877f1741..c09c5502d 100644
--- a/ports/esp32s2/common-hal/digitalio/DigitalInOut.h
+++ b/ports/esp32s2/common-hal/digitalio/DigitalInOut.h
@@ -33,6 +33,7 @@
 typedef struct {
     mp_obj_base_t base;
     const mcu_pin_obj_t *pin;
+    bool output_value;
 } digitalio_digitalinout_obj_t;
 
 #endif // MICROPY_INCLUDED_ESP32S2_COMMON_HAL_DIGITALIO_DIGITALINOUT_H
diff --git a/ports/esp32s2/common-hal/wifi/Radio.c b/ports/esp32s2/common-hal/wifi/Radio.c
index ac3e2ee4c..b62ad611b 100644
--- a/ports/esp32s2/common-hal/wifi/Radio.c
+++ b/ports/esp32s2/common-hal/wifi/Radio.c
@@ -106,6 +106,8 @@ void common_hal_wifi_radio_stop_scanning_networks(wifi_radio_obj_t *self) {
 
 wifi_radio_error_t common_hal_wifi_radio_connect(wifi_radio_obj_t *self, uint8_t* ssid, size_t ssid_len, uint8_t* password, size_t password_len, uint8_t channel, mp_float_t timeout, uint8_t* bssid, size_t bssid_len) {
     // check enabled
+    start_station(self);
+
     wifi_config_t* config = &self->sta_config;
     memcpy(&config->sta.ssid, ssid, ssid_len);
     config->sta.ssid[ssid_len] = 0;
diff --git a/ports/esp32s2/partitions-16MB.csv b/ports/esp32s2/esp-idf-config/partitions-16MB.csv
index 13ea81bea..13ea81bea 100644
--- a/ports/esp32s2/partitions-16MB.csv
+++ b/ports/esp32s2/esp-idf-config/partitions-16MB.csv
diff --git a/ports/esp32s2/partitions-4MB.csv b/ports/esp32s2/esp-idf-config/partitions-4MB.csv
index cf9b3cca8..cf9b3cca8 100644
--- a/ports/esp32s2/partitions-4MB.csv
+++ b/ports/esp32s2/esp-idf-config/partitions-4MB.csv
diff --git a/ports/esp32s2/partitions-8MB.csv b/ports/esp32s2/esp-idf-config/partitions-8MB.csv
index f4ba9b60a..f4ba9b60a 100644
--- a/ports/esp32s2/partitions-8MB.csv
+++ b/ports/esp32s2/esp-idf-config/partitions-8MB.csv
diff --git a/ports/esp32s2/sdkconfig-16MB.defaults b/ports/esp32s2/esp-idf-config/sdkconfig-16MB.defaults
index af477999b..2299feccd 100644
--- a/ports/esp32s2/sdkconfig-16MB.defaults
+++ b/ports/esp32s2/esp-idf-config/sdkconfig-16MB.defaults
@@ -1,10 +1,9 @@
-
+# No newlines in this file so they are preserved in the board sdkconfig.
 # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE_16MB=y
 CONFIG_ESPTOOLPY_FLASHSIZE="16MB"
-
-CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions-16MB.csv"
-CONFIG_PARTITION_TABLE_FILENAME="partitions-16MB.csv"
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="esp-idf-config/partitions-16MB.csv"
+CONFIG_PARTITION_TABLE_FILENAME="esp-idf-config/partitions-16MB.csv"
\ No newline at end of file
diff --git a/ports/esp32s2/sdkconfig-4MB.defaults b/ports/esp32s2/esp-idf-config/sdkconfig-4MB.defaults
index 561f971c3..4da90d1bc 100644
--- a/ports/esp32s2/sdkconfig-4MB.defaults
+++ b/ports/esp32s2/esp-idf-config/sdkconfig-4MB.defaults
@@ -1,10 +1,9 @@
-
+# No newlines in this file so they are preserved in the board sdkconfig.
 # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
-
-CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions-4MB.csv"
-CONFIG_PARTITION_TABLE_FILENAME="partitions-4MB.csv"
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="esp-idf-config/partitions-4MB.csv"
+CONFIG_PARTITION_TABLE_FILENAME="esp-idf-config/partitions-4MB.csv"
\ No newline at end of file
diff --git a/ports/esp32s2/sdkconfig-8MB.defaults b/ports/esp32s2/esp-idf-config/sdkconfig-8MB.defaults
index fcff17f46..af681c5ea 100644
--- a/ports/esp32s2/sdkconfig-8MB.defaults
+++ b/ports/esp32s2/esp-idf-config/sdkconfig-8MB.defaults
@@ -1,10 +1,9 @@
-
+# No newlines in this file so they are preserved in the board sdkconfig.
 # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE_8MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="8MB"
-
-CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions-8MB.csv"
-CONFIG_PARTITION_TABLE_FILENAME="partitions-8MB.csv"
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="esp-idf-config/partitions-8MB.csv"
+CONFIG_PARTITION_TABLE_FILENAME="esp-idf-config/partitions-8MB.csv"
\ No newline at end of file
diff --git a/ports/esp32s2/esp-idf-config/sdkconfig-debug.defaults b/ports/esp32s2/esp-idf-config/sdkconfig-debug.defaults
new file mode 100644
index 000000000..f45f6ae9f
--- /dev/null
+++ b/ports/esp32s2/esp-idf-config/sdkconfig-debug.defaults
@@ -0,0 +1,13 @@
+# No newlines in this file so they are preserved in the board sdkconfig.
+CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
+CONFIG_ESP_CONSOLE_UART_DEFAULT=y
+# CONFIG_ESP_CONSOLE_USB_CDC is not set
+# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set
+# CONFIG_ESP_CONSOLE_NONE is not set
+CONFIG_ESP_CONSOLE_UART=y
+CONFIG_ESP_CONSOLE_UART_NUM=0
+CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
+CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT=y
+# CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT is not set
+# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
+# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
\ No newline at end of file
diff --git a/ports/esp32s2/esp-idf-config/sdkconfig-opt.defaults b/ports/esp32s2/esp-idf-config/sdkconfig-opt.defaults
new file mode 100644
index 000000000..af0746bc0
--- /dev/null
+++ b/ports/esp32s2/esp-idf-config/sdkconfig-opt.defaults
@@ -0,0 +1,12 @@
+# No newlines in this file so they are preserved in the board sdkconfig.
+# CONFIG_ESP_ERR_TO_NAME_LOOKUP is not set
+# CONFIG_ESP_CONSOLE_UART_DEFAULT is not set
+# CONFIG_CONSOLE_UART_DEFAULT is not set
+CONFIG_ESP_CONSOLE_UART_NONE=y
+CONFIG_ESP_CONSOLE_NONE=y
+CONFIG_ESP_CONSOLE_UART_NUM=-1
+CONFIG_CONSOLE_UART_NUM=-1
+# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
+CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT=y
+# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
+CONFIG_ESP32S2_PANIC_SILENT_REBOOT=y
\ No newline at end of file
diff --git a/ports/esp32s2/sdkconfig.defaults b/ports/esp32s2/esp-idf-config/sdkconfig.defaults
index 4094367e0..4094367e0 100644
--- a/ports/esp32s2/sdkconfig.defaults
+++ b/ports/esp32s2/esp-idf-config/sdkconfig.defaults
diff --git a/ports/esp32s2/supervisor/port.c b/ports/esp32s2/supervisor/port.c
index d2630617b..4290b9bb4 100644
--- a/ports/esp32s2/supervisor/port.c
+++ b/ports/esp32s2/supervisor/port.c
@@ -56,6 +56,8 @@ uint32_t heap_size;
 
 STATIC esp_timer_handle_t _tick_timer;
 
+extern void esp_restart(void) NORETURN;
+
 void tick_timer_cb(void* arg) {
     supervisor_tick();
 }
@@ -118,9 +120,11 @@ void reset_port(void) {
 }
 
 void reset_to_bootloader(void) {
+    esp_restart();
 }
 
 void reset_cpu(void) {
+    esp_restart();
 }
 
 uint32_t *port_heap_get_bottom(void) {
diff --git a/ports/litex/supervisor/port.c b/ports/litex/supervisor/port.c
index 3125072e6..e55eb49f0 100644
--- a/ports/litex/supervisor/port.c
+++ b/ports/litex/supervisor/port.c
@@ -85,9 +85,17 @@ void reset_port(void) {
 
 void reset_to_bootloader(void) {
     reboot_ctrl_write(0xac);
+    for(;;) {}
 }
 
 void reset_cpu(void) {
+    // "You can reset Fomu by writing a special value to the CSR_REBOOT_CTRL
+    // register at 0xe0006000L. All writes to this register must start with
+    // 0xac, to ensure random values aren’t written. We can reboot Fomu by
+    // simply writing this value" --
+    //     https://workshop.fomu.im/en/latest/riscv.html
+    reboot_ctrl_write(0xac);
+    for(;;) {}
 }
 
 supervisor_allocation* port_fixed_stack(void) {
diff --git a/ports/mimxrt10xx/reset.h b/ports/mimxrt10xx/reset.h
index dc3106cf0..ea56df02a 100644
--- a/ports/mimxrt10xx/reset.h
+++ b/ports/mimxrt10xx/reset.h
@@ -30,12 +30,14 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#include "py/mpconfig.h"
+
 // Copied from inc/uf2.h in https://github.com/Microsoft/uf2-samd21
 #define DBL_TAP_MAGIC 0xf01669ef // Randomly selected, adjusted to have first and last bit set
 #define DBL_TAP_MAGIC_QUICK_BOOT 0xf02669ef
 
-void reset_to_bootloader(void);
-void reset(void);
+void reset_to_bootloader(void) NORETURN;
+void reset(void) NORETURN;
 bool bootloader_available(void);
 
 #endif  // MICROPY_INCLUDED_MIMXRT10XX_RESET_H
diff --git a/ports/nrf/boards/clue_nrf52840_express/board.c b/ports/nrf/boards/clue_nrf52840_express/board.c
index 45452a35e..523bd7677 100644
--- a/ports/nrf/boards/clue_nrf52840_express/board.c
+++ b/ports/nrf/boards/clue_nrf52840_express/board.c
@@ -91,7 +91,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // not SH1107
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/nrf/boards/hiibot_bluefi/board.c b/ports/nrf/boards/hiibot_bluefi/board.c
index 6b53cab13..93e31aef0 100644
--- a/ports/nrf/boards/hiibot_bluefi/board.c
+++ b/ports/nrf/boards/hiibot_bluefi/board.c
@@ -92,7 +92,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/board.c b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/board.c
index e7f946f4d..e08d00dac 100644
--- a/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/board.c
+++ b/ports/nrf/boards/makerdiary_nrf52840_m2_devkit/board.c
@@ -92,7 +92,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/nrf/boards/ohs2020_badge/board.c b/ports/nrf/boards/ohs2020_badge/board.c
index 9fcf9d2bf..ec52690ce 100644
--- a/ports/nrf/boards/ohs2020_badge/board.c
+++ b/ports/nrf/boards/ohs2020_badge/board.c
@@ -91,7 +91,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        false); // backlight_on_high
+        false, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/nrf/supervisor/port.c b/ports/nrf/supervisor/port.c
index 2945f244d..bc8b47be7 100644
--- a/ports/nrf/supervisor/port.c
+++ b/ports/nrf/supervisor/port.c
@@ -234,6 +234,8 @@ void reset_cpu(void) {
     uint32_t ticks = nrfx_rtc_counter_get(&rtc_instance);
     overflow_tracker.overflowed_ticks += ticks / 32;
     NVIC_SystemReset();
+    for (;;) {
+    }
 }
 
 // The uninitialized data section is placed directly after BSS, under the theory
diff --git a/ports/stm/boards/meowbit_v121/board.c b/ports/stm/boards/meowbit_v121/board.c
index b74f13516..f67b4a49d 100644
--- a/ports/stm/boards/meowbit_v121/board.c
+++ b/ports/stm/boards/meowbit_v121/board.c
@@ -111,7 +111,8 @@ void board_init(void) {
         false, // data_as_commands
         true, // auto_refresh
         60, // native_frames_per_second
-        true); // backlight_on_high
+        true, // backlight_on_high
+        false); // SH1107_addressing
 }
 
 bool board_requests_safe_mode(void) {
diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c
index e21105001..bb304a317 100644
--- a/ports/stm/supervisor/port.c
+++ b/ports/stm/supervisor/port.c
@@ -56,6 +56,8 @@
 
 #include STM32_HAL_H
 
+void NVIC_SystemReset(void) NORETURN;
+
 #if (CPY_STM32H7) || (CPY_STM32F7)
 
 // Device memories must be accessed in order.
@@ -247,7 +249,7 @@ void reset_port(void) {
 }
 
 void reset_to_bootloader(void) {
-
+    NVIC_SystemReset();
 }
 
 void reset_cpu(void) {