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-rw-r--r--ports/mimxrt10xx/boards/board.h8
-rw-r--r--ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c187
-rw-r--r--ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c187
-rw-r--r--ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c187
-rw-r--r--ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c188
-rw-r--r--ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c191
-rw-r--r--ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c189
-rw-r--r--ports/mimxrt10xx/boards/metro_m7_1011/board.c52
-rw-r--r--ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c179
-rw-r--r--ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.h20
-rw-r--r--ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.mk12
-rw-r--r--ports/mimxrt10xx/boards/metro_m7_1011/pins.c59
-rw-r--r--ports/mimxrt10xx/boards/teensy40/flash_config.c201
-rw-r--r--ports/mimxrt10xx/boards/teensy41/flash_config.c191
14 files changed, 1278 insertions, 573 deletions
diff --git a/ports/mimxrt10xx/boards/board.h b/ports/mimxrt10xx/boards/board.h
index 92d02d900..678c223ae 100644
--- a/ports/mimxrt10xx/boards/board.h
+++ b/ports/mimxrt10xx/boards/board.h
@@ -33,6 +33,7 @@
#include "py/mpconfig.h"
#include "fsl_common.h"
+#include "fsl_flexspi_nor_config.h"
// Initializes board related state once on start up.
void board_init(void);
@@ -45,4 +46,11 @@ bool board_requests_safe_mode(void);
// Reset the state of off MCU components such as neopixels.
void reset_board(void);
+#define SEQUENCE(first, second, third, fourth) first, second, third, fourth
+#define TWO_EMPTY_STEPS 0x00000000
+#define EMPTY_SEQUENCE SEQUENCE(TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS)
+
+// FlexSPI configuration that stores command info.
+extern const flexspi_nor_config_t qspiflash_config;
+
#endif // MICROPY_INCLUDED_MIMXRT10XX_BOARDS_BOARD_H
diff --git a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c
index b74c0b151..282464c75 100644
--- a/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c
+++ b/ports/mimxrt10xx/boards/feather_m7_1011/flash_config.c
@@ -6,7 +6,7 @@
*/
#include "fsl_flexspi_nor_boot.h"
-#include "fsl_flexspi_nor_config.h"
+#include "boards/board.h"
__attribute__((section(".boot_hdr.ivt")))
@@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = {
0xFFFFFFFF /* empty - extra data word */
};
+// Config for W25Q32JV with QSPI routed.
__attribute__((section(".boot_hdr.conf")))
-// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
- .csHoldTime = 1u,
- .csSetupTime = 2u,
- // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x02, // Bit pattern for setting Quad Enable.
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
+ .serialClkFreq = kFlexSpiSerialClk_133MHz,
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
- // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
- // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- 0,
- 0,
-
- 0x24040405,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000406,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x08180420,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x081804D8,
- 0,
- 0,
- 0,
-
- 0x08180402,
- 0x00002004,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000460,
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ // READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x02),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ EMPTY_SEQUENCE,
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status -2
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x01 /* number of bytes to write */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
},
},
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
- .blockSize = 0x00010000,
- .isUniformBlockSize = false,
};
diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c
index b74c0b151..51cc0f164 100644
--- a/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c
+++ b/ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c
@@ -6,7 +6,7 @@
*/
#include "fsl_flexspi_nor_boot.h"
-#include "fsl_flexspi_nor_config.h"
+#include "boards/board.h"
__attribute__((section(".boot_hdr.ivt")))
@@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = {
0xFFFFFFFF /* empty - extra data word */
};
+// Config for W25Q64JV with QSPI routed.
__attribute__((section(".boot_hdr.conf")))
-// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
- .csHoldTime = 1u,
- .csSetupTime = 2u,
- // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x02,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
+ .serialClkFreq = kFlexSpiSerialClk_133MHz,
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
- // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
- // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- 0,
- 0,
-
- 0x24040405,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000406,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x08180420,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x081804D8,
- 0,
- 0,
- 0,
-
- 0x08180402,
- 0x00002004,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000460,
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ // READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ EMPTY_SEQUENCE,
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
},
},
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
- .blockSize = 0x00010000,
- .isUniformBlockSize = false,
};
diff --git a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c
index b74c0b151..51cc0f164 100644
--- a/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c
+++ b/ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c
@@ -6,7 +6,7 @@
*/
#include "fsl_flexspi_nor_boot.h"
-#include "fsl_flexspi_nor_config.h"
+#include "boards/board.h"
__attribute__((section(".boot_hdr.ivt")))
@@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = {
0xFFFFFFFF /* empty - extra data word */
};
+// Config for W25Q64JV with QSPI routed.
__attribute__((section(".boot_hdr.conf")))
-// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
- .csHoldTime = 1u,
- .csSetupTime = 2u,
- // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x02,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
+ .serialClkFreq = kFlexSpiSerialClk_133MHz,
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
- // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
- // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- 0,
- 0,
-
- 0x24040405,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000406,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x08180420,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x081804D8,
- 0,
- 0,
- 0,
-
- 0x08180402,
- 0x00002004,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000460,
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ // READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ EMPTY_SEQUENCE,
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
},
},
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
- .blockSize = 0x00010000,
- .isUniformBlockSize = false,
};
diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c
index 7e8fb75b2..19573bd99 100644
--- a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c
+++ b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c
@@ -6,7 +6,8 @@
*/
#include "fsl_flexspi_nor_boot.h"
-#include "fsl_flexspi_nor_config.h"
+#include "boards/board.h"
+
__attribute__((section(".boot_hdr.ivt")))
/*************************************
@@ -34,88 +35,135 @@ const BOOT_DATA_T boot_data = {
0xFFFFFFFF /* empty - extra data word */
};
+// Config for AT25SF128A with QSPI routed.
__attribute__((section(".boot_hdr.conf")))
-// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
- .csHoldTime = 1u,
- .csSetupTime = 2u,
- // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x02,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
+ .serialClkFreq = kFlexSpiSerialClk_60MHz,
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
- // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
- // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- 0,
- 0,
-
- 0x24040405,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000406,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x08180420,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x081804D8,
- 0,
- 0,
- 0,
-
- 0x08180402,
- 0x00002004,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000460,
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ // READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x02),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ EMPTY_SEQUENCE,
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
},
},
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
- .blockSize = 0x00010000,
- .isUniformBlockSize = false,
};
diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c
index 43ffe0dd1..40b566618 100644
--- a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c
+++ b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c
@@ -6,7 +6,7 @@
*/
#include "fsl_flexspi_nor_boot.h"
-#include "fsl_flexspi_nor_config.h"
+#include "boards/board.h"
__attribute__((section(".boot_hdr.ivt")))
@@ -35,92 +35,135 @@ const BOOT_DATA_T boot_data = {
0xFFFFFFFF /* empty - extra data word */
};
+// Config for IS25LP064A with QSPI routed.
__attribute__((section(".boot_hdr.conf")))
-// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
-#ifdef BOARD_USING_SECONDARY_QSPI_PINMUX
- .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromInternally,
-#else
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
-#endif
- .csHoldTime = 1u,
- .csSetupTime = 2u,
- // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x40,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
+ .serialClkFreq = kFlexSpiSerialClk_30MHz,
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
- // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
- // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- 0,
- 0,
-
- 0x24040405,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000406,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x08180420,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x081804D8,
- 0,
- 0,
- 0,
-
- 0x08180402,
- 0x00002004,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000460,
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ // RADDR_SDR, FLEXSPI_4PAD, 24 bits to transmit ),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ // READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ EMPTY_SEQUENCE,
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
},
},
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
- .blockSize = 0x00010000,
- .isUniformBlockSize = false,
};
diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c
index 7e046d494..d79a8d0f9 100644
--- a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c
+++ b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c
@@ -6,10 +6,10 @@
*/
#include "fsl_flexspi_nor_boot.h"
-#include "fsl_flexspi_nor_config.h"
+#include "boards/board.h"
-__attribute__((section(".boot_hdr.ivt")))
+__attribute__((section(".boot_hdr.ivt")))
/*************************************
* IVT Data
*************************************/
@@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = {
0xFFFFFFFF /* empty - extra data word */
};
+// Config for IS25WP064A with QSPI routed.
__attribute__((section(".boot_hdr.conf")))
-// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
- .csHoldTime = 1u,
- .csSetupTime = 2u,
- // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x40,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
+ .serialClkFreq = kFlexSpiSerialClk_60MHz,
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
- // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
- // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- 0,
- 0,
-
- 0x24040405,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000406,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x08180420,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x081804D8,
- 0,
- 0,
- 0,
-
- 0x08180402,
- 0x00002004,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000460,
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ // READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x02),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ EMPTY_SEQUENCE,
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
},
},
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
- .blockSize = 0x00010000,
- .isUniformBlockSize = false,
};
diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board.c b/ports/mimxrt10xx/boards/metro_m7_1011/board.c
new file mode 100644
index 000000000..ed543e1b0
--- /dev/null
+++ b/ports/mimxrt10xx/boards/metro_m7_1011/board.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
+ * Copyright (c) 2019 Artur Pacholec
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "boards/board.h"
+#include "mpconfigboard.h"
+#include "shared-bindings/microcontroller/Pin.h"
+
+void board_init(void) {
+ // SWD Pins
+ common_hal_never_reset_pin(&pin_GPIO_AD_13);//SWDIO
+ common_hal_never_reset_pin(&pin_GPIO_AD_12);//SWCLK
+
+ // FLEX flash
+ common_hal_never_reset_pin(&pin_GPIO_SD_12);
+ common_hal_never_reset_pin(&pin_GPIO_SD_11);
+ common_hal_never_reset_pin(&pin_GPIO_SD_10);
+ common_hal_never_reset_pin(&pin_GPIO_SD_09);
+ common_hal_never_reset_pin(&pin_GPIO_SD_08);
+ common_hal_never_reset_pin(&pin_GPIO_SD_07);
+ common_hal_never_reset_pin(&pin_GPIO_SD_06);
+}
+
+bool board_requests_safe_mode(void) {
+ return false;
+}
+
+void reset_board(void) {
+}
diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c
new file mode 100644
index 000000000..30ce67523
--- /dev/null
+++ b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexspi_nor_boot.h"
+#include "boards/board.h"
+
+
+__attribute__((section(".boot_hdr.ivt")))
+/*************************************
+ * IVT Data
+ *************************************/
+const ivt image_vector_table = {
+ IVT_HEADER, /* IVT Header */
+ IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
+ IVT_RSVD, /* Reserved = 0 */
+ (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
+ (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
+ (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
+ (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
+ IVT_RSVD /* Reserved = 0 */
+};
+
+__attribute__((section(".boot_hdr.boot_data")))
+/*************************************
+ * Boot Data
+ *************************************/
+const BOOT_DATA_T boot_data = {
+ FLASH_BASE, /* boot start location */
+ FLASH_SIZE, /* size */
+ PLUGIN_FLAG, /* Plugin flag*/
+ 0xFFFFFFFF /* empty - extra data word */
+};
+
+// Config for W25Q16JV with QSPI routed.
+__attribute__((section(".boot_hdr.conf")))
+const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
+ .memConfig =
+ {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x0200,
+ .configCmdEnable = 1u,
+ .configModeType[0] = kDeviceConfigCmdType_Generic,
+ .configCmdSeqs[0] = {
+ .seqId = 2u,
+ .seqNum = 1u,
+ },
+ .deviceType = kFlexSpiDeviceType_SerialNOR,
+ .sflashPadType = kSerialFlash_4Pads,
+ .serialClkFreq = kFlexSpiSerialClk_60MHz,
+ .sflashA1Size = FLASH_SIZE,
+ .lookupTable =
+ {
+ // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ // READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x02),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */,
+ DUMMY_SDR, FLEXSPI_1PAD, 8),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x02),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
+ },
+ },
+};
diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.h b/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.h
new file mode 100644
index 000000000..b11edb18b
--- /dev/null
+++ b/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.h
@@ -0,0 +1,20 @@
+#define MICROPY_HW_BOARD_NAME "Metro MIMXRT1011"
+#define MICROPY_HW_MCU_NAME "IMXRT1011DAE5A"
+
+#define MICROPY_HW_NEOPIXEL (&pin_GPIO_00)
+
+// If you change this, then make sure to update the linker scripts as well to
+// make sure you don't overwrite code
+#define CIRCUITPY_INTERNAL_NVM_SIZE 0
+
+#define BOARD_FLASH_SIZE (2 * 1024 * 1024)
+
+#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_02)
+#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_01)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_AD_06)
+#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_AD_04)
+#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_AD_03)
+
+#define DEFAULT_UART_BUS_RX (&pin_GPIO_09)
+#define DEFAULT_UART_BUS_TX (&pin_GPIO_10)
diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.mk b/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.mk
new file mode 100644
index 000000000..1a3f7e766
--- /dev/null
+++ b/ports/mimxrt10xx/boards/metro_m7_1011/mpconfigboard.mk
@@ -0,0 +1,12 @@
+USB_VID = 0x239A
+USB_PID = 0x80E2
+USB_PRODUCT = "Metro M7 1011"
+USB_MANUFACTURER = "Adafruit"
+
+CHIP_VARIANT = MIMXRT1011DAE5A
+CHIP_FAMILY = MIMXRT1011
+FLASH = W25Q16JV
+
+# Include these Python libraries in the firmware
+FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_ESP32SPI
+FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Requests
diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/pins.c b/ports/mimxrt10xx/boards/metro_m7_1011/pins.c
new file mode 100644
index 000000000..e88493413
--- /dev/null
+++ b/ports/mimxrt10xx/boards/metro_m7_1011/pins.c
@@ -0,0 +1,59 @@
+#include "shared-bindings/board/__init__.h"
+
+#include "boards/board.h"
+
+STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
+ // Analog
+ { MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_02) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_01) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_00) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_05) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_10) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_08) },
+
+ // Digital
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_09) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_10) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_13) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_12) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_SD_00) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_SD_01) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_SD_02) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_11) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_08) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_07) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_06) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_05) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_04) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_D13),MP_ROM_PTR(&pin_GPIO_03) },
+
+ // ESP control
+ { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_CS), MP_ROM_PTR(&pin_GPIO_AD_14) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_GPIO0), MP_ROM_PTR(&pin_GPIO_SD_05) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_BUSY), MP_ROM_PTR(&pin_GPIO_AD_11) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RESET), MP_ROM_PTR(&pin_GPIO_AD_07) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_TX), MP_ROM_PTR(&pin_GPIO_09) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_ESP_RX), MP_ROM_PTR(&pin_GPIO_10) },
+
+ // SPI
+ { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO_AD_06) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO_AD_03) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO_AD_04) },
+
+ // UART
+ { MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) },
+
+ // I2C
+ { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_01) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_02) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO_00) },
+
+ { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
+ { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
+ { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
diff --git a/ports/mimxrt10xx/boards/teensy40/flash_config.c b/ports/mimxrt10xx/boards/teensy40/flash_config.c
index 426deb884..30ce67523 100644
--- a/ports/mimxrt10xx/boards/teensy40/flash_config.c
+++ b/ports/mimxrt10xx/boards/teensy40/flash_config.c
@@ -6,12 +6,8 @@
*/
#include "fsl_flexspi_nor_boot.h"
-#include "fsl_flexspi_nor_config.h"
+#include "boards/board.h"
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_device"
-#endif
__attribute__((section(".boot_hdr.ivt")))
/*************************************
@@ -39,88 +35,145 @@ const BOOT_DATA_T boot_data = {
0xFFFFFFFF /* empty - extra data word */
};
+// Config for W25Q16JV with QSPI routed.
__attribute__((section(".boot_hdr.conf")))
-// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
- .csHoldTime = 1u,
- .csSetupTime = 2u,
- // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x0200,
+ .configCmdEnable = 1u,
+ .configModeType[0] = kDeviceConfigCmdType_Generic,
+ .configCmdSeqs[0] = {
+ .seqId = 2u,
+ .seqNum = 1u,
+ },
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
+ .serialClkFreq = kFlexSpiSerialClk_60MHz,
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
- // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
- // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- 0,
- 0,
-
- 0x24040405,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000406,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x08180420,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x081804D8,
- 0,
- 0,
- 0,
-
- 0x08180402,
- 0x00002004,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000460,
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ // READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x02),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */,
+ DUMMY_SDR, FLEXSPI_1PAD, 8),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x02),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
},
},
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
- .blockSize = 0x00010000,
- .isUniformBlockSize = false,
};
diff --git a/ports/mimxrt10xx/boards/teensy41/flash_config.c b/ports/mimxrt10xx/boards/teensy41/flash_config.c
index 426deb884..7b2bfb768 100644
--- a/ports/mimxrt10xx/boards/teensy41/flash_config.c
+++ b/ports/mimxrt10xx/boards/teensy41/flash_config.c
@@ -6,12 +6,8 @@
*/
#include "fsl_flexspi_nor_boot.h"
-#include "fsl_flexspi_nor_config.h"
+#include "boards/board.h"
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_device"
-#endif
__attribute__((section(".boot_hdr.ivt")))
/*************************************
@@ -39,88 +35,135 @@ const BOOT_DATA_T boot_data = {
0xFFFFFFFF /* empty - extra data word */
};
+// Config for W25Q64JV with QSPI routed.
__attribute__((section(".boot_hdr.conf")))
-// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
+ .blockSize = 0x00010000,
+ .isUniformBlockSize = false,
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
- .csHoldTime = 1u,
- .csSetupTime = 2u,
- // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+
+ .busyOffset = 0u, // Status bit 0 indicates busy.
+ .busyBitPolarity = 0u, // Busy when the bit is 1.
+
+ .deviceModeCfgEnable = 1u,
+ .deviceModeType = kDeviceConfigCmdType_QuadEnable,
+ .deviceModeSeq = {
+ .seqId = 4u,
+ .seqNum = 1u,
+ },
+ .deviceModeArg = 0x02,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
+ .serialClkFreq = kFlexSpiSerialClk_60MHz,
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
- // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
- // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- 0,
- 0,
-
- 0x24040405,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000406,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x08180420,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x081804D8,
- 0,
- 0,
- 0,
-
- 0x08180402,
- 0x00002004,
- 0,
- 0,
-
- 0,
- 0,
- 0,
- 0,
-
- 0x00000460,
+ // The high 16 bits is command 1 and the low are command 0.
+ // Within a command, the top 6 bits are the opcode, the next two are the number
+ // of pads and then last byte is the operand. The operand's meaning changes
+ // per opcode.
+
+ // Indices with ROM should always have the same function because the ROM
+ // bootloader uses it.
+
+ // 0: ROM: Read LUTs
+ // Quad version
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */,
+ RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */,
+ READ_SDR, FLEXSPI_4PAD, 0x04),
+ // Single fast read version, good for debugging.
+ // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */,
+ // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */,
+ // READ_SDR, FLEXSPI_1PAD, 0x04),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 1: ROM: Read status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */,
+ READ_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 2: Empty
+ EMPTY_SEQUENCE,
+
+ // 3: ROM: Write Enable
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0x00),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 4: Config: Write Status
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */,
+ WRITE_SDR, FLEXSPI_1PAD, 0x01),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 5: ROM: Erase Sector
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 6: Empty
+ EMPTY_SEQUENCE,
+
+ // 7: Empty
+ EMPTY_SEQUENCE,
+
+ // 8: Block Erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 9: ROM: Page program
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */,
+ RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */),
+
+ FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 10: Empty
+ EMPTY_SEQUENCE,
+
+ // 11: ROM: Chip erase
+ SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */,
+ STOP, FLEXSPI_1PAD, 0),
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS,
+ TWO_EMPTY_STEPS),
+
+ // 12: Empty
+ EMPTY_SEQUENCE,
+
+ // 13: ROM: Read SFDP
+ EMPTY_SEQUENCE,
+
+ // 14: ROM: Restore no cmd
+ EMPTY_SEQUENCE,
+
+ // 15: ROM: Dummy
+ EMPTY_SEQUENCE
},
},
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
- .blockSize = 0x00010000,
- .isUniformBlockSize = false,
};
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-08 11:29:55 +0000